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feat(uart): apply default LP uart clock source
1 parent 4c6d92c commit 291358d

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+4
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cores/esp32/esp32-hal-uart.c

+4-3
Original file line numberDiff line numberDiff line change
@@ -1158,13 +1158,14 @@ bool uartSetClockSource(uart_t *uart, uart_sclk_t clkSrc) {
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if (uart->num >= SOC_UART_HP_NUM) {
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switch (clkSrc) {
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case UART_SCLK_XTAL:
1161-
uart->_uart_clock_source = SOC_MOD_CLK_XTAL_D2;
1161+
uart->_uart_clock_source = LP_UART_SCLK_XTAL_D2;
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break;
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case UART_SCLK_RTC:
1164-
uart->_uart_clock_source = SOC_MOD_CLK_RTC_FAST;
1164+
uart->_uart_clock_source = LP_UART_SCLK_LP_FAST;
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break;
1166+
case UART_SCLK_DEFAULT:
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default:
1167-
uart->_uart_clock_source = -1;
1168+
uart->_uart_clock_source = LP_UART_SCLK_DEFAULT;
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}
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} else
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#endif

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