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1 commit comments
kbickham commentedon Aug 22, 2019
Curious, someone already mentioned in #3095 ,
while(uart->dev->status.rxfifo_cnt != 0 || (uart->dev->mem_rx_status.wr_addr != uart->dev->mem_rx_status.rd_addr)) { READ_PERI_REG(UART_FIFO_REG(uart->num));
is this clearing the input buffer as well? I believe this may be effecting something I'm working on. May the force be with you.