From e0664105c8540f28a84eb04dd2e0c95002769fec Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sun, 14 Jul 2019 11:29:40 -0700 Subject: [PATCH] Added memory fence to xt_rsil(). Without this the compiler may use memory refernces loaded to registers before the fence, in computation within the fence. These values could have changed before xt_rsil() (critical section start) was called. --- cores/esp8266/Arduino.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/esp8266/Arduino.h b/cores/esp8266/Arduino.h index 5ab2b84762..d962923de8 100644 --- a/cores/esp8266/Arduino.h +++ b/cores/esp8266/Arduino.h @@ -159,7 +159,7 @@ void ets_intr_unlock(); // level 15 will disable ALL interrupts, // level 0 will enable ALL interrupts, // -#define xt_rsil(level) (__extension__({uint32_t state; __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state)); state;})) +#define xt_rsil(level) (__extension__({uint32_t state; __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state) :: "memory"); state;})) #define xt_wsr_ps(state) __asm__ __volatile__("wsr %0,ps; isync" :: "a" (state) : "memory") #define interrupts() xt_rsil(0)