From ae055f9cb3ab8684a3e71266c569c5984168e084 Mon Sep 17 00:00:00 2001 From: John Doe Date: Mon, 1 Jun 2015 03:27:21 +0300 Subject: [PATCH 1/4] add RTC registers --- docs/rgisters_dump.txt | 18 +++++++++--------- .../esp8266/cores/esp8266/esp8266_peri.h | 11 +++++++++++ 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/docs/rgisters_dump.txt b/docs/rgisters_dump.txt index 957a9e1305..8143dba63a 100644 --- a/docs/rgisters_dump.txt +++ b/docs/rgisters_dump.txt @@ -547,21 +547,21 @@ | 10987654321098765432109876543210 | | | | ===========|==================================|============|============|======| 0x60000700 | 00000000000110011100000001101010 | 0x0019C06A | 1687658 | Àj | -0x60000704 | 00000000001111100011111111111111 | 0x003E3FFF | 4079615 | >?ÿ | +0x60000704 | 00000000001111100011111111111111 | 0x003E3FFF | 4079615 | >?ÿ | RTCSV 0x60000708 | 00000000001000000000000000000000 | 0x00200000 | 2097152 | | 0x6000070C | 00000000000000011110000000101000 | 0x0001E028 | 122920 | à( | 0x60000710 | 11111110000000000000000000000000 | 0xFE000000 | 4261412864 | þ | 0x60000714 | 00000000000000000000000000000010 | 0x00000002 | 2 | | 0x60000718 | 00000000000000000000100000001000 | 0x00000808 | 2056 | | -0x6000071C | 00000000010100001010011111000011 | 0x0050A7C3 | 5285827 | P§Ã | -0x60000720 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x60000724 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x60000728 | 00000000000000000000000000000101 | 0x00000005 | 5 | | +0x6000071C | 00000000010100001010011111000011 | 0x0050A7C3 | 5285827 | P§Ã | RTCCV +0x60000720 | 00000000000000000000000000000000 | 0x00000000 | 0 | | RTCIS +0x60000724 | 00000000000000000000000000000000 | 0x00000000 | 0 | | RTCIC +0x60000728 | 00000000000000000000000000000101 | 0x00000005 | 5 | | RTCIE 0x6000072C | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x60000730 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x60000734 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x60000738 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x6000073C | 00000000000000000000000000000000 | 0x00000000 | 0 | | +0x60000730 | 00000000000000000000000000000000 | 0x00000000 | 0 | | RTCS0 +0x60000734 | 00000000000000000000000000000000 | 0x00000000 | 0 | | RTCS1 +0x60000738 | 00000000000000000000000000000000 | 0x00000000 | 0 | | RTCS2 +0x6000073C | 00000000000000000000000000000000 | 0x00000000 | 0 | | RTCS3 0x60000740 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x60000744 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x60000748 | 00100000001100000010000000100000 | 0x20302020 | 540024864 | 0 | diff --git a/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h b/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h index e2998cf540..f6be56756d 100644 --- a/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h +++ b/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h @@ -148,6 +148,17 @@ extern uint8_t esp8266_gpioToFn[16]; #define TCPD 2 //Prescale Devider (2bit) 0:1(12.5ns/tick), 1:16(0.2us/tick), 2/3:256(3.2us/tick) #define TCIT 0 //Interrupt Type 0:edge, 1:level +//RTC Registers +#define RTCMEM(i) ESP8266_REG(0x1100 + (((i) & 0xFF) * 4)) //RTC RAM 768 bytes, 192 registers +#define RTCSV ESP8266_REG(0x704) //RTC SLEEP COUNTER Target Value +#define RTCCV ESP8266_REG(0x71C) //RTC SLEEP COUNTER Value +#define RTCIS ESP8266_REG(0x720) //RTC INT Status +#define RTCIC ESP8266_REG(0x724) //RTC INT Clear +#define RTCIE ESP8266_REG(0x728) //RTC INT Enable +#define RTCS0 ESP8266_REG(0x730) //RTC SCRATCH 0 +#define RTCS1 ESP8266_REG(0x734) //RTC SCRATCH 1 +#define RTCS2 ESP8266_REG(0x738) //RTC SCRATCH 2 +#define RTCS3 ESP8266_REG(0x73C) //RTC SCRATCH 3 //UART SWAP Register #define USWAP ESP8266_DREG(0x28) From a6e8697ae15cfcb2f4767412c94645a57b183229 Mon Sep 17 00:00:00 2001 From: John Doe Date: Tue, 2 Jun 2015 00:11:20 +0300 Subject: [PATCH 2/4] register and clock changes --- docs/rgisters_dump.txt | 17 ++-- .../esp8266/cores/esp8266/HardwareSerial.cpp | 6 +- .../cores/esp8266/core_esp8266_wiring_pwm.c | 2 +- .../esp8266/cores/esp8266/esp8266_peri.h | 79 ++++++++++++------- .../esp8266com/esp8266/libraries/SPI/SPI.cpp | 6 +- .../esp8266com/esp8266/libraries/SPI/SPI.h | 2 - .../esp8266/tools/sdk/include/ets_sys.h | 4 +- 7 files changed, 67 insertions(+), 49 deletions(-) diff --git a/docs/rgisters_dump.txt b/docs/rgisters_dump.txt index 8143dba63a..0039ac8b93 100644 --- a/docs/rgisters_dump.txt +++ b/docs/rgisters_dump.txt @@ -5,14 +5,14 @@ 0x3FF00000 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF00004 | 00000000000000000000000000000101 | 0x00000005 | 5 | | TEIE 0x3FF00008 | 00000000000000000000100000001111 | 0x0000080F | 2063 | . | -0x3FF0000C | 00000100000000000000000100000010 | 0x04000102 | 67109122 | | +0x3FF0000C | 00000100000000000000000100000010 | 0x04000102 | 67109122 | | SPIRDY 0x3FF00010 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x3FF00014 | 00000000000000000000000000000000 | 0x00000000 | 0 | | +0x3FF00014 | 00000000000000000000000000000000 | 0x00000000 | 0 | | CPU2X 0x3FF00018 | 11111111111111110000000011111111 | 0xFFFF00FF | 4294902015 | .. . | 0x3FF0001C | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF00020 | 00000000000000000000000000010000 | 0x00000010 | 16 | . | SPIIR 0x3FF00024 | 00000000000000000000000000011010 | 0x0000001A | 26 | . | -0x3FF00028 | 00000000000000000000000000000000 | 0x00000000 | 0 | | USWAP +0x3FF00028 | 00000000000000000000000000000000 | 0x00000000 | 0 | | IOSWAP 0x3FF0002C | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF00030 | 00000000000000000100000001000000 | 0x00004040 | 16448 | @@ | 0x3FF00034 | 00000000000000000000000000000000 | 0x00000000 | 0 | | @@ -22,9 +22,9 @@ 0x3FF00044 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF00048 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF0004C | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x3FF00050 | 10011101111011100000000000000000 | 0x9DEE0000 | 2649620480 | .. | -0x3FF00054 | 00000010000000001001110011000010 | 0x02009CC2 | 33594562 | .. | -0x3FF00058 | 00000000000000001010000000000000 | 0x0000A000 | 40960 | . | +0x3FF00050 | 10011101111011100000000000000000 | 0x9DEE0000 | 2649620480 | .. | MAC0 +0x3FF00054 | 00000010000000001001110011000010 | 0x02009CC2 | 33594562 | .. | MAC1 +0x3FF00058 | 00000000000000001010000000000000 | 0x0000A000 | 40960 | . | CHIPID 0x3FF0005C | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF00060 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x3FF00064 | 00000000000000000000000000000000 | 0x00000000 | 0 | | @@ -687,14 +687,13 @@ 0x60000908 | 00000000000000000000000000001011 | 0x0000000B | 11 | | 0x6000090C | 00000000000000111001000001110010 | 0x00039072 | 233586 | r | 0x60000910 | 00000000000000000000000000000000 | 0x00000000 | 0 | | -0x60000914 | 00000000000000000000000000000000 | 0x00000000 | 0 | | WDTRST +0x60000914 | 00000000000000000000000000000000 | 0x00000000 | 0 | | WDTFEED 0x60000918 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x6000091C | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x60000920 | 00000000000000000000000000111001 | 0x00000039 | 57 | 9 | 0x60000924 | 00000000000000000000000000001011 | 0x0000000B | 11 | | 0x60000928 | 00000000000000000000000000001011 | 0x0000000B | 11 | | -0x6000092C | 00000111100111110000110111101010 | 0x079F0DEA | 127864298 |Ÿ -ê| +0x6000092C | 00000111100111110000110111101010 | 0x079F0DEA | 127864298 | Ÿê | 0x60000930 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x60000934 | 00000000000000000000000000000000 | 0x00000000 | 0 | | 0x60000938 | 00000000000000000000000000000000 | 0x00000000 | 0 | | diff --git a/hardware/esp8266com/esp8266/cores/esp8266/HardwareSerial.cpp b/hardware/esp8266com/esp8266/cores/esp8266/HardwareSerial.cpp index ac56919ca7..970b16c50a 100644 --- a/hardware/esp8266com/esp8266/cores/esp8266/HardwareSerial.cpp +++ b/hardware/esp8266com/esp8266/cores/esp8266/HardwareSerial.cpp @@ -262,7 +262,7 @@ void uart_set_baudrate(uart_t* uart, int baud_rate) { if(uart == 0) return; uart->baud_rate = baud_rate; - USD(uart->uart_nr) = (80000000UL / uart->baud_rate); + USD(uart->uart_nr) = (ESP8266_CLOCK / uart->baud_rate); } int uart_get_baudrate(uart_t* uart) { @@ -359,7 +359,7 @@ void uart_swap(uart_t* uart) { if(uart->txPin == 1 && uart->rxPin == 3) { pinMode(15, FUNCTION_4); //TX pinMode(13, FUNCTION_4); //RX - USWAP |= (1 << USWAP0); + IOSWAP |= (1 << IOSWAPU0); pinMode(1, INPUT); //TX pinMode(3, INPUT); //RX uart->rxPin = 13; @@ -367,7 +367,7 @@ void uart_swap(uart_t* uart) { } else { pinMode(1, SPECIAL); //TX pinMode(3, SPECIAL); //RX - USWAP &= ~(1 << USWAP0); + IOSWAP &= ~(1 << IOSWAPU0); pinMode(15, INPUT); //TX pinMode(13, INPUT); //RX uart->rxPin = 3; diff --git a/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c b/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c index c74f76bc3f..7a70f5d276 100644 --- a/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c +++ b/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c @@ -83,7 +83,7 @@ void prep_pwm_steps(){ pwm_steps_len = pwm_temp_steps_len; ets_memcpy(pwm_steps, pwm_temp_steps, (pwm_temp_steps_len + 1) * 2); ets_memcpy(pwm_steps_mask, pwm_temp_masks, pwm_temp_steps_len * 4); - pwm_multiplier = F_CPU/(PWMRANGE * pwm_freq); + pwm_multiplier = ESP8266_CLOCK/(PWMRANGE * pwm_freq); ETS_FRC1_INTR_ENABLE(); } diff --git a/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h b/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h index f6be56756d..d7723c3ad4 100644 --- a/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h +++ b/hardware/esp8266com/esp8266/cores/esp8266/esp8266_peri.h @@ -25,6 +25,15 @@ #define ESP8266_REG(addr) *((volatile uint32_t *)(0x60000000+(addr))) #define ESP8266_DREG(addr) *((volatile uint32_t *)(0x3FF00000+(addr))) +#define ESP8266_CLOCK 80000000UL + +//CPU Register +#define CPU2X ESP8266_DREG(0x14) //when bit 0 is set, F_CPU = 160MHz + +//OTP Registers +#define MAC0 ESP8266_DREG(0x50) +#define MAC1 ESP8266_DREG(0x54) +#define CHIPID ESP8266_DREG(0x58) //GPIO (0-15) Control Registers #define GPO ESP8266_REG(0x300) //GPIO_OUT R/W (Output Level) @@ -149,20 +158,26 @@ extern uint8_t esp8266_gpioToFn[16]; #define TCIT 0 //Interrupt Type 0:edge, 1:level //RTC Registers -#define RTCMEM(i) ESP8266_REG(0x1100 + (((i) & 0xFF) * 4)) //RTC RAM 768 bytes, 192 registers #define RTCSV ESP8266_REG(0x704) //RTC SLEEP COUNTER Target Value #define RTCCV ESP8266_REG(0x71C) //RTC SLEEP COUNTER Value #define RTCIS ESP8266_REG(0x720) //RTC INT Status #define RTCIC ESP8266_REG(0x724) //RTC INT Clear #define RTCIE ESP8266_REG(0x728) //RTC INT Enable -#define RTCS0 ESP8266_REG(0x730) //RTC SCRATCH 0 -#define RTCS1 ESP8266_REG(0x734) //RTC SCRATCH 1 -#define RTCS2 ESP8266_REG(0x738) //RTC SCRATCH 2 -#define RTCS3 ESP8266_REG(0x73C) //RTC SCRATCH 3 -//UART SWAP Register -#define USWAP ESP8266_DREG(0x28) -#define USWAP0 2 //BIT 2 swaps UART 0 +//IO SWAP Register +#define IOSWAP ESP8266_DREG(0x28) +#define IOSWAPU 0 //Swaps UART +#define IOSWAPS 1 //Swaps SPI +#define IOSWAPU0 2 //Swaps UART 0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts) +#define IOSWAPU1 3 //Swaps UART 1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts) +#define IOSWAPHS 5 //Sets HSPI with higher prio +#define IOSWAP2HS 6 //Sets Two SPI Masters on HSPI +#define IOSWAP2CS 7 //Sets Two SPI Masters on CSPI + +//UART INT Status +#define UIS ESP8266_DREG(0x20020) +#define UIS0 0 +#define UIS1 2 //UART 0 Registers #define U0F ESP8266_REG(0x000) //UART FIFO @@ -227,9 +242,9 @@ extern uint8_t esp8266_gpioToFn[16]; #define UIFF 0 //RX FIFO Full //UART STATUS Registers Bits -#define USTX 31 //TX PIN Level -#define USRTS 30 //RTS PIN Level -#define USDTR 39 //DTR PIN Level +#define USTX 31 //TX PIN Level +#define USRTS 30 //RTS PIN Level +#define USDTR 39 //DTR PIN Level #define USTXC 16 //TX FIFO COUNT (8bit) #define USRXD 15 //RX PIN Level #define USCTS 14 //CTS PIN Level @@ -237,35 +252,39 @@ extern uint8_t esp8266_gpioToFn[16]; #define USRXC 0 //RX FIFO COUNT (8bit) //UART CONF0 Registers Bits -#define UCDTRI 24 //Invert DTR -#define UCRTSI 23 //Invert RTS -#define UCTXI 22 //Invert TX -#define UCDSRI 21 //Invert DSR -#define UCCTSI 20 //Invert CTS -#define UCRXI 19 //Invert RX +#define UCDTRI 24 //Invert DTR +#define UCRTSI 23 //Invert RTS +#define UCTXI 22 //Invert TX +#define UCDSRI 21 //Invert DSR +#define UCCTSI 20 //Invert CTS +#define UCRXI 19 //Invert RX #define UCTXRST 18 //Reset TX FIFO #define UCRXRST 17 //Reset RX FIFO #define UCTXHFE 15 //TX Harware Flow Enable -#define UCLBE 14 //LoopBack Enable -#define UCBRK 8 //Send Break on the TX line +#define UCLBE 14 //LoopBack Enable +#define UCBRK 8 //Send Break on the TX line #define UCSWDTR 7 //Set this bit to assert DTR #define UCSWRTS 6 //Set this bit to assert RTS -#define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit -#define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit -#define UCPAE 1 //Parity Enable -#define UCPA 0 //Parity 0:even, 1:odd +#define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit +#define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit +#define UCPAE 1 //Parity Enable +#define UCPA 0 //Parity 0:even, 1:odd //UART CONF1 Registers Bits -#define UCTOE 31 //RX TimeOut Enable -#define UCTOT 24 //RX TimeOut Treshold (7bit) +#define UCTOE 31 //RX TimeOut Enable +#define UCTOT 24 //RX TimeOut Treshold (7bit) #define UCRXHFE 23 //RX Harware Flow Enable #define UCRXHFT 16 //RX Harware Flow Treshold (7bit) -#define UCFET 8 //TX FIFO Empty Treshold (7bit) -#define UCFFT 0 //RX FIFO Full Treshold (7bit) +#define UCFET 8 //TX FIFO Empty Treshold (7bit) +#define UCFFT 0 //RX FIFO Full Treshold (7bit) + +//WDT Feed (the dog) Register +#define WDTFEED ESP8266_REG(0x914) +#define WDT_FEED() (WDTFEED = 0x73) -//WDT Register used for UART -#define WDTRST ESP8266_REG(0x914) -#define WDT_RESET() (WDTRST = 0x73) +//SPI_READY +#define SPIRDY ESP8266_DREG(0x0C) +#define SPIBUSY 9 //wait SPI idle //SPI0 Registers (SPI0 is used for the flash) #define SPI0CMD ESP8266_REG(0x200) diff --git a/hardware/esp8266com/esp8266/libraries/SPI/SPI.cpp b/hardware/esp8266com/esp8266/libraries/SPI/SPI.cpp index 7d52528ef1..4e73021220 100644 --- a/hardware/esp8266com/esp8266/libraries/SPI/SPI.cpp +++ b/hardware/esp8266com/esp8266/libraries/SPI/SPI.cpp @@ -121,14 +121,14 @@ void SPIClass::setBitOrder(uint8_t bitOrder) { * @return */ static uint32_t ClkRegToFreq(spiClk_t * reg) { - return (SPI_MAX_SPEED / ((reg->regPre + 1) * (reg->regN + 1))); + return (ESP8266_CLOCK / ((reg->regPre + 1) * (reg->regN + 1))); } void SPIClass::setFrequency(uint32_t freq) { static uint32_t lastSetFrequency = 0; static uint32_t lastSetRegister = 0; - if(freq >= SPI_MAX_SPEED) { + if(freq >= ESP8266_CLOCK) { setClockDivider(0x80000000); return; } @@ -164,7 +164,7 @@ void SPIClass::setFrequency(uint32_t freq) { reg.regN = calN; while(calPreVari++ <= 1) { // test different variants for Pre (we calculate in int so we miss the decimals, testing is the easyest and fastest way) - calPre = (((SPI_MAX_SPEED / (reg.regN + 1)) / freq) - 1) + calPreVari; + calPre = (((ESP8266_CLOCK / (reg.regN + 1)) / freq) - 1) + calPreVari; if(calPre > 0x1FFF) { reg.regPre = 0x1FFF; // 8191 } else if(calPre <= 0) { diff --git a/hardware/esp8266com/esp8266/libraries/SPI/SPI.h b/hardware/esp8266com/esp8266/libraries/SPI/SPI.h index 68d2a3dc6c..e67b5b0d58 100644 --- a/hardware/esp8266com/esp8266/libraries/SPI/SPI.h +++ b/hardware/esp8266com/esp8266/libraries/SPI/SPI.h @@ -45,8 +45,6 @@ #define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz #endif -#define SPI_MAX_SPEED (80000000L) - const uint8_t SPI_MODE0 = 0x00; ///< CPOL: 0 CPHA: 0 const uint8_t SPI_MODE1 = 0x01; ///< CPOL: 0 CPHA: 1 const uint8_t SPI_MODE2 = 0x10; ///< CPOL: 1 CPHA: 0 diff --git a/hardware/esp8266com/esp8266/tools/sdk/include/ets_sys.h b/hardware/esp8266com/esp8266/tools/sdk/include/ets_sys.h index ad1a4c7be6..8b118b3416 100644 --- a/hardware/esp8266com/esp8266/tools/sdk/include/ets_sys.h +++ b/hardware/esp8266com/esp8266/tools/sdk/include/ets_sys.h @@ -39,11 +39,13 @@ typedef struct _ETSTIMER_ { typedef void (*int_handler_t)(void*); -#define ETS_SPI_INUM 2 +#define ETS_SPI_INUM 2 #define ETS_GPIO_INUM 4 #define ETS_UART_INUM 5 #define ETS_UART1_INUM 5 #define ETS_CCOMPARE0_INUM 6 +#define ETS_SOFT_INUM 7 +#define ETS_WDT_INUM 8 #define ETS_FRC_TIMER1_INUM 9 /* use edge*/ #define ETS_INTR_LOCK() \ From 2f157b80e63e66c123cb08f6d167076d6315d561 Mon Sep 17 00:00:00 2001 From: John Doe Date: Tue, 2 Jun 2015 01:11:08 +0300 Subject: [PATCH 3/4] add PWM Range control setting freq to 50, range to 20000 and writing between 700 and 2200 gives servo control for example --- hardware/esp8266com/esp8266/cores/esp8266/Arduino.h | 1 + .../esp8266/cores/esp8266/core_esp8266_wiring_pwm.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/hardware/esp8266com/esp8266/cores/esp8266/Arduino.h b/hardware/esp8266com/esp8266/cores/esp8266/Arduino.h index 3f67fdaead..138aea96b5 100644 --- a/hardware/esp8266com/esp8266/cores/esp8266/Arduino.h +++ b/hardware/esp8266com/esp8266/cores/esp8266/Arduino.h @@ -188,6 +188,7 @@ int analogRead(uint8_t); void analogReference(uint8_t mode); void analogWrite(uint8_t, int); void analogWriteFreq(uint32_t freq); +void analogWriteRange(uint32_t range); unsigned long millis(void); unsigned long micros(void); diff --git a/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c b/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c index 7a70f5d276..d102f93d65 100644 --- a/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c +++ b/hardware/esp8266com/esp8266/cores/esp8266/core_esp8266_wiring_pwm.c @@ -27,6 +27,7 @@ uint32_t pwm_mask = 0; uint16_t pwm_values[17] = {0,}; uint32_t pwm_freq = 1000; +uint32_t pwm_range = PWMRANGE; uint32_t pwm_multiplier = 0; uint16_t pwm_steps[17]; @@ -71,7 +72,7 @@ void prep_pwm_steps(){ for(i=0; i<17; i++){ if((pwm_mask & (1 << i)) != 0 && pwm_values[i] != 0) pwm_temp_steps[pwm_temp_steps_len++] = pwm_values[i]; } - pwm_temp_steps[pwm_temp_steps_len++] = PWMRANGE; + pwm_temp_steps[pwm_temp_steps_len++] = pwm_range; pwm_temp_steps_len = pwm_sort_array(pwm_temp_steps, pwm_temp_steps_len) - 1; for(i=0; i Date: Tue, 2 Jun 2015 01:13:15 +0300 Subject: [PATCH 4/4] spi clock does not depend on cpu clock --- hardware/esp8266com/esp8266/libraries/SPI/SPI.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/hardware/esp8266com/esp8266/libraries/SPI/SPI.h b/hardware/esp8266com/esp8266/libraries/SPI/SPI.h index e67b5b0d58..141f30ef4b 100644 --- a/hardware/esp8266com/esp8266/libraries/SPI/SPI.h +++ b/hardware/esp8266com/esp8266/libraries/SPI/SPI.h @@ -28,7 +28,6 @@ // This defines are not representing the real Divider of the ESP8266 // the Defines match to an AVR Arduino on 16MHz for better compatibility -#if F_CPU == 80000000L #define SPI_CLOCK_DIV2 0x00101001 //8 MHz #define SPI_CLOCK_DIV4 0x00241001 //4 MHz #define SPI_CLOCK_DIV8 0x004c1001 //2 MHz @@ -36,14 +35,6 @@ #define SPI_CLOCK_DIV32 0x013c1001 //500 KHz #define SPI_CLOCK_DIV64 0x027c1001 //250 KHz #define SPI_CLOCK_DIV128 0x04fc1001 //125 KHz -#else -#define SPI_CLOCK_DIV2 0x00241001 //8 MHz -#define SPI_CLOCK_DIV4 0x004c1001 //4 MHz -#define SPI_CLOCK_DIV8 0x009c1001 //2 MHz -#define SPI_CLOCK_DIV16 0x013c1001 //1 MHz -#define SPI_CLOCK_DIV32 0x027c1001 //500 KHz -#define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz -#endif const uint8_t SPI_MODE0 = 0x00; ///< CPOL: 0 CPHA: 0 const uint8_t SPI_MODE1 = 0x01; ///< CPOL: 0 CPHA: 1