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Merge branch 'ficeto-esp8266' into esp8266
* ficeto-esp8266: (31 commits) leftovers Update to the latest SPIFFS git and cleanup add Exception Causes (EXCCAUSE) docu fix possible null ptr in EEPROM.cpp Align the start of functions to the next power-of-two greater than 4, skipping up to 3 bytes. improve os_printf handling when buffer full. - wait for free buffer in hw fifo force all os_malloc calls to request a aligned size. - this fix Fatal exception (9) by unaligned class memory add some __attribute__ for compiler to get better optimizations and warning handle fix possible problems in EEPROM regarding interrupt handling and SPI flash blocking spiffs fixes improve includes add ssid and ip to debug out add examples/WiFiMulti/WiFiMulti.ino add support for list of AP connections - auto select ssid with best signal - for debugging enable DEBUG_WIFI_MULTI macro and call Serial.setDebugOutput(true); fix start address so erase works disable all interrupts when reading from spiffs printf to print instead of write fix uart triggering reset when spi has been read/written ESP8266WiFiClass::waitForConnectResult() add Print::printf fix data types ...
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‎docs/exception_causes.md

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
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Exception Causes (EXCCAUSE)
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===========================================
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4+
| EXC-CAUSE Code | Cause Name | Cause Description | Required Option | EXC-VADDR Loaded |
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|:--------------:|:---------------------------|:------------------------------------------------------------------------------------------------------------|:-------------------------|:----------------:|
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| 0 | IllegalInstructionCause | Illegal instruction | Exception | No |
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| 1 | SyscallCause | SYSCALL instruction | Exception | No |
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| 2 | InstructionFetchErrorCause | Processor internal physical address or data error during instruction fetch | Exception | Yes |
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| 3 | LoadStoreErrorCause | Processor internal physical address or data error during load or store | Exception | Yes |
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| 4 | Level1InterruptCause | Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register | Interrupt | No |
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| 5 | AllocaCause | MOVSP instruction, if caller’s registers are not in the register file | Windowed Register | No |
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| 6 | IntegerDivideByZeroCause | QUOS, QUOU, REMS, or REMU divisor operand is zero | 32-bit Integer Divide | No |
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| 7 | Reserved for Tensilica | | | |
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| 8 | PrivilegedCause | Attempt to execute a privileged operation when CRING ? 0 | MMU | No |
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| 9 | LoadStoreAlignmentCause | Load or store to an unaligned address | Unaligned Exception | Yes |
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| 10..11 | Reserved for Tensilica | | | |
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| 12 | InstrPIFDataErrorCause | PIF data error during instruction fetch | Processor Interface | Yes |
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| 13 | LoadStorePIFDataErrorCause | Synchronous PIF data error during LoadStore access | Processor Interface | Yes |
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| 14 | InstrPIFAddrErrorCause | PIF address error during instruction fetch | Processor Interface | Yes |
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| 15 | LoadStorePIFAddrErrorCause | Synchronous PIF address error during LoadStore access | Processor Interface | Yes |
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| 16 | InstTLBMissCause | Error during Instruction TLB refill | MMU | Yes |
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| 17 | InstTLBMultiHitCause | Multiple instruction TLB entries matched | MMU | Yes |
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| 18 | InstFetchPrivilegeCause | An instruction fetch referenced a virtual address at a ring level less than CRING | MMU | Yes |
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| 19 | Reserved for Tensilica | | | |
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| 20 | InstFetchProhibitedCause | An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch | Region Protection or MMU | Yes |
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| 21..23 | Reserved for Tensilica | | | |
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| 24 | LoadStoreTLBMissCause | Error during TLB refill for a load or store | MMU | Yes |
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| 25 | LoadStoreTLBMultiHitCause | Multiple TLB entries matched for a load or store | MMU | Yes |
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| 26 | LoadStorePrivilegeCause | A load or store referenced a virtual address at a ring level less than CRING | MMU | Yes |
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| 27 | Reserved for Tensilica | | | |
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| 28 | LoadProhibitedCause | A load referenced a page mapped with an attribute that does not permit loads | Region Protection or MMU | Yes |
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| 29 | StoreProhibitedCause | A store referenced a page mapped with an attribute that does not permit stores | Region Protection or MMU | Yes |
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| 30..31 | Reserved for Tensilica | | | |
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| 32..39 | CoprocessornDisabled | Coprocessor n instruction when cpn disabled. n varies 0..7 as the cause varies 32..39 | Coprocessor | No |
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| 40..63 | Reserved | | | |
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Infos from Xtensa Instruction Set Architecture (ISA) Reference Manual

‎hardware/esp8266com/esp8266/boards.txt

+41-30
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,6 @@ menu.UploadSpeed=Upload Speed
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menu.CpuFrequency=CPU Frequency
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menu.FlashSize=Flash Size
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menu.FlashFreq=Flash Frequency
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menu.FlashMode=Flash Mode
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##############################################################
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generic.name=Generic ESP8266 Module
@@ -24,6 +23,8 @@ generic.build.flash_mode=qio
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generic.build.flash_size=512K
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generic.build.flash_freq=40
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generic.build.flash_ld=eagle.flash.512k.ld
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generic.build.spiffs_start=0x6B000
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generic.build.spiffs_end=0x7B000
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generic.menu.CpuFrequency.80=80 MHz
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generic.menu.CpuFrequency.80.build.f_cpu=80000000L
@@ -49,39 +50,46 @@ generic.menu.UploadSpeed.512000.upload.speed=512000
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generic.menu.UploadSpeed.921600=921600
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generic.menu.UploadSpeed.921600.upload.speed=921600
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generic.menu.FlashSize.512K=512K
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generic.menu.FlashSize.512K=512K (64K SPIFFS)
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generic.menu.FlashSize.512K.build.flash_size=512K
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generic.menu.FlashSize.512K.build.flash_ld=eagle.flash.512k.ld
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generic.menu.FlashSize.256K=256K
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generic.menu.FlashSize.256K.build.flash_size=256K
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generic.menu.FlashSize.256K.build.flash_ld=eagle.flash.256k.ld
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generic.menu.FlashSize.1M=1M
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generic.menu.FlashSize.1M.build.flash_size=1M
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generic.menu.FlashSize.1M.build.flash_ld=eagle.flash.1m.ld
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generic.menu.FlashSize.2M=2M
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generic.menu.FlashSize.512K.build.spiffs_start=0x6B000
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generic.menu.FlashSize.512K.build.spiffs_end=0x7B000
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generic.menu.FlashSize.1M512=1M (512K SPIFFS)
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generic.menu.FlashSize.1M512.build.flash_size=1M
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generic.menu.FlashSize.1M512.build.flash_ld=eagle.flash.1m512.ld
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generic.menu.FlashSize.1M512.build.spiffs_start=0x6B000
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generic.menu.FlashSize.1M512.build.spiffs_end=0xFB000
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generic.menu.FlashSize.1M256=1M (256K SPIFFS)
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generic.menu.FlashSize.1M256.build.flash_size=1M
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generic.menu.FlashSize.1M256.build.flash_ld=eagle.flash.1m256.ld
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generic.menu.FlashSize.1M256.build.spiffs_start=0xAB000
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generic.menu.FlashSize.1M256.build.spiffs_end=0xFB000
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generic.menu.FlashSize.1M128=1M (128K SPIFFS)
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generic.menu.FlashSize.1M128.build.flash_size=1M
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generic.menu.FlashSize.1M128.build.flash_ld=eagle.flash.1m128.ld
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generic.menu.FlashSize.1M128.build.spiffs_start=0xCB000
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generic.menu.FlashSize.1M128.build.spiffs_end=0xFB000
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generic.menu.FlashSize.1M64=1M (64K SPIFFS)
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generic.menu.FlashSize.1M64.build.flash_size=1M
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generic.menu.FlashSize.1M64.build.flash_ld=eagle.flash.1m64.ld
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generic.menu.FlashSize.1M64.build.spiffs_start=0xEB000
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generic.menu.FlashSize.1M64.build.spiffs_end=0xFB000
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generic.menu.FlashSize.2M=2M (1M SPIFFS)
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generic.menu.FlashSize.2M.build.flash_size=2M
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generic.menu.FlashSize.2M.build.flash_ld=eagle.flash.2m.ld
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generic.menu.FlashSize.4M=4M
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generic.menu.FlashSize.2M.build.spiffs_start=0x100000
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generic.menu.FlashSize.2M.build.spiffs_end=0x1FB000
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generic.menu.FlashSize.4M=4M (3M SPIFFS)
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generic.menu.FlashSize.4M.build.flash_size=4M
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generic.menu.FlashSize.4M.build.flash_ld=eagle.flash.4m.ld
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generic.menu.FlashSize.4M.build.spiffs_start=0x100000
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generic.menu.FlashSize.4M.build.spiffs_end=0x3FB000
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generic.menu.FlashFreq.40=40MHz
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generic.menu.FlashFreq.40.build.flash_freq=40
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generic.menu.FlashFreq.20=20MHz
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generic.menu.FlashFreq.20.build.flash_freq=20
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generic.menu.FlashFreq.26=26.7MHz
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generic.menu.FlashFreq.26.build.flash_freq=26.7
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generic.menu.FlashFreq.80=80MHz
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generic.menu.FlashFreq.80.build.flash_freq=80
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generic.menu.FlashMode.qio=QIO
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generic.menu.FlashMode.qio.build.flash_mode=qio
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generic.menu.FlashMode.qout=QOUT
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generic.menu.FlashMode.qout.build.flash_mode=qout
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generic.menu.FlashMode.dio=DIO
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generic.menu.FlashMode.dio.build.flash_mode=dio
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generic.menu.FlashMode.dout=DOUT
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generic.menu.FlashMode.dout.build.flash_mode=dout
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# generic.menu.FlashFreq.40=40MHz
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# generic.menu.FlashFreq.40.build.flash_freq=40
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# generic.menu.FlashFreq.80=80MHz
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# generic.menu.FlashFreq.80.build.flash_freq=80
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##############################################################
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modwifi.name=Olimex MOD-WIFI-ESP8266(-DEV)
@@ -104,6 +112,8 @@ modwifi.build.flash_mode=qio
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modwifi.build.flash_size=2M
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modwifi.build.flash_freq=40
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modwifi.build.flash_ld=eagle.flash.2m.ld
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modwifi.build.spiffs_start=0x100000
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modwifi.build.spiffs_end=0x1FB000
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modwifi.menu.CpuFrequency.80=80 MHz
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modwifi.menu.CpuFrequency.80.build.f_cpu=80000000L
@@ -150,6 +160,8 @@ nodemcu.build.flash_mode=qio
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nodemcu.build.flash_size=4M
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nodemcu.build.flash_freq=40
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nodemcu.build.flash_ld=eagle.flash.4m.ld
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nodemcu.build.spiffs_start=0x100000
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nodemcu.build.spiffs_end=0x3FB000
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nodemcu.menu.CpuFrequency.80=80 MHz
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nodemcu.menu.CpuFrequency.80.build.f_cpu=80000000L
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nodemcu.menu.UploadSpeed.921600=921600
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nodemcu.menu.UploadSpeed.921600.upload.speed=921600
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nodemcu.menu.FlashSize.4M=4M
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nodemcu.menu.FlashSize.4M.build.flash_size=4M
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##############################################################
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# wifio.name=Wifio
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#
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# wifio.build.flash_size=512K
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# wifio.build.flash_freq=40
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# wifio.build.flash_ld=eagle.flash.512k.ld
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# wifio.build.spiffs_start=0x6B000
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# wifio.build.spiffs_end=0x7B000
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#
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# wifio.menu.CpuFrequency.80=80MHz
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# wifio.menu.CpuFrequency.80.build.f_cpu=80000000L

‎hardware/esp8266com/esp8266/cores/esp8266/Arduino.h

+1-1
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@@ -135,7 +135,7 @@ void ets_intr_unlock();
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extern uint32_t interruptsState;
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137137
#define interrupts() xt_enable_interrupts(interruptsState)
138-
#define noInterrupts() xt_disable_interrupts(interruptsState, 15)
138+
#define noInterrupts() __asm__ __volatile__("rsil %0,15; esync; isync; dsync" : "=a" (interruptsState))
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140140
#define clockCyclesPerMicrosecond() ( F_CPU / 1000000L )
141141
#define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )

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