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| 18 | InstFetchPrivilegeCause | An instruction fetch referenced a virtual address at a ring level less than CRING | MMU | Yes |
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| 19 | Reserved for Tensilica ||||
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| 20 | InstFetchProhibitedCause | An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch | Region Protection or MMU | Yes |
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| 21..23 | Reserved for Tensilica ||||
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| 24 | LoadStoreTLBMissCause | Error during TLB refill for a load or store | MMU | Yes |
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| 25 | LoadStoreTLBMultiHitCause | Multiple TLB entries matched for a load or store | MMU | Yes |
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| 26 | LoadStorePrivilegeCause | A load or store referenced a virtual address at a ring level less than CRING | MMU | Yes |
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| 27 | Reserved for Tensilica ||||
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| 28 | LoadProhibitedCause | A load referenced a page mapped with an attribute that does not permit loads | Region Protection or MMU | Yes |
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| 29 | StoreProhibitedCause | A store referenced a page mapped with an attribute that does not permit stores | Region Protection or MMU | Yes |
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| 30..31 | Reserved for Tensilica ||||
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| 32..39 | CoprocessornDisabled | Coprocessor n instruction when cpn disabled. n varies 0..7 as the cause varies 32..39 | Coprocessor | No |
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| 40..63 | Reserved ||||
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Infos from Xtensa Instruction Set Architecture (ISA) Reference Manual
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