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| 1 | +/* |
| 2 | + ESP8266-specific implementation of the UART download mode |
| 3 | + Copyright (c) 2021 Timo Wischer <[email protected]> |
| 4 | + All rights reserved. |
| 5 | + This file is part of the esp8266 core for Arduino environment. |
| 6 | +
|
| 7 | + This library is free software; you can redistribute it and/or |
| 8 | + modify it under the terms of the GNU Lesser General Public |
| 9 | + License as published by the Free Software Foundation; either |
| 10 | + version 2.1 of the License, or (at your option) any later version. |
| 11 | +
|
| 12 | + This library is distributed in the hope that it will be useful, |
| 13 | + but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | + Lesser General Public License for more details. |
| 16 | +
|
| 17 | + You should have received a copy of the GNU Lesser General Public |
| 18 | + License along with this library; if not, write to the Free Software |
| 19 | + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | +
|
| 21 | + This implementation is based on the original implementation of the ROM. |
| 22 | + It was shortend to reduce the memory usage. The complete version and the |
| 23 | + development history can be found in: |
| 24 | + https://github.com/twischer/Arduino/tree/reboot_uart_download_full |
| 25 | + This might be usefull in case of issues. |
| 26 | + */ |
| 27 | +#include "reboot_uart_dwnld.h" |
| 28 | +#include <stdnoreturn.h> |
| 29 | +#include <user_interface.h> |
| 30 | +#include <esp8266_undocumented.h> |
| 31 | + |
| 32 | + |
| 33 | +static inline uint32_t __rsil_1() { |
| 34 | + uint32_t program_state; |
| 35 | + asm volatile("rsil %0, 1" : "=r" (program_state)); |
| 36 | + return program_state; |
| 37 | +} |
| 38 | + |
| 39 | +static inline void __wsr_intenable(uint32_t interupt_enable) { |
| 40 | + asm volatile("wsr.intenable %0" :: "r" (interupt_enable)); |
| 41 | +} |
| 42 | + |
| 43 | +static inline void __wsr_litbase(uint32_t literal_base) { |
| 44 | + asm volatile("wsr.litbase %0" :: "r" (literal_base)); |
| 45 | +} |
| 46 | + |
| 47 | +static inline void __wsr_ps(uint32_t program_state) { |
| 48 | + asm volatile("wsr.ps %0" :: "r" (program_state)); |
| 49 | +} |
| 50 | + |
| 51 | +static inline void __wsr_vecbase(uint32_t vector_base) { |
| 52 | + asm volatile("wsr.vecbase %0" :: "r" (vector_base)); |
| 53 | +} |
| 54 | + |
| 55 | +[[noreturn]] void ICACHE_RAM_ATTR esp8266UartDownloadMode() |
| 56 | +{ |
| 57 | + /* reverse engineered from system_restart_core() */ |
| 58 | + /* Before disabling instruction cache and restoring instruction RAM to a |
| 59 | + * power-on like state, SPI bus must be idle. |
| 60 | + */ |
| 61 | + Wait_SPI_Idle(flashchip); |
| 62 | + |
| 63 | + Cache_Read_Disable(); |
| 64 | + /* This will disable the 32kB instruction cache and extend the IRAM by 32kB. |
| 65 | + * Therefore the full 64kB of IRAM will be available for boot. |
| 66 | + * Cache_Read_Enable() sets those bits but Cache_Read_Disable() does not clear |
| 67 | + * them. On hardware reset those bits are cleared. Therefore clear them also |
| 68 | + * for this reboot. |
| 69 | + */ |
| 70 | + CLEAR_PERI_REG_MASK(PERIPHS_DPORT_ICACHE_ENABLE, |
| 71 | + ICACHE_ENABLE_FIRST_16K | ICACHE_ENABLE_SECOND_16K); |
| 72 | + |
| 73 | + /* reverse engineered from _ResetHandler() */ |
| 74 | + /* disable all level 1 interrupts */ |
| 75 | + __wsr_intenable(0); |
| 76 | + /* Clear the literal base to use an offset of 0 for |
| 77 | + * Load 32-bit PC-Relative(L32R) instructions |
| 78 | + */ |
| 79 | + __wsr_litbase(0); |
| 80 | + asm volatile("rsync"); |
| 81 | + |
| 82 | + /* Set interrupt vector base address to system ROM */ |
| 83 | + __wsr_vecbase(0x40000000); |
| 84 | + /* Set interrupt level to 1. Therefore disable interrupts of level 1. |
| 85 | + * Above levels like level 2,... might still be active if available |
| 86 | + * on ESP8266. |
| 87 | + */ |
| 88 | + __rsil_1(); |
| 89 | + |
| 90 | + /* reverse engineered from _start() */ |
| 91 | + /* Set stack pointer to upper end of data RAM */ |
| 92 | + const uint32_t stack_pointer = 0x40000000; |
| 93 | + asm volatile("mov a1, %0" :: "r" (stack_pointer)); |
| 94 | + |
| 95 | + /* Set the program state register |
| 96 | + * Name Value Description |
| 97 | + * Interrupt level disable 0 enable all interrupt levels |
| 98 | + * Exception mode 0 normal operation |
| 99 | + * User vector mode 1 user vector mode, exceptions need to switch stacks |
| 100 | + * Privilege level 0 Set to Ring 0 |
| 101 | + */ |
| 102 | + __wsr_ps(0x20); |
| 103 | + asm volatile("rsync"); |
| 104 | + |
| 105 | + /* reverse engineered from main() */ |
| 106 | + const uint32_t uart_no = 0; |
| 107 | + uartAttach(); |
| 108 | + Uart_Init(uart_no); |
| 109 | + ets_install_uart_printf(uart_no); |
| 110 | + |
| 111 | + /* reverse engineered from boot_from_something() */ |
| 112 | + const uint16_t divlatch = uart_baudrate_detect(uart_no, 0); |
| 113 | + rom_uart_div_modify(uart_no, divlatch); |
| 114 | + UartDwnLdProc((uint8_t*)0x3fffa000, 0x2000, &user_start_fptr); |
| 115 | + |
| 116 | + /* reverse engineered from main() */ |
| 117 | + if (user_start_fptr == NULL) { |
| 118 | + if (boot_from_flash() != 0) { |
| 119 | + ets_printf("boot_from_flash() failed\n"); |
| 120 | + while (true); |
| 121 | + } |
| 122 | + } |
| 123 | + |
| 124 | + if (user_start_fptr) { |
| 125 | + user_start_fptr(); |
| 126 | + } |
| 127 | + |
| 128 | + ets_printf("user code done\n"); |
| 129 | + ets_run(); |
| 130 | +} |
| 131 | + |
| 132 | +[[noreturn]] void esp8266RebootIntoUartDownloadMode() |
| 133 | +{ |
| 134 | + /* reverse engineered from system_restart_local() */ |
| 135 | + if (system_func1(0x4) == -1) { |
| 136 | + clockgate_watchdog(0); |
| 137 | + SET_PERI_REG_MASK(PERIPHS_DPORT_18, 0xffff00ff); |
| 138 | + pm_open_rf(); |
| 139 | + } |
| 140 | + |
| 141 | + user_uart_wait_tx_fifo_empty(0, 0x7a120); |
| 142 | + user_uart_wait_tx_fifo_empty(1, 0x7a120); |
| 143 | + ets_intr_lock(); |
| 144 | + SET_PERI_REG_MASK(PERIPHS_DPORT_18, 0x7500); |
| 145 | + CLEAR_PERI_REG_MASK(PERIPHS_DPORT_18, 0x7500); |
| 146 | + SET_PERI_REG_MASK(PERIPHS_I2C_48, 0x2); |
| 147 | + CLEAR_PERI_REG_MASK(PERIPHS_I2C_48, 0x2); |
| 148 | + |
| 149 | + esp8266UartDownloadMode(); |
| 150 | +} |
| 151 | + |
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