@@ -157,6 +157,8 @@ void ICACHE_FLASH_ATTR uart_interrupt_handler(uart_t* uart) {
157
157
// ####################################################################################################
158
158
159
159
void ICACHE_FLASH_ATTR uart_wait_for_tx_fifo (uart_t * uart, size_t size_needed) {
160
+ if (uart == 0 )
161
+ return ;
160
162
if (uart->txEnabled ) {
161
163
while (true ) {
162
164
size_t tx_count = (READ_PERI_REG (UART_STATUS (uart->uart_nr )) >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT;
@@ -167,25 +169,33 @@ void ICACHE_FLASH_ATTR uart_wait_for_tx_fifo(uart_t* uart, size_t size_needed) {
167
169
}
168
170
169
171
size_t ICACHE_FLASH_ATTR uart_get_tx_fifo_room (uart_t * uart) {
172
+ if (uart == 0 )
173
+ return 0 ;
170
174
if (uart->txEnabled ) {
171
175
return UART_TX_FIFO_SIZE - ((READ_PERI_REG (UART_STATUS (uart->uart_nr )) >> UART_TXFIFO_CNT_S) & UART_TXFIFO_CNT);
172
176
}
173
177
return 0 ;
174
178
}
175
179
176
180
void ICACHE_FLASH_ATTR uart_wait_for_transmit (uart_t * uart) {
181
+ if (uart == 0 )
182
+ return ;
177
183
if (uart->txEnabled ) {
178
184
uart_wait_for_tx_fifo (uart, UART_TX_FIFO_SIZE);
179
185
}
180
186
}
181
187
182
188
void ICACHE_FLASH_ATTR uart_transmit_char (uart_t * uart, char c) {
189
+ if (uart == 0 )
190
+ return ;
183
191
if (uart->txEnabled ) {
184
192
WRITE_PERI_REG (UART_FIFO (uart->uart_nr ), c);
185
193
}
186
194
}
187
195
188
196
void ICACHE_FLASH_ATTR uart_transmit (uart_t * uart, const char * buf, size_t size) {
197
+ if (uart == 0 )
198
+ return ;
189
199
if (uart->txEnabled ) {
190
200
while (size) {
191
201
size_t part_size = (size > UART_TX_FIFO_SIZE) ? UART_TX_FIFO_SIZE : size;
@@ -201,6 +211,9 @@ void ICACHE_FLASH_ATTR uart_transmit(uart_t* uart, const char* buf, size_t size)
201
211
void ICACHE_FLASH_ATTR uart_flush (uart_t * uart) {
202
212
uint32_t tmp = 0x00000000 ;
203
213
214
+ if (uart == 0 )
215
+ return ;
216
+
204
217
if (uart->rxEnabled ) {
205
218
tmp |= UART_RXFIFO_RST;
206
219
}
@@ -214,6 +227,8 @@ void ICACHE_FLASH_ATTR uart_flush(uart_t* uart) {
214
227
}
215
228
216
229
void ICACHE_FLASH_ATTR uart_interrupt_enable (uart_t * uart) {
230
+ if (uart == 0 )
231
+ return ;
217
232
WRITE_PERI_REG (UART_INT_CLR (uart->uart_nr ), 0x1ff );
218
233
ETS_UART_INTR_ATTACH (&uart_interrupt_handler, uart); // uart parameter is not osed in irq function!
219
234
if (uart->rxEnabled ) {
@@ -223,6 +238,8 @@ void ICACHE_FLASH_ATTR uart_interrupt_enable(uart_t* uart) {
223
238
}
224
239
225
240
void ICACHE_FLASH_ATTR uart_interrupt_disable (uart_t * uart) {
241
+ if (uart == 0 )
242
+ return ;
226
243
if (uart->rxEnabled ) {
227
244
CLEAR_PERI_REG_MASK (UART_INT_ENA (uart->uart_nr ), UART_RXFIFO_FULL_INT_ENA);
228
245
}
@@ -233,30 +250,43 @@ void ICACHE_FLASH_ATTR uart_interrupt_disable(uart_t* uart) {
233
250
}
234
251
235
252
void ICACHE_FLASH_ATTR uart_arm_tx_interrupt (uart_t * uart) {
253
+ if (uart == 0 )
254
+ return ;
236
255
if (uart->txEnabled ) {
237
256
SET_PERI_REG_MASK (UART_INT_ENA (uart->uart_nr ), UART_TXFIFO_EMPTY_INT_ENA);
238
257
}
239
258
}
240
259
241
260
void ICACHE_FLASH_ATTR uart_disarm_tx_interrupt (uart_t * uart) {
261
+ if (uart == 0 )
262
+ return ;
242
263
if (uart->txEnabled ) {
243
264
CLEAR_PERI_REG_MASK (UART_INT_ENA (uart->uart_nr ), UART_TXFIFO_EMPTY_INT_ENA);
244
265
}
245
266
}
246
267
247
268
void ICACHE_FLASH_ATTR uart_set_baudrate (uart_t * uart, int baud_rate) {
269
+ if (uart == 0 )
270
+ return ;
248
271
uart->baud_rate = baud_rate;
249
272
uart_div_modify (uart->uart_nr , UART_CLK_FREQ / (uart->baud_rate ));
250
273
}
251
274
252
275
int ICACHE_FLASH_ATTR uart_get_baudrate (uart_t * uart) {
276
+ if (uart == 0 )
277
+ return 0 ;
253
278
return uart->baud_rate ;
254
279
}
255
280
256
281
uart_t * ICACHE_FLASH_ATTR uart_init (UARTnr_t uart_nr, int baudrate) {
257
282
258
283
uint32_t conf1 = 0x00000000 ;
259
284
uart_t * uart = (uart_t *) os_malloc (sizeof (uart_t ));
285
+
286
+ if (uart == 0 ) {
287
+ return 0 ;
288
+ }
289
+
260
290
uart->uart_nr = uart_nr;
261
291
262
292
switch (uart->uart_nr ) {
@@ -303,6 +333,8 @@ uart_t* ICACHE_FLASH_ATTR uart_init(UARTnr_t uart_nr, int baudrate) {
303
333
}
304
334
305
335
void ICACHE_FLASH_ATTR uart_uninit (uart_t * uart) {
336
+ if (uart == 0 )
337
+ return ;
306
338
uart_interrupt_disable (uart);
307
339
308
340
switch (uart->rxPin ) {
@@ -316,7 +348,7 @@ void ICACHE_FLASH_ATTR uart_uninit(uart_t* uart) {
316
348
break ;
317
349
}
318
350
319
- switch (uart->rxPin ) {
351
+ switch (uart->txPin ) {
320
352
case 1 :
321
353
PIN_FUNC_SELECT (PERIPHS_IO_MUX_U0TXD_U, FUNC_GPIO1);
322
354
break ;
@@ -335,6 +367,8 @@ void ICACHE_FLASH_ATTR uart_uninit(uart_t* uart) {
335
367
}
336
368
337
369
void ICACHE_FLASH_ATTR uart_swap (uart_t * uart) {
370
+ if (uart == 0 )
371
+ return ;
338
372
switch (uart->uart_nr ) {
339
373
case UART0:
340
374
if (uart->txPin == 1 && uart->rxPin == 3 ) {
@@ -461,6 +495,10 @@ void ICACHE_FLASH_ATTR HardwareSerial::begin(unsigned long baud, byte config) {
461
495
462
496
_uart = uart_init (_uart_nr, baud);
463
497
498
+ if (_uart == 0 ) {
499
+ return ;
500
+ }
501
+
464
502
if (_uart->rxEnabled ) {
465
503
_rx_buffer = new cbuf (SERIAL_RX_BUFFER_SIZE);
466
504
}
@@ -481,10 +519,14 @@ void ICACHE_FLASH_ATTR HardwareSerial::end() {
481
519
}
482
520
483
521
void ICACHE_FLASH_ATTR HardwareSerial::swap () {
522
+ if (_uart == 0 )
523
+ return ;
484
524
uart_swap (_uart);
485
525
}
486
526
487
527
void ICACHE_FLASH_ATTR HardwareSerial::setDebugOutput (bool en) {
528
+ if (_uart == 0 )
529
+ return ;
488
530
if (en) {
489
531
uart_set_debug (_uart->uart_nr );
490
532
} else {
@@ -508,6 +550,8 @@ bool ICACHE_FLASH_ATTR HardwareSerial::isRxEnabled(void) {
508
550
}
509
551
510
552
int ICACHE_FLASH_ATTR HardwareSerial::available (void ) {
553
+ if (_uart == 0 )
554
+ return 0 ;
511
555
if (_uart->rxEnabled ) {
512
556
return static_cast <int >(_rx_buffer->getSize ());
513
557
} else {
@@ -516,6 +560,8 @@ int ICACHE_FLASH_ATTR HardwareSerial::available(void) {
516
560
}
517
561
518
562
int ICACHE_FLASH_ATTR HardwareSerial::peek (void ) {
563
+ if (_uart == 0 )
564
+ return -1 ;
519
565
if (_uart->rxEnabled ) {
520
566
return _rx_buffer->peek ();
521
567
} else {
@@ -524,6 +570,8 @@ int ICACHE_FLASH_ATTR HardwareSerial::peek(void) {
524
570
}
525
571
526
572
int ICACHE_FLASH_ATTR HardwareSerial::read (void ) {
573
+ if (_uart == 0 )
574
+ return -1 ;
527
575
if (_uart->rxEnabled ) {
528
576
return _rx_buffer->read ();
529
577
} else {
@@ -532,6 +580,8 @@ int ICACHE_FLASH_ATTR HardwareSerial::read(void) {
532
580
}
533
581
534
582
int ICACHE_FLASH_ATTR HardwareSerial::availableForWrite (void ) {
583
+ if (_uart == 0 )
584
+ return 0 ;
535
585
if (_uart->txEnabled ) {
536
586
return static_cast <int >(_tx_buffer->room ());
537
587
} else {
@@ -540,6 +590,8 @@ int ICACHE_FLASH_ATTR HardwareSerial::availableForWrite(void) {
540
590
}
541
591
542
592
void ICACHE_FLASH_ATTR HardwareSerial::flush () {
593
+ if (_uart == 0 )
594
+ return ;
543
595
if (!_uart->txEnabled )
544
596
return ;
545
597
if (!_written)
@@ -552,7 +604,7 @@ void ICACHE_FLASH_ATTR HardwareSerial::flush() {
552
604
}
553
605
554
606
size_t ICACHE_FLASH_ATTR HardwareSerial::write (uint8_t c) {
555
- if (!_uart->txEnabled )
607
+ if (_uart == 0 || !_uart->txEnabled )
556
608
return 0 ;
557
609
_written = true ;
558
610
size_t room = uart_get_tx_fifo_room (_uart);
@@ -577,10 +629,16 @@ ICACHE_FLASH_ATTR HardwareSerial::operator bool() const {
577
629
}
578
630
579
631
void ICACHE_FLASH_ATTR HardwareSerial::_rx_complete_irq (char c) {
580
- _rx_buffer->write (c);
632
+ if (_rx_buffer) {
633
+ _rx_buffer->write (c);
634
+ }
581
635
}
582
636
583
637
void ICACHE_FLASH_ATTR HardwareSerial::_tx_empty_irq (void ) {
638
+ if (_uart == 0 )
639
+ return ;
640
+ if (_tx_buffer == 0 )
641
+ return ;
584
642
size_t queued = _tx_buffer->getSize ();
585
643
if (!queued) {
586
644
uart_disarm_tx_interrupt (_uart);
0 commit comments