Merge branch 'master' of https://github.com/esp8266/Arduino into gcc9.1

Rebuild eboot.elf with new sources.

Author: earlephilhower

README.md

@@ -135,3 +135,5 @@ ESP8266 core files are licensed under LGPL.
 [SoftwareSerial repo](https://github.com/plerup/espsoftwareserial)
 
 [Serial Monitor Arduino IDE plugin](https://github.com/mytrain/arduino-esp8266-serial-plugin) Original discussion [here](https://github.com/esp8266/Arduino/issues/1360), quick download [there](http://mytrain.fr/cms//images/mytrain/private/ESP8266SM.v3.zip).
+
+[FTP Client/Server Library](https://github.com/dplasa/FTPClientServer) 

bootloaders/eboot/eboot.c

@@ -12,7 +12,6 @@
 #include <string.h>
 #include "flash.h"
 #include "eboot_command.h"
-#include "spi_vendors.h"
 #include <uzlib.h>
 
 extern unsigned char _gzip_dict;
@@ -115,10 +114,12 @@ int uzlib_flash_read_cb(struct uzlib_uncomp *m)
 }
 
 unsigned char gzip_dict[32768];
+uint8_t buffer2[FLASH_SECTOR_SIZE]; // no room for this on the stack
 
 int copy_raw(const uint32_t src_addr,
              const uint32_t dst_addr,
-             const uint32_t size)
+             const uint32_t size,
+             const bool verify)
 {
     // require regions to be aligned
     if ((src_addr & 0xfff) != 0 ||
@@ -158,8 +159,10 @@ int copy_raw(const uint32_t src_addr,
 	gzip = true;
     }
     while (left > 0) {
-        if (SPIEraseSector(daddr/buffer_size)) {
-            return 2;
+        if (!verify) {
+           if (SPIEraseSector(daddr/buffer_size)) {
+               return 2;
+           }
         }
         if (!gzip) {
             if (SPIRead(saddr, buffer, buffer_size)) {
@@ -179,8 +182,17 @@ int copy_raw(const uint32_t src_addr,
                 buffer[i] = 0xff;
             }
         }
-        if (SPIWrite(daddr, buffer, buffer_size)) {
-            return 4;
+        if (verify) {
+            if (SPIRead(daddr, buffer2, buffer_size)) {
+                return 4;
+            }
+            if (memcmp(buffer, buffer2, buffer_size)) {
+                return 9;
+            }
+        } else {
+            if (SPIWrite(daddr, buffer, buffer_size)) {
+                return 4;
+            }
         }
         saddr += buffer_size;
         daddr += buffer_size;
@@ -190,29 +202,6 @@ int copy_raw(const uint32_t src_addr,
     return 0;
 }
 
-//#define XMC_SUPPORT
-#ifdef XMC_SUPPORT
-// Define a few SPI0 registers we need access to
-#define ESP8266_REG(addr) *((volatile uint32_t *)(0x60000000+(addr)))
-#define SPI0CMD ESP8266_REG(0x200)
-#define SPI0CLK ESP8266_REG(0x218)
-#define SPI0C   ESP8266_REG(0x208)
-#define SPI0W0  ESP8266_REG(0x240)
-
-#define SPICMDRDID (1 << 28)
-
-/* spi_flash_get_id()
-   Returns the flash chip ID - same as the SDK function.
-   We need our own version as the SDK isn't available here.
- */
-uint32_t __attribute__((noinline)) spi_flash_get_id() {
-  SPI0W0=0;
-  SPI0CMD=SPICMDRDID;
-  while (SPI0CMD) {}
-  return SPI0W0;
-}
-#endif // XMC_SUPPORT
-
 int main()
 {
     int res = 9;
@@ -235,47 +224,20 @@ int main()
     if (cmd.action == ACTION_COPY_RAW) {
         ets_putc('c'); ets_putc('p'); ets_putc(':');
 
-#ifdef XMC_SUPPORT
-        // save the flash access speed registers
-        uint32_t spi0clk = SPI0CLK;
-        uint32_t spi0c   = SPI0C;
-        
-        uint32_t vendor  = spi_flash_get_id() & 0x000000ff;
-        if (vendor == SPI_FLASH_VENDOR_XMC) {
-           uint32_t flashinfo=0;
-           if (SPIRead(0, &flashinfo, 4)) {
-              // failed to read the configured flash speed.
-              // Do not change anything,
-           } else {
-              // select an appropriate flash speed
-              // Register values are those used by ROM
-              switch ((flashinfo >> 24) & 0x0f) {
-                 case 0x0: // 40MHz, slow to 20
-                 case 0x1: // 26MHz, slow to 20
-                      SPI0CLK = 0x00003043;
-                      SPI0C   = 0x00EAA313;
-                      break;
-                 case 0x2: // 20MHz, no change
-                      break;
-                 case 0xf: // 80MHz, slow to 26
-                      SPI0CLK = 0x00002002;
-                      SPI0C   = 0x00EAA202;
-                      break;
-                 default:
-                      break;
-              }
-           }
-        }
-#endif // XMC_SUPPORT
         ets_wdt_disable();
-        res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2]);
+        res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2], false);
         ets_wdt_enable();
-        
-#ifdef XMC_SUPPORT
-        // restore the saved flash access speed registers
-        SPI0CLK = spi0clk;
-        SPI0C   = spi0c;
-#endif        
+
+        ets_putc('0'+res); ets_putc('\n');
+
+        // Verify the copy
+        ets_putc('c'); ets_putc('m'); ets_putc('p'); ets_putc(':');
+        if (res == 0) {
+            ets_wdt_disable();
+            res = copy_raw(cmd.args[0], cmd.args[1], cmd.args[2], true);
+            ets_wdt_enable();
+            }
+
         ets_putc('0'+res); ets_putc('\n');
         if (res == 0) {
             cmd.action = ACTION_LOAD_APP;

bootloaders/eboot/eboot.elf

@@ -52,7 +52,7 @@ static SpiOpResult PRECACHE_ATTR
 _SPICommand(volatile uint32_t spiIfNum,
             uint32_t spic,uint32_t spiu,uint32_t spiu1,uint32_t spiu2,
             uint32_t *data,uint32_t writeWords,uint32_t readWords)
-{ 
+{
   if (spiIfNum>1)
      return SPI_RESULT_ERR;
 
@@ -69,8 +69,11 @@ _SPICommand(volatile uint32_t spiIfNum,
   volatile SpiFlashChip *fchip=flashchip;
   volatile uint32_t spicmdusr=SPICMDUSR;
 
+  uint32_t saved_ps=0;
+
   if (!spiIfNum) {
-     // Only need to precache when using SPI0
+     // Only need to disable interrupts and precache when using SPI0
+     saved_ps = xt_rsil(15);
      PRECACHE_START();
      Wait_SPI_Idlep((SpiFlashChip *)fchip);
   }
@@ -116,6 +119,9 @@ _SPICommand(volatile uint32_t spiIfNum,
   SPIREG(SPI0C) = oldSPI0C;
 
   PRECACHE_END();
+  if (!spiIfNum) {
+      xt_wsr_ps(saved_ps);
+  }
   return (timeout>0 ? SPI_RESULT_OK : SPI_RESULT_TIMEOUT);
 }
 

cores/esp8266/core_esp8266_spi_utils.cpp

@@ -175,7 +175,7 @@ void configTime(int timezone_sec, int daylightOffset_sec, const char* server1, c
         tzr->d = 0;
         tzr->s = 0;
         tzr->change = 0;
-        tzr->offset = _timezone;
+        tzr->offset = -_timezone;
     }
 
     // sntp servers

cores/esp8266/time.cpp

@@ -136,7 +136,7 @@ For reference:
 
 Time-wait PCB state helps TCP not confusing two consecutive connections with the
 same (s-ip,s-port,d-ip,d-port) when the first is already closed but still
-having duplicate packets lost in internet arriving later during the second. 
+having duplicate packets lost in internet arriving later during the second.
 Artificially clearing them is a workaround to help saving precious heap.
 
 The following lines are compatible with both lwIP versions:
@@ -147,7 +147,7 @@ The following lines are compatible with both lwIP versions:
     struct tcp_pcb;
     extern struct tcp_pcb* tcp_tw_pcbs;
     extern "C" void tcp_abort (struct tcp_pcb* pcb);
-    
+
     void tcpCleanup (void) {
       while (tcp_tw_pcbs)
         tcp_abort(tcp_tw_pcbs);
@@ -168,3 +168,15 @@ This script is also used to manage uncommon options that are currently not
 available in the IDE menu.
 
 `Read more <a05-board-generator.rst>`__.
+
+My WiFi won't reconnect after deep sleep using ``WAKE_RF_DISABLED``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+When you implement deep sleep using ``WAKE_RF_DISABLED``, this forces what
+appears to be a bare metal disabling of WiFi functionality, which is not
+restored using ``WiFi.forceSleepWake()`` or ``WiFi.mode(WIFI_STA)``. If you need
+to implement deep sleep with ``WAKE_RF_DISABLED`` and later connect to WiFi, you
+will need to implement an additional (short) deep sleep using
+``WAKE_RF_DEFAULT``.
+
+Ref.  `#3072 <https://github.com/esp8266/Arduino/issues/3072>`__

doc/faq/readme.rst

@@ -41,7 +41,7 @@ SPI
 
 SPI library supports the entire Arduino SPI API including transactions, including setting phase (CPHA). Setting the Clock polarity (CPOL) is not supported, yet (SPI\_MODE2 and SPI\_MODE3 not working).
 
-The usual SPI pins are: 
+The usual SPI pins are:
 
 - ``MOSI`` = GPIO13
 - ``MISO`` = GPIO12
@@ -73,7 +73,7 @@ ESP-specific APIs
 
 Some ESP-specific APIs related to deep sleep, RTC and flash memories are available in the ``ESP`` object.
 
-``ESP.deepSleep(microseconds, mode)`` will put the chip into deep sleep. ``mode`` is one of ``WAKE_RF_DEFAULT``, ``WAKE_RFCAL``, ``WAKE_NO_RFCAL``, ``WAKE_RF_DISABLED``. (GPIO16 needs to be tied to RST to wake from deepSleep.) The chip can sleep for at most ``ESP.deepSleepMax()`` microseconds.
+``ESP.deepSleep(microseconds, mode)`` will put the chip into deep sleep. ``mode`` is one of ``WAKE_RF_DEFAULT``, ``WAKE_RFCAL``, ``WAKE_NO_RFCAL``, ``WAKE_RF_DISABLED``. (GPIO16 needs to be tied to RST to wake from deepSleep.) The chip can sleep for at most ``ESP.deepSleepMax()`` microseconds. If you implement deep sleep with ``WAKE_RF_DISABLED`` and require WiFi functionality on wake up, you will need to implement an additional ``WAKE_RF_DEFAULT`` before WiFi functionality is available.
 
 ``ESP.deepSleepInstant(microseconds, mode)`` works similarly to ``ESP.deepSleep`` but  sleeps instantly without waiting for WiFi to shutdown.
 
@@ -87,7 +87,7 @@ Some ESP-specific APIs related to deep sleep, RTC and flash memories are availab
 
 ``ESP.getHeapFragmentation()`` returns the fragmentation metric (0% is clean, more than ~50% is not harmless)
 
-``ESP.getMaxFreeBlockSize()`` returns the maximum allocatable ram block regarding heap fragmentation
+``ESP.getMaxFreeBlockSize()`` returns the largest contiguous free RAM block in the heap, useful for checking heap fragmentation.  **NOTE:** Maximum ``malloc()``able block will be smaller due to memory manager overheads.
 
 ``ESP.getChipId()`` returns the ESP8266 chip ID as a 32-bit integer.