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Merge pull request #433 from me-no-dev/esp8266
allow proper content length handling
2 parents 432198f + 8ba054c commit 5d4266a

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5 files changed

+448
-31
lines changed

5 files changed

+448
-31
lines changed

‎.gitignore

-1
Original file line numberDiff line numberDiff line change
@@ -72,4 +72,3 @@ nbproject
7272
build/macosx/esptool-*-osx.zip
7373

7474
build/macosx/dist/osx-xtensa-lx106-elf.tgz
75-
/hardware/esp8266com/esp8266/tools

‎libraries/ESP8266WebServer/src/ESP8266WebServer.cpp

+4-5
Original file line numberDiff line numberDiff line change
@@ -140,11 +140,10 @@ void ESP8266WebServer::send(int code, const char* content_type, String content)
140140
content_type = "text/html";
141141

142142
sendHeader("Content-Type", content_type, true);
143-
if (_contentLength != CONTENT_LENGTH_UNKNOWN) {
144-
size_t length = (_contentLength == CONTENT_LENGTH_NOT_SET) ?
145-
content.length() : _contentLength;
146-
String lengthStr(length);
147-
sendHeader("Content-Length", lengthStr.c_str());
143+
if (_contentLength != CONTENT_LENGTH_UNKNOWN && _contentLength != CONTENT_LENGTH_NOT_SET) {
144+
sendHeader("Content-Length", String(_contentLength).c_str());
145+
} else if(content.length() > 0){
146+
sendHeader("Content-Length", String(content.length()).c_str());
148147
}
149148
sendHeader("Connection", "close");
150149
sendHeader("Access-Control-Allow-Origin", "*");

‎tools/sdk/include/ets_sys.h

+43-25
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ typedef struct _ETSTIMER_ {
3939

4040
typedef void (*int_handler_t)(void*);
4141

42+
#define ETS_SLC_INUM 1
4243
#define ETS_SPI_INUM 2
4344
#define ETS_GPIO_INUM 4
4445
#define ETS_UART_INUM 5
@@ -54,6 +55,12 @@ typedef void (*int_handler_t)(void*);
5455
#define ETS_INTR_UNLOCK() \
5556
ets_intr_unlock()
5657

58+
#define ETS_INTR_ENABLE(inum) \
59+
ets_isr_unmask((1<<inum))
60+
61+
#define ETS_INTR_DISABLE(inum) \
62+
ets_isr_mask((1<<inum))
63+
5764
inline uint32_t ETS_INTR_ENABLED(void)
5865
{
5966
uint32_t enabled;
@@ -71,53 +78,64 @@ inline uint32_t ETS_INTR_PENDING(void)
7178
#define ETS_CCOMPARE0_INTR_ATTACH(func, arg) \
7279
ets_isr_attach(ETS_CCOMPARE0_INUM, (int_handler_t)(func), (void *)(arg))
7380

81+
#define ETS_CCOMPARE0_ENABLE() \
82+
ETS_INTR_ENABLE(ETS_CCOMPARE0_INUM)
83+
84+
#define ETS_CCOMPARE0_DISABLE() \
85+
ETS_INTR_DISABLE(ETS_CCOMPARE0_INUM)
86+
87+
7488
#define ETS_FRC_TIMER1_INTR_ATTACH(func, arg) \
7589
ets_isr_attach(ETS_FRC_TIMER1_INUM, (int_handler_t)(func), (void *)(arg))
7690

7791
#define ETS_FRC_TIMER1_NMI_INTR_ATTACH(func) \
78-
NmiTimSetFunc(func)
79-
92+
NmiTimSetFunc(func)
93+
94+
#define ETS_FRC1_INTR_ENABLE() \
95+
ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
96+
97+
#define ETS_FRC1_INTR_DISABLE() \
98+
ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
99+
100+
80101
#define ETS_GPIO_INTR_ATTACH(func, arg) \
81102
ets_isr_attach(ETS_GPIO_INUM, (int_handler_t)(func), (void *)(arg))
82103

83-
#define ETS_UART_INTR_ATTACH(func, arg) \
84-
ets_isr_attach(ETS_UART_INUM, (int_handler_t)(func), (void *)(arg))
85-
86-
#define ETS_SPI_INTR_ATTACH(func, arg) \
87-
ets_isr_attach(ETS_SPI_INUM, (int_handler_t)(func), (void *)(arg))
104+
#define ETS_GPIO_INTR_ENABLE() \
105+
ETS_INTR_ENABLE(ETS_GPIO_INUM)
88106

89-
#define ETS_INTR_ENABLE(inum) \
90-
ets_isr_unmask((1<<inum))
107+
#define ETS_GPIO_INTR_DISABLE() \
108+
ETS_INTR_DISABLE(ETS_GPIO_INUM)
91109

92-
#define ETS_INTR_DISABLE(inum) \
93-
ets_isr_mask((1<<inum))
94110

95-
#define ETS_SPI_INTR_ENABLE() \
96-
ETS_INTR_ENABLE(ETS_SPI_INUM)
111+
#define ETS_UART_INTR_ATTACH(func, arg) \
112+
ets_isr_attach(ETS_UART_INUM, (int_handler_t)(func), (void *)(arg))
97113

98114
#define ETS_UART_INTR_ENABLE() \
99115
ETS_INTR_ENABLE(ETS_UART_INUM)
100116

101117
#define ETS_UART_INTR_DISABLE() \
102118
ETS_INTR_DISABLE(ETS_UART_INUM)
103119

104-
#define ETS_CCOMPARE0_ENABLE() \
105-
ETS_INTR_ENABLE(ETS_CCOMPARE0_INUM)
106120

107-
#define ETS_CCOMPARE0_DISABLE() \
108-
ETS_INTR_DISABLE(ETS_CCOMPARE0_INUM)
121+
#define ETS_SPI_INTR_ATTACH(func, arg) \
122+
ets_isr_attach(ETS_SPI_INUM, (int_handler_t)(func), (void *)(arg))
109123

110-
#define ETS_FRC1_INTR_ENABLE() \
111-
ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
124+
#define ETS_SPI_INTR_ENABLE() \
125+
ETS_INTR_ENABLE(ETS_SPI_INUM)
112126

113-
#define ETS_FRC1_INTR_DISABLE() \
114-
ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
127+
#define ETS_SPI_INTR_DISABLE() \
128+
ETS_INTR_DISABLE(ETS_SPI_INUM)
115129

116-
#define ETS_GPIO_INTR_ENABLE() \
117-
ETS_INTR_ENABLE(ETS_GPIO_INUM)
118130

119-
#define ETS_GPIO_INTR_DISABLE() \
120-
ETS_INTR_DISABLE(ETS_GPIO_INUM)
131+
#define ETS_SLC_INTR_ATTACH(func, arg) \
132+
ets_isr_attach(ETS_SLC_INUM, (int_handler_t)(func), (void *)(arg))
133+
134+
#define ETS_SLC_INTR_ENABLE() \
135+
ETS_INTR_ENABLE(ETS_SLC_INUM)
136+
137+
#define ETS_SLC_INTR_DISABLE() \
138+
ETS_INTR_DISABLE(ETS_SLC_INUM)
121139

122140

123141
void *pvPortMalloc(size_t xWantedSize) __attribute__((malloc, alloc_size(1)));

‎tools/sdk/include/i2s_reg.h

+118
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
/*
2+
* Copyright (c) 2010 - 2011 Espressif System
3+
*
4+
*/
5+
6+
#ifndef I2S_REGISTER_H_
7+
#define I2S_REGISTER_H_
8+
9+
#define DR_REG_I2S_BASE (0x60000e00)
10+
11+
#define I2STXFIFO (DR_REG_I2S_BASE + 0x0000)
12+
#define I2SRXFIFO (DR_REG_I2S_BASE + 0x0004)
13+
#define I2SCONF (DR_REG_I2S_BASE + 0x0008)
14+
#define I2S_BCK_DIV_NUM 0x0000003F
15+
#define I2S_BCK_DIV_NUM_S 22
16+
#define I2S_CLKM_DIV_NUM 0x0000003F
17+
#define I2S_CLKM_DIV_NUM_S 16
18+
#define I2S_BITS_MOD 0x0000000F
19+
#define I2S_BITS_MOD_S 12
20+
#define I2S_RECE_MSB_SHIFT (BIT(11))
21+
#define I2S_TRANS_MSB_SHIFT (BIT(10))
22+
#define I2S_I2S_RX_START (BIT(9))
23+
#define I2S_I2S_TX_START (BIT(8))
24+
#define I2S_MSB_RIGHT (BIT(7))
25+
#define I2S_RIGHT_FIRST (BIT(6))
26+
#define I2S_RECE_SLAVE_MOD (BIT(5))
27+
#define I2S_TRANS_SLAVE_MOD (BIT(4))
28+
#define I2S_I2S_RX_FIFO_RESET (BIT(3))
29+
#define I2S_I2S_TX_FIFO_RESET (BIT(2))
30+
#define I2S_I2S_RX_RESET (BIT(1))
31+
#define I2S_I2S_TX_RESET (BIT(0))
32+
#define I2S_I2S_RESET_MASK 0xf
33+
34+
#define I2SINT_RAW (DR_REG_I2S_BASE + 0x000c)
35+
#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5))
36+
#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4))
37+
#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3))
38+
#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2))
39+
#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1))
40+
#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0))
41+
42+
43+
#define I2SINT_ST (DR_REG_I2S_BASE + 0x0010)
44+
#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5))
45+
#define I2S_I2S_TX_WFULL_INT_ST (BIT(4))
46+
#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3))
47+
#define I2S_I2S_RX_WFULL_INT_ST (BIT(2))
48+
#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1))
49+
#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0))
50+
51+
#define I2SINT_ENA (DR_REG_I2S_BASE + 0x0014)
52+
#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5))
53+
#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4))
54+
#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3))
55+
#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2))
56+
#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1))
57+
#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0))
58+
59+
#define I2SINT_CLR (DR_REG_I2S_BASE + 0x0018)
60+
#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5))
61+
#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4))
62+
#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3))
63+
#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2))
64+
#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1))
65+
#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0))
66+
67+
#define I2STIMING (DR_REG_I2S_BASE + 0x001c)
68+
#define I2S_TRANS_BCK_IN_INV (BIT(22))
69+
#define I2S_RECE_DSYNC_SW (BIT(21))
70+
#define I2S_TRANS_DSYNC_SW (BIT(20))
71+
#define I2S_RECE_BCK_OUT_DELAY 0x00000003
72+
#define I2S_RECE_BCK_OUT_DELAY_S 18
73+
#define I2S_RECE_WS_OUT_DELAY 0x00000003
74+
#define I2S_RECE_WS_OUT_DELAY_S 16
75+
#define I2S_TRANS_SD_OUT_DELAY 0x00000003
76+
#define I2S_TRANS_SD_OUT_DELAY_S 14
77+
#define I2S_TRANS_WS_OUT_DELAY 0x00000003
78+
#define I2S_TRANS_WS_OUT_DELAY_S 12
79+
#define I2S_TRANS_BCK_OUT_DELAY 0x00000003
80+
#define I2S_TRANS_BCK_OUT_DELAY_S 10
81+
#define I2S_RECE_SD_IN_DELAY 0x00000003
82+
#define I2S_RECE_SD_IN_DELAY_S 8
83+
#define I2S_RECE_WS_IN_DELAY 0x00000003
84+
#define I2S_RECE_WS_IN_DELAY_S 6
85+
#define I2S_RECE_BCK_IN_DELAY 0x00000003
86+
#define I2S_RECE_BCK_IN_DELAY_S 4
87+
#define I2S_TRANS_WS_IN_DELAY 0x00000003
88+
#define I2S_TRANS_WS_IN_DELAY_S 2
89+
#define I2S_TRANS_BCK_IN_DELAY 0x00000003
90+
#define I2S_TRANS_BCK_IN_DELAY_S 0
91+
92+
#define I2S_FIFO_CONF (DR_REG_I2S_BASE + 0x0020)
93+
#define I2S_I2S_RX_FIFO_MOD 0x00000007
94+
#define I2S_I2S_RX_FIFO_MOD_S 16
95+
#define I2S_I2S_TX_FIFO_MOD 0x00000007
96+
#define I2S_I2S_TX_FIFO_MOD_S 13
97+
#define I2S_I2S_DSCR_EN (BIT(12))
98+
#define I2S_I2S_TX_DATA_NUM 0x0000003F
99+
#define I2S_I2S_TX_DATA_NUM_S 6
100+
#define I2S_I2S_RX_DATA_NUM 0x0000003F
101+
#define I2S_I2S_RX_DATA_NUM_S 0
102+
103+
104+
#define I2SRXEOF_NUM (DR_REG_I2S_BASE + 0x0024)
105+
#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF
106+
#define I2S_I2S_RX_EOF_NUM_S 0
107+
108+
#define I2SCONF_SIGLE_DATA (DR_REG_I2S_BASE + 0x0028)
109+
#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF
110+
#define I2S_I2S_SIGLE_DATA_S 0
111+
112+
#define I2SCONF_CHAN (DR_REG_I2S_BASE + 0x002c)
113+
#define I2S_RX_CHAN_MOD 0x00000003
114+
#define I2S_RX_CHAN_MOD_S 3
115+
#define I2S_TX_CHAN_MOD 0x00000007
116+
#define I2S_TX_CHAN_MOD_S 0
117+
118+
#endif

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