Add {set,get}_atomic_ordering to instruction_value.

Author: nlewycky

Diff for: src/values/instruction_value.rs

@@ -1,5 +1,5 @@
 use either::{Either, Either::{Left, Right}};
-use llvm_sys::core::{LLVMGetAlignment, LLVMSetAlignment, LLVMGetInstructionOpcode, LLVMIsTailCall, LLVMGetPreviousInstruction, LLVMGetNextInstruction, LLVMGetInstructionParent, LLVMInstructionEraseFromParent, LLVMInstructionClone, LLVMSetVolatile, LLVMGetVolatile, LLVMGetNumOperands, LLVMGetOperand, LLVMGetOperandUse, LLVMSetOperand, LLVMValueAsBasicBlock, LLVMIsABasicBlock, LLVMGetICmpPredicate, LLVMGetFCmpPredicate, LLVMIsAAllocaInst, LLVMIsALoadInst, LLVMIsAStoreInst};
+use llvm_sys::core::{LLVMGetAlignment, LLVMSetAlignment, LLVMGetOrdering, LLVMSetOrdering, LLVMGetInstructionOpcode, LLVMIsTailCall, LLVMGetPreviousInstruction, LLVMGetNextInstruction, LLVMGetInstructionParent, LLVMInstructionEraseFromParent, LLVMInstructionClone, LLVMSetVolatile, LLVMGetVolatile, LLVMGetNumOperands, LLVMGetOperand, LLVMGetOperandUse, LLVMSetOperand, LLVMValueAsBasicBlock, LLVMIsABasicBlock, LLVMGetICmpPredicate, LLVMGetFCmpPredicate, LLVMIsAAllocaInst, LLVMIsALoadInst, LLVMIsAStoreInst};
 #[llvm_versions(3.9..=latest)]
 use llvm_sys::core::LLVMInstructionRemoveFromParent;
 use llvm_sys::LLVMOpcode;
@@ -8,7 +8,7 @@ use llvm_sys::prelude::LLVMValueRef;
 use crate::basic_block::BasicBlock;
 use crate::values::traits::AsValueRef;
 use crate::values::{BasicValue, BasicValueEnum, BasicValueUse, Value};
-use crate::{IntPredicate, FloatPredicate};
+use crate::{AtomicOrdering, IntPredicate, FloatPredicate};
 
 // REVIEW: Split up into structs for SubTypes on InstructionValues?
 // REVIEW: This should maybe be split up into InstructionOpcode and ConstOpcode?
@@ -243,6 +243,45 @@ impl InstructionValue {
         }
     }
 
+    // SubTypes: Only apply to memory access instructions
+    /// Returns atomic ordering on a memory access instruction.
+    pub fn get_atomic_ordering(&self) -> Result<AtomicOrdering, &'static str> {
+        let value_ref = self.as_value_ref();
+        if unsafe { LLVMIsALoadInst(value_ref) }.is_null() &&
+            unsafe { LLVMIsAStoreInst(value_ref) }.is_null() {
+                return Err("Value is not a load or store.");
+            }
+        Ok(unsafe { LLVMGetOrdering(value_ref) }.into())
+    }
+
+    // SubTypes: Only apply to memory access instructions
+    /// Sets atomic ordering on a memory access instruction.
+    pub fn set_atomic_ordering(&self, ordering: AtomicOrdering) -> Result<(), &'static str> {
+        let value_ref = self.as_value_ref();
+        let is_load = !unsafe { LLVMIsALoadInst(value_ref) }.is_null();
+        let is_store = !unsafe { LLVMIsAStoreInst(value_ref) }.is_null();
+
+        // Although fence and atomicrmw both have an ordering, the LLVM C API
+        // does not support them. The cmpxchg instruction has two orderings and
+        // does not work with this API.
+        if !is_load && !is_store {
+            return Err("Value is not a load or store instruction.");
+        }
+        match ordering {
+            AtomicOrdering::Release => {
+                if is_load { return Err("The release ordering is not valid on load instructions.") }
+            }
+            AtomicOrdering::AcquireRelease => {
+                return Err("The acq_rel ordering is not valid on load or store instructions.")
+            }
+            AtomicOrdering::Acquire => {
+                if is_store { return Err("The acquire ordering is not valid on store instructions.") }
+            }
+            _ => { }
+        };
+        Ok(unsafe { LLVMSetOrdering(value_ref, ordering.into()) })
+    }
+
     /// Obtains the number of operands an `InstructionValue` has.
     /// An operand is a `BasicValue` used in an IR instruction.
     ///

Diff for: tests/all/test_instruction_values.rs

@@ -1,6 +1,6 @@
 extern crate inkwell;
 
-use self::inkwell::{AddressSpace, IntPredicate, FloatPredicate};
+use self::inkwell::{AddressSpace, AtomicOrdering, IntPredicate, FloatPredicate};
 use self::inkwell::context::Context;
 use self::inkwell::values::{BasicValue, InstructionOpcode::*};
 
@@ -304,9 +304,23 @@ fn test_mem_instructions() {
     assert!(store_instruction.set_alignment(14).is_err());
     assert_eq!(store_instruction.get_alignment().unwrap(), 0);
 
+    assert_eq!(store_instruction.get_atomic_ordering().unwrap(), AtomicOrdering::NotAtomic);
+    assert_eq!(load_instruction.get_atomic_ordering().unwrap(), AtomicOrdering::NotAtomic);
+    assert!(store_instruction.set_atomic_ordering(AtomicOrdering::Monotonic).is_ok());
+    assert_eq!(store_instruction.get_atomic_ordering().unwrap(), AtomicOrdering::Monotonic);
+    assert!(store_instruction.set_atomic_ordering(AtomicOrdering::Release).is_ok());
+    assert!(load_instruction.set_atomic_ordering(AtomicOrdering::Acquire).is_ok());
+
+    assert!(store_instruction.set_atomic_ordering(AtomicOrdering::Acquire).is_err());
+    assert!(store_instruction.set_atomic_ordering(AtomicOrdering::AcquireRelease).is_err());
+    assert!(load_instruction.set_atomic_ordering(AtomicOrdering::AcquireRelease).is_err());
+    assert!(load_instruction.set_atomic_ordering(AtomicOrdering::Release).is_err());
+
     let fadd_instruction = builder.build_float_add(load.into_float_value(), f32_val, "").as_instruction_value().unwrap();
     assert!(fadd_instruction.get_volatile().is_err());
     assert!(fadd_instruction.set_volatile(false).is_err());
     assert!(fadd_instruction.get_alignment().is_err());
     assert!(fadd_instruction.set_alignment(16).is_err());
+    assert!(fadd_instruction.get_atomic_ordering().is_err());
+    assert!(fadd_instruction.set_atomic_ordering(AtomicOrdering::NotAtomic).is_err());
 }