Skip to content

Commit 286bbff

Browse files
committed
Add regression tests for the right shifting behaviour of the new SMT backend
1 parent 88ab75c commit 286bbff

File tree

2 files changed

+37
-0
lines changed

2 files changed

+37
-0
lines changed
Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
int main()
2+
{
3+
// In C, whether a right-shift is arithmetic or logical depends on the
4+
// original type being shifted. An unsigned value will be shifted to
5+
// the right in a logical manner (this assigns `0` to the leftmost bit).
6+
// If the type is signed, right shift will assign the sign bit to the
7+
// leftmost digit.
8+
9+
int bitmask_2 = 0x2;
10+
int bitmask_3 = 0x3;
11+
12+
int first;
13+
unsigned int second;
14+
15+
int place;
16+
__CPROVER_assume(place >= 1);
17+
18+
int result_signed = first >> place;
19+
unsigned int result_unsigned = second >> place;
20+
21+
__CPROVER_assert(result_signed && bitmask_2, "This should be satisfiable");
22+
__CPROVER_assert(
23+
result_unsigned && bitmask_3, "This should also be satisfiable");
24+
}
Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
CORE
2+
shift_right.c
3+
--incremental-smt2-solver 'z3 --smt2 -in' --slice-formula
4+
\[main\.assertion\.1\] line \d+ This should be satisfiable: FAILURE
5+
\[main\.assertion\.2\] line \d+ This should also be satisfiable: FAILURE
6+
^EXIT=10$
7+
^SIGNAL=0$
8+
--
9+
--
10+
The assertions in the C file for this test are designed to be satisfiable,
11+
by certain results that we get back from the solver. This is so that we can
12+
test the driving of the new SMT backend, and to make sure we do get results
13+
back that are the result of a verification run.

0 commit comments

Comments
 (0)