h33: rebuild variant

Former-commit-id: 63de8e0

Author: facchinm

variants/PORTENTA_H33/includes/ra/fsp/inc/instances/r_canfd.h

@@ -324,6 +324,7 @@ typedef struct st_canfd_extended_cfg
     can_bit_timing_cfg_t * p_data_timing;      ///< FD Data Rate (when bitrate switching is used)
     uint8_t                delay_compensation; ///< FD Transceiver Delay Compensation (enable or disable)
     canfd_global_cfg_t   * p_global_cfg;       ///< Global configuration (global error callback channel only)
+    uint32_t               global_err_channel;
 } canfd_extended_cfg_t;
 
 /**********************************************************************************************************************

variants/PORTENTA_H33/includes/ra_cfg/fsp_cfg/r_canfd_cfg.h

@@ -7,7 +7,7 @@
 
 /* Buffer RAM used: 320 bytes */
 
-#define CANFD_CFG_PARAM_CHECKING_ENABLE   ((1))
+#define CANFD_CFG_PARAM_CHECKING_ENABLE   ((BSP_CFG_PARAM_CHECKING_ENABLE))
 
 #define CANFD_CFG_AFL_CH0_RULE_NUM   (32)
 #define CANFD_CFG_AFL_CH1_RULE_NUM   (0)

variants/PORTENTA_H33/includes/ra_gen/bsp_clock_cfg.h

@@ -12,7 +12,7 @@
 #define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
 #define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL2 Mul x20.0 */
 #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
-#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* CLKOUT Src: HOCO */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
 #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
 #define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
 #define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* CANFDCLK Src: XTAL */

variants/PORTENTA_H33/libs/libfsp.a.REMOVED.git-id

@@ -1 +1 @@
-699cac7a47bdcf6ccac8a8a319d2ec6a06291de7
+ffcfdd8d4197bb105a38a36a52f312037985ac15