Missing IPCC enable for C2 in several examples from stm32CubeWB

This fix is coming from
STMicroelectronics/STM32CubeWB#19

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

src/utility/STM32Cube_FW/hw_ipcc.c

@@ -94,6 +94,12 @@ void IPCC_C1_TX_IRQHandler(void)
  ******************************************************************************/
 void HW_IPCC_Enable(void)
 {
+  /**
+  * Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running
+    when FUS is running on CPU2 and CPU1 enters deep sleep mode
+  */
+  LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC);
+
   /**
    * When the device is out of standby, it is required to use the EXTI mechanism to wakeup CPU2
    */