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ryanmkurtzryanmkurtz
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Merge remote-tracking branch 'origin/patch'
2 parents bc24351 + 3d5f8a5 commit f755681

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4 files changed

+39
-24
lines changed

4 files changed

+39
-24
lines changed

‎Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -4483,13 +4483,14 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; }
44834483

44844484
:strex^ItCond Rd0811,Rt1215,[Rn0003,Immed8_4] is TMode=1 & ItCond & op4=0xe84 & Rn0003; Rt1215 & Rd0811 & Immed8_4
44854485
{
4486-
build ItCond;
4486+
build ItCond;
44874487
local tmp = Rn0003 + Immed8_4;
4488+
local tmpRt = Rt1215;
44884489
access:1 = hasExclusiveAccess(tmp);
44894490
Rd0811 = 1;
44904491
if (!access) goto inst_next;
44914492
Rd0811 = 0;
4492-
*tmp = Rt1215;
4493+
*tmp = tmpRt;
44934494
}
44944495

44954496
@endif # VERSION_6T2 || VERSION_7
@@ -4498,39 +4499,41 @@ thumbEndianNess: "BE" is op0=0xb658 { export 1:1; }
44984499

44994500
:strexb^ItCond Rd0003,Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=4 & Rd0003
45004501
{
4501-
build ItCond;
4502+
build ItCond;
45024503
local tmp = Rn0003;
4504+
local tmpRt = Rt1215;
45034505
access:1 = hasExclusiveAccess(tmp);
45044506
Rd0003 = 1;
45054507
if (!access) goto inst_next;
45064508
Rd0003 = 0;
4507-
local tmpRt1215 = Rt1215;
4508-
*tmp = tmpRt1215:1;
4509+
*tmp = tmpRt:1;
45094510
}
45104511

45114512
:strexh^ItCond Rd0003,Rt1215,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & thc0811=15 & thc0407=5 & Rd0003
45124513
{
4513-
build ItCond;
4514+
build ItCond;
45144515
local tmp = Rn0003;
4516+
local tmpRt = Rt1215;
45154517
access:1 = hasExclusiveAccess(tmp);
45164518
Rd0003 = 1;
45174519
if (!access) goto inst_next;
45184520
Rd0003 = 0;
4519-
local tmpRt1215 = Rt1215;
4520-
*tmp = tmpRt1215:1;
4521+
*tmp = tmpRt:2;
45214522
}
45224523

45234524
:strexd^ItCond Rd0003,Rt1215,Rt0811,[Rn0003] is TMode=1 & ItCond & op4=0xe8c & Rn0003; Rt1215 & Rt0811 & thc0407=7 & Rd0003
45244525
{
45254526
build ItCond;
45264527
local tmp = Rn0003;
4528+
local tmpRt = Rt1215;
4529+
local tmpRt2 = Rt0811;
45274530
access:1 = hasExclusiveAccess(tmp);
45284531
Rd0003 = 1;
45294532
if (!access) goto inst_next;
45304533
Rd0003 = 0;
4531-
*tmp = Rt1215;
4534+
*tmp = tmpRt;
45324535
tmp = tmp + 4;
4533-
*tmp = Rt0811;
4536+
*tmp = tmpRt2;
45344537
}
45354538

45364539
@endif # VERSION_7

‎Ghidra/Processors/ARM/data/languages/ARMinstructions.sinc

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5502,11 +5502,12 @@ armEndianNess: "BE" is c0031=0xf1010200 { export 1:1; }
55025502
{
55035503
build COND;
55045504
local tmp = Rn;
5505+
local tmpRm = Rm;
55055506
access:1 = hasExclusiveAccess(tmp);
55065507
Rd = 1;
55075508
if (!access) goto inst_next;
55085509
Rd = 0;
5509-
*tmp = Rm;
5510+
*tmp = tmpRm;
55105511
}
55115512

55125513
@endif # VERSION_6
@@ -5517,36 +5518,38 @@ armEndianNess: "BE" is c0031=0xf1010200 { export 1:1; }
55175518
{
55185519
build COND;
55195520
local tmp = Rn;
5520-
access:1 = hasExclusiveAccess(tmp);
5521-
Rd = 1;
5522-
if (!access) goto inst_next;
5523-
Rd = 0;
5524-
local tmpRm = Rm;
5525-
*tmp = tmpRm:1;
5521+
local tmpRm = Rm;
5522+
access:1 = hasExclusiveAccess(tmp);
5523+
Rd = 1;
5524+
if (!access) goto inst_next;
5525+
Rd = 0;
5526+
*tmp = tmpRm:1;
55265527
}
55275528

55285529
:strexd^COND Rd,Rm,Rm2,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1a & Rn & Rd & c0411=0xf9 & c0003 & Rm & Rm2
55295530
{
55305531
build COND;
55315532
local addr = Rn;
5533+
local tmpRm = Rm;
5534+
local tmpRm2 = Rm2;
55325535
access:1 = hasExclusiveAccess(addr);
55335536
Rd = 1;
55345537
if (!access) goto inst_next;
55355538
Rd = 0;
5536-
*(addr) = Rm;
5539+
*(addr) = tmpRm;
55375540
addr = addr + 4;
5538-
*(addr) = Rm2;
5541+
*(addr) = tmpRm2;
55395542
}
55405543

55415544
:strexh^COND Rd,Rm,[Rn] is $(AMODE) & ARMcond=1 & COND & c2027=0x1e & c0411=0xf9 & Rn & Rd & Rm
55425545
{
55435546
build COND;
55445547
local tmp = Rn;
5548+
local tmpRm = Rm;
55455549
access:1 = hasExclusiveAccess(tmp);
55465550
Rd = 1;
55475551
if (!access) goto inst_next;
55485552
Rd = 0;
5549-
local tmpRm = Rm;
55505553
*tmp = tmpRm:2;
55515554
}
55525555

‎Ghidra/Processors/MC6800/data/languages/6x09.sinc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -504,6 +504,7 @@ macro clear(op)
504504
op = 0;
505505
$(Z) = 1;
506506
$(N) = 0;
507+
$(C) = 0;
507508
}
508509

509510
macro addition(reg, op)

‎Ghidra/Processors/Z80/data/languages/z80.slaspec

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -111,6 +111,14 @@ macro additionFlags(operand1, operand2) {
111111
$(C_flag) = carry(operand1, operand2);
112112
}
113113

114+
macro additionFlagsNoC(operand1, operand2) {
115+
local AFmask = -1 >> 4;
116+
$(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;
117+
$(PV_flag) = scarry(operand1, operand2);
118+
$(N_flag) = 0;
119+
# $(C_flag) is not affected
120+
}
121+
114122
macro additionFlagsNoPV(operand1, operand2) {
115123
local AFmask = -1 >> 4;
116124
$(H_flag) = (((operand1 & AFmask) + (operand2 & AFmask)) & (AFmask + 1)) != 0;
@@ -1021,7 +1029,7 @@ cc2: "C" is bits3_3=0x7 { c:1 = $(C_flag); export c; }
10211029

10221030
reg3_3 = reg3_3 + 1;
10231031
setResultFlags(reg3_3);
1024-
additionFlags(r_temp, 1);
1032+
additionFlagsNoC(r_temp, 1);
10251033
}
10261034

10271035
:INC (HL) is op0_8=0x34 & HL {
@@ -1032,7 +1040,7 @@ cc2: "C" is bits3_3=0x7 { c:1 = $(C_flag); export c; }
10321040
val = val + 1;
10331041
MemStore(HL,val);
10341042
setResultFlags(val);
1035-
additionFlags(val_temp, 1);
1043+
additionFlagsNoC(val_temp, 1);
10361044
}
10371045

10381046
:INC ixMem8 is op0_8=0xdd; op0_8=0x34; ixMem8 {
@@ -1042,7 +1050,7 @@ cc2: "C" is bits3_3=0x7 { c:1 = $(C_flag); export c; }
10421050
val = val + 1;
10431051
ixMem8 = val;
10441052
setResultFlags(val);
1045-
additionFlags(val_temp, 1);
1053+
additionFlagsNoC(val_temp, 1);
10461054
}
10471055

10481056
:INC iyMem8 is op0_8=0xfd; op0_8=0x34; iyMem8 {
@@ -1052,7 +1060,7 @@ cc2: "C" is bits3_3=0x7 { c:1 = $(C_flag); export c; }
10521060
val = val + 1;
10531061
iyMem8 = val;
10541062
setResultFlags(val);
1055-
additionFlags(val_temp, 1);
1063+
additionFlagsNoC(val_temp, 1);
10561064
}
10571065

10581066
:DEC reg3_3 is op6_2=0x0 & reg3_3 & bits0_3=0x5 {

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