GT-3232: Corrected PowerPC VLE bit generation for several instructions

GhidorahRex · GhidorahRex · commit dba454d348ad · 2019-10-10T10:05:55.000-04:00
diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc
@@ -541,7 +541,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 }
 
 :se_btsti RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {
-	tmp:$(REGISTER_SIZE) = (RX_VLE >> OIM5_VLE) & 0x1;
+	tmp:$(REGISTER_SIZE) = (RX_VLE >> (0x1F - OIM5_VLE)) & 0x1;
 	cr0flags(tmp);
 }
 
@@ -709,13 +709,13 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 }
 
 :se_bclri RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {
-	tmp:$(REGISTER_SIZE) = 1 << OIM5_VLE;
+	tmp:$(REGISTER_SIZE) =  0x80000000 >> OIM5_VLE;
 	tmp = ~tmp;
 	RX_VLE = RX_VLE & tmp;
 }
 
 :se_bgeni RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {
-	RX_VLE = 1 << OIM5_VLE;
+	RX_VLE = 0x80000000 >> OIM5_VLE;
 }
 
 :se_bmaski RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=11 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {
@@ -726,7 +726,7 @@ IMM16B: val						is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
 }
 
 :se_bseti RX_VLE,OIM5_VLE		is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {
-	tmp:$(REGISTER_SIZE) = 1 << OIM5_VLE;
+	tmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE;
 	RX_VLE = RX_VLE | tmp;	
 }
 

Original file line number	Diff line number	Diff line change
`@@ -541,7 +541,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) \|`
`541`	`541`	`}`
`542`	`542`
`543`	`543`	`:se_btsti RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {`
`544`		`- tmp:$(REGISTER_SIZE) = (RX_VLE >> OIM5_VLE) & 0x1;`
	`544`	`+ tmp:$(REGISTER_SIZE) = (RX_VLE >> (0x1F - OIM5_VLE)) & 0x1;`
`545`	`545`	`cr0flags(tmp);`
`546`	`546`	`}`
`547`	`547`
`@@ -709,13 +709,13 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) \|`
`709`	`709`	`}`
`710`	`710`
`711`	`711`	`:se_bclri RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {`
`712`		`- tmp:$(REGISTER_SIZE) = 1 << OIM5_VLE;`
	`712`	`+ tmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE;`
`713`	`713`	`tmp = ~tmp;`
`714`	`714`	`RX_VLE = RX_VLE & tmp;`
`715`	`715`	`}`
`716`	`716`
`717`	`717`	`:se_bgeni RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=24 & BIT9_VLE=1 & RX_VLE & OIM5_VLE {`
`718`		`- RX_VLE = 1 << OIM5_VLE;`
	`718`	`+ RX_VLE = 0x80000000 >> OIM5_VLE;`
`719`	`719`	`}`
`720`	`720`
`721`	`721`	`:se_bmaski RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=11 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {`
`@@ -726,7 +726,7 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) \|`
`726`	`726`	`}`
`727`	`727`
`728`	`728`	`:se_bseti RX_VLE,OIM5_VLE is $(ISVLE) & OP6_VLE=25 & BIT9_VLE=0 & RX_VLE & OIM5_VLE {`
`729`		`- tmp:$(REGISTER_SIZE) = 1 << OIM5_VLE;`
	`729`	`+ tmp:$(REGISTER_SIZE) = 0x80000000 >> OIM5_VLE;`
`730`	`730`	`RX_VLE = RX_VLE \| tmp;`
`731`	`731`	`}`
`732`	`732`