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ryanmkurtzryanmkurtz
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Merge remote-tracking branch 'origin/GP-1262_Dan_backport-GP-1185' into patch
2 parents dbae8f3 + 73d3647 commit 763381a

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6 files changed

+404
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‎Ghidra/Processors/x86/data/languages/avx.sinc

Lines changed: 0 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1224,36 +1224,6 @@ define pcodeop vmovddup_avx ;
12241224
# TODO ZmmReg1 = zext(YmmReg1)
12251225
}
12261226

1227-
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61667
1228-
define pcodeop vmovdqa_avx ;
1229-
:VMOVDQA XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
1230-
{
1231-
local tmp:16 = vmovdqa_avx( XmmReg2_m128 );
1232-
YmmReg1 = zext(tmp);
1233-
# TODO ZmmReg1 = zext(XmmReg1)
1234-
}
1235-
1236-
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669
1237-
:VMOVDQA XmmReg2_m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 ... & XmmReg2_m128
1238-
{
1239-
XmmReg2_m128 = vmovdqa_avx( XmmReg1 );
1240-
# TODO ZmmReg2 = zext(XmmReg2)
1241-
}
1242-
1243-
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61671
1244-
:VMOVDQA YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; YmmReg1 ... & YmmReg2_m256
1245-
{
1246-
YmmReg1 = vmovdqa_avx( YmmReg2_m256 );
1247-
# TODO ZmmReg1 = zext(YmmReg1)
1248-
}
1249-
1250-
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61673
1251-
:VMOVDQA YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & YmmReg2_m256
1252-
{
1253-
YmmReg2_m256 = vmovdqa_avx( YmmReg1 );
1254-
# TODO ZmmReg2 = zext(YmmReg2)
1255-
}
1256-
12571227
# MOVDQU,VMOVDQU8/16/32/64 4-67 PAGE 1187 LINE 61930
12581228
define pcodeop vmovdqu_avx ;
12591229
:VMOVDQU XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_F3) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
@@ -1891,15 +1861,6 @@ define pcodeop vpcmpeqd_avx ;
18911861
# TODO ZmmReg1 = zext(XmmReg1)
18921862
}
18931863

1894-
# PCMPEQQ 4-250 PAGE 1370 LINE 71169
1895-
define pcodeop vpcmpeqq_avx ;
1896-
:VPCMPEQQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x29; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
1897-
{
1898-
local tmp:16 = vpcmpeqq_avx( vexVVVV_XmmReg, XmmReg2_m128 );
1899-
YmmReg1 = zext(tmp);
1900-
# TODO ZmmReg1 = zext(XmmReg1)
1901-
}
1902-
19031864
# PCMPESTRI 4-253 PAGE 1373 LINE 71311
19041865
define pcodeop vpcmpestri_avx ;
19051866
:VPCMPESTRI XmmReg1, XmmReg2_m128, imm8 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F3A); byte=0x61; XmmReg1 ... & XmmReg2_m128; imm8
@@ -2234,14 +2195,6 @@ define pcodeop vpminud_avx ;
22342195
# TODO ZmmReg1 = zext(XmmReg1)
22352196
}
22362197

2237-
# PMOVMSKB 4-338 PAGE 1458 LINE 75651
2238-
define pcodeop vpmovmskb_avx ;
2239-
:VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2)
2240-
{
2241-
Reg32 = vpmovmskb_avx( XmmReg2 );
2242-
# TODO Reg64 = zext(Reg32)
2243-
}
2244-
22452198
# PMOVSX 4-340 PAGE 1460 LINE 75770
22462199
define pcodeop vpmovsxbw_avx ;
22472200
:VPMOVSXBW XmmReg1, XmmReg2_m64 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; (XmmReg1 & YmmReg1) ... & XmmReg2_m64

‎Ghidra/Processors/x86/data/languages/avx2.sinc

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -218,14 +218,6 @@ define pcodeop vpcmpeqd_avx2 ;
218218
# TODO ZmmReg1 = zext(YmmReg1)
219219
}
220220

221-
# PCMPEQQ 4-250 PAGE 1370 LINE 71171
222-
define pcodeop vpcmpeqq_avx2 ;
223-
:VPCMPEQQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x29; YmmReg1 ... & YmmReg2_m256
224-
{
225-
YmmReg1 = vpcmpeqq_avx2( vexVVVV_YmmReg, YmmReg2_m256 );
226-
# TODO ZmmReg1 = zext(YmmReg1)
227-
}
228-
229221
# PCMPGTB/PCMPGTW/PCMPGTD 4-257 PAGE 1377 LINE 71508
230222
define pcodeop vpcmpgtb_avx2 ;
231223
:VPCMPGTB YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x64; YmmReg1 ... & YmmReg2_m256
@@ -418,14 +410,6 @@ define pcodeop vpminud_avx2 ;
418410
# TODO ZmmReg1 = zext(YmmReg1)
419411
}
420412

421-
# PMOVMSKB 4-338 PAGE 1458 LINE 75655
422-
define pcodeop vpmovmskb_avx2 ;
423-
:VPMOVMSKB Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & YmmReg2)
424-
{
425-
Reg32 = vpmovmskb_avx2( YmmReg2 );
426-
# TODO Reg64 = zext(Reg32)
427-
}
428-
429413
# PMOVSX 4-340 PAGE 1460 LINE 75782
430414
define pcodeop vpmovsxbw_avx2 ;
431415
:VPMOVSXBW YmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG); byte=0x20; YmmReg1 ... & XmmReg2_m128

‎Ghidra/Processors/x86/data/languages/avx2_manual.sinc

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,15 @@ define pcodeop vgatherqps ;
109109
}
110110
@endif
111111

112+
# PCMPEQQ 4-250 PAGE 1370 LINE 71171
113+
:VPCMPEQQ YmmReg1, vexVVVV_YmmReg, YmmReg2_m256 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_YmmReg; byte=0x29; YmmReg1 ... & YmmReg2_m256
114+
{
115+
YmmReg1[0,64] = zext(vexVVVV_YmmReg[0,64] == YmmReg2_m256[0,64]) * 0xffffffffffffffff:8;
116+
YmmReg1[64,64] = zext(vexVVVV_YmmReg[64,64] == YmmReg2_m256[64,64]) * 0xffffffffffffffff:8;
117+
YmmReg1[128,64] = zext(vexVVVV_YmmReg[128,64] == YmmReg2_m256[128,64]) * 0xffffffffffffffff:8;
118+
YmmReg1[192,64] = zext(vexVVVV_YmmReg[192,64] == YmmReg2_m256[192,64]) * 0xffffffffffffffff:8;
119+
# TODO ZmmReg1 = zext(YmmReg1)
120+
}
112121

113122
# VPGATHERDD/VPGATHERQD 5-273 PAGE 2097 LINE 107884
114123
define pcodeop vpgatherdd ;
@@ -201,3 +210,43 @@ define pcodeop vpgatherqq ;
201210
@endif
202211

203212

213+
# PMOVMSKB 4-338 PAGE 1458 LINE 75655
214+
:VPMOVMSKB Reg32, YmmReg2 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & YmmReg2) & check_Reg32_dest
215+
{
216+
local byte_mask:4 = 0:4;
217+
byte_mask[0,1] = YmmReg2[7,1];
218+
byte_mask[1,1] = YmmReg2[15,1];
219+
byte_mask[2,1] = YmmReg2[23,1];
220+
byte_mask[3,1] = YmmReg2[31,1];
221+
byte_mask[4,1] = YmmReg2[39,1];
222+
byte_mask[5,1] = YmmReg2[47,1];
223+
byte_mask[6,1] = YmmReg2[55,1];
224+
byte_mask[7,1] = YmmReg2[63,1];
225+
byte_mask[8,1] = YmmReg2[71,1];
226+
byte_mask[9,1] = YmmReg2[79,1];
227+
byte_mask[10,1] = YmmReg2[87,1];
228+
byte_mask[11,1] = YmmReg2[95,1];
229+
byte_mask[12,1] = YmmReg2[103,1];
230+
byte_mask[13,1] = YmmReg2[111,1];
231+
byte_mask[14,1] = YmmReg2[119,1];
232+
byte_mask[15,1] = YmmReg2[127,1];
233+
byte_mask[16,1] = YmmReg2[135,1];
234+
byte_mask[17,1] = YmmReg2[143,1];
235+
byte_mask[18,1] = YmmReg2[151,1];
236+
byte_mask[19,1] = YmmReg2[159,1];
237+
byte_mask[20,1] = YmmReg2[167,1];
238+
byte_mask[21,1] = YmmReg2[175,1];
239+
byte_mask[22,1] = YmmReg2[183,1];
240+
byte_mask[23,1] = YmmReg2[191,1];
241+
byte_mask[24,1] = YmmReg2[199,1];
242+
byte_mask[25,1] = YmmReg2[207,1];
243+
byte_mask[26,1] = YmmReg2[215,1];
244+
byte_mask[27,1] = YmmReg2[223,1];
245+
byte_mask[28,1] = YmmReg2[231,1];
246+
byte_mask[29,1] = YmmReg2[239,1];
247+
byte_mask[30,1] = YmmReg2[247,1];
248+
byte_mask[31,1] = YmmReg2[255,1];
249+
Reg32 = zext(byte_mask);
250+
build check_Reg32_dest;
251+
}
252+

‎Ghidra/Processors/x86/data/languages/avx_manual.sinc

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,39 @@
1+
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61667
2+
# Note: we do not model the exception generated if VMOVDQA is used with a memory operand which is not 16-bye aligned
3+
:VMOVDQA XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
4+
{
5+
YmmReg1 = zext(XmmReg2_m128);
6+
# TODO ZmmReg1 = zext(XmmReg1)
7+
}
8+
9+
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669
10+
:VMOVDQA XmmReg2, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 & (mod = 3 & XmmReg2 & YmmReg2)
11+
{
12+
YmmReg2 = zext(XmmReg1);
13+
# TODO ZmmReg2 = zext(XmmReg2)
14+
}
15+
16+
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61669
17+
:VMOVDQA m128, XmmReg1 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; XmmReg1 ... & m128
18+
{
19+
m128 = XmmReg1;
20+
# TODO ZmmReg2 = zext(XmmReg2)
21+
}
22+
23+
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61671
24+
:VMOVDQA YmmReg1, YmmReg2_m256 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x6F; YmmReg1 ... & YmmReg2_m256
25+
{
26+
YmmReg1 = YmmReg2_m256;
27+
# TODO ZmmReg1 = zext(YmmReg1)
28+
}
29+
30+
# MOVDQA,VMOVDQA32/64 4-62 PAGE 1182 LINE 61673
31+
:VMOVDQA YmmReg2_m256, YmmReg1 is $(VEX_NONE) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0x7F; YmmReg1 ... & YmmReg2_m256
32+
{
33+
YmmReg2_m256 = YmmReg1;
34+
# TODO ZmmReg2 = zext(YmmReg2)
35+
}
36+
137
# MOVSD 4-111 PAGE 1231 LINE 63970
238
:VMOVSD XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; XmmReg1 & YmmReg1 & (mod=0x3 & XmmReg2)
339
{
@@ -70,3 +106,40 @@
70106
{
71107
YmmReg2_m256 = YmmReg1;
72108
}
109+
110+
# PCMPEQQ 4-250 PAGE 1370 LINE 71169
111+
:VPCMPEQQ XmmReg1, vexVVVV_XmmReg, XmmReg2_m128 is $(VEX_NDS) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F38) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x29; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
112+
{
113+
XmmReg1[0,64] = zext(vexVVVV_XmmReg[0,64] == XmmReg2_m128[0,64]) * 0xffffffffffffffff:8;
114+
XmmReg1[64,64] = zext(vexVVVV_XmmReg[64,64] == XmmReg2_m128[64,64]) * 0xffffffffffffffff:8;
115+
YmmReg1 = zext(XmmReg1);
116+
# TODO ZmmReg1 = zext(XmmReg1)
117+
}
118+
119+
120+
# PMOVMSKB 4-338 PAGE 1458 LINE 75651
121+
:VPMOVMSKB Reg32, XmmReg2 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_66) & $(VEX_0F) & $(VEX_WIG); byte=0xD7; Reg32 & (mod=0x3 & XmmReg2) & check_Reg32_dest
122+
{
123+
local byte_mask:2 = 0:2;
124+
byte_mask[0,1] = XmmReg2[7,1];
125+
byte_mask[1,1] = XmmReg2[15,1];
126+
byte_mask[2,1] = XmmReg2[23,1];
127+
byte_mask[3,1] = XmmReg2[31,1];
128+
byte_mask[4,1] = XmmReg2[39,1];
129+
byte_mask[5,1] = XmmReg2[47,1];
130+
byte_mask[6,1] = XmmReg2[55,1];
131+
byte_mask[7,1] = XmmReg2[63,1];
132+
byte_mask[8,1] = XmmReg2[71,1];
133+
byte_mask[9,1] = XmmReg2[79,1];
134+
byte_mask[10,1] = XmmReg2[87,1];
135+
byte_mask[11,1] = XmmReg2[95,1];
136+
byte_mask[12,1] = XmmReg2[103,1];
137+
byte_mask[13,1] = XmmReg2[111,1];
138+
byte_mask[14,1] = XmmReg2[119,1];
139+
byte_mask[15,1] = XmmReg2[127,1];
140+
Reg32 = zext(byte_mask);
141+
build check_Reg32_dest;
142+
}
143+
144+
145+

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