Merge remote-tracking branch 'origin/caheckman_sleighx86vector'

Author: ryanmkurtz

Ghidra/Processors/x86/data/languages/avx2_manual.sinc

@@ -1,20 +1,20 @@
 # VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4 5-314 PAGE 2138 LINE 109785
 define pcodeop vinserti128 ;
-:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg & vexVVVV_YmmReg_DQa & vexVVVV_YmmReg_DQb; byte=0x38; (YmmReg1 & YmmReg1_DQa & YmmReg1_DQb) ... & XmmReg2_m128; imm8 & imm8_0 {
+:VINSERTI128 YmmReg1, vexVVVV_YmmReg, XmmReg2_m128, imm8 is $(VEX_NDS) & $(VEX_L256) & $(VEX_PRE_66) & $(VEX_0F3A) & $(VEX_W0) & vexVVVV_YmmReg; byte=0x38; YmmReg1 ... & XmmReg2_m128; imm8 & imm8_0 {
 	local tmp:16 = XmmReg2_m128;
 
 	# ignoring all but the least significant bit
 	if (imm8_0:1 == 0) goto <case0>;
 	if (imm8_0:1 == 1) goto <case1>;
 
  <case0>
-	YmmReg1_DQa = tmp;
-	YmmReg1_DQb = vexVVVV_YmmReg_DQb;
+	YmmReg1[0,128] = tmp;
+	YmmReg1[128,128] = vexVVVV_YmmReg[128,128];
 	goto <done>;
 
  <case1>
-	YmmReg1_DQa = vexVVVV_YmmReg_DQa;
-	YmmReg1_DQb = tmp;
+	YmmReg1[0,128] = vexVVVV_YmmReg[0,128];
+	YmmReg1[128,128] = tmp;
 
  <done>
 }

Ghidra/Processors/x86/data/languages/avx_manual.sinc

@@ -1,44 +1,46 @@
 # MOVSD 4-111 PAGE 1231 LINE 63970
-:VMOVSD XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg & vexVVVV_XmmReg_Qb; byte=0x10; (XmmReg1 & XmmReg1_Qa & XmmReg1_Qb & YmmReg1) & (mod=0x3 & XmmReg2 & XmmReg2_Qa)
+:VMOVSD XmmReg1, vexVVVV_XmmReg, XmmReg2 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x10; XmmReg1 & YmmReg1 & (mod=0x3 & XmmReg2)
 {
-	local tmpa:8 = XmmReg2_Qa;
-	local tmpb:8 = vexVVVV_XmmReg_Qb;
+	local tmpa:8 = XmmReg2[0,64];
+	local tmpb:8 = vexVVVV_XmmReg[64,64];
 	YmmReg1 = 0;
-	XmmReg1_Qa = tmpa;
-	XmmReg1_Qb = tmpb;
+	XmmReg1[0,64] = tmpa;
+	XmmReg1[64,64] = tmpb;
 	# TODO ZmmReg1 = zext(XmmReg1)
 }
 
 # MOVSD 4-111 PAGE 1231 LINE 63972
 :VMOVSD XmmReg1, m64 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & m64
 {
-	local tmp:16 = zext(m64);
-	YmmReg1 = zext(tmp);
+	YmmReg1[0,64] = m64;
+	YmmReg1[64,64] = 0;
 	# TODO ZmmReg1 = zext(XmmReg1)
 }
 
 # MOVSD 4-111 PAGE 1231 LINE 63974
-:VMOVSD XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg & vexVVVV_XmmReg_Qb; byte=0x11; XmmReg1 & XmmReg1_Qa & (mod=0x3 & (XmmReg2 & XmmReg2_Qa & XmmReg2_Qb & YmmReg2))
+:VMOVSD XmmReg2, vexVVVV_XmmReg, XmmReg1 is $(VEX_NDS) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG) & vexVVVV_XmmReg; byte=0x11; XmmReg1 & (mod=0x3 & (XmmReg2 & YmmReg2))
 {
-	local tmpa:8 = XmmReg1_Qa;
-	local tmpb:8 = vexVVVV_XmmReg_Qb;
+	local tmpa:8 = XmmReg1[0,64];
+	local tmpb:8 = vexVVVV_XmmReg[64,64];
 	YmmReg2 = 0;
-	XmmReg2_Qa = tmpa;
-	XmmReg2_Qb = tmpb;
+	XmmReg2[0,64] = tmpa;
+	XmmReg2[64,64] = tmpb;
 	# TODO ZmmReg2 = zext(XmmReg2)
 }
 
 # MOVSD 4-111 PAGE 1231 LINE 63976
-:VMOVSD m64, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x11; (XmmReg1 & XmmReg1_Qa) ... & m64
+:VMOVSD m64, XmmReg1 is $(VEX_NONE) & $(VEX_LIG) & $(VEX_PRE_F2) & $(VEX_0F) & $(VEX_WIG); byte=0x11; XmmReg1 ... & m64
 {
-	m64 = XmmReg1_Qa;
+	m64 = XmmReg1[0,64];
 }
 
 # MOVUPS 4-130 PAGE 1250 LINE 64872
 :VMOVUPS XmmReg1, XmmReg2_m128 is $(VEX_NONE) & $(VEX_L128) & $(VEX_PRE_NONE) & $(VEX_0F) & $(VEX_WIG); byte=0x10; (XmmReg1 & YmmReg1) ... & XmmReg2_m128
 {
 	local tmp:16 = XmmReg2_m128;
-	YmmReg1 = zext(tmp);
+	YmmReg1[0,128] = tmp;
+	YmmReg1[128,64] = 0;
+	YmmReg1[192,64] = 0;
 }
 
 # MOVUPS 4-130 PAGE 1250 LINE 64874