Skip to content

Commit 08a2571

Browse files
ryanmkurtzryanmkurtz
committed
Merge remote-tracking branch 'origin/GP-3733_ghidracadabra_PR-5208_jobermayr_fxsave'
2 parents 1d16c0c + 56d2d08 commit 08a2571

File tree

1 file changed

+20
-215
lines changed
  • Ghidra/Processors/x86/data/languages

1 file changed

+20
-215
lines changed

‎Ghidra/Processors/x86/data/languages/ia.sinc

Lines changed: 20 additions & 215 deletions
Original file line numberDiff line numberDiff line change
@@ -4436,240 +4436,45 @@ define pcodeop fsin;
44364436
:FXCH freg is vexMode=0 & byte=0xD9; frow=12 & fpage=1 & freg { local tmp = ST0; ST0 = freg; freg = tmp; }
44374437
:FXCH is vexMode=0 & byte=0xD9; byte=0xC9 { local tmp = ST0; ST0 = ST1; ST1 = tmp; }
44384438

4439-
# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode
4439+
# fxsave and fxrstor
4440+
define pcodeop _fxsave;
4441+
define pcodeop _fxrstor;
4442+
@ifdef IA64
4443+
define pcodeop _fxsave64;
4444+
define pcodeop _fxrstor64;
4445+
@endif
4446+
4447+
# this saves the FPU state into 512 bytes of memory
44404448
:FXSAVE Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem
44414449
{
4442-
# not saved in the same spacing as the actual processor
4443-
*:2 (Mem) = FPUControlWord;
4444-
*:2 (Mem + 2) = FPUStatusWord;
4445-
*:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
4446-
*:2 (Mem + 6) = FPULastInstructionOpcode;
4447-
*:4 (Mem + 8) = FPUInstructionPointer;
4448-
*:2 (Mem + 12) = FPUPointerSelector;
4449-
*:4 (Mem + 16) = FPUDataPointer;
4450-
*:2 (Mem + 20) = FPUDataSelector;
4451-
*:4 (Mem + 24) = MXCSR;
4452-
# MXCSR_MASK not modeled, since it is processor specific, set to 0.
4453-
4454-
# saved the FPU ST registers to the ST/MM area of the structure,
4455-
*:10 (Mem + 32) = ST0;
4456-
*:10 (Mem + 48) = ST1;
4457-
*:10 (Mem + 64) = ST2;
4458-
*:10 (Mem + 80) = ST3;
4459-
*:10 (Mem + 96) = ST4;
4460-
*:10 (Mem + 112) = ST5;
4461-
*:10 (Mem + 128) = ST6;
4462-
*:10 (Mem + 144) = ST7;
4463-
4464-
*:16 (Mem + 160) = XMM0;
4465-
*:16 (Mem + 176) = XMM1;
4466-
*:16 (Mem + 192) = XMM2;
4467-
*:16 (Mem + 208) = XMM3;
4468-
*:16 (Mem + 224) = XMM4;
4469-
*:16 (Mem + 240) = XMM5;
4470-
*:16 (Mem + 256) = XMM6;
4471-
*:16 (Mem + 272) = XMM7;
4450+
_fxsave(Mem);
4451+
}
4452+
4453+
:FXRSTOR Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
4454+
{
4455+
_fxrstor(Mem);
44724456
}
44734457

44744458
@ifdef IA64
44754459
# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode
44764460
:FXSAVE Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem
44774461
{
4478-
*:2 (Mem) = FPUControlWord;
4479-
*:2 (Mem + 2) = FPUStatusWord;
4480-
*:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
4481-
*:2 (Mem + 6) = FPULastInstructionOpcode;
4482-
*:4 (Mem + 8) = FPUInstructionPointer;
4483-
*:2 (Mem + 12) = FPUPointerSelector;
4484-
*:4 (Mem + 16) = FPUDataPointer;
4485-
*:2 (Mem + 20) = FPUDataSelector;
4486-
*:4 (Mem + 24) = MXCSR;
4487-
# MXCSR_MASK not modeled, since it is processor specific, set to 0.
4488-
4489-
4490-
# saved the FPU ST registers to the ST/MM area of the structure,
4491-
*:10 (Mem + 32) = ST0;
4492-
*:10 (Mem + 48) = ST1;
4493-
*:10 (Mem + 64) = ST2;
4494-
*:10 (Mem + 80) = ST3;
4495-
*:10 (Mem + 96) = ST4;
4496-
*:10 (Mem + 112) = ST5;
4497-
*:10 (Mem + 128) = ST6;
4498-
*:10 (Mem + 144) = ST7;
4499-
4500-
*:16 (Mem + 160) = XMM0;
4501-
*:16 (Mem + 176) = XMM1;
4502-
*:16 (Mem + 192) = XMM2;
4503-
*:16 (Mem + 208) = XMM3;
4504-
*:16 (Mem + 224) = XMM4;
4505-
*:16 (Mem + 240) = XMM5;
4506-
*:16 (Mem + 256) = XMM6;
4507-
*:16 (Mem + 272) = XMM7;
4508-
*:16 (Mem + 288) = XMM8;
4509-
*:16 (Mem + 304) = XMM9;
4510-
*:16 (Mem + 320) = XMM10;
4511-
*:16 (Mem + 336) = XMM11;
4512-
*:16 (Mem + 352) = XMM12;
4513-
*:16 (Mem + 368) = XMM13;
4514-
*:16 (Mem + 384) = XMM14;
4515-
*:16 (Mem + 400) = XMM15;
4462+
_fxsave(Mem);
45164463
}
45174464

4518-
# this saves the FPU state into 512 bytes of memory similar to the 32-bit mode
45194465
:FXSAVE64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=0 ) ... & Mem
45204466
{
4521-
*:2 (Mem) = FPUControlWord;
4522-
*:2 (Mem + 2) = FPUStatusWord;
4523-
*:2 (Mem + 4) = FPUTagWord; #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
4524-
*:2 (Mem + 6) = FPULastInstructionOpcode;
4525-
*:8 (Mem + 8) = FPUInstructionPointer;
4526-
*:8 (Mem + 16) = FPUDataPointer;
4527-
*:4 (Mem + 24) = MXCSR;
4528-
# MXCSR_MASK not modeled, since it is processor specific, set to 0.
4529-
4530-
# saved the FPU ST registers to the ST/MM area of the structure,
4531-
*:10 (Mem + 32) = ST0;
4532-
*:10 (Mem + 48) = ST1;
4533-
*:10 (Mem + 64) = ST2;
4534-
*:10 (Mem + 80) = ST3;
4535-
*:10 (Mem + 96) = ST4;
4536-
*:10 (Mem + 112) = ST5;
4537-
*:10 (Mem + 128) = ST6;
4538-
*:10 (Mem + 144) = ST7;
4539-
4540-
4541-
*:16 (Mem + 160) = XMM0;
4542-
*:16 (Mem + 176) = XMM1;
4543-
*:16 (Mem + 192) = XMM2;
4544-
*:16 (Mem + 208) = XMM3;
4545-
*:16 (Mem + 224) = XMM4;
4546-
*:16 (Mem + 240) = XMM5;
4547-
*:16 (Mem + 256) = XMM6;
4548-
*:16 (Mem + 272) = XMM7;
4549-
*:16 (Mem + 288) = XMM8;
4550-
*:16 (Mem + 304) = XMM9;
4551-
*:16 (Mem + 320) = XMM10;
4552-
*:16 (Mem + 336) = XMM11;
4553-
*:16 (Mem + 352) = XMM12;
4554-
*:16 (Mem + 368) = XMM13;
4555-
*:16 (Mem + 384) = XMM14;
4556-
*:16 (Mem + 400) = XMM15;
4467+
_fxsave64(Mem);
45574468
}
4558-
@endif
45594469

4560-
:FXRSTOR Mem is $(LONGMODE_OFF) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
4470+
:FXRSTOR Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
45614471
{
4562-
FPUControlWord = *:2 (Mem);
4563-
FPUStatusWord = *:2 (Mem + 2);
4564-
FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
4565-
FPULastInstructionOpcode = *:2 (Mem + 6);
4566-
FPUInstructionPointer = *:4 (Mem + 8);
4567-
FPUPointerSelector = *:2 (Mem + 12);
4568-
FPUDataPointer = *:4 (Mem + 16);
4569-
FPUDataSelector = *:2 (Mem + 20);
4570-
MXCSR = *:4 (Mem + 24);
4571-
# MXCSR_MASK not modeled, since it is processor specific, set to 0.
4572-
4573-
# saved the FPU ST registers to the ST/MM area of the structure,
4574-
ST0 = *:10 (Mem + 32);
4575-
ST1 = *:10 (Mem + 48);
4576-
ST2 = *:10 (Mem + 64);
4577-
ST3 = *:10 (Mem + 80);
4578-
ST4 = *:10 (Mem + 96);
4579-
ST5 = *:10 (Mem + 112);
4580-
ST6 = *:10 (Mem + 128);
4581-
ST7 = *:10 (Mem + 144);
4582-
4583-
XMM0 = *:16 (Mem + 160);
4584-
XMM1 = *:16 (Mem + 176);
4585-
XMM2 = *:16 (Mem + 192);
4586-
XMM3 = *:16 (Mem + 208);
4587-
XMM4 = *:16 (Mem + 224);
4588-
XMM5 = *:16 (Mem + 240);
4589-
XMM6 = *:16 (Mem + 256);
4590-
XMM7 = *:16 (Mem + 272);
4472+
_fxrstor(Mem);
45914473
}
45924474

4593-
@ifdef IA64
45944475
:FXRSTOR64 Mem is $(LONGMODE_ON) & vexMode=0 & $(REX_W) & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
45954476
{
4596-
FPUControlWord = *:2 (Mem);
4597-
FPUStatusWord = *:2 (Mem + 2);
4598-
FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
4599-
FPULastInstructionOpcode = *:2 (Mem + 6);
4600-
FPUInstructionPointer = *:8 (Mem + 8);
4601-
FPUDataPointer = *:8 (Mem + 16);
4602-
MXCSR = *:4 (Mem + 24);
4603-
# MXCSR_MASK not modeled, since it is processor specific, set to 0.
4604-
4605-
# saved the FPU ST registers to the ST/MM area of the structure,
4606-
ST0 = *:10 (Mem + 32);
4607-
ST1 = *:10 (Mem + 48);
4608-
ST2 = *:10 (Mem + 64);
4609-
ST3 = *:10 (Mem + 80);
4610-
ST4 = *:10 (Mem + 96);
4611-
ST5 = *:10 (Mem + 112);
4612-
ST6 = *:10 (Mem + 128);
4613-
ST7 = *:10 (Mem + 144);
4614-
4615-
XMM0 = *:16 (Mem + 160);
4616-
XMM1 = *:16 (Mem + 176);
4617-
XMM2 = *:16 (Mem + 192);
4618-
XMM3 = *:16 (Mem + 208);
4619-
XMM4 = *:16 (Mem + 224);
4620-
XMM5 = *:16 (Mem + 240);
4621-
XMM6 = *:16 (Mem + 256);
4622-
XMM7 = *:16 (Mem + 272);
4623-
XMM8 = *:16 (Mem + 288);
4624-
XMM9 = *:16 (Mem + 304);
4625-
XMM10 = *:16 (Mem + 320);
4626-
XMM11 = *:16 (Mem + 336);
4627-
XMM12 = *:16 (Mem + 352);
4628-
XMM13 = *:16 (Mem + 368);
4629-
XMM14 = *:16 (Mem + 384);
4630-
XMM15 = *:16 (Mem + 400);
4631-
}
4632-
4633-
:FXRSTOR Mem is $(LONGMODE_ON) & vexMode=0 & byte=0x0F; byte=0xAE; ( mod != 0b11 & reg_opcode=1 ) ... & Mem
4634-
{
4635-
FPUControlWord = *:2 (Mem);
4636-
FPUStatusWord = *:2 (Mem + 2);
4637-
FPUTagWord = *:2 (Mem + 4); #The real implementation saves an 'abridged' tag word, but that is a non-trivial operation
4638-
FPULastInstructionOpcode = *:2 (Mem + 6);
4639-
FPUInstructionPointer = *:4 (Mem + 8);
4640-
FPUPointerSelector = *:2 (Mem + 12);
4641-
FPUDataPointer = *:4 (Mem + 16);
4642-
FPUDataSelector = *:2 (Mem + 20);
4643-
MXCSR = *:4 (Mem + 24);
4644-
# MXCSR_MASK not modeled, since it is processor specific, set to 0.
4645-
4646-
# saved the FPU ST registers to the ST/MM area of the structure,
4647-
ST0 = *:10 (Mem + 32);
4648-
ST1 = *:10 (Mem + 48);
4649-
ST2 = *:10 (Mem + 64);
4650-
ST3 = *:10 (Mem + 80);
4651-
ST4 = *:10 (Mem + 96);
4652-
ST5 = *:10 (Mem + 112);
4653-
ST6 = *:10 (Mem + 128);
4654-
ST7 = *:10 (Mem + 144);
4655-
4656-
4657-
XMM0 = *:16 (Mem + 160);
4658-
XMM1 = *:16 (Mem + 176);
4659-
XMM2 = *:16 (Mem + 192);
4660-
XMM3 = *:16 (Mem + 208);
4661-
XMM4 = *:16 (Mem + 224);
4662-
XMM5 = *:16 (Mem + 240);
4663-
XMM6 = *:16 (Mem + 256);
4664-
XMM7 = *:16 (Mem + 272);
4665-
XMM8 = *:16 (Mem + 288);
4666-
XMM9 = *:16 (Mem + 304);
4667-
XMM10 = *:16 (Mem + 320);
4668-
XMM11 = *:16 (Mem + 336);
4669-
XMM12 = *:16 (Mem + 352);
4670-
XMM13 = *:16 (Mem + 368);
4671-
XMM14 = *:16 (Mem + 384);
4672-
XMM15 = *:16 (Mem + 400);
4477+
_fxrstor64(Mem);
46734478
}
46744479
@endif
46754480

0 commit comments

Comments
 (0)