Fixes the lvalue for movu.b and movu.w

Wesley Ceraso Prudencio · web-flow · commit 077b5788abc6 · 2019-11-21T08:22:52.000-08:00
As with all other mov instructions, the second address is the lvalue, the one to receive the data.
For movu.b and movu.w the first address was receiving its own data.
diff --git a/Ghidra/Processors/SuperH/data/languages/superh.sinc b/Ghidra/Processors/SuperH/data/languages/superh.sinc
@@ -488,15 +488,15 @@ disppc2: @(disp,pc) is disp_00_07 & pc
 :movu.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27
     is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1000 & l_disp_00_11
 {
-    l_rm_20_23 = zext(*:1 (l_disp_00_11 + l_rm_20_23));
+    l_rn_24_27 = zext(*:1 (l_disp_00_11 + l_rm_20_23));
 }
 
 # MOVU.W @(disp12,Rm), Rn 0011nnnnmmmm0001 1001dddddddddddd (disp×2+Rm) → zero extension → Rn
 :movu.w @(disp, l_rm_20_23), l_rn_24_27
     is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1001 & l_disp_00_11
     [ disp = l_disp_00_11 * 2; ]
 {
-    l_rm_20_23 = zext(*:2 (disp + l_rm_20_23));
+    l_rn_24_27 = zext(*:2 (disp + l_rm_20_23));
 }
 
 simm20: "#"value is l_simm20_20_23 & l_imm20_00_15

Original file line number	Diff line number	Diff line change
`@@ -488,15 +488,15 @@ disppc2: @(disp,pc) is disp_00_07 & pc`
`488`	`488`	`:movu.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27`
`489`	`489`	`is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1000 & l_disp_00_11`
`490`	`490`	`{`
`491`		`- l_rm_20_23 = zext(*:1 (l_disp_00_11 + l_rm_20_23));`
	`491`	`+ l_rn_24_27 = zext(*:1 (l_disp_00_11 + l_rm_20_23));`
`492`	`492`	`}`
`493`	`493`
`494`	`494`	`# MOVU.W @(disp12,Rm), Rn 0011nnnnmmmm0001 1001dddddddddddd (disp×2+Rm) → zero extension → Rn`
`495`	`495`	`:movu.w @(disp, l_rm_20_23), l_rn_24_27`
`496`	`496`	`is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1001 & l_disp_00_11`
`497`	`497`	`[ disp = l_disp_00_11 * 2; ]`
`498`	`498`	`{`
`499`		`- l_rm_20_23 = zext(*:2 (disp + l_rm_20_23));`
	`499`	`+ l_rn_24_27 = zext(*:2 (disp + l_rm_20_23));`
`500`	`500`	`}`
`501`	`501`
`502`	`502`	`simm20: "#"value is l_simm20_20_23 & l_imm20_00_15`