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ryanmkurtzryanmkurtz
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Merge remote-tracking branch 'origin/patch'
2 parents cdbf926 + fb2daf5 commit 0123c85

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7 files changed

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7 files changed

+85
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‎Ghidra/Processors/Atmel/certification.manifest

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@@ -34,3 +34,5 @@ data/languages/avr8xmega.pspec||GHIDRA||||END|
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data/languages/avr8xmega.slaspec||GHIDRA||||END|
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data/manuals/AVR32.idx||GHIDRA||||END|
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data/manuals/AVR8.idx||GHIDRA||||END|
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data/patterns/AVR8_patterns.xml||GHIDRA||||END|
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data/patterns/patternconstraints.xml||GHIDRA||||END|

‎Ghidra/Processors/Atmel/data/languages/avr8.ldefs

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@@ -20,21 +20,21 @@
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</language>
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<language processor="AVR8"
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deprecated="true"
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endian="little"
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size="16"
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size="24"
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variant="extended"
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version="1.4"
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slafile="avr8e.sla"
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slafile="avr8eind.sla"
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processorspec="avr8.pspec"
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manualindexfile="../manuals/AVR8.idx"
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id="avr8:LE:16:extended">
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<description>AVR8 with 22-bit word addressable code space</description>
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<description>AVR8 with 22-bit word addressable with EIND code space</description>
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<compiler name="gcc" spec="avr8egcc.cspec" id="gcc"/>
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<external_name tool="gnu" name="avr:51"/>
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<external_name tool="IDA-PRO" name="avr"/>
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</language>
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<language processor="AVR8"
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<language processor="AVR8"
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endian="little"
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size="24"
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variant="atmega256"
@@ -45,6 +45,7 @@
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id="avr8:LE:16:atmega256">
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<description>AVR8 for an Atmega 256</description>
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<compiler name="gcc" spec="avr8egcc.cspec" id="gcc"/>
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<external_name tool="gnu" name="avr:51"/>
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<external_name tool="gnu" name="avr:6"/>
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<external_name tool="IDA-PRO" name="avr"/>
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</language>

‎Ghidra/Processors/Atmel/data/languages/avr8egcc.cspec

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@@ -38,10 +38,10 @@
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<stackpointer register="SP" space="mem" growth="negative"/>
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<default_proto>
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<prototype name="__stdcall" extrapop="3" stackshift="3" strategy="register">
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<prototype name="__stdcall" extrapop="3" stackshift="3">
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<input>
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<pentry minsize="1" maxsize="2">
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<register name="W"/>
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<register name="W"/> <!-- R25R24 -->
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="R23R22"/>
@@ -67,14 +67,11 @@
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<pentry minsize="1" maxsize="2">
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<register name="R9R8"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="Z"/>
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</pentry>
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<!-- set to 20 on purpose, so that large values don't get assigned to stack -->
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<!-- They get allocated across register pairs, but layout algorithm too simple -->
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<pentry minsize="24" maxsize="500" align="1">
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<addr offset="20" space="stack"/>
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</pentry>
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<!-- Currently messes up parameter allocation, for known data types bigger than 2 -->
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<!-- strategy="packreg" planned to mitigate this problem -->
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<pentry minsize="1" maxsize="500" align="1">
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<addr offset="4" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="2">
@@ -126,16 +123,22 @@
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</prototype>
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</default_proto>
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<prototype name="__stackcall" extrapop="3" stackshift="3" strategy="register">
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<prototype name="__stackcall" extrapop="3" stackshift="3">
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<input>
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<pentry minsize="1" maxsize="500" align="1">
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<addr offset="1" space="stack"/>
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<addr offset="4" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="2">
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<register name="W"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="W"/>
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</pentry>
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<pentry minsize="3" maxsize="4">
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<addr space="join" piece1="W" piece2="R23R22"/>
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</pentry>
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<pentry minsize="5" maxsize="8">
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<addr space="join" piece1="W" piece2="R23R22" piece3="R21R20" piece4="R19R18"/>
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</pentry>
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</output>
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<unaffected>
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<register name="SP"/>

‎Ghidra/Processors/Atmel/data/languages/avr8gcc.cspec

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@@ -38,10 +38,10 @@
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<stackpointer register="SP" space="mem" growth="negative"/>
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<default_proto>
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<prototype name="__stdcall" extrapop="" stackshift="2" strategy="register">
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<prototype name="__stdcall" extrapop="2" stackshift="2">
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<input>
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<pentry minsize="1" maxsize="2">
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<register name="W"/>
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<register name="W"/> <!-- R25R24 -->
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="R23R22"/>
@@ -67,14 +67,11 @@
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<pentry minsize="1" maxsize="2">
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<register name="R9R8"/>
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</pentry>
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<pentry minsize="1" maxsize="2">
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<register name="Z"/>
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</pentry>
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<!-- set to 20 on purpose, so that large values don't get assigned to stack -->
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<!-- They get allocated across register pairs, but layout algorithm too simple -->
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<pentry minsize="24" maxsize="500" align="1">
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<addr offset="20" space="stack"/>
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</pentry>
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<!-- Currently messes up parameter allocation, for known data types bigger than 2 -->
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<!-- strategy="packreg" planned to mitigate this problem -->
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<pentry minsize="1" maxsize="500" align="1">
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<addr offset="3" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="2">
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</prototype>
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</default_proto>
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<prototype name="__stackcall" extrapop="3" stackshift="3" strategy="register">
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<prototype name="__stackcall" extrapop="2" stackshift="2">
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<input>
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<pentry minsize="1" maxsize="500" align="1">
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<addr offset="3" space="stack"/>

‎Ghidra/Processors/Atmel/data/languages/avr8iarV1.cspec

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@@ -15,18 +15,27 @@
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<!-- <prototype name="__stdcall" extrapop="2" stackshift="2"> -->
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<prototype name="__stdcall" extrapop="0" stackshift="0" strategy="register">
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<input>
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<pentry minsize="1" maxsize="4">
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<pentry minsize="1" maxsize="2">
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<register name="R17R16"/>
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</pentry>
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<pentry minsize="3" maxsize="4">
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<addr space="join" piece1="R19R18" piece2="R17R16"/>
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</pentry>
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<pentry minsize="1" maxsize="4">
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<pentry minsize="1" maxsize="2">
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<register name="R21R20"/>
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</pentry>
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<pentry minsize="3" maxsize="4">
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<addr space="join" piece1="R23R22" piece2="R21R20"/>
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</pentry>
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<pentry minsize="1" maxsize="500" align="1">
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<addr offset="0" space="stack"/>
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</pentry>
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</input>
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<output>
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<pentry minsize="1" maxsize="4">
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<pentry minsize="1" maxsize="2">
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<register name="R17R16"/>
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</pentry>
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<pentry minsize="3" maxsize="4">
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<addr space="join" piece1="R19R18" piece2="R17R16"/>
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</pentry>
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</output>

‎Ghidra/Processors/Atmel/data/patterns/AVR8_patterns.xml

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<patternlist>
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<patternpairs totalbits="32" postbits="16">
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<prepatterns>
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<data>0x08 0x95</data> <!-- ret -->
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<data>0x18 0x95</data> <!-- reti -->
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</prepatterns>
8+
9+
<postpatterns>
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<data>....1111 1001001. ....1111 1001001. </data> <!-- push reg, push reg -->
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<funcstart/>
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</postpatterns>
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</patternpairs>
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15+
<pattern> <!-- 24-bit processors copy static bytes to mem -->
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<data>
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0x1. 0xe. <!-- ldi R17,<upper> -->
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0xa. 0xe. <!-- ldi Xlo,<memlo> -->
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0xb. 0xe. <!-- ldi Xhi,<memhi> -->
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0xe. 0xe. <!-- ldi Zlo,<codelo> -->
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0xf. 0xe. <!-- ldi Zhi,<codehi> -->
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0x0. 0xe. <!-- ldi R16,<codepage> -->
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0x0b 0xbf <!-- out RAMPZ,R16 -->
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0x02 0xc0 <!-- rjmp LAB_instr_next+2 -->
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0x07 0x90 <!-- elpm R0,Z+ -->
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0x0d 0x92 <!-- st X+,R0 -->
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0xa. 0x3. <!-- cpi Xlo,<lower> -->
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0xb1 0x07 <!-- cpc Xhi,R17 -->
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0xd9 0xf7 <!-- brbc inst_start-4,Zflg -->
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</data>
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<funcstart label="__do_copy_data"/>
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</pattern>
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</patternlist>

‎Ghidra/Processors/Atmel/data/patterns/patternconstraints.xml

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@@ -0,0 +1,5 @@
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<patternconstraints>
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<language id="avr8:*:*:*">
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<patternfile>AVR8_patterns.xml</patternfile>
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</language>
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</patternconstraints>

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