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Move Vector trait to lib.rs
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2 files changed

+16
-18
lines changed

2 files changed

+16
-18
lines changed

src/lib.rs

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@@ -149,6 +149,21 @@ impl MemchrSearcher {
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}
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}
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/// Represents a generic SIMD register type.
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trait Vector: Copy {
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const LANES: usize;
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unsafe fn set1_epi8(a: i8) -> Self;
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unsafe fn loadu_si(a: *const u8) -> Self;
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unsafe fn cmpeq_epi8(a: Self, b: Self) -> Self;
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unsafe fn and_si(a: Self, b: Self) -> Self;
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unsafe fn movemask_epi8(a: Self) -> i32;
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}
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#[cfg(test)]
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mod tests {
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use super::{MemchrSearcher, Needle};

src/x86.rs

Lines changed: 1 addition & 18 deletions
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@@ -1,29 +1,12 @@
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#![allow(clippy::missing_safety_doc)]
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use crate::{bits, memcmp, MemchrSearcher, Needle, NeedleWithSize};
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use crate::{bits, memcmp, MemchrSearcher, Needle, NeedleWithSize, Vector};
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use seq_macro::seq;
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#[cfg(target_arch = "x86")]
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use std::arch::x86::*;
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#[cfg(target_arch = "x86_64")]
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use std::arch::x86_64::*;
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/// Represents an SIMD register type that is x86-specific (but could be used
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/// more generically) in order to share functionality between SSE2, AVX2 and
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/// possibly future implementations.
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trait Vector: Copy {
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const LANES: usize;
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unsafe fn set1_epi8(a: i8) -> Self;
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unsafe fn loadu_si(a: *const u8) -> Self;
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unsafe fn cmpeq_epi8(a: Self, b: Self) -> Self;
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unsafe fn and_si(a: Self, b: Self) -> Self;
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unsafe fn movemask_epi8(a: Self) -> i32;
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}
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#[derive(Clone, Copy)]
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#[repr(transparent)]
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#[allow(non_camel_case_types)]

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