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bjorn3bjorn3
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Update portable-simd
1 parent 7f260a9 commit c4c393c

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3 files changed

+170
-63
lines changed

3 files changed

+170
-63
lines changed

‎build_system/prepare.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ pub(crate) fn prepare() {
4141
"portable-simd",
4242
"rust-lang",
4343
"portable-simd",
44-
"b8d6b6844602f80af79cd96401339ec594d472d8",
44+
"d5cd4a8112d958bd3a252327e0d069a6363249bd",
4545
);
4646
apply_patches("portable-simd", Path::new("portable-simd"));
4747

‎patches/0001-portable-simd-Disable-unsupported-tests.patch

+168-61
Original file line numberDiff line numberDiff line change
@@ -1,80 +1,188 @@
1-
From 97c473937382a5b5858d9cce3c947855d23b2dc5 Mon Sep 17 00:00:00 2001
1+
From 82f597cf81b169b0e72a576ac8751f598c059c48 Mon Sep 17 00:00:00 2001
22
From: bjorn3 <[email protected]>
33
Date: Thu, 18 Nov 2021 19:28:40 +0100
44
Subject: [PATCH] Disable unsupported tests
55

66
---
7-
crates/core_simd/src/math.rs | 6 ++++++
8-
crates/core_simd/src/vector.rs | 2 ++
9-
crates/core_simd/tests/masks.rs | 2 ++
10-
crates/core_simd/tests/ops_macros.rs | 4 ++++
11-
4 files changed, 14 insertions(+)
7+
crates/core_simd/src/elements/int.rs | 8 ++++++++
8+
crates/core_simd/src/elements/uint.rs | 4 ++++
9+
crates/core_simd/src/masks/full_masks.rs | 9 +++++++++
10+
crates/core_simd/src/vector.rs | 2 ++
11+
crates/core_simd/tests/masks.rs | 2 ++
12+
5 files changed, 25 insertions(+)
1213

13-
diff --git a/crates/core_simd/src/math.rs b/crates/core_simd/src/math.rs
14-
index 2bae414..2f87499 100644
15-
--- a/crates/core_simd/src/math.rs
16-
+++ b/crates/core_simd/src/math.rs
17-
@@ -5,6 +5,7 @@ macro_rules! impl_uint_arith {
18-
($($ty:ty),+) => {
19-
$( impl<const LANES: usize> Simd<$ty, LANES> where LaneCount<LANES>: SupportedLaneCount {
14+
diff --git a/crates/core_simd/src/elements/int.rs b/crates/core_simd/src/elements/int.rs
15+
index 9b8c37e..ea95f08 100644
16+
--- a/crates/core_simd/src/elements/int.rs
17+
+++ b/crates/core_simd/src/elements/int.rs
18+
@@ -11,6 +11,7 @@ pub trait SimdInt: Copy + Sealed {
19+
/// Scalar type contained by this SIMD vector type.
20+
type Scalar;
2021

21-
+ /*
22-
/// Lanewise saturating add.
23-
///
24-
/// # Examples
25-
@@ -43,6 +44,7 @@ macro_rules! impl_uint_arith {
26-
pub fn saturating_sub(self, second: Self) -> Self {
27-
unsafe { simd_saturating_sub(self, second) }
28-
}
29-
+ */
30-
})+
31-
}
32-
}
33-
@@ -51,6 +53,7 @@ macro_rules! impl_int_arith {
34-
($($ty:ty),+) => {
35-
$( impl<const LANES: usize> Simd<$ty, LANES> where LaneCount<LANES>: SupportedLaneCount {
22+
+ /*
23+
/// Lanewise saturating add.
24+
///
25+
/// # Examples
26+
@@ -45,6 +46,7 @@ pub trait SimdInt: Copy + Sealed {
27+
/// assert_eq!(unsat, Simd::from_array([1, MAX, MIN, 0]));
28+
/// assert_eq!(sat, Simd::from_array([MIN, MIN, MIN, 0]));
29+
fn saturating_sub(self, second: Self) -> Self;
30+
+ */
31+
32+
/// Lanewise absolute value, implemented in Rust.
33+
/// Every lane becomes its absolute value.
34+
@@ -61,6 +63,7 @@ pub trait SimdInt: Copy + Sealed {
35+
/// ```
36+
fn abs(self) -> Self;
37+
38+
+ /*
39+
/// Lanewise saturating absolute value, implemented in Rust.
40+
/// As abs(), except the MIN value becomes MAX instead of itself.
41+
///
42+
@@ -96,6 +99,7 @@ pub trait SimdInt: Copy + Sealed {
43+
/// assert_eq!(sat, Simd::from_array([MAX, 2, -3, MIN + 1]));
44+
/// ```
45+
fn saturating_neg(self) -> Self;
46+
+ */
47+
48+
/// Returns true for each positive lane and false if it is zero or negative.
49+
fn is_positive(self) -> Self::Mask;
50+
@@ -199,6 +203,7 @@ macro_rules! impl_trait {
51+
type Mask = Mask<<$ty as SimdElement>::Mask, LANES>;
52+
type Scalar = $ty;
3653

3754
+ /*
38-
/// Lanewise saturating add.
39-
///
40-
/// # Examples
41-
@@ -89,6 +92,7 @@ macro_rules! impl_int_arith {
42-
pub fn saturating_sub(self, second: Self) -> Self {
43-
unsafe { simd_saturating_sub(self, second) }
55+
#[inline]
56+
fn saturating_add(self, second: Self) -> Self {
57+
// Safety: `self` is a vector
58+
@@ -210,6 +215,7 @@ macro_rules! impl_trait {
59+
// Safety: `self` is a vector
60+
unsafe { intrinsics::simd_saturating_sub(self, second) }
4461
}
4562
+ */
4663

47-
/// Lanewise absolute value, implemented in Rust.
48-
/// Every lane becomes its absolute value.
49-
@@ -109,6 +113,7 @@ macro_rules! impl_int_arith {
64+
#[inline]
65+
fn abs(self) -> Self {
66+
@@ -218,6 +224,7 @@ macro_rules! impl_trait {
5067
(self^m) - m
5168
}
5269

5370
+ /*
54-
/// Lanewise saturating absolute value, implemented in Rust.
55-
/// As abs(), except the MIN value becomes MAX instead of itself.
56-
///
57-
@@ -151,6 +156,7 @@ macro_rules! impl_int_arith {
58-
pub fn saturating_neg(self) -> Self {
71+
#[inline]
72+
fn saturating_abs(self) -> Self {
73+
// arith shift for -1 or 0 mask based on sign bit, giving 2s complement
74+
@@ -230,6 +237,7 @@ macro_rules! impl_trait {
75+
fn saturating_neg(self) -> Self {
5976
Self::splat(0).saturating_sub(self)
6077
}
6178
+ */
62-
})+
79+
80+
#[inline]
81+
fn is_positive(self) -> Self::Mask {
82+
diff --git a/crates/core_simd/src/elements/uint.rs b/crates/core_simd/src/elements/uint.rs
83+
index 21e7e76..0d6dee2 100644
84+
--- a/crates/core_simd/src/elements/uint.rs
85+
+++ b/crates/core_simd/src/elements/uint.rs
86+
@@ -6,6 +6,7 @@ pub trait SimdUint: Copy + Sealed {
87+
/// Scalar type contained by this SIMD vector type.
88+
type Scalar;
89+
90+
+ /*
91+
/// Lanewise saturating add.
92+
///
93+
/// # Examples
94+
@@ -40,6 +41,7 @@ pub trait SimdUint: Copy + Sealed {
95+
/// assert_eq!(unsat, Simd::from_array([3, 2, 1, 0]));
96+
/// assert_eq!(sat, Simd::splat(0));
97+
fn saturating_sub(self, second: Self) -> Self;
98+
+ */
99+
100+
/// Returns the sum of the lanes of the vector, with wrapping addition.
101+
fn reduce_sum(self) -> Self::Scalar;
102+
@@ -78,6 +80,7 @@ macro_rules! impl_trait {
103+
{
104+
type Scalar = $ty;
105+
106+
+ /*
107+
#[inline]
108+
fn saturating_add(self, second: Self) -> Self {
109+
// Safety: `self` is a vector
110+
@@ -89,6 +92,7 @@ macro_rules! impl_trait {
111+
// Safety: `self` is a vector
112+
unsafe { intrinsics::simd_saturating_sub(self, second) }
113+
}
114+
+ */
115+
116+
#[inline]
117+
fn reduce_sum(self) -> Self::Scalar {
118+
diff --git a/crates/core_simd/src/masks/full_masks.rs b/crates/core_simd/src/masks/full_masks.rs
119+
index adf0fcb..5b10292 100644
120+
--- a/crates/core_simd/src/masks/full_masks.rs
121+
+++ b/crates/core_simd/src/masks/full_masks.rs
122+
@@ -150,6 +150,7 @@ where
123+
super::Mask<T, LANES>: ToBitMaskArray,
124+
[(); <super::Mask<T, LANES> as ToBitMaskArray>::BYTES]: Sized,
125+
{
126+
+ /*
127+
assert_eq!(<super::Mask<T, LANES> as ToBitMaskArray>::BYTES, N);
128+
129+
// Safety: N is the correct bitmask size
130+
@@ -170,6 +171,8 @@ where
131+
132+
bitmask
133+
}
134+
+ */
135+
+ panic!();
63136
}
64-
}
137+
138+
#[cfg(feature = "generic_const_exprs")]
139+
@@ -209,6 +212,7 @@ where
140+
where
141+
super::Mask<T, LANES>: ToBitMask<BitMask = U>,
142+
{
143+
+ /*
144+
// Safety: U is required to be the appropriate bitmask type
145+
let bitmask: U = unsafe { intrinsics::simd_bitmask(self.0) };
146+
147+
@@ -218,6 +222,8 @@ where
148+
} else {
149+
bitmask
150+
}
151+
+ */
152+
+ panic!();
153+
}
154+
155+
#[inline]
156+
@@ -225,6 +231,7 @@ where
157+
where
158+
super::Mask<T, LANES>: ToBitMask<BitMask = U>,
159+
{
160+
+ /*
161+
// LLVM assumes bit order should match endianness
162+
let bitmask = if cfg!(target_endian = "big") {
163+
bitmask.reverse_bits(LANES)
164+
@@ -240,6 +247,8 @@ where
165+
Self::splat(false).to_int(),
166+
))
167+
}
168+
+ */
169+
+ panic!();
170+
}
171+
172+
#[inline]
65173
diff --git a/crates/core_simd/src/vector.rs b/crates/core_simd/src/vector.rs
66-
index 7c5ec2b..c8631e8 100644
174+
index e8e8f68..7173c24 100644
67175
--- a/crates/core_simd/src/vector.rs
68176
+++ b/crates/core_simd/src/vector.rs
69-
@@ -75,6 +75,7 @@ where
70-
Self(array)
177+
@@ -250,6 +250,7 @@ where
178+
unsafe { intrinsics::simd_cast(self) }
71179
}
72180

73181
+ /*
74182
/// Reads from potentially discontiguous indices in `slice` to construct a SIMD vector.
75183
/// If an index is out-of-bounds, the lane is instead selected from the `or` vector.
76184
///
77-
@@ -297,6 +298,7 @@ where
185+
@@ -473,6 +474,7 @@ where
78186
// Cleared ☢️ *mut T Zone
79187
}
80188
}
@@ -83,25 +191,24 @@ index 7c5ec2b..c8631e8 100644
83191

84192
impl<T, const LANES: usize> Copy for Simd<T, LANES>
85193
diff --git a/crates/core_simd/tests/masks.rs b/crates/core_simd/tests/masks.rs
86-
index 6a8ecd3..68fcb49 100644
194+
index 673d0db..0d68b01 100644
87195
--- a/crates/core_simd/tests/masks.rs
88196
+++ b/crates/core_simd/tests/masks.rs
89-
@@ -68,6 +68,7 @@ macro_rules! test_mask_api {
90-
assert_eq!(core_simd::Mask::<$type, 8>::from_int(int), mask);
197+
@@ -59,6 +59,7 @@ macro_rules! test_mask_api {
198+
assert!(!v.all());
91199
}
92200

93201
+ /*
94-
#[cfg(feature = "generic_const_exprs")]
95202
#[test]
96-
fn roundtrip_bitmask_conversion() {
97-
@@ -80,6 +81,7 @@ macro_rules! test_mask_api {
98-
assert_eq!(bitmask, [0b01001001, 0b10000011]);
99-
assert_eq!(core_simd::Mask::<$type, 16>::from_bitmask(bitmask), mask);
203+
fn roundtrip_int_conversion() {
204+
let values = [true, false, false, true, false, false, true, false];
205+
@@ -99,6 +100,7 @@ macro_rules! test_mask_api {
206+
assert_eq!(bitmask, 0b01);
207+
assert_eq!(core_simd::Mask::<$type, 2>::from_bitmask(bitmask), mask);
100208
}
101209
+ */
102-
}
103-
}
104-
}
210+
211+
#[test]
212+
fn cast() {
105213
--
106-
2.26.2.7.g19db9cfb68
107-
214+
2.25.1

‎src/intrinsics/simd.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
2626
span: Span,
2727
) {
2828
match intrinsic {
29-
sym::simd_cast => {
29+
sym::simd_as | sym::simd_cast => {
3030
intrinsic_args!(fx, args => (a); intrinsic);
3131

3232
if !a.layout().ty.is_simd() {

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