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| 1 | +/** |
| 2 | + ****************************************************************************** |
| 3 | + * @file dwt.c |
| 4 | + * @author Frederic Pillon |
| 5 | + * @brief Provide Data Watchpoint and Trace services |
| 6 | + ****************************************************************************** |
| 7 | + * @attention |
| 8 | + * |
| 9 | + * Copyright (c) 2019, STMicroelectronics |
| 10 | + * All rights reserved. |
| 11 | + * |
| 12 | + * This software component is licensed by ST under BSD 3-Clause license, |
| 13 | + * the "License"; You may not use this file except in compliance with the |
| 14 | + * License. You may obtain a copy of the License at: |
| 15 | + * opensource.org/licenses/BSD-3-Clause |
| 16 | + * |
| 17 | + ****************************************************************************** |
| 18 | + */ |
| 19 | + |
| 20 | +#include "dwt.h" |
| 21 | + |
| 22 | +#ifdef DWT_BASE |
| 23 | +#ifdef __cplusplus |
| 24 | +extern "C" { |
| 25 | +#endif |
| 26 | + |
| 27 | + |
| 28 | +uint32_t dwt_init(void) |
| 29 | +{ |
| 30 | + |
| 31 | + /* Enable use of DWT */ |
| 32 | + if (!(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)) { |
| 33 | + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; |
| 34 | + } |
| 35 | + |
| 36 | + /* Unlock */ |
| 37 | + dwt_access(true); |
| 38 | + |
| 39 | + /* Reset the clock cycle counter value */ |
| 40 | + DWT->CYCCNT = 0; |
| 41 | + |
| 42 | + /* Enable clock cycle counter */ |
| 43 | + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; |
| 44 | + |
| 45 | + /* 3 NO OPERATION instructions */ |
| 46 | + asm volatile(" nop \n\t" |
| 47 | + " nop \n\t" |
| 48 | + " nop \n\t"); |
| 49 | + |
| 50 | + /* Check if clock cycle counter has started */ |
| 51 | + return (DWT->CYCCNT) ? 0 : 1; |
| 52 | +} |
| 53 | + |
| 54 | +void dwt_access(bool ena) |
| 55 | +{ |
| 56 | +#if (__CORTEX_M == 0x07U) |
| 57 | + /* |
| 58 | + * Define DWT LSR mask which is (currentuly) not defined by the CMSIS. |
| 59 | + * Same as ITM LSR one. |
| 60 | + */ |
| 61 | +#if !defined DWT_LSR_Present_Msk |
| 62 | +#define DWT_LSR_Present_Msk ITM_LSR_Present_Msk |
| 63 | +#endif |
| 64 | +#if !defined DWT_LSR_Access_Msk |
| 65 | +#define DWT_LSR_Access_Msk ITM_LSR_Access_Msk |
| 66 | +#endif |
| 67 | + uint32_t lsr = DWT->LSR; |
| 68 | + |
| 69 | + if ((lsr & DWT_LSR_Present_Msk) != 0) { |
| 70 | + if (ena) { |
| 71 | + if ((lsr & DWT_LSR_Access_Msk) != 0) { //locked |
| 72 | + DWT->LAR = 0xC5ACCE55; |
| 73 | + } |
| 74 | + } else { |
| 75 | + if ((lsr & DWT_LSR_Access_Msk) == 0) { //unlocked |
| 76 | + DWT->LAR = 0; |
| 77 | + } |
| 78 | + } |
| 79 | + } |
| 80 | +#else /* __CORTEX_M */ |
| 81 | + UNUSED(ena); |
| 82 | +#endif /* __CORTEX_M */ |
| 83 | +} |
| 84 | + |
| 85 | +#ifdef __cplusplus |
| 86 | +} |
| 87 | +#endif |
| 88 | + |
| 89 | +#endif |
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