From 8e6142eb9b1cf1af4e4a1fa64f54b1bc92ca8b6f Mon Sep 17 00:00:00 2001 From: Mike S Date: Sat, 11 Jan 2025 12:18:11 -0500 Subject: [PATCH] Added SDRAM + Lib + llext_export changes --- cores/arduino/abi.cpp | 26 + firmwares/zephyr-arduino_giga_r1_m7.bin | Bin 141148 -> 146908 bytes firmwares/zephyr-arduino_giga_r1_m7.elf | Bin 2368172 -> 2521776 bytes installed.json | 4872 ++++ libraries/SocketWrapper/WiFi.cpp | 3 + libraries/SocketWrapper/WiFi.h | 4 + libraries/SocketWrapper/ZephyrSSLClient.h | 18 + libraries/SocketWrapper/ZephyrUDP.h | 330 + .../SocketWrapper/utility/wl_definitions.h | 77 + .../SDRAM_operations/SDRAM_operations.ino | 68 + libraries/Zephyr_SDRAM/library.properties | 9 + libraries/Zephyr_SDRAM/src/SDRAM.cpp | 69 + libraries/Zephyr_SDRAM/src/SDRAM.h | 27 + libraries/ea_malloc/ea_malloc.h | 46 + libraries/ea_malloc/ll.h | 367 + libraries/ea_malloc/malloc_freelist.c | 168 + loader/boards/arduino_giga_r1_m7.conf | 12 +- loader/boards/arduino_giga_r1_m7.overlay | 42 + loader/llext_exports.c | 34 +- samples/analog_input/CMakeLists.txt | 12 - samples/analog_input/README.rst | 24 - samples/analog_input/prj.conf | 2 - samples/analog_input/src/main.cpp | 29 - samples/attach_interrupt/CMakeLists.txt | 13 - samples/attach_interrupt/README.rst | 22 - samples/attach_interrupt/prj.conf | 1 - samples/attach_interrupt/src/main.cpp | 25 - samples/blinky_arduino/CMakeLists.txt | 13 - samples/blinky_arduino/README.rst | 71 - samples/blinky_arduino/prj.conf | 2 - samples/blinky_arduino/src/main.cpp | 19 - samples/button_press_led/CMakeLists.txt | 13 - samples/button_press_led/README.rst | 67 - samples/button_press_led/prj.conf | 2 - samples/button_press_led/src/main.cpp | 34 - samples/fade/CMakeLists.txt | 13 - samples/fade/README.rst | 21 - samples/fade/prj.conf | 2 - samples/fade/src/app.cpp | 31 - samples/hello_arduino/CMakeLists.txt | 13 - samples/hello_arduino/README.rst | 33 - samples/hello_arduino/prj.conf | 1 - samples/hello_arduino/src/app.cpp | 29 - samples/i2cdemo/CMakeLists.txt | 12 - samples/i2cdemo/README.rst | 28 - samples/i2cdemo/prj.conf | 6 - samples/i2cdemo/src/main.cpp | 118 - samples/serial_event/CMakeLists.txt | 13 - samples/serial_event/README.rst | 20 - samples/serial_event/prj.conf | 1 - samples/serial_event/src/app.cpp | 20 - samples/spi_controller/CMakeLists.txt | 13 - samples/spi_controller/README.rst | 9 - samples/spi_controller/prj.conf | 6 - samples/spi_controller/src/app.cpp | 27 - samples/threads_arduino/CMakeLists.txt | 12 - samples/threads_arduino/README.rst | 47 - samples/threads_arduino/prj.conf | 3 - samples/threads_arduino/src/main.cpp | 51 - .../llext-edk/Makefile.cflags | 8 +- .../arduino_giga_r1_m7/llext-edk/cmake.cflags | 8 +- .../common_ll/include/stm32_ll_adc.h | 4 + .../common_ll/include/stm32_ll_bus.h | 4 + .../common_ll/include/stm32_ll_comp.h | 2 + .../common_ll/include/stm32_ll_cortex.h | 4 + .../common_ll/include/stm32_ll_crc.h | 4 + .../common_ll/include/stm32_ll_crs.h | 6 +- .../common_ll/include/stm32_ll_dac.h | 2 + .../common_ll/include/stm32_ll_dma.h | 4 + .../common_ll/include/stm32_ll_dmamux.h | 4 + .../common_ll/include/stm32_ll_exti.h | 2 + .../common_ll/include/stm32_ll_gpio.h | 4 + .../common_ll/include/stm32_ll_i2c.h | 4 + .../common_ll/include/stm32_ll_iwdg.h | 4 + .../common_ll/include/stm32_ll_lptim.h | 2 + .../common_ll/include/stm32_ll_lpuart.h | 4 + .../common_ll/include/stm32_ll_opamp.h | 2 + .../common_ll/include/stm32_ll_pka.h | 2 + .../common_ll/include/stm32_ll_pwr.h | 4 + .../common_ll/include/stm32_ll_radio.h | 9 + .../common_ll/include/stm32_ll_rcc.h | 4 + .../common_ll/include/stm32_ll_rng.h | 4 + .../common_ll/include/stm32_ll_rtc.h | 4 + .../common_ll/include/stm32_ll_spi.h | 4 + .../common_ll/include/stm32_ll_system.h | 4 + .../common_ll/include/stm32_ll_tim.h | 4 + .../common_ll/include/stm32_ll_usart.h | 4 + .../common_ll/include/stm32_ll_utils.h | 4 + .../common_ll/include/stm32_ll_wwdg.h | 2 + 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.../zephyr/dt-bindings/regulator/nrf5x.h | 27 + .../dt-bindings/regulator/silabs_dcdc.h | 27 + .../reserved-memory/nordic-owned-memory.h | 53 + .../zephyr/dt-bindings/reset/rp2040_reset.h | 36 + .../zephyr/dt-bindings/reset/stm32u0_reset.h | 18 + .../zephyr/dt-bindings/reset/stm32wb0_reset.h | 18 + .../zephyr/dt-bindings/sensor/apds9253.h | 55 + .../zephyr/dt-bindings/sensor/lis2dw12.h | 18 + .../zephyr/dt-bindings/sensor/lps2xdf.h | 4 + .../zephyr/dt-bindings/sensor/lsm6dsv16x.h | 36 + .../zephyr/dt-bindings/sensor/lsm9ds1.h | 46 + .../zephyr/dt-bindings/sensor/mc3419.h | 50 + .../zephyr/dt-bindings/sensor/tmp116.h | 31 + .../dt-bindings/video/video-interfaces.h | 17 + .../include/zephyr/include/zephyr/fs/nvs.h | 24 + .../include/zephyr/include/zephyr/fs/zms.h | 211 + .../zephyr/include/zephyr/input/input.h | 28 +- .../include/zephyr/input/input_kbd_matrix.h | 23 + .../zephyr/include/zephyr/input/input_touch.h | 94 + .../include/zephyr/internal/syscall_handler.h | 4 +- .../include/zephyr/include/zephyr/ipc/icmsg.h | 4 +- .../include/zephyr/ipc/ipc_static_vrings.h | 6 +- .../include/zephyr/include/zephyr/ipc/pbuf.h | 38 +- .../zephyr/include/zephyr/irq_multilevel.h | 164 +- .../include/zephyr/include/zephyr/kernel.h | 162 +- .../include/zephyr/include/zephyr/kernel/mm.h | 84 + .../include/zephyr/kernel/mm/demand_paging.h | 37 + .../include/zephyr/kernel/thread_stack.h | 22 - .../zephyr/include/zephyr/kernel_structs.h | 11 +- .../zephyr/linker/devicetree_regions.h | 70 +- .../include/zephyr/linker/linker-defs.h | 28 +- .../include/zephyr/linker/linker-devnull.h | 1 + .../include/zephyr/linker/section_tags.h | 11 + .../zephyr/include/zephyr/linker/sections.h | 14 + .../zephyr/include/zephyr/llext/buf_loader.h | 23 +- .../include/zephyr/include/zephyr/llext/elf.h | 48 - .../zephyr/include/zephyr/llext/fs_loader.h | 73 + .../zephyr/include/zephyr/llext/llext.h | 76 +- .../include/zephyr/llext/llext_internal.h | 32 + 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.../include/zephyr/mgmt/mcumgr/mgmt/mgmt.h | 25 +- .../zephyr/mgmt/mcumgr/mgmt/mgmt_defines.h | 3 + .../include/zephyr/mgmt/mcumgr/smp/smp.h | 8 +- .../zephyr/mgmt/mcumgr/smp/smp_client.h | 2 +- .../zephyr/mgmt/mcumgr/transport/smp.h | 2 + .../zephyr/mgmt/mcumgr/transport/smp_bt.h | 19 + .../zephyr/mgmt/mcumgr/transport/smp_dummy.h | 2 +- .../include/zephyr/include/zephyr/mgmt/osdp.h | 6 +- .../zephyr/include/zephyr/misc/lorem_ipsum.h | 57 + .../zephyr/include/zephyr/modem/cmux.h | 2 +- .../zephyr/include/zephyr/modem/pipe.h | 10 +- .../zephyr/multi_heap/shared_multi_heap.h | 3 + .../include/zephyr/include/zephyr/net/buf.h | 2733 +-- .../zephyr/include/zephyr/net/capture.h | 2 + .../include/zephyr/include/zephyr/net/coap.h | 50 +- .../zephyr/include/zephyr/net/coap_client.h | 64 +- .../zephyr/include/zephyr/net/coap_mgmt.h | 2 + .../zephyr/include/zephyr/net/coap_service.h | 20 +- .../zephyr/net/conn_mgr_connectivity.h | 4 +- .../zephyr/net/conn_mgr_connectivity_impl.h | 4 +- .../include/zephyr/net/conn_mgr_monitor.h | 2 + .../zephyr/include/zephyr/net/dhcpv4.h | 2 + .../zephyr/include/zephyr/net/dhcpv4_server.h | 30 + .../zephyr/include/zephyr/net/dhcpv6.h | 2 + .../zephyr/include/zephyr/net/dns_resolve.h | 15 +- .../zephyr/include/zephyr/net/dns_sd.h | 14 +- .../include/zephyr/include/zephyr/net/dsa.h | 2 + .../include/zephyr/include/zephyr/net/dummy.h | 2 + .../zephyr/include/zephyr/net/ethernet.h | 31 +- .../include/zephyr/net/ethernet_bridge.h | 140 +- .../zephyr/include/zephyr/net/ethernet_mgmt.h | 2 + .../zephyr/include/zephyr/net/ethernet_vlan.h | 2 + .../include/zephyr/include/zephyr/net/gptp.h | 2 + .../zephyr/net/hdlc_rcp_if/hdlc_rcp_if.h | 77 + .../zephyr/include/zephyr/net/hostname.h | 34 +- .../zephyr/include/zephyr/net/http/hpack.h | 2 + .../zephyr/include/zephyr/net/http/method.h | 2 + .../zephyr/include/zephyr/net/http/server.h | 155 +- .../zephyr/include/zephyr/net/http/service.h | 24 +- .../zephyr/include/zephyr/net/http/status.h | 2 + .../include/zephyr/include/zephyr/net/icmp.h | 2 + .../zephyr/include/zephyr/net/ieee802154_ie.h | 2 +- .../include/zephyr/net/ieee802154_mgmt.h | 7 + .../include/zephyr/net/ieee802154_pkt.h | 22 + .../include/zephyr/net/ieee802154_radio.h | 61 +- .../zephyr/net/ieee802154_radio_openthread.h | 67 +- .../include/zephyr/include/zephyr/net/igmp.h | 2 + .../include/zephyr/include/zephyr/net/lldp.h | 2 + .../include/zephyr/include/zephyr/net/lwm2m.h | 140 +- .../zephyr/include/zephyr/net/lwm2m_path.h | 2 + .../include/zephyr/include/zephyr/net/mdio.h | 12 + .../include/zephyr/include/zephyr/net/mii.h | 11 + .../include/zephyr/include/zephyr/net/mld.h | 84 + .../zephyr/include/zephyr/net/mqtt_sn.h | 92 +- .../zephyr/include/zephyr/net/net_config.h | 2 + .../zephyr/include/zephyr/net/net_context.h | 37 +- .../zephyr/include/zephyr/net/net_core.h | 2 + .../zephyr/include/zephyr/net/net_event.h | 38 + .../zephyr/include/zephyr/net/net_if.h | 257 +- .../zephyr/include/zephyr/net/net_ip.h | 123 +- .../zephyr/include/zephyr/net/net_l2.h | 20 +- .../zephyr/include/zephyr/net/net_linkaddr.h | 2 + .../zephyr/include/zephyr/net/net_mgmt.h | 2 + .../zephyr/include/zephyr/net/net_offload.h | 4 +- .../zephyr/include/zephyr/net/net_pkt.h | 141 +- .../include/zephyr/net/net_pkt_filter.h | 6 + .../zephyr/include/zephyr/net/net_stats.h | 660 + .../zephyr/include/zephyr/net/net_time.h | 2 + .../zephyr/include/zephyr/net/net_timeout.h | 2 + .../include/zephyr/net/offloaded_netdev.h | 2 + .../zephyr/include/zephyr/net/openthread.h | 2 + .../include/zephyr/include/zephyr/net/phy.h | 8 +- .../include/zephyr/include/zephyr/net/ppp.h | 2 + .../include/zephyr/net/prometheus/collector.h | 177 + .../include/zephyr/net/prometheus/counter.h | 111 + .../include/zephyr/net/prometheus/formatter.h | 56 + .../include/zephyr/net/prometheus/gauge.h | 90 + .../include/zephyr/net/prometheus/histogram.h | 112 + .../include/zephyr/net/prometheus/label.h | 42 + .../include/zephyr/net/prometheus/metric.h | 76 + .../include/zephyr/net/prometheus/summary.h | 130 + .../zephyr/include/zephyr/net/promiscuous.h | 2 + .../include/zephyr/include/zephyr/net/ptp.h | 2 + .../zephyr/include/zephyr/net/ptp_time.h | 2 + .../include/zephyr/include/zephyr/net/sntp.h | 19 +- .../zephyr/include/zephyr/net/socket.h | 631 +- .../include/zephyr/net/socket_net_mgmt.h | 4 +- .../zephyr/include/zephyr/net/socket_poll.h | 6 + .../zephyr/include/zephyr/net/socket_select.h | 131 +- .../include/zephyr/net/socket_service.h | 35 +- .../zephyr/include/zephyr/net/socketcan.h | 4 +- .../include/zephyr/net/socketcan_utils.h | 3 +- .../include/zephyr/include/zephyr/net/tftp.h | 2 + .../include/zephyr/net/tls_credentials.h | 2 + .../zephyr/include/zephyr/net/trickle.h | 6 +- .../zephyr/include/zephyr/net/virtual.h | 5 + .../zephyr/include/zephyr/net/virtual_mgmt.h | 2 + .../zephyr/include/zephyr/net/websocket.h | 2 + .../include/zephyr/include/zephyr/net/wifi.h | 201 +- .../include/zephyr/net/wifi_credentials.h | 218 + .../zephyr/include/zephyr/net/wifi_mgmt.h | 583 +- .../zephyr/include/zephyr/net/wifi_nm.h | 2 + .../include/zephyr/include/zephyr/net/zperf.h | 2 + .../include/zephyr/include/zephyr/net_buf.h | 2731 ++ .../zephyr/include/zephyr/platform/hooks.h | 81 + .../include/zephyr/include/zephyr/pm/device.h | 17 +- .../include/zephyr/include/zephyr/pm/policy.h | 180 +- .../include/zephyr/include/zephyr/pm/state.h | 6 +- .../zephyr/include/zephyr/posix/dirent.h | 5 +- .../zephyr/include/zephyr/posix/fcntl.h | 9 +- .../include/zephyr/include/zephyr/posix/grp.h | 35 + .../zephyr/include/zephyr/posix/mqueue.h | 2 +- .../zephyr/include/zephyr/posix/poll.h | 3 + .../include/zephyr/posix/posix_features.h | 7 +- .../zephyr/include/zephyr/posix/posix_types.h | 83 +- .../zephyr/include/zephyr/posix/pthread.h | 18 +- .../include/zephyr/include/zephyr/posix/pwd.h | 36 + .../zephyr/include/zephyr/posix/sched.h | 3 +- .../zephyr/include/zephyr/posix/semaphore.h | 2 +- .../zephyr/include/zephyr/posix/signal.h | 37 +- .../zephyr/include/zephyr/posix/sys/select.h | 21 +- .../zephyr/include/zephyr/posix/sys/stat.h | 37 +- .../zephyr/include/zephyr/posix/sys/time.h | 1 + .../zephyr/include/zephyr/posix/time.h | 3 +- .../zephyr/include/zephyr/posix/unistd.h | 7 +- .../include/zephyr/include/zephyr/rtio/rtio.h | 108 +- .../zephyr/include/zephyr/settings/settings.h | 33 +- .../zephyr/include/zephyr/shell/shell.h | 108 +- .../include/zephyr/shell/shell_backend.h | 6 +- .../zephyr/include/zephyr/shell/shell_dummy.h | 6 +- .../include/zephyr/shell/shell_fprintf.h | 6 +- .../include/zephyr/shell/shell_history.h | 6 +- .../include/zephyr/shell/shell_log_backend.h | 6 +- .../zephyr/include/zephyr/shell/shell_mqtt.h | 6 +- .../zephyr/include/zephyr/shell/shell_rpmsg.h | 6 +- .../zephyr/include/zephyr/shell/shell_rtt.h | 6 +- .../include/zephyr/shell/shell_string_conv.h | 6 +- .../include/zephyr/shell/shell_telnet.h | 6 +- .../zephyr/include/zephyr/shell/shell_types.h | 6 +- .../zephyr/include/zephyr/shell/shell_uart.h | 6 +- .../include/zephyr/shell/shell_websocket.h | 151 + .../zephyr/include/zephyr/storage/flash_map.h | 66 +- .../include/zephyr/storage/stream_flash.h | 9 +- .../zephyr/include/zephyr/sys/atomic.h | 10 +- .../zephyr/include/zephyr/sys/cbprintf.h | 6 - .../include/zephyr/include/zephyr/sys/crc.h | 26 +- .../zephyr/include/zephyr/sys/errno_private.h | 3 +- .../zephyr/include/zephyr/sys/fdtable.h | 56 +- .../zephyr/include/zephyr/sys/libc-hooks.h | 4 +- .../zephyr/include/zephyr/sys/multi_heap.h | 26 + .../zephyr/include/zephyr/sys/poweroff.h | 2 - .../zephyr/include/zephyr/sys/printk-hooks.h | 38 + .../include/zephyr/include/zephyr/sys/rb.h | 4 +- .../zephyr/include/zephyr/sys/ring_buffer.h | 3 - .../include/zephyr/include/zephyr/sys/sem.h | 77 + .../zephyr/include/zephyr/sys/sys_heap.h | 9 + .../zephyr/include/zephyr/sys/timeutil.h | 3 + .../include/zephyr/include/zephyr/sys/util.h | 64 +- .../zephyr/include/zephyr/sys/util_internal.h | 2 +- .../include/zephyr/sys/util_internal_is_eq.h | 20485 ++++++++++++---- .../zephyr/include/zephyr/sys/util_macro.h | 30 +- .../include/zephyr/include/zephyr/sys_clock.h | 21 +- .../zephyr/include/zephyr/task_wdt/task_wdt.h | 6 +- .../zephyr/include/zephyr/toolchain/gcc.h | 14 + .../zephyr/include/zephyr/toolchain/mwdt.h | 10 - .../zephyr/include/zephyr/toolchain/xcc.h | 33 +- .../zephyr/include/zephyr/tracing/tracing.h | 303 + .../include/zephyr/tracing/tracing_macros.h | 8 +- .../include/zephyr/include/zephyr/types.h | 18 + .../include/zephyr/include/zephyr/usb/bos.h | 2 + .../zephyr/include/zephyr/usb/class/hid.h | 2 + .../include/zephyr/usb/class/usb_audio.h | 2 +- .../zephyr/include/zephyr/usb/class/usb_cdc.h | 28 + .../zephyr/include/zephyr/usb/class/usb_hid.h | 2 + .../include/zephyr/usb/class/usbd_hid.h | 2 + .../include/zephyr/usb/class/usbd_msc.h | 15 +- .../include/zephyr/usb/class/usbd_uac2.h | 35 + .../zephyr/include/zephyr/usb/msos_desc.h | 29 + .../zephyr/include/zephyr/usb/usb_ch9.h | 36 +- .../zephyr/include/zephyr/usb/usb_device.h | 2 + .../include/zephyr/include/zephyr/usb/usbd.h | 161 +- .../zephyr/include/zephyr/usb/usbd_msg.h | 5 + .../include/zephyr/include/zephyr/usb/usbh.h | 2 +- .../zephyr/include/zephyr/usb_c/tcpci.h | 788 + .../include/zephyr/xen/public/grant_table.h | 8 +- .../zephyr/include/zephyr/xen/public/memory.h | 4 +- .../zephyr/include/zephyr/xen/public/xen.h | 6 +- .../include/zephyr/include/zephyr/zbus/zbus.h | 147 +- .../zephyr/modules/cmsis/cmsis_core_a_r.h | 2 + .../zephyr/soc/st/stm32/stm32u0x/soc.h | 22 + .../zephyr/soc/st/stm32/stm32wb0x/soc.h | 33 + .../zephyr/soc/st/stm32/stm32wbax/soc.h | 5 +- .../modules/kernel_service/kernel_shell.h | 29 + .../zephyr/subsys/bluetooth/host/classic/at.h | 2 +- 915 files changed, 102622 insertions(+), 38258 deletions(-) create mode 100644 cores/arduino/abi.cpp create mode 100644 installed.json create mode 100644 libraries/SocketWrapper/WiFi.cpp create mode 100644 libraries/SocketWrapper/WiFi.h create mode 100644 libraries/SocketWrapper/ZephyrSSLClient.h create mode 100644 libraries/SocketWrapper/ZephyrUDP.h create mode 100644 libraries/SocketWrapper/utility/wl_definitions.h create mode 100644 libraries/Zephyr_SDRAM/examples/SDRAM_operations/SDRAM_operations.ino create mode 100644 libraries/Zephyr_SDRAM/library.properties create mode 100644 libraries/Zephyr_SDRAM/src/SDRAM.cpp create mode 100644 libraries/Zephyr_SDRAM/src/SDRAM.h create mode 100644 libraries/ea_malloc/ea_malloc.h create mode 100644 libraries/ea_malloc/ll.h create mode 100644 libraries/ea_malloc/malloc_freelist.c delete mode 100644 samples/analog_input/CMakeLists.txt delete mode 100644 samples/analog_input/README.rst delete mode 100644 samples/analog_input/prj.conf delete mode 100644 samples/analog_input/src/main.cpp delete mode 100644 samples/attach_interrupt/CMakeLists.txt delete mode 100644 samples/attach_interrupt/README.rst delete mode 100644 samples/attach_interrupt/prj.conf delete mode 100644 samples/attach_interrupt/src/main.cpp delete mode 100644 samples/blinky_arduino/CMakeLists.txt delete mode 100644 samples/blinky_arduino/README.rst delete mode 100644 samples/blinky_arduino/prj.conf delete mode 100644 samples/blinky_arduino/src/main.cpp delete mode 100644 samples/button_press_led/CMakeLists.txt delete mode 100644 samples/button_press_led/README.rst delete mode 100644 samples/button_press_led/prj.conf delete mode 100644 samples/button_press_led/src/main.cpp delete mode 100644 samples/fade/CMakeLists.txt delete mode 100644 samples/fade/README.rst delete mode 100644 samples/fade/prj.conf delete mode 100644 samples/fade/src/app.cpp delete mode 100644 samples/hello_arduino/CMakeLists.txt delete mode 100644 samples/hello_arduino/README.rst delete mode 100644 samples/hello_arduino/prj.conf delete mode 100644 samples/hello_arduino/src/app.cpp delete mode 100644 samples/i2cdemo/CMakeLists.txt delete mode 100644 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__throw_length_error(const char* __s __attribute__((unused))) {} +}; + +extern "C" int strcmp(const char* s1, const char* s2) { + while(*s1 && (*s1 == *s2)) + { + s1++; + s2++; + } + return *(const unsigned char*)s1 - *(const unsigned char*)s2; +} diff --git a/firmwares/zephyr-arduino_giga_r1_m7.bin b/firmwares/zephyr-arduino_giga_r1_m7.bin index 159443f54b4d9d441f84aee7483b043241b6133f..71c62aa8e75bbb638a99858e42ef0c93c2fdaee3 100755 GIT binary patch delta 59365 zcmbq*d3;kv_xHWIS#FcGNjE5MDQQw5v;{(2pe#a2%k2i1MS0ki0*Wavt>A*9CI~7j zDl(`@T@YMYT$+|D1+ln3ZulfDT0kG_0uib>rG?%mZSsC6E$Z`of1mgLy+Xb_bNpm&%XorKmLt=sP{X|ei3D#mzCmGkNj8Q z`fnTfFYCMhEA0Qv&e6B)za!s&jezUFoWK7Tft3G81NF};UedbUl(Q>ZxTZCfo8sUG zH7zR=t7?=;`hz4mD;uk_z5$^4gOMs*5&J&aeh(shiwDme1iQ zH2BLgP}g~v`Ie+6HqLY}!&T{JMa3pjsxI1io;Rd6ai;2`IO-}_`s|#w$qs7ay^UKj zv5C9H0U0)q0vfV2DpVJNYD@Z|HdQHe3|P?`ZvKw(%4nP;@UXMfG{n`Fvt|<69u`t>={AaKoZbaaqZyIJ$|fi5b8@L~3Hv`8&wL zm=t~)IT14~S@~C4S|D_edzr?4n%tBXinTpmd^*kkV8=eba{dggEab>Yq`xqi7} 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"1186835", + "checksum": "SHA-256:2a399efdf9c94eab3097f8bfc535e7585634f7f103f3aac51c52e9fbd6863c51" + }, + { + "host": "i386-apple-darwin11", + "url": "http://downloads.arduino.cc/tools/zephyr-post-build-tool-0.0.1-macos_amd64.tar.gz", + "archiveFileName": "zephyr-post-build-tool-0.0.1-macos_amd64.tar.gz", + "size": "1243020", + "checksum": "SHA-256:7f0bf1a5c2a2548c4d4faf081d8956d403a5de3d55e082bcd77660f01b47de10" + }, + { + "host": "i686-mingw32", + "url": "http://downloads.arduino.cc/tools/zephyr-post-build-tool-0.0.1-windows_386.zip", + "archiveFileName": "zephyr-post-build-tool-0.0.1-windows_386.zip", + "size": "1232672", + "checksum": "SHA-256:f4547d401363666f8ec29fce12ec12f4500188a7035f6ce840be48c98cf5fd40" + }, + { + "host": "x86_64-linux-gnu", + "url": "http://downloads.arduino.cc/tools/zephyr-post-build-tool-0.0.1-linux_amd64.tar.gz", + "archiveFileName": "zephyr-post-build-tool-0.0.1-linux_amd64.tar.gz", + "size": "1249164", + "checksum": "SHA-256:8286db4cdd7dd8aeb8587c233de8a88b3b8168b85f053aa64cd5a58856676fa2" + } + ] + } + ], + "help": { + "online": "http://www.arduino.cc/en/Reference/HomePage" + } + } + ], + "IsTrusted": true +} \ No newline at end of file diff --git a/libraries/SocketWrapper/WiFi.cpp b/libraries/SocketWrapper/WiFi.cpp new file mode 100644 index 00000000..f7374eb4 --- /dev/null +++ b/libraries/SocketWrapper/WiFi.cpp @@ -0,0 +1,3 @@ +#include "WiFi.h" + +NetworkInterface WiFi(1); diff --git a/libraries/SocketWrapper/WiFi.h b/libraries/SocketWrapper/WiFi.h new file mode 100644 index 00000000..29a1dc02 --- /dev/null +++ b/libraries/SocketWrapper/WiFi.h @@ -0,0 +1,4 @@ +#define SPECIALIZE_FOR_WIFI +#include "SocketHelpers.h" + +extern NetworkInterface WiFi; diff --git a/libraries/SocketWrapper/ZephyrSSLClient.h b/libraries/SocketWrapper/ZephyrSSLClient.h new file mode 100644 index 00000000..085f6a40 --- /dev/null +++ b/libraries/SocketWrapper/ZephyrSSLClient.h @@ -0,0 +1,18 @@ +#include "SocketWrapper.h" +#include "api/Client.h" +#include "unistd.h" +#include "zephyr/sys/printk.h" +#include "ZephyrClient.h" + +#if defined(CONFIG_NET_SOCKETS_SOCKOPT_TLS) +class ZephyrSSLClient : public ZephyrClient { + +public: + int connect(const char* host, uint16_t port, const char* cert) { + return connectSSL(host, port, (char*)cert); + } + int connect(const char* host, uint16_t port, char* cert) { + return connectSSL(host, port, cert); + } +}; +#endif \ No newline at end of file diff --git a/libraries/SocketWrapper/ZephyrUDP.h b/libraries/SocketWrapper/ZephyrUDP.h new file mode 100644 index 00000000..d0620205 --- /dev/null +++ b/libraries/SocketWrapper/ZephyrUDP.h @@ -0,0 +1,330 @@ +/* + MbedUdp.h - UDP implementation using mbed Sockets + Copyright (c) 2021 Arduino SA. All right reserved. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ + +#include "Arduino.h" +#include "SocketWrapper.h" +#include "api/Udp.h" +#include "sys/socket.h" +#include "zephyr/net/net_ip.h" +#include "zephyr/net/net_if.h" + +#include +#include +#include +#include + +class ZephyrUDP : public arduino::UDP { +private: + int _socket; + +public: + ZephyrUDP() : _socket(-1) {} // Constructor + ~ZephyrUDP() { + stop(); + } + + // initialize, start listening on specified port. Returns 1 if successful, 0 if there are no sockets available to use + virtual uint8_t begin(uint16_t port) { + + struct sockaddr_in addr; + addr.sin_family = AF_INET; + addr.sin_port = htons(port); + addr.sin_addr.s_addr = INADDR_ANY; + + _socket = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + + zsock_ioctl(_socket, ZFD_IOCTL_FIONBIO); + + if (::bind(_socket, (struct sockaddr*)&addr, sizeof(addr)) < 0) { + ::close(_socket); + _socket = -1; + return false; + } + + return true; + } + + // initialize, start listening on specified multicast IP address and port. Returns 1 if successful, 0 if there are no sockets available to use + virtual uint8_t beginMulticast(IPAddress ip, uint16_t port) { + bool ret = begin(port); + if (ret == false) { + return false; + } + + struct sockaddr_in addr; + addr.sin_family = AF_INET; + addr.sin_addr.s_addr = ip; + + net_if_ipv4_maddr_join(net_if_get_by_index(1), net_if_ipv4_maddr_add(net_if_get_by_index(1), (struct in_addr*)&addr)); + return true; + } + + // Finish with the UDP socket + virtual void stop() { + if (_socket != -1) { + ::close(_socket); + _socket = -1; + } + } + + // Sending UDP packets + + // Start building up a packet to send to the remote host specific in ip and port + // Returns 1 if successful, 0 if there was a problem with the supplied IP address or port + virtual int beginPacket(IPAddress ip, uint16_t port) { + _send_to_ip = ip; + _send_to_port = port; + + /* Make sure that the transmit data buffer is empty. */ + _tx_data.clear(); + return true; + } + + // Start building up a packet to send to the remote host specific in host and port + // Returns 1 if successful, 0 if there was a problem resolving the hostname or port + virtual int beginPacket(const char* host, uint16_t port) { + // Resolve address + struct addrinfo hints; + struct addrinfo *res; + + hints.ai_family = AF_INET; + hints.ai_socktype = SOCK_DGRAM; + + int resolve_attempts = 100; + int ret; + + while (resolve_attempts--) { + ret = getaddrinfo(host, String(port).c_str(), &hints, &res); + + if (ret == 0) { + break; + } else { + k_sleep(K_MSEC(1)); + } + } + + if (ret != 0) { + return false; + } + + return beginPacket(IPAddress(((sockaddr_in*)(res->ai_addr))->sin_addr.s_addr), port); + } + + // Finish off this packet and send it + // Returns 1 if the packet was sent successfully, 0 if there was an error + virtual int endPacket() { + struct sockaddr_in addr; + addr.sin_family = AF_INET; + addr.sin_port = htons(_send_to_port); + addr.sin_addr.s_addr = _send_to_ip; + return ::sendto(_socket, _tx_data.data(), _tx_data.size(), 0, (sockaddr*)&addr, sizeof(addr)); + } + + // Write a single byte into the packet + virtual size_t write(uint8_t data) { + _tx_data.push_back(data); + return 1; + } + + // Write size bytes from buffer into the packet + virtual size_t write(uint8_t* buffer, size_t size) { + std::copy(buffer, buffer + size, std::back_inserter(_tx_data)); + return size; + } + + // Write size bytes from buffer into the packet + virtual size_t write(const uint8_t* buffer, size_t size) { + std::copy(buffer, buffer + size, std::back_inserter(_tx_data)); + return size; + } + + using Print::write; + + int parsePacket() + { + struct sockaddr_in addr; + socklen_t addrlen = sizeof(addr); + uint8_t tmp_buf[512]; + + int ret = ::recvfrom(_socket, tmp_buf, sizeof(tmp_buf), 0, (sockaddr*)&addr, &addrlen); + if (ret > 0) + { + auto pkt = std::make_shared( + IPAddress(addr.sin_addr.s_addr), + ntohs(addr.sin_port), tmp_buf, ret); + + _rx_pkt_list.push_back(pkt); + + // drop the oldest packet if the list is full + if(_rx_pkt_list.size() > _rx_pkt_list_size) { + _rx_pkt_list.pop_front(); + } + } + + if (_rx_pkt_list.size()) + { + /* Discard UdpRxPacket object previously held by _rx_pkt + * and replace it with the new one. + */ + _rx_pkt = _rx_pkt_list.front(); + _rx_pkt_list.pop_front(); + return _rx_pkt->totalSize(); + } + else + { + /* Otherwise ensure that _rx_pkt definitely + * does not hold any UdpRxPacket object anymore. + */ + _rx_pkt.reset(); + return 0; + } + } + + int available() + { + if (_rx_pkt) + return _rx_pkt->available(); + else + return 0; + } + + int read() + { + if (_rx_pkt) + return _rx_pkt->read(); + else + return -1; + } + + int read(unsigned char* buffer, size_t len) + { + if (_rx_pkt) + return _rx_pkt->read(buffer, len); + else + return -1; + } + + int read(char* buffer, size_t len) + { + if (_rx_pkt) + return _rx_pkt->read(buffer, len); + else + return -1; + } + + int peek() + { + if (_rx_pkt) + return _rx_pkt->peek(); + else + return -1; + } + + void flush() + { + /* Delete UdpRxPacket object held by _rx_pkt. */ + if (_rx_pkt) + _rx_pkt.reset(); + } + + virtual IPAddress remoteIP() { + if (_rx_pkt) + return _rx_pkt->remoteIP(); + else + return IPAddress(); + } + + virtual uint16_t remotePort() { + if (_rx_pkt) + return _rx_pkt->remotePort(); + else + return 0; + } + +private: + + /* UDP TRANSMISSION */ + IPAddress _send_to_ip; + uint16_t _send_to_port; + std::vector _tx_data; + int _rx_pkt_list_size = 10; + /* UDP RECEPTION */ + class UdpRxPacket + { + private: + IPAddress const _remote_ip; + uint16_t const _remote_port; + size_t const _rx_data_len; + std::deque _rx_data; + + public: + UdpRxPacket( + IPAddress const remote_ip, + uint16_t const remote_port, + uint8_t const * p_data, + size_t const data_len) + : _remote_ip(remote_ip) + , _remote_port(remote_port) + , _rx_data_len(data_len) + , _rx_data(p_data, p_data + data_len) + { + } + + typedef std::shared_ptr SharedPtr; + + IPAddress remoteIP() const { return _remote_ip; } + uint16_t remotePort() const { return _remote_port; } + size_t totalSize() const { return _rx_data_len; } + + int available() + { + return _rx_data.size(); + } + + int read() + { + uint8_t const data = _rx_data.front(); + _rx_data.pop_front(); + return data; + } + + int read(unsigned char* buffer, size_t len) + { + size_t bytes_read = 0; + for (; bytes_read < len && !_rx_data.empty(); bytes_read++) + { + buffer[bytes_read] = _rx_data.front(); + _rx_data.pop_front(); + } + return bytes_read; + } + + int read(char* buffer, size_t len) + { + return read((unsigned char*)buffer, len); + } + + int peek() + { + return _rx_data.front(); + } + }; + std::list _rx_pkt_list; + UdpRxPacket::SharedPtr _rx_pkt; +}; \ No newline at end of file diff --git a/libraries/SocketWrapper/utility/wl_definitions.h b/libraries/SocketWrapper/utility/wl_definitions.h new file mode 100644 index 00000000..1c49a7af --- /dev/null +++ b/libraries/SocketWrapper/utility/wl_definitions.h @@ -0,0 +1,77 @@ +/* + wl_definitions.h - Library for Arduino Wifi shield. + Copyright (c) 2011-2014 Arduino. All right reserved. + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +/* + * wl_definitions.h + * + * Created on: Mar 6, 2011 + * Author: dlafauci + */ + +#ifndef WL_DEFINITIONS_H_ +#define WL_DEFINITIONS_H_ + +// Maximum size of a SSID +#define WL_SSID_MAX_LENGTH 32 +// Length of passphrase. Valid lengths are 8-63. +#define WL_WPA_KEY_MAX_LENGTH 63 +// Length of key in bytes. Valid values are 5 and 13. +#define WL_WEP_KEY_MAX_LENGTH 13 +// Size of a MAC-address or BSSID +#define WL_MAC_ADDR_LENGTH 6 +// Size of a MAC-address or BSSID +#define WL_IPV4_LENGTH 4 +// Maximum size of a SSID list +#define WL_NETWORKS_LIST_MAXNUM 10 +// Maxmium number of socket +#define MAX_SOCK_NUM 4 +// Socket not available constant +#define SOCK_NOT_AVAIL 255 +// Default state value for Wifi state field +#define NA_STATE -1 +//Maximum number of attempts to establish wifi connection +#define WL_MAX_ATTEMPT_CONNECTION 10 + +typedef enum { + WL_NO_SHIELD = 255, + WL_NO_MODULE = 255, + WL_IDLE_STATUS = 0, + WL_NO_SSID_AVAIL, + WL_SCAN_COMPLETED, + WL_CONNECTED, + WL_CONNECT_FAILED, + WL_CONNECTION_LOST, + WL_DISCONNECTED, + WL_AP_LISTENING, + WL_AP_CONNECTED, + WL_AP_FAILED +} wl_status_t; + +/* Encryption modes */ +enum wl_enc_type { /* Values map to 802.11 Cipher Algorithm Identifier */ + ENC_TYPE_WEP = 5, + ENC_TYPE_TKIP = 2, + ENC_TYPE_WPA = ENC_TYPE_TKIP, + ENC_TYPE_CCMP = 4, + ENC_TYPE_WPA2 = ENC_TYPE_CCMP, + ENC_TYPE_GCMP = 6, + ENC_TYPE_WPA3 = ENC_TYPE_GCMP, + /* ... except these two, 7 and 8 are reserved in 802.11-2007 */ + ENC_TYPE_NONE = 7, + ENC_TYPE_UNKNOWN = 9, + ENC_TYPE_AUTO = 8 +}; + +#endif /* WL_DEFINITIONS_H_ */ \ No newline at end of file diff --git a/libraries/Zephyr_SDRAM/examples/SDRAM_operations/SDRAM_operations.ino b/libraries/Zephyr_SDRAM/examples/SDRAM_operations/SDRAM_operations.ino new file mode 100644 index 00000000..c55795ea --- /dev/null +++ b/libraries/Zephyr_SDRAM/examples/SDRAM_operations/SDRAM_operations.ino @@ -0,0 +1,68 @@ +/* + How to interact with external SDRAM on Portenta H7 + + The board comes with an hefty 8MB of external fast RAM, which can be used: + - as a framebuffer (raw mode) + - as an expansion of on-chip RAM to store "standard" data + + This example shows both the usages +*/ + +#include "SDRAM.h" + +void nonFrameBuffer() { + // Initilize SDRAM for non-framebuffer operations + SDRAM.begin(); // is the same as SDRAM.begin(SDRAM_START_ADDRESS); + + // Now we can malloc() and free() in the whole RAM space + // For example, let's create a 7MB array + uint8_t* myVeryBigArray = (uint8_t*)SDRAM.malloc(7 * 1024 * 1024); + + // and a small one + uint8_t* mySmallArray = (uint8_t*)SDRAM.malloc(128); + + // and use then as usual + for (int i = 0; i<128; i++) { + myVeryBigArray[i] = i; + mySmallArray[i] = i*2; + } + + // free the memory when you don't need them anymore + SDRAM.free(myVeryBigArray); +} + +void frameBuffer() { + // In case we want a framebuffer-like area at the beginning of the flash, + // simply initialize the memory as + + SDRAM.begin(SDRAM_START_ADDRESS + 2 * 1024 * 1024); + // 2MB of contiguous memory available at the beginning + + uint32_t* framebuffer = (uint32_t*)SDRAM_START_ADDRESS; + + // We can't allocate anymore the huge 7MB array + + uint8_t* myVeryBigArray = (uint8_t*)SDRAM.malloc(7 * 1024 * 1024); + if (myVeryBigArray == NULL) { + Serial.println("Oops, too big :)"); + } + +} + +void setup() { + Serial.begin(115200); + while (!Serial); + + frameBuffer(); + // Uncomment to test the other functionality + // nonFrameBuffer(); + + // Sort of memtest for stability, useful for testing when overclocking + if (SDRAM.test()) { + Serial.println("SDRAM completely functional"); + } +} + +void loop() { + +} \ No newline at end of file diff --git a/libraries/Zephyr_SDRAM/library.properties b/libraries/Zephyr_SDRAM/library.properties new file mode 100644 index 00000000..cc80e102 --- /dev/null +++ b/libraries/Zephyr_SDRAM/library.properties @@ -0,0 +1,9 @@ +name=Portenta_SDRAM +version=1.0 +author=Arduino +maintainer=Arduino +sentence=Interact with external SDRAM chip on Portenta H7 +paragraph= +category=Other +url=https://github.com/arduino/ArduinoCore-mbed/tree/master/libraries/Portenta_SDRAM +architectures=* diff --git a/libraries/Zephyr_SDRAM/src/SDRAM.cpp b/libraries/Zephyr_SDRAM/src/SDRAM.cpp new file mode 100644 index 00000000..23c93f03 --- /dev/null +++ b/libraries/Zephyr_SDRAM/src/SDRAM.cpp @@ -0,0 +1,69 @@ +#include "SDRAM.h" +#include "Arduino.h" + +int SDRAMClass::begin(uint32_t start_address) { + if (start_address) { + malloc_addblock((void*)start_address, SDRAM_END_ADDRESS - start_address); + } + + return 1; +} + +void* SDRAMClass::malloc(size_t size) { + return ea_malloc(size); +} + +void SDRAMClass::free(void* ptr) { + ea_free(ptr); +} + +bool SDRAMClass::test(bool fast, Stream& _serial) { + uint8_t const pattern = 0xaa; + uint8_t const antipattern = 0x55; + uint8_t *const mem_base = (uint8_t*)SDRAM_START_ADDRESS; + + /* test data bus */ + for (uint8_t i = 1; i; i <<= 1) { + *mem_base = i; + if (*mem_base != i) { + _serial.println("data bus lines test failed! data (" + String(i) + ")"); + __asm__ volatile ("BKPT"); + } + } + + /* test address bus */ + /* Check individual address lines */ + for (uint32_t i = 1; i < HW_SDRAM_SIZE; i <<= 1) { + mem_base[i] = pattern; + if (mem_base[i] != pattern) { + _serial.println("address bus lines test failed! address ("+ String((uint32_t)&mem_base[i], HEX) + ")"); + __asm__ volatile ("BKPT"); + } + } + + /* Check for aliasing (overlaping addresses) */ + mem_base[0] = antipattern; + for (uint32_t i = 1; i < HW_SDRAM_SIZE; i <<= 1) { + if (mem_base[i] != pattern) { + _serial.println("address bus overlap! address ("+ String((uint32_t)&mem_base[i], HEX) + ")"); + __asm__ volatile ("BKPT"); + } + } + + /* test all ram cells */ + if (!fast) { + for (uint32_t i = 0; i < HW_SDRAM_SIZE; ++i) { + mem_base[i] = pattern; + if (mem_base[i] != pattern) { + _serial.println("address bus test failed! address ("+ String((uint32_t)&mem_base[i], HEX) + ")"); + __asm__ volatile ("BKPT"); + } + } + } else { + memset(mem_base, pattern, HW_SDRAM_SIZE); + } + + return true; +} + +SDRAMClass SDRAM; \ No newline at end of file diff --git a/libraries/Zephyr_SDRAM/src/SDRAM.h b/libraries/Zephyr_SDRAM/src/SDRAM.h new file mode 100644 index 00000000..853b705a --- /dev/null +++ b/libraries/Zephyr_SDRAM/src/SDRAM.h @@ -0,0 +1,27 @@ +#ifndef __SDRAM_H +#define __SDRAM_H + +#include "ea_malloc.h" + +#ifdef __cplusplus + +#include "Arduino.h" + +#define SDRAM_END_ADDRESS (0xc0800000) +#define SDRAM_START_ADDRESS (0xc0000000) +#define HW_SDRAM_SIZE (8 * 1024 * 1024) + +class SDRAMClass { +public: + SDRAMClass() {} + int begin(uint32_t start_address = SDRAM_START_ADDRESS); + void* malloc(size_t size); + void free(void* ptr); + bool test(bool fast = false, Stream& _serial = Serial); +private: + +}; +extern SDRAMClass SDRAM; + +#endif +#endif // __SDRAM_H diff --git a/libraries/ea_malloc/ea_malloc.h b/libraries/ea_malloc/ea_malloc.h new file mode 100644 index 00000000..1fd54287 --- /dev/null +++ b/libraries/ea_malloc/ea_malloc.h @@ -0,0 +1,46 @@ +/* +* Copyright © 2017 Embedded Artistry LLC. +* License: MIT. See LICENSE file for details. +*/ + +#ifndef MALLOC_H_ +#define MALLOC_H_ + +#ifdef __cplusplus +extern "C" { +#endif //__cplusplus + +#include + +/** +* @brief Assign blocks of memory for use by malloc(). +* +* Initializes the malloc() backend with a memory address and memory pool size. +* This memory is assumed to be owned by malloc() and is vended out when memory is requested. +* Multiple blocks can be added. +* +* NOTE: This API must be called before malloc() can be used. If you call malloc() before +* allocating memory, malloc() will return NULL because there is no available memory +* to provide to the user. +* +* @param addr Pointer to the memory block address that you are providing to malloc() +* @param size Size of the memory block that you are providing to malloc() +*/ +void malloc_addblock(void* addr, size_t size); + +/** +* @brief Initialize Malloc +* +* Weakly linked, can be overridden based on your needs. +* Each malloc implementation contains a different set of initialization requirements +*/ +void malloc_init(void); + +void* ea_malloc(size_t size); +void ea_free(void* ptr); + +#ifdef __cplusplus +} +#endif //__cplusplus + +#endif //MALLOC_H_ \ No newline at end of file diff --git a/libraries/ea_malloc/ll.h b/libraries/ea_malloc/ll.h new file mode 100644 index 00000000..a83be8ff --- /dev/null +++ b/libraries/ea_malloc/ll.h @@ -0,0 +1,367 @@ +#ifndef LL_H__ +#define LL_H__ + +#include +#include //size_t, NULL + +/** @defgroup linkedlist-C C Linked List Interface + * A linked list library for C modules + * + * @ingroup FrameworkUtils + * @{ + */ + +/** + * Define offsetof if we don't have it already + */ +#ifndef offsetof +#ifdef __compiler_offsetof +#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER) +#else +#define offsetof(TYPE, MEMBER) ((size_t) & ((TYPE*)0)->MEMBER) +#endif +#endif // offsetof + +/** + * Define container_of if we don't have it already + */ +#ifndef container_of +#ifdef __GNUC__ +#ifndef __clang__ +// Isolate the GNU-specific expression +#define container_of(ptr, type, member) \ + __extension__ ({ \ + const __typeof__(((type*)0)->member)* __mptr = (ptr); \ + (type*)((uintptr_t)__mptr - offsetof(type, member)); \ + }) +#else // we are clang - avoid GNU expression +#define container_of(ptr, type, member) ((type*)((uintptr_t)(ptr)-offsetof(type, member))) +#endif // GNU and not clang +#else +#define container_of(ptr, type, member) ((type*)((uintptr_t)(ptr)-offsetof(type, member))) +#endif // not GNU +#endif // container_of + +#ifdef __cplusplus +extern "C" { +#endif //__cplusplus + +/** Linked list struct + * + * This is a doubly linked list structure. + * The ll_t structure should be embedded in a container structure that you want to list. + * + * Example: + * + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + */ +typedef struct ll_head +{ + /// Pointer to the next element in the list. + struct ll_head* next; + /// Pointer to the previous element in the list. + struct ll_head* prev; +} ll_t; + +//#pragma mark - List Manipulation - + +/// @name Get Containers +/// @{ + +/** Get the container for a list entry + * + * @param[in] ptr The pointer to the target ll_t node. + * @param[in] type The struct type which contains the ll_t node. For this example struct, + * type would refer to alloc_node_t: + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + * + * @param[in] member The member which corresponds to the member name of the ll_t entry. For this + * example struct, member would refer to `node`. + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + * + * @returns a pointer to the struct containing the linked list node at `ptr`, cast to type `type`. + */ +#define list_entry(ptr, type, member) container_of(ptr, type, member) + +/** Get the container for the first item in the list + * + * @param[in] head The pointer to the head of the list. + * @param[in] type The struct type which contains the ll_t node. For this example struct, + * type would refer to alloc_node_t: + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + + * @param[in] member The member which corresponds to the member name of the ll_t entry. For this + * example struct, member would refer to `node`. + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + * + * @returns a pointer to the struct containing the linked list node at `ptr`, cast to type `type`. + */ +#define list_first_entry(head, type, member) list_entry((head)->next, type, member) + +/// @} +// Get containers + +//#pragma mark - Foreach - + +/// @name Foreach Operations +/// @{ + +/** Declare a foreach loop which iterates over the list + * + * list_for_each() will run as long as the current object's next pointer is not equal to the + * head of the list. It's possible for a malformed list to loop forever. + * + * @param[in] pos The variable which will hold the current iteration's position value. + * This variable must be a pointer and should be pre-declared before instantiating the loop. + * @code + * ll_t *b; + * list_for_each(b, &free_list) + * { + * ... + * } + * @endcode + * @param[in] head The head of of the linked list. Input should be a pointer. + */ +#define list_for_each(pos, head) for(pos = (head)->next; pos != (head); pos = pos->next) + +/** Declare a foreach loop which iterates over the list, copy current node pointer. + * + * list_for_each_safe() will run as long as the current object's next pointer is not equal to the + * head of the list. It's possible for a malformed list to loop forever. + * + * The list_for_each_safe() variant makes a copy of the current node pointer, enabling the loop + * to get to the next pointer if there is a deletion. + * + * @param[in] pos The variable which will hold the current iteration's position value. + * This variable must be a pointer should be pre-declared before instantiating the loop. + * @code + * ll_t *b, *t; + * list_for_each_safe(b, t, &free_list) + * { + * ... + * } + * @endcode + * @param[in] n The variable which will hold the current iteration's position value **copy**. + * This variable must be a pointer and should be pre-declared before instantiating the loop. + * @code + * alloc_node_t *b, *t; + * list_for_each_safe(b, t, &free_list) + * { + * ... + * } + * @endcode + * @param[in] head The head of of the linked list. Input should be a pointer. + */ +#define list_for_each_safe(pos, n, head) \ + for(pos = (head)->next, n = pos->next; pos != (head); pos = n, n = pos->next) + +/** Declare a for loop which operates on each node in the list using the container value. + * + * @param[in] pos The variable which will hold the current iteration's position value. + * This variable must be a pointer and should be pre-declared before instantiating the loop. + * The `pos` variable must be the container type. + * @code + * alloc_node_t *b, *t; + * list_for_each_entry(b, &free_list, node) + * { + * ... + * } + * @endcode + * + * @param[in] head The head of of the linked list. Input should be a pointer. + * + * @param[in] member The member which corresponds to the member name of the ll_t entry. For this + * example struct, member would refer to `node`. + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + */ +#define list_for_each_entry(pos, head, member) \ + for(pos = list_entry((head)->next, __typeof__(*pos), member); &pos->member != (head); \ + pos = list_entry(pos->member.next, __typeof__(*pos), member)) + +/** Declare a for loop which operates on each node in the list using a copy of the container value. + * + * @param[in] pos The variable which will hold the current iteration's position value. + * This variable must be a pointer and should be pre-declared before instantiating the loop. + * The `pos` variable must be the container type. + * @code + * alloc_node_t *b, *t; + * list_for_each_entry(b, &free_list, node) + * { + * ... + * } + * @endcode + * @param[in] n The variable which will hold the current iteration's position value **copy**. + * This variable must be a pointer and should be pre-declared before instantiating the loop. + * The `n` variable must be the container type. + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * + * alloc_node_t *b, *t; + * list_for_each_entrysafe(b, t, &free_list, node) + * { + * ... + * } + * @endcode + * @param[in] head The head of of the linked list. Input should be a pointer. + * @param[in] member The member which corresponds to the member name of the ll_t entry. For this + * example struct, member would refer to `node`. + * @code + * typedef struct + * { + * ll_t node; + * size_t size; + * char* block; + * } alloc_node_t; + * @endcode + */ +#define list_for_each_entry_safe(pos, n, head, member) \ + for(pos = list_entry((head)->next, __typeof__(*pos), member), \ + n = list_entry(pos->member.next, __typeof__(*pos), member); \ + &pos->member != (head); pos = n, n = list_entry(n->member.next, __typeof__(*n), member)) + +/// @} +// End foreach + +//#pragma mark - Init - + +/// @name Initialization +/// @{ + +/// Initialize a linked list so it points to itself +/// @param[in] name of the linked list object +#define ll_head_INIT(name) \ + { \ + &(name), &(name) \ + } + +/** Initialize a linked list + * + * @code + * // This macro declares and initializes our linked list + * static LIST_INIT(free_list); + * @endcode + * @param[in] name The name of the linked list object to declare + */ +#define LIST_INIT(name) struct ll_head name = ll_head_INIT(name) + +/// @} + +//#pragma mark - Add - + +/// @name Addition +/// @{ + +/// Insert a new element between two existing elements. +/// @param[in] n The node to add to the list. +/// @param[in] prev The pointer to the node before where the new node will be inserted. +/// @param[in] next The pointer to the new node after where the new node will be inserted. +static inline void list_insert(struct ll_head* n, struct ll_head* prev, struct ll_head* next) +{ + next->prev = n; + n->next = next; + n->prev = prev; + prev->next = n; +} + +/// Add a node to the front of the list +/// @param[in] n The node to add to the list. +/// @param[in] head The head of the list. +static inline void list_add(struct ll_head* n, struct ll_head* head) +{ + list_insert(n, head, head->next); +} + +/// Add a node to the end of the list +/// @param[in] n The node to add to the list. +/// @param[in] head The head of the list. +static inline void list_add_tail(struct ll_head* n, struct ll_head* head) +{ + list_insert(n, head->prev, head); +} + +/// @} + +//#pragma mark - Delete - + +/// @name Deletion +/// @{ + +/// Remove the node between two element pointers. +/// +/// Joins the `prev` and `next` elements together, effectively removing +/// the element in the middle. +/// +/// @param[in] prev The previous element in the list, which will now be joined to next. +/// @param[in] next The next element in the list, which will now be joined to prev. +static inline void list_join_nodes(struct ll_head* prev, struct ll_head* next) +{ + next->prev = prev; + prev->next = next; +} + +/// Remove an entry from the list +/// @param[in] entry The pointer to the entry to remove from the list. +static inline void list_del(struct ll_head* entry) +{ + list_join_nodes(entry->prev, entry->next); + entry->next = NULL; + entry->prev = NULL; +} + +/// @} + +/// @} +// end group + +#ifdef __cplusplus +} +#endif //__cplusplus + +#endif // LL_H__ diff --git a/libraries/ea_malloc/malloc_freelist.c b/libraries/ea_malloc/malloc_freelist.c new file mode 100644 index 00000000..4fb1f7b3 --- /dev/null +++ b/libraries/ea_malloc/malloc_freelist.c @@ -0,0 +1,168 @@ +/* + * Copyright © 2017 Embedded Artistry LLC. + * License: MIT. See LICENSE file for details. + */ + +#include +#include +#include +#include + +//#pragma mark - Definitions - + +/** + * Simple macro for making sure memory addresses are aligned + * to the nearest power of two + */ +#ifndef align_up +#define align_up(num, align) (((num) + ((align)-1)) & ~((align)-1)) +#endif + +/* + * This is the container for our free-list. + * Note the usage of the linked list here: the library uses offsetof + * and container_of to manage the list and get back to the parent struct. + */ +typedef struct +{ + ll_t node; + size_t size; + char* block; +} alloc_node_t; + +/** + * We vend a memory address to the user. This lets us translate back and forth + * between the vended pointer and the container we use for managing the data. + */ +#define ALLOC_HEADER_SZ offsetof(alloc_node_t, block) + +// We are enforcing a minimum allocation size of 32B. +#define MIN_ALLOC_SZ ALLOC_HEADER_SZ + 32 + +//#pragma mark - Prototypes - + +static void defrag_free_list(void); + +//#pragma mark - Declarations - + +// This macro simply declares and initializes our linked list +static LIST_INIT(free_list); + +//#pragma mark - Private Functions - + +/** + * When we free, we can take our node and check to see if any memory blocks + * can be combined into larger blocks. This will help us fight against + * memory fragmentation in a simple way. + */ +void defrag_free_list(void) +{ + alloc_node_t* b; + alloc_node_t* lb = NULL; + alloc_node_t* t; + + list_for_each_entry_safe(b, t, &free_list, node) + { + if(lb) + { + if((((uintptr_t)&lb->block) + lb->size) == (uintptr_t)b) + { + lb->size += ALLOC_HEADER_SZ + b->size; + list_del(&b->node); + continue; + } + } + lb = b; + } +} + +//#pragma mark - APIs - + +__attribute__((weak)) void malloc_init(void) +{ + // Unused here, override to specify your own init functin + // Which includes malloc_addblock calls +} + +void* ea_malloc(size_t size) +{ + void* ptr = NULL; + alloc_node_t* blk = NULL; + + if(size > 0) + { + // Align the pointer + size = align_up(size, sizeof(void*)); + + // try to find a big enough block to alloc + list_for_each_entry(blk, &free_list, node) + { + if(blk->size >= size) + { + ptr = &blk->block; + break; + } + } + + // we found something + if(ptr) + { + // Can we split the block? + if((blk->size - size) >= MIN_ALLOC_SZ) + { + alloc_node_t* new_blk; + new_blk = (alloc_node_t*)((uintptr_t)(&blk->block) + size); + new_blk->size = blk->size - size - ALLOC_HEADER_SZ; + blk->size = size; + list_insert(&new_blk->node, &blk->node, blk->node.next); + } + + list_del(&blk->node); + } + + } // else NULL + + return ptr; +} + +void ea_free(void* ptr) +{ + alloc_node_t* free_blk; + alloc_node_t* blk; + + // Don't free a NULL pointer.. + if(ptr) + { + // we take the pointer and use container_of to get the corresponding alloc block + blk = container_of(ptr, alloc_node_t, block); + + // Let's put it back in the proper spot + list_for_each_entry(free_blk, &free_list, node) + { + if(free_blk > blk) + { + list_insert(&blk->node, free_blk->node.prev, &free_blk->node); + goto blockadded; + } + } + list_add_tail(&blk->node, &free_list); + + blockadded: + // Let's see if we can combine any memory + defrag_free_list(); + } +} + +void malloc_addblock(void* addr, size_t size) +{ + alloc_node_t* blk; + + // let's align the start address of our block to the next pointer aligned number + blk = (void*)align_up((uintptr_t)addr, sizeof(void*)); + + // calculate actual size - remove our alignment and our header space from the availability + blk->size = (uintptr_t)addr + size - (uintptr_t)blk - ALLOC_HEADER_SZ; + + // and now our giant block of memory is added to the list! + list_add(&blk->node, &free_list); +} diff --git a/loader/boards/arduino_giga_r1_m7.conf b/loader/boards/arduino_giga_r1_m7.conf index 7b3f94ea..f9855f66 100644 --- a/loader/boards/arduino_giga_r1_m7.conf +++ b/loader/boards/arduino_giga_r1_m7.conf @@ -10,6 +10,10 @@ CONFIG_UART_LINE_CTRL=y CONFIG_CDC_ACM_DTE_RATE_CALLBACK_SUPPORT=y CONFIG_LLEXT_STORAGE_WRITABLE=n +CONFIG_HEAP_MEM_POOL_SIZE=2048 +CONFIG_SHELL_STACK_SIZE=32768 +CONFIG_MAIN_STACK_SIZE=32768 +CONFIG_LLEXT_HEAP_SIZE=128 CONFIG_FPU=y @@ -22,4 +26,10 @@ CONFIG_MEMC=y #CONFIG_VIDEO=y CONFIG_VIDEO_STM32_DCMI=y CONFIG_VIDEO_BUFFER_POOL_NUM_MAX=1 -CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=160000 \ No newline at end of file +CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=160000 + +CONFIG_ENTROPY_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y + +CONFIG_CPP=y +CONFIG_STD_CPP17=y \ No newline at end of file diff --git a/loader/boards/arduino_giga_r1_m7.overlay b/loader/boards/arduino_giga_r1_m7.overlay index f6711d65..0f6a138f 100644 --- a/loader/boards/arduino_giga_r1_m7.overlay +++ b/loader/boards/arduino_giga_r1_m7.overlay @@ -27,6 +27,7 @@ status = "okay"; }; + &i2c4 { status = "okay"; ov7670: ov7670@21 { @@ -258,6 +259,47 @@ }; }; + +&fmc { + status = "okay"; + pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 + &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_ph2 + &fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15 + + &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4 + &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14 + &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2 + &fmc_a14_pg4 &fmc_a15_pg5 + + &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1 + &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10 + &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14 + &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>; + pinctrl-names = "default"; + + sdram { + status = "okay"; + + power-up-delay = <100>; + num-auto-refresh = <8>; + mode-register = <0x220>; + refresh-rate = <603>; + + bank@0 { + reg = <0>; + st,sdram-control = ; + st,sdram-timing = <2 6 4 6 2 2 2>; + }; + }; +}; + /{ chosen { zephyr,camera = &dcmi; diff --git a/loader/llext_exports.c b/loader/llext_exports.c index 0c9d4b5a..4d04336f 100644 --- a/loader/llext_exports.c +++ b/loader/llext_exports.c @@ -21,8 +21,15 @@ EXPORT_SYMBOL(strtoul); EXPORT_SYMBOL(strcmp); EXPORT_SYMBOL(strlen); EXPORT_SYMBOL(strchr); +EXPORT_SYMBOL(strcat); +EXPORT_SYMBOL(strtok); +EXPORT_SYMBOL(strtol); + EXPORT_SYMBOL(memmove); +EXPORT_SYMBOL(memcpy); +EXPORT_SYMBOL(memset); +EXPORT_SYMBOL(k_malloc); EXPORT_SYMBOL(malloc); EXPORT_SYMBOL(realloc); EXPORT_SYMBOL(calloc); @@ -30,6 +37,7 @@ EXPORT_SYMBOL(free); EXPORT_SYMBOL(rand); EXPORT_SYMBOL(srand); +EXPORT_SYMBOL(atoi); EXPORT_SYMBOL(atof); EXPORT_SYMBOL(atol); EXPORT_SYMBOL(isspace); @@ -42,8 +50,10 @@ EXPORT_SYMBOL(isdigit); EXPORT_SYMBOL(isgraph); EXPORT_SYMBOL(isprint); EXPORT_SYMBOL(isupper); +EXPORT_SYMBOL(islower); EXPORT_SYMBOL(isxdigit); + #if defined(CONFIG_USB_DEVICE_STACK) EXPORT_SYMBOL(usb_enable); EXPORT_SYMBOL(usb_disable); @@ -54,6 +64,8 @@ EXPORT_SYMBOL(z_log_msg_runtime_vcreate); #if defined(CONFIG_NETWORKING) FORCE_EXPORT_SYM(net_if_foreach); FORCE_EXPORT_SYM(net_if_get_by_iface); +//FORCE_EXPORT_SYM(net_if_ipv4_maddr_add); +//FORCE_EXPORT_SYM(net_if_ipv4_maddr_join); #endif #if defined(CONFIG_NET_DHCPV4) @@ -65,14 +77,26 @@ FORCE_EXPORT_SYM(net_dhcpv4_add_option_callback); #if defined(CONFIG_NET_MGMT_EVENT) FORCE_EXPORT_SYM(net_mgmt_add_event_callback); +FORCE_EXPORT_SYM(net_mgmt_event_wait_on_iface); +#endif + +#if defined(CONFIG_MBEDTLS) +FORCE_EXPORT_SYM(tls_credential_add); +#endif + +#if defined(CONFIG_WIFI) +FORCE_EXPORT_SYM(net_if_get_wifi_sta); +FORCE_EXPORT_SYM(net_mgmt_NET_REQUEST_WIFI_CONNECT); +FORCE_EXPORT_SYM(net_mgmt_NET_REQUEST_WIFI_IFACE_STATUS); #endif #if defined(CONFIG_BT) FORCE_EXPORT_SYM(bt_enable_raw); FORCE_EXPORT_SYM(bt_hci_raw_set_mode); -FORCE_EXPORT_SYM(bt_send); +FORCE_EXPORT_SYM(bt_send) FORCE_EXPORT_SYM(net_buf_get); FORCE_EXPORT_SYM(bt_buf_get_tx); +FORCE_EXPORT_SYM(bt_conn_get_dst); FORCE_EXPORT_SYM(net_buf_simple_pull); FORCE_EXPORT_SYM(net_buf_simple_add_mem); FORCE_EXPORT_SYM(net_buf_simple_pull_mem); @@ -98,6 +122,9 @@ FORCE_EXPORT_SYM(bind); FORCE_EXPORT_SYM(listen); EXPORT_SYMBOL(exit); FORCE_EXPORT_SYM(inet_pton); +FORCE_EXPORT_SYM(sendto); +FORCE_EXPORT_SYM(recvfrom); +FORCE_EXPORT_SYM(setsockopt); #endif #if defined(CONFIG_CDC_ACM_DTE_RATE_CALLBACK_SUPPORT) @@ -106,6 +133,7 @@ FORCE_EXPORT_SYM(cdc_acm_dte_rate_callback_set); EXPORT_SYMBOL(k_timer_init); EXPORT_SYMBOL(k_fatal_halt); +EXPORT_SYMBOL(k_work_schedule); //FORCE_EXPORT_SYM(k_timer_user_data_set); //FORCE_EXPORT_SYM(k_timer_start); @@ -120,7 +148,7 @@ EXPORT_SYMBOL(printf); EXPORT_SYMBOL(sprintf); EXPORT_SYMBOL(snprintf); EXPORT_SYMBOL(cbvprintf); - +; FORCE_EXPORT_SYM(abort); #if defined(CONFIG_RING_BUFFER) FORCE_EXPORT_SYM(ring_buf_get); @@ -153,3 +181,5 @@ FORCE_EXPORT_SYM(__aeabi_d2iz); FORCE_EXPORT_SYM(__aeabi_f2d); FORCE_EXPORT_SYM(__aeabi_idivmod); FORCE_EXPORT_SYM(__aeabi_ldivmod); +FORCE_EXPORT_SYM(__aeabi_ul2f); +FORCE_EXPORT_SYM(__cxa_pure_virtual); \ No newline at end of file diff --git a/samples/analog_input/CMakeLists.txt b/samples/analog_input/CMakeLists.txt deleted file mode 100644 index 83ac0d6b..00000000 --- a/samples/analog_input/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(analog_input) - -target_sources(app PRIVATE src/main.cpp) -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/analog_input/README.rst b/samples/analog_input/README.rst deleted file mode 100644 index 51349e48..00000000 --- a/samples/analog_input/README.rst +++ /dev/null @@ -1,24 +0,0 @@ -.. _analog_input: - -Analog Input -############ - -Overview -******** - -The analog_input sample blinks the LED with control of the period -by the voltage of the input pin. -Inputting high voltage to blink the LED slowly. -Blink the LED fast on input voltage is low. -When the input is 0V, LED light. - -Building and Running -******************** - -Build and flash analog_input sample as follows, - -```sh -$> west build -p -b arduino_nano_33_ble sample/analog_input/ - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` diff --git a/samples/analog_input/prj.conf b/samples/analog_input/prj.conf deleted file mode 100644 index 7db48201..00000000 --- a/samples/analog_input/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ADC=y -CONFIG_ARDUINO_API=y diff --git a/samples/analog_input/src/main.cpp b/samples/analog_input/src/main.cpp deleted file mode 100644 index 9cc23dae..00000000 --- a/samples/analog_input/src/main.cpp +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2022 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -const int analog_input = A0; // select the input pin for the potentiometer -const int ledPin = LED_BUILTIN; // select the pin for the LED -const float wait_factor = 1.f; - -void setup() { - pinMode(ledPin, OUTPUT); -} - -void loop() { - int value = 0; - - value = analogRead(analog_input); - - /* Blinks slowly when the input voltage is high */ - - digitalWrite(ledPin, HIGH); - delay(value * wait_factor); - - digitalWrite(ledPin, LOW); - delay(value * wait_factor); -} diff --git a/samples/attach_interrupt/CMakeLists.txt b/samples/attach_interrupt/CMakeLists.txt deleted file mode 100644 index 711b9673..00000000 --- a/samples/attach_interrupt/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(attach_interrupt) - -target_sources(app PRIVATE src/main.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/attach_interrupt/README.rst b/samples/attach_interrupt/README.rst deleted file mode 100644 index f85d738a..00000000 --- a/samples/attach_interrupt/README.rst +++ /dev/null @@ -1,22 +0,0 @@ -.. _attach_interrupt-sample: - -AttachInterrupt -###### - -Overview -******** - -This sample demonstrates how to use attachInterrupt API. - -Building and Running -******************** - -Build and flash attachInterrupt sample as follows, - -```sh -$> west build -p -b arduino_nano_33_ble samples/basic/attach_interrupt/ -DZEPHYR_EXTRA_MODULES=/home/$USER/zephyrproject/modules/lib/Arduino-Core-Zephyr - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` - -Turn on the LED by detecting interrupts. And Turn off the next interrupt. diff --git a/samples/attach_interrupt/prj.conf b/samples/attach_interrupt/prj.conf deleted file mode 100644 index f93fa321..00000000 --- a/samples/attach_interrupt/prj.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_ARDUINO_API=y diff --git a/samples/attach_interrupt/src/main.cpp b/samples/attach_interrupt/src/main.cpp deleted file mode 100644 index 3d803dbb..00000000 --- a/samples/attach_interrupt/src/main.cpp +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2022 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -const pin_size_t ledPin = LED_BUILTIN; -const pin_size_t interruptPin = 2; -PinStatus state = LOW; - -void blink() { - state = (state == LOW) ? HIGH : LOW; - digitalWrite(ledPin, state); -} - -void setup() { - pinMode(ledPin, OUTPUT); - pinMode(interruptPin, INPUT_PULLUP); - attachInterrupt(interruptPin, blink, CHANGE); -} - -void loop() { -} diff --git a/samples/blinky_arduino/CMakeLists.txt b/samples/blinky_arduino/CMakeLists.txt deleted file mode 100644 index e5c58ee3..00000000 --- a/samples/blinky_arduino/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(blinky) - -target_sources(app PRIVATE src/main.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/blinky_arduino/README.rst b/samples/blinky_arduino/README.rst deleted file mode 100644 index 67027e57..00000000 --- a/samples/blinky_arduino/README.rst +++ /dev/null @@ -1,71 +0,0 @@ -.. _blinky-sample: - -Blinky -###### - -Overview -******** - -This Arduino Blinky sample blinks an LED forever using the `ArduinoAPI`. - -Requirements -************ - -Your board must: - -#. Have an LED connected via a GPIO pin (these are called "User LEDs" on many of - Zephyr's :ref:`boards`). -#. Have the LED configured using the ``led0`` devicetree alias. - -Building and Running -******************** - -Build and flash Blinky as follows, - -```sh -$> west build -p -b arduino_nano_33_ble samples/basic/arduino-blinky/ -DZEPHYR_EXTRA_MODULES=/home/$USER/zephyrproject/modules/lib/Arduino-Core-Zephyr - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` - -After flashing, the LED starts to blink. If a runtime error occurs, the sample -exits without printing to the console. - -Adding board support -******************** - -To add support for your board, add something like this to your devicetree: - -.. code-block:: DTS - - / { - aliases { - led0 = &myled0; - }; - - leds { - compatible = "gpio-leds"; - myled0: led_0 { - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - }; - }; - -The above sets your board's ``led0`` alias to use pin 13 on GPIO controller -``gpio0``. The pin flags :c:macro:`GPIO_ACTIVE_HIGH` mean the LED is on when -the pin is set to its high state, and off when the pin is in its low state. - -Tips: - -- See :dtcompatible:`gpio-leds` for more information on defining GPIO-based LEDs - in devicetree. - -- If you're not sure what to do, check the devicetrees for supported boards which - use the same SoC as your target. See :ref:`get-devicetree-outputs` for details. - -- See :zephyr_file:`include/zephyr/dt-bindings/gpio/gpio.h` for the flags you can use - in devicetree. - -- If the LED is built in to your board hardware, the alias should be defined in - your :ref:`BOARD.dts file `. Otherwise, you can - define one in a :ref:`devicetree overlay `. diff --git a/samples/blinky_arduino/prj.conf b/samples/blinky_arduino/prj.conf deleted file mode 100644 index 290d61a3..00000000 --- a/samples/blinky_arduino/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_GPIO=y -CONFIG_ARDUINO_API=y diff --git a/samples/blinky_arduino/src/main.cpp b/samples/blinky_arduino/src/main.cpp deleted file mode 100644 index b3c1103e..00000000 --- a/samples/blinky_arduino/src/main.cpp +++ /dev/null @@ -1,19 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Blink inbuilt LED example */ - -#include - -/* 1000 msec = 1 sec */ -#define SLEEP_TIME_MS 1000 - -void setup() { pinMode(LED_BUILTIN, OUTPUT); } - -void loop() { - digitalWrite(LED_BUILTIN, HIGH); - delay(SLEEP_TIME_MS); - digitalWrite(LED_BUILTIN, LOW); - delay(SLEEP_TIME_MS); -} \ No newline at end of file diff --git a/samples/button_press_led/CMakeLists.txt b/samples/button_press_led/CMakeLists.txt deleted file mode 100644 index e5c58ee3..00000000 --- a/samples/button_press_led/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(blinky) - -target_sources(app PRIVATE src/main.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/button_press_led/README.rst b/samples/button_press_led/README.rst deleted file mode 100644 index f3cef794..00000000 --- a/samples/button_press_led/README.rst +++ /dev/null @@ -1,67 +0,0 @@ -Button press LED -###### - -Overview -******** - -This Arduino sample turns ON an LED if button pressed using the `ArduinoAPI`. - -Requirements -************ - -Your board must: - -#. Have an LED connected via a GPIO pin (these are called "User LEDs" on many of - Zephyr's :ref:`boards`). -#. Have the LED configured using the ``led0`` devicetree alias. -#. Have a button connected to pin `D9` of the arduino externally (pulled down by default) - -Building and Running -******************** - -Build and flash as follows, - -```sh -$> west build -p -b arduino_nano_33_ble samples/button_press_led -DZEPHYR_EXTRA_MODULES=/home/$USER/zephyrproject/modules/lib/Arduino-Core-Zephyr - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` - -Adding board support -******************** - -To add support for your board, add something like this to your devicetree: - -.. code-block:: DTS - - / { - aliases { - led0 = &myled0; - }; - - leds { - compatible = "gpio-leds"; - myled0: led_0 { - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - }; - }; - }; - -The above sets your board's ``led0`` alias to use pin 13 on GPIO controller -``gpio0``. The pin flags :c:macro:`GPIO_ACTIVE_HIGH` mean the LED is on when -the pin is set to its high state, and off when the pin is in its low state. - -Tips: - -- See :dtcompatible:`gpio-leds` for more information on defining GPIO-based LEDs - in devicetree. - -- If you're not sure what to do, check the devicetrees for supported boards which - use the same SoC as your target. See :ref:`get-devicetree-outputs` for details. - -- See :zephyr_file:`include/zephyr/dt-bindings/gpio/gpio.h` for the flags you can use - in devicetree. - -- If the LED is built in to your board hardware, the alias should be defined in - your :ref:`BOARD.dts file `. Otherwise, you can - define one in a :ref:`devicetree overlay `. diff --git a/samples/button_press_led/prj.conf b/samples/button_press_led/prj.conf deleted file mode 100644 index 290d61a3..00000000 --- a/samples/button_press_led/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_GPIO=y -CONFIG_ARDUINO_API=y diff --git a/samples/button_press_led/src/main.cpp b/samples/button_press_led/src/main.cpp deleted file mode 100644 index 9440ceea..00000000 --- a/samples/button_press_led/src/main.cpp +++ /dev/null @@ -1,34 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Button Press turns on inbuilt LED example */ - -#include - -const int buttonPin = D9; // the number of the pushbutton pin -const int ledPin = 13; // the number of the LED pin - -// variables will change: -int buttonState = 0; // variable for reading the pushbutton status - -void setup() { - // initialize the LED pin as an output: - pinMode(ledPin, OUTPUT); - // initialize the pushbutton pin as an input: - pinMode(buttonPin, INPUT); -} - -void loop() { - // read the state of the pushbutton value: - buttonState = digitalRead(buttonPin); - - // check if the pushbutton is pressed. If it is, the buttonState is HIGH: - if (buttonState == HIGH) { - // turn LED on: - digitalWrite(ledPin, HIGH); - } else { - // turn LED off: - digitalWrite(ledPin, LOW); - } -} diff --git a/samples/fade/CMakeLists.txt b/samples/fade/CMakeLists.txt deleted file mode 100644 index 6f3c4cff..00000000 --- a/samples/fade/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(fade) - -target_sources(app PRIVATE src/app.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/fade/README.rst b/samples/fade/README.rst deleted file mode 100644 index 8de33953..00000000 --- a/samples/fade/README.rst +++ /dev/null @@ -1,21 +0,0 @@ -.. _fade: - -Fade -#### - -Overview -******** - -The Fade sample gradually increases/decreases the voltage of the output pin. -When connecting the LED to the output pin, the LED blinks gradually. - -Building and Running -******************** - -Build and flash Fade sample as follows, - -```sh -$> west build -p -b arduino_nano_33_ble samples/basic/fade/ -DZEPHYR_EXTRA_MODULES=/home/$USER/zephyrproject/modules/lib/Arduino-Core-Zephyr - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` diff --git a/samples/fade/prj.conf b/samples/fade/prj.conf deleted file mode 100644 index cd969855..00000000 --- a/samples/fade/prj.conf +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARDUINO_API=y -CONFIG_PWM=y diff --git a/samples/fade/src/app.cpp b/samples/fade/src/app.cpp deleted file mode 100644 index e812dcd0..00000000 --- a/samples/fade/src/app.cpp +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2022 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -const int led = 3; // PWM output pin. -const int increments = 5; -const int wait_ms = 10; - -void setup() { - /* Pin that use as the PWM output need not be configured by pinMode() */ -} - -void loop() { - int value = 0; - while (value < 256) { - analogWrite(led, value); - value += increments; - delay(wait_ms); - } - - value = 255; - while (value >= 0) { - analogWrite(led, value); - value -= increments; - delay(wait_ms); - } -} diff --git a/samples/hello_arduino/CMakeLists.txt b/samples/hello_arduino/CMakeLists.txt deleted file mode 100644 index 0675b10d..00000000 --- a/samples/hello_arduino/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(hello_world) - -target_sources(app PRIVATE src/app.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/hello_arduino/README.rst b/samples/hello_arduino/README.rst deleted file mode 100644 index ce5423d6..00000000 --- a/samples/hello_arduino/README.rst +++ /dev/null @@ -1,33 +0,0 @@ -.. _hello_world: - -Hello World -########### - -Overview -******** - -A simple sample that can be used with any :ref:`supported board ` and -prints "Hello World" to the console. - -Building and Running -******************** - -This application can be built and executed on QEMU as follows: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :host-os: unix - :board: qemu_x86 - :goals: run - :compact: - -To build for another board, change "qemu_x86" above to that board's name. - -Sample Output -============= - -.. code-block:: console - - Hello World! x86 - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. diff --git a/samples/hello_arduino/prj.conf b/samples/hello_arduino/prj.conf deleted file mode 100644 index f93fa321..00000000 --- a/samples/hello_arduino/prj.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_ARDUINO_API=y diff --git a/samples/hello_arduino/src/app.cpp b/samples/hello_arduino/src/app.cpp deleted file mode 100644 index aa7cd536..00000000 --- a/samples/hello_arduino/src/app.cpp +++ /dev/null @@ -1,29 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include "zephyrSerial.h" - - -void setup() { - // put your setup code here, to run once: - Serial.begin(115200); // dummy as of now, need to study and refer https://docs.zephyrproject.org/latest/hardware/peripherals/uart.html -} -void loop() { - char c = 'D'; - size_t ret1; - size_t ret2; - ret1 = Serial.print(c); - ret2 = Serial.println("Hello, World!"); - printk("Sizes: %d %d\n", ret1, ret2); - Serial.println(); - ret1 = Serial.print("My letter is: "); - ret2 = Serial.println(c); - printk("Sizes: %d %d\n", ret1, ret2); - Serial.println(); - char myString[] = "Will it print?"; - ret1 = Serial.println(myString); - printk("Size: %d \n\n\n", ret1); - delay(1000); // 1 second delay -} diff --git a/samples/i2cdemo/CMakeLists.txt b/samples/i2cdemo/CMakeLists.txt deleted file mode 100644 index e79ab241..00000000 --- a/samples/i2cdemo/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(blinky) - -target_sources(app PRIVATE src/main.cpp) -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/i2cdemo/README.rst b/samples/i2cdemo/README.rst deleted file mode 100644 index 41c6cb43..00000000 --- a/samples/i2cdemo/README.rst +++ /dev/null @@ -1,28 +0,0 @@ -i2c demo -###### - -Overview -******** - -This Arduino i2c sample gets data from an ADXL345 sensor connected over `i2c0`. - -Requirements -************ - -Your board must: - -#. Have atleast 1 i2c port. -#. Have the ADXL345 sensor connected to the I2C port. - -Building and Running -******************** - -Build and flash Blinky as follows, - -```sh -$> west build -p -b arduino_nano_33_ble samples/i2cdemo - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` - -After flashing, probe the UART pin (TX) and you should be able to see X, Y and Z values if everything goes well. diff --git a/samples/i2cdemo/prj.conf b/samples/i2cdemo/prj.conf deleted file mode 100644 index d546d036..00000000 --- a/samples/i2cdemo/prj.conf +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GPIO=y -CONFIG_ARDUINO_API=y -CONFIG_I2C=y -CONFIG_NEWLIB_LIBC=y -CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y -CONFIG_RING_BUFFER=y diff --git a/samples/i2cdemo/src/main.cpp b/samples/i2cdemo/src/main.cpp deleted file mode 100644 index 6f3f4c79..00000000 --- a/samples/i2cdemo/src/main.cpp +++ /dev/null @@ -1,118 +0,0 @@ -/* Blink inbuilt LED example */ - -#include -#include "Wire.h" - -void setup() -{ - printf("\n\nSetup begins\n"); - Wire.begin(); - // initialize the LED pin as an output: - - // initialize the pushbutton pin as an input: - // pinMode(buttonPin, INPUT); - // pinMode(ledPin, OUTPUT); - Wire.beginTransmission(0x53); - Wire.write(0x2C); - Wire.write(0x08); - Wire.endTransmission(); - - Wire.beginTransmission(0x53); - Wire.write(0x31); - Wire.write(0x08); - Wire.endTransmission(); - - Wire.beginTransmission(0x53); - Wire.write(0x2D); - Wire.write(0x08); - Wire.endTransmission(); - printf("\n\nSetup COMPLETE\n\n\n"); -} - -void loop() -{ - Wire.beginTransmission(0x53); -Wire.write(0x32); -Wire.endTransmission(); -// printf("\n\nrequesting from 53\n\n\n"); -Wire.requestFrom(0x53, 1); -byte x0 = Wire.read(); - -Wire.beginTransmission(0x53); -Wire.write(0x33); -Wire.endTransmission(); -Wire.requestFrom(0x53, 1); -byte x1 = Wire.read(); -x1 = x1 & 0x03; - -uint16_t x = (x1 << 8) + x0; -int16_t xf = x; -if(xf > 511) -{ -xf = xf - 1024; -} -float xa = xf * 0.004; -printf("\n\nX = %f\n",xa); -// Serial.print("X = "); -// Serial.print(xa); -// Serial.print(" g"); -// Serial.println(); - - -Wire.beginTransmission(0x53); -Wire.write(0x34); -Wire.endTransmission(); -Wire.requestFrom(0x53, 1); -byte y0 = Wire.read(); - -Wire.beginTransmission(0x53); -Wire.write(0x35); -Wire.endTransmission(); -Wire.requestFrom(0x53, 1); -byte y1 = Wire.read(); -y1 = y1 & 0x03; - -uint16_t y = (y1 << 8) + y0; -int16_t yf = y; -if(yf > 511) -{ -yf = yf - 1024; -} -float ya = yf * 0.004; -// printk("Y = %f\n",ya); -printf("Y = %f\n",ya); -// printf("\n\nYa = %f\n\n\n",ya); -// Serial.print("Y = "); -// Serial.print(ya); -// Serial.print(" g"); -// Serial.println(); - -Wire.beginTransmission(0x53); -Wire.write(0x36); -Wire.endTransmission(); -Wire.requestFrom(0x53, 1); -byte z0 = Wire.read(); - -Wire.beginTransmission(0x53); -Wire.write(0x37); -Wire.endTransmission(); -Wire.requestFrom(0x53, 1); -byte z1 = Wire.read(); -z1 = z1 & 0x03; - -uint16_t z = (z1 << 8) + z0; -int16_t zf = z; -if(zf > 511) -{ -zf = zf - 1024; -} -float za = zf * 0.004; -printf("Z = %f\n\n",za); -// Serial.print("Z = "); -// Serial.print(za); -// Serial.print(" g"); -// Serial.println(); -// Serial.println(); -delay(500); - -} \ No newline at end of file diff --git a/samples/serial_event/CMakeLists.txt b/samples/serial_event/CMakeLists.txt deleted file mode 100644 index a275e3cc..00000000 --- a/samples/serial_event/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(serial_event) - -target_sources(app PRIVATE src/app.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/serial_event/README.rst b/samples/serial_event/README.rst deleted file mode 100644 index e4dde008..00000000 --- a/samples/serial_event/README.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. _serial_event: - -Serial Event -############ - -Overview -******** - -The serial_event sample echo back serial input data. - -Building and Running -******************** - -Build and flash serial_event sample as follows, - -```sh -$> west build -p -b arduino_nano_33_ble sample/serial_event/ - -$> west flash --bossac=/home/$USER/.arduino15/packages/arduino/tools/bossac/1.9.1-arduino2/bossac -``` diff --git a/samples/serial_event/prj.conf b/samples/serial_event/prj.conf deleted file mode 100644 index f93fa321..00000000 --- a/samples/serial_event/prj.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_ARDUINO_API=y diff --git a/samples/serial_event/src/app.cpp b/samples/serial_event/src/app.cpp deleted file mode 100644 index 602d378a..00000000 --- a/samples/serial_event/src/app.cpp +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2022 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -void setup() { - Serial.begin(115200); -} - -void loop() { -} - -void serialEvent() { - while(Serial.available()) { - Serial.print((char)Serial.read()); - } -} diff --git a/samples/spi_controller/CMakeLists.txt b/samples/spi_controller/CMakeLists.txt deleted file mode 100644 index 824634e5..00000000 --- a/samples/spi_controller/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(spi_controller) - -target_sources(app PRIVATE src/app.cpp) - -zephyr_compile_options(-Wno-unused-variable -Wno-comment) diff --git a/samples/spi_controller/README.rst b/samples/spi_controller/README.rst deleted file mode 100644 index 8d2aad33..00000000 --- a/samples/spi_controller/README.rst +++ /dev/null @@ -1,9 +0,0 @@ -.. _spi_controller: - -SPI Controller -############### - -Overview -******** - -A simple sample that sends incrementing byte to SPI peripheral. diff --git a/samples/spi_controller/prj.conf b/samples/spi_controller/prj.conf deleted file mode 100644 index 661fb228..00000000 --- a/samples/spi_controller/prj.conf +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_CPLUSPLUS=y -CONFIG_ARDUINO_API=y -CONFIG_SPI=y -CONFIG_LOG=y -CONFIG_LOG_OUTPUT=y -CONFIG_LOG_MODE_IMMEDIATE=y diff --git a/samples/spi_controller/src/app.cpp b/samples/spi_controller/src/app.cpp deleted file mode 100644 index d0306512..00000000 --- a/samples/spi_controller/src/app.cpp +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2024 Ayush Singh - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "SPI.h" -#include - -#define CHIPSELECT 3 - -static uint8_t data = 0; - -void setup() { - SPI.begin(); - pinMode(CHIPSELECT, OUTPUT); - digitalWrite(CHIPSELECT, HIGH); -} - -void loop() { - SPI.beginTransaction(SPISettings(2000000, MSBFIRST, SPI_MODE0)); - digitalWrite(CHIPSELECT, LOW); - SPI.transfer(data++); - digitalWrite(CHIPSELECT, HIGH); - SPI.endTransaction(); - delay(1000); -} diff --git a/samples/threads_arduino/CMakeLists.txt b/samples/threads_arduino/CMakeLists.txt deleted file mode 100644 index f9aea636..00000000 --- a/samples/threads_arduino/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) - -cmake_path(SET ZephyrBase $ENV{ZEPHYR_BASE}) -set(DTC_OVERLAY_FILE ${ZephyrBase}/../modules/lib/Arduino-Zephyr-API/variants/${BOARD}/${BOARD}.overlay) - -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(threads) - -target_sources(app PRIVATE src/main.cpp) -zephyr_compile_options(-Wno-unused-variable -Wno-comment) \ No newline at end of file diff --git a/samples/threads_arduino/README.rst b/samples/threads_arduino/README.rst deleted file mode 100644 index 670cd23d..00000000 --- a/samples/threads_arduino/README.rst +++ /dev/null @@ -1,47 +0,0 @@ -.. _arduino_nano_33_ble_multi_thread_blinky: - -Basic Thread Example -#################### - -Overview -******** - -This example demonstrates spawning multiple threads using -:c:func:`K_THREAD_DEFINE`. It spawns three threads. Each thread is then defined -at compile time using `K_THREAD_DEFINE`. - -These three each control an LED. These LEDs, ``LED_BUILTIN``, ``D10`` and ``D11``, have -loop control and timing logic controlled by separate functions. - -- ``blink0()`` controls ``LED_BUILTIN`` and has a 100ms sleep cycle -- ``blink1()`` controls ``D11`` and has a 1000ms sleep cycle -- ``loop()`` controls ``D10`` and has a 300ms sleep cycle - -Requirements -************ - -The board must have two LEDs connected via GPIO pins and one builtin LED. These are called "User -LEDs" on many of Zephyr's :ref:`boards`. The LEDs must be mapped using the `` -``LED_BUILTIN``, ``D10`` and ``D11`` to the :ref:`devicetree ` aliases, in the -variants folder. - -You will see one of these errors if you try to build this sample for an -unsupported board: - -.. code-block:: none - - Unsupported board: LED_BUILTIN devicetree alias is not defined - Unsupported board: D11 devicetree alias is not defined - -Building -******** - -For example, to build this sample for :ref:`arduino_nano_33_ble`: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/arduino-threads - :board: arduino_nano_33_ble - :goals: build flash - :compact: - -Change ``arduino_nano_33_ble`` appropriately for other supported boards. diff --git a/samples/threads_arduino/prj.conf b/samples/threads_arduino/prj.conf deleted file mode 100644 index 2d0830d4..00000000 --- a/samples/threads_arduino/prj.conf +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_HEAP_MEM_POOL_SIZE=256 -CONFIG_GPIO=y -CONFIG_ARDUINO_API=y diff --git a/samples/threads_arduino/src/main.cpp b/samples/threads_arduino/src/main.cpp deleted file mode 100644 index 7fa01650..00000000 --- a/samples/threads_arduino/src/main.cpp +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2022 Dhruva Gole - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -/* size of stack area used by each thread */ -#define STACKSIZE 1024 - -/* scheduling priority used by each thread */ -#define PRIORITY 7 - -void blink0(void) -{ - while (1) { - digitalWrite(LED_BUILTIN, HIGH); - delay(100); - digitalWrite(LED_BUILTIN, LOW); - delay(100); - } -} - -void blink1(void) -{ - while (1) { - digitalWrite(D11, HIGH); - delay(1000); - digitalWrite(D11, LOW); - delay(1000); - } -} - -K_THREAD_DEFINE(blink0_id, STACKSIZE, blink0, NULL, NULL, NULL, PRIORITY, 0, 0); -K_THREAD_DEFINE(blink1_id, STACKSIZE, blink1, NULL, NULL, NULL, PRIORITY, 0, 0); -K_THREAD_DEFINE(blink2_id, STACKSIZE, loop, NULL, NULL, NULL, PRIORITY, 0, 0); - -void setup() -{ - pinMode(LED_BUILTIN, OUTPUT); - pinMode(D11, OUTPUT); - pinMode(D10, OUTPUT); -} -void loop() -{ - digitalWrite(D10, HIGH); - delay(300); - digitalWrite(D10, LOW); - delay(300); -} diff --git a/variants/arduino_giga_r1_m7/llext-edk/Makefile.cflags b/variants/arduino_giga_r1_m7/llext-edk/Makefile.cflags index 1abe1f6c..6ec4ccb5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/Makefile.cflags +++ b/variants/arduino_giga_r1_m7/llext-edk/Makefile.cflags @@ -1,11 +1,11 @@ -LLEXT_CFLAGS = -fno-strict-aliasing -fno-common -fdiagnostics-color=always -mcpu=cortex-m7 -mthumb -mabi=aapcs -mfpu=fpv5-d16 -mfloat-abi=hard -mfp16-format=ieee -mtp=soft -Wall -Wformat -Wformat-security -Wformat -Wno-format-zero-length -Wdouble-promotion -Wno-pointer-sign -Wpointer-arith -Wexpansion-to-defined -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -ftls-model=local-exec -fno-reorder-functions --param=min-pagesize=0 -fno-defer-pop --specs=picolibc.specs -D_POSIX_THREADS -std=c99 -mlong-calls -mthumb -nodefaultlibs -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h -DLL_EXTENSION_BUILD -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr/autoconf.h -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32 -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/libc/common/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/posix/options/getopt/ -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/common/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/drivers -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/stm32h7x/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/usb/device -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/cmsis/CMSIS/Core/Include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/modules/cmsis/. -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/soc -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/common_ll/include +LLEXT_CFLAGS = -DKERNEL -D__ZEPHYR__=1 -D__LINUX_ERRNO_EXTENSIONS__ -DPICOLIBC_DOUBLE_PRINTF_SCANF -D__PROGRAM_START -DSTM32H747xx -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -DCORE_CM7 -DHSE_VALUE=16000000 -DK_HEAP_MEM_POOL_SIZE=2048 -DLL_EXTENSION_BUILD -fno-strict-aliasing -fno-common -fdiagnostics-color=always -mcpu=cortex-m7 -mthumb -mabi=aapcs -mfpu=fpv5-d16 -mfloat-abi=hard -mfp16-format=ieee -mtp=soft -Wall -Wformat -Wformat-security -Wformat -Wno-format-zero-length -Wdouble-promotion -Wno-pointer-sign -Wpointer-arith -Wexpansion-to-defined -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -ftls-model=local-exec -fno-reorder-functions --param=min-pagesize=0 -fno-defer-pop -specs=picolibc.specs -D_POSIX_THREADS -std=c99 -mlong-calls -mthumb -nodefaultlibs -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr/autoconf.h -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32 -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/libc/common/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/posix/options/getopt/ -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/cpp/minimal/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/common/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/drivers -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/stm32h7x/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/usb/device -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/shell/modules/kernel_service/thread/../ -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/cmsis/CMSIS/Core/Include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/modules/cmsis/. -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/soc -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/common_ll/include -LLEXT_ALL_INCLUDE_CFLAGS = -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32 -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/libc/common/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/posix/options/getopt/ -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/common/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/drivers -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/stm32h7x/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/usb/device -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/cmsis/CMSIS/Core/Include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/modules/cmsis/. -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/soc -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/common_ll/include +LLEXT_ALL_INCLUDE_CFLAGS = -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32 -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/libc/common/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/posix/options/getopt/ -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/cpp/minimal/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/common/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/drivers -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/stm32h7x/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/usb/device -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/shell/modules/kernel_service/thread/../ -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/cmsis/CMSIS/Core/Include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/modules/cmsis/. -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/soc -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/common_ll/include -LLEXT_INCLUDE_CFLAGS = -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32 -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/libc/common/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/posix/options/getopt/ -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/common/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/drivers -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/stm32h7x/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/usb/device -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/cmsis/CMSIS/Core/Include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/modules/cmsis/. -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/soc -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/common_ll/include +LLEXT_INCLUDE_CFLAGS = -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32 -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/libc/common/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/posix/options/getopt/ -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/lib/cpp/minimal/include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/common/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/drivers -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/soc/st/stm32/stm32h7x/. -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/usb/device -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/subsys/shell/modules/kernel_service/thread/../ -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/cmsis/CMSIS/Core/Include -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/modules/cmsis/. -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/soc -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include -I$(LLEXT_EDK_INSTALL_DIR)/include/modules/hal/stm32/stm32cube/common_ll/include LLEXT_GENERATED_INCLUDE_CFLAGS = -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr -I$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated -LLEXT_BASE_CFLAGS = -fno-strict-aliasing -fno-common -fdiagnostics-color=always -mcpu=cortex-m7 -mthumb -mabi=aapcs -mfpu=fpv5-d16 -mfloat-abi=hard -mfp16-format=ieee -mtp=soft -Wall -Wformat -Wformat-security -Wformat -Wno-format-zero-length -Wdouble-promotion -Wno-pointer-sign -Wpointer-arith -Wexpansion-to-defined -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -ftls-model=local-exec -fno-reorder-functions --param=min-pagesize=0 -fno-defer-pop --specs=picolibc.specs -D_POSIX_THREADS -std=c99 -mlong-calls -mthumb -nodefaultlibs -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h -DLL_EXTENSION_BUILD +LLEXT_BASE_CFLAGS = -DKERNEL -D__ZEPHYR__=1 -D__LINUX_ERRNO_EXTENSIONS__ -DPICOLIBC_DOUBLE_PRINTF_SCANF -D__PROGRAM_START -DSTM32H747xx -DUSE_HAL_DRIVER -DUSE_FULL_LL_DRIVER -DCORE_CM7 -DHSE_VALUE=16000000 -DK_HEAP_MEM_POOL_SIZE=2048 -DLL_EXTENSION_BUILD -fno-strict-aliasing -fno-common -fdiagnostics-color=always -mcpu=cortex-m7 -mthumb -mabi=aapcs -mfpu=fpv5-d16 -mfloat-abi=hard -mfp16-format=ieee -mtp=soft -Wall -Wformat -Wformat-security -Wformat -Wno-format-zero-length -Wdouble-promotion -Wno-pointer-sign -Wpointer-arith -Wexpansion-to-defined -Wno-unused-but-set-variable -Werror=implicit-int -fno-asynchronous-unwind-tables -ftls-model=local-exec -fno-reorder-functions --param=min-pagesize=0 -fno-defer-pop -specs=picolibc.specs -D_POSIX_THREADS -std=c99 -mlong-calls -mthumb -nodefaultlibs -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h LLEXT_GENERATED_IMACROS_CFLAGS = -imacros$(LLEXT_EDK_INSTALL_DIR)/include/zephyr/include/generated/zephyr/autoconf.h \ No newline at end of file diff --git a/variants/arduino_giga_r1_m7/llext-edk/cmake.cflags b/variants/arduino_giga_r1_m7/llext-edk/cmake.cflags index 3ebd562f..fed550b1 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/cmake.cflags +++ b/variants/arduino_giga_r1_m7/llext-edk/cmake.cflags @@ -1,11 +1,11 @@ -set(LLEXT_CFLAGS -fno-strict-aliasing;-fno-common;-fdiagnostics-color=always;-mcpu=cortex-m7;-mthumb;-mabi=aapcs;-mfpu=fpv5-d16;-mfloat-abi=hard;-mfp16-format=ieee;-mtp=soft;-Wall;-Wformat;-Wformat-security;-Wformat;-Wno-format-zero-length;-Wdouble-promotion;-Wno-pointer-sign;-Wpointer-arith;-Wexpansion-to-defined;-Wno-unused-but-set-variable;-Werror=implicit-int;-fno-asynchronous-unwind-tables;-ftls-model=local-exec;-fno-reorder-functions;--param=min-pagesize=0;-fno-defer-pop;--specs=picolibc.specs;-D_POSIX_THREADS;-std=c99;-mlong-calls;-mthumb;-nodefaultlibs;-imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h;-DLL_EXTENSION_BUILD;-imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr/autoconf.h;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/libc/common/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/posix/options/getopt/;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/common/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/drivers;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/stm32h7x/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/usb/device;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/cmsis/CMSIS/Core/Include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/modules/cmsis/.;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/soc;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/common_ll/include) +set(LLEXT_CFLAGS -DKERNEL;-D__ZEPHYR__=1;-D__LINUX_ERRNO_EXTENSIONS__;-DPICOLIBC_DOUBLE_PRINTF_SCANF;-D__PROGRAM_START;-DSTM32H747xx;-DUSE_HAL_DRIVER;-DUSE_FULL_LL_DRIVER;-DCORE_CM7;-DHSE_VALUE=16000000;-DK_HEAP_MEM_POOL_SIZE=2048;-DLL_EXTENSION_BUILD;-fno-strict-aliasing;-fno-common;-fdiagnostics-color=always;-mcpu=cortex-m7;-mthumb;-mabi=aapcs;-mfpu=fpv5-d16;-mfloat-abi=hard;-mfp16-format=ieee;-mtp=soft;-Wall;-Wformat;-Wformat-security;-Wformat;-Wno-format-zero-length;-Wdouble-promotion;-Wno-pointer-sign;-Wpointer-arith;-Wexpansion-to-defined;-Wno-unused-but-set-variable;-Werror=implicit-int;-fno-asynchronous-unwind-tables;-ftls-model=local-exec;-fno-reorder-functions;--param=min-pagesize=0;-fno-defer-pop;-specs=picolibc.specs;-D_POSIX_THREADS;-std=c99;-mlong-calls;-mthumb;-nodefaultlibs;-imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h;-imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr/autoconf.h;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/libc/common/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/posix/options/getopt/;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/cpp/minimal/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/common/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/drivers;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/stm32h7x/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/usb/device;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/shell/modules/kernel_service/thread/../;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/cmsis/CMSIS/Core/Include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/modules/cmsis/.;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/soc;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/common_ll/include) -set(LLEXT_ALL_INCLUDE_CFLAGS -I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/libc/common/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/posix/options/getopt/;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/common/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/drivers;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/stm32h7x/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/usb/device;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/cmsis/CMSIS/Core/Include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/modules/cmsis/.;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/soc;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/common_ll/include) +set(LLEXT_ALL_INCLUDE_CFLAGS -I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/libc/common/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/posix/options/getopt/;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/cpp/minimal/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/common/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/drivers;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/stm32h7x/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/usb/device;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/shell/modules/kernel_service/thread/../;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/cmsis/CMSIS/Core/Include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/modules/cmsis/.;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/soc;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/common_ll/include) -set(LLEXT_INCLUDE_CFLAGS -I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/libc/common/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/posix/options/getopt/;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/common/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/drivers;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/stm32h7x/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/usb/device;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/cmsis/CMSIS/Core/Include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/modules/cmsis/.;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/soc;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/common_ll/include) +set(LLEXT_INCLUDE_CFLAGS -I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/libc/common/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/posix/options/getopt/;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/lib/cpp/minimal/include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/common/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/drivers;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/soc/st/stm32/stm32h7x/.;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/usb/device;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/subsys/shell/modules/kernel_service/thread/../;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/cmsis/CMSIS/Core/Include;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/modules/cmsis/.;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/soc;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include;-I${CMAKE_CURRENT_LIST_DIR}/include/modules/hal/stm32/stm32cube/common_ll/include) set(LLEXT_GENERATED_INCLUDE_CFLAGS -I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr;-I${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated) -set(LLEXT_BASE_CFLAGS -fno-strict-aliasing;-fno-common;-fdiagnostics-color=always;-mcpu=cortex-m7;-mthumb;-mabi=aapcs;-mfpu=fpv5-d16;-mfloat-abi=hard;-mfp16-format=ieee;-mtp=soft;-Wall;-Wformat;-Wformat-security;-Wformat;-Wno-format-zero-length;-Wdouble-promotion;-Wno-pointer-sign;-Wpointer-arith;-Wexpansion-to-defined;-Wno-unused-but-set-variable;-Werror=implicit-int;-fno-asynchronous-unwind-tables;-ftls-model=local-exec;-fno-reorder-functions;--param=min-pagesize=0;-fno-defer-pop;--specs=picolibc.specs;-D_POSIX_THREADS;-std=c99;-mlong-calls;-mthumb;-nodefaultlibs;-imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h;-DLL_EXTENSION_BUILD) +set(LLEXT_BASE_CFLAGS -DKERNEL;-D__ZEPHYR__=1;-D__LINUX_ERRNO_EXTENSIONS__;-DPICOLIBC_DOUBLE_PRINTF_SCANF;-D__PROGRAM_START;-DSTM32H747xx;-DUSE_HAL_DRIVER;-DUSE_FULL_LL_DRIVER;-DCORE_CM7;-DHSE_VALUE=16000000;-DK_HEAP_MEM_POOL_SIZE=2048;-DLL_EXTENSION_BUILD;-fno-strict-aliasing;-fno-common;-fdiagnostics-color=always;-mcpu=cortex-m7;-mthumb;-mabi=aapcs;-mfpu=fpv5-d16;-mfloat-abi=hard;-mfp16-format=ieee;-mtp=soft;-Wall;-Wformat;-Wformat-security;-Wformat;-Wno-format-zero-length;-Wdouble-promotion;-Wno-pointer-sign;-Wpointer-arith;-Wexpansion-to-defined;-Wno-unused-but-set-variable;-Werror=implicit-int;-fno-asynchronous-unwind-tables;-ftls-model=local-exec;-fno-reorder-functions;--param=min-pagesize=0;-fno-defer-pop;-specs=picolibc.specs;-D_POSIX_THREADS;-std=c99;-mlong-calls;-mthumb;-nodefaultlibs;-imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/zephyr/toolchain/zephyr_stdint.h) set(LLEXT_GENERATED_IMACROS_CFLAGS -imacros${CMAKE_CURRENT_LIST_DIR}/include/zephyr/include/generated/zephyr/autoconf.h) \ No newline at end of file diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_adc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_adc.h index 68f6321d..0a7bf0d3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_adc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_adc.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_bus.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_bus.h index 6b6d7019..ab48223e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_bus.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_bus.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_comp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_comp.h index 8cba2e90..cbb4883c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_comp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_comp.h @@ -24,6 +24,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_cortex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_cortex.h index 62d750d3..e0db9300 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_cortex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_cortex.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crc.h index aed5fa86..c97bf984 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crc.h @@ -36,8 +36,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crs.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crs.h index 6949fada..c3632cad 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_crs.h @@ -4,7 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -#if defined(CONFIG_SOC_SERIES_STM32F0X) +#if defined(CONFIG_SOC_SERIES_STM32C0X) +#include +#elif defined(CONFIG_SOC_SERIES_STM32F0X) #include #elif defined(CONFIG_SOC_SERIES_STM32G0X) #include @@ -22,6 +24,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dac.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dac.h index 7dc42e63..5075cda4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dac.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dac.h @@ -32,6 +32,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WLX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dma.h index 7aacaeb0..0611d758 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dma.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dmamux.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dmamux.h index 5d351323..941fe309 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dmamux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_dmamux.h @@ -18,6 +18,10 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBX) #include #elif defined(CONFIG_SOC_SERIES_STM32WLX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_exti.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_exti.h index 41ead159..8efcd25c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_exti.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_exti.h @@ -38,6 +38,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_gpio.h index 026ee612..d1ad5e4b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_gpio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_gpio.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_i2c.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_i2c.h index e43f2edc..3c12db06 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_i2c.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_i2c.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_iwdg.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_iwdg.h index 8ef649f1..4ab93b5b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_iwdg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_iwdg.h @@ -36,8 +36,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lptim.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lptim.h index 28e7a22c..b5e2e3d4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lptim.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lptim.h @@ -26,6 +26,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lpuart.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lpuart.h index 1a710f98..96f99760 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lpuart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_lpuart.h @@ -20,8 +20,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_opamp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_opamp.h index c59a3571..f37c13b5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_opamp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_opamp.h @@ -18,6 +18,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pka.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pka.h index ba7698be..90740fc0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pka.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pka.h @@ -14,6 +14,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pwr.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pwr.h index d030da3a..fa8f7793 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pwr.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_pwr.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_radio.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_radio.h new file mode 100644 index 00000000..01625310 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_radio.h @@ -0,0 +1,9 @@ +/* + * NOTE: Autogenerated file using genllheaders.py + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if defined(CONFIG_SOC_SERIES_STM32WB0X) +#include +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rcc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rcc.h index d2ea7d71..27e6308e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rcc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rcc.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rng.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rng.h index 88664e07..d1787ab0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rng.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rng.h @@ -26,8 +26,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32L5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rtc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rtc.h index edfb7abc..c633c129 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rtc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_rtc.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_spi.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_spi.h index 7183e183..f678d7ec 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_spi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_spi.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_system.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_system.h index f2175797..122ccd87 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_system.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_system.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_tim.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_tim.h index 3e09aa48..a2698819 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_tim.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_tim.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_usart.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_usart.h index eafc819c..40f41901 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_usart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_usart.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_utils.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_utils.h index ba5e9834..699d7979 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_utils.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_utils.h @@ -38,8 +38,12 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_wwdg.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_wwdg.h index b1bad707..091793da 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_wwdg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/common_ll/include/stm32_ll_wwdg.h @@ -38,6 +38,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32MP1X) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h index 2013593c..07a7c67a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/Legacy/stm32_hal_legacy.h @@ -472,7 +472,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) /* #define PAGESIZE FLASH_PAGE_SIZE */ +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -601,6 +603,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -806,6 +817,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -860,6 +886,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -997,8 +1027,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1249,10 +1279,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1264,10 +1294,10 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #if defined(STM32F7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK @@ -1817,7 +1847,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1999,12 +2029,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2731,6 +2761,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3659,7 +3695,7 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3910,7 +3946,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4204,6 +4241,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h index c3760b17..222a4e9d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal.h @@ -59,8 +59,14 @@ typedef enum * @{ */ #define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ +#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */ +#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */ #define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ +#if (STM32H7_DEV_ID == 0x450UL) #define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ +#else +#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */ +#endif /* STM32H7_DEV_ID */ #define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h index 861324a3..7cde9f1e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc.h @@ -1962,7 +1962,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1990,8 +1990,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h index 2da227fa..d2900314 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_adc_ex.h @@ -1011,6 +1011,80 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_14) || \ ((__CHANNEL__) == ADC_CHANNEL_15) ) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC1. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_16) ? ADC_CHANNEL_17 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC2. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_12) ? ADC_CHANNEL_13 : \ + ((__CHANNEL__) == ADC_CHANNEL_18) ? ADC_CHANNEL_19 : 0UL) + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input for ADC3. + * @param __CHANNEL__: programmed ADC channel. + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) ? ADC_CHANNEL_0 : \ + ((__CHANNEL__) == ADC_CHANNEL_2) ? ADC_CHANNEL_6 : \ + ((__CHANNEL__) == ADC_CHANNEL_3) ? ADC_CHANNEL_7 : \ + ((__CHANNEL__) == ADC_CHANNEL_4) ? ADC_CHANNEL_8 : \ + ((__CHANNEL__) == ADC_CHANNEL_5) ? ADC_CHANNEL_9 : \ + ((__CHANNEL__) == ADC_CHANNEL_10) ? ADC_CHANNEL_11 : \ + ((__CHANNEL__) == ADC_CHANNEL_11) ? ADC_CHANNEL_12 : \ + ((__CHANNEL__) == ADC_CHANNEL_13) ? ADC_CHANNEL_14 : \ + ((__CHANNEL__) == ADC_CHANNEL_14) ? ADC_CHANNEL_15 : 0UL) +#endif /* ADC_VER_V5_V90 */ + +#if defined(ADC_VER_V5_V90) +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC3) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC3(__CHANNEL__) : 0UL) +#else +/** + * @brief Helper macro to determine the selected channel corresponding + * negative input on the ADC instance selected. + * @param __HANDLE__ ADC handle. + * @param __CHANNEL__ This parameter can be one of the following values: + * @retval return the negative input channels corresponding to the selected channel. + */ +#define ADC_CHANNEL_DIFF_NEG_INPUT(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC1(__CHANNEL__) : \ + (((__HANDLE__)->Instance) == ADC2) ? ADC_CHANNEL_DIFF_NEG_INPUT_ADC2(__CHANNEL__) : 0UL) +#endif /* ADC_VER_V5_V90 */ + /** * @brief Verify the ADC single-ended input or differential mode setting. * @param __SING_DIFF__ programmed channel setting. @@ -1311,7 +1385,7 @@ typedef struct /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); @@ -1328,12 +1402,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC multimode */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, const uint32_t *pData, uint32_t Length); HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h index 9d16f6aa..83265b01 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_comp.h @@ -915,7 +915,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); * @{ */ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); /* Callback in Interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @@ -926,8 +926,8 @@ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); /** @addtogroup COMP_Exported_Functions_Group4 * @{ */ -HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); -uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp); +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h index 36ed9cac..54fcc2d9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_conf.h @@ -84,6 +84,7 @@ #define HAL_RTC_MODULE_ENABLED #define HAL_SAI_MODULE_ENABLED #define HAL_SD_MODULE_ENABLED +#define HAL_SDIO_MODULE_ENABLED #define HAL_SDRAM_MODULE_ENABLED #define HAL_SMARTCARD_MODULE_ENABLED #define HAL_SMBUS_MODULE_ENABLED @@ -168,6 +169,8 @@ #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SPI_CRC 1U /*!< use CRC in SPI */ #define USE_FLASH_ECC 0U /*!< use ECC error management in FLASH */ +#define USE_SDIO_TRANSCEIVER 0U /*!< use SDIO Transceiver */ +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ @@ -208,6 +211,7 @@ #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ @@ -438,6 +442,10 @@ #include "stm32h7xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32h7xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + #ifdef HAL_SDRAM_MODULE_ENABLED #include "stm32h7xx_hal_sdram.h" #endif /* HAL_SDRAM_MODULE_ENABLED */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h index 0aa08c43..28949bed 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cordic.h @@ -149,7 +149,6 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants * @{ @@ -166,6 +165,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ + /** * @} */ @@ -183,6 +183,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */ #define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */ #define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */ + /** * @} */ @@ -212,6 +213,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ |CORDIC_CSR_PRECISION_0)) + /** * @} */ @@ -229,6 +231,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0)) #define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1)) #define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0)) + /** * @} */ @@ -237,6 +240,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */ + /** * @} */ @@ -245,6 +249,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */ + /** * @} */ @@ -253,6 +258,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */ + /** * @} */ @@ -288,6 +294,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */ #define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */ + /** * @} */ @@ -297,6 +304,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */ #define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */ + /** * @} */ @@ -305,6 +313,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */ + /** * @} */ @@ -316,6 +325,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */ #define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */ #define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */ + /** * @} */ @@ -336,9 +346,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -416,7 +426,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @} */ -/* Private macros --------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /** @defgroup CORDIC_Private_Macros CORDIC Private Macros * @{ */ @@ -584,6 +594,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic); /* Peripheral State functions *************************************************/ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic); uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic); + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h index 134fc483..cc4c24c7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cortex.h @@ -309,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control); void HAL_MPU_Disable(void); void HAL_MPU_EnableRegion(uint32_t RegionNumber); void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); #endif /* __MPU_PRESENT */ uint32_t HAL_NVIC_GetPriorityGrouping(void); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h index a6802ed6..59bf9cd5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp.h @@ -454,11 +454,11 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu */ /* Interrupt Handler functions **********************************************/ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp); void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h index 8820e0b7..3c193cde 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_cryp_ex.h @@ -91,8 +91,8 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h index 65e5fd93..90590387 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dac.h @@ -286,10 +286,13 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) -#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) -#define DAC_CHIPCONNECT_BOTH (1UL << 2) - +#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/ +#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. */ +#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via + internal paths) and to an external pin. + Note: this connection is not available in mode normal + with buffer disabled. */ /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h index a21afc09..672d5de0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dcmi.h @@ -569,8 +569,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_ * @{ */ /* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); +HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); +uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h index 82f6f215..59ad97a8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma.h @@ -1211,8 +1211,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca * @brief Peripheral State functions * @{ */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h index 00f205bc..dd32a99b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dma2d.h @@ -511,9 +511,9 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); @@ -550,8 +550,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t */ /* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); +HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d); +uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h index f9bff170..3bb262fa 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_dts.h @@ -423,7 +423,7 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts); HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts); void HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts); -HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts); +HAL_DTS_StateTypeDef HAL_DTS_GetState(const DTS_HandleTypeDef *hdts); /* Callback in Interrupt mode */ void HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts); void HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h index 726127ea..b3d9eefb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_eth.h @@ -105,7 +105,7 @@ typedef struct uint32_t *PacketAddress[ETH_TX_DESC_CNT]; /*= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) ) +#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \ + (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX)))) /** * @brief Verify the FMAC filter parameter R. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h index 9e93c229..1a1e9849 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gfxmmu.h @@ -344,16 +344,16 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf * @{ */ /* Operation functions ********************************************************/ -HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber, uint32_t Address); -HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu, +HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(const GFXMMU_HandleTypeDef *hgfxmmu, uint32_t FirstLine, uint32_t LinesNumber); -HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); +HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(const GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine); HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam); @@ -373,7 +373,7 @@ void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu); * @{ */ /* State function *************************************************************/ -HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu); +HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(const GFXMMU_HandleTypeDef *hgfxmmu); uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu); /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h index 1cd9178b..e0b75b70 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_gpio.h @@ -252,7 +252,7 @@ typedef enum * @{ */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** * @} @@ -262,7 +262,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); * @{ */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h index 15b1213f..54df4670 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +499,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +519,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +533,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +548,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -571,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash); +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); /** * @} @@ -594,19 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h index 78fc650f..2ac9297a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h index 7b709f3e..a6841ada 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_hrtim.h @@ -21,7 +21,7 @@ #define STM32H7xx_HAL_HRTIM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -60,7 +60,7 @@ */ typedef struct { - uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. + uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. The HRTIM instance can be configured to act as a slave (waiting for a trigger @@ -119,7 +119,7 @@ typedef struct __HRTIM_HandleTypeDef typedef struct #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ { - HRTIM_TypeDef * Instance; /*!< Register base address */ + HRTIM_TypeDef *Instance; /*!< Register base address */ HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ @@ -129,12 +129,12 @@ typedef struct __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ - DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ - DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ + DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ + DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ @@ -481,7 +481,8 @@ typedef struct /** * @brief HAL HRTIM Callback ID enumeration definition */ -typedef enum { +typedef enum +{ HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ @@ -510,7 +511,7 @@ typedef enum { HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ -}HAL_HRTIM_CallbackIDTypeDef; +} HAL_HRTIM_CallbackIDTypeDef; /** * @brief HAL HRTIM Callback function pointer definitions @@ -556,8 +557,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit * @{ @@ -567,9 +568,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit * @{ @@ -609,10 +610,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ - (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ - ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) + (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ + ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) /** * @} */ @@ -649,10 +650,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ - /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio +/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio * @{ * @brief Constants defining timer high-resolution clock prescaler ratio. - */ + */ #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ @@ -934,9 +935,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ - (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ - ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) + (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ + ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) /** * @} */ @@ -1040,9 +1041,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level * @{ @@ -1267,9 +1268,9 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ - /** +/** * @} - */ + */ /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle * @{ @@ -1804,8 +1805,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ - (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ - ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) + (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ + ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) /** * @} */ @@ -1999,169 +2000,169 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @} */ - /* Private macros --------------------------------------------------------*/ +/* Private macros --------------------------------------------------------*/ /** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ - (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ - ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) + (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ + ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ - ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ + ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ - (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ - ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) + (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ + ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ - ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ - || \ - (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ - ((OUTPUT) == HRTIM_OUTPUT_TE2)))) + ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ + (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ + (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ + (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ + (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ + || \ + (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ + (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ + ((OUTPUT) == HRTIM_OUTPUT_TE2)))) #define IS_HRTIM_EVENT(EVENT)\ - (((EVENT) == HRTIM_EVENT_NONE)|| \ - ((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5) || \ - ((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) + (((EVENT) == HRTIM_EVENT_NONE)|| \ + ((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5) || \ + ((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) #define IS_HRTIM_FAULT(FAULT)\ - (((FAULT) == HRTIM_FAULT_1) || \ - ((FAULT) == HRTIM_FAULT_2) || \ - ((FAULT) == HRTIM_FAULT_3) || \ - ((FAULT) == HRTIM_FAULT_4) || \ - ((FAULT) == HRTIM_FAULT_5)) + (((FAULT) == HRTIM_FAULT_1) || \ + ((FAULT) == HRTIM_FAULT_2) || \ + ((FAULT) == HRTIM_FAULT_3) || \ + ((FAULT) == HRTIM_FAULT_4) || \ + ((FAULT) == HRTIM_FAULT_5)) #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) + (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) #define IS_HRTIM_MODE(MODE)\ - (((MODE) == HRTIM_MODE_CONTINUOUS) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_CONTINUOUS) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_MODE_ONEPULSE(MODE)\ - (((MODE) == HRTIM_MODE_SINGLESHOT) || \ - ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) + (((MODE) == HRTIM_MODE_SINGLESHOT) || \ + ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) #define IS_HRTIM_HALFMODE(HALFMODE)\ - (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ - ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) + (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ + ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) #define IS_HRTIM_SYNCSTART(SYNCSTART)\ - (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ - ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) + (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ + ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) #define IS_HRTIM_SYNCRESET(SYNCRESET)\ - (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ - ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) + (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ + ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) #define IS_HRTIM_DACSYNC(DACSYNC)\ - (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ - ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) + (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ + ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) #define IS_HRTIM_PRELOAD(PRELOAD)\ - (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ - ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) + (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ + ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ - (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ - ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) + (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ + ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) #define IS_HRTIM_TIMERBURSTMODE(MODE) \ - (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ - ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) + (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ + ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ - (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ - ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) + (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ + ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ - ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ + ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ - (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ - ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) + (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ + ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ - ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ - ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) + ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ + ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ - ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ - || \ - (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ - (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ - ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) + ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ + || \ + (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ + (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ + ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) @@ -2169,128 +2170,128 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ - (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ - ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) + (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ + ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) /* Auto delayed mode is only available for compare units 2 and 4U */ #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ - ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ - || \ - (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ - (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ - ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) + ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ + || \ + (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ + (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ + ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ - (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ - ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) + (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ + ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ - (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ - ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) + (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ + ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ - (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ - ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) + (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ + ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ - (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ - ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) + (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ + ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ - (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ - ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) + (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ + ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ - (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ - ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) + (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ + ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ - (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ - ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) + (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ + ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ - (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ - ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) + (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ + ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ @@ -2304,420 +2305,420 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ - || \ + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ + || \ (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ - (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ - ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) + (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ + ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ - (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ - ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) + (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ + ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ - (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ - ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) + (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ + ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ - ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) + (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ + ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ - (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ - ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) + (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ + ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ - (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ - ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) + (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ + ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ - (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ - ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) + (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ + ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ - (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ - ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) + (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ + ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ - (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ - ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) + (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ + ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ - (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ - ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) + (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ + ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ - (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ - ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) + (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ + ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ - (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ - ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) + (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ + ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ - (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ - ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) + (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ + ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ - (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ - ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) + (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ + ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ - (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ - ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) + (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ + ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ - (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ - ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) + (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ + ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) #define IS_HRTIM_EVENTSRC(EVENTSRC)\ - (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ - ((EVENTSRC) == HRTIM_EVENTSRC_4)) + (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ + ((EVENTSRC) == HRTIM_EVENTSRC_4)) #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ - ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ - (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ - ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ - || \ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) + ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ + (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ + ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ + || \ + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ - (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ - ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) + (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ + ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ - (((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) && \ - (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ - ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ - || \ - (((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10))) + (((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) && \ + (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ + ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ + || \ + (((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10))) #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ - ((((EVENT) == HRTIM_EVENT_1) || \ - ((EVENT) == HRTIM_EVENT_2) || \ - ((EVENT) == HRTIM_EVENT_3) || \ - ((EVENT) == HRTIM_EVENT_4) || \ - ((EVENT) == HRTIM_EVENT_5)) \ - || \ - ((((EVENT) == HRTIM_EVENT_6) || \ - ((EVENT) == HRTIM_EVENT_7) || \ - ((EVENT) == HRTIM_EVENT_8) || \ - ((EVENT) == HRTIM_EVENT_9) || \ - ((EVENT) == HRTIM_EVENT_10)) && \ - (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ - ((FILTER) == HRTIM_EVENTFILTER_1) || \ - ((FILTER) == HRTIM_EVENTFILTER_2) || \ - ((FILTER) == HRTIM_EVENTFILTER_3) || \ - ((FILTER) == HRTIM_EVENTFILTER_4) || \ - ((FILTER) == HRTIM_EVENTFILTER_5) || \ - ((FILTER) == HRTIM_EVENTFILTER_6) || \ - ((FILTER) == HRTIM_EVENTFILTER_7) || \ - ((FILTER) == HRTIM_EVENTFILTER_8) || \ - ((FILTER) == HRTIM_EVENTFILTER_9) || \ - ((FILTER) == HRTIM_EVENTFILTER_10) || \ - ((FILTER) == HRTIM_EVENTFILTER_11) || \ - ((FILTER) == HRTIM_EVENTFILTER_12) || \ - ((FILTER) == HRTIM_EVENTFILTER_13) || \ - ((FILTER) == HRTIM_EVENTFILTER_14) || \ - ((FILTER) == HRTIM_EVENTFILTER_15)))) + ((((EVENT) == HRTIM_EVENT_1) || \ + ((EVENT) == HRTIM_EVENT_2) || \ + ((EVENT) == HRTIM_EVENT_3) || \ + ((EVENT) == HRTIM_EVENT_4) || \ + ((EVENT) == HRTIM_EVENT_5)) \ + || \ + ((((EVENT) == HRTIM_EVENT_6) || \ + ((EVENT) == HRTIM_EVENT_7) || \ + ((EVENT) == HRTIM_EVENT_8) || \ + ((EVENT) == HRTIM_EVENT_9) || \ + ((EVENT) == HRTIM_EVENT_10)) && \ + (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ + ((FILTER) == HRTIM_EVENTFILTER_1) || \ + ((FILTER) == HRTIM_EVENTFILTER_2) || \ + ((FILTER) == HRTIM_EVENTFILTER_3) || \ + ((FILTER) == HRTIM_EVENTFILTER_4) || \ + ((FILTER) == HRTIM_EVENTFILTER_5) || \ + ((FILTER) == HRTIM_EVENTFILTER_6) || \ + ((FILTER) == HRTIM_EVENTFILTER_7) || \ + ((FILTER) == HRTIM_EVENTFILTER_8) || \ + ((FILTER) == HRTIM_EVENTFILTER_9) || \ + ((FILTER) == HRTIM_EVENTFILTER_10) || \ + ((FILTER) == HRTIM_EVENTFILTER_11) || \ + ((FILTER) == HRTIM_EVENTFILTER_12) || \ + ((FILTER) == HRTIM_EVENTFILTER_13) || \ + ((FILTER) == HRTIM_EVENTFILTER_14) || \ + ((FILTER) == HRTIM_EVENTFILTER_15)))) #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ - (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ - ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) + (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ + ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ - (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ - ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) + (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ + ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ - (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ - ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) + (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ + ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ - (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ - ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) + (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ + ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ - (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ - ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) + (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ + ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ - (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ - ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) + (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ + ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ - (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ - ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) + (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ + ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) #define IS_HRTIM_BURSTMODE(BURSTMODE)\ - (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ - ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) + (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ + ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ - (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ - ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) + (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ + ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ - (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ - ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) + (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ + ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ - (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ - ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) + (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ + ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ - (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ - ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) + (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ + ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ - (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ - ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) + (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ + ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ - (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ - ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) + (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ + ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ - ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ - || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) + ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ + || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ - (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ - ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) + (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ + ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) @@ -2750,10 +2751,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) #endif @@ -2782,44 +2783,44 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ do {\ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ - }\ + {\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ }\ + }\ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ + {\ + if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ {\ - if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ - {\ - ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ - }\ + ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ }\ + }\ } while(0U) @@ -2852,8 +2853,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval None */ -#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) -#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + |= (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ + &= ~(__INTERRUPT__)) /** @brief Enables or disables the specified HRTIM Timerx interrupts. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2892,7 +2895,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2907,7 +2911,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2937,7 +2942,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Clears the specified HRTIM common pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2967,7 +2973,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag * @retval None */ -#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) +#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ + = (__INTERRUPT__)) /** @brief Clears the specified HRTIM Timerx pending flag. * @param __HANDLE__ specifies the HRTIM Handle. @@ -2990,7 +2997,8 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag * @retval None */ -#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) +#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__INTERRUPT__)) /* DMA HANDLING */ /** @brief Enables or disables the specified HRTIM Master timer DMA requests. @@ -3033,14 +3041,18 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) -#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) -#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ + (__FLAG__)) == (__FLAG__)) #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) -#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) -#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) +#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ + (__FLAG__)) == (__FLAG__)) +#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ + = (__FLAG__)) /** @brief Sets the HRTIM timer Counter Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3136,16 +3148,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval None */ #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) /** @brief Gets the HRTIM timer Compare Register value on runtime * @param __HANDLE__ HRTIM Handle. @@ -3161,16 +3173,16 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @retval Compare value */ #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ - (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ - ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ - : \ - (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ - ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ - ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) + (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ + ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ + : \ + (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ + ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ + ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) /** * @} @@ -3178,17 +3190,17 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< /* Exported functions --------------------------------------------------------*/ /** @addtogroup HRTIM_Exported_Functions -* @{ -*/ + * @{ + */ /** @addtogroup HRTIM_Exported_Functions_Group1 -* @{ -*/ + * @{ + */ /* Initialization and Configuration functions ********************************/ HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); -HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); +HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); @@ -3196,244 +3208,244 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); + const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group2 -* @{ -*/ + * @{ + */ /* Simple time base related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group3 -* @{ -*/ + * @{ + */ /* Simple output compare related functions ************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); + uint32_t TimerIdx, + uint32_t OCChannel, + const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t OCChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OCChannel); + uint32_t TimerIdx, + uint32_t OCChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group4 -* @{ -*/ + * @{ + */ /* Simple PWM output related functions ****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); + uint32_t TimerIdx, + uint32_t PWMChannel, + const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t PWMChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t PWMChannel); + uint32_t TimerIdx, + uint32_t PWMChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group5 -* @{ -*/ + * @{ + */ /* Simple capture related functions *******************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); + uint32_t TimerIdx, + uint32_t CaptureChannel, + const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel, - uint32_t SrcAddr, - uint32_t DestAddr, - uint32_t Length); + uint32_t TimerIdx, + uint32_t CaptureChannel, + uint32_t SrcAddr, + uint32_t DestAddr, + uint32_t Length); HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t CaptureChannel); + uint32_t TimerIdx, + uint32_t CaptureChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group6 -* @{ -*/ + * @{ + */ /* Simple one pulse related functions *****************************************/ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel, - const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); + uint32_t TimerIdx, + uint32_t OnePulseChannel, + const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx, - uint32_t OnePulseChannel); + uint32_t TimerIdx, + uint32_t OnePulseChannel); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group7 -* @{ -*/ + * @{ + */ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, - const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); + const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Event, - const HRTIM_EventCfgTypeDef* pEventCfg); + const HRTIM_EventCfgTypeDef *pEventCfg); HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Fault, - const HRTIM_FaultCfgTypeDef* pFaultCfg); + const HRTIM_FaultCfgTypeDef *pFaultCfg); HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t Prescaler); -void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, +void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, uint32_t Faults, uint32_t Enable); HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t ADCTrigger, - const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); + const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); /** * @} */ /** @addtogroup HRTIM_Exported_Functions_Group8 -* @{ -*/ + * @{ + */ /* Waveform related functions *************************************************/ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_TimerCfgTypeDef * pTimerCfg); + const HRTIM_TimerCfgTypeDef *pTimerCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CompareUnit, - const HRTIM_CompareCfgTypeDef* pCompareCfg); + const HRTIM_CompareCfgTypeDef *pCompareCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit, - const HRTIM_CaptureCfgTypeDef* pCaptureCfg); + const HRTIM_CaptureCfgTypeDef *pCaptureCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output, - const HRTIM_OutputCfgTypeDef * pOutputCfg); + const HRTIM_OutputCfgTypeDef *pOutputCfg); HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3443,15 +3455,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Event, - const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); + const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); + const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, - const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); + const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, @@ -3459,22 +3471,22 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, uint32_t OutputsToStart); @@ -3503,7 +3515,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, uint32_t BurstBufferLength); HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, - uint32_t Timers); + uint32_t Timers); HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, uint32_t Timers); @@ -3513,12 +3525,12 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group9 -* @{ -*/ + * @{ + */ /* HRTIM peripheral state functions */ -HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim); +HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); -uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t CaptureUnit); @@ -3526,7 +3538,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); -uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim, +uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx, uint32_t Output); @@ -3547,8 +3559,8 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, */ /** @addtogroup HRTIM_Exported_Functions_Group10 -* @{ -*/ + * @{ + */ /* IRQ handler */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); @@ -3565,50 +3577,50 @@ void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); /* Timer events related callback functions */ void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, - uint32_t TimerIdx); + uint32_t TimerIdx); void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID, pHRTIM_TIMxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, +HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, HAL_HRTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h index 407bf2cc..40f321f8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_i2s.h @@ -505,6 +505,11 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); +/* IO Swap feature */ +HAL_StatusTypeDef HAL_I2S_EnableIOSwap(I2S_HandleTypeDef *hi2s); +HAL_StatusTypeDef HAL_I2S_DisableIOSwap(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_IsEnabledIOSwap(const I2S_HandleTypeDef *hi2s); + /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h index d5b4a665..a72e42f9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ltdc.h @@ -592,7 +592,8 @@ HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, u HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, const uint32_t *pCLUT, uint32_t CLUTSize, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); @@ -625,8 +626,8 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint3 * @{ */ /* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); +HAL_LTDC_StateTypeDef HAL_LTDC_GetState(const LTDC_HandleTypeDef *hltdc); +uint32_t HAL_LTDC_GetError(const LTDC_HandleTypeDef *hltdc); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h index 50c61f41..fecf9fe2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdios.h @@ -509,8 +509,8 @@ HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_ HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetWrittenRegAddress(const MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetReadRegAddress(const MDIOS_HandleTypeDef *hmdios); HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); @@ -527,8 +527,8 @@ void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); /** @addtogroup MDIOS_Exported_Functions_Group3 * @{ */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); +uint32_t HAL_MDIOS_GetError(const MDIOS_HandleTypeDef *hmdios); +HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(const MDIOS_HandleTypeDef *hmdios); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h index a39cc0d7..fb611786 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mdma.h @@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM */ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); -HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode); +HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); @@ -687,8 +687,8 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma); * @brief Peripheral State functions * @{ */ -HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma); -uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma); +HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma); +uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h index ed4e5e5a..3b242bae 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMC * @{ @@ -121,7 +122,7 @@ typedef struct HAL_LockTypeDef Lock; /*!< MMC locking object */ - const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ uint32_t TxXferSize; /*!< MMC Tx Transfer size */ @@ -135,6 +136,8 @@ typedef struct __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + __IO uint16_t RPMBErrorCode; /*!< MMC RPMB Area Error codes */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ uint32_t CSD[4U]; /*!< MMC card specific data table */ @@ -276,45 +279,55 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition * @{ */ -#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ /*!< number of transferred bytes does not match the block length */ -#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ /*!< command or if there was an attempt to access a locked card */ -#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ /*!< of erase sequence command was received */ -#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +/*!< response results after operating with RPMB partition */ +#define HAL_MMC_ERROR_RPMB_OPERATION_OK 0x0000U /*!< Operation OK */ +#define HAL_MMC_ERROR_RPMB_GENERAL_FAILURE 0x0001U /*!< General failure */ +#define HAL_MMC_ERROR_RPMB_AUTHENTICATION_FAILURE 0x0002U /*!< Authentication failure */ +#define HAL_MMC_ERROR_RPMB_COUNTER_FAILURE 0x0003U /*!< Counter failure */ +#define HAL_MMC_ERROR_RPMB_ADDRESS_FAILURE 0x0004U /*!< Address failure */ +#define HAL_MMC_ERROR_RPMB_WRITE_FAILURE 0x0005U /*!< Write failure */ +#define HAL_MMC_ERROR_RPMB_READ_FAILURE 0x0006U /*!< Read failure */ +#define HAL_MMC_ERROR_RPMB_KEY_NOT_YET_PROG 0x0007U /*!< Authentication Key not yet programmed */ +#define HAL_MMC_ERROR_RPMB_COUNTER_EXPIRED 0x0080U /*!< Write Counter has expired i.e. reached its max value */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} @@ -399,6 +412,19 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); * @} */ +/** @defgroup MMC_Exported_Constansts_Group7 MMC Partitions types + * @{ + */ +typedef uint32_t HAL_MMC_PartitionTypeDef; + +#define HAL_MMC_USER_AREA_PARTITION 0x00000000U /*!< User area partition */ +#define HAL_MMC_BOOT_PARTITION1 0x00000100U /*!< Boot partition 1 */ +#define HAL_MMC_BOOT_PARTITION2 0x00000200U /*!< Boot partition 2 */ +#define HAL_MMC_RPMB_PARTITION 0x00000300U /*!< RPMB partition */ +/** + * @} + */ + /** * @} */ @@ -686,6 +712,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); +HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition); /** * @} */ @@ -694,9 +721,9 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} @@ -705,8 +732,9 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC /** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +HAL_MMC_StateTypeDef HAL_MMC_GetState(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(const MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetRPMBError(const MMC_HandleTypeDef *hmmc); /** * @} */ @@ -740,6 +768,29 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ + +/** @defgroup MMC_Exported_Functions_Group9 Replay Protected Memory Block management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pKey, + uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter(MMC_HandleTypeDef *hmmc, uint8_t *pNonce, uint32_t Timeout); +uint32_t HAL_MMC_RPMB_GetWriteCounter_IT(MMC_HandleTypeDef *hmmc, uint8_t *pNonce); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pMAC); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC, + uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_RPMB_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint16_t BlockAdd, + uint16_t NumberOfBlocks, const uint8_t *pNonce, uint8_t *pMAC); + +/** + * @} + */ + /* Private types -------------------------------------------------------------*/ /** @defgroup MMC_Private_Types MMC Private Types * @{ @@ -812,6 +863,7 @@ HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h index 21574958..c610a2bd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_mmc_ex.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup MMCEx * @brief SD HAL extended module driver * @{ @@ -100,6 +100,7 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h index 7290893b..b0b31b91 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_nand.h @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h index ef354861..cac09484 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_opamp.h @@ -417,7 +417,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp); -HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); +HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (const OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset); /** * @} @@ -428,7 +428,7 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop */ /* Peripheral State functions **************************************************/ -HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp); +HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(const OPAMP_HandleTypeDef *hopamp); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h index bfdfb0b4..9aa5e3ab 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_otfdec.h @@ -342,8 +342,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, - OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); -uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); + const OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); +uint32_t HAL_OTFDEC_KeyCRCComputation(const uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); /** @@ -353,8 +353,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 /** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions * @{ */ -HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec); -uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); +HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(const OTFDEC_HandleTypeDef *hotfdec); +uint32_t HAL_OTFDEC_RegionGetKeyCRC(const OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config); /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h index 9cfa0125..221e2af3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pcd_ex.h @@ -45,7 +45,6 @@ extern "C" { /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @{ */ - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h index 91a90540..c1d72223 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr.h @@ -692,7 +692,7 @@ void HAL_PWR_DisableBkUpAccess (void); */ /* Peripheral Control functions **********************************************/ /* PVD configuration */ -void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD (void); void HAL_PWR_DisablePVD (void); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h index 61c76092..e8455d8d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_pwr_ex.h @@ -544,7 +544,7 @@ void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock); void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); #endif /* defined(PWR_CR1_SRDRAMSO) */ /* Wakeup Pins control functions */ -void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams); +void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams); void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); @@ -599,7 +599,7 @@ uint32_t HAL_PWREx_GetVBATLevel (void); PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); #endif /* PWR_CSR1_MMCVDO */ /* Power AVD configuration functions */ -void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD); +void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD); void HAL_PWREx_EnableAVD (void); void HAL_PWREx_DisableAVD (void); /* Power PVD/AVD IRQ Handler */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h index 98b2c5cf..321f05f5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_qspi.h @@ -26,6 +26,9 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined (DLYB_QUADSPI) +#include "stm32h7xx_ll_delayblock.h" +#endif /* DLYB_QUADSPI */ #if defined(QUADSPI) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h index f9444ebc..b681c8de 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_ramecc.h @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc); * @brief Error information functions * @{ */ -uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingAddress(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataLow(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetFailingDataHigh(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetHammingErrorCode(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCSingleErrorDetected(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(const RAMECC_HandleTypeDef *hramecc); /** * @} */ @@ -317,9 +317,9 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc); * @brief State and Error Functions * @{ */ -HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc); -uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc); +HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetError(const RAMECC_HandleTypeDef *hramecc); +uint32_t HAL_RAMECC_GetRAMECCError(const RAMECC_HandleTypeDef *hramecc); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h index 1626c6d0..564a8a09 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc.h @@ -7968,7 +7968,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h index 2fb1fd29..d39df84c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rcc_ex.h @@ -3936,7 +3936,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx); * @{ */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h index e7dd55a1..409ac73b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng.h @@ -178,6 +178,9 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#if defined(RNG_CR_CONDRST) +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ +#endif /* RNG_CR_CONDRST */ /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h index ee43ec10..05c83d07 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h index ad0fa135..30198263 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc.h @@ -935,9 +935,9 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); /** * @} */ @@ -949,7 +949,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -970,7 +970,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h index bb29abe8..61845fff 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_rtc_ex.h @@ -1658,8 +1658,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1668,8 +1668,8 @@ void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); #if defined(TAMP) -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, const RTC_InternalTamperTypeDef *sIntTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc); @@ -1679,8 +1679,8 @@ void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed); HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); #endif /* TAMP */ @@ -1700,7 +1700,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1717,8 +1717,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions * @{ */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); /** * @} */ @@ -1742,7 +1742,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); #if defined(TAMP) HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t *Counter, uint32_t Instance); #endif /* TAMP */ /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h index 83fa74fd..a2536da2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd.h @@ -33,6 +33,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @defgroup SD SD * @brief SD HAL module driver @@ -315,12 +316,12 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ #define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ - /*!< number of transferred bytes does not match the block length */ +/*!< number of transferred bytes does not match the block length */ #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ #define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ - /*!< command or if there was an attempt to access a locked card */ +/*!< command or if there was an attempt to access a locked card */ #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -332,7 +333,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ #define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ - /*!< of erase sequence command was received */ +/*!< of erase sequence command was received */ #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -690,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -701,8 +702,8 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf /** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions * @{ */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +HAL_SD_StateTypeDef HAL_SD_GetState(const SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(const SD_HandleTypeDef *hsd); /** * @} */ @@ -787,6 +788,7 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h index 450e7dfa..050005b0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sd_ex.h @@ -30,6 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_HAL_Driver * @{ */ +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDEx * @brief SD HAL extended module driver @@ -98,6 +99,7 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); /** * @} */ +#endif /* SDMMC1 || SDMMC2 */ /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdio.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdio.h new file mode 100644 index 00000000..77cb250e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdio.h @@ -0,0 +1,600 @@ +/** + ********************************************************************************************************************** + * @file stm32h7xx_hal_sdio.h + * @author MCD Application Team + * @brief Header file of SDIO HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H7xx_HAL_SDIO_H +#define STM32H7xx_HAL_SDIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32h7xx_ll_sdmmc.h" + +/** @addtogroup STM32U5xx_HAL_Driver + * @{ + */ +#if defined (SDMMC1) || defined (SDMMC2) + +/** @defgroup SDIO SDIO + * @brief SDIO HAL module driver + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Types SDIO Exported Types + * @{ + */ + +/** @defgroup SDIO_Exported_Types_Group1 SDIO State enumeration structure + * @{ + + */ +typedef enum +{ + HAL_SDIO_STATE_RESET = 0x00U, /*!< SDIO not yet initialized or disabled */ + HAL_SDIO_STATE_READY = 0x01U, /*!< SDIO initialized and ready for us */ + HAL_SDIO_STATE_BUSY = 0x02U, /*!< SDIO process ongoing */ +} HAL_SDIO_StateTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group2 SDIO Handle and Structure definition + * @{ + */ +/** + * @brief SDIO Card Common Control Register Structure definition + */ +typedef struct +{ + uint8_t sdio_revision; /*!< SDIO revision */ + uint8_t cccr_revision; /*!< CCCR version */ + uint8_t sd_spec_revision; /*!< SD revision */ + uint8_t bus_width_8Bit; /*!< SDIO bus width 8 bit support */ + uint32_t card_capability; /*!< SDIO card capability */ + uint32_t commonCISPointer; /*!< point to common CIS */ +} HAL_SDIO_CCCR_TypeDef; + +/** + * @brief sdio card FBR register(Function Basic Register) + */ +typedef struct +{ + uint8_t flags; /*!< SDIO current IO flags */ + uint8_t ioStdFunctionCode; /*!< SDIO current IO standard function code */ + uint8_t ioExtFunctionCode; /*!< SDIO current IO extended function code */ + uint32_t ioPointerToCIS; /*!< SDIO current IO pointer to CIS */ + uint32_t ioPointerToCSA; /*!< SDIO current IO pointer to CSA */ +} HAL_SDIO_FBR_t; + +/** + * @brief SDIO CMD52 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint8_t ReadAfterWrite; /*!< This is the read after write flag, it is used for write access only. */ + uint8_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_DirectCmd_TypeDef; + +/** + * @brief SDIO CMD53 Structure definition + */ +typedef struct +{ + uint32_t Reg_Addr; /*!< This is the address of the byte of data inside of the selected function to read or write */ + uint32_t OpCode; /*!< Read/Write operation mode */ + uint32_t Block_Mode; /*!< Bytes or Blocks mode */ + uint32_t IOFunctionNbr; /*!< The number of the function within the IO card you wish to read or write */ +} HAL_SDIO_ExtendedCmd_TypeDef; + +#define SDIO_InitTypeDef SDMMC_InitTypeDef +#define SDIO_TypeDef SDMMC_TypeDef + +/** + * @brief SDIO handle Structure definition + */ +typedef struct __SDIO_HandleTypeDef +{ + SDIO_TypeDef *Instance; /*!< SDIO registers base address */ + + SDIO_InitTypeDef Init; /*!< SDIO required parameters */ + + HAL_LockTypeDef Lock; /*!< SDIO locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SDIO Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SDIO Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SDIO Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SDIO Rx Transfer size */ + + uint32_t remaining_data; /*!< Remaining data to transfer */ + + uint32_t next_data_addr; /*!< SDIO Next data address */ + + __IO uint32_t next_reg_addr; /*!< SDIO Next register address */ + + uint16_t block_size; /*!< SDIO Block size */ + + __IO uint32_t Context; /*!< SDIO transfer context */ + + __IO HAL_SDIO_StateTypeDef State; /*!< SDIO card State */ + + __IO uint32_t ErrorCode; /*!< SDIO Card Error codes */ + + uint8_t IOFunctionMask; /*!< SDIO used to record current enabled io interrupt */ + + volatile uint8_t IOInterruptNbr; /*!< SDIO used to record total enabled io interrupt numbers */ + + void (* SDIO_IOFunction_Callback[SDIO_MAX_IO_NUMBER])(struct __SDIO_HandleTypeDef *hsdio, uint32_t func); + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* RxCpltCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* ErrorCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspInitCallback)(struct __SDIO_HandleTypeDef *hsdio); + void (* MspDeInitCallback)(struct __SDIO_HandleTypeDef *hsdio); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) + void (* DriveTransceiver_1_8V_Callback)(struct __SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + + HAL_StatusTypeDef(* SDIO_IdentifyCard)(struct __SDIO_HandleTypeDef *hsdio); + +} SDIO_HandleTypeDef; + +/** + * @} + */ +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +/** @defgroup SDIO_Exported_Types_Group3 SDIO Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SDIO_TX_CPLT_CB_ID = 0x00U, /*!< SDIO Tx Complete Callback ID */ + HAL_SDIO_RX_CPLT_CB_ID = 0x01U, /*!< SDIO Rx Complete Callback ID */ + HAL_SDIO_ERROR_CB_ID = 0x02U, /*!< SDIO Error Callback ID */ + HAL_SDIO_MSP_INIT_CB_ID = 0x10U, /*!< SDIO MspInit Callback ID */ + HAL_SDIO_MSP_DEINIT_CB_ID = 0x11U /*!< SDIO MspDeInit Callback ID */ +} HAL_SDIO_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SDIO_Exported_Types_Group4 SDIO Callback pointer definition + * @{ + */ +typedef void (*pSDIO_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +typedef void (*pSDIO_TransceiverCallbackTypeDef)(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +typedef HAL_StatusTypeDef(*pSDIO_IdentifyCardCallbackTypeDef)(SDIO_HandleTypeDef *hsdio); +typedef void (*HAL_SDIO_IOFunction_CallbackTypeDef)(SDIO_HandleTypeDef *hsdio, uint32_t func); +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Constants SDIO Exported Constants + * @{ + */ + +/** @defgroup SDIO_Exported_Constansts_Group1 SDIO Error status Structure definition + * @{ + */ +#define HAL_SDIO_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SDIO_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SDIO_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SDIO_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SDIO_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SDIO_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_SDIO_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group2 SDIO context enumeration + * @{ + */ +#define SDIO_CONTEXT_NONE 0x00U /*!< None */ +#define SDIO_CONTEXT_READ_SINGLE_BLOCK 0x01U /*!< Read single block operation */ +#define SDIO_CONTEXT_READ_MULTIPLE_BLOCK 0x02U /*!< Read multiple blocks operation */ +#define SDIO_CONTEXT_WRITE_SINGLE_BLOCK 0x10U /*!< Write single block operation */ +#define SDIO_CONTEXT_WRITE_MULTIPLE_BLOCK 0x20U /*!< Write multiple blocks operation */ +#define SDIO_CONTEXT_IT 0x08U /*!< Process in Interrupt mode */ +#define SDIO_CONTEXT_DMA 0x80U /*!< Process in DMA mode */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group3 SDIO Block mode enumeration + * @{ + */ +#define HAL_SDIO_MODE_BYTE SDMMC_SDIO_MODE_BYTE +#define HAL_SDIO_MODE_BLOCK SDMMC_SDIO_MODE_BLOCK +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group4 SDIO operation code enumeration + * @{ + */ +#define HAL_SDIO_OP_CODE_NO_INC SDMMC_SDIO_NO_INC +#define HAL_SDIO_OP_CODE_AUTO_INC SDMMC_SDIO_AUTO_INC +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group5 SDIO Read After Write(RAW) enumeration + * @{ + */ +#define HAL_SDIO_WRITE_ONLY SDMMC_SDIO_WO /*!< SDIO Write only */ +#define HAL_SDIO_READ_AFTER_WRITE SDMMC_SDIO_RAW /*!< SDIO Read after write */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group6 SDIO wire mode enumeration + * @{ + */ +#define HAL_SDIO_1_WIRE_MODE 0U /*!< SDIO wire support 1 wire */ +#define HAL_SDIO_4_WIRES_MODE 1U /*!< SDIO wire support 4 wires */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group7 SDIO Data block size enumeration + * @{ + */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1BYTE 1U /*!< SDIO data block size 1 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2BYTE 2U /*!< SDIO data block size 2 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_4BYTE 4U /*!< SDIO data block size 4 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_8BYTE 8U /*!< SDIO data block size 8 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_16BYTE 16U /*!< SDIO data block size 16 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_32BYTE 32U /*!< SDIO data block size 32 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_64BYTE 64U /*!< SDIO data block size 64 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_128BYTE 128U /*!< SDIO data block size 128 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_256BYTE 256U /*!< SDIO data block size 256 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_512BYTE 512U /*!< SDIO data block size 512 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_1024BYTE 1024U /*!< SDIO data block size 1024 byte */ +#define HAL_SDIO_DATA_BLOCK_SIZE_2048BYTE 2048U /*!< SDIO data block size 2048 byte */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group8 SDIO Bus Width enumeration + * @{ + */ +#define HAL_SDIO_BUS_WIDTH_8BIT_NOT_SUPPORTED 0U /*!< SDIO bus width 8 bit is not supported */ +#define HAL_SDIO_BUS_WIDTH_8BIT_SUPPORTED 1U /*!< SDIO bus width 8 bit is supported */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group9 SDIO Data rate definitions + * @{ + */ +#define HAL_SDIOS_DATA_RATE_SDR12 0U /*!< SDIO Data rate SDR12 */ +#define HAL_SDIOS_DATA_RATE_SDR25 1U /*!< SDIO Data rate SDR25 */ +#define HAL_SDIOS_DATA_RATE_SDR50 2U /*!< SDIO Data rate SDR50 */ +#define HAL_SDIOS_DATA_RATE_DDR50 3U /*!< SDIO Data rate DDR50 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group10 SDIO Functions definitions + * @{ + */ +#define HAL_SDIO_FUNCTION_0 0U /*!< SDIO function 0 */ +#define HAL_SDIO_FUNCTION_1 1U /*!< SDIO function 1 */ +#define HAL_SDIO_FUNCTION_2 2U /*!< SDIO function 2 */ +#define HAL_SDIO_FUNCTION_3 3U /*!< SDIO function 3 */ +#define HAL_SDIO_FUNCTION_4 4U /*!< SDIO function 4 */ +#define HAL_SDIO_FUNCTION_5 5U /*!< SDIO function 5 */ +#define HAL_SDIO_FUNCTION_6 6U /*!< SDIO function 6 */ +#define HAL_SDIO_FUNCTION_7 7U /*!< SDIO function 7 */ +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constansts_Group11 SDIO FBR definitions + * @{ + */ +#define HAL_SDIO_FBR_SUPPORT_CSA 1U /*!< SDIO function support CSA */ +#define HAL_SDIO_FBR_SUPPORT_POWER_SELECTION 1U /*!< SDIO function support power selection */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_macros SDIO Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** + * @brief Enable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SDIO device interrupt. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of @ref SDMMC_LL_Interrupt_sources. + * @retval None + */ +#define __HAL_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SDIO flag is set or not. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @ref SDMMC_LL_Flags. + * @retval The new state of SDIO FLAG (SET or RESET). + */ +#define __HAL_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SDIO's pending flags. + * @param __HANDLE__ SDIO Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one or a combination of @ref SDMMC_LL_Flags. + * @retval None + */ +#define __HAL_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SDIO interrupt has occurred or not. + * @param __HANDLE__ SDIO Handle. + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of @ref SDMMC_LL_Interrupt_sources. + * @retval The new state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDIO interrupt is enabled or not. + * @param __HANDLE__ : SDIO handle. + * @param __INTERRUPT__ : specifies the SDMMC interrupt source to check. + * @retval The state of SDIO IT (SET or RESET). + */ +#define __HAL_SDIO_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + __SDMMC_GET_IT_SOURCE((__HANDLE__)->Instance, (__INTERRUPT__)) +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Exported_Functions SDIO Exported Functions + * @{ + */ +/** @defgroup SDIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_Init(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DeInit(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_MspInit(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_MspDeInit(SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_SetDataBusWidth(SDIO_HandleTypeDef *hsdio, uint32_t BusWide); +HAL_StatusTypeDef HAL_SDIO_ConfigFrequency(SDIO_HandleTypeDef *hsdio, uint32_t ClockSpeed); + +HAL_StatusTypeDef HAL_SDIO_SetBlockSize(SDIO_HandleTypeDef *hsdio, uint8_t function_nbr, uint16_t BlockSize); +HAL_StatusTypeDef HAL_SDIO_SetSpeedMode(SDIO_HandleTypeDef *hsdio, uint32_t DataRate); + +HAL_StatusTypeDef HAL_SDIO_CardReset(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_GetCardCommonControlRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CCCR_TypeDef *pCccr); +HAL_StatusTypeDef HAL_SDIO_GetCardFBRRegister(SDIO_HandleTypeDef *hsdio, HAL_SDIO_FBR_t *pFbr); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group3 Process functions + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_ReadDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t *pData); +HAL_StatusTypeDef HAL_SDIO_WriteDirect(SDIO_HandleTypeDef *hsdio, HAL_SDIO_DirectCmd_TypeDef *Argument, uint8_t Data); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte, uint32_t Timeout_Ms); + +HAL_StatusTypeDef HAL_SDIO_ReadExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); + +HAL_StatusTypeDef HAL_SDIO_WriteExtended_DMA(SDIO_HandleTypeDef *hsdio, HAL_SDIO_ExtendedCmd_TypeDef *Argument, + uint8_t *pData, uint32_t Size_byte); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group4 IRQHandler and callback functions + * @{ + */ +void HAL_SDIO_IRQHandler(SDIO_HandleTypeDef *hsdio); + +void HAL_SDIO_TxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_RxCpltCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_ErrorCallback(SDIO_HandleTypeDef *hsdio); +void HAL_SDIO_IOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t func); +#if (USE_SDIO_TRANSCEIVER != 0U) +/* Callback to switch in 1.8V mode */ +void HAL_SDIO_DriveTransceiver_1_8V_Callback(SDIO_HandleTypeDef *hsdio, FlagStatus status); +#endif /* USE_SDIO_TRANSCEIVER */ + +#if defined (USE_HAL_SDIO_REGISTER_CALLBACKS) && (USE_HAL_SDIO_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SDIO_RegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID, + pSDIO_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_UnRegisterCallback(SDIO_HandleTypeDef *hsdio, HAL_SDIO_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SDIO_REGISTER_CALLBACKS */ + +#if (USE_SDIO_TRANSCEIVER != 0U) +HAL_StatusTypeDef HAL_SDIO_RegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDIO_UnRegisterTransceiverCallback(SDIO_HandleTypeDef *hsdio); +#endif /* USE_SDIO_TRANSCEIVER */ + +HAL_StatusTypeDef HAL_SDIO_RegisterIOFunctionCallback(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction, + HAL_SDIO_IOFunction_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_SDIO_RegisterIdentifyCardCallback(SDIO_HandleTypeDef *hsdio, + pSDIO_IdentifyCardCallbackTypeDef pCallback); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SDIO_StateTypeDef HAL_SDIO_GetState(const SDIO_HandleTypeDef *hsdio); +uint32_t HAL_SDIO_GetError(const SDIO_HandleTypeDef *hsdio); +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions_Group6 Peripheral IO interrupt + * @{ + */ +HAL_StatusTypeDef HAL_SDIO_EnableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunctionInterrupt(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_DisableIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_SelectIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); +HAL_StatusTypeDef HAL_SDIO_AbortIOFunction(SDIO_HandleTypeDef *hsdio, uint32_t IOFunction); + +HAL_StatusTypeDef HAL_SDIO_EnableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); +HAL_StatusTypeDef HAL_SDIO_DisableIOAsynInterrupt(SDIO_HandleTypeDef *hsdio); + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Types SDIO Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines ---------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Defines SDIO Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Variables SDIO Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Constants SDIO Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Macros SDIO Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes --------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions_Prototypes SDIO Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup SDIO_Private_Functions SDIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SDMMC1 || SDMMC2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32H7xx_HAL_SDIO_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h index cee1ffdd..e90d546c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_sdram.h @@ -211,7 +211,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); * @{ */ /* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h index 4180c713..0a9e11ae 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_swpmi.h @@ -92,7 +92,7 @@ typedef struct SWPMI_InitTypeDef Init; /*!< SWPMI communication parameters */ - uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ + const uint32_t *pTxBuffPtr; /*!< Pointer to SWPMI Tx transfer Buffer */ uint32_t TxXferSize; /*!< SWPMI Tx Transfer size */ @@ -122,7 +122,7 @@ typedef struct void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */ void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */ void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ } SWPMI_HandleTypeDef; @@ -145,7 +145,7 @@ typedef enum * @brief SWPMI callback pointer definition */ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} @@ -170,7 +170,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); #define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080) /*!< Transceiver not ready */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) #define HAL_SWPMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100) /*!< Invalid callback error */ -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @} */ @@ -258,14 +258,14 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @retval None */ #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1) -#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET) -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /** * @brief Enable the SWPMI peripheral. @@ -401,7 +401,8 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi); * @arg SWPMI_IT_RXBFIE Receive buffer full interrupt. * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET) +#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__))\ + == (__IT__)) ? SET : RESET) /** * @} @@ -424,14 +425,15 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef *hswpmi, pSWPMI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef *hswpmi, HAL_SWPMI_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, const uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi); HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi); @@ -444,8 +446,8 @@ void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi); void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi); /* Peripheral Control and State functions ************************************/ -HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi); -uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi); +HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(const SWPMI_HandleTypeDef *hswpmi); +uint32_t HAL_SWPMI_GetError(const SWPMI_HandleTypeDef *hswpmi); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h index c6fced02..5f0db220 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_uart.h @@ -1233,7 +1233,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1248,8 +1248,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h index 518c0aa3..28ba1ed1 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_usart.h @@ -706,8 +706,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h index 8f2e4dc1..bee4437e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h index c8f38afa..8ca787b3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_adc.h @@ -386,12 +386,12 @@ extern "C" { #endif /* ADC_VER_V5_3 */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) +#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) #define TEMPSENSOR_CAL2_TEMP ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L) /* Internal temperature sensor , temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR 110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */ #else -#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been +#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */ #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ @@ -2600,7 +2600,7 @@ typedef struct * (1) Available on devices with several ADC instances. * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr; @@ -2688,7 +2688,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC)); } @@ -2750,7 +2750,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } @@ -2887,7 +2887,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff) { /* Retrieve bits with position in register depending on parameter */ /* "SingleDiff". */ @@ -3059,7 +3059,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * (1): Specific to ADC instance: ADC1, ADC2 * (2): Specific to ADC instance: ADC3 */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { #if defined (ADC_VER_V5_3) @@ -3204,7 +3204,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_MODE_NONE * @arg @ref LL_ADC_LP_AUTOWAIT */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY)); } @@ -3285,7 +3285,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_19 * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected) */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) if (ADCx != ADC3) @@ -3458,7 +3458,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3484,7 +3484,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off * @arg @ref LL_ADC_OFFSET_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); @@ -3526,7 +3526,7 @@ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offset * @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE * @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(const ADC_TypeDef *ADCx, uint32_t Offsety) { return (uint32_t)((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL)); } @@ -3581,7 +3581,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -3649,7 +3649,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offs * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3713,7 +3713,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety) { if (ADCx == ADC3) { @@ -3787,7 +3787,7 @@ __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, * @arg @ref LL_ADC_OFFSET_DISABLE * @arg @ref LL_ADC_OFFSET_ENABLE */ -__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety) +__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety); if (ADCx == ADC3) @@ -3898,7 +3898,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN); @@ -3925,7 +3925,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL); } @@ -3960,7 +3960,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN)); } @@ -4105,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); } @@ -4160,7 +4160,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM)); } @@ -4354,7 +4354,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); @@ -4400,7 +4400,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT)); } @@ -4438,7 +4438,7 @@ __STATIC_INLINE void LL_ADC_DisableDMAReq(ADC_TypeDef *ADCx) CLEAR_BIT (ADCx->CFGR, ADC3_CFGR_DMAEN); } -__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN) == (ADC3_CFGR_DMAEN)) ? 1UL : 0UL); } @@ -4515,7 +4515,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransferMode(ADC_TypeDef *ADCx, uint32_t D * @arg @ref LL_ADC3_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC3_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(const ADC_TypeDef *ADCx) { if (ADCx == ADC3) { @@ -4544,7 +4544,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED * @arg @ref LL_ADC_REG_DFSDM_TRANSFER */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT)); } @@ -4584,7 +4584,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD)); } @@ -4685,7 +4685,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN); @@ -4712,7 +4712,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL); } @@ -4747,7 +4747,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN)); } @@ -4794,7 +4794,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); } @@ -4827,7 +4827,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN)); } @@ -4962,7 +4962,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) @@ -5014,7 +5014,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO)); } @@ -5075,7 +5075,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMo * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS)); } @@ -5491,7 +5491,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS)); @@ -5623,7 +5623,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha * @arg @ref LL_ADC_CHANNEL_19 * @retval 0: channel in single-ended mode, else: channel in differential mode */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel) { #if defined(ADC_VER_V5_V90) return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK))); @@ -5910,7 +5910,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1. */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); @@ -6085,7 +6085,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { #if defined(ADC_VER_V5_V90) if (ADCx == ADC3) @@ -6245,7 +6245,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES */ -__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy) { if (ADCx == ADC3) { @@ -6318,7 +6318,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_GRP_INJECTED * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM)); } @@ -6364,7 +6364,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS)); } @@ -6441,7 +6441,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { #if defined(ADC_VER_V5_V90) if(ADCx==ADC3) @@ -6478,7 +6478,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -6536,7 +6536,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) * @param ADCx ADC instance * @retval 0: Boost disabled 1: Boost enabled */ -__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(const ADC_TypeDef *ADCx) { if ((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */ { @@ -6598,7 +6598,7 @@ __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint3 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL)); } @@ -6689,7 +6689,7 @@ __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON * @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B * @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF)); } @@ -6767,7 +6767,7 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C * (6) Parameter available only if ADC resolution is 12 bits. * (7) Parameter available only if ADC resolution is 16 or 14 bits. */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); } @@ -6829,7 +6829,7 @@ __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: deep power down is disabled, 1: deep power down is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL); } @@ -6878,7 +6878,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -6938,7 +6938,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -6949,7 +6949,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -7003,7 +7003,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t Calibra * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -7070,7 +7070,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -7081,7 +7081,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -7095,7 +7095,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7110,7 +7110,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7125,7 +7125,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7140,7 +7140,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7155,7 +7155,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7170,7 +7170,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA)); } @@ -7195,7 +7195,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_MULTI_MASTER_SLAVE * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, ConversionData) @@ -7265,7 +7265,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL); } @@ -7276,7 +7276,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group injected. */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL); } @@ -7298,7 +7298,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7325,7 +7325,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7352,7 +7352,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7379,7 +7379,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7406,7 +7406,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7433,7 +7433,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_INJ_RANK_4 * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS)); @@ -7459,7 +7459,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -7470,7 +7470,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -7481,7 +7481,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -7492,7 +7492,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -7503,7 +7503,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -7514,7 +7514,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL); } @@ -7525,7 +7525,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL); } @@ -7536,7 +7536,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL); } @@ -7547,7 +7547,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); } @@ -7558,7 +7558,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -7569,7 +7569,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -7580,7 +7580,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -7716,7 +7716,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL); } @@ -7728,7 +7728,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL); } @@ -7740,7 +7740,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7752,7 +7752,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL); } @@ -7764,7 +7764,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL); } @@ -7776,7 +7776,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL); } @@ -7788,7 +7788,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL); } @@ -7800,7 +7800,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL); } @@ -7812,7 +7812,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_C * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL); } @@ -7824,7 +7824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL); } @@ -7836,7 +7836,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL); } @@ -7848,7 +7848,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL); } @@ -7860,7 +7860,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL); } @@ -7872,7 +7872,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL); } @@ -7884,7 +7884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL); } @@ -7896,7 +7896,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL); } @@ -7908,7 +7908,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL); } @@ -7920,7 +7920,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL); } @@ -7932,7 +7932,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL); } @@ -7944,7 +7944,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL); } @@ -7956,7 +7956,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_ * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON) { return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL); } @@ -8230,7 +8230,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -8242,7 +8242,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -8254,7 +8254,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -8266,7 +8266,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -8278,7 +8278,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -8290,7 +8290,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL); } @@ -8302,7 +8302,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL); } @@ -8314,7 +8314,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL); } @@ -8326,7 +8326,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -8338,7 +8338,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -8350,7 +8350,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -8365,7 +8365,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h index 8db1b7cc..72b747a6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_bdma.h @@ -132,7 +132,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX2_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ @@ -499,7 +499,7 @@ LL_BDMA_CHANNEL_7) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -521,7 +521,7 @@ __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -543,7 +543,7 @@ __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -584,7 +584,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_BDMA_ConfigTransfer(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -613,7 +613,7 @@ __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channe * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -640,7 +640,7 @@ __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint3 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -668,7 +668,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, u * @arg @ref LL_BDMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_BDMA_SetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -693,7 +693,7 @@ __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint * @arg @ref LL_BDMA_MODE_NORMAL * @arg @ref LL_BDMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -719,7 +719,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -744,7 +744,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_PERIPH_INCREMENT * @arg @ref LL_BDMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -770,7 +770,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -795,7 +795,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_MEMORY_INCREMENT * @arg @ref LL_BDMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -822,7 +822,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_BDMA_SetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD * @arg @ref LL_BDMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -875,7 +875,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_BDMA_SetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -901,7 +901,7 @@ __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD * @arg @ref LL_BDMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -929,7 +929,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -956,7 +956,7 @@ __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_PRIORITY_HIGH * @arg @ref LL_BDMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -982,7 +982,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, ui * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_BDMA_SetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1007,7 +1007,7 @@ __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1033,7 +1033,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) +__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1057,7 +1057,7 @@ __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t C * @arg @ref LL_BDMA_CURRENTTARGETMEM0 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1101,7 +1101,7 @@ __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_ * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1123,7 +1123,7 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32 * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel) { register uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1154,7 +1154,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_BDMA_ConfigAddresses(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1191,7 +1191,7 @@ __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Chann * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1216,7 +1216,7 @@ __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_BDMA_SetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1239,7 +1239,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1262,7 +1262,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1287,7 +1287,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1312,7 +1312,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Chan * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1358,7 +1358,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1381,7 +1381,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) +__STATIC_INLINE void LL_BDMA_SetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1403,7 +1403,7 @@ __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Cha * @arg @ref LL_BDMA_CHANNEL_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -1449,7 +1449,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_BDMA_SetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) { UNUSED(BDMAx); MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -1493,7 +1493,7 @@ __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Chan * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel) { UNUSED(BDMAx); return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -1513,7 +1513,7 @@ __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); } @@ -1524,7 +1524,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1535,7 +1535,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1546,7 +1546,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1557,7 +1557,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1568,7 +1568,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1579,7 +1579,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1590,7 +1590,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); } @@ -1611,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1622,7 +1622,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1633,7 +1633,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1644,7 +1644,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1655,7 +1655,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1677,7 +1677,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1688,7 +1688,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1710,7 +1710,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1721,7 +1721,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1743,7 +1743,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1754,7 +1754,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1765,7 +1765,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1776,7 +1776,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); } @@ -1787,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1798,7 +1798,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1809,7 +1809,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1820,7 +1820,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1831,7 +1831,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1842,7 +1842,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) * @param BDMAx BDMA Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) +__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(const BDMA_TypeDef *BDMAx) { return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -2264,7 +2264,7 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2286,7 +2286,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2308,7 +2308,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_EnableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2330,7 +2330,7 @@ __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2352,7 +2352,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2374,7 +2374,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE void LL_BDMA_DisableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2396,7 +2396,7 @@ __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2418,7 +2418,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; @@ -2440,7 +2440,7 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Ch * @arg @ref LL_BDMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel) { uint32_t bdma_base_addr = (uint32_t)BDMAx; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h index 44fd717d..0a0ba777 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_comp.h @@ -341,7 +341,7 @@ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COM * @arg @ref LL_COMP_WINDOWMODE_DISABLE * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON */ -__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON) +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) { return (uint32_t)(READ_BIT(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE)); } @@ -378,7 +378,7 @@ __STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMod * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED * @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER */ -__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_PWRMODE)); } @@ -480,7 +480,7 @@ __STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlu * @arg @ref LL_COMP_INPUT_PLUS_IO2 * @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1 */ -__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) { #if defined (COMP_CFGRx_INP2SEL) return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL)); @@ -549,7 +549,7 @@ __STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMi * @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1 * @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP */ -__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)); } @@ -580,7 +580,7 @@ __STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t In * @arg @ref LL_COMP_HYSTERESIS_MEDIUM * @arg @ref LL_COMP_HYSTERESIS_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_HYST)); } @@ -615,7 +615,7 @@ __STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t Out * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED * @arg @ref LL_COMP_OUTPUTPOL_INVERTED */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_POLARITY)); } @@ -660,7 +660,7 @@ __STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32 * @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5 * @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) { return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_BLANKING)); } @@ -685,7 +685,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_AF_PK2 * @retval None */ -__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uint32_t CompAFx) +__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(const COMP_TypeDef *COMPx, uint32_t CompAFx) { MODIFY_REG(COMP12->OR, 0x7FFUL, (COMPx == COMP1) ? ((~CompAFx) & 0x7FFUL) : CompAFx); } @@ -706,7 +706,7 @@ __STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uin * @arg @ref LL_COMP_AF_PI4 * @arg @ref LL_COMP_AF_PK2 */ -__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(COMP_TypeDef *COMPx ) +__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(const COMP_TypeDef *COMPx ) { return (uint32_t) ((COMPx == COMP1) ? ((~COMP12->OR) & 0x7FFUL) : (COMP12->OR & 0x7FFUL)); } @@ -751,7 +751,7 @@ __STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_EN) == (COMP_CFGRx_EN)) ? 1UL : 0UL); } @@ -778,7 +778,7 @@ __STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_LOCK) == (COMP_CFGRx_LOCK)) ? 1UL : 0UL); } @@ -803,7 +803,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx) * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH */ -__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -829,7 +829,7 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -847,7 +847,7 @@ __STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval None */ -__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(const COMP_TypeDef *COMPx) { if (COMPx == COMP1) { @@ -895,7 +895,7 @@ __STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx) * @param COMPx Comparator instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx) +__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(const COMP_TypeDef *COMPx) { return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h index fe1f6f9e..f36ebfc0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_cordic.h @@ -131,12 +131,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE * @{ */ -#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two - 16-bit data input (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input - (Q1.31 format) */ +#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one + 32-bits data input (Q1.31 format), or two + 16-bits data input (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input + (Q1.31 format) */ /** * @} */ @@ -144,12 +144,12 @@ extern "C" { /** @defgroup CORDIC_LL_EC_NBREAD NBREAD * @{ */ -#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two - 16-bit data output (Q1.15 format) packed - in one 32 bits Data */ -#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output - (Q1.31 format) */ +#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one + 32-bits data output (Q1.31 format), or two + 16-bits data output (Q1.15 format) packed + in one 32 bits Data */ +#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output + (Q1.31 format) */ /** * @} */ @@ -218,9 +218,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions * @{ */ @@ -749,8 +747,6 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx) * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h index c05815a9..5195c3b7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma.h @@ -140,7 +140,7 @@ typedef struct This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ uint32_t PeriphRequest; /*!< Specifies the peripheral request. - This parameter can be a value of @ref DMAMUX1_Request_selection + This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ @@ -486,7 +486,7 @@ typedef struct * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -508,7 +508,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -530,7 +530,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -571,7 +571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 *@retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -599,7 +599,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -624,7 +624,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -651,7 +651,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_MODE_PFCTRL * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -677,7 +677,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t * @arg @ref LL_DMA_MODE_CIRCULAR * @arg @ref LL_DMA_MODE_PFCTRL */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -702,7 +702,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_PERIPH_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -726,7 +726,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @arg @ref LL_DMA_PERIPH_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_MEMORY_INCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -775,7 +775,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -801,7 +801,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -826,7 +826,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -877,7 +877,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 * @retval None */ -__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_OFFSETSIZE_PSIZE * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 */ -__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -953,7 +953,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -979,7 +979,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1001,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1023,7 +1023,7 @@ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_ * @param NbData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1072,7 +1072,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, ui * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1396,7 +1396,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, * * @note (*) Availability depends on devices. */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream) { return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); } @@ -1421,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t St * @arg @ref LL_DMA_MBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1447,7 +1447,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_MBURST_INC8 * @arg @ref LL_DMA_MBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_PBURST_INC16 * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1500,7 +1500,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_PBURST_INC8 * @arg @ref LL_DMA_PBURST_INC16 */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1525,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_CURRENTTARGETMEM1 * @retval None */ -__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1549,7 +1549,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_CURRENTTARGETMEM0 * @arg @ref LL_DMA_CURRENTTARGETMEM1 */ -__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t S * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1615,9 +1615,9 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) { - register uint32_t dma_base_addr = (uint32_t)DMAx; + uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); } @@ -1643,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_FIFOSTATUS_EMPTY * @arg @ref LL_DMA_FIFOSTATUS_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1665,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1687,7 +1687,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1714,7 +1714,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1740,7 +1740,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1801,7 +1801,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint3 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1837,7 +1837,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param PeriphAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1885,7 +1885,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1908,7 +1908,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1933,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Str * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @param MemoryAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1981,7 +1981,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2004,7 +2004,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Str * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2027,7 +2027,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Str * @param Address Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2049,7 +2049,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream * @arg @ref LL_DMA_STREAM_7 * @retval Between 0 to 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t St * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); } @@ -2081,7 +2081,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); } @@ -2092,7 +2092,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); } @@ -2103,7 +2103,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); } @@ -2114,7 +2114,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); } @@ -2125,7 +2125,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); } @@ -2136,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); } @@ -2147,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); } @@ -2158,7 +2158,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); } @@ -2169,7 +2169,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); } @@ -2180,7 +2180,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); } @@ -2191,7 +2191,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); } @@ -2202,7 +2202,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); } @@ -2213,7 +2213,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); } @@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); } @@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); } @@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); } @@ -2257,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); } @@ -2268,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); } @@ -2279,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); } @@ -2290,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); } @@ -2301,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); } @@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); } @@ -2323,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); } @@ -2334,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); } @@ -2345,7 +2345,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); } @@ -2356,7 +2356,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); } @@ -2367,7 +2367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); } @@ -2378,7 +2378,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); } @@ -2389,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); } @@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); } @@ -2411,7 +2411,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); } @@ -2422,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); } @@ -2433,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); } @@ -2444,7 +2444,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); } @@ -2455,7 +2455,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); } @@ -2466,7 +2466,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); } @@ -2477,7 +2477,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); } @@ -2488,7 +2488,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); } @@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); } @@ -2967,7 +2967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -2989,7 +2989,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3011,7 +3011,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3055,7 +3055,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3077,7 +3077,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3099,7 +3099,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3121,7 +3121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3143,7 +3143,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3165,7 +3165,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3187,7 +3187,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3209,7 +3209,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3231,7 +3231,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3253,7 +3253,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Strea * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -3275,7 +3275,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre * @arg @ref LL_DMA_STREAM_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) { uint32_t dma_base_addr = (uint32_t)DMAx; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h index daea4758..905cbc7e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dma2d.h @@ -582,7 +582,7 @@ __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); } @@ -619,7 +619,7 @@ __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); } @@ -644,7 +644,7 @@ __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); } @@ -679,7 +679,7 @@ __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); } @@ -712,7 +712,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); } @@ -739,7 +739,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_ * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); } @@ -766,7 +766,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); } @@ -794,7 +794,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); } @@ -821,7 +821,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); } @@ -844,7 +844,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t Line * @param DMA2Dx DMA2D Instance * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); } @@ -867,7 +867,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint * @param DMA2Dx DMA2D Instance * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); } @@ -890,7 +890,7 @@ __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrO * @param DMA2Dx DMA2D Instance * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); } @@ -913,7 +913,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t O * @param DMA2Dx DMA2D Instance * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); } @@ -934,8 +934,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) */ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) { - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); + WRITE_REG(DMA2Dx->OCOLR, OutputColor); } /** @@ -950,7 +949,7 @@ __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t Out * @param DMA2Dx DMA2D Instance * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); @@ -974,7 +973,7 @@ __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t L * @param DMA2Dx DMA2D Instance * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); } @@ -997,7 +996,7 @@ __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTi * @param DMA2Dx DMA2D Instance * @retval Dead time value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); } @@ -1030,7 +1029,7 @@ __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); } @@ -1057,7 +1056,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); } @@ -1079,7 +1078,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); } @@ -1124,7 +1123,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); } @@ -1153,7 +1152,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); } @@ -1176,7 +1175,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); } @@ -1203,7 +1202,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); } @@ -1230,7 +1229,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); } @@ -1253,7 +1252,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); } @@ -1293,7 +1292,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); } @@ -1316,7 +1315,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); } @@ -1339,7 +1338,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); } @@ -1362,7 +1361,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); } @@ -1385,7 +1384,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); } @@ -1412,7 +1411,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); } @@ -1441,7 +1440,7 @@ __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint * @arg @ref LL_DMA2D_CSS_422 * @arg @ref LL_DMA2D_CSS_420 */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); } @@ -1471,7 +1470,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t Me * @param DMA2Dx DMA2D Instance * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); } @@ -1493,7 +1492,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); } @@ -1538,7 +1537,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_INPUT_MODE_A8 * @arg @ref LL_DMA2D_INPUT_MODE_A4 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); } @@ -1567,7 +1566,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); } @@ -1590,7 +1589,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alph * @param DMA2Dx DMA2D Instance * @retval Alpha value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); } @@ -1617,7 +1616,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t * @arg @ref LL_DMA2D_RB_MODE_REGULAR * @arg @ref LL_DMA2D_RB_MODE_SWAP */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); } @@ -1644,7 +1643,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32 * @arg @ref LL_DMA2D_ALPHA_REGULAR * @arg @ref LL_DMA2D_ALPHA_INVERTED */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); } @@ -1667,7 +1666,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); } @@ -1707,7 +1706,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t R * @param DMA2Dx DMA2D Instance * @retval Red color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); } @@ -1730,7 +1729,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Green color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); } @@ -1753,7 +1752,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t * @param DMA2Dx DMA2D Instance * @retval Blue color value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); } @@ -1776,7 +1775,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_ * @param DMA2Dx DMA2D Instance * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); } @@ -1799,7 +1798,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t C * @param DMA2Dx DMA2D Instance * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); } @@ -1826,7 +1825,7 @@ __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint3 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx) { return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); } @@ -1850,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); } @@ -1861,7 +1860,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); } @@ -1872,7 +1871,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); } @@ -1883,7 +1882,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); } @@ -1894,7 +1893,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); } @@ -1905,7 +1904,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); } @@ -2122,7 +2121,7 @@ __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); } @@ -2133,7 +2132,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); } @@ -2144,7 +2143,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); } @@ -2155,7 +2154,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); } @@ -2166,7 +2165,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); } @@ -2177,7 +2176,7 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) * @param DMA2Dx DMA2D Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) +__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx) { return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); } @@ -2193,16 +2192,16 @@ __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) * @{ */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); +ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx); ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); +uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h index bf4cffa0..be9b2fc4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_dmamux.h @@ -726,7 +726,7 @@ extern "C" { * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -919,7 +919,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -950,7 +950,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -980,7 +980,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1015,7 +1015,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1109,7 +1109,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1169,7 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1199,7 +1199,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1229,7 +1229,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1284,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1338,7 +1338,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1360,7 +1360,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1400,7 +1400,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1427,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1453,7 +1453,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1477,7 +1477,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1561,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1607,7 +1607,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI2 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1628,7 +1628,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1641,7 +1641,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1654,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1667,7 +1667,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1680,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1693,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1706,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1719,7 +1719,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1758,7 +1758,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1784,7 +1784,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1797,7 +1797,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1810,7 +1810,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1823,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1836,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1849,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1862,7 +1862,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1875,7 +1875,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1901,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1914,7 +1914,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1927,7 +1927,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1940,7 +1940,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1966,7 +1966,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1979,7 +1979,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -1992,7 +1992,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2005,7 +2005,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2018,7 +2018,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2057,7 +2057,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2070,7 +2070,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2083,7 +2083,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2109,7 +2109,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2122,7 +2122,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2135,7 +2135,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2148,7 +2148,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2161,7 +2161,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2174,7 +2174,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2187,7 +2187,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2200,7 +2200,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2226,7 +2226,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2239,7 +2239,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2277,7 +2277,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2307,7 +2307,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2337,7 +2337,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2359,7 +2359,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2381,7 +2381,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; @@ -2403,7 +2403,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h index 8e92c3d4..5edb287d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmac.h @@ -38,7 +38,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants * @{ @@ -147,9 +146,7 @@ extern "C" { * @} */ - /* Exported functions --------------------------------------------------------*/ - /** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions * @{ */ @@ -1033,8 +1030,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint * @} */ - - #if defined(USE_FULL_LL_DRIVER) /** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions * @{ @@ -1042,7 +1037,6 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx); ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx); - /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h index 3d34898e..7509bced 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_fmc.h @@ -190,61 +190,62 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ } FMC_NORSRAM_InitTypeDef; /** @@ -288,7 +289,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; /** @@ -1056,11 +1057,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -1086,11 +1087,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1101,7 +1102,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -1117,9 +1118,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1131,7 +1132,7 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h index b51f9d3b..b099741d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_gpio.h @@ -309,7 +309,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); } @@ -377,7 +377,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); } @@ -515,7 +515,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); } @@ -591,7 +591,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); @@ -669,7 +669,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * @@ -741,7 +741,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -752,7 +752,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -771,7 +771,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -800,7 +800,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -823,7 +823,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -954,7 +954,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h index d3f3608f..741d758b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hrtim.h @@ -1972,7 +1972,7 @@ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCT { uint32_t shift = ((3U * ADCTrig) & 0x1FU); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); } @@ -2247,7 +2247,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2464,7 +2464,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -3138,7 +3138,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3158,7 +3158,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3178,7 +3178,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3209,7 +3209,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3238,7 +3238,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3268,7 +3268,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3290,7 +3290,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3313,7 +3313,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3335,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3358,7 +3358,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3380,7 +3380,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3405,7 +3405,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3429,7 +3429,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3454,7 +3454,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3478,7 +3478,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3503,7 +3503,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3527,7 +3527,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3552,7 +3552,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3576,7 +3576,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3663,7 +3663,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3743,7 +3743,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3763,7 +3763,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3783,7 +3783,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3871,7 +3871,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -3957,7 +3957,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -3977,7 +3977,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -3997,7 +3997,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4017,7 +4017,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRT { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -4062,7 +4062,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4103,7 +4103,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4124,7 +4124,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4145,7 +4145,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4165,7 +4165,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4195,7 +4195,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4225,7 +4225,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4255,7 +4255,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -4277,7 +4277,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4442,7 +4442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeD { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4464,7 +4464,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4524,7 +4524,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4581,7 +4581,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4627,7 +4627,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4670,7 +4670,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *H uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4704,7 +4704,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4733,7 +4733,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4761,7 +4761,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4782,7 +4782,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4802,7 +4802,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4825,7 +4825,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4847,7 +4847,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -4868,7 +4868,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -4888,7 +4888,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -4911,7 +4911,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -4933,7 +4933,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -4953,7 +4953,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -4973,7 +4973,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -4993,7 +4993,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5013,7 +5013,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5049,7 +5049,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5089,7 +5089,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5125,7 +5125,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5157,7 +5157,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5185,7 +5185,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5224,7 +5224,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5260,7 +5260,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5389,7 +5389,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5509,7 +5509,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIM { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5630,7 +5630,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5750,7 +5750,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRT { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5793,7 +5793,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5823,7 +5823,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5851,7 +5851,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5881,7 +5881,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } @@ -5909,7 +5909,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, u { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -5940,7 +5940,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -5968,7 +5968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6001,7 +6001,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6031,7 +6031,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6061,7 +6061,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6089,7 +6089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6119,7 +6119,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6147,7 +6147,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6176,7 +6176,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HR { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -6214,7 +6214,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6242,7 +6242,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint { uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -6323,7 +6323,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6363,7 +6363,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6401,7 +6401,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6440,7 +6440,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6476,7 +6476,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6516,7 +6516,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6554,7 +6554,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6587,7 +6587,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6618,7 +6618,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, ui { uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6770,7 +6770,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6799,7 +6799,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6824,8 +6824,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6853,7 +6853,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6878,8 +6878,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -6921,7 +6921,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -6960,8 +6960,8 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7017,7 +7017,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7041,7 +7041,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7065,7 +7065,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7089,7 +7089,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uin { uint32_t iFault = (uint8_t)POSITION_VAL(Fault); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); } @@ -7765,7 +7765,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -7787,7 +7787,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -7810,7 +7810,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -7833,7 +7833,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -7856,7 +7856,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -7878,7 +7878,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -7901,7 +7901,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -7923,7 +7923,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -7946,7 +7946,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -7968,7 +7968,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -7991,7 +7991,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8013,7 +8013,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -8034,7 +8034,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8054,7 +8054,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -8075,7 +8075,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8095,7 +8095,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -8116,7 +8116,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8136,7 +8136,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -8157,7 +8157,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8177,7 +8177,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -8198,7 +8198,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8218,7 +8218,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -8239,7 +8239,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8259,7 +8259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -8280,7 +8280,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8300,7 +8300,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -8321,7 +8321,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8341,7 +8341,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } @@ -8636,7 +8636,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8658,7 +8658,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); } @@ -8680,7 +8680,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); } @@ -8703,7 +8703,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8725,7 +8725,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); } @@ -8747,7 +8747,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); } @@ -8770,7 +8770,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8792,7 +8792,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); } @@ -8814,7 +8814,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); } @@ -8837,7 +8837,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8859,7 +8859,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); } @@ -8881,7 +8881,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); } @@ -8904,7 +8904,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8926,7 +8926,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); } @@ -8948,7 +8948,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); } @@ -8971,7 +8971,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -8993,7 +8993,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); } @@ -9015,7 +9015,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); } @@ -9036,7 +9036,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9056,7 +9056,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); } @@ -9076,7 +9076,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); } @@ -9097,7 +9097,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9117,7 +9117,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); } @@ -9137,7 +9137,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); } @@ -9158,7 +9158,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9178,7 +9178,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); } @@ -9198,7 +9198,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); } @@ -9219,7 +9219,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9239,7 +9239,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); } @@ -9259,7 +9259,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); } @@ -9280,7 +9280,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9300,7 +9300,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); } @@ -9320,7 +9320,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); } @@ -9341,7 +9341,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9361,7 +9361,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); } @@ -9381,7 +9381,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); } @@ -9402,7 +9402,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9422,7 +9422,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); } @@ -9442,7 +9442,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, u { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); } @@ -9463,7 +9463,7 @@ __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Ti { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9483,7 +9483,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); } @@ -9503,7 +9503,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); } @@ -9567,7 +9567,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9589,7 +9589,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); } @@ -9611,7 +9611,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); } @@ -9634,7 +9634,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9656,7 +9656,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); } @@ -9678,7 +9678,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); } @@ -9701,7 +9701,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9723,7 +9723,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); } @@ -9745,7 +9745,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); } @@ -9768,7 +9768,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9790,7 +9790,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); } @@ -9812,7 +9812,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); } @@ -9835,7 +9835,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9857,7 +9857,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); } @@ -9879,7 +9879,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); } @@ -9902,7 +9902,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9924,7 +9924,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); } @@ -9946,7 +9946,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); } @@ -9967,7 +9967,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -9987,7 +9987,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); } @@ -10007,7 +10007,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); } @@ -10028,7 +10028,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10048,7 +10048,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); } @@ -10068,7 +10068,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); } @@ -10089,7 +10089,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10109,7 +10109,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); } @@ -10129,7 +10129,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); } @@ -10150,7 +10150,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10170,7 +10170,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); } @@ -10190,7 +10190,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); } @@ -10211,7 +10211,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10231,7 +10231,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); } @@ -10251,7 +10251,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); } @@ -10272,7 +10272,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10292,7 +10292,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); } @@ -10312,7 +10312,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTI { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); } @@ -10333,7 +10333,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t T { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10353,7 +10353,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); } @@ -10373,7 +10373,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIM { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); } @@ -10394,7 +10394,7 @@ __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_ { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10414,7 +10414,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32 { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); } @@ -10434,7 +10434,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR { uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); } @@ -10447,7 +10447,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HR /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions * @{ */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); +ErrorStatus LL_HRTIM_DeInit(const HRTIM_TypeDef *HRTIMx); /** * @} */ @@ -10473,4 +10473,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); #endif /* STM32H7xx_LL_HRTIM_H */ - diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h index cff88b5c..689b7e57 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_hsem.h @@ -163,7 +163,7 @@ extern "C" { * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); } @@ -178,7 +178,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_COREID_CPU1 * @arg @ref LL_HSEM_COREID_CPU2 */ -__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); } @@ -190,7 +190,7 @@ __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval Process number. Value between Min_Data=0 and Max_Data=255 */ -__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); } @@ -236,7 +236,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ -__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); } @@ -261,7 +261,7 @@ __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 0 semaphore is free, 1 semaphore is locked */ -__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) * @param HSEMx HSEM Instance. * @retval key to unlock all semaphore from the same core */ -__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) { return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); } @@ -450,7 +450,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -586,7 +586,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -689,7 +689,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -736,7 +736,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_ * depends on devices. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -827,7 +827,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -872,7 +872,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h index d34acc26..743c9173 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h index fe66becb..2f362a4e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_lpuart.h @@ -2605,6 +2605,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h index 8b80c7d8..a55cb828 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_mdma.h @@ -688,7 +688,7 @@ typedef struct * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -718,7 +718,7 @@ __STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -748,7 +748,7 @@ __STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -778,7 +778,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_GenerateSWRequest(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -814,7 +814,7 @@ __STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE or @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -848,7 +848,7 @@ __STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -881,7 +881,7 @@ __STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -914,7 +914,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -947,7 +947,7 @@ __STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -980,7 +980,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) +__STATIC_INLINE void LL_MDMA_SetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1013,7 +1013,7 @@ __STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1048,7 +1048,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1083,7 +1083,7 @@ __STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1143,7 +1143,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, ui * @param BufferXferLength This parameter can be a value Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) +__STATIC_INLINE void LL_MDMA_ConfigTransfer(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1174,7 +1174,7 @@ __STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1204,7 +1204,7 @@ __STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1234,7 +1234,7 @@ __STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1267,7 +1267,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) +__STATIC_INLINE void LL_MDMA_SetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1300,7 +1300,7 @@ __STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_REQUEST_MODE_SW * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1335,7 +1335,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) +__STATIC_INLINE void LL_MDMA_SetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1370,7 +1370,7 @@ __STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_FULL_TRANSFER * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) +__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DATAALIGN_LEFT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1469,7 +1469,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisablePacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1529,7 +1529,7 @@ __STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channe * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1560,7 +1560,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t * @param Length Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) +__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1592,7 +1592,7 @@ __STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32 * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1631,7 +1631,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) +__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1670,7 +1670,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_DEST_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, ui * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) +__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1748,7 +1748,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BURST_128BEATS * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1783,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1818,7 +1818,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1853,7 +1853,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) +__STATIC_INLINE void LL_MDMA_SetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1888,7 +1888,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1923,7 +1923,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) +__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_ * @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -1993,7 +1993,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) +__STATIC_INLINE void LL_MDMA_SetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2028,7 +2028,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Cha * @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2062,7 +2062,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) +__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_DEST_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2130,7 +2130,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) +__STATIC_INLINE void LL_MDMA_SetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2164,7 +2164,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Chan * @arg @ref LL_MDMA_SRC_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2197,7 +2197,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2230,7 +2230,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Cha * @param BlkDataLength Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) +__STATIC_INLINE void LL_MDMA_SetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2261,7 +2261,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0x00010000 * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2292,7 +2292,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t * @param BlockRepeatCount Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2324,7 +2324,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Cha * @retval Between 0 to 0x00000FFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2358,7 +2358,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2393,7 +2393,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2426,7 +2426,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2459,7 +2459,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) +__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2492,7 +2492,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint * @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2526,7 +2526,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) +__STATIC_INLINE void LL_MDMA_ConfigAddresses(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2557,7 +2557,7 @@ __STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Chann * @param SrcAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) +__STATIC_INLINE void LL_MDMA_SetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2588,7 +2588,7 @@ __STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Chan * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2619,7 +2619,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t * @param DestAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) +__STATIC_INLINE void LL_MDMA_SetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2650,7 +2650,7 @@ __STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2684,7 +2684,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint * @param DestAdrUpdateValue Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2716,7 +2716,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @param DestAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2748,7 +2748,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, u * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2779,7 +2779,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMA * @param SrcAdrUpdateValue Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) +__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2810,7 +2810,7 @@ __STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, ui * @retval Between 0 to 0x0000FFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2841,7 +2841,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx * @param LinkAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) +__STATIC_INLINE void LL_MDMA_SetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2872,7 +2872,7 @@ __STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2906,7 +2906,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI or @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_MDMA_ConfigBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2941,7 +2941,7 @@ __STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) +__STATIC_INLINE void LL_MDMA_SetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -2974,7 +2974,7 @@ __STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_DEST_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3007,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32 * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) +__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3040,7 +3040,7 @@ __STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_SRC_BUS_AHB_TCM * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3108,7 +3108,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_ * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) +__STATIC_INLINE void LL_MDMA_SetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3176,7 +3176,7 @@ __STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, * @note (*) Availability depends on devices. * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3207,7 +3207,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Chan * @param MaskAddress Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) +__STATIC_INLINE void LL_MDMA_SetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3238,7 +3238,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channe * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3269,7 +3269,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Ch * @param MaskData Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) +__STATIC_INLINE void LL_MDMA_SetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3300,7 +3300,7 @@ __STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, * @retval Between 0 to 0xFFFFFFFF * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3333,7 +3333,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Chann * @arg @ref LL_MDMA_WRITE_ERROR * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3364,7 +3364,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint * @retval Between 0 to 0x0000007F * @retval None */ -__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3402,7 +3402,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uin * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(const MDMA_TypeDef *MDMAx, uint32_t Channel) { return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); } @@ -3430,7 +3430,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3460,7 +3460,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3490,7 +3490,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3520,7 +3520,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3550,7 +3550,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3580,7 +3580,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3610,7 +3610,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3640,7 +3640,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3670,7 +3670,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3700,7 +3700,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3730,7 +3730,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3760,7 +3760,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3790,7 +3790,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3820,7 +3820,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3850,7 +3850,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_ClearFlag_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3888,7 +3888,7 @@ __STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3918,7 +3918,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3948,7 +3948,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -3978,7 +3978,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4008,7 +4008,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_EnableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4038,7 +4038,7 @@ __STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4068,7 +4068,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4098,7 +4098,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4128,7 +4128,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4158,7 +4158,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE void LL_MDMA_DisableIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4188,7 +4188,7 @@ __STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4218,7 +4218,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4248,7 +4248,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4278,7 +4278,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t C * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; @@ -4308,7 +4308,7 @@ __STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Ch * @arg @ref LL_MDMA_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(const MDMA_TypeDef *MDMAx, uint32_t Channel) { uint32_t mdma_base_addr = (uint32_t)MDMAx; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h index 03ab42c7..abd81e3e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_opamp.h @@ -392,7 +392,7 @@ __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode) * @arg @ref LL_OPAMP_MODE_FUNCTIONAL * @arg @ref LL_OPAMP_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON)); } @@ -434,7 +434,7 @@ __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS * @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS */ -__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL)); } @@ -469,7 +469,7 @@ __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain * @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 * @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0)); } @@ -498,7 +498,7 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power * @arg @ref LL_OPAMP_POWERMODE_NORMAL * @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) { uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM)); @@ -536,7 +536,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC * @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL)); } @@ -572,7 +572,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *OPAMPx) { uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL); @@ -611,7 +611,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t Tr * @arg @ref LL_OPAMP_TRIMMING_FACTORY * @arg @ref LL_OPAMP_TRIMMING_USER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM)); } @@ -658,7 +658,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin * using two trimming steps (one with each transistors differential * pair NMOS and PMOS) */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *OPAMPx) { uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); @@ -675,7 +675,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT)?1UL:0UL); } @@ -728,7 +728,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P * @arg @ref LL_OPAMP_TRIMMING_PMOS * @retval 0x0...0x1F */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); @@ -779,7 +779,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN))?1UL:0UL); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h index 62039d0e..cf1ab84f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rng.h @@ -680,7 +680,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h index 85e6fadd..c7c0084f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_rtc.h @@ -903,7 +903,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -935,7 +935,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -992,7 +992,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); } @@ -1078,7 +1078,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1112,7 +1112,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } @@ -1173,7 +1173,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1184,7 +1184,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1376,7 +1376,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1411,7 +1411,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1446,7 +1446,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1481,7 +1481,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1535,7 +1535,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1575,7 +1575,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } @@ -1617,7 +1617,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1674,7 +1674,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1713,7 +1713,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1767,7 +1767,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1797,7 +1797,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1865,7 +1865,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1944,7 +1944,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1994,7 +1994,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -2058,7 +2058,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -2086,7 +2086,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2114,7 +2114,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2142,7 +2142,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2214,7 +2214,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2237,7 +2237,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2310,7 +2310,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2360,7 +2360,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2397,7 +2397,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2424,7 +2424,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2452,7 +2452,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2480,7 +2480,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2508,7 +2508,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2580,7 +2580,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2603,7 +2603,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2689,7 +2689,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2702,7 +2702,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2715,7 +2715,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2728,7 +2728,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2741,7 +2741,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2759,7 +2759,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2778,7 +2778,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2803,7 +2803,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2816,7 +2816,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2833,7 +2833,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2844,7 +2844,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -3070,7 +3070,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); } @@ -3101,7 +3101,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); } @@ -3140,7 +3140,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); } @@ -3490,7 +3490,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } @@ -3527,7 +3527,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3551,7 +3551,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3656,7 +3656,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR31 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3707,7 +3707,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -3805,7 +3805,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3832,7 +3832,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } @@ -3865,7 +3865,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3890,7 +3890,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3911,7 +3911,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL); } @@ -3922,7 +3922,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); } @@ -3933,7 +3933,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL); } @@ -3944,7 +3944,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); } @@ -3955,7 +3955,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); } @@ -3966,7 +3966,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); } @@ -3977,7 +3977,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); } @@ -3988,7 +3988,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); } @@ -3999,7 +3999,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); } @@ -4010,7 +4010,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); } @@ -4120,7 +4120,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); } @@ -4131,7 +4131,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); } @@ -4153,7 +4153,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); } @@ -4164,7 +4164,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); } @@ -4175,7 +4175,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); } @@ -4186,7 +4186,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); } @@ -4197,7 +4197,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } @@ -4801,7 +4801,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } @@ -4812,7 +4812,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } @@ -4823,7 +4823,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } @@ -4834,7 +4834,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } @@ -4846,7 +4846,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); } @@ -4857,7 +4857,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); @@ -4869,7 +4869,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); } @@ -4880,7 +4880,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h index 6e12084e..9887fe0e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_sdmmc.h @@ -30,7 +30,7 @@ extern "C" { /** @addtogroup STM32H7xx_Driver * @{ */ - +#if defined (SDMMC1) || defined (SDMMC2) /** @addtogroup SDMMC_LL * @{ */ @@ -61,10 +61,10 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ -#if (USE_SD_TRANSCEIVER != 0U) +#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ -#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ } SDMMC_InitTypeDef; @@ -160,84 +160,128 @@ typedef struct #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +/** + * @brief Masks for R5 Response + */ +/** this is the reserved for future use in spec RFU */ +#define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) +/** Out of range error */ +#define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) +/** Invalid function number */ +#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) +/** General or an unknown error */ +#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) +/** SDIO Card current state + * 00=DIS (card not selected) + * 01=CMD (data line free) + * 10=TRN (transfer on data lines) */ +#define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) +/** Illegal command error */ +#define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) +/** CRC check of previous cmd failed */ +#define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ + SDMMC_SDIO_R5_ILLEGAL_CMD | \ + SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ + SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ + SDMMC_SDIO_R5_OUT_OF_RANGE) +/** + * @brief SDIO_CMD53_MODE + */ +#define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ +#define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ + +/** + * @brief SDIO_CMD53_OP_CODE + */ +#define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ +#define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ + +/** + * @brief SDIO_CMD53_RAW + */ +#define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ +#define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ + /** * @brief SDMMC Commands Index */ -#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ -#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ -#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ /*!< for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are MMC Specific commands. */ -#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) -#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) -#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) -#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) -#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) -#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) -#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U /** * @brief Masks for errors Card Status R1 (OCR Register) @@ -291,9 +335,14 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_SWDATATIMEOUT */ + #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) @@ -303,6 +352,8 @@ typedef struct #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) +/* SDMMC FIFO Size */ +#define SDMMC_FIFO_SIZE 32U /** * @brief Command Class supported */ @@ -543,9 +594,11 @@ typedef struct * @{ */ #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) +#define SDMMC_TRANSFER_MODE_SDIO SDMMC_DCTRL_DTMODE_0 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_SDIO) || \ ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} @@ -657,6 +710,82 @@ typedef struct * @} */ +/** @defgroup SDMMC_SDIO_CCCR_Registers + * @{ + */ +/*-------------------------------- CCCR0 ----------------------------------*/ +#define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ + +/*-------------------------------- CCCR4 ----------------------------------*/ +#define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ + +/*-------------------------------- CCCR8 ----------------------------------*/ +#define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ + +/*-------------------------------- CCCR12 ---------------------------------*/ +#define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ + +/*-------------------------------- CCCR16 ---------------------------------*/ +#define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ + +/*-------------------------------- CCCR20 ---------------------------------*/ +#define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ + +/*-------------------------------- F1BR0 ----------------------------------*/ +#define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ + +/*-------------------------------- F1BR8 ----------------------------------*/ +#define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ + +/*-------------------------------- F1BR12 ---------------------------------*/ +#define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ + +/*-------------------------------- F1BR16 ---------------------------------*/ +#define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ +/** + * @} + */ + /** * @} */ @@ -871,6 +1000,38 @@ typedef struct */ #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +/** + * @brief Checks the source of specified interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) + /** * @brief Clears the SDMMC's interrupt pending bits. * @param __INSTANCE__ Pointer to SDMMC register base @@ -1009,7 +1170,7 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); /** @addtogroup HAL_SDMMC_LL_Group2 * @{ */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_ReadFIFO(const SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); /** * @} @@ -1022,17 +1183,17 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); +uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); +uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); @@ -1073,6 +1234,10 @@ uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); /** * @} */ @@ -1084,6 +1249,8 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** @@ -1106,7 +1273,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** * @} */ - +#endif /* SDMMC1 || SDMMC2 */ /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h index c2b31d60..06568c7b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_swpmi.h @@ -63,24 +63,30 @@ typedef struct uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetVoltageClass. */ uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. - This parameter must be a number between Min_Data=0 and Max_Data=255U. + This parameter must be a number between Min_Data=0 + and Max_Data=255U. - The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER + The value can be calculated thanks to helper + macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ + This feature can be modified afterwards using unitary + function @ref LL_SWPMI_SetBitRatePrescaler. */ uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetTransmissionMode. */ uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX - This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ + This feature can be modified afterwards using + unitary function @ref LL_SWPMI_SetReceptionMode. */ } LL_SWPMI_InitTypeDef; /** @@ -266,7 +272,7 @@ __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t R * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); } @@ -294,7 +300,7 @@ __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_ * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI */ -__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); } @@ -351,7 +357,7 @@ __STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL); } @@ -381,7 +387,7 @@ __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL); } @@ -428,7 +434,7 @@ __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_ * @param SWPMIx SWPMI Instance * @retval A number between Min_Data=0 and Max_Data=255U */ -__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); } @@ -455,7 +461,7 @@ __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t Vo * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B */ -__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); } @@ -474,7 +480,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL); } @@ -485,7 +491,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL); } @@ -496,7 +502,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL); } @@ -507,7 +513,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL); } @@ -518,7 +524,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL); } @@ -530,7 +536,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL); } @@ -542,7 +548,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL); } @@ -554,7 +560,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL); } @@ -566,7 +572,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL); } @@ -577,7 +583,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL); } @@ -588,7 +594,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL); } @@ -599,7 +605,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL); } @@ -926,7 +932,7 @@ __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL); } @@ -937,7 +943,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL); } @@ -948,7 +954,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL); } @@ -959,7 +965,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL); } @@ -970,7 +976,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL); } @@ -981,7 +987,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL); } @@ -992,7 +998,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL); } @@ -1003,7 +1009,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL); } @@ -1014,7 +1020,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL); } @@ -1025,7 +1031,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL); } @@ -1066,7 +1072,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL); } @@ -1099,7 +1105,7 @@ __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @param SWPMIx SWPMI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(const SWPMI_TypeDef *SWPMIx) { return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL); } @@ -1114,19 +1120,19 @@ __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) +__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(const SWPMI_TypeDef *SWPMIx, uint32_t Direction) { uint32_t data_reg_addr; if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->TDR); + data_reg_addr = (uint32_t) &(SWPMIx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t)&(SWPMIx->RDR); + data_reg_addr = (uint32_t) &(SWPMIx->RDR); } return data_reg_addr; @@ -1146,7 +1152,7 @@ __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t * @param SWPMIx SWPMI Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1F */ -__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) +__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(const SWPMI_TypeDef *SWPMIx) { return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); } @@ -1210,8 +1216,8 @@ __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) * @{ */ -ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); -ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); +ErrorStatus LL_SWPMI_DeInit(const SWPMI_TypeDef *SWPMIx); +ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, const LL_SWPMI_InitTypeDef *SWPMI_InitStruct); void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h index eef033dd..a8625e96 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/drivers/include/stm32h7xx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h723xx.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h723xx.h index 4c8a9d0d..b139a388 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h723xx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h723xx.h @@ -11785,101 +11785,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -21641,7 +21738,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h725xx.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h725xx.h index 56eb3938..02749c7a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h725xx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h725xx.h @@ -11786,101 +11786,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -21653,7 +21750,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xx.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xx.h index 2b2cea29..6bab03e3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xx.h @@ -12039,101 +12039,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -22128,7 +22225,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xxq.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xxq.h index 01c6a27f..4601a20b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xxq.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h730xxq.h @@ -12040,101 +12040,198 @@ typedef struct /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ -#define GPIO_MODER_MODE0_Pos (0U) -#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ -#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk -#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ -#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ - -#define GPIO_MODER_MODE1_Pos (2U) -#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ -#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk -#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ -#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ - -#define GPIO_MODER_MODE2_Pos (4U) -#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ -#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk -#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ -#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ - -#define GPIO_MODER_MODE3_Pos (6U) -#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ -#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk -#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ -#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ - -#define GPIO_MODER_MODE4_Pos (8U) -#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ -#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk -#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ -#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ - -#define GPIO_MODER_MODE5_Pos (10U) -#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ -#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk -#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ -#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ - -#define GPIO_MODER_MODE6_Pos (12U) -#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ -#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk -#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ -#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ - -#define GPIO_MODER_MODE7_Pos (14U) -#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ -#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk -#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ -#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ - -#define GPIO_MODER_MODE8_Pos (16U) -#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ -#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk -#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ -#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ - -#define GPIO_MODER_MODE9_Pos (18U) -#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ -#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk -#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ -#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ - -#define GPIO_MODER_MODE10_Pos (20U) -#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ -#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk -#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ -#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ - -#define GPIO_MODER_MODE11_Pos (22U) -#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ -#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk -#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ -#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ - -#define GPIO_MODER_MODE12_Pos (24U) -#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ -#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk -#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ -#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ - -#define GPIO_MODER_MODE13_Pos (26U) -#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ -#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk -#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ -#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ - -#define GPIO_MODER_MODE14_Pos (28U) -#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ -#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk -#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ -#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ - -#define GPIO_MODER_MODE15_Pos (30U) -#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ -#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk -#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ -#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ +#define GPIO_MODER_MODER0_Pos (0U) +#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ + +#define GPIO_MODER_MODER1_Pos (2U) +#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ + +#define GPIO_MODER_MODER2_Pos (4U) +#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ + +#define GPIO_MODER_MODER3_Pos (6U) +#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ + +#define GPIO_MODER_MODER4_Pos (8U) +#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ + +#define GPIO_MODER_MODER5_Pos (10U) +#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ + +#define GPIO_MODER_MODER6_Pos (12U) +#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ + +#define GPIO_MODER_MODER7_Pos (14U) +#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ + +#define GPIO_MODER_MODER8_Pos (16U) +#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ + +#define GPIO_MODER_MODER9_Pos (18U) +#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ + +#define GPIO_MODER_MODER10_Pos (20U) +#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk +#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ + +#define GPIO_MODER_MODER11_Pos (22U) +#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk +#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ + +#define GPIO_MODER_MODER12_Pos (24U) +#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk +#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ + +#define GPIO_MODER_MODER13_Pos (26U) +#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk +#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ + +#define GPIO_MODER_MODER14_Pos (28U) +#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk +#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ + +#define GPIO_MODER_MODER15_Pos (30U) +#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk +#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ + +/* Legacy Defines */ +#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos +#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk +#define GPIO_MODER_MODE0 GPIO_MODER_MODER0 +#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0 +#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1 + +#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos +#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk +#define GPIO_MODER_MODE1 GPIO_MODER_MODER1 +#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0 +#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1 + +#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos +#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk +#define GPIO_MODER_MODE2 GPIO_MODER_MODER2 +#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0 +#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1 + +#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos +#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk +#define GPIO_MODER_MODE3 GPIO_MODER_MODER3 +#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0 +#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1 + +#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos +#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk +#define GPIO_MODER_MODE4 GPIO_MODER_MODER4 +#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0 +#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1 + +#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos +#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk +#define GPIO_MODER_MODE5 GPIO_MODER_MODER5 +#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0 +#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1 + +#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos +#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk +#define GPIO_MODER_MODE6 GPIO_MODER_MODER6 +#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0 +#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1 + +#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos +#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk +#define GPIO_MODER_MODE7 GPIO_MODER_MODER7 +#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0 +#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1 + +#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos +#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk +#define GPIO_MODER_MODE8 GPIO_MODER_MODER8 +#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0 +#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1 + +#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos +#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk +#define GPIO_MODER_MODE9 GPIO_MODER_MODER9 +#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0 +#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1 + +#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po +#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms +#define GPIO_MODER_MODE10 GPIO_MODER_MODER10 +#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0 +#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1 + +#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po +#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms +#define GPIO_MODER_MODE11 GPIO_MODER_MODER11 +#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0 +#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1 + +#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po +#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms +#define GPIO_MODER_MODE12 GPIO_MODER_MODER12 +#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0 +#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1 + +#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po +#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms +#define GPIO_MODER_MODE13 GPIO_MODER_MODER13 +#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0 +#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1 + +#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po +#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms +#define GPIO_MODER_MODE14 GPIO_MODER_MODER14 +#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0 +#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1 + +#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po +#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms +#define GPIO_MODER_MODE15 GPIO_MODER_MODER15 +#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0 +#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1 /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) @@ -22140,7 +22237,7 @@ typedef struct #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos (24U) #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM23 DBGMCU_APB1HFZ1_DBG_TIM23_Msk -#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (24U) +#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos (25U) #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1HFZ1_DBG_TIM24 DBGMCU_APB1HFZ1_DBG_TIM24_Msk /******************** Bit definition for APB2FZ1 register ************/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h733xx.h b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h733xx.h index 21823273..8d9f1048 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h733xx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/modules/hal/stm32/stm32cube/stm32h7xx/soc/stm32h733xx.h @@ -11981,7 +11981,7 @@ typedef struct #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*! #include /* Common values */ -#define PICOS_IN_SEC 1000000000000 -#define BITS_PER_BYTE 8 +#define PICOS_IN_SEC 1000000000000 /* MMCM specific numbers */ #define CLKOUT_MAX 7 @@ -73,7 +73,7 @@ lcko->margin.exp = CLKOUT_MARGIN_EXP(N); /* Devicetree clkout defines */ -#define CLKOUT_EXIST(N) DT_NODE_HAS_STATUS(DT_NODELABEL(clk##N), okay) +#define CLKOUT_EXIST(N) DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(clk##N)) #define CLKOUT_ID(N) DT_REG_ADDR(DT_NODELABEL(clk##N)) #define CLKOUT_FREQ(N) DT_PROP(DT_NODELABEL(clk##N), \ litex_clock_frequency) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_control_nrf2_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_control_nrf2_common.h new file mode 100644 index 00000000..858698c3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_control_nrf2_common.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF2_COMMON_H_ +#define ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF2_COMMON_H_ + +#include +#include +#include +#include +#include + +#define FLAGS_COMMON_BITS 10 + +struct clock_onoff { + struct onoff_manager mgr; + onoff_notify_fn notify; + uint8_t idx; +}; + +/** + * @brief Defines a type for specific clock configuration structure. + * + * @param type suffix added clock_config_ to form the type name. + * @param _onoff_cnt number of clock configuration options to be handled; + * for each one a separate onoff manager instance is used. + */ +#define STRUCT_CLOCK_CONFIG(type, _onoff_cnt) \ + struct clock_config_##type { \ + atomic_t flags; \ + uint32_t flags_snapshot; \ + struct k_work work; \ + uint8_t onoff_cnt; \ + struct clock_onoff onoff[_onoff_cnt]; \ + } + +/** + * @brief Initializes a clock configuration structure. + * + * @param clk_cfg pointer to the structure to be initialized. + * @param onoff_cnt number of clock configuration options handled + * handled by the structure. + * @param update_work_handler function that performs configuration update, + * called from the system work queue. + * + * @return 0 on success, negative value when onoff initialization fails. + */ +int clock_config_init(void *clk_cfg, uint8_t onoff_cnt, k_work_handler_t update_work_handler); + +/** + * @brief Starts a clock configuration update. + * + * This function is supposed to be called by a specific clock control driver + * from its update work handler. + * + * @param work pointer to the work item received by the update work handler. + * + * @return index of the clock configuration onoff option to be activated. + */ +uint8_t clock_config_update_begin(struct k_work *work); + +/** + * @brief Finalizes a clock configuration update. + * + * Notifies all relevant onoff managers about the update result. + * Only the first call after each clock_config_update_begin() performs + * the actual operation. Any further calls are simply no-ops. + * + * @param clk_cfg pointer to the clock configuration structure. + * @param status result to be passed to onoff managers. + */ +void clock_config_update_end(void *clk_cfg, int status); + +int api_nosys_on_off(const struct device *dev, clock_control_subsys_t sys); + +#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_NRF2_COMMON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_stm32_ll_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_stm32_ll_common.h index a97d0133..1988bb06 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_stm32_ll_common.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/clock_control/clock_stm32_ll_common.h @@ -27,9 +27,18 @@ #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v #define pllr(v) z_pllr(v) +#if defined(RCC_PLLI2SCFGR_PLLI2SM) +/* Some stm32F4 devices have a dedicated PLL I2S with M divider */ #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v +#else +/* Some stm32F4 devices (typ. stm32F401) have a dedicated PLL I2S with PLL M divider */ +#define z_plli2s_m(v) LL_RCC_PLLM_DIV_ ## v +#endif /* RCC_PLLI2SCFGR_PLLI2SM */ #define plli2sm(v) z_plli2s_m(v) +#define z_plli2s_q(v) LL_RCC_PLLI2SQ_DIV_ ## v +#define plli2sq(v) z_plli2s_q(v) + #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v #define plli2sr(v) z_plli2s_r(v) @@ -50,6 +59,11 @@ void config_plli2s(void); #endif void config_enable_default_clocks(void); void config_regulator_voltage(uint32_t hclk_freq); +int enabled_clock(uint32_t src_clk); + +#if defined(STM32_CK48_ENABLED) +uint32_t get_ck48_frequency(void); +#endif /* functions exported to the soc power.c */ int stm32_clock_control_init(const struct device *dev); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/crypto/crypto_stm32_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/crypto/crypto_stm32_priv.h index 374cc33b..e74b33be 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/crypto/crypto_stm32_priv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/crypto/crypto_stm32_priv.h @@ -8,10 +8,17 @@ #ifndef ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_PRIV_H_ #define ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_PRIV_H_ +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32l4_aes) +#define crypt_config_t CRYP_InitTypeDef +#else +#define crypt_config_t CRYP_ConfigTypeDef +#endif + /* Maximum supported key length is 256 bits */ #define CRYPTO_STM32_AES_MAX_KEY_LEN (256 / 8) struct crypto_stm32_config { + const struct reset_dt_spec reset; struct stm32_pclken pclken; }; @@ -22,7 +29,7 @@ struct crypto_stm32_data { }; struct crypto_stm32_session { - CRYP_ConfigTypeDef config; + crypt_config_t config; uint32_t key[CRYPTO_STM32_AES_MAX_KEY_LEN / sizeof(uint32_t)]; bool in_use; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/dmic/dmic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/dmic/dmic.h index d690c0cd..9b7d8c03 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/dmic/dmic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/dmic/dmic.h @@ -173,7 +173,7 @@ struct dai_intel_dmic { /* hardware parameters */ uint32_t reg_base; uint32_t shim_base; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) uint32_t hdamldmic_base; uint32_t vshim_base; #endif @@ -185,12 +185,13 @@ struct dai_intel_dmic { static inline int32_t sat_int32(int64_t x) { - if (x > INT32_MAX) + if (x > INT32_MAX) { return INT32_MAX; - else if (x < INT32_MIN) + } else if (x < INT32_MIN) { return INT32_MIN; - else + } else { return (int32_t)x; + } } /* Fractional multiplication with shift and saturation */ static inline int32_t q_multsr_sat_32x32(int32_t x, int32_t y, @@ -205,11 +206,13 @@ static inline int dmic_get_unmute_ramp_from_samplerate(int rate) time_ms = Q_MULTSR_32X32((int32_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) + LOGRAMP_TIME_OFFS_Q0; - if (time_ms > LOGRAMP_TIME_MAX_MS) + if (time_ms > LOGRAMP_TIME_MAX_MS) { return LOGRAMP_TIME_MAX_MS; + } - if (time_ms < LOGRAMP_TIME_MIN_MS) + if (time_ms < LOGRAMP_TIME_MIN_MS) { return LOGRAMP_TIME_MIN_MS; + } return time_ms; } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/dai-params-intel-ipc4.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/dai-params-intel-ipc4.h index a92f06d6..46acee04 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/dai-params-intel-ipc4.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/dai-params-intel-ipc4.h @@ -231,18 +231,27 @@ struct dai_intel_ipc4_ssp_config { uint32_t ssc1; uint32_t sscto; uint32_t sspsp; -#ifndef CONFIG_SOC_INTEL_ACE30_PTL uint32_t sstsa; uint32_t ssrsa; -#endif uint32_t ssc2; uint32_t sspsp2; uint32_t ssc3; uint32_t ssioc; -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +} __packed; + +struct dai_intel_ipc4_ssp_config_ver_3_0 { + uint32_t ssc0; + uint32_t ssc1; + uint32_t sscto; + uint32_t sspsp; + uint32_t ssc2; + uint32_t sspsp2; + uint32_t ssc3; + uint32_t ssioc; + /* Specifies which time slots the DMA FIFO will receive from the SSP Interface*/ uint64_t ssmidytsa[I2SIPCMC]; + /* Specifies which time slots the DMA FIFO will transmit to the SSP Interface */ uint64_t ssmodytsa[I2SOPCMC]; -#endif } __packed; struct dai_intel_ipc4_ssp_mclk_config { @@ -260,7 +269,11 @@ struct dai_intel_ipc4_ssp_mclk_config_2 { } __packed; struct dai_intel_ipc4_ssp_driver_config { +#ifdef CONFIG_SOC_INTEL_ACE30 + struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_config; +#else struct dai_intel_ipc4_ssp_config i2s_config; +#endif struct dai_intel_ipc4_ssp_mclk_config mclk_config; } __packed; @@ -320,7 +333,7 @@ struct dai_intel_ipc4_ssp_configuration_blob { struct dai_intel_ipc4_ssp_driver_config i2s_driver_config; /* optional configuration parameters */ - union dai_intel_ipc4_ssp_dma_control i2s_dma_control[0]; + FLEXIBLE_ARRAY_DECLARE(union dai_intel_ipc4_ssp_dma_control, i2s_dma_control); } __packed; #define SSP_BLOB_VER_1_5 0xee000105 @@ -340,4 +353,21 @@ struct dai_intel_ipc4_ssp_configuration_blob_ver_1_5 { struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control; } __packed; +#define SSP_BLOB_VER_3_0 0xee000300 + +struct dai_intel_ipc4_ssp_configuration_blob_ver_3_0 { + union dai_intel_ipc4_gateway_attributes gw_attr; + + uint32_t version; + uint32_t size; + + /* TDM time slot mappings */ + uint32_t tdm_ts_group[DAI_INTEL_I2S_TDM_MAX_SLOT_MAP_COUNT]; + + /* i2s port configuration */ + struct dai_intel_ipc4_ssp_config_ver_3_0 i2s_ssp_config; + /* clock configuration parameters */ + struct dai_intel_ipc4_ssp_mclk_config_2 i2s_mclk_control; +} __packed; + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp.h index 560b5d3d..d85a95aa 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp.h @@ -7,6 +7,24 @@ #ifndef __INTEL_DAI_DRIVER_SSP_H__ #define __INTEL_DAI_DRIVER_SSP_H__ +#define SSP_IP_VER_1_0 0x10000 /* cAVS */ +#define SSP_IP_VER_1_5 0x10500 /* ACE15 */ +#define SSP_IP_VER_2_0 0x20000 /* ACE20 */ +#define SSP_IP_VER_3_0 0x30000 /* ACE30 */ + +/* SSP IP version defined by CONFIG_SOC*/ +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS) +#define SSP_IP_VER SSP_IP_VER_1_0 +#elif defined(CONFIG_SOC_INTEL_ACE15_MTPM) +#define SSP_IP_VER SSP_IP_VER_1_5 +#elif defined(CONFIG_SOC_INTEL_ACE20_LNL) +#define SSP_IP_VER SSP_IP_VER_2_0 +#elif defined(CONFIG_SOC_INTEL_ACE30) +#define SSP_IP_VER SSP_IP_VER_3_0 +#else +#error "Unknown SSP IP" +#endif + #include #include #include "dai-params-intel-ipc3.h" @@ -52,13 +70,13 @@ #include "ssp_regs_v1.h" #elif defined(CONFIG_SOC_INTEL_ACE20_LNL) #include "ssp_regs_v2.h" -#elif defined(CONFIG_SOC_INTEL_ACE30_PTL) +#elif defined(CONFIG_SOC_INTEL_ACE30) #include "ssp_regs_v3.h" #else #error "Missing ssp definitions" #endif -#if CONFIG_INTEL_MN +#if SSP_IP_VER == SSP_IP_VER_1_0 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly. * Even in the case of M/N, the actual clock source can be XTAL, * Audio cardinal clock (24.576) or 96 MHz PLL. @@ -86,7 +104,7 @@ struct dai_intel_ssp_mn { int mclk_rate[DAI_INTEL_SSP_NUM_MCLK]; int mclk_source_clock; -#if CONFIG_INTEL_MN +#if SSP_IP_VER == SSP_IP_VER_1_0 enum bclk_source bclk_sources[(CONFIG_DAI_INTEL_SSP_NUM_BASE + CONFIG_DAI_INTEL_SSP_NUM_EXT)]; int bclk_source_mn_clock; @@ -116,7 +134,7 @@ struct dai_intel_ssp_plat_data { uint32_t base; uint32_t ip_base; uint32_t shim_base; -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if SSP_IP_VER > SSP_IP_VER_1_5 uint32_t hdamlssp_base; uint32_t i2svss_base; #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v1.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v1.h index a821ab87..ba76de12 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v1.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v1.h @@ -215,7 +215,7 @@ #define I2SLCTL_SPA(x) BIT(0 + x) #define I2SLCTL_CPA(x) BIT(8 + x) -#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) +#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x) #define SHIM_CLKCTL 0x78 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v2.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v2.h index e2d1c826..72ff40b7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v2.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v2.h @@ -218,7 +218,7 @@ #define PCMS0CM_OFFSET 0x16 #define PCMS1CM_OFFSET 0x1A -#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) +#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x) #define SHIM_CLKCTL 0x78 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v3.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v3.h index 5990404c..e11f5543 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v3.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/intel/ssp/ssp_regs_v3.h @@ -215,7 +215,7 @@ #define I2SLCTL_SPA(x) BIT(16 + x) #define I2SLCTL_CPA(x) BIT(23 + x) -#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) +#define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(29, 27, x) #define SHIM_CLKCTL 0x78 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/nxp/sai/sai.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/nxp/sai/sai.h index 2fa890e9..07042744 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/nxp/sai/sai.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dai/nxp/sai/sai.h @@ -38,7 +38,7 @@ LOG_MODULE_REGISTER(nxp_dai_sai); /* used to retrieve a clock's ID using its index generated via _SAI_CLOCK_INDEX_ARRAY */ #define _SAI_GET_CLOCK_ID(clock_idx, inst)\ - DT_INST_CLOCKS_CELL_BY_IDX(inst, clock_idx, name) + DT_INST_PHA_BY_IDX_OR(inst, clocks, clock_idx, name, 0x0) /* used to retrieve a clock's name using its index generated via _SAI_CLOCK_INDEX_ARRAY */ #define _SAI_GET_CLOCK_NAME(clock_idx, inst)\ @@ -210,6 +210,11 @@ LOG_MODULE_REGISTER(nxp_dai_sai); ((dir) == DAI_DIR_RX ? ((UINT_TO_I2S(regmap))->RCSR & (which)) : \ ((UINT_TO_I2S(regmap))->TCSR & (which))) +/* used to clear status flags */ +#define SAI_TX_RX_STATUS_CLEAR(dir, regmap, which) \ + ((dir) == DAI_DIR_RX ? SAI_RxClearStatusFlags(UINT_TO_I2S(regmap), which) \ + : SAI_TxClearStatusFlags(UINT_TO_I2S(regmap), which)) + /* used to retrieve the SYNC direction. Use this macro when you know for sure * you have 1 SYNC direction with 1 ASYNC direction. */ @@ -254,6 +259,7 @@ struct sai_data { struct sai_config { uint32_t regmap_phys; uint32_t regmap_size; + uint32_t irq; struct sai_clock_data clk_data; bool mclk_is_output; /* if the tx/rx-fifo-watermark properties are not specified, it's going diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9340.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9340.h index 50836b03..aaa0d2bf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9340.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9340.h @@ -50,7 +50,7 @@ struct ili9340_regs { /* Initializer macro for ILI9340 registers. */ #define ILI9340_REGS_INIT(n) \ - static const struct ili9340_regs ili9xxx_regs_##n = { \ + static const struct ili9340_regs ili9340_regs_##n = { \ .gamset = DT_PROP(DT_INST(n, ilitek_ili9340), gamset), \ .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9340), frmctr1), \ .disctrl = DT_PROP(DT_INST(n, ilitek_ili9340), disctrl), \ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9341.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9341.h index 5ffd60fc..b46f6ba9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9341.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9341.h @@ -121,7 +121,7 @@ struct ili9341_regs { "ili9341: Error length frame rate control (IFCTL) register"); \ BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), etmod) == ILI9341_ETMOD_LEN, \ "ili9341: Error length entry Mode Set (ETMOD) register"); \ - static const struct ili9341_regs ili9xxx_regs_##n = { \ + static const struct ili9341_regs ili9341_regs_##n = { \ .gamset = DT_PROP(DT_INST(n, ilitek_ili9341), gamset), \ .ifmode = DT_PROP(DT_INST(n, ilitek_ili9341), ifmode), \ .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9341), frmctr1), \ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9342c.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9342c.h index c5cc8fb5..d028248c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9342c.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9342c.h @@ -67,7 +67,7 @@ struct ili9342c_regs { /* Initializer macro for ILI9342C registers. */ #define ILI9342c_REGS_INIT(n) \ - static const struct ili9342c_regs ili9xxx_regs_##n = { \ + static const struct ili9342c_regs ili9342c_regs_##n = { \ .gamset = DT_PROP(DT_INST(n, ilitek_ili9342c), gamset), \ .ifmode = DT_PROP(DT_INST(n, ilitek_ili9342c), ifmode), \ .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9342c), frmctr1), \ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9488.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9488.h index 8cb9f37b..93d8be2d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9488.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ili9488.h @@ -44,7 +44,7 @@ struct ili9488_regs { /* Initializer macro for ILI9488 registers. */ #define ILI9488_REGS_INIT(n) \ - static const struct ili9488_regs ili9xxx_regs_##n = { \ + static const struct ili9488_regs ili9488_regs_##n = { \ .frmctr1 = DT_PROP(DT_INST(n, ilitek_ili9488), frmctr1), \ .disctrl = DT_PROP(DT_INST(n, ilitek_ili9488), disctrl), \ .pwctrl1 = DT_PROP(DT_INST(n, ilitek_ili9488), pwctrl1), \ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ist3931.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ist3931.h new file mode 100644 index 00000000..0b901aea --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_ist3931.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Shen Xuyang + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef IST3931_DISPLAY_DRIVER_H__ +#define IST3931_DISPLAY_DRIVER_H__ + +#define IST3931_CMD_NOP 0xe3 +#define IST3931_CMD_IST_COMMAND_ENTRY 0x88 +#define IST3931_CMD_EXIT_ENTRY 0xe3 +#define IST3931_CMD_IST_COM_MAPPING 0x60 +#define IST3931_CMD_POWER_CONTROL 0x2c +#define IST3931_CMD_BIAS 0x30 +#define IST3931_CMD_CT 0xb1 +#define IST3931_CMD_FRAME_CONTROL 0xb2 +#define IST3931_CMD_SET_AX_ADD 0xc0 +#define IST3931_CMD_SET_AY_ADD_LSB 0x00 +#define IST3931_CMD_SET_AY_ADD_MSB 0x10 +#define IST3931_CMD_SET_START_LINE_LSB 0x40 +#define IST3931_CMD_SET_START_LINE_MSB 0x50 +#define IST3931_CMD_OSC_CONTROL 0x2a +#define IST3931_CMD_DRIVER_DISPLAY_CONTROL 0x60 +#define IST3931_CMD_SW_RESET 0x76 +#define IST3931_CMD_SET_DUTY_LSB 0x90 +#define IST3931_CMD_SET_DUTY_MSB 0xa0 +#define IST3931_CMD_DISPLAY_ON_OFF 0x3c +#define IST3931_CMD_SLEEP_MODE 0x38 + +#define IST3931_CMD_BYTE 0x80 +#define IST3931_DATA_BYTE 0xc0 +#define IST3931_RESET_DELAY 50 +#define IST3931_CMD_DELAY 10 +#define IST3931_RAM_WIDTH 144 +#define IST3931_RAM_HEIGHT 65 +#endif /* _ZEPHYR_DRIVERS_DISPLAY_IST3931_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_sdl_bottom.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_sdl_bottom.h index 54973777..16a6a2ce 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_sdl_bottom.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_sdl_bottom.h @@ -22,19 +22,20 @@ extern "C" { int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct, bool use_accelerator, void **window, void **renderer, void **mutex, - void **texture, void **read_texture); -void sdl_display_write_bottom(const uint16_t height, const uint16_t width, - const uint16_t x, const uint16_t y, - void *renderer, void *mutex, void *texture, - uint8_t *buf, bool display_on); -int sdl_display_read_bottom(const uint16_t height, const uint16_t width, - const uint16_t x, const uint16_t y, - void *renderer, void *buf, uint16_t pitch, - void *mutex, void *texture, void **read_texture); -void sdl_display_blanking_off_bottom(void *renderer, void *texture); + void **texture, void **read_texture, void **background_texture, + uint32_t transparency_grid_color1, uint32_t transparency_grid_color2, + uint16_t transparency_grid_cell_size); +void sdl_display_write_bottom(const uint16_t height, const uint16_t width, const uint16_t x, + const uint16_t y, void *renderer, void *mutex, void *texture, + void *background_texture, uint8_t *buf, bool display_on, + bool frame_incomplete); +int sdl_display_read_bottom(const uint16_t height, const uint16_t width, const uint16_t x, + const uint16_t y, void *renderer, void *buf, uint16_t pitch, + void *mutex, void *texture, void *read_texture); +void sdl_display_blanking_off_bottom(void *renderer, void *texture, void *background_texture); void sdl_display_blanking_on_bottom(void *renderer); void sdl_display_cleanup_bottom(void **window, void **renderer, void **mutex, void **texture, - void **read_texture); + void **read_texture, void **background_texture); #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_st7796s.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_st7796s.h index 7b0be000..43e4e2e4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_st7796s.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/display_st7796s.h @@ -16,6 +16,7 @@ #define ST7796S_CMD_RAMWR 0x2C /* Memory write */ #define ST7796S_CMD_DISPOFF 0x28 /* Display off */ #define ST7796S_CMD_DISPON 0x29 /* Display on */ +#define ST7796S_CMD_TEON 0x35 /* Tearing effect on */ #define ST7796S_CMD_MADCTL 0x36 /* Memory data access control */ #define ST7796S_CMD_COLMOD 0x3A /* Interface pixel format */ #define ST7796S_CMD_FRMCTR1 0xB1 /* Frame rate control 1 (normal mode) */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1306_regs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1306_regs.h index 04092a88..c2982c1f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1306_regs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1306_regs.h @@ -76,7 +76,11 @@ #define SSD1306_SET_PADS_HW_CONFIG 0xda /* double byte command */ #define SSD1306_SET_PADS_HW_SEQUENTIAL 0x02 -#define SSD1306_SET_PADS_HW_ALTERNATIVE 0x12 +#define SSD1306_SET_PADS_HW_ALTERNATIVE 0x12 + +#define SSD1306_SET_IREF_MODE 0xad +#define SSD1306_SET_IREF_MODE_INTERNAL 0x30 +#define SSD1306_SET_IREF_MODE_EXTERNAL 0x00 /* diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1327_regs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1327_regs.h new file mode 100644 index 00000000..443a1375 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/display/ssd1327_regs.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2024 Savoir-faire Linux + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __SSD1327_REGS_H__ +#define __SSD1327_REGS_H__ + +/* + * Fundamental Command Table + */ +#define SSD1327_SET_COLUMN_ADDR 0x15 +#define SSD1327_SET_ROW_ADDR 0x75 + +#define SSD1327_SET_CONTRAST_CTRL 0x81 + +#define SSD1327_SET_SEGMENT_MAP_REMAPED 0xa0 +#define SSD1327_SET_DISPLAY_START_LINE 0xa1 +#define SSD1327_SET_DISPLAY_OFFSET 0xa2 + +#define SSD1327_SET_NORMAL_DISPLAY 0xa4 +#define SSD1327_SET_ENTIRE_DISPLAY_ON 0xa5 +#define SSD1327_SET_ENTIRE_DISPLAY_OFF 0xa6 +#define SSD1327_SET_REVERSE_DISPLAY 0xa7 +#define SSD1327_SET_MULTIPLEX_RATIO 0xa8 + +#define SSD1327_DISPLAY_OFF 0xae +#define SSD1327_DISPLAY_ON 0xaf + +#define SSD1327_SET_FUNCTION_A 0xab +#define SSD1327_SET_PHASE_LENGTH 0xb1 +#define SSD1327_SET_OSC_FREQ 0xb3 +#define SSD1327_SET_PRECHARGE_PERIOD 0xb6 +#define SSD1327_FUNCTION_SELECTION_B 0xd5 + +#define SSD1327_LINEAR_LUT 0xb9 + +#define SSD1327_SET_PRECHARGE_VOLTAGE 0xbc +#define SSD1327_SET_VCOMH 0xbe + + +#define SSD1327_SET_COMMAND_LOCK 0xfd + +/* Time constant in ms */ +#define SSD1327_RESET_DELAY 10 + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_nxp_edma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_nxp_edma.h index 6f4ac669..52f65a76 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_nxp_edma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_nxp_edma.h @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include "fsl_edma_soc_rev2.h" @@ -54,12 +56,18 @@ LOG_MODULE_REGISTER(nxp_edma); 0, edma_isr, \ &channels_##inst[idx], 0) +#define _EDMA_CHANNEL_PD_DEVICE_OR_NULL(idx, inst) \ + COND_CODE_1(CONFIG_PM_DEVICE_POWER_DOMAIN, \ + (DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE_BY_IDX(inst, power_domains, idx))), \ + (NULL)) + /* used to declare a struct edma_channel by the non-explicit macro suite */ #define _EDMA_CHANNEL_DECLARE(idx, inst) \ { \ .id = DT_INST_PROP_BY_IDX(inst, valid_channels, idx), \ .dev = DEVICE_DT_INST_GET(inst), \ .irq = DT_INST_IRQN_BY_IDX(inst, idx), \ + .pd_dev = _EDMA_CHANNEL_PD_DEVICE_OR_NULL(idx, inst), \ } /* used to declare a struct edma_channel by the explicit macro suite */ @@ -68,6 +76,7 @@ LOG_MODULE_REGISTER(nxp_edma); .id = idx, \ .dev = DEVICE_DT_INST_GET(inst), \ .irq = DT_INST_IRQN_BY_IDX(inst, idx), \ + .pd_dev = _EDMA_CHANNEL_PD_DEVICE_OR_NULL(idx, inst), \ } /* used to create an array of channel IDs via the valid-channels property */ @@ -88,11 +97,6 @@ LOG_MODULE_REGISTER(nxp_edma); (_EDMA_CHANNEL_ARRAY_EXPLICIT(inst)), \ (_EDMA_CHANNEL_ARRAY(inst))) -#define EDMA_HAL_CFG_GET(inst) \ - COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(inst, DT_DRV_COMPAT), hal_cfg_index), \ - (s_edmaConfigs[DT_INST_PROP(inst, hal_cfg_index)]), \ - (s_edmaConfigs[0])) - /* used to register edma_isr for all specified interrupts */ #define EDMA_CONNECT_INTERRUPTS(inst) \ FOR_EACH_FIXED_ARG(_EDMA_INT_CONNECT, (;), \ @@ -165,6 +169,10 @@ LOG_MODULE_REGISTER(nxp_edma); edma_chan_cyclic_produce(chan, size) :\ edma_chan_cyclic_consume(chan, size)) +#define EDMA_CHAN_IS_ACTIVE(data, chan)\ + (EDMA_ChannelRegRead((data)->hal_cfg, (chan)->id, EDMA_TCD_CH_CSR) &\ + EDMA_TCD_CH_CSR_ACTIVE_MASK) + enum channel_type { CHAN_TYPE_CONSUMER = 0, CHAN_TYPE_PRODUCER, @@ -176,6 +184,7 @@ enum channel_state { CHAN_STATE_STARTED, CHAN_STATE_STOPPED, CHAN_STATE_SUSPENDED, + CHAN_STATE_RELEASING, }; struct edma_channel { @@ -183,6 +192,8 @@ struct edma_channel { uint32_t id; /* pointer to device representing the EDMA instance, used by edma_isr */ const struct device *dev; + /* channel power domain device */ + const struct device *pd_dev; /* current state of the channel */ enum channel_state state; /* type of the channel (PRODUCER/CONSUMER) - only applicable to cyclic @@ -226,52 +237,49 @@ struct edma_config { bool contiguous_channels; }; -static inline int channel_change_state(struct edma_channel *chan, - enum channel_state next) +static inline bool channel_allows_transition(struct edma_channel *chan, + enum channel_state next) { enum channel_state prev = chan->state; - LOG_DBG("attempting to change state from %d to %d for channel %d", prev, next, chan->id); - /* validate transition */ switch (prev) { case CHAN_STATE_INIT: if (next != CHAN_STATE_CONFIGURED) { - return -EPERM; + return false; } break; case CHAN_STATE_CONFIGURED: if (next != CHAN_STATE_STARTED && - next != CHAN_STATE_CONFIGURED) { - return -EPERM; + next != CHAN_STATE_CONFIGURED && + next != CHAN_STATE_RELEASING) { + return false; } break; case CHAN_STATE_STARTED: if (next != CHAN_STATE_STOPPED && next != CHAN_STATE_SUSPENDED) { - return -EPERM; + return false; } break; case CHAN_STATE_STOPPED: - if (next != CHAN_STATE_CONFIGURED) { - return -EPERM; + if (next != CHAN_STATE_CONFIGURED && + next != CHAN_STATE_RELEASING) { + return false; } break; case CHAN_STATE_SUSPENDED: if (next != CHAN_STATE_STARTED && next != CHAN_STATE_STOPPED) { - return -EPERM; + return false; } break; default: LOG_ERR("invalid channel previous state: %d", prev); - return -EINVAL; + return false; } - /* transition OK, proceed */ - chan->state = next; - - return 0; + return true; } static inline int get_transfer_type(enum dma_channel_direction dir, uint32_t *type) @@ -417,6 +425,8 @@ static inline int edma_chan_cyclic_produce(struct edma_channel *chan, static inline void edma_dump_channel_registers(struct edma_data *data, uint32_t chan_id) { + uint32_t mux_reg; + LOG_DBG("dumping channel data for channel %d", chan_id); LOG_DBG("CH_CSR: 0x%x", @@ -431,8 +441,13 @@ static inline void edma_dump_channel_registers(struct edma_data *data, EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_PRI)); if (EDMA_HAS_MUX(data->hal_cfg)) { - LOG_DBG("CH_MUX: 0x%x", - EDMA_ChannelRegRead(data->hal_cfg, chan_id, EDMA_TCD_CH_MUX)); + if (data->hal_cfg->flags & EDMA_HAS_MP_MUX_FLAG) { + mux_reg = EDMA_MP_CH_MUX; + } else { + mux_reg = EDMA_TCD_CH_MUX; + } + + LOG_DBG("CH_MUX: 0x%x", EDMA_ChannelRegRead(data->hal_cfg, chan_id, mux_reg)); } LOG_DBG("TCD_SADDR: 0x%x", @@ -507,6 +522,13 @@ static inline int set_slast_dlast(struct dma_config *dma_cfg, EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA, slast); EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA, dlast); + if (data->hal_cfg->flags & EDMA_HAS_64BIT_TCD_FLAG) { + EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA_HIGH, + slast >= 0x0 ? 0x0 : 0xffffffff); + EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA_HIGH, + dlast >= 0x0 ? 0x0 : 0xffffffff); + } + return 0; } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32.h index 553e0983..54e7ac45 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32.h @@ -52,7 +52,9 @@ uint32_t dma_stm32_slot_to_channel(uint32_t id); #endif typedef void (*dma_stm32_clear_flag_func)(DMA_TypeDef *DMAx); -#if !defined(CONFIG_SOC_SERIES_STM32G0X) +#if !defined(CONFIG_SOC_SERIES_STM32G0X) && \ + !defined(CONFIG_SOC_SERIES_STM32H7X) && \ + !defined(CONFIG_SOC_SERIES_STM32U0X) typedef uint32_t (*dma_stm32_check_flag_func)(DMA_TypeDef *DMAx); #else typedef uint32_t (*dma_stm32_check_flag_func)(const DMA_TypeDef *DMAx); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32_bdma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32_bdma.h index b25ebc80..ea6ee145 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32_bdma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_stm32_bdma.h @@ -28,6 +28,7 @@ struct bdma_stm32_channel { uint32_t dst_size; void *user_data; /* holds the client data */ dma_callback_t bdma_callback; + bool cyclic; }; struct bdma_stm32_data { @@ -52,7 +53,7 @@ uint32_t bdma_stm32_slot_to_channel(uint32_t id); #endif typedef void (*bdma_stm32_clear_flag_func)(BDMA_TypeDef *DMAx); -typedef uint32_t (*bdma_stm32_check_flag_func)(BDMA_TypeDef *DMAx); +typedef uint32_t (*bdma_stm32_check_flag_func)(const BDMA_TypeDef *DMAx); bool bdma_stm32_is_gi_active(BDMA_TypeDef *DMAx, uint32_t id); void bdma_stm32_clear_gi(BDMA_TypeDef *DMAx, uint32_t id); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_xilinx_axi_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_xilinx_axi_dma.h new file mode 100644 index 00000000..05d33566 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dma/dma_xilinx_axi_dma.h @@ -0,0 +1,28 @@ +/** @file + * @brief Definitions and non-standard functions for Xilinx AXI DMA. + */ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef DMA_XILINX_AXI_DMA_H +#define DMA_XILINX_AXI_DMA_H + +#define XILINX_AXI_DMA_NUM_CHANNELS 2 +#define XILINX_AXI_DMA_TX_CHANNEL_NUM 0 +#define XILINX_AXI_DMA_RX_CHANNEL_NUM 1 + +#define XILINX_AXI_DMA_LINKED_CHANNEL_NO_CSUM_OFFLOAD 0x0 +#define XILINX_AXI_DMA_LINKED_CHANNEL_FULL_CSUM_OFFLOAD 0x1 + +#include +#include + +/** + * @brief Returns the size of the last RX transfer conducted by the DMA, based on the descriptor + * status. + */ +extern uint32_t dma_xilinx_axi_dma_last_received_frame_length(const struct device *dev); + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dp/swdp_ll_pin.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dp/swdp_ll_pin.h index 3044931a..48b4ea14 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dp/swdp_ll_pin.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/dp/swdp_ll_pin.h @@ -6,8 +6,9 @@ #include #include +#include -#if defined(CONFIG_SOC_SERIES_NRF52X) +#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X) #define CPU_CLOCK 64000000U #else #define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/eeprom/eeprom_simulator_native.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/eeprom/eeprom_simulator_native.h new file mode 100644 index 00000000..ecd3071f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/eeprom/eeprom_simulator_native.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef DRIVERS_EEPROM_EEPROM_SIMULATOR_NATIVE_H +#define DRIVERS_EEPROM_EEPROM_SIMULATOR_NATIVE_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int eeprom_mock_init_native(bool eeprom_in_ram, char **mock_eeprom, unsigned int size, + int *eeprom_fd, const char *eeprom_file_path, unsigned int erase_value, + bool eeprom_erase_at_start); + +void eeprom_mock_cleanup_native(bool eeprom_in_ram, int eeprom_fd, char *mock_eeprom, + unsigned int size, const char *eeprom_file_path, + bool eeprom_rm_at_exit); + +#ifdef __cplusplus +} +#endif + +#endif /* DRIVERS_EEPROM_EEPROM_SIMULATOR_NATIVE_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac_priv.h new file mode 100644 index 00000000..0f9a3eca --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac_priv.h @@ -0,0 +1,690 @@ +/* + * Intel Hard Processor System 10 Giga bit TSN Ethernet Media Access controller (XGMAC) driver + * + * Driver private data declarations + * + * Copyright (c) 2024 Intel Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DRIVERS_ETHERNET_ETH_DWC_XGMAC_PRIV_H_ +#define _ZEPHYR_DRIVERS_ETHERNET_ETH_DWC_XGMAC_PRIV_H_ + +#include +#include +#include +#include "../eth.h" + +#define SET_BIT 1 +#define RESET_BIT 0 + +#define READ_BIT(var, bit) ((var >> bit) & 1u) + +/* Offset addresses of the register sets in XGMAC + */ +#define XGMAC_CORE_BASE_ADDR_OFFSET (0x0000u) +#define XGMAC_MTL_BASE_ADDR_OFFSET (0x1000u) +#define XGMAC_MTL_TCQ_BASE_ADDR_OFFSET (0x1100u) +#define XGMAC_DMA_BASE_ADDR_OFFSET (0x3000u) +#define XGMAC_DMA_CHNL_BASE_ADDR_OFFSET (0x3100u) +#define XGMAC_DMA_CHNLx_BASE_ADDR_OFFSET(x) (XGMAC_DMA_CHNL_BASE_ADDR_OFFSET + (x * 0x80u)) +#define XGMAC_MTL_TCQx_BASE_ADDR_OFFSET(x) (XGMAC_MTL_TCQ_BASE_ADDR_OFFSET + (x * 0x80u)) +#define XGMAC_CORE_ADDRx_HIGH(x) (CORE_MAC_ADDRESS0_HIGH_OFST + (x) * 0x8) +#define XGMAC_CORE_ADDRx_LOW(x) (CORE_MAC_ADDRESS0_LOW_OFST + (x) * 0x8) + +#define XGMAC_DESC_OWNED_BY_DMA (1u) + +#define NUM_OF_RxQs_PER_DMA_MAP_REG (4u) +#define MTL_RXQ_DMA_MAP_Qx_MSK(q_pos) (~(0xffu << (q_pos * 8u))) +#define MTL_RXQ_DMA_MAP_QxDDMACH_SET(q_pos, value) ((value & 0x1u) << (8u * q_pos + 7u)) +#define MTL_RXQ_DMA_MAP_QxMDMACH_SET(q_pos, value) ((value & 0x7u) << (8u * q_pos)) + +#define NUM_OF_TCs_PER_TC_PRTY_MAP_REG (4u) +#define TC_PRTY_MAP_FEILD_SIZE_IN_BITS (8u) +#define MTL_TCx_PRTY_MAP_MSK(TCx_pos) (~(0xff << (TCx_pos * TC_PRTY_MAP_FEILD_SIZE_IN_BITS))) + +#define MTL_TCx_PRTY_MAP_PSTC_SET(TCx_pos, prio) ((prio & 0xff) << (8u * TCx_pos)) + +#define DMA_MODE_OFST (0x0) + +#define DMA_MODE_SWR_SET(value) ((value) & 0x00000001) + +#define DMA_MODE_SWR_SET_MSK (0x00000001) + +#define DMA_MODE_INTM_CLR_MSK (0xffffcfff) + +#define DMA_MODE_INTM_SET(value) (((value) << 12) & 0x00003000) + +#define DMA_SYSBUS_MODE_OFST (0x4) + +#define DMA_SYSBUS_MODE_RD_OSR_LMT_SET(value) (((value) << 16) & 0x001f0000) + +#define DMA_SYSBUS_MODE_WR_OSR_LMT_SET(value) (((value) << 24) & 0x1f000000) + +#define DMA_SYSBUS_MODE_AAL_SET(value) (((value) << 12) & 0x00001000) + +#define DMA_SYSBUS_MODE_EAME_SET(value) (((value) << 11) & 0x00000800) + +#define DMA_SYSBUS_MODE_BLEN4_SET(value) (((value) << 1) & 0x00000002) + +#define DMA_SYSBUS_MODE_BLEN8_SET(value) (((value) << 2) & 0x00000004) + +#define DMA_SYSBUS_MODE_BLEN16_SET(value) (((value) << 3) & 0x00000008) + +#define DMA_SYSBUS_MODE_BLEN32_SET(value) (((value) << 4) & 0x00000010) + +#define DMA_SYSBUS_MODE_BLEN64_SET(value) (((value) << 5) & 0x00000020) + +#define DMA_SYSBUS_MODE_BLEN128_SET(value) (((value) << 6) & 0x00000040) + +#define DMA_SYSBUS_MODE_BLEN256_SET(value) (((value) << 7) & 0x00000080) + +#define DMA_SYSBUS_MODE_UNDEF_SET(value) ((value) & 0x00000001) + +#define DMA_TX_EDMA_CONTROL_OFST (0x40) + +#define DMA_TX_EDMA_CONTROL_TDPS_SET(value) ((value) & 0x00000003) + +#define DMA_RX_EDMA_CONTROL_OFST (0x44) + +#define DMA_RX_EDMA_CONTROL_RDPS_SET(value) ((value) & 0x00000003) + +#define DMA_INTERRUPT_STATUS_OFST (0x8) + +#define DMA_CHx_STATUS_OFST (0x60) + +#define DMA_CHx_STATUS_TI_SET_MSK (0x00000001) + +#define DMA_CHx_STATUS_RI_SET_MSK (0x00000040) + +#define DMA_CHx_STATUS_TPS_SET_MSK (0x00000002) + +#define DMA_CHx_STATUS_TBU_SET_MSK (0x00000004) + +#define DMA_CHx_STATUS_RBU_SET_MSK (0x00000080) + +#define DMA_CHx_STATUS_RPS_SET_MSK (0x00000100) + +#define DMA_CHx_STATUS_DDE_SET_MSK (0x00000200) + +#define DMA_CHx_STATUS_FBE_SET_MSK (0x00001000) + +#define DMA_CHx_STATUS_CDE_SET_MSK (0x00002000) + +#define DMA_CHx_STATUS_AIS_SET_MSK (0x00004000) + +#define DMA_CHx_STATUS_NIS_SET_MSK (0x00008000) + +#define DMA_CHx_CONTROL_OFST (0x0) + +#define DMA_CHx_CONTROL_SPH_SET(value) (((value) << 24) & 0x01000000) + +#define DMA_CHx_CONTROL_PBLX8_SET(value) (((value) << 16) & 0x00010000) + +#define DMA_CHx_CONTROL_MSS_SET(value) ((value) & 0x00003fff) + +#define DMA_CHx_TX_CONTROL_OFST (0x4) + +#define DMA_CHx_TX_CONTROL_TXPBL_SET(value) (((value) << 16) & 0x003f0000) + +#define DMA_CHx_TX_CONTROL_TSE_SET(value) (((value) << 12) & 0x00001000) + +#define DMA_CHx_TX_CONTROL_RESERVED_OSP_SET(value) (((value) << 4) & 0x00000010) + +#define DMA_CHx_TX_CONTROL_ST_CLR_MSK (0xfffffffe) + +#define DMA_CHx_RX_CONTROL_OFST (0x8) + +#define DMA_CHx_RX_CONTROL_RPF_SET(value) (((value) << 31) & 0x80000000) + +#define DMA_CHx_RX_CONTROL_RXPBL_SET(value) (((value) << 16) & 0x003f0000) + +#define DMA_CHx_RX_CONTROL_RBSZ_SET(value) ((value << 1) & 0x00007ff0) + +#define DMA_CHx_RX_CONTROL_SR_CLR_MSK (0xfffffffe) + +#define DMA_CHx_TXDESC_LIST_HADDRESS_OFST (0x10) + +#define DMA_CHx_TXDESC_LIST_HADDRESS_TDESHA_SET(value) ((value) & 0x000000ff) + +#define DMA_CHx_TXDESC_LIST_LADDRESS_OFST (0x14) + +#define DMA_CHx_RXDESC_LIST_HADDRESS_OFST (0x18) + +#define DMA_CHx_RXDESC_LIST_LADDRESS_OFST (0x1c) + +#define DMA_CHx_TXDESC_TAIL_LPOINTER_OFST (0x24) + +#define DMA_CHx_TXDESC_TAIL_LPOINTER_TDT_SET(value) ((value) & 0xfffffff8) + +#define DMA_CHx_RXDESC_TAIL_LPOINTER_OFST (0x2c) + +#define DMA_CHx_RXDESC_TAIL_LPOINTER_RDT_SET(value) ((value) & 0xfffffff8) + +#define DMA_CHx_TX_CONTROL2_OFST (0x30) + +#define DMA_CHx_TX_CONTROL2_TDRL_SET(value) (((value) << 0) & 0x0000ffff) + +#define DMA_CHx_RX_CONTROL2_OFST (0x34) + +#define DMA_CHx_RX_CONTROL2_RDRL_SET(value) (((value) << 0) & 0x0000ffff) + +#define DMA_CHx_TX_CONTROL_ST_SET_MSK (0x00000001) + +#define DMA_CHx_RX_CONTROL_SR_SET_MSK (0x00000001) + +#define DMA_CHx_INTERRUPT_ENABLE_OFST (0x38) + +#define DMA_CHx_INTERRUPT_ENABLE_NIE_SET(value) (((value) << 15) & 0x00008000) + +#define DMA_CHx_INTERRUPT_ENABLE_AIE_SET(value) (((value) << 14) & 0x00004000) + +#define DMA_CHx_INTERRUPT_ENABLE_CDEE_SET(value) (((value) << 13) & 0x00002000) + +#define DMA_CHx_INTERRUPT_ENABLE_FBEE_SET(value) (((value) << 12) & 0x00001000) + +#define DMA_CHx_INTERRUPT_ENABLE_DDEE_SET(value) (((value) << 9) & 0x00000200) + +#define DMA_CHx_INTERRUPT_ENABLE_RSE_SET(value) (((value) << 8) & 0x00000100) + +#define DMA_CHx_INTERRUPT_ENABLE_RBUE_SET(value) (((value) << 7) & 0x00000080) + +#define DMA_CHx_INTERRUPT_ENABLE_RIE_SET(value) (((value) << 6) & 0x00000040) + +#define DMA_CHx_INTERRUPT_ENABLE_TBUE_SET(value) (((value) << 2) & 0x00000004) + +#define DMA_CHx_INTERRUPT_ENABLE_TXSE_SET(value) (((value) << 1) & 0x00000002) + +#define DMA_CHx_INTERRUPT_ENABLE_TIE_SET(value) (((value) << 0) & 0x00000001) + +#define MTL_OPERATION_MODE_OFST (0x0) + +#define MTL_OPERATION_MODE_ETSALG_SET(value) (((value) << 5) & 0x00000060) + +#define MTL_OPERATION_MODE_RAA_SET(value) (((value) << 2) & 0x00000004) + +#define MTL_TC_PRTY_MAP0_OFST (0x40) + +#define MTL_RXQ_DMA_MAP0_OFST (0x30) + +#define MTL_TCQx_MTL_TXQx_OPERATION_MODE_OFST (0x0) + +#define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TQS_SET(value) (((value) << 16) & 0x007f0000) + +#define MTL_TCQx_MTL_TXQx_OPERATION_MODE_Q2TCMAP_SET(value) (((value) << 8) & 0x00000700) + +#define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TTC_SET(value) (((value) << 4) & 0x00000070) + +#define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TXQEN_SET(value) (((value) << 2) & 0x0000000c) + +#define MTL_TCQx_MTL_TXQx_OPERATION_MODE_TSF_SET(value) (((value) << 1) & 0x00000002) + +#define MTL_TCQx_MTC_TCx_ETS_CONTROL_OFST (0x10) + +#define MTL_TCQx_MTC_TCx_ETS_CONTROL_TSA_SET(value) (((value) << 0) & 0x00000003) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_OFST (0x40) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_RQS_SET(value) (((value) << 16) & 0x003f0000) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_EHFC_SET(value) (((value) << 7) & 0x00000080) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_DIS_TCP_EF_SET(value) (((value) << 6) & 0x00000040) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_RSF_SET(value) (((value) << 5) & 0x00000020) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_FEF_SET(value) (((value) << 4) & 0x00000010) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_FUF_SET(value) (((value) << 3) & 0x00000008) + +#define MTL_TCQx_MTL_RXQx_OPERATION_MODE_RTC_SET(value) (((value) << 0) & 0x00000003) + +#define MTL_INTERRUPT_STATUS_OFST (0x20) + +#define CORE_MAC_ADDRESSx_HIGH_SA_SET(value) (((value) << 30) & 0x40000000) + +#define CORE_MAC_ADDRESS1_HIGH_AE_SET_MSK (0x80000000) + +#define CORE_MAC_ADDRESS0_HIGH_OFST (0x300) + +#define CORE_MAC_ADDRESS0_LOW_OFST (0x304) + +#define CORE_MAC_TX_CONFIGURATION_OFST (0x0) + +#define CORE_MAC_TX_CONFIGURATION_SS_CLR_MSK (0x1fffffff) + +#define CORE_MAC_TX_CONFIGURATION_SS_SET(value) (((value) << 29) & 0xe0000000) + +#define CORE_MAC_TX_CONFIGURATION_JD_SET(value) (((value) << 16) & 0x00010000) + +#define CORE_MAC_RXQ_CTRL0_OFST (0xa0) + +#define CORE_MAC_RX_CONFIGURATION_OFST (0x4) + +#define CORE_MAC_RX_CONFIGURATION_GPSLCE_SET(value) (((value) << 6) & 0x00000040) + +#define CORE_MAC_RX_CONFIGURATION_WD_SET(value) (((value) << 7) & 0x00000080) + +#define CORE_MAC_RX_CONFIGURATION_JE_SET(value) (((value) << 8) & 0x00000100) + +#define CORE_MAC_RX_CONFIGURATION_ARPEN_SET(value) (((value) << 31) & 0x80000000) + +#define CORE_MAC_RX_CONFIGURATION_GPSL_SET(value) (((value) << 16) & 0x3fff0000) + +#define CORE_MAC_TX_CONFIGURATION_TE_SET(value) (((value) << 0) & 0x00000001) + +#define CORE_MAC_RX_CONFIGURATION_RE_SET(value) (((value) << 0) & 0x00000001) + +#define CORE_MAC_TX_CONFIGURATION_TE_CLR_MSK (0xfffffffe) + +#define CORE_MAC_TX_CONFIGURATION_SS_10MHZ (0x07) + +#define CORE_MAC_TX_CONFIGURATION_SS_100MHZ (0x04) + +#define CORE_MAC_TX_CONFIGURATION_SS_1000MHZ (0x03) + +#define CORE_MAC_TX_CONFIGURATION_SS_2500MHZ (0x06) + +#define CORE_MAC_RX_CONFIGURATION_RE_CLR_MSK (0xfffffffe) + +#define CORE_MAC_INTERRUPT_STATUS_OFST (0xb0) + +#define CORE_MAC_INTERRUPT_ENABLE_OFST (0xb4) + +#define CORE_MAC_INTERRUPT_ENABLE_LSIE_SET(value) (((value) << 0) & 0x00000001) + +#define CORE_MAC_PACKET_FILTER_OFST (0x8) + +#define CORE_MAC_PACKET_FILTER_IPFE_SET(value) (((value) << 20) & 0x00100000) + +#define CORE_MAC_PACKET_FILTER_HPF_SET(value) (((value) << 10) & 0x00000400) + +#define CORE_MAC_PACKET_FILTER_HMC_SET(value) (((value) << 2) & 0x00000004) + +#define CORE_MAC_PACKET_FILTER_HUC_SET(value) (((value) << 1) & 0x00000002) + +#define CORE_MAC_RX_CONFIGURATION_IPC_SET(value) (((value) << 9) & 0x00000200) + +#define CORE_MAC_ADDRESS1_HIGH_AE_CLR_MSK 0x7fffffff + +#define CORE_MAC_ADDRESS1_LOW_ADDRLO_SET_MSK 0xffffffff + +#define CORE_MAC_PACKET_FILTER_PR_CLR_MSK 0xfffffffe + +#define CORE_MAC_PACKET_FILTER_PR_SET(value) (((value) << 0) & 0x00000001) + +#define CORE_MAC_PACKET_FILTER_RA_SET(value) (((value) << 31) & 0x80000000) + +#define CORE_MAC_PACKET_FILTER_PM_SET(value) (((value) << 4) & 0x00000010) + +/* 0th index mac address is not used for L2 filtering */ +#define XGMAC_MAX_MAC_ADDR_COUNT (32u) +#define MAC_ADDR_BYTE_5 (5) +#define MAC_ADDR_BYTE_4 (4) +#define MAC_ADDR_BYTE_3 (3) +#define MAC_ADDR_BYTE_2 (2) +#define MAC_ADDR_BYTE_1 (1) +#define MAC_ADDR_BYTE_0 (0) +#define BIT_OFFSET_8 (8) +#define BIT_OFFSET_16 (16) +#define BIT_OFFSET_24 (24) + +#define XGMAC_RXQxEN_DCB (2u) /* RX queue enabled for Data Center Bridging or Generic */ +#define XGMAC_RXQxEN_SIZE_BITS (2u) +#define ETH_MAC_ADDRESS_SIZE (6u) /*Ethernet MAC address size 6 bytes */ + +#define XGMAC_TDES2_IOC BIT(31) +#define XGMAC_TDES3_OWN BIT(31) +#define XGMAC_TDES3_FD BIT(29) +#define XGMAC_TDES3_LD BIT(28) +#define XGMAC_TDES3_CS_EN_MSK (3u << 16u) + +#define XGMAC_RDES3_OWN BIT(31) +#define XGMAC_RDES3_IOC BIT(30) +#define XGMAC_RDES3_FD BIT(29) +#define XGMAC_RDES3_LD BIT(28) +#define XGMAC_RDES3_ES BIT(15) +#define XGMAC_RDES3_PL GENMASK(14, 0) + +#define RX_FRAGS_PER_DESC (2u) +#define XGMAC_POLLING_MODE (2u) +#define RX_FRAG_ONE (0u) +#define RX_FRAG_TWO (1u) + +#ifdef CONFIG_ETH_DWC_XGMAC_ARP_OFFLOAD +#define ETH_DWC_XGMAC_ARP_OFFLOAD (1u) +#else +#define ETH_DWC_XGMAC_ARP_OFFLOAD (0u) +#endif + +#define XGMAC_INTERRUPT_POLING_TIMEOUT_US (500u) + +#define ETH_DWC_XGMAC_RESET_STATUS_CHECK_RETRY_COUNT \ + (100) /* retry up to 100ms (1 x 100ms poll interval) */ +#define XGMAC_REG_SIZE_BYTES (4u) /*4 Bytes*/ +#define XGMAC_REG_SIZE_BITS (32u) /*4 Bytes*/ + +#define CHLCNT(n) DT_INST_PROP(n, num_dma_ch) +#define MAX_TX_RING(n) DT_INST_PROP(n, dma_ch_tdrl) +#define MAX_RX_RING(n) DT_INST_PROP(n, dma_ch_rdrl) + +typedef void (*eth_config_irq_t)(const struct device *port); +typedef void (*eth_enable_irq_t)(const struct device *port, bool en); + +/** + * @brief Transmit descriptor + */ +struct xgmac_dma_tx_desc { + /* First word of descriptor */ + uint32_t tdes0; + /* Second word of descriptor */ + uint32_t tdes1; + /* Third word of descriptor */ + uint32_t tdes2; + /* Fourth word of descriptor */ + uint32_t tdes3; +}; + +/** + * @brief Receive descriptor + * + */ +struct xgmac_dma_rx_desc { + /* First word of descriptor */ + uint32_t rdes0; + /* Second word of descriptor */ + uint32_t rdes1; + /* Third word of descriptor */ + uint32_t rdes2; + /* Fourth word of descriptor */ + uint32_t rdes3; +}; + +/** + * @brief TX DMA memory area buffer descriptor ring management structure. + * + * The DMA memory area buffer descriptor ring management structure + * is used to manage either the TX buffer descriptor array. + * It contains a pointer to the start of the descriptor array, a + * semaphore as a means of preventing concurrent access, a free entry + * counter as well as indices used to determine which BD shall be used + * or evaluated for the next TX operation. + */ +struct xgmac_dma_tx_desc_meta { + struct k_sem free_tx_descs_sem; + /* Concurrent modification protection */ + struct k_mutex ring_lock; + /* Index of the next BD to be used for TX */ + volatile uint16_t next_to_use; + /* Address of the first descriptor in the TX descriptor ring. This field will be + * updated in TX descriptor initialization and consumed by channel initialization. + */ + mem_addr_t desc_list_addr; + /* Address of the last descriptor in the TX descriptor ring. This field will be + * updated in TX descriptor initialization and consumed by channel initialization. + */ + volatile mem_addr_t desc_tail_addr; +}; +/** + * @brief RX DMA memory area buffer descriptor ring management structure. + * + * The DMA memory area buffer descriptor ring management structure + * is used to manage either the RX buffer descriptor array. + * It contains a pointer to the start of the descriptor array, a + * semaphore as a means of preventing concurrent access, a free entry + * counter as well as indices used to determine which BD shall be used + * or evaluated for the next RX operation. + */ +struct xgmac_dma_rx_desc_meta { + /* Index of the next BD to be read for RX */ + volatile uint16_t next_to_read; + /* Address of the first descriptor in the RX descriptor ring. this field will be + * updated in RX descriptor initialization and consumed by channel initialization + */ + mem_addr_t desc_list_addr; + /* Address of the last descriptor in the RX descriptor ring. this field will be + * updated in RX descriptor initialization and consumed by channel initialization + */ + volatile mem_addr_t desc_tail_addr; + struct net_pkt *rx_pkt; +}; + +struct xgmac_tx_cntxt { + int timeout; /*Time out in sleep intervals count*/ + /* TX packet queue ID */ + uint8_t q_id; + struct xgmac_dma_tx_desc_meta *descmeta; + struct xgmac_dma_tx_desc *tx_desc; + uint16_t pkt_desc_id; +}; + +struct xgmac_dma_cfg { + /* Software configured maximum number of AXI data writing requests */ + uint8_t wr_osr_lmt; + /* Software configured maximum number of AXI data reading requests */ + uint8_t rd_osr_lmt; + /* This field controls the threshold in the Descriptor cache after which + * the EDMA starts pre-fetching the TxDMA descriptors + */ + uint8_t edma_tdps; + /* This field controls the threshold in the Descriptor cache after which + * the EDMA starts pre-fetching the RxDMA descriptors + */ + uint8_t edma_rdps; + /* Mixed burst: AXI master can perform burst transfers that are equal to or + * less than the maximum allowed burst length programmed + */ + bool ubl; + /* burst length 4bytes */ + bool blen4; + /* burst length 8bytes */ + bool blen8; + /* burst length 16bytes */ + bool blen16; + /* burst length 32bytes */ + bool blen32; + /* burst length 64bytes */ + bool blen64; + /* burst length 128bytes */ + bool blen128; + /* burst length 256bytes */ + bool blen256; + /* Address-Aligned Beats. When this bit is set to 1, the AXI master performs + * address-aligned burst transfers on Read and Write channels + */ + bool aal; + /* Enhanced Address Mode Enable: e DMA engine uses either the 40- or 48-bit address, + * depending on the configuration. This bit is valid only when Address Width is greater than + * 32 + */ + bool eame; +}; + +struct xgmac_dma_chnl_config { + /* This field specifies the maximum segment size that should be used while + * segmenting the Transmit packet. not applicable when TSO is disabled + */ + uint16_t mss; + /* Transmit Descriptor Ring Length. This field sets the maximum number of Tx + * descriptors in the circular descriptor ring. The maximum number of descriptors + * is limited to 65536 descriptors + */ + uint16_t tdrl; + /* Receive Descriptor Ring Length. This field sets the maximum number of Rx + * descriptors in the circular descriptor ring. The maximum number of descriptors + * is limited to 65536 descriptors + */ + uint16_t rdrl; + /* Alternate Receive Buffer Size Indicates size for Buffer 1 when ARBS is + * programmed to a non-zero value (when split header feature is not enabled). + * When split header feature is enabled, ARBS indicates the buffer size for + * header data. It is recommended to use this field when split header feature is + * enabled. + */ + uint8_t arbs; + /* maximum receive burst length */ + uint8_t rxpbl; + /* maximum transmit burst length */ + uint8_t txpbl; + /* When this bit is set, the DMA splits the header and payload in + * the Receive path and stores into the buffer1 and buffer 2 respectively + */ + bool sph; + /* When this is set, the PBL value programmed in Tx_control is multiplied + * eight times + */ + bool pblx8; + /* TCP Segmentation Enabled.When this bit is set, the DMA performs the TCP + * segmentation for packets in Channel. not applicable when TSO is disabled + */ + bool tse; + /* Operate on Second Packet. When this bit is set, it instructs the DMA to process + * the second packet of the Transmit data even before closing the descriptor of the + * first packet. not applicable when edma is enabled + */ + bool osp; +}; + +struct xgmac_mtl_config { + /* Receive Arbitration Algorithm.This field is used to select the arbitration algorithm + * for the RX side. + * 0: Strict Priority (SP): Queue 0 has the lowest priority and the last queue has the + * highest priority. 1: Weighted Strict Priority (WSP) + */ + bool raa; + /* ETS Algorithm. This field selects the type of ETS algorithm to be applied for + * traffic classes whose transmission selection algorithm (TSA) is set to ETS: + * 0: WRR algorithm + * 1: WFQ algorithm + * 2: DWRR algorithm + */ + uint8_t etsalg; +}; + +struct xgmac_mac_config { + /* Giant Packet Size Limit + */ + uint32_t gpsl; + /* ARP offload is enabled/disabled. + */ + bool arp_offload_en; + /* jumbo packet is enabled/disabled. + */ + bool je; +}; + +struct xgmac_tcq_config { + /* Receive queue enabled for dynamic DMA channel selection when set, this bit indicates + * that each packet received in receive queue is routed to a DMA channel as decided in + * the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter + * registers, RSS lookup table, the ethernet DA address registers or VLAN filter registers. + * When reset, this bit indicates that all packets received in receive queue are routed to + * the DMA Channel programmed in the rx_q_dma_chnl_sel field. + */ + uint8_t rx_q_ddma_en; + /* Receive Queue Mapped to DMA Channel. This field is valid when the rx_q_ddma_en field is + * reset + */ + uint8_t rx_q_dma_chnl_sel[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* Transmit Queue Size. This field indicates the size of the allocated Transmit queues in + * blocks of 256 bytes. Range 0 - 63 + */ + uint8_t tx_q_size[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* Queue to Traffic Class Mapping + * Range TC0 - TC7 -> 0 to 7 + */ + uint8_t q_to_tc_map[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* Transmit Threshold Control. These bits control the threshold level of the MTL TX Queue. + * Transmission starts when the packet size within the MTL TX Queue is larger than the + * threshold. In addition, full packets with length less than the threshold are also + * transmitted 0: 64 2: 96 3: 128 4: 192 5: 256 6: 384 7: 512 + */ + uint8_t ttc[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* Receive Queue Size. This field indicates the size of the allocated Receive queues in + * blocks of 256 bytes Range: 0 - 127 + */ + uint8_t rx_q_size[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* Transmit Store and Forward. When this bit is set, the transmission starts when a full + * packet resides in the MTL TX Queue. When this bit is set, the values specified in the TTC + * field are ignored + */ + uint8_t tsf_en; + /* Enable Hardware Flow Control. When this bit is set, the flow control signal operation, + * based on the fill-level of RX queue, is enabled + */ + uint8_t hfc_en; + /* Disable Dropping of TCP/IP Checksum Error Packets */ + uint8_t cs_err_pkt_drop_dis; + /* Receive Queue Store and Forward. When this bit is set, DWC_xgmac reads a packet from the + * RX queue only after the complete packet has been written to it, ignoring the RTC field of + * this register + */ + uint8_t rsf_en; + /* Forward Error Packets. When this bit is set, all packets except the runt error + * packets are forwarded to the application or DMA + */ + uint8_t fep_en; + /* Forward Undersized Good Packets. When this bit is set, the RX queue forwards the + * undersized good packets + */ + uint8_t fup_en; + /* Receive Queue Threshold Control. These bits control the threshold level of the MTL Rx + * queue in bytes 0: 64 2: 96 3: 128 + */ + uint8_t rtc[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* Priorities Mapped to Traffic Class. This field determines if the transmit queues + * associated with the traffic class should be blocked from transmitting for the specified + * pause time when a PFC packet is received with priorities matching the priorities + * programmed in this field + */ + uint8_t pstc[CONFIG_ETH_XGMAC_MAX_QUEUES]; + /* + * uint8_t slc; + * uint8_t cc; + * uint8_t cbs_en; + */ + + /* Transmission Selection Algorithm. This field is used to assign a transmission selection + * algorithm for this traffic class. + * 0: Strict priority + * 1: CBS + * 2: ETS + */ + uint8_t tsa[CONFIG_ETH_XGMAC_MAX_QUEUES]; +}; + +struct xgmac_irq_cntxt_data { + const struct device *dev; + /* + * DMA interrupt status value + */ + volatile uint32_t dma_interrupt_sts; + /* + * Array pointer all dma channel interrupt status registers values + */ + volatile uint32_t *dma_chnl_interrupt_sts; + /* + * MTL interrupt status register value + */ + volatile uint32_t mtl_interrupt_sts; + /* + * MAC interrupt status register value + */ + volatile uint32_t mac_interrupt_sts; +}; + +/** + * @brief Link speed configuration enumeration type. + * + * Enumeration type for link speed indication, contains 'link down' + * plus all link speeds supported by the controller (10/100/1000). + */ +enum eth_dwc_xgmac_link_speed { + /* The values of this enum are consecutively numbered */ + LINK_DOWN = 0, + LINK_10MBIT = 10, + LINK_100MBIT = 100, + LINK_1GBIT = 1000 +}; + +#endif /* _ZEPHYR_DRIVERS_ETHERNET_ETH_DWC_XGMAC_PRIV_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_enc28j60_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_enc28j60_priv.h index 5b63ddab..2f2eb4ff 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_enc28j60_priv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_enc28j60_priv.h @@ -141,7 +141,6 @@ #define ENC28J60_BIT_MICMD_MIIRD (0x01) #define ENC28J60_BIT_MISTAT_BUSY (0x01) #define ENC28J60_BIT_ESTAT_CLKRDY (0x01) -#define ENC28J60_BIT_MACON1_MARXEN (0x01) #define ENC28J60_BIT_MACON1_RXPAUS (0x04) #define ENC28J60_BIT_MACON1_TXPAUS (0x08) #define ENC28J60_BIT_MACON1_MARXEN (0x01) @@ -151,7 +150,6 @@ #define ENC28J60_BIT_ECON1_TXRTS (0x08) #define ENC28J60_BIT_ECON1_RXEN (0x04) #define ENC28J60_BIT_ECON2_PKTDEC (0x40) -#define ENC28J60_BIT_EIR_PKTIF (0x40) #define ENC28J60_BIT_EIE_TXIE (0x08) #define ENC28J60_BIT_EIE_PKTIE (0x40) #define ENC28J60_BIT_EIE_LINKIE (0x10) @@ -166,7 +164,7 @@ #define ENC28J60_BIT_ESTAT_TXABRT (0x02) #define ENC28J60_BIT_ESTAT_LATECOL (0x10) #define ENC28J60_BIT_PHCON1_PDPXMD (0x0100) -#define ENC28J60_BIT_PHCON2_HDLDIS (0x0001) +#define ENC28J60_BIT_PHCON2_HDLDIS (0x0100) #define ENC28J60_BIT_PHSTAT2_LSTAT (0x0400) #define ENC28J60_BIT_PHIE_PGEIE (0x0002) #define ENC28J60_BIT_PHIE_PLNKIE (0x0010) @@ -227,6 +225,7 @@ struct eth_enc28j60_config { uint8_t full_duplex; int32_t timeout; uint8_t hw_rx_filter; + bool random_mac; }; struct eth_enc28j60_runtime { @@ -239,6 +238,7 @@ struct eth_enc28j60_runtime { struct k_sem tx_rx_sem; struct k_sem int_sem; bool iface_initialized : 1; + bool iface_carrier_on_init : 1; }; #endif /*_ENC28J60_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan865x_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan865x_priv.h index 8f1b7675..1ba84bd9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan865x_priv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan865x_priv.h @@ -28,6 +28,9 @@ #define LAN865x_MAC_NCR_RXEN BIT(2) #define LAN865x_MAC_NCFGR MMS_REG(0x1, 0x001) #define LAN865x_MAC_NCFGR_CAF BIT(4) +#define LAN865x_MAC_NCFGR_MTIHEN BIT(6) +#define LAN865x_MAC_HRB MMS_REG(0x1, 0x020) +#define LAN865x_MAC_HRT MMS_REG(0x1, 0x021) #define LAN865x_MAC_SAB1 MMS_REG(0x1, 0x022) #define LAN865x_MAC_SAB2 MMS_REG(0x1, 0x024) #define LAN865x_MAC_SAT2 MMS_REG(0x1, 0x025) @@ -78,4 +81,14 @@ struct lan865x_data { k_tid_t tid_int; }; +static inline void lan865x_update_dev_cfg_array(oa_mem_map_t *cfg, uint8_t size, + uint32_t addr, uint16_t val) +{ + for (uint8_t i = 0; i < size; i++) { + if (cfg[i].address == addr) { + cfg[i].value = val; + } + } +} + #endif /* ETH_LAN865X_PRIV_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan9250_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan9250_priv.h new file mode 100644 index 00000000..b6379216 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_lan9250_priv.h @@ -0,0 +1,333 @@ +/* LAN9250 Stand-alone Ethernet Controller with SPI + * + * Copyright (c) 2024 Mario Paja + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#ifndef _LAN9250_ +#define _LAN9250_ + +#define LAN9250_DEFAULT_NUMOF_RETRIES 3U +#define LAN9250_PHY_TIMEOUT 2000 +#define LAN9250_MAC_TIMEOUT 2000 +#define LAN9250_RESET_TIMEOUT 5000 + +#define LAN9250_ALIGN(v) (((v) + 3) & (~3)) + +/* SPI instructions */ +#define LAN9250_SPI_INSTR_WRITE 0x02 +#define LAN9250_SPI_INSTR_READ 0x03 + +/* TX command 'A' format */ +#define LAN9250_TX_CMD_A_INT_ON_COMP 0x80000000 +#define LAN9250_TX_CMD_A_BUFFER_ALIGN_4B 0x00000000 +#define LAN9250_TX_CMD_A_START_OFFSET_0B 0x00000000 +#define LAN9250_TX_CMD_A_FIRST_SEG 0x00002000 +#define LAN9250_TX_CMD_A_LAST_SEG 0x00001000 + +/* TX command 'B' format */ +#define LAN9250_TX_CMD_B_PACKET_TAG 0xFFFF0000 + +/* RX status format */ +#define LAN9250_RX_STS_PACKET_LEN 0x3FFF0000 + +/* LAN9250 System registers */ +#define LAN9250_RX_DATA_FIFO 0x0000 +#define LAN9250_TX_DATA_FIFO 0x0020 +#define LAN9250_RX_STATUS_FIFO 0x0040 +#define LAN9250_TX_STATUS_FIFO 0x0048 +#define LAN9250_ID_REV 0x0050 +#define LAN9250_IRQ_CFG 0x0054 +#define LAN9250_INT_STS 0x0058 +#define LAN9250_INT_EN 0x005C +#define LAN9250_BYTE_TEST 0x0064 +#define LAN9250_FIFO_INT 0x0068 +#define LAN9250_RX_CFG 0x006C +#define LAN9250_TX_CFG 0x0070 +#define LAN9250_HW_CFG 0x0074 +#define LAN9250_RX_FIFO_INF 0x007C +#define LAN9250_TX_FIFO_INF 0x0080 +#define LAN9250_PMT_CTRL 0x0084 +#define LAN9250_MAC_CSR_CMD 0x00A4 +#define LAN9250_MAC_CSR_DATA 0x00A8 +#define LAN9250_AFC_CFG 0x00AC +#define LAN9250_RESET_CTL 0x01F8 + +/* LAN9250 Host MAC registers */ +#define LAN9250_HMAC_CR 0x01 +#define LAN9250_HMAC_ADDRH 0x02 +#define LAN9250_HMAC_ADDRL 0x03 +#define LAN9250_HMAC_MII_ACC 0x06 +#define LAN9250_HMAC_MII_DATA 0x07 + +/* LAN9250 PHY registers */ +#define LAN9250_PHY_BASIC_CONTROL 0x00 +#define LAN9250_PHY_AN_ADV 0x04 +#define LAN9250_PHY_SPECIAL_MODES 0x12 +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND 0x1B +#define LAN9250_PHY_INTERRUPT_SOURCE 0x1D +#define LAN9250_PHY_INTERRUPT_MASK 0x1E +#define LAN9250_PHY_SPECIAL_CONTROL_STATUS 0x1F + +/* Interrupt Configuration register */ +#define LAN9250_IRQ_CFG_INT_DEAS 0xFF000000 +#define LAN9250_IRQ_CFG_INT_DEAS_10US 0x01000000 +#define LAN9250_IRQ_CFG_INT_DEAS_100US 0x0A000000 +#define LAN9250_IRQ_CFG_INT_DEAS_1MS 0x64000000 +#define LAN9250_IRQ_CFG_INT_DEAS_CLR 0x00004000 +#define LAN9250_IRQ_CFG_INT_DEAS_STS 0x00002000 +#define LAN9250_IRQ_CFG_IRQ_INT 0x00001000 +#define LAN9250_IRQ_CFG_IRQ_EN 0x00000100 +#define LAN9250_IRQ_CFG_IRQ_POL 0x00000010 +#define LAN9250_IRQ_CFG_IRQ_POL_LOW 0x00000000 +#define LAN9250_IRQ_CFG_IRQ_POL_HIGH 0x00000010 +#define LAN9250_IRQ_CFG_IRQ_CLK_SELECT 0x00000002 +#define LAN9250_IRQ_CFG_IRQ_TYPE 0x00000001 +#define LAN9250_IRQ_CFG_IRQ_TYPE_OD 0x00000000 +#define LAN9250_IRQ_CFG_IRQ_TYPE_PP 0x00000001 + +/* INTERRUPT STATUS REGISTER (INT_STS) */ +#define LAN9250_INT_STS_SW_INT 0x80000000 +#define LAN9250_INT_STS_READY 0x40000000 +#define LAN9250_INT_STS_1588_EVNT 0x20000000 +#define LAN9250_INT_STS_PHY_INT 0x04000000 +#define LAN9250_INT_STS_TXSTOP_INT 0x02000000 +#define LAN9250_INT_STS_RXSTOP_INT 0x01000000 +#define LAN9250_INT_STS_RXDFH_INT 0x00800000 +#define LAN9250_INT_STS_TX_IOC 0x00200000 +#define LAN9250_INT_STS_RXD_INT 0x00100000 +#define LAN9250_INT_STS_GPT_INT 0x00080000 +#define LAN9250_INT_STS_PME_INT 0x00020000 +#define LAN9250_INT_STS_TXSO 0x00010000 +#define LAN9250_INT_STS_RWT 0x00008000 +#define LAN9250_INT_STS_RXE 0x00004000 +#define LAN9250_INT_STS_TXE 0x00002000 +#define LAN9250_INT_STS_GPIO 0x00001000 +#define LAN9250_INT_STS_TDFO 0x00000400 +#define LAN9250_INT_STS_TDFA 0x00000200 +#define LAN9250_INT_STS_TSFF 0x00000100 +#define LAN9250_INT_STS_TSFL 0x00000080 +#define LAN9250_INT_STS_RXDF_INT 0x00000040 +#define LAN9250_INT_STS_RSFF 0x00000010 +#define LAN9250_INT_STS_RSFL 0x00000008 + +/* INTERRUPT ENABLE REGISTER (INT_EN) */ +#define LAN9250_INT_EN_SW_INT_EN 0x80000000 +#define LAN9250_INT_EN_READY_EN 0x40000000 +#define LAN9250_INT_EN_1588_EVNT_EN 0x20000000 +#define LAN9250_INT_EN_PHY_INT_EN 0x04000000 +#define LAN9250_INT_EN_TXSTOP_INT_EN 0x02000000 +#define LAN9250_INT_EN_RXSTOP_INT_EN 0x01000000 +#define LAN9250_INT_EN_RXDFH_INT_EN 0x00800000 +#define LAN9250_INT_EN_TIOC_INT_EN 0x00200000 +#define LAN9250_INT_EN_RXD_INT_EN 0x00100000 +#define LAN9250_INT_EN_GPT_INT_EN 0x00080000 +#define LAN9250_INT_EN_PME_INT_EN 0x00020000 +#define LAN9250_INT_EN_TXSO_EN 0x00010000 +#define LAN9250_INT_EN_RWT_INT_EN 0x00008000 +#define LAN9250_INT_EN_RXE_INT_EN 0x00004000 +#define LAN9250_INT_EN_TXE_INT_EN 0x00002000 +#define LAN9250_INT_EN_GPIO_EN 0x00001000 +#define LAN9250_INT_EN_TDFO_EN 0x00000400 +#define LAN9250_INT_EN_TDFA_EN 0x00000200 +#define LAN9250_INT_EN_TSFF_EN 0x00000100 +#define LAN9250_INT_EN_TSFL_EN 0x00000080 +#define LAN9250_INT_EN_RXDF_INT_EN 0x00000040 +#define LAN9250_INT_EN_RSFF_EN 0x00000010 +#define LAN9250_INT_EN_RSFL_EN 0x00000008 + +/* Byte Order Test register */ +#define LAN9250_BYTE_TEST_DEFAULT 0x87654321 +#define BOTR_MASK 0xffffffff + +/* FIFO Level Interrupt register */ +#define LAN9250_FIFO_INT_TX_DATA_AVAILABLE_LEVEL 0xFF000000 +#define LAN9250_FIFO_INT_TX_STATUS_LEVEL 0x00FF0000 +#define LAN9250_FIFO_INT_RX_STATUS_LEVEL 0x000000FF + +/* TRANSMIT CONFIGURATION REGISTER (TX_CFG) */ +#define LAN9250_TX_CFG_TXS_DUMP 0x00008000 +#define LAN9250_TX_CFG_TXD_DUMP 0x00004000 +#define LAN9250_TX_CFG_TXSAO 0x00000004 +#define LAN9250_TX_CFG_TX_ON 0x00000002 +#define LAN9250_TX_CFG_STOP_TX 0x00000001 + +/* HARDWARE CONFIGURATION REGISTER (HW_CFG) */ +#define LAN9250_HW_CFG_DEVICE_READY 0x08000000 +#define LAN9250_HW_CFG_AMDIX_EN_STRAP_STATE 0x02000000 +#define LAN9250_HW_CFG_MBO 0x00100000 +#define LAN9250_HW_CFG_TX_FIF_SZ 0x000F0000 +#define LAN9250_HW_CFG_TX_FIF_SZ_2KB 0x00020000 +#define LAN9250_HW_CFG_TX_FIF_SZ_3KB 0x00030000 +#define LAN9250_HW_CFG_TX_FIF_SZ_4KB 0x00040000 +#define LAN9250_HW_CFG_TX_FIF_SZ_5KB 0x00050000 +#define LAN9250_HW_CFG_TX_FIF_SZ_6KB 0x00060000 +#define LAN9250_HW_CFG_TX_FIF_SZ_7KB 0x00070000 +#define LAN9250_HW_CFG_TX_FIF_SZ_8KB 0x00080000 +#define LAN9250_HW_CFG_TX_FIF_SZ_9KB 0x00090000 +#define LAN9250_HW_CFG_TX_FIF_SZ_10KB 0x000A0000 +#define LAN9250_HW_CFG_TX_FIF_SZ_11KB 0x000B0000 +#define LAN9250_HW_CFG_TX_FIF_SZ_12KB 0x000C0000 +#define LAN9250_HW_CFG_TX_FIF_SZ_13KB 0x000D0000 +#define LAN9250_HW_CFG_TX_FIF_SZ_14KB 0x000E0000 + +/* RX FIFO Information register */ +#define LAN9250_RX_FIFO_INF_RXSUSED 0x00FF0000 +#define LAN9250_RX_FIFO_INF_RXDUSED 0x0000FFFF + +/* TX FIFO Information register */ +#define LAN9250_TX_FIFO_INF_TXSUSED 0x00FF0000 +#define LAN9250_TX_FIFO_INF_TXFREE 0x0000FFFF + +/* Power Management Control Register (PMT_CTRL) */ +#define LAN9250_PMT_CTRL_PM_MODE 0xE0000000 +#define LAN9250_PMT_CTRL_PM_SLEEP_EN 0x10000000 +#define LAN9250_PMT_CTRL_PM_WAKE 0x08000000 +#define LAN9250_PMT_CTRL_LED_DIS 0x04000000 +#define LAN9250_PMT_CTRL_1588_DIS 0x02000000 +#define LAN9250_PMT_CTRL_1588_TSU_DIS 0x00400000 +#define LAN9250_PMT_CTRL_HMAC_DIS 0x00080000 +#define LAN9250_PMT_CTRL_HMAC_SYS_ONLY_DIS 0x00040000 +#define LAN9250_PMT_CTRL_ED_STS 0x00010000 +#define LAN9250_PMT_CTRL_ED_EN 0x00004000 +#define LAN9250_PMT_CTRL_WOL_EN 0x00000200 +#define LAN9250_PMT_CTRL_PME_TYPE 0x00000040 +#define LAN9250_PMT_CTRL_WOL_STS 0x00000020 +#define LAN9250_PMT_CTRL_PME_IND 0x00000008 +#define LAN9250_PMT_CTRL_PME_POL 0x00000004 +#define LAN9250_PMT_CTRL_PME_EN 0x00000002 +#define LAN9250_PMT_CTRL_READY 0x00000001 + +/* HOST MAC CSR INTERFACE COMMAND REGISTER (MAC_CSR_CMD) */ +#define LAN9250_MAC_CSR_CMD_BUSY 0x80000000 +#define LAN9250_MAC_CSR_CMD_WRITE 0x00000000 +#define LAN9250_MAC_CSR_CMD_READ 0x40000000 +#define LAN9250_MAC_CSR_CMD_ADDR 0x000000FF + +/* Reset Control Register (RESET_CTL) */ +#define LAN9250_RESET_CTL_HMAC_RST 0x00000020 +#define LAN9250_RESET_CTL_PHY_RST 0x00000002 +#define LAN9250_RESET_CTL_DIGITAL_RST 0x00000001 + +/* HOST MAC CONTROL REGISTER (HMAC_CR) */ +#define LAN9250_HMAC_CR_RXALL 0x80000000 +#define LAN9250_HMAC_CR_HMAC_EEE_ENABLE 0x02000000 +#define LAN9250_HMAC_CR_RCVOWN 0x00800000 +#define LAN9250_HMAC_CR_LOOPBK 0x00200000 +#define LAN9250_HMAC_CR_FDPX 0x00100000 +#define LAN9250_HMAC_CR_MCPAS 0x00080000 +#define LAN9250_HMAC_CR_PRMS 0x00040000 +#define LAN9250_HMAC_CR_INVFILT 0x00020000 +#define LAN9250_HMAC_CR_PASSBAD 0x00010000 +#define LAN9250_HMAC_CR_HO 0x00008000 +#define LAN9250_HMAC_CR_HPFILT 0x00002000 +#define LAN9250_HMAC_CR_BCAST 0x00000800 +#define LAN9250_HMAC_CR_DISRTY 0x00000400 +#define LAN9250_HMAC_CR_PADSTR 0x00000100 +#define LAN9250_HMAC_CR_BOLMT 0x000000C0 +#define LAN9250_HMAC_CR_BOLMT_10_BITS 0x00000000 +#define LAN9250_HMAC_CR_BOLMT_8_BITS 0x00000040 +#define LAN9250_HMAC_CR_BOLMT_4_BITS 0x00000080 +#define LAN9250_HMAC_CR_BOLMT_1_BIT 0x000000C0 +#define LAN9250_HMAC_CR_DFCHK 0x00000020 +#define LAN9250_HMAC_CR_TXEN 0x00000008 +#define LAN9250_HMAC_CR_RXEN 0x00000004 + +/* HOST MAC MII ACCESS REGISTER (HMAC_MII_ACC) */ +#define LAN9250_HMAC_MII_ACC_PHY_ADDR 0x0000F800 +#define LAN9250_HMAC_MII_ACC_PHY_ADDR_DEFAULT 0x00000800 +#define LAN9250_HMAC_MII_ACC_MIIRINDA 0x000007C0 +#define LAN9250_HMAC_MII_ACC_MIIW_R 0x00000002 +#define LAN9250_HMAC_MII_ACC_MIIBZY 0x00000001 + +/* PHY Basic Control Register (PHY_BASIC_CONTROL) */ +#define LAN9250_PHY_BASIC_CONTROL_PHY_SRST 0x8000 +#define LAN9250_PHY_BASIC_CONTROL_PHY_LOOPBACK 0x4000 +#define LAN9250_PHY_BASIC_CONTROL_PHY_SPEED_SEL_LSB 0x2000 +#define LAN9250_PHY_BASIC_CONTROL_PHY_AN 0x1000 +#define LAN9250_PHY_BASIC_CONTROL_PHY_PWR_DWN 0x0800 +#define LAN9250_PHY_BASIC_CONTROL_PHY_RST_AN 0x0200 +#define LAN9250_PHY_BASIC_CONTROL_PHY_DUPLEX 0x0100 +#define LAN9250_PHY_BASIC_CONTROL_PHY_COL_TEST 0x0080 + +/* PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV) */ +#define LAN9250_PHY_AN_ADV_NEXT_PAGE 0x8000 +#define LAN9250_PHY_AN_ADV_REMOTE_FAULT 0x2000 +#define LAN9250_PHY_AN_ADV_EXTENDED_NEXT_PAGE 0x1000 +#define LAN9250_PHY_AN_ADV_ASYM_PAUSE 0x0800 +#define LAN9250_PHY_AN_ADV_SYM_PAUSE 0x0400 +#define LAN9250_PHY_AN_ADV_100BTX_FD 0x0100 +#define LAN9250_PHY_AN_ADV_100BTX_HD 0x0080 +#define LAN9250_PHY_AN_ADV_10BT_FD 0x0040 +#define LAN9250_PHY_AN_ADV_10BT_HD 0x0020 +#define LAN9250_PHY_AN_ADV_SELECTOR 0x001F +#define LAN9250_PHY_AN_ADV_SELECTOR_DEFAULT 0x0001 + +/* PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS) */ +#define LAN9250_PHY_MODE_CONTROL_STATUS_EDPWRDOWN 0x2000 +#define LAN9250_PHY_MODE_CONTROL_STATUS_ALTINT 0x0040 +#define LAN9250_PHY_MODE_CONTROL_STATUS_ENERGYON 0x0002 + +/* PHY Special Control/Status Indication Register (PHY_SPECIAL_CONTROL_STAT_IND) */ +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXCTRL 0x8000 +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXEN 0x4000 +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_AMDIXSTATE 0x2000 +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_SQEOFF 0x0800 +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_FEFI_EN 0x0020 +#define LAN9250_PHY_SPECIAL_CONTROL_STAT_IND_XPOL 0x0010 + +/* PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE) */ +#define LAN9250_PHY_INTERRUPT_SOURCE_LINK_UP 0x0200 +#define LAN9250_PHY_INTERRUPT_SOURCE_ENERGYON 0x0080 +#define LAN9250_PHY_INTERRUPT_SOURCE_AN_COMPLETE 0x0040 +#define LAN9250_PHY_INTERRUPT_SOURCE_REMOTE_FAULT 0x0020 +#define LAN9250_PHY_INTERRUPT_SOURCE_LINK_DOWN 0x0010 +#define LAN9250_PHY_INTERRUPT_SOURCE_AN_LP_ACK 0x0008 +#define LAN9250_PHY_INTERRUPT_SOURCE_PARALLEL_DETECT_FAULT 0x0004 +#define LAN9250_PHY_INTERRUPT_SOURCE_AN_PAGE_RECEIVED 0x0002 + +/* PHY Interrupt Mask Register (PHY_INTERRUPT_MASK) */ +#define LAN9250_PHY_INTERRUPT_MASK_LINK_UP 0x0200 +#define LAN9250_PHY_INTERRUPT_MASK_ENERGYON 0x0080 +#define LAN9250_PHY_INTERRUPT_MASK_AN_COMPLETE 0x0040 +#define LAN9250_PHY_INTERRUPT_MASK_REMOTE_FAULT 0x0020 +#define LAN9250_PHY_INTERRUPT_MASK_LINK_DOWN 0x0010 +#define LAN9250_PHY_INTERRUPT_MASK_AN_LP_ACK 0x0008 +#define LAN9250_PHY_INTERRUPT_MASK_PARALLEL_DETECT_FAULT 0x0004 +#define LAN9250_PHY_INTERRUPT_MASK_AN_PAGE_RECEIVED 0x0002 + +/* Chip ID and Revision register */ +#define LAN9250_ID_REV_CHIP_ID 0xFFFF0000 +#define LAN9250_ID_REV_CHIP_ID_DEFAULT 0x92500000 +#define LAN9250_ID_REV_CHIP_REV 0x0000FFFF + +struct lan9250_config { + struct spi_dt_spec spi; + struct gpio_dt_spec interrupt; + struct gpio_dt_spec reset; + uint8_t full_duplex; + int32_t timeout; +}; + +struct lan9250_runtime { + struct net_if *iface; + const struct device *dev; + + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ETH_LAN9250_RX_THREAD_STACK_SIZE); + k_tid_t tid_int; + struct k_thread thread; + + uint8_t mac_address[6]; + struct gpio_callback gpio_cb; + struct k_sem tx_rx_sem; + struct k_sem int_sem; + uint8_t buf[NET_ETH_MAX_FRAME_SIZE]; + struct k_mutex lock; +}; + +#endif /*_LAN9250_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_imx_netc_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_imx_netc_priv.h new file mode 100644 index 00000000..f09e718f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_imx_netc_priv.h @@ -0,0 +1,121 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_IMX_NETC_PRIV_H_ +#define ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_IMX_NETC_PRIV_H_ + +#include "fsl_netc_endpoint.h" +#include "fsl_msgintr.h" + +/* Buffer and descriptor alignment */ +#define NETC_BD_ALIGN 128 +#define NETC_BUFF_ALIGN 64 +#define NETC_RX_RING_BUF_SIZE_ALIGN \ + SDK_SIZEALIGN(CONFIG_ETH_NXP_IMX_RX_RING_BUF_SIZE, NETC_BUFF_ALIGN) + +/* MSIX definitions */ +#define NETC_TX_MSIX_ENTRY_IDX 0 +#define NETC_RX_MSIX_ENTRY_IDX 1 +#define NETC_MSIX_ENTRY_NUM 2 + +#define NETC_MSIX_EVENTS_COUNT NETC_MSIX_ENTRY_NUM +#define NETC_TX_INTR_MSG_DATA_START 0 +#define NETC_RX_INTR_MSG_DATA_START 16 +#define NETC_DRV_MAX_INST_SUPPORT 16 + +/* MSGINTR */ +#define NETC_MSGINTR_CHANNEL 0 + +#if (CONFIG_ETH_NXP_IMX_MSGINTR == 1) +#define NETC_MSGINTR MSGINTR1 +#define NETC_MSGINTR_IRQ MSGINTR1_IRQn +#elif (CONFIG_ETH_NXP_IMX_MSGINTR == 2) +#define NETC_MSGINTR MSGINTR2 +#define NETC_MSGINTR_IRQ MSGINTR2_IRQn +#else +#error "Current CONFIG_ETH_NXP_IMX_MSGINTR not support" +#endif + +/* Timeout for various operations */ +#define NETC_TIMEOUT K_MSEC(20) + +/* Helper macros to convert from Zephyr PHY speed to NETC speed/duplex types */ +#define PHY_TO_NETC_SPEED(x) \ + (PHY_LINK_IS_SPEED_1000M(x) \ + ? kNETC_MiiSpeed1000M \ + : (PHY_LINK_IS_SPEED_100M(x) ? kNETC_MiiSpeed100M : kNETC_MiiSpeed10M)) + +#define PHY_TO_NETC_DUPLEX_MODE(x) \ + (PHY_LINK_IS_FULL_DUPLEX(x) ? kNETC_MiiFullDuplex : kNETC_MiiHalfDuplex) + +/* Helper function to generate an Ethernet MAC address for a given ENETC instance */ +#define FREESCALE_OUI_B0 0x00 +#define FREESCALE_OUI_B1 0x04 +#define FREESCALE_OUI_B2 0x9f + +#define _NETC_GENERATE_MAC_ADDRESS_RANDOM \ + gen_random_mac(mac_addr, FREESCALE_OUI_B0, FREESCALE_OUI_B1, FREESCALE_OUI_B2) + +#define _NETC_GENERATE_MAC_ADDRESS_UNIQUE(n) \ + do { \ + uint32_t id = 0x001100; \ + \ + mac_addr[0] = FREESCALE_OUI_B0; \ + mac_addr[1] = FREESCALE_OUI_B1; \ + /* Set MAC address locally administered bit (LAA) */ \ + mac_addr[2] = FREESCALE_OUI_B2 | 0x02; \ + mac_addr[3] = (id >> 16) & 0xff; \ + mac_addr[4] = (id >> 8) & 0xff; \ + mac_addr[5] = (id + n) & 0xff; \ + } while (0) + +#define NETC_GENERATE_MAC_ADDRESS(n) \ + static void netc_eth##n##_generate_mac(uint8_t mac_addr[6]) \ + { \ + COND_CODE_1(DT_INST_PROP(n, zephyr_random_mac_address), \ + (_NETC_GENERATE_MAC_ADDRESS_RANDOM), \ + (COND_CODE_0(DT_INST_NODE_HAS_PROP(n, local_mac_address), \ + (_NETC_GENERATE_MAC_ADDRESS_UNIQUE(n)), \ + (ARG_UNUSED(mac_addr))))); \ + } + +struct netc_eth_config { + uint16_t si_idx; + const struct device *phy_dev; + void (*generate_mac)(uint8_t *mac_addr); + void (*bdr_init)(netc_bdr_config_t *bdr_config, netc_rx_bdr_config_t *rx_bdr_config, + netc_tx_bdr_config_t *tx_bdr_config); + const struct pinctrl_dev_config *pincfg; + uint8_t tx_intr_msg_data; + uint8_t rx_intr_msg_data; +}; + +typedef uint8_t rx_buffer_t[NETC_RX_RING_BUF_SIZE_ALIGN]; + +struct netc_eth_data { + ep_handle_t handle; + struct net_if *iface; + uint8_t mac_addr[6]; + /* TX */ + struct k_mutex tx_mutex; + netc_tx_frame_info_t tx_info; + uint8_t *tx_buff; + volatile bool tx_done; + /* RX */ + struct k_sem rx_sem; + struct k_thread rx_thread; + + K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_NXP_IMX_RX_THREAD_STACK_SIZE); + uint8_t *rx_frame; +}; + +int netc_eth_init_common(const struct device *dev); +int netc_eth_tx(const struct device *dev, struct net_pkt *pkt); +enum ethernet_hw_caps netc_eth_get_capabilities(const struct device *dev); +int netc_eth_set_config(const struct device *dev, enum ethernet_config_type type, + const struct ethernet_config *config); + +#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_IMX_NETC_PRIV_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_s32_netc_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_s32_netc_priv.h index e259b67c..760522b5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_s32_netc_priv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_nxp_s32_netc_priv.h @@ -1,5 +1,5 @@ /* - * Copyright 2022-2023 NXP + * Copyright 2022-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -99,7 +99,7 @@ #define _CONCAT3(a, b, c) DT_CAT3(a, b, c) struct nxp_s32_eth_msix { - void (*handler)(uint8_t chan, const uint32_t *buf, uint8_t buf_size); + void (*handler)(uint8_t chan, const uint32 *buf, uint8_t buf_size); struct mbox_dt_spec mbox_spec; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_stm32_hal_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_stm32_hal_priv.h index 9502537a..4aef0389 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_stm32_hal_priv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/eth_stm32_hal_priv.h @@ -50,10 +50,9 @@ struct eth_stm32_hal_dev_data { const struct device *clock; struct k_mutex tx_mutex; struct k_sem rx_int_sem; -#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X) || \ - defined(CONFIG_ETH_STM32_HAL_API_V2) +#if defined(CONFIG_ETH_STM32_HAL_API_V2) struct k_sem tx_int_sem; -#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X || CONFIG_ETH_STM32_HAL_API_V2*/ +#endif /* CONFIG_ETH_STM32_HAL_API_V2 */ K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_STM32_HAL_RX_THREAD_STACK_SIZE); struct k_thread rx_thread; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/oa_tc6.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/oa_tc6.h index 0918e138..c61e0359 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/oa_tc6.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/oa_tc6.h @@ -113,8 +113,9 @@ struct oa_tc6 { }; typedef struct { - uint32_t address; - uint32_t value; + uint8_t mms; + uint8_t address; + uint16_t value; } oa_mem_map_t; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/phy/phy_dm8806_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/phy/phy_dm8806_priv.h new file mode 100644 index 00000000..4c4a292c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ethernet/phy/phy_dm8806_priv.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2024 Robert Slawinski + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Port 0~4 PHY Control Register. */ +#define PORTX_PHY_CONTROL_REGISTER 0x0u +/* 10 Mbit/s transfer with half duplex mask. */ +#define MODE_10_BASET_HALF_DUPLEX 0x0u +/* 10 Mbit/s transfer with full duplex mask. */ +#define MODE_10_BASET_FULL_DUPLEX 0x100u +/* 100 Mbit/s transfer with half duplex mask. */ +#define MODE_100_BASET_HALF_DUPLEX 0x2000u +/* 100 Mbit/s transfer with full duplex mask. */ +#define MODE_100_BASET_FULL_DUPLEX 0x2100u +/* Duplex mode ability offset. */ +#define DUPLEX_MODE (1 << 8) +/* Power down mode offset. */ +#define POWER_DOWN (1 << 11) +/* Auto negotiation mode offset. */ +#define AUTO_NEGOTIATION (1 << 12) +/* Link speed selection offset. */ +#define LINK_SPEED (1 << 13) + +/* Port 0~4 Status Data Register. */ +#define PORTX_SWITCH_STATUS 0x10u +/* 10 Mbit/s transfer speed with half duplex. */ +#define SPEED_10MBPS_HALF_DUPLEX 0x00u +/* 10 Mbit/s transfer speed with full duplex. */ +#define SPEED_10MBPS_FULL_DUPLEX 0x01u +/* 100 Mbit/s transfer speed with half duplex. */ +#define SPEED_100MBPS_HALF_DUPLEX 0x02u +/* 100 Mbit/s transfer speed with full duplex. */ +#define SPEED_100MBPS_FULL_DUPLEX 0x03u +/* Speed and duplex mode status offset. */ +#define SPEED_AND_DUPLEX_OFFSET 0x01u +/* Speed and duplex mode staus mask. */ +#define SPEED_AND_DUPLEX_MASK 0x07u +/* Link status mask. */ +#define LINK_STATUS_MASK 0x1u + +/* Switch Engine Registers */ +/* Address Table Control And Status Register PHY Address */ +#define ADDR_TAB_CTRL_STAT_PHY_ADDR 0x15u +/* Address Table Control And Status Register Register SAddress */ +#define ADDR_TAB_CTRL_STAT_REG_ADDR 0x10u + +/* Address Table Access bussy flag offset */ +#define ATB_S_OFFSET 0xf +/* Address Table Command Result flag offset */ +#define ATB_CR_OFFSET 0xd +/* Address Table Command Result flag mask */ +#define ATB_CR_MASK 0x3 + +/* Unicast Address Table Index*/ +#define UNICAST_ADDR_TAB (1 << 0 | 1 << 1) +/* Multicast Address Table Index*/ +#define MULTICAST_ADDR_TAB (1 << 0) +/* IGMP Table Index*/ +#define IGMP_ADDR_TAB (1 << 1) + +/* Read a entry with sequence number of address table */ +#define ATB_CMD_READ (1 << 2 | 1 << 3 | 1 << 4) +/* Write a entry with MAC address */ +#define ATB_CMD_WRITE (1 << 2) +/* Delete a entry with MAC address */ +#define ATB_CMD_DELETE (1 << 3) +/* Search a entry with MAC address */ +#define ATB_CMD_SEARCH (1 << 2 | 1 << 3) +/* Clear one or more than one entries with Port or FID */ +#define ATB_CMD_CLEAR (1 << 4) + +/* Address Table Data 0 PHY Address */ +#define ADDR_TAB_DATA0_PHY_ADDR 0x15u +/* Address Table Data 0 Register Address */ +#define ADDR_TAB_DATA0_REG_ADDR 0x11u +/* Port number or port map mask*/ +#define ATB_PORT_MASK 0x1f + +/* Address Table Data 1 PHY Address */ +#define ADDR_TAB_DATA1_PHY_ADDR 0x15u +/* Address Table Data 1 Register Address */ +#define ADDR_TAB_DATA1_REG_ADDR 0x12u + +/* Address Table Data 2 PHY Address */ +#define ADDR_TAB_DATA2_PHY_ADDR 0x15u +/* Address Table Data 2 Register Address */ +#define ADDR_TAB_DATA2_REG_ADDR 0x13u + +/* Address Table Data 3 PHY Address */ +#define ADDR_TAB_DATA3_PHY_ADDR 0x15u +/* Address Table Data 3 Register Address */ +#define ADDR_TAB_DATA3_REG_ADDR 0x14u + +/* Address Table Data 4 PHY Address */ +#define ADDR_TAB_DATA4_PHY_ADDR 0x15u +/* Address Table Data 4 Register Address */ +#define ADDR_TAB_DATA4_REG_ADDR 0x15u + +/* WoL Control Register PHY Address */ +#define WOLL_CTRL_REG_PHY_ADDR 0x15u +/* WoL Control Register Register Address */ +#define WOLL_CTRL_REG_REG_ADDR 0x1bu + +/* PHY address 0x18h */ +#define PHY_ADDRESS_18H 0x18u + +/* Interrupt Status Register PHY Address. */ +#define INT_STAT_PHY_ADDR 0x18u +/* Interrupt Status Register Register Address. */ +#define INT_STAT_REG_ADDR 0x18u + +/* Interrupt Mask & Control Register PHY Address. */ +#define INT_MASK_CTRL_PHY_ADDR 0x18u +/* Interrupt Mask & Control Register Register Address. */ +#define INT_MASK_CTRL_REG_ADDR 0x19u + +#define PORT5_MAC_CONTROL 0x15u +/* Port 5 Force Speed control bit */ +#define P5_SPEED_100M ~BIT(0) +/* Port 5 Force Duplex control bit */ +#define P5_FULL_DUPLEX ~BIT(1) +/* Port 5 Force Link control bit. Only available in force mode. */ +#define P5_FORCE_LINK_ON ~BIT(2) +/* Port 5 Force Mode Enable control bit. Only available for + * MII/RevMII/RMII + */ +#define P5_EN_FORCE BIT(3) +/* Bit 4 is reserved and should not be use */ +/* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5 + * be configured as RMII + */ +#define P5_50M_CLK_OUT_ENABLE BIT(5) +/* Port 5 Clock Source Selection control bit. Only available when Port 5 + * is configured as RMII + */ +#define P5_50M_INT_CLK_SOURCE BIT(6) +/* Port 5 Output Pin Slew Rate. */ +#define P5_NORMAL_SLEW_RATE ~BIT(7) +/* IRQ and LED Control Register. */ +#define IRQ_LED_CONTROL 0x17u +/* LED mode 0: + * LNK_LED: + * 100M link fail - LED off + * 100M link ok and no TX/RX activity - LED on + * 100M link ok and TX/RX activity - LED blinking + * SPD_LED: + * No colision: - LED off + * Colision: - LED blinking + * FDX_LED: + * 10M link fail - LED off + * 10M link ok and no TX/RX activity - LED on + * 10M link ok and TX/RX activity - LED blinking + */ +#define LED_MODE_0 ~(BIT(0) | BIT(1)) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/firmware/scmi/mailbox.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/firmware/scmi/mailbox.h new file mode 100644 index 00000000..4e758d8e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/firmware/scmi/mailbox.h @@ -0,0 +1,117 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_ +#define _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_ + +#include +#include +#include +#include +#include + +#define DT_DRV_COMPAT arm_scmi + +/* get a `struct device` for a protocol's shared memory area */ +#define _SCMI_MBOX_SHMEM_BY_IDX(node_id, idx) \ + COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \ + (DEVICE_DT_GET(DT_PROP_BY_IDX(node_id, shmem, idx))), \ + (NULL)) + +/* get the name of mailbox channel's private data */ +#define _SCMI_MBOX_CHAN_NAME(proto, idx)\ + CONCAT(SCMI_TRANSPORT_CHAN_NAME(proto, idx), _, priv) + +/* fetch a mailbox channel's doorbell */ +#define _SCMI_MBOX_CHAN_DBELL(node_id, name) \ + COND_CODE_1(DT_PROP_HAS_NAME(node_id, mboxes, name), \ + (MBOX_DT_SPEC_GET(node_id, name)), \ + ({ })) + +/* define private data for a protocol TX channel */ +#define _SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto) \ + static struct scmi_mbox_channel _SCMI_MBOX_CHAN_NAME(proto, 0) =\ + { \ + .shmem = _SCMI_MBOX_SHMEM_BY_IDX(node_id, 0), \ + .tx = _SCMI_MBOX_CHAN_DBELL(node_id, tx), \ + .tx_reply = _SCMI_MBOX_CHAN_DBELL(node_id, tx_reply), \ + } + +/* + * Define a mailbox channel. This does two things: + * 1) Define the mandatory `struct scmi_channel` structure + * 2) Define the mailbox-specific private data for said + * channel (i.e: a struct scmi_mbox_channel) + */ +#define _SCMI_MBOX_CHAN_DEFINE(node_id, proto, idx) \ + _SCMI_MBOX_CHAN_DEFINE_PRIV_TX(node_id, proto); \ + DT_SCMI_TRANSPORT_CHAN_DEFINE(node_id, idx, proto, \ + &(_SCMI_MBOX_CHAN_NAME(proto, idx))); \ + +/* + * Optionally define a mailbox channel for a protocol. This is optional + * because a protocol might not have a dedicated channel. + */ +#define _SCMI_MBOX_CHAN_DEFINE_OPTIONAL(node_id, proto, idx) \ + COND_CODE_1(DT_PROP_HAS_IDX(node_id, shmem, idx), \ + (_SCMI_MBOX_CHAN_DEFINE(node_id, proto, idx)), \ + ()) + +/* define a TX channel for a protocol node. This is preferred over + * _SCMI_MBOX_CHAN_DEFINE_OPTIONAL() since support for RX channels + * might be added later on. This macro is supposed to also define + * the RX channel + */ +#define SCMI_MBOX_PROTO_CHAN_DEFINE(node_id)\ + _SCMI_MBOX_CHAN_DEFINE_OPTIONAL(node_id, DT_REG_ADDR(node_id), 0) + +/* define and validate base protocol TX channel */ +#define DT_INST_SCMI_MBOX_BASE_CHAN_DEFINE(inst) \ + BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 1 || \ + (DT_INST_PROP_HAS_IDX(inst, shmem, 0) && \ + DT_INST_PROP_HAS_NAME(inst, mboxes, tx)), \ + "bad bidirectional channel description"); \ + \ + BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 2 || \ + (DT_INST_PROP_HAS_NAME(inst, mboxes, tx) && \ + DT_INST_PROP_HAS_NAME(inst, mboxes, tx_reply)), \ + "bad unidirectional channel description"); \ + \ + BUILD_ASSERT(DT_INST_PROP_LEN(inst, shmem) == 1, \ + "bad SHMEM count"); \ + \ + BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) <= 2, \ + "bad mbox count"); \ + \ + _SCMI_MBOX_CHAN_DEFINE(DT_INST(inst, DT_DRV_COMPAT), SCMI_PROTOCOL_BASE, 0) + +/* + * Define the mailbox-based transport layer. What this does is: + * + * 1) Goes through all protocol nodes (children of the `scmi` node) + * and creates a `struct scmi_channel` and its associated + * `struct scmi_mbox_channel` if the protocol has a dedicated channel. + * + * 2) Creates aforementioned structures for the base protocol + * (identified by the `scmi` node) + * + * 3) "registers" the driver via `DT_INST_SCMI_TRANSPORT_DEFINE()`. + */ +#define DT_INST_SCMI_MAILBOX_DEFINE(inst, level, prio, api) \ + DT_INST_FOREACH_CHILD_STATUS_OKAY(inst, SCMI_MBOX_PROTO_CHAN_DEFINE) \ + DT_INST_SCMI_MBOX_BASE_CHAN_DEFINE(inst) \ + DT_INST_SCMI_TRANSPORT_DEFINE(inst, NULL, NULL, NULL, level, prio, api) + +struct scmi_mbox_channel { + /* SHMEM area bound to the channel */ + const struct device *shmem; + /* TX dbell */ + struct mbox_dt_spec tx; + /* TX reply dbell */ + struct mbox_dt_spec tx_reply; +}; + +#endif /* _ZEPHYR_DRIVERS_FIRMWARE_SCMI_MAILBOX_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_hp_ra.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_hp_ra.h index a2c208c8..968c74c4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_hp_ra.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_hp_ra.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2024 Renesas Electronics Corporation + * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,54 +12,33 @@ #include #include -#if DT_PROP(DT_INST(0, soc_nv_flash), write_block_size) -#define FLASH_RA_WRITE_BLOCK_SIZE DT_PROP(DT_INST(0, soc_nv_flash), write_block_size) -#else -#error Flash write block size not available -/* Flash Write block size is extracted from device tree */ -/* as flash node property 'write-block-size' */ -#endif - -#if defined(CONFIG_DUAL_BANK_MODE) -#define SOC_NV_FLASH_SIZE 0x2F8000 -#else -#define SOC_NV_FLASH_SIZE DT_REG_SIZE(DT_INST(0, soc_nv_flash)) -#endif - -#define VECTOR_NUMBER_FCU_FRDYI ((IRQn_Type) 0) /* FCU FRDYI (Flash ready interrupt) */ -#define VECTOR_NUMBER_FCU_FIFERR ((IRQn_Type) 1) /* FCU FIFERR (Flash access error interrupt) */ - -struct flash_hp_ra_data { - struct st_flash_hp_instance_ctrl flash_ctrl; - struct st_flash_cfg fsp_config; -}; - -struct flash_hp_ra_config { - struct flash_parameters flash_ra_parameters; -}; +#define CHECK_EQ(val1, val2) ((val1) == (val2) ? 1 : 0) +#define GET_SIZE(COND, value, default_value) ((COND) ? (value) : (default_value)) #define FLASH_HP_BANK2_OFFSET \ (BSP_FEATURE_FLASH_HP_CF_DUAL_BANK_START - BSP_FEATURE_FLASH_CODE_FLASH_START) #define FLASH_HP_CF_BLOCK_8KB_SIZE BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE #define FLASH_HP_CF_BLOCK_32KB_SIZE BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE +#define FLASH_HP_DF_BLOCK_SIZE BSP_FEATURE_FLASH_HP_DF_BLOCK_SIZE +#define FLASH_HP_DF_START BSP_FEATURE_FLASH_DATA_FLASH_START -#define FLASH_HP_CF_BLOCK_8KB_LOW_START (0) -#define FLASH_HP_CF_BLOCK_8KB_LOW_END (7) +#define FLASH_HP_CF_BLOCK_8KB_LOW_START (0) +#define FLASH_HP_CF_BLOCK_8KB_LOW_END (7) #define FLASH_HP_CF_BLOCK_8KB_HIGH_START (70) #define FLASH_HP_CF_BLOCK_8KB_HIGH_END (77) -#define FLASH_HP_CF_BLOCK_32KB_LINEAR_START (8) +#define FLASH_HP_CF_BLOCK_32KB_LINEAR_START (8) #define FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_START (8) #define FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_START (78) -#if defined(CONFIG_SOC_R7FA8M1AHECBD) || defined(CONFIG_SOC_R7FA8D1BHECBD) \ -|| defined(CONFIG_SOC_R7FA8T1AHECBD) -#define FLASH_RESERVED_AREA_NUM (33) -#define FLASH_HP_CF_BLOCK_32KB_LINEAR_END (68) -#define FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_END (36) -#define FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_END (106) +#if defined(CONFIG_SOC_R7FA8M1AHECBD) || defined(CONFIG_SOC_R7FA8D1BHECBD) || \ + defined(CONFIG_SOC_R7FA8T1AHECBD) +#define FLASH_RESERVED_AREA_NUM (33) +#define FLASH_HP_CF_BLOCK_32KB_LINEAR_END (68) +#define FLASH_HP_CF_BLOCK_32KB_DUAL_LOW_END (36) +#define FLASH_HP_CF_BLOCK_32KB_DUAL_HIGH_END (106) #endif #if defined(CONFIG_FLASH_EX_OP_ENABLED) @@ -68,24 +48,46 @@ struct flash_hp_ra_config { #define FLASH_HP_FCU_CONFIG_SET_PBPS (0x1300A1E0U) #define FLASH_HP_FCU_CONFIG_SET_PBPS_SEC (0x0300A260U) +#endif /* CONFIG_FLASH_EX_OP_ENABLED */ /* Zero based offset into g_configuration_area_data[] for BPS */ #define FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET (0U) +enum flash_region { + CODE_FLASH, + DATA_FLASH, +}; + +typedef void (*irq_config_func_t)(const struct device *dev); + +struct flash_hp_ra_controller { + struct st_flash_hp_instance_ctrl flash_ctrl; + struct k_sem ctrl_sem; + struct st_flash_cfg fsp_config; +}; + +struct flash_hp_ra_controller_config { + irq_config_func_t irq_config; +}; + +struct flash_hp_ra_data { + struct flash_hp_ra_controller *controller; + enum flash_region FlashRegion; + uint32_t area_address; + uint32_t area_size; +}; + +struct flash_hp_ra_config { + struct flash_parameters flash_ra_parameters; +}; + +struct event_flash { + volatile bool erase_complete; + volatile bool write_complete; +}; + #if defined(CONFIG_FLASH_RA_WRITE_PROTECT) -int flash_ra_block_protect_set(const struct device *dev, - const struct flash_ra_ex_write_protect_in_t *request); -int flash_ra_block_protect_get(const struct device *dev, - struct flash_ra_ex_write_protect_out_t *response); int flash_ra_ex_op_write_protect(const struct device *dev, const uintptr_t in, void *out); #endif /*CONFIG_FLASH_RA_WRITE_PROTECT*/ -fsp_err_t R_FLASH_HP_BlockProtectSet(flash_ctrl_t *const p_api_ctrl, uint8_t *bps_val_ns, - uint8_t *bps_val_sec, uint8_t *bps_val_sel, - uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, uint32_t size); -fsp_err_t R_FLASH_HP_BlockProtectGet(flash_ctrl_t *const p_api_ctrl, uint32_t *bps_val_ns, - uint32_t *bps_val_sec, uint8_t *bps_val_sel, - uint8_t *pbps_val_ns, uint8_t *pbps_val_sec, uint32_t *size); -#endif - #endif /* ZEPHYR_DRIVERS_FLASH_RA_HP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_stm32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_stm32.h index ca08b7e1..48e75145 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_stm32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/flash_stm32.h @@ -10,6 +10,7 @@ #define ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ #include +#include "stm32_hsem.h" #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_flash_controller), clocks) || \ DT_NODE_HAS_PROP(DT_INST(0, st_stm32h7_flash_controller), clocks) @@ -271,6 +272,40 @@ static inline bool flash_stm32_range_exists(const struct device *dev, } #endif /* CONFIG_FLASH_PAGE_LAYOUT */ + +#if defined(CONFIG_MULTITHREADING) || defined(CONFIG_STM32H7_DUAL_CORE) +/* + * This is named flash_stm32_sem_take instead of flash_stm32_lock (and + * similarly for flash_stm32_sem_give) to avoid confusion with locking + * actual flash pages. + */ + +static inline void _flash_stm32_sem_take(const struct device *dev) +{ + k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER); + z_stm32_hsem_lock(CFG_HW_FLASH_SEMID, HSEM_LOCK_WAIT_FOREVER); +} + +static inline void _flash_stm32_sem_give(const struct device *dev) +{ + z_stm32_hsem_unlock(CFG_HW_FLASH_SEMID); + k_sem_give(&FLASH_STM32_PRIV(dev)->sem); +} + +#define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1) +#define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev) +#define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev) +#else +#define flash_stm32_sem_init(dev) +#define flash_stm32_sem_take(dev) +#define flash_stm32_sem_give(dev) +#endif /* CONFIG_MULTITHREADING */ + +#ifdef CONFIG_FLASH_EX_OP_ENABLED +int flash_stm32_ex_op(const struct device *dev, uint16_t code, + const uintptr_t in, void *out); +#endif /* CONFIG_FLASH_EX_OP_ENABLED */ + static inline bool flash_stm32_valid_write(off_t offset, uint32_t len) { return ((offset % FLASH_STM32_WRITE_BLOCK_SIZE == 0) && @@ -311,22 +346,14 @@ int flash_stm32_get_wp_sectors(const struct device *dev, uint32_t *protected_sectors); #endif #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION) +uint8_t flash_stm32_get_rdp_level(const struct device *dev); -int flash_stm32_update_rdp(const struct device *dev, bool enable, - bool permanent); - -int flash_stm32_get_rdp(const struct device *dev, bool *enabled, - bool *permanent); +void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level); #endif -/* Flash extended operations */ -#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT) -int flash_stm32_ex_op_sector_wp(const struct device *dev, const uintptr_t in, - void *out); -#endif -#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION) -int flash_stm32_ex_op_rdp(const struct device *dev, const uintptr_t in, - void *out); +#if defined(CONFIG_FLASH_STM32_BLOCK_REGISTERS) +int flash_stm32_control_register_disable(const struct device *dev); +int flash_stm32_option_bytes_disable(const struct device *dev); #endif #endif /* ZEPHYR_DRIVERS_FLASH_FLASH_STM32_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/jesd216.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/jesd216.h index facd11a3..7395cfb3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/jesd216.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/jesd216.h @@ -129,6 +129,8 @@ static inline uint32_t jesd216_sfdp_magic(const struct jesd216_sfdp_header *hp) * the standard. Rather than pre-define layouts to access to all * potential fields this header provides functions for specific fields * known to be important, such as density and erase command support. + * + * Must be aligned to a DWORD (32-bit) address according to JESD216F. */ struct jesd216_bfp { uint32_t dw1; @@ -141,7 +143,7 @@ struct jesd216_bfp { uint32_t dw8; uint32_t dw9; uint32_t dw10[]; -} __packed; +} __aligned(4); /* Provide a few word-specific flags and bitfield ranges for values * that an application or driver might expect to want to extract. @@ -529,4 +531,15 @@ int jesd216_bfp_decode_dw16(const struct jesd216_param_header *php, const struct jesd216_bfp *bfp, struct jesd216_bfp_dw16 *res); +/* JESD216D-01 section 6.6: 4-Byte Address Instruction Parameter */ +#define JESD216_SFDP_4B_ADDR_DW1_1S_1S_1S_READ_13_SUP BIT(0) +#define JESD216_SFDP_4B_ADDR_DW1_1S_1S_1S_FAST_READ_0C_SUP BIT(1) +#define JESD216_SFDP_4B_ADDR_DW1_1S_1S_2_FAST_READ_3C_SUP BIT(2) +#define JESD216_SFDP_4B_ADDR_DW1_1S_2S_2S_FAST_READ_BC_SUP BIT(3) +#define JESD216_SFDP_4B_ADDR_DW1_1S_1S_4S_FAST_READ_6C_SUP BIT(4) +#define JESD216_SFDP_4B_ADDR_DW1_1S_4S_4_FAST_READ_EC_SUP BIT(5) +#define JESD216_SFDP_4B_ADDR_DW1_1S_1S_1S_PP_12_SUP BIT(6) +#define JESD216_SFDP_4B_ADDR_DW1_1S_1S_4S_PP_34_SUP BIT(7) +#define JESD216_SFDP_4B_ADDR_DW1_1S_4S_4S_PP_3E_SUP BIT(8) + #endif /* ZEPHYR_DRIVERS_FLASH_JESD216_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/spi_nor.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/spi_nor.h index 5f38c982..a918e0a9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/spi_nor.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/flash/spi_nor.h @@ -39,6 +39,7 @@ #define SPI_NOR_CMD_SE_4B 0x21 /* Sector erase 4 byte address*/ #define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */ #define SPI_NOR_CMD_BE 0xD8 /* Block erase */ +#define SPI_NOR_CMD_BE_4B 0xDC /* Block erase 4 byte address*/ #define SPI_NOR_CMD_CE 0xC7 /* Chip erase */ #define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */ #define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/fpga/fpga_ice40_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/fpga/fpga_ice40_common.h new file mode 100644 index 00000000..55faf0ee --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/fpga/fpga_ice40_common.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2022 Meta + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_FPGA_FPGA_ICE40_COMMON_H_ +#define ZEPHYR_SUBSYS_FPGA_FPGA_ICE40_COMMON_H_ + +#include +#include +#include +#include +#include +#include + +/* + * Values in Hz, intentionally to be comparable with the spi-max-frequency + * property from DT bindings in spi-device.yaml. + */ +#define FPGA_ICE40_SPI_HZ_MIN 1000000 +#define FPGA_ICE40_SPI_HZ_MAX 25000000 + +#define FPGA_ICE40_CRESET_DELAY_US_MIN 1 /* 200ns absolute minimum */ +#define FPGA_ICE40_CONFIG_DELAY_US_MIN 1200 +#define FPGA_ICE40_LEADING_CLOCKS_MIN 8 +#define FPGA_ICE40_TRAILING_CLOCKS_MIN 49 + +#define FPGA_ICE40_CONFIG_DEFINE(inst, derived_config_) \ + BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) >= FPGA_ICE40_SPI_HZ_MIN); \ + BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) <= FPGA_ICE40_SPI_HZ_MAX); \ + BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) >= FPGA_ICE40_CONFIG_DELAY_US_MIN); \ + BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) <= UINT16_MAX); \ + BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) >= FPGA_ICE40_CRESET_DELAY_US_MIN); \ + BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) <= UINT16_MAX); \ + BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) >= FPGA_ICE40_LEADING_CLOCKS_MIN); \ + BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) <= UINT8_MAX); \ + BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) >= FPGA_ICE40_TRAILING_CLOCKS_MIN); \ + BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) <= UINT8_MAX); \ + \ + static const struct fpga_ice40_config fpga_ice40_config_##inst = { \ + .bus = SPI_DT_SPEC_INST_GET(inst, \ + SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | \ + SPI_WORD_SET(8) | SPI_TRANSFER_MSB, \ + 0), \ + .creset = GPIO_DT_SPEC_INST_GET(inst, creset_gpios), \ + .cdone = GPIO_DT_SPEC_INST_GET(inst, cdone_gpios), \ + .config_delay_us = DT_INST_PROP(inst, config_delay_us), \ + .creset_delay_us = DT_INST_PROP(inst, creset_delay_us), \ + .leading_clocks = DT_INST_PROP(inst, leading_clocks), \ + .trailing_clocks = DT_INST_PROP(inst, trailing_clocks), \ + .derived_config = derived_config_, \ + } + +struct fpga_ice40_data { + uint32_t crc; + /* simply use crc32 as info */ + char info[2 * sizeof(uint32_t) + 1]; + bool on; + bool loaded; + struct k_spinlock lock; +}; + +struct fpga_ice40_config { + struct spi_dt_spec bus; + struct gpio_dt_spec cdone; + struct gpio_dt_spec creset; + uint16_t creset_delay_us; + uint16_t config_delay_us; + uint8_t leading_clocks; + uint8_t trailing_clocks; + const void *derived_config; +}; + +void fpga_ice40_crc_to_str(uint32_t crc, char *s); +enum FPGA_status fpga_ice40_get_status(const struct device *dev); +int fpga_ice40_on(const struct device *dev); +int fpga_ice40_off(const struct device *dev); +int fpga_ice40_reset(const struct device *dev); +const char *fpga_ice40_get_info(const struct device *dev); +int fpga_ice40_init(const struct device *dev); + +#endif /* ZEPHYR_SUBSYS_FPGA_FPGA_ICE40_COMMON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h index 870f3f48..977081a4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gnss/gnss_u_blox_protocol/gnss_u_blox_protocol_defines.h @@ -32,12 +32,12 @@ enum ubx_dynamic_model { UBX_DYN_MODEL_PORTABLE = 0, UBX_DYN_MODEL_STATIONARY = 2, UBX_DYN_MODEL_PEDESTRIAN = 3, - UBX_DYN_MODEL_AUTOMOTIV = 4, + UBX_DYN_MODEL_AUTOMOTIVE = 4, UBX_DYN_MODEL_SEA = 5, - UBX_DYN_MODEL_AIRBONE1G = 6, - UBX_DYN_MODEL_AIRBONE2G = 7, - UBX_DYN_MODEL_AIRBONE4G = 8, - UBX_DYN_MODEL_WIRST = 9, + UBX_DYN_MODEL_AIRBORNE1G = 6, + UBX_DYN_MODEL_AIRBORNE2G = 7, + UBX_DYN_MODEL_AIRBORNE4G = 8, + UBX_DYN_MODEL_WRIST = 9, UBX_DYN_MODEL_BIKE = 10, }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_grgpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_grgpio.h new file mode 100644 index 00000000..6a3958f7 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_grgpio.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2023 Frontgrade Gaisler AB + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_GRGPIO_H_ +#define ZEPHYR_DRIVERS_GPIO_GPIO_GRGPIO_H_ + +struct grgpio_regs { + uint32_t data; /* 0x00 I/O port data register */ + uint32_t output; /* 0x04 I/O port output register */ + uint32_t dir; /* 0x08 I/O port direction register */ + uint32_t imask; /* 0x0C Interrupt mask register */ + uint32_t ipol; /* 0x10 Interrupt polarity register */ + uint32_t iedge; /* 0x14 Interrupt edge register */ + uint32_t bypass; /* 0x18 Bypass register */ + uint32_t cap; /* 0x1C Capability register */ + uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ + uint32_t res_30; /* 0x30 Reserved */ + uint32_t res_34; /* 0x34 Reserved */ + uint32_t res_38; /* 0x38 Reserved */ + uint32_t res_3C; /* 0x3C Reserved */ + uint32_t iavail; /* 0x40 Interrupt available register */ + uint32_t iflag; /* 0x44 Interrupt flag register */ + uint32_t res_48; /* 0x48 Reserved */ + uint32_t pulse; /* 0x4C Pulse register */ + uint32_t res_50; /* 0x50 Reserved */ + uint32_t output_or; /* 0x54 I/O port output register, logical-OR */ + uint32_t dir_or; /* 0x58 I/O port dir. register, logical-OR */ + uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */ + uint32_t res_60; /* 0x60 Reserved */ + uint32_t output_and; /* 0x64 I/O port output register, logical-AND */ + uint32_t dir_and; /* 0x68 I/O port dir. register, logical-AND */ + uint32_t imask_and; /* 0x6C Interrupt mask register, logical-AND */ + uint32_t res_70; /* 0x70 Reserved */ + uint32_t output_xor; /* 0x74 I/O port output register, logical-XOR */ + uint32_t dir_xor; /* 0x78 I/O port dir. register, logical-XOR */ + uint32_t imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ +}; + +#define GRGPIO_CAP_PU_BIT 18 +#define GRGPIO_CAP_IER_BIT 17 +#define GRGPIO_CAP_IFL_BIT 16 +#define GRGPIO_CAP_IRQGEN_BIT 8 +#define GRGPIO_CAP_NLINES_BIT 0 + +#define GRGPIO_CAP_PU (0x1 << GRGPIO_CAP_PU_BIT) +#define GRGPIO_CAP_IER (0x1 << GRGPIO_CAP_IER_BIT) +#define GRGPIO_CAP_IFL (0x1 << GRGPIO_CAP_IFL_BIT) +#define GRGPIO_CAP_IRQGEN (0x1f << GRGPIO_CAP_IRQGEN_BIT) +#define GRGPIO_CAP_NLINES (0x1f << GRGPIO_CAP_NLINES_BIT) + +#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_GRGPIO_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max14906.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max14906.h new file mode 100644 index 00000000..647088f5 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max14906.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2024 Analog Devices Inc. + * Copyright (c) 2024 Baylibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MAX14906_H_ +#define ZEPHYR_DRIVERS_GPIO_GPIO_MAX14906_H_ + +#define MAX14906_FAULT2_ENABLES 5 +#define MAX14906_CHANNELS 4 +#define MAX14916_CHANNELS 8 +#define MAX149x6_MAX_PKT_SIZE 3 + +#define MAX14906_SETOUT_REG 0x0 +#define MAX14906_SETLED_REG 0x1 +#define MAX14906_DOILEVEL_REG 0x2 +#define MAX14906_INT_REG 0x3 +#define MAX14906_OVR_LD_REG 0x4 +#define MAX14906_OPN_WIR_FLT_REG 0x5 +#define MAX14906_SHT_VDD_FLT_REG 0x6 +#define MAX14906_GLOB_ERR_REG 0x7 +#define MAX14906_OPN_WR_EN_REG 0x8 +#define MAX14906_SHT_VDD_EN_REG 0x9 +#define MAX14906_CONFIG1_REG 0xA +#define MAX14906_CONFIG2_REG 0xB +#define MAX14906_CONFIG_DI_REG 0xC +#define MAX14906_CONFIG_DO_REG 0xD +#define MAX14906_CONFIG_CURR_LIM 0xE +#define MAX14906_CONFIG_MASK 0xF + +#define MAX149x6_CHIP_ADDR_MASK GENMASK(7, 6) +#define MAX149x6_ADDR_MASK GENMASK(4, 1) +#define MAX149x6_RW_MASK BIT(0) + +/* DoiLevel register */ +#define MAX14906_DOI_LEVEL_MASK(x) BIT(x) + +/* SetOUT register */ +#define MAX14906_HIGHO_MASK(x) BIT(x) + +#define MAX14906_DO_MASK(x) (GENMASK(1, 0) << (2 * (x))) +#define MAX14906_CH_DIR_MASK(x) BIT((x) + 4) +#define MAX14906_CH(x) (x) +#define MAX14906_IEC_TYPE_MASK BIT(7) +#define MAX14906_CL_MASK(x) (GENMASK(1, 0) << (2 * (x))) + +/** + * @brief Hardwired device address + */ +enum max149x6_spi_addr { + MAX14906_ADDR_0, /* A0=0, A1=0 */ + MAX14906_ADDR_1, /* A0=1, A1=0 */ + MAX14906_ADDR_2, /* A0=0, A1=1 */ + MAX14906_ADDR_3, /* A0=1, A1=1 */ +}; + +enum max14906_iec_type { + MAX14906_TYPE_1_3, + MAX14906_TYPE_2, +}; + +/** + * @brief Channel configuration options. + */ +enum max14906_function { + MAX14906_OUT, + MAX14906_IN, + MAX14906_HIGH_Z +}; + +/** + * @brief Configuration options for the output driver (on each channel). + */ +enum max14906_do_mode { + MAX14906_HIGH_SIDE, + MAX14906_HIGH_SIDE_INRUSH, + MAX14906_PUSH_PULL_CLAMP, + MAX14906_PUSH_PULL +}; + +/** + * @brief Current limit options for output channels. + */ +enum max14906_cl { + MAX14906_CL_600, + MAX14906_CL_130, + MAX14906_CL_300, + MAX14906_CL_1200, +}; + +union max14906_doi_level { + uint8_t reg_raw; + struct { + uint8_t VDDOK_FAULT1: 1; /* BIT0 */ + uint8_t VDDOK_FAULT2: 1; + uint8_t VDDOK_FAULT3: 1; + uint8_t VDDOK_FAULT4: 1; + uint8_t SAFE_DAMAGE_F1: 1; + uint8_t SAFE_DAMAGE_F2: 1; + uint8_t SAFE_DAMAGE_F3: 1; + uint8_t SAFE_DAMAGE_F4: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_interrupt { + uint8_t reg_raw; + struct { + uint8_t OVER_LD_FAULT: 1; /* BIT0 */ + uint8_t CURR_LIM: 1; + uint8_t OW_OFF_FAULT: 1; + uint8_t ABOVE_VDD_FAULT: 1; + uint8_t SHT_VDD_FAULT: 1; + uint8_t DE_MAG_FAULT: 1; + uint8_t SUPPLY_ERR: 1; + uint8_t COM_ERR: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_ovr_ld_chf { + uint8_t reg_raw; + struct { + uint8_t OVL1: 1; /* BIT0 */ + uint8_t OVL2: 1; + uint8_t OVL3: 1; + uint8_t OVL4: 1; + uint8_t CL1: 1; + uint8_t CL2: 1; + uint8_t CL3: 1; + uint8_t CL4: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_opn_wir_chf { + uint8_t reg_raw; + struct { + uint8_t OW_OFF1: 1; /* BIT0 */ + uint8_t OW_OFF2: 1; + uint8_t OW_OFF3: 1; + uint8_t OW_OFF4: 1; + uint8_t ABOVE_VDD1: 1; + uint8_t ABOVE_VDD2: 1; + uint8_t ABOVE_VDD3: 1; + uint8_t ABOVE_VDD4: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_sht_vdd_chf { + uint8_t reg_raw; + struct { + uint8_t SHVDD1: 1; /* BIT0 */ + uint8_t SHVDD2: 1; + uint8_t SHVDD3: 1; + uint8_t SHVDD4: 1; + uint8_t VDDOV1: 1; + uint8_t VDDOV2: 1; + uint8_t VDDOV3: 1; + uint8_t VDDOV4: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_global_err { + uint8_t reg_raw; + struct { + uint8_t VINT_UV: 1; /* BIT0 */ + uint8_t V5_UVLO: 1; + uint8_t VDD_LOW: 1; + uint8_t VDD_WARN: 1; + uint8_t VDD_UVLO: 1; + uint8_t THRMSHUTD: 1; + uint8_t LOSSGND: 1; + uint8_t WDOG_ERR: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_opn_wr_en { + uint8_t reg_raw; + struct { + uint8_t OW_OFF_EN1: 1; /* BIT0 */ + uint8_t OW_OFF_EN2: 1; + uint8_t OW_OFF_EN3: 1; + uint8_t OW_OFF_EN4: 1; + uint8_t GDRV_EN1: 1; + uint8_t GDRV_EN2: 1; + uint8_t GDRV_EN3: 1; + uint8_t GDRV_EN4: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_sht_vdd_en { + uint8_t reg_raw; + struct { + uint8_t SH_VDD_EN1: 1; /* BIT0 */ + uint8_t SH_VDD_EN2: 1; + uint8_t SH_VDD_EN3: 1; + uint8_t SH_VDD_EN4: 1; + uint8_t VDD_OV_EN1: 1; + uint8_t VDD_OV_EN2: 1; + uint8_t VDD_OV_EN3: 1; + uint8_t VDD_OV_EN4: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_config_di { + uint8_t reg_raw; + struct { + uint8_t OVL_BLANK: 2; /* BIT0 */ + uint8_t OVL_STRETCH_EN: 1; + uint8_t ABOVE_VDD_PROT_EN: 1; + uint8_t VDD_FAULT_SEL: 1; + uint8_t VDD_FAULT_DIS: 1; + uint8_t RESERVED: 1; + uint8_t TYP_2_DI: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_config_do { + uint8_t reg_raw; + struct { + uint8_t DO_MODE1: 2; /* BIT0 */ + uint8_t DO_MODE2: 2; + uint8_t DO_MODE3: 2; + uint8_t DO_MODE4: 2; /* BIT7 */ + } reg_bits; +}; + +union max14906_config_curr_lim { + uint8_t reg_raw; + struct { + uint8_t CL1: 2; /* BIT0 */ + uint8_t CL2: 2; + uint8_t CL3: 2; + uint8_t CL4: 2; /* BIT7 */ + } reg_bits; +}; + +union max14906_mask { + uint8_t reg_raw; + struct { + uint8_t OVER_LD_M: 1; /* BIT0 */ + uint8_t CURR_LIM_M: 1; + uint8_t OW_OFF_M: 1; + uint8_t ABOVE_VDD_M: 1; + uint8_t SHT_VDD_M: 1; + uint8_t VDD_OK_M: 1; + uint8_t SUPPLY_ERR_M: 1; + uint8_t COM_ERR_M: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_config1 { + uint8_t reg_raw; + struct { + uint8_t FLED_SET: 1; /* BIT0 */ + uint8_t SLED_SET: 1; + uint8_t FLED_STRETCH: 2; + uint8_t FFILTER_EN: 1; + uint8_t FILTER_LONG: 1; + uint8_t FLATCH_EN: 1; + uint8_t LED_CURR_LIM: 1; /* BIT7 */ + } reg_bits; +}; + +union max14906_config2 { + uint8_t reg_raw; + struct { + uint8_t VDD_ON_THR: 1; /* BIT0 */ + uint8_t SYNCH_WD_EN: 1; + uint8_t SHT_VDD_THR: 2; + uint8_t OW_OFF_CS: 2; + uint8_t WD_TO: 2; /* BIT7 */ + } reg_bits; +}; + +/* Config1 register Enable/Disable SLED */ +#define MAX149x6_SLED_MASK BIT(1) +/* Config1 register Enable/Disable FLED */ +#define MAX149x6_FLED_MASK BIT(0) + +#define MAX149x6_ENABLE 1 +#define MAX149x6_DISABLE 0 + +struct max149x6_config { + struct spi_dt_spec spi; + struct gpio_dt_spec fault_gpio; + struct gpio_dt_spec ready_gpio; + struct gpio_dt_spec sync_gpio; + struct gpio_dt_spec en_gpio; + bool crc_en; + union max14906_config1 config1; + union max14906_config2 config2; + union max14906_config_curr_lim curr_lim; + union max14906_config_di config_do; + union max14906_config_do config_di; + enum max149x6_spi_addr spi_addr; + uint8_t pkt_size; +}; + +#define max14906_config max149x6_config + +struct max14906_data { + struct gpio_driver_data common; + struct { + union max14906_doi_level doi_level; + union max14906_ovr_ld_chf ovr_ld; + union max14906_opn_wir_chf opn_wir; + union max14906_sht_vdd_chf sht_vdd; + } chan; + struct { + union max14906_opn_wr_en opn_wr_en; + union max14906_sht_vdd_en sht_vdd_en; + } chan_en; + struct { + union max14906_interrupt interrupt; + union max14906_global_err glob_err; + union max14906_mask mask; + } glob; +}; + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max14916.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max14916.h new file mode 100644 index 00000000..bcc842b2 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max14916.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2024 Analog Devices Inc. + * Copyright (c) 2024 Baylibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MAX14916_H_ +#define ZEPHYR_DRIVERS_GPIO_GPIO_MAX14916_H_ + +#define MAX14906_ENABLE 1 +#define MAX14906_DISABLE 0 + +#define MAX149x6_MAX_PKT_SIZE 3 + +#define MAX14916_CHANNELS 8 + +#define MAX14916_SETOUT_REG 0x0 +#define MAX14916_SET_FLED_REG 0x1 +#define MAX14916_SET_SLED_REG 0x2 +#define MAX14916_INT_REG 0x3 +#define MAX14916_OVR_LD_REG 0x4 +#define MAX14916_CURR_LIM_REG 0x5 +#define MAX14916_OW_OFF_FLT_REG 0x6 +#define MAX14916_OW_ON_FLT_REG 0x7 +#define MAX14916_SHT_VDD_FLT_REG 0x8 +#define MAX14916_GLOB_ERR_REG 0x9 +#define MAX14916_OW_OFF_EN_REG 0xA +#define MAX14916_OW_ON_EN_REG 0xB +#define MAX14916_SHT_VDD_EN_REG 0xC +#define MAX14916_CONFIG1_REG 0xD +#define MAX14916_CONFIG2_REG 0xE +#define MAX14916_CONFIG_MASK 0xF + +#define MAX149x6_CHIP_ADDR_MASK GENMASK(7, 6) +#define MAX149x6_ADDR_MASK GENMASK(4, 1) +#define MAX149x6_RW_MASK BIT(0) + +/* DoiLevel register */ +#define MAX149x6_DOI_LEVEL_MASK(x) BIT(x) + +/* SetOUT register */ +#define MAX14906_HIGHO_MASK(x) BIT(x) + +#define MAX14906_DO_MASK(x) (GENMASK(1, 0) << (2 * (x))) +#define MAX14906_CH_DIR_MASK(x) BIT((x) + 4) +#define MAX14906_CH(x) (x) +#define MAX14906_IEC_TYPE_MASK BIT(7) +#define MAX14906_CL_MASK(x) (GENMASK(1, 0) << (2 * (x))) + +/* Config1 register */ +#define MAX14906_SLED_MASK BIT(1) +#define MAX14906_FLED_MASK BIT(0) + +#define MAX14906_CHAN_MASK_LSB(x) BIT(x) +#define MAX14906_CHAN_MASK_MSB(x) BIT((x) + 4) + +enum max149x6_spi_addr { + MAX14906_ADDR_0, /* A0=0, A1=0 */ + MAX14906_ADDR_1, /* A0=1, A1=0 */ + MAX14906_ADDR_2, /* A0=0, A1=1 */ + MAX14906_ADDR_3, /* A0=1, A1=1 */ +}; + +enum max14916_fled_time { + MAX14916_FLED_TIME_DISABLED, + MAX14916_FLED_TIME_1S, + MAX14916_FLED_TIME_2S, + MAX14916_FLED_TIME_3S +}; + +enum max14916_sled_state { + MAX14916_SLED_OFF, + MAX14916_SLED_ON +}; + +enum max14916_wd { + MAX14916_WD_DISABLED, + MAX14916_WD_200MS, + MAX14916_WD_600MS, + MAX14916_WD_1200MS +}; + +enum max14916_ow_off_cs { + MAX14916_OW_OFF_CS_20UA, + MAX14916_OW_OFF_CS_100UA, + MAX14916_OW_OFF_CS_300UA, + MAX14916_OW_OFF_CS_600UA +}; + +enum max14916_sht_vdd_thr { + MAX14916_SHT_VDD_THR_9V, + MAX14916_SHT_VDD_THR_10V, + MAX14916_SHT_VDD_THR_12V, + MAX14916_SHT_VDD_THR_14V +}; + +union max14916_interrupt { + uint8_t reg_raw; + struct { + uint8_t OVER_LD_FLT: 1; /* BIT0 */ + uint8_t CURR_LIM: 1; + uint8_t OW_OFF_FLT: 1; + uint8_t OW_ON_FLT: 1; + uint8_t SHT_VDD_FLT: 1; + uint8_t DE_MAG_FLT: 1; + uint8_t SUPPLY_ERR: 1; + uint8_t COM_ERR: 1; /* BIT7 */ + } reg_bits; +}; + +union max14916_config1 { + uint8_t reg_raw; + struct { + uint8_t FLED_SET: 1; /* BIT0 */ + uint8_t SLED_SET: 1; + uint8_t FLED_STRETCH: 2; + uint8_t FFILTER_EN: 1; + uint8_t FILTER_LONG: 1; + uint8_t FLATCH_EN: 1; + uint8_t LED_CURR_LIM: 1; /* BIT7 */ + } reg_bits; +}; + +union max14916_config2 { + uint8_t reg_raw; + struct { + uint8_t VDD_ON_THR: 1; /* BIT0 */ + uint8_t SYNCH_WD_EN: 1; + uint8_t SHT_VDD_THR: 2; + uint8_t OW_OFF_CS: 2; + uint8_t WD_TO: 2; /* BIT7 */ + } reg_bits; +}; + +union max14916_mask { + uint8_t reg_raw; + struct { + uint8_t OVER_LD_M: 1; /* BIT0 */ + uint8_t CURR_LIM_M: 1; + uint8_t OW_OFF_M: 1; + uint8_t OW_ON_M: 1; + uint8_t SHT_VDD_M: 1; + uint8_t VDD_OK_M: 1; + uint8_t SUPPLY_ERR_M: 1; + uint8_t COM_ERR_M: 1; /* BIT7 */ + } reg_bits; +}; + +union max14916_global_err { + uint8_t reg_raw; + struct { + uint8_t VINT_UV: 1; /* BIT0 */ + uint8_t VA_UVLO: 1; + uint8_t VDD_BAD: 1; + uint8_t VDD_WARN: 1; + uint8_t VDD_UVLO: 1; + uint8_t THRMSHUTD: 1; + uint8_t SYNC_ERR: 1; + uint8_t WDOG_ERR: 1; /* BIT7 */ + } reg_bits; +}; + +struct max149x6_config { + struct spi_dt_spec spi; + struct gpio_dt_spec fault_gpio; + struct gpio_dt_spec ready_gpio; + struct gpio_dt_spec sync_gpio; + struct gpio_dt_spec en_gpio; + bool crc_en; + union max14916_config1 config1; + union max14916_config2 config2; + enum max149x6_spi_addr spi_addr; + uint8_t pkt_size; +}; + +#define max14916_config max149x6_config + +struct max14916_data { + struct gpio_driver_data common; + struct { + uint8_t ovr_ld; + uint8_t curr_lim; + uint8_t ow_off; + uint8_t ow_on; + uint8_t sht_vdd; + } chan; + struct { + uint8_t ow_off_en; + uint8_t ow_on_en; + uint8_t sht_vdd_en; + } chan_en; + struct { + union max14916_interrupt interrupt; + union max14916_global_err glob_err; + union max14916_mask mask; + } glob; +}; + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max149x6.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max149x6.h new file mode 100644 index 00000000..3266a219 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_max149x6.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2024 Analog Devices Inc. + * Copyright (c) 2024 Baylibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MAX149X6_H_ +#define ZEPHYR_DRIVERS_GPIO_GPIO_MAX149X6_H_ + +#define MAX149x6_READ 0 +#define MAX149x6_WRITE 1 + +#define MAX149X6_GET_BIT(val, i) (0x1 & ((val) >> (i))) +#define PRINT_ERR_BIT(bit1, bit2) \ + if ((bit1) & (bit2)) \ + LOG_ERR("[%s] %d", #bit1, bit1) +#define PRINT_ERR(bit) \ + if (bit) \ + LOG_ERR("[DIAG] [%s] %d\n", #bit, bit) +#define PRINT_INF(bit) LOG_INFO("[%s] %d\n", #bit, bit) +#define LOG_DIAG(...) Z_LOG(LOG_LEVEL_ERR, __VA_ARGS__) + +/** + * @brief Compute the CRC5 value for an array of bytes when writing to MAX149X6 + * @param data - array of data to encode + * @param encode - action to be performed - true(encode), false(decode) + * @return the resulted CRC5 + */ +static uint8_t max149x6_crc(uint8_t *data, bool encode) +{ + uint8_t crc5_start = 0x1f; + uint8_t crc5_poly = 0x15; + uint8_t crc5_result = crc5_start; + uint8_t extra_byte = 0x00; + uint8_t data_bit; + uint8_t result_bit; + int i; + + /* + * This is a custom implementation of a CRC5 algorithm, detailed here: + * https://www.analog.com/en/app-notes/how-to-program-the-max14906-quadchannel- + * industrial-digital-output-digital-input.html + */ + + for (i = (encode) ? 0 : 2; i < 8; i++) { + data_bit = (data[0] >> (7 - i)) & 0x01; + result_bit = (crc5_result & 0x10) >> 4; + if (data_bit ^ result_bit) { + crc5_result = crc5_poly ^ ((crc5_result << 1) & 0x1f); + } else { + crc5_result = (crc5_result << 1) & 0x1f; + } + } + + for (i = 0; i < 8; i++) { + data_bit = (data[1] >> (7 - i)) & 0x01; + result_bit = (crc5_result & 0x10) >> 4; + if (data_bit ^ result_bit) { + crc5_result = crc5_poly ^ ((crc5_result << 1) & 0x1f); + } else { + crc5_result = (crc5_result << 1) & 0x1f; + } + } + + for (i = 0; i < 3; i++) { + data_bit = (extra_byte >> (7 - i)) & 0x01; + result_bit = (crc5_result & 0x10) >> 4; + if (data_bit ^ result_bit) { + crc5_result = crc5_poly ^ ((crc5_result << 1) & 0x1f); + } else { + crc5_result = (crc5_result << 1) & 0x1f; + } + } + + return crc5_result; +} + +/* + * @brief Register read/write function for MAX149x6 + * + * @param dev - MAX149x6 device config. + * @param addr - Register value to which data is written. + * @param val - Value which is to be written to requested register. + * @return 0 in case of success, negative error code otherwise. + */ +static int max149x6_reg_transceive(const struct device *dev, uint8_t addr, uint8_t val, + uint8_t *rx_diag_buff, uint8_t rw) +{ + uint8_t crc; + int ret; + + uint8_t local_rx_buff[MAX149x6_MAX_PKT_SIZE] = {0}; + uint8_t local_tx_buff[MAX149x6_MAX_PKT_SIZE] = {0}; + + const struct max149x6_config *config = dev->config; + + struct spi_buf tx_buf = { + .buf = &local_tx_buff, + .len = config->pkt_size, + }; + const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1}; + + struct spi_buf rx_buf = { + .buf = &local_rx_buff, + .len = config->pkt_size, + }; + const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1}; + + if (config->crc_en & 0) { + rx_buf.len++; + } + + local_tx_buff[0] = FIELD_PREP(MAX149x6_ADDR_MASK, addr) | + FIELD_PREP(MAX149x6_CHIP_ADDR_MASK, config->spi_addr) | + FIELD_PREP(MAX149x6_RW_MASK, rw & 0x1); + local_tx_buff[1] = val; + + /* If CRC enabled calculate it */ + if (config->crc_en) { + local_tx_buff[2] = max149x6_crc(&local_tx_buff[0], true); + } + + /* write cmd & read resp at once */ + ret = spi_transceive_dt(&config->spi, &tx, &rx); + + if (ret) { + LOG_ERR("Err spi_transcieve_dt [%d]\n", ret); + return ret; + } + + /* if CRC enabled check readed */ + if (config->crc_en) { + crc = max149x6_crc(&local_rx_buff[0], false); + if (crc != (local_rx_buff[2] & 0x1F)) { + LOG_ERR("READ CRC ERR (%d)-(%d)\n", crc, (local_rx_buff[2] & 0x1F)); + return -EINVAL; + } + } + + if (rx_diag_buff != NULL) { + rx_diag_buff[0] = local_rx_buff[0]; + } + + /* In case of write we are getting 2 diagnostic bytes - byte0 & byte1 + * and pass them to diag buffer to be parsed in next stage + */ + if ((MAX149x6_WRITE == rw) && (rx_diag_buff != NULL)) { + rx_diag_buff[1] = local_rx_buff[1]; + } else { + ret = local_rx_buff[1]; + } + + return ret; +} + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_mcp23xxx.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_mcp23xxx.h index b741cc95..4be6378d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_mcp23xxx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_mcp23xxx.h @@ -61,6 +61,7 @@ struct mcp23xxx_config { struct gpio_dt_spec gpio_reset; uint8_t ngpios; + bool is_open_drain; mcp23xxx_read_port_regs read_fn; mcp23xxx_write_port_regs write_fn; mcp23xxx_bus_is_ready bus_fn; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_renesas_rz.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_renesas_rz.h new file mode 100644 index 00000000..6980450f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_renesas_rz.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ +#define ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ + +#include +#include "r_ioport.h" + +#define GPIO_RZ_IOPORT_P_REG_BASE_GET (&R_GPIO->P_20) +#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20) + +#define GPIO_RZ_REG_OFFSET(port, pin) (port + (pin / 4)) + +#define GPIO_RZ_P_VALUE_GET(value, pin) ((value >> pin) & 1U) +#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U) + +#define GPIO_RZ_MAX_PORT_NUM 19 +#define GPIO_RZ_MAX_TINT_NUM 32 + +#define GPIO_RZ_TINT_IRQ_OFFSET 429 +#define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET) + +#define GPIO_RZ_TINT_EDGE_RISING 0x0 +#define GPIO_RZ_TINT_EDGE_FALLING 0x1 +#define GPIO_RZ_TINT_LEVEL_HIGH 0x2 +#define GPIO_RZ_TINT_LEVEL_LOW 0x3 + +#define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin)) +#define GPIO_RZ_TSSR_OFFSET(irq) ((irq % 4) * 8) +#define GPIO_RZ_TITSR_OFFSET(irq) ((irq % 16) * 2) + +#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZG3S_GPIO_FILTER_SHIFT) & 0x1F) << 19U) +#define GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flag) \ + (((flag >> RZG3S_GPIO_IOLH_SHIFT) & 0x3) << 10U) + +#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE IOPORT_CFG_TINT_ENABLE +#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE (~(IOPORT_CFG_TINT_ENABLE)) +#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2)) + +static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0, 4, 9, 13, 17, 23, 28, 33, 38, 43, + 47, 52, 56, 58, 63, 66, 70, 72, 76}; +#endif /* ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_rt1718s.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_rt1718s.h index 3a1c9897..faba3cdb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_rt1718s.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_rt1718s.h @@ -155,8 +155,9 @@ static inline int rt1718s_reg_burst_write(const struct device *dev, uint8_t star static inline int rt1718s_reg_update(const struct device *dev, uint8_t reg_addr, uint8_t reg_val, uint8_t new_val) { - if (reg_val == new_val) + if (reg_val == new_val) { return 0; + } return rt1718s_reg_write_byte(dev, reg_addr, new_val); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_stm32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_stm32.h index 9aa83a54..65b6bcc9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_stm32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/gpio/gpio_stm32.h @@ -259,6 +259,8 @@ struct gpio_stm32_data { const struct device *dev; /* user ISR cb */ sys_slist_t cb; + /* keep track of pins that are connected and need GPIO clock to be enabled */ + uint32_t pin_has_clock_enabled; }; /** @@ -271,6 +273,6 @@ struct gpio_stm32_data { * * @return 0 on success, negative errno code on failure */ -int gpio_stm32_configure(const struct device *dev, int pin, int conf, int func); +int gpio_stm32_configure(const struct device *dev, gpio_pin_t pin, uint32_t conf, uint32_t func); #endif /* ZEPHYR_DRIVERS_GPIO_GPIO_STM32_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw.h index c25246bb..004cbb0a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw.h @@ -26,73 +26,64 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE"); extern "C" { #endif -#define I2C_DW_MAGIC_KEY 0x44570140 - +#define I2C_DW_MAGIC_KEY 0x44570140 typedef void (*i2c_isr_cb_t)(const struct device *port); - -#define IC_ACTIVITY (1 << 0) -#define IC_ENABLE_BIT (1 << 0) - +#define IC_ACTIVITY (1 << 0) +#define IC_ENABLE_BIT (1 << 0) /* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */ -#define I2C_DW_STATE_READY (0) -#define I2C_DW_CMD_SEND (1 << 0) -#define I2C_DW_CMD_RECV (1 << 1) -#define I2C_DW_CMD_ERROR (1 << 2) -#define I2C_DW_BUSY (1 << 3) - +#define I2C_DW_STATE_READY (0) +#define I2C_DW_CMD_SEND (1 << 0) +#define I2C_DW_CMD_RECV (1 << 1) +#define I2C_DW_CMD_ERROR (1 << 2) +#define I2C_DW_BUSY (1 << 3) -#define DW_ENABLE_TX_INT_I2C_MASTER (DW_INTR_STAT_TX_OVER | \ - DW_INTR_STAT_TX_EMPTY | \ - DW_INTR_STAT_TX_ABRT | \ - DW_INTR_STAT_STOP_DET) -#define DW_ENABLE_RX_INT_I2C_MASTER (DW_INTR_STAT_RX_UNDER | \ - DW_INTR_STAT_RX_OVER | \ - DW_INTR_STAT_RX_FULL | \ - DW_INTR_STAT_STOP_DET) +#define DW_ENABLE_TX_INT_I2C_MASTER \ + (DW_INTR_STAT_TX_OVER | DW_INTR_STAT_TX_EMPTY | DW_INTR_STAT_TX_ABRT | \ + DW_INTR_STAT_STOP_DET) +#define DW_ENABLE_RX_INT_I2C_MASTER \ + (DW_INTR_STAT_RX_UNDER | DW_INTR_STAT_RX_OVER | DW_INTR_STAT_RX_FULL | \ + DW_INTR_STAT_STOP_DET) -#define DW_ENABLE_TX_INT_I2C_SLAVE (DW_INTR_STAT_RD_REQ | \ - DW_INTR_STAT_TX_ABRT | \ - DW_INTR_STAT_STOP_DET) -#define DW_ENABLE_RX_INT_I2C_SLAVE (DW_INTR_STAT_RX_FULL | \ - DW_INTR_STAT_STOP_DET) - -#define DW_DISABLE_ALL_I2C_INT 0x00000000 +#define DW_ENABLE_TX_INT_I2C_SLAVE \ + (DW_INTR_STAT_RD_REQ | DW_INTR_STAT_TX_ABRT | DW_INTR_STAT_STOP_DET) +#define DW_ENABLE_RX_INT_I2C_SLAVE (DW_INTR_STAT_RX_FULL | DW_INTR_STAT_STOP_DET) +#define DW_DISABLE_ALL_I2C_INT 0x00000000 /* IC_CON Low count and high count default values */ -/* TODO verify values for high and fast speed */ -#define I2C_STD_HCNT (CONFIG_I2C_DW_CLOCK_SPEED * 4) -#define I2C_STD_LCNT (CONFIG_I2C_DW_CLOCK_SPEED * 5) -#define I2C_FS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) -#define I2C_FS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) -#define I2C_HS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) -#define I2C_HS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) +/* TODO verify values for high speed */ +#define I2C_STD_HCNT (CONFIG_I2C_DW_CLOCK_SPEED * 4) +#define I2C_STD_LCNT (CONFIG_I2C_DW_CLOCK_SPEED * 5) +#define I2C_FS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) +#define I2C_FS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) +#define I2C_FSP_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 2) / 8) +#define I2C_FSP_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 2) / 8) +#define I2C_HS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) +#define I2C_HS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) /* * DesignWare speed values don't directly translate from the Zephyr speed * selections in include/i2c.h so here we do a little translation */ -#define I2C_DW_SPEED_STANDARD 0x1 -#define I2C_DW_SPEED_FAST 0x2 -#define I2C_DW_SPEED_FAST_PLUS 0x2 -#define I2C_DW_SPEED_HIGH 0x3 - +#define I2C_DW_SPEED_STANDARD 0x1 +#define I2C_DW_SPEED_FAST 0x2 +#define I2C_DW_SPEED_FAST_PLUS 0x2 +#define I2C_DW_SPEED_HIGH 0x3 /* * These values have been randomly selected. It would be good to test different * watermark levels for performance capabilities */ -#define I2C_DW_TX_WATERMARK 2 -#define I2C_DW_RX_WATERMARK 7 - +#define I2C_DW_TX_WATERMARK 2 +#define I2C_DW_RX_WATERMARK 7 struct i2c_dw_rom_config { DEVICE_MMIO_ROM; - i2c_isr_cb_t config_func; - uint32_t bitrate; + i2c_isr_cb_t config_func; + uint32_t bitrate; #if defined(CONFIG_PINCTRL) const struct pinctrl_dev_config *pcfg; @@ -112,21 +103,21 @@ struct i2c_dw_rom_config { struct i2c_dw_dev_config { DEVICE_MMIO_RAM; - struct k_sem device_sync_sem; - struct k_mutex bus_mutex; + struct k_sem device_sync_sem; + struct k_mutex bus_mutex; uint32_t app_config; - uint8_t *xfr_buf; - uint32_t xfr_len; - uint32_t rx_pending; + uint8_t *xfr_buf; + uint32_t xfr_len; + uint32_t rx_pending; - uint16_t hcnt; - uint16_t lcnt; + uint16_t hcnt; + uint16_t lcnt; - volatile uint8_t state; /* last direction of transfer */ - uint8_t request_bytes; - uint8_t xfr_flags; - bool support_hs_mode; + volatile uint8_t state; /* last direction of transfer */ + uint8_t request_bytes; + uint8_t xfr_flags; + bool support_hs_mode; #ifdef CONFIG_I2C_DW_LPSS_DMA uintptr_t phy_addr; uintptr_t base_addr; @@ -137,39 +128,39 @@ struct i2c_dw_dev_config { struct i2c_target_config *slave_cfg; }; -#define Z_REG_READ(__sz) sys_read##__sz +#define Z_REG_READ(__sz) sys_read##__sz #define Z_REG_WRITE(__sz) sys_write##__sz -#define Z_REG_SET_BIT sys_set_bit -#define Z_REG_CLEAR_BIT sys_clear_bit -#define Z_REG_TEST_BIT sys_test_bit - -#define DEFINE_MM_REG_READ(__reg, __off, __sz) \ - static inline uint32_t read_##__reg(uint32_t addr) \ - { \ - return Z_REG_READ(__sz)(addr + __off); \ +#define Z_REG_SET_BIT sys_set_bit +#define Z_REG_CLEAR_BIT sys_clear_bit +#define Z_REG_TEST_BIT sys_test_bit + +#define DEFINE_MM_REG_READ(__reg, __off, __sz) \ + static inline uint32_t read_##__reg(uint32_t addr) \ + { \ + return Z_REG_READ(__sz)(addr + __off); \ } -#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \ - static inline void write_##__reg(uint32_t data, uint32_t addr) \ - { \ - Z_REG_WRITE(__sz)(data, addr + __off); \ +#define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \ + static inline void write_##__reg(uint32_t data, uint32_t addr) \ + { \ + Z_REG_WRITE(__sz)(data, addr + __off); \ } -#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \ - static inline void set_bit_##__reg_bit(uint32_t addr) \ - { \ - Z_REG_SET_BIT(addr + __reg_off, __bit); \ +#define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \ + static inline void set_bit_##__reg_bit(uint32_t addr) \ + { \ + Z_REG_SET_BIT(addr + __reg_off, __bit); \ } -#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \ - static inline void clear_bit_##__reg_bit(uint32_t addr) \ - { \ - Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \ +#define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \ + static inline void clear_bit_##__reg_bit(uint32_t addr) \ + { \ + Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \ } -#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \ - static inline int test_bit_##__reg_bit(uint32_t addr) \ - { \ - return Z_REG_TEST_BIT(addr + __reg_off, __bit); \ +#define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \ + static inline int test_bit_##__reg_bit(uint32_t addr) \ + { \ + return Z_REG_TEST_BIT(addr + __reg_off, __bit); \ } #ifdef __cplusplus diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw_registers.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw_registers.h index 6b2a11df..117fcb19 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw_registers.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_dw_registers.h @@ -14,154 +14,154 @@ extern "C" { /* IC_CON bits */ union ic_con_register { - uint32_t raw; + uint32_t raw; struct { - uint32_t master_mode : 1 __packed; - uint32_t speed : 2 __packed; - uint32_t addr_slave_10bit : 1 __packed; - uint32_t addr_master_10bit : 1 __packed; - uint32_t restart_en : 1 __packed; - uint32_t slave_disable : 1 __packed; - uint32_t stop_det : 1 __packed; - uint32_t tx_empty_ctl : 1 __packed; - uint32_t rx_fifo_full : 1 __packed; + uint32_t master_mode: 1 __packed; + uint32_t speed: 2 __packed; + uint32_t addr_slave_10bit: 1 __packed; + uint32_t addr_master_10bit: 1 __packed; + uint32_t restart_en: 1 __packed; + uint32_t slave_disable: 1 __packed; + uint32_t stop_det: 1 __packed; + uint32_t tx_empty_ctl: 1 __packed; + uint32_t rx_fifo_full: 1 __packed; } bits; }; /* IC_DATA_CMD bits */ -#define IC_DATA_CMD_DAT_MASK 0xFF -#define IC_DATA_CMD_CMD BIT(8) -#define IC_DATA_CMD_STOP BIT(9) -#define IC_DATA_CMD_RESTART BIT(10) +#define IC_DATA_CMD_DAT_MASK 0xFF +#define IC_DATA_CMD_CMD BIT(8) +#define IC_DATA_CMD_STOP BIT(9) +#define IC_DATA_CMD_RESTART BIT(10) /* DesignWare Interrupt bits positions */ -#define DW_INTR_STAT_RX_UNDER BIT(0) -#define DW_INTR_STAT_RX_OVER BIT(1) -#define DW_INTR_STAT_RX_FULL BIT(2) -#define DW_INTR_STAT_TX_OVER BIT(3) -#define DW_INTR_STAT_TX_EMPTY BIT(4) -#define DW_INTR_STAT_RD_REQ BIT(5) -#define DW_INTR_STAT_TX_ABRT BIT(6) -#define DW_INTR_STAT_RX_DONE BIT(7) -#define DW_INTR_STAT_ACTIVITY BIT(8) -#define DW_INTR_STAT_STOP_DET BIT(9) -#define DW_INTR_STAT_START_DET BIT(10) -#define DW_INTR_STAT_GEN_CALL BIT(11) -#define DW_INTR_STAT_RESTART_DET BIT(12) -#define DW_INTR_STAT_MST_ON_HOLD BIT(13) - -#define DW_INTR_MASK_RX_UNDER BIT(0) -#define DW_INTR_MASK_RX_OVER BIT(1) -#define DW_INTR_MASK_RX_FULL BIT(2) -#define DW_INTR_MASK_TX_OVER BIT(3) -#define DW_INTR_MASK_TX_EMPTY BIT(4) -#define DW_INTR_MASK_RD_REQ BIT(5) -#define DW_INTR_MASK_TX_ABRT BIT(6) -#define DW_INTR_MASK_RX_DONE BIT(7) -#define DW_INTR_MASK_ACTIVITY BIT(8) -#define DW_INTR_MASK_STOP_DET BIT(9) -#define DW_INTR_MASK_START_DET BIT(10) -#define DW_INTR_MASK_GEN_CALL BIT(11) -#define DW_INTR_MASK_RESTART_DET BIT(12) -#define DW_INTR_MASK_MST_ON_HOLD BIT(13) -#define DW_INTR_MASK_RESET 0x000008ff +#define DW_INTR_STAT_RX_UNDER BIT(0) +#define DW_INTR_STAT_RX_OVER BIT(1) +#define DW_INTR_STAT_RX_FULL BIT(2) +#define DW_INTR_STAT_TX_OVER BIT(3) +#define DW_INTR_STAT_TX_EMPTY BIT(4) +#define DW_INTR_STAT_RD_REQ BIT(5) +#define DW_INTR_STAT_TX_ABRT BIT(6) +#define DW_INTR_STAT_RX_DONE BIT(7) +#define DW_INTR_STAT_ACTIVITY BIT(8) +#define DW_INTR_STAT_STOP_DET BIT(9) +#define DW_INTR_STAT_START_DET BIT(10) +#define DW_INTR_STAT_GEN_CALL BIT(11) +#define DW_INTR_STAT_RESTART_DET BIT(12) +#define DW_INTR_STAT_MST_ON_HOLD BIT(13) + +#define DW_INTR_MASK_RX_UNDER BIT(0) +#define DW_INTR_MASK_RX_OVER BIT(1) +#define DW_INTR_MASK_RX_FULL BIT(2) +#define DW_INTR_MASK_TX_OVER BIT(3) +#define DW_INTR_MASK_TX_EMPTY BIT(4) +#define DW_INTR_MASK_RD_REQ BIT(5) +#define DW_INTR_MASK_TX_ABRT BIT(6) +#define DW_INTR_MASK_RX_DONE BIT(7) +#define DW_INTR_MASK_ACTIVITY BIT(8) +#define DW_INTR_MASK_STOP_DET BIT(9) +#define DW_INTR_MASK_START_DET BIT(10) +#define DW_INTR_MASK_GEN_CALL BIT(11) +#define DW_INTR_MASK_RESTART_DET BIT(12) +#define DW_INTR_MASK_MST_ON_HOLD BIT(13) +#define DW_INTR_MASK_RESET 0x000008ff union ic_interrupt_register { - uint32_t raw; + uint32_t raw; struct { - uint32_t rx_under : 1 __packed; - uint32_t rx_over : 1 __packed; - uint32_t rx_full : 1 __packed; - uint32_t tx_over : 1 __packed; - uint32_t tx_empty : 1 __packed; - uint32_t rd_req : 1 __packed; - uint32_t tx_abrt : 1 __packed; - uint32_t rx_done : 1 __packed; - uint32_t activity : 1 __packed; - uint32_t stop_det : 1 __packed; - uint32_t start_det : 1 __packed; - uint32_t gen_call : 1 __packed; - uint32_t restart_det : 1 __packed; - uint32_t mst_on_hold : 1 __packed; - uint32_t reserved : 2 __packed; + uint32_t rx_under: 1 __packed; + uint32_t rx_over: 1 __packed; + uint32_t rx_full: 1 __packed; + uint32_t tx_over: 1 __packed; + uint32_t tx_empty: 1 __packed; + uint32_t rd_req: 1 __packed; + uint32_t tx_abrt: 1 __packed; + uint32_t rx_done: 1 __packed; + uint32_t activity: 1 __packed; + uint32_t stop_det: 1 __packed; + uint32_t start_det: 1 __packed; + uint32_t gen_call: 1 __packed; + uint32_t restart_det: 1 __packed; + uint32_t mst_on_hold: 1 __packed; + uint32_t reserved: 2 __packed; } bits; }; /* IC_TAR */ union ic_tar_register { - uint32_t raw; + uint32_t raw; struct { - uint32_t ic_tar : 10 __packed; - uint32_t gc_or_start : 1 __packed; - uint32_t special : 1 __packed; - uint32_t ic_10bitaddr_master : 1 __packed; - uint32_t reserved : 3 __packed; + uint32_t ic_tar: 10 __packed; + uint32_t gc_or_start: 1 __packed; + uint32_t special: 1 __packed; + uint32_t ic_10bitaddr_master: 1 __packed; + uint32_t reserved: 3 __packed; } bits; }; /* IC_COMP_PARAM_1 */ union ic_comp_param_1_register { - uint32_t raw; + uint32_t raw; struct { - uint32_t apb_data_width : 2 __packed; - uint32_t max_speed_mode : 2 __packed; - uint32_t hc_count_values : 1 __packed; - uint32_t intr_io : 1 __packed; - uint32_t has_dma : 1 __packed; - uint32_t add_encoded_params : 1 __packed; - uint32_t rx_buffer_depth : 8 __packed; - uint32_t tx_buffer_depth : 8 __packed; - uint32_t reserved : 7 __packed; + uint32_t apb_data_width: 2 __packed; + uint32_t max_speed_mode: 2 __packed; + uint32_t hc_count_values: 1 __packed; + uint32_t intr_io: 1 __packed; + uint32_t has_dma: 1 __packed; + uint32_t add_encoded_params: 1 __packed; + uint32_t rx_buffer_depth: 8 __packed; + uint32_t tx_buffer_depth: 8 __packed; + uint32_t reserved: 7 __packed; } bits; }; -#define DW_IC_REG_CON (0x00) -#define DW_IC_REG_TAR (0x04) -#define DW_IC_REG_SAR (0x08) -#define DW_IC_REG_DATA_CMD (0x10) -#define DW_IC_REG_SS_SCL_HCNT (0x14) -#define DW_IC_REG_SS_SCL_LCNT (0x18) -#define DW_IC_REG_FS_SCL_HCNT (0x1C) -#define DW_IC_REG_FS_SCL_LCNT (0x20) -#define DW_IC_REG_HS_SCL_HCNT (0x24) -#define DW_IC_REG_HS_SCL_LCNT (0x28) -#define DW_IC_REG_INTR_STAT (0x2C) -#define DW_IC_REG_INTR_MASK (0x30) -#define DW_IC_REG_RX_TL (0x38) -#define DW_IC_REG_TX_TL (0x3C) -#define DW_IC_REG_CLR_INTR (0x40) -#define DW_IC_REG_CLR_RX_UNDER (0x44) -#define DW_IC_REG_CLR_RX_OVER (0x48) -#define DW_IC_REG_CLR_TX_OVER (0x4c) -#define DW_IC_REG_CLR_RD_REQ (0x50) -#define DW_IC_REG_CLR_TX_ABRT (0x54) -#define DW_IC_REG_CLR_RX_DONE (0x58) -#define DW_IC_REG_CLR_ACTIVITY (0x5c) -#define DW_IC_REG_CLR_STOP_DET (0x60) -#define DW_IC_REG_CLR_START_DET (0x64) -#define DW_IC_REG_CLR_GEN_CALL (0x68) -#define DW_IC_REG_ENABLE (0x6C) -#define DW_IC_REG_STATUS (0x70) -#define DW_IC_REG_TXFLR (0x74) -#define DW_IC_REG_RXFLR (0x78) -#define DW_IC_REG_DMA_CR (0x88) -#define DW_IC_REG_TDLR (0x8C) -#define DW_IC_REG_RDLR (0x90) -#define DW_IC_REG_FS_SPKLEN (0xA0) -#define DW_IC_REG_HS_SPKLEN (0xA4) -#define DW_IC_REG_COMP_PARAM_1 (0xF4) -#define DW_IC_REG_COMP_TYPE (0xFC) - -#define IDMA_REG_INTR_STS 0xAE8 -#define IDMA_TX_RX_CHAN_MASK 0x3 +#define DW_IC_REG_CON (0x00) +#define DW_IC_REG_TAR (0x04) +#define DW_IC_REG_SAR (0x08) +#define DW_IC_REG_DATA_CMD (0x10) +#define DW_IC_REG_SS_SCL_HCNT (0x14) +#define DW_IC_REG_SS_SCL_LCNT (0x18) +#define DW_IC_REG_FS_SCL_HCNT (0x1C) +#define DW_IC_REG_FS_SCL_LCNT (0x20) +#define DW_IC_REG_HS_SCL_HCNT (0x24) +#define DW_IC_REG_HS_SCL_LCNT (0x28) +#define DW_IC_REG_INTR_STAT (0x2C) +#define DW_IC_REG_INTR_MASK (0x30) +#define DW_IC_REG_RX_TL (0x38) +#define DW_IC_REG_TX_TL (0x3C) +#define DW_IC_REG_CLR_INTR (0x40) +#define DW_IC_REG_CLR_RX_UNDER (0x44) +#define DW_IC_REG_CLR_RX_OVER (0x48) +#define DW_IC_REG_CLR_TX_OVER (0x4c) +#define DW_IC_REG_CLR_RD_REQ (0x50) +#define DW_IC_REG_CLR_TX_ABRT (0x54) +#define DW_IC_REG_CLR_RX_DONE (0x58) +#define DW_IC_REG_CLR_ACTIVITY (0x5c) +#define DW_IC_REG_CLR_STOP_DET (0x60) +#define DW_IC_REG_CLR_START_DET (0x64) +#define DW_IC_REG_CLR_GEN_CALL (0x68) +#define DW_IC_REG_ENABLE (0x6C) +#define DW_IC_REG_STATUS (0x70) +#define DW_IC_REG_TXFLR (0x74) +#define DW_IC_REG_RXFLR (0x78) +#define DW_IC_REG_DMA_CR (0x88) +#define DW_IC_REG_TDLR (0x8C) +#define DW_IC_REG_RDLR (0x90) +#define DW_IC_REG_FS_SPKLEN (0xA0) +#define DW_IC_REG_HS_SPKLEN (0xA4) +#define DW_IC_REG_COMP_PARAM_1 (0xF4) +#define DW_IC_REG_COMP_TYPE (0xFC) + +#define IDMA_REG_INTR_STS 0xAE8 +#define IDMA_TX_RX_CHAN_MASK 0x3 /* CON Bit */ -#define DW_IC_CON_MASTER_MODE_BIT (0) +#define DW_IC_CON_MASTER_MODE_BIT (0) /* DMA control bits */ -#define DW_IC_DMA_RX_ENABLE BIT(0) -#define DW_IC_DMA_TX_ENABLE BIT(1) -#define DW_IC_DMA_ENABLE (BIT(0) | BIT(1)) +#define DW_IC_DMA_RX_ENABLE BIT(0) +#define DW_IC_DMA_TX_ENABLE BIT(1) +#define DW_IC_DMA_ENABLE (BIT(0) | BIT(1)) DEFINE_TEST_BIT_OP(con_master_mode, DW_IC_REG_CON, DW_IC_CON_MASTER_MODE_BIT) DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32) @@ -179,14 +179,12 @@ DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32) DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32) DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32) - - DEFINE_MM_REG_READ(intr_stat, DW_IC_REG_INTR_STAT, 32) -#define DW_IC_INTR_STAT_TX_ABRT_BIT (6) +#define DW_IC_INTR_STAT_TX_ABRT_BIT (6) DEFINE_TEST_BIT_OP(intr_stat_tx_abrt, DW_IC_REG_INTR_STAT, DW_IC_INTR_STAT_TX_ABRT_BIT) DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32) -#define DW_IC_INTR_MASK_TX_EMPTY_BIT (4) +#define DW_IC_INTR_MASK_TX_EMPTY_BIT (4) DEFINE_CLEAR_BIT_OP(intr_mask_tx_empty, DW_IC_REG_INTR_MASK, DW_IC_INTR_MASK_TX_EMPTY_BIT) DEFINE_SET_BIT_OP(intr_mask_tx_empty, DW_IC_REG_INTR_MASK, DW_IC_INTR_MASK_TX_EMPTY_BIT) @@ -205,14 +203,13 @@ DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32) DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32) DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32) -#define DW_IC_ENABLE_EN_BIT (0) +#define DW_IC_ENABLE_EN_BIT (0) DEFINE_CLEAR_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT) DEFINE_SET_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT) - -#define DW_IC_STATUS_ACTIVITY_BIT (0) -#define DW_IC_STATUS_TFNT_BIT (1) -#define DW_IC_STATUS_RFNE_BIT (3) +#define DW_IC_STATUS_ACTIVITY_BIT (0) +#define DW_IC_STATUS_TFNT_BIT (1) +#define DW_IC_STATUS_RFNE_BIT (3) DEFINE_TEST_BIT_OP(status_activity, DW_IC_REG_STATUS, DW_IC_STATUS_ACTIVITY_BIT) DEFINE_TEST_BIT_OP(status_tfnt, DW_IC_REG_STATUS, DW_IC_STATUS_TFNT_BIT) DEFINE_TEST_BIT_OP(status_rfne, DW_IC_REG_STATUS, DW_IC_STATUS_RFNE_BIT) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twi_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twi_common.h index a8925d3f..a3e9847b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twi_common.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twi_common.h @@ -22,7 +22,8 @@ extern "C" { : I2C_NRFX_TWI_INVALID_FREQUENCY) #define I2C(idx) DT_NODELABEL(i2c##idx) #define I2C_FREQUENCY(idx) \ - I2C_NRFX_TWI_FREQUENCY(DT_PROP(I2C(idx), clock_frequency)) + I2C_NRFX_TWI_FREQUENCY(DT_PROP_OR(I2C(idx), clock_frequency, \ + I2C_BITRATE_STANDARD)) struct i2c_nrfx_twi_common_data { uint32_t dev_config; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twim_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twim_common.h new file mode 100644 index 00000000..ba7fa72f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/i2c/i2c_nrfx_twim_common.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2024, Croxel Inc + * Copyright (c) 2024, Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWIM_COMMON_H_ +#define ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWIM_COMMON_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define I2C_NRFX_TWIM_INVALID_FREQUENCY ((nrf_twim_frequency_t)-1) +#define I2C_NRFX_TWIM_FREQUENCY(bitrate) \ + (bitrate == I2C_BITRATE_STANDARD ? NRF_TWIM_FREQ_100K \ + : bitrate == 250000 ? NRF_TWIM_FREQ_250K \ + : bitrate == I2C_BITRATE_FAST \ + ? NRF_TWIM_FREQ_400K \ + : IF_ENABLED(NRF_TWIM_HAS_1000_KHZ_FREQ, \ + (bitrate == I2C_BITRATE_FAST_PLUS ? NRF_TWIM_FREQ_1000K :)) \ + I2C_NRFX_TWIM_INVALID_FREQUENCY) + +#define I2C(idx) DT_NODELABEL(i2c##idx) +#define I2C_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(I2C(idx), prop) +#define I2C_FREQUENCY(idx) I2C_NRFX_TWIM_FREQUENCY(DT_PROP_OR(I2C(idx), clock_frequency, \ + I2C_BITRATE_STANDARD)) + +struct i2c_nrfx_twim_common_config { + nrfx_twim_t twim; + nrfx_twim_config_t twim_config; + nrfx_twim_evt_handler_t event_handler; + uint16_t msg_buf_size; + void (*irq_connect)(void); + const struct pinctrl_dev_config *pcfg; + uint8_t *msg_buf; + uint16_t max_transfer_size; +}; + +int i2c_nrfx_twim_common_init(const struct device *dev); +int i2c_nrfx_twim_configure(const struct device *dev, uint32_t i2c_config); +int i2c_nrfx_twim_recover_bus(const struct device *dev); +int i2c_nrfx_twim_msg_transfer(const struct device *dev, uint8_t flags, uint8_t *buf, + size_t buf_len, uint16_t i2c_addr); + +#ifdef CONFIG_PM_DEVICE +int twim_nrfx_pm_action(const struct device *dev, enum pm_device_action action); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_I2C_I2C_NRFX_TWIM_COMMON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h index 185e445a..4d4ee458 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h @@ -80,7 +80,15 @@ struct ieee802154_cc13xx_cc26xx_data { volatile rfc_CMD_IEEE_CSMA_t cmd_ieee_csma; volatile rfc_CMD_IEEE_TX_t cmd_ieee_tx; volatile rfc_CMD_IEEE_RX_ACK_t cmd_ieee_rx_ack; +#if defined(CONFIG_SOC_CC1352R) || defined(CONFIG_SOC_CC2652R) || \ + defined(CONFIG_SOC_CC1352R7) || defined(CONFIG_SOC_CC2652R7) volatile rfc_CMD_RADIO_SETUP_t cmd_radio_setup; +#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC2652P) || \ + defined(CONFIG_SOC_CC1352P7) || defined(CONFIG_SOC_CC2652P7) + volatile rfc_CMD_RADIO_SETUP_PA_t cmd_radio_setup; +#else + BUILD_ASSERT(false, "unknown model"); +#endif /* CONFIG_SOC_CCxx52x */ volatile int16_t saved_cmdhandle; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/modem/modem_context.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/modem/modem_context.h index de76b0a4..8c75e24a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/modem/modem_context.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/modem/modem_context.h @@ -15,7 +15,7 @@ #define ZEPHYR_INCLUDE_DRIVERS_MODEM_MODEM_CONTEXT_H_ #include -#include +#include #include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/mspi/mspi_ambiq.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/mspi/mspi_ambiq.h index 7cfe07b6..b289f190 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/mspi/mspi_ambiq.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/mspi/mspi_ambiq.h @@ -47,6 +47,9 @@ enum mspi_ambiq_timing_param { MSPI_AMBIQ_SET_RXDQSDLYEXT = BIT(7), }; +#define MSPI_PORT(n) ((DT_REG_ADDR(DT_INST_BUS(n)) - MSPI0_BASE) / \ + (DT_REG_SIZE(DT_INST_BUS(n)) * 4)) + #define TIMING_CFG_GET_RX_DUMMY(cfg) \ { \ mspi_timing_cfg *timing = (mspi_timing_cfg *)cfg; \ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/nsos.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/nsos.h index f1e2f12e..9b901d91 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/nsos.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/nsos.h @@ -14,17 +14,22 @@ #define NSOS_MID_PF_UNSPEC 0 /**< Unspecified protocol family. */ #define NSOS_MID_PF_INET 1 /**< IP protocol family version 4. */ #define NSOS_MID_PF_INET6 2 /**< IP protocol family version 6. */ +#define NSOS_MID_PF_UNIX 6 /**< Unix protocol. */ +#define NSOS_MID_PF_PACKET 3 /**< Packet family. */ /* Address families. */ #define NSOS_MID_AF_UNSPEC NSOS_MID_PF_UNSPEC /**< Unspecified address family. */ #define NSOS_MID_AF_INET NSOS_MID_PF_INET /**< IP protocol family version 4. */ #define NSOS_MID_AF_INET6 NSOS_MID_PF_INET6 /**< IP protocol family version 6. */ +#define NSOS_MID_AF_UNIX NSOS_MID_PF_UNIX /**< Unix protocol. */ +#define NSOS_MID_AF_PACKET NSOS_MID_PF_PACKET /**< Packet family. */ /** Protocol numbers from IANA/BSD */ enum nsos_mid_net_ip_protocol { NSOS_MID_IPPROTO_IP = 0, /**< IP protocol (pseudo-val for setsockopt() */ NSOS_MID_IPPROTO_ICMP = 1, /**< ICMP protocol */ NSOS_MID_IPPROTO_IGMP = 2, /**< IGMP protocol */ + NSOS_MID_IPPROTO_ETH_P_ALL = 3, /**< Every packet. from linux if_ether.h */ NSOS_MID_IPPROTO_IPIP = 4, /**< IPIP tunnels */ NSOS_MID_IPPROTO_TCP = 6, /**< TCP protocol */ NSOS_MID_IPPROTO_UDP = 17, /**< UDP protocol */ @@ -63,10 +68,28 @@ struct nsos_mid_sockaddr_in6 { uint32_t sin6_scope_id; /* Set of interfaces for a scope */ }; +#define UNIX_PATH_MAX 108 +struct nsos_mid_sockaddr_un { + sa_family_t sun_family; /* AF_UNIX */ + char sun_path[UNIX_PATH_MAX]; /* pathname */ +}; + +struct nsos_mid_sockaddr_ll { + sa_family_t sll_family; /**< Always AF_PACKET */ + uint16_t sll_protocol; /**< Physical-layer protocol */ + int sll_ifindex; /**< Interface number */ + uint16_t sll_hatype; /**< ARP hardware type */ + uint8_t sll_pkttype; /**< Packet type */ + uint8_t sll_halen; /**< Length of address */ + uint8_t sll_addr[8]; /**< Physical-layer address, big endian */ +}; + struct nsos_mid_sockaddr_storage { union { struct nsos_mid_sockaddr_in sockaddr_in; struct nsos_mid_sockaddr_in6 sockaddr_in6; + struct nsos_mid_sockaddr_un sockaddr_un; + struct nsos_mid_sockaddr_ll sockaddr_ll; }; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/slip.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/slip.h index 94c5c853..554cf395 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/slip.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/net/slip.h @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl345/adxl345.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl345/adxl345.h index 35412ac7..4fc55d30 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl345/adxl345.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl345/adxl345.h @@ -7,9 +7,19 @@ #ifndef ZEPHYR_DRIVERS_SENSOR_ADX345_ADX345_H_ #define ZEPHYR_DRIVERS_SENSOR_ADX345_ADX345_H_ +#include #include #include #include +#include +#include + +#ifdef CONFIG_ADXL345_STREAM +#include +#endif /* CONFIG_ADXL345_STREAM */ + +#define DT_DRV_COMPAT adi_adxl345 + #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) #include #endif @@ -23,14 +33,21 @@ #define ADXL345_READ_CMD 0x80 #define ADXL345_MULTIBYTE_FLAG 0x40 +#define ADXL345_REG_READ(x) ((x & 0xFF) | ADXL345_READ_CMD) + +#define SAMPLE_SIZE 6 +#define SAMPLE_MASK 0x3F +#define SAMPLE_NUM 0x1F + /* Registers */ -#define ADXL345_DEVICE_ID_REG 0x00 -#define ADXL345_RATE_REG 0x2c -#define ADXL345_POWER_CTL_REG 0x2d -#define ADXL345_DATA_FORMAT_REG 0x31 -#define ADXL345_X_AXIS_DATA_0_REG 0x32 -#define ADXL345_FIFO_CTL_REG 0x38 -#define ADXL345_FIFO_STATUS_REG 0x39 +#define ADXL345_DEVICE_ID_REG 0x00 +#define ADXL345_RATE_REG 0x2c +#define ADXL345_POWER_CTL_REG 0x2d +#define ADXL345_DATA_FORMAT_REG 0x31 +#define ADXL345_DATA_FORMAT_FULL_RES 0x08 +#define ADXL345_X_AXIS_DATA_0_REG 0x32 +#define ADXL345_FIFO_CTL_REG 0x38 +#define ADXL345_FIFO_STATUS_REG 0x39 #define ADXL345_PART_ID 0xe5 @@ -42,19 +59,148 @@ #define ADXL345_ENABLE_MEASURE_BIT (1 << 3) #define ADXL345_FIFO_STREAM_MODE (1 << 7) #define ADXL345_FIFO_COUNT_MASK 0x3f +#define ADXL345_COMPLEMENT_MASK(x) GENMASK(15, (x)) #define ADXL345_COMPLEMENT 0xfc00 #define ADXL345_MAX_FIFO_SIZE 32 +#define ADXL345_INT_ENABLE 0x2Eu +#define ADXL345_INT_MAP 0x2Fu +#define ADXL345_INT_SOURCE 0x30u + +/* ADXL345_STATUS_1 */ +#define ADXL345_STATUS_DOUBLE_TAP(x) (((x) >> 5) & 0x1) +#define ADXL345_STATUS_SINGLE_TAP(x) (((x) >> 6) & 0x1) +#define ADXL345_STATUS_DATA_RDY(x) (((x) >> 7) & 0x1) + +/* ADXL345_INT_MAP */ +#define ADXL345_INT_MAP_OVERRUN_MSK BIT(0) +#define ADXL345_INT_MAP_OVERRUN_MODE(x) (((x) & 0x1) << 0) +#define ADXL345_INT_MAP_WATERMARK_MSK BIT(1) +#define ADXL345_INT_MAP_WATERMARK_MODE(x) (((x) & 0x1) << 1) +#define ADXL345_INT_MAP_FREE_FALL_MSK BIT(2) +#define ADXL345_INT_MAP_FREE_FALL_MODE(x) (((x) & 0x1) << 2) +#define ADXL345_INT_MAP_INACT_MSK BIT(3) +#define ADXL345_INT_MAP_INACT_MODE(x) (((x) & 0x1) << 3) +#define ADXL345_INT_MAP_ACT_MSK BIT(4) +#define ADXL345_INT_MAP_ACT_MODE(x) (((x) & 0x1) << 4) +#define ADXL345_INT_MAP_DOUBLE_TAP_MSK BIT(5) +#define ADXL345_INT_MAP_DOUBLE_TAP_MODE(x) (((x) & 0x1) << 5) +#define ADXL345_INT_MAP_SINGLE_TAP_MSK BIT(6) +#define ADXL345_INT_MAP_SINGLE_TAP_MODE(x) (((x) & 0x1) << 6) +#define ADXL345_INT_MAP_DATA_RDY_MSK BIT(7) +#define ADXL345_INT_MAP_DATA_RDY_MODE(x) (((x) & 0x1) << 7) + +/* POWER_CTL */ +#define ADXL345_POWER_CTL_WAKEUP_4HZ BIT(0) +#define ADXL345_POWER_CTL_WAKEUP_4HZ_MODE(x) (((x) & 0x1) << 0) +#define ADXL345_POWER_CTL_WAKEUP_2HZ BIT(1) +#define ADXL345_POWER_CTL_WAKEUP_2HZ_MODE(x) (((x) & 0x1) << 1) +#define ADXL345_POWER_CTL_SLEEP BIT(2) +#define ADXL345_POWER_CTL_SLEEP_MODE(x) (((x) & 0x1) << 2) +#define ADXL345_POWER_CTL_MEASURE_MSK GENMASK(3, 3) +#define ADXL345_POWER_CTL_MEASURE_MODE(x) (((x) & 0x1) << 3) +#define ADXL345_POWER_CTL_STANDBY_MODE(x) (((x) & 0x0) << 3) + +/* ADXL345_FIFO_CTL */ +#define ADXL345_FIFO_CTL_MODE_MSK GENMASK(7, 6) +#define ADXL345_FIFO_CTL_MODE_MODE(x) (((x) & 0x3) << 6) +#define ADXL345_FIFO_CTL_TRIGGER_MSK BIT(5) +#define ADXL345_FIFO_CTL_TRIGGER_MODE(x) (((x) & 0x1) << 5) +#define ADXL345_FIFO_CTL_SAMPLES_MSK BIT(0) +#define ADXL345_FIFO_CTL_SAMPLES_MODE(x) ((x) & 0x1F) + +#define ADXL345_ODR_MSK GENMASK(3, 0) +#define ADXL345_ODR_MODE(x) ((x) & 0xF) + +enum adxl345_odr { + ADXL345_ODR_12HZ = 0x7, + ADXL345_ODR_25HZ, + ADXL345_ODR_50HZ, + ADXL345_ODR_100HZ, + ADXL345_ODR_200HZ, + ADXL345_ODR_400HZ +}; + +enum adxl345_fifo_trigger { + ADXL345_INT1, + ADXL345_INT2 +}; + +enum adxl345_fifo_mode { + ADXL345_FIFO_BYPASSED, + ADXL345_FIFO_OLD_SAVED, + ADXL345_FIFO_STREAMED, + ADXL345_FIFO_TRIGGERED +}; + +struct adxl345_fifo_config { + enum adxl345_fifo_mode fifo_mode; + enum adxl345_fifo_trigger fifo_trigger; + uint16_t fifo_samples; +}; + +enum adxl345_op_mode { + ADXL345_STANDBY, + ADXL345_MEASURE +}; + struct adxl345_dev_data { unsigned int sample_number; - int16_t bufx[ADXL345_MAX_FIFO_SIZE]; int16_t bufy[ADXL345_MAX_FIFO_SIZE]; int16_t bufz[ADXL345_MAX_FIFO_SIZE]; + struct adxl345_fifo_config fifo_config; + uint8_t is_full_res; + uint8_t selected_range; +#ifdef CONFIG_ADXL345_TRIGGER + struct gpio_callback gpio_cb; + + sensor_trigger_handler_t th_handler; + const struct sensor_trigger *th_trigger; + sensor_trigger_handler_t drdy_handler; + const struct sensor_trigger *drdy_trigger; + const struct device *dev; + +#if defined(CONFIG_ADXL345_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ADXL345_THREAD_STACK_SIZE); + struct k_sem gpio_sem; + struct k_thread thread; +#elif defined(CONFIG_ADXL345_TRIGGER_GLOBAL_THREAD) + struct k_work work; +#endif +#endif /* CONFIG_ADXL345_TRIGGER */ +#ifdef CONFIG_ADXL345_STREAM + struct rtio_iodev_sqe *sqe; + struct rtio *rtio_ctx; + struct rtio_iodev *iodev; + uint8_t status1; + uint8_t fifo_ent[1]; + uint64_t timestamp; + struct rtio *r_cb; + uint8_t fifo_watermark_irq; + uint8_t fifo_samples; + uint16_t fifo_total_bytes; +#endif /* CONFIG_ADXL345_STREAM */ }; +struct adxl345_fifo_data { + uint8_t is_fifo: 1; + uint8_t is_full_res: 1; + uint8_t selected_range: 2; + uint8_t sample_set_size: 4; + uint8_t int_status; + uint16_t accel_odr: 4; + uint16_t fifo_byte_count: 12; + uint64_t timestamp; +} __attribute__((__packed__)); + struct adxl345_sample { +#ifdef CONFIG_ADXL345_STREAM + uint8_t is_fifo: 1; + uint8_t res: 7; +#endif /* CONFIG_ADXL345_STREAM */ + uint8_t selected_range; int16_t x; int16_t y; int16_t z; @@ -77,6 +223,58 @@ struct adxl345_dev_config { const union adxl345_bus bus; adxl345_bus_is_ready_fn bus_is_ready; adxl345_reg_access_fn reg_access; + enum adxl345_odr odr; + bool op_mode; + struct adxl345_fifo_config fifo_config; +#ifdef CONFIG_ADXL345_TRIGGER + struct gpio_dt_spec interrupt; +#endif }; +void adxl345_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +void adxl345_stream_irq_handler(const struct device *dev); + +#ifdef CONFIG_ADXL345_TRIGGER +int adxl345_get_status(const struct device *dev, + uint8_t *status, uint16_t *fifo_entries); + +int adxl345_trigger_set(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +int adxl345_init_interrupt(const struct device *dev); + +#endif /* CONFIG_ADXL345_TRIGGER */ + +int adxl345_reg_write_mask(const struct device *dev, + uint8_t reg_addr, + uint8_t mask, + uint8_t data); + +int adxl345_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr, + uint8_t *data, size_t len); + +int adxl345_reg_write(const struct device *dev, uint8_t addr, uint8_t *data, + uint8_t len); + +int adxl345_reg_read(const struct device *dev, uint8_t addr, uint8_t *data, + uint8_t len); + +int adxl345_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val); + +int adxl345_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf); + +int adxl345_set_op_mode(const struct device *dev, enum adxl345_op_mode op_mode); +#ifdef CONFIG_SENSOR_ASYNC_API +int adxl345_read_sample(const struct device *dev, struct adxl345_sample *sample); +void adxl345_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +int adxl345_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); +void adxl345_accel_convert(struct sensor_value *val, int16_t sample); +#endif /* CONFIG_SENSOR_ASYNC_API */ + +#ifdef CONFIG_ADXL345_STREAM +int adxl345_configure_fifo(const struct device *dev, enum adxl345_fifo_mode mode, + enum adxl345_fifo_trigger trigger, uint16_t fifo_samples); +size_t adxl345_get_packet_size(const struct adxl345_dev_config *cfg); +#endif /* CONFIG_ADXL345_STREAM */ #endif /* ZEPHYR_DRIVERS_SENSOR_ADX345_ADX345_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl362/adxl362.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl362/adxl362.h index ac41a2ff..1959833e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl362/adxl362.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl362/adxl362.h @@ -11,13 +11,14 @@ #include #include #include +#include #define ADXL362_SLAVE_ID 1 /* ADXL362 communication commands */ #define ADXL362_WRITE_REG 0x0A #define ADXL362_READ_REG 0x0B -#define ADXL362_WRITE_FIFO 0x0D +#define ADXL362_READ_FIFO 0x0D /* Registers */ #define ADXL362_REG_DEVID_AD 0x00 @@ -160,6 +161,8 @@ #define ADXL362_STATUS_CHECK_DATA_READY(x) (((x) >> 0) & 0x1) #define ADXL362_STATUS_CHECK_INACT(x) (((x) >> 5) & 0x1) #define ADXL362_STATUS_CHECK_ACTIVITY(x) (((x) >> 4) & 0x1) +#define ADXL362_STATUS_CHECK_FIFO_OVR(x) (((x) >> 3) & 0x1) +#define ADXL362_STATUS_CHECK_FIFO_WTR(x) (((x) >> 2) & 0x1) /* ADXL362 scale factors from specifications */ #define ADXL362_ACCEL_2G_LSB_PER_G 1000 @@ -171,6 +174,12 @@ #define ADXL362_TEMP_BIAS_LSB 350 #define ADXL362_TEMP_BIAS_TEST_CONDITION 25 +/* ADXL362 check fifo sample header */ +#define ADXL362_FIFO_HDR_CHECK_ACCEL_X(x) ((((x) & 0xC000) >> 14) == 0x00) +#define ADXL362_FIFO_HDR_CHECK_ACCEL_Y(x) ((((x) & 0xC000) >> 14) == 0x01) +#define ADXL362_FIFO_HDR_CHECK_ACCEL_Z(x) ((((x) & 0xC000) >> 14) == 0x02) +#define ADXL362_FIFO_HDR_CHECK_TEMP(x) ((((x) & 0xC000) >> 14) == 0x03) + struct adxl362_config { struct spi_dt_spec bus; #if defined(CONFIG_ADXL362_TRIGGER) @@ -192,6 +201,11 @@ struct adxl362_data { } __packed; int16_t temp; uint8_t selected_range; + uint8_t accel_odr; + + uint8_t fifo_mode; + uint8_t en_temp_read; + uint16_t water_mark_lvl; #if defined(CONFIG_ADXL362_TRIGGER) const struct device *dev; @@ -213,8 +227,45 @@ struct adxl362_data { struct k_work work; #endif #endif /* CONFIG_ADXL362_TRIGGER */ +#ifdef CONFIG_ADXL362_STREAM + uint8_t status; + uint8_t fifo_ent[2]; + struct rtio_iodev_sqe *sqe; + struct rtio *rtio_ctx; + struct rtio_iodev *iodev; + uint64_t timestamp; + struct rtio *r_cb; + uint8_t fifo_full_irq: 1; + uint8_t fifo_wmark_irq: 1; + uint8_t res: 6; +#endif /* CONFIG_ADXL362_STREAM */ }; +struct adxl362_sample_data { +#ifdef CONFIG_ADXL362_STREAM + uint8_t is_fifo: 1; + uint8_t res: 7; +#endif /*CONFIG_ADXL362_STREAM*/ + uint8_t selected_range; + int16_t acc_x; + int16_t acc_y; + int16_t acc_z; + int16_t temp; +}; + +struct adxl362_fifo_data { + uint8_t is_fifo: 1; + uint8_t has_tmp: 1; + uint8_t selected_range: 3; + uint8_t accel_odr: 3; + uint8_t int_status; + uint16_t fifo_byte_count; + uint64_t timestamp; +} __attribute__((__packed__)); + +BUILD_ASSERT(sizeof(struct adxl362_fifo_data) % 4 == 0, + "adxl362_fifo_data struct should be word aligned"); + #if defined(CONFIG_ADXL362_ACCEL_RANGE_RUNTIME) ||\ defined(CONFIG_ADXL362_ACCEL_RANGE_2G) # define ADXL362_DEFAULT_RANGE_ACC ADXL362_RANGE_2G @@ -239,6 +290,10 @@ struct adxl362_data { # define ADXL362_DEFAULT_ODR_ACC ADXL362_ODR_400_HZ #endif +void adxl362_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +void adxl362_stream_irq_handler(const struct device *dev); +int adxl362_fifo_read(const struct device *dev, void *buff, size_t length); + #ifdef CONFIG_ADXL362_TRIGGER int adxl362_reg_write_mask(const struct device *dev, uint8_t reg_addr, uint8_t mask, uint8_t data); @@ -258,4 +313,21 @@ int adxl362_set_interrupt_mode(const struct device *dev, uint8_t mode); int adxl362_clear_data_ready(const struct device *dev); #endif /* CONFIG_ADT7420_TRIGGER */ +#ifdef CONFIG_SENSOR_ASYNC_API +int adxl362_rtio_fetch(const struct device *dev, + struct adxl362_sample_data *sample_data); +void adxl362_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +int adxl362_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); +void adxl362_accel_convert(struct sensor_value *val, int accel, + int range); +void adxl362_temp_convert(struct sensor_value *val, int temp); +#endif /* CONFIG_SENSOR_ASYNC_API */ + +#ifdef CONFIG_ADXL362_STREAM +int adxl362_fifo_setup(const struct device *dev, uint8_t mode, + uint16_t water_mark_lvl, uint8_t en_temp_read); +#endif /* CONFIG_ADXL362_STREAM */ + +int adxl362_reg_access(const struct device *dev, uint8_t cmd, + uint8_t reg_addr, void *data, size_t length); #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL362_ADXL362_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl367/adxl367.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl367/adxl367.h index 8cef4742..a8d28a6a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl367/adxl367.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl367/adxl367.h @@ -14,13 +14,34 @@ #include #include +#define DT_DRV_COMPAT adi_adxl367 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) -#include +#define ADXL367_BUS_SPI #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#define ADXL367_BUS_I2C +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ +#undef DT_DRV_COMPAT +#define DT_DRV_COMPAT adi_adxl366 +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#define ADXL367_BUS_SPI +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) -#include +#define ADXL367_BUS_I2C #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ +#undef DT_DRV_COMPAT + +#ifdef ADXL367_BUS_SPI +#include +#endif /* ADXL367_BUS_SPI */ + +#ifdef ADXL367_BUS_I2C +#include +#endif /* ADXL367_BUS_I2C */ + +#define ADXL367_CHIP_ID 0 +#define ADXL366_CHIP_ID 1 /* * ADXL367 registers definition @@ -102,6 +123,7 @@ #define ADXL367_TO_REG(x) ((x) >> 1) #define ADXL367_SPI_WRITE_REG 0x0Au #define ADXL367_SPI_READ_REG 0x0Bu +#define ADXL367_SPI_READ_FIFO 0x0Du #define ADXL367_ABSOLUTE 0x00 #define ADXL367_REFERENCED 0x01 @@ -201,10 +223,19 @@ /* Max change = 270mg. Sensitivity = 4LSB / mg */ #define ADXL367_SELF_TEST_MAX (270 * 100 / 25) +/* ADXL367 get fifo sample header */ +#define ADXL367_FIFO_HDR_GET_ACCEL_AXIS(x) (((x) & 0xC000) >> 14) +#define ADXL367_FIFO_HDR_CHECK_TEMP(x) ((((x) & 0xC000) >> 14) == 0x3) + +/* ADXL362 scale factors from specifications */ +#define ADXL367_ACCEL_2G_LSB_PER_G 4000 +#define ADXL367_ACCEL_4G_LSB_PER_G 2000 +#define ADXL367_ACCEL_8G_LSB_PER_G 1000 + enum adxl367_axis { - ADXL367_X_AXIS, - ADXL367_Y_AXIS, - ADXL367_Z_AXIS + ADXL367_X_AXIS = 0x0, + ADXL367_Y_AXIS = 0x1, + ADXL367_Z_AXIS = 0x2 }; enum adxl367_op_mode { @@ -279,6 +310,16 @@ struct adxl367_xyz_accel_data { int16_t x; int16_t y; int16_t z; + enum adxl367_range range; +}; + +struct adxl367_sample_data { +#ifdef CONFIG_ADXL367_STREAM + uint8_t is_fifo: 1; + uint8_t res: 7; +#endif /*CONFIG_ADXL367_STREAM*/ + struct adxl367_xyz_accel_data xyz; + int16_t raw_temp; }; struct adxl367_transfer_function { @@ -316,15 +357,29 @@ struct adxl367_data { struct k_work work; #endif #endif /* CONFIG_ADXL367_TRIGGER */ +#ifdef CONFIG_ADXL367_STREAM + uint8_t status; + uint8_t fifo_ent[2]; + struct rtio_iodev_sqe *sqe; + struct rtio *rtio_ctx; + struct rtio_iodev *iodev; + uint64_t timestamp; + struct rtio *r_cb; + uint8_t fifo_full_irq: 1; + uint8_t fifo_wmark_irq: 1; + uint8_t res: 6; + enum adxl367_odr odr; + uint8_t pwr_reg; +#endif /* CONFIG_ADXL367_STREAM */ }; struct adxl367_dev_config { -#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#ifdef ADXL367_BUS_I2C struct i2c_dt_spec i2c; -#endif -#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#endif /* ADXL367_BUS_I2C */ +#ifdef ADXL367_BUS_SPI struct spi_dt_spec spi; -#endif +#endif /* ADXL367_BUS_SPI */ int (*bus_init)(const struct device *dev); #ifdef CONFIG_ADXL367_TRIGGER @@ -347,8 +402,30 @@ struct adxl367_dev_config { uint16_t inactivity_time; uint8_t activity_time; + uint8_t chip_id; }; +struct adxl367_fifo_data { + uint8_t is_fifo: 1; + uint8_t res: 7; + uint8_t packet_size; + uint8_t fifo_read_mode; + uint8_t has_tmp: 1; + uint8_t has_adc: 1; + uint8_t has_x: 1; + uint8_t has_y: 1; + uint8_t has_z: 1; + uint8_t res1: 3; + uint8_t int_status; + uint8_t accel_odr: 4; + uint8_t range: 4; + uint16_t fifo_byte_count; + uint64_t timestamp; +} __attribute__((__packed__)); + +BUILD_ASSERT(sizeof(struct adxl367_fifo_data) % 4 == 0, + "adxl367_fifo_data struct should be word aligned"); + int adxl367_spi_init(const struct device *dev); int adxl367_i2c_init(const struct device *dev); int adxl367_trigger_set(const struct device *dev, @@ -356,5 +433,29 @@ int adxl367_trigger_set(const struct device *dev, sensor_trigger_handler_t handler); int adxl367_init_interrupt(const struct device *dev); +void adxl367_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +void adxl367_stream_irq_handler(const struct device *dev); + +#ifdef CONFIG_SENSOR_ASYNC_API +void adxl367_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +int adxl367_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); +int adxl367_get_accel_data(const struct device *dev, + struct adxl367_xyz_accel_data *accel_data); +int adxl367_get_temp_data(const struct device *dev, int16_t *raw_temp); +void adxl367_accel_convert(struct sensor_value *val, int16_t value, + enum adxl367_range range); +void adxl367_temp_convert(struct sensor_value *val, int16_t value); +#endif /* CONFIG_SENSOR_ASYNC_API */ + +#ifdef CONFIG_ADXL367_STREAM +int adxl367_fifo_setup(const struct device *dev, + enum adxl367_fifo_mode mode, + enum adxl367_fifo_format format, + enum adxl367_fifo_read_mode read_mode, + uint8_t sets_nb); +int adxl367_set_op_mode(const struct device *dev, + enum adxl367_op_mode op_mode); +size_t adxl367_get_packet_size(const struct adxl367_dev_config *cfg); +#endif /* CONFIG_ADXL367_STREAM */ #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL367_ADXL367_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl372/adxl372.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl372/adxl372.h index 13b4d934..a3f93ceb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl372/adxl372.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/adi/adxl372/adxl372.h @@ -14,6 +14,12 @@ #include #include +#ifdef CONFIG_ADXL372_STREAM +#include +#endif /* CONFIG_ADXL372_STREAM */ + +#define DT_DRV_COMPAT adi_adxl372 + #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) #include #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ @@ -281,6 +287,10 @@ struct adxl372_activity_threshold { }; struct adxl372_xyz_accel_data { +#ifdef CONFIG_ADXL372_STREAM + uint8_t is_fifo: 1; + uint8_t res: 7; +#endif /* CONFIG_ADXL372_STREAM */ int16_t x; int16_t y; int16_t z; @@ -319,6 +329,16 @@ struct adxl372_data { struct k_work work; #endif #endif /* CONFIG_ADXL372_TRIGGER */ +#ifdef CONFIG_ADXL372_STREAM + struct rtio_iodev_sqe *sqe; + struct rtio *rtio_ctx; + struct rtio_iodev *iodev; + uint8_t status1; + uint8_t fifo_ent[2]; + uint64_t timestamp; + uint8_t fifo_full_irq; + uint8_t pwr_reg; +#endif /* CONFIG_ADXL372_STREAM */ }; struct adxl372_dev_config { @@ -358,9 +378,27 @@ struct adxl372_dev_config { uint8_t int2_config; }; +struct adxl372_fifo_data { + uint8_t is_fifo: 1; + uint8_t sample_set_size: 4; + uint8_t has_x: 1; + uint8_t has_y: 1; + uint8_t has_z: 1; + uint8_t int_status; + uint16_t accel_odr: 4; + uint16_t fifo_byte_count: 12; + uint64_t timestamp; +} __attribute__((__packed__)); + +BUILD_ASSERT(sizeof(struct adxl372_fifo_data) % 4 == 0, + "adxl372_fifo_data struct should be word aligned"); + int adxl372_spi_init(const struct device *dev); int adxl372_i2c_init(const struct device *dev); +void adxl372_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +void adxl372_stream_irq_handler(const struct device *dev); + #ifdef CONFIG_ADXL372_TRIGGER int adxl372_get_status(const struct device *dev, uint8_t *status1, uint8_t *status2, uint16_t *fifo_entries); @@ -372,4 +410,19 @@ int adxl372_trigger_set(const struct device *dev, int adxl372_init_interrupt(const struct device *dev); #endif /* CONFIG_ADXL372_TRIGGER */ +#ifdef CONFIG_SENSOR_ASYNC_API +int adxl372_get_accel_data(const struct device *dev, bool maxpeak, + struct adxl372_xyz_accel_data *accel_data); +void adxl372_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +int adxl372_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); +void adxl372_accel_convert(struct sensor_value *val, int16_t sample); +#endif /* CONFIG_SENSOR_ASYNC_API */ + +#ifdef CONFIG_ADXL372_STREAM +int adxl372_configure_fifo(const struct device *dev, enum adxl372_fifo_mode mode, + enum adxl372_fifo_format format, uint16_t fifo_samples); +size_t adxl372_get_packet_size(const struct adxl372_dev_config *cfg); +int adxl372_set_op_mode(const struct device *dev, enum adxl372_op_mode op_mode); +#endif /* CONFIG_ADXL372_STREAM */ + #endif /* ZEPHYR_DRIVERS_SENSOR_ADXL372_ADXL372_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/apds9253/apds9253.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/apds9253/apds9253.h new file mode 100644 index 00000000..9fbe4a43 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/apds9253/apds9253.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2018 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_APDS9253_APDS9253_H_ +#define ZEPHYR_DRIVERS_SENSOR_APDS9253_APDS9253_H_ + +#include + +#define APDS9253_MAIN_CTRL_REG 0x00 +#define APDS9253_MAIN_CTRL_REG_MASK GENMASK(5, 0) +#define APDS9253_MAIN_CTRL_SAI_LS BIT(5) +#define APDS9253_MAIN_CTRL_SW_RESET BIT(4) +#define APDS9253_MAIN_CTRL_RGB_MODE BIT(2) +#define APDS9253_MAIN_CTRL_LS_EN BIT(1) + +#define APDS9253_LS_MEAS_RATE_REG 0x04 +#define APDS9253_LS_MEAS_RATE_RES_MASK GENMASK(6, 4) +#define APDS9253_LS_MEAS_RATE_RES_20BIT_400MS 0 +#define APDS9253_LS_MEAS_RATE_RES_19BIT_200MS BIT(4) +#define APDS9253_LS_MEAS_RATE_RES_18BIT_100MS BIT(5) /* default */ +#define APDS9253_LS_MEAS_RATE_RES_17BIT_50MS (BIT(5) | BIT(4)) +#define APDS9253_LS_MEAS_RATE_RES_16BIT_25MS BIT(6) +#define APDS9253_LS_MEAS_RATE_RES_13_3MS (BIT(6) | BIT(4)) +#define APDS9253_LS_MEAS_RATE_MES_MASK GENMASK(2, 0) +#define APDS9253_LS_MEAS_RATE_MES_2000MS (BIT(2) | BIT(1) | BIT(0)) +#define APDS9253_LS_MEAS_RATE_MES_1000MS (BIT(2) | BIT(0)) +#define APDS9253_LS_MEAS_RATE_MES_500MS BIT(2) +#define APDS9253_LS_MEAS_RATE_MES_200MS (BIT(1) | BIT(0)) +#define APDS9253_LS_MEAS_RATE_MES_100MS BIT(1) /* default */ +#define APDS9253_LS_MEAS_RATE_MES_50MS BIT(0) +#define APDS9253_LS_MEAS_RATE_MES_25MS 0 + +#define APDS9253_LS_GAIN_REG 0x05 +#define APDS9253_LS_GAIN_MASK GENMASK(2, 0) +#define APDS9253_LS_GAIN_RANGE_18 BIT(2) +#define APDS9253_LS_GAIN_RANGE_9 (BIT(1) | BIT(0)) +#define APDS9253_LS_GAIN_RANGE_6 BIT(1) +#define APDS9253_LS_GAIN_RANGE_3 BIT(0) /* default */ +#define APDS9253_LS_GAIN_RANGE_1 0 + +#define APDS9253_PART_ID 0x06 +#define APDS9253_DEVICE_PART_ID 0xC0 +#define APDS9253_PART_ID_REV_MASK GENMASK(3, 0) +#define APDS9253_PART_ID_ID_MASK GENMASK(7, 4) + +#define APDS9253_MAIN_STATUS_REG 0x07 +#define APDS9253_MAIN_STATUS_POWER_ON BIT(5) +#define APDS9253_MAIN_STATUS_LS_INTERRUPT BIT(4) +#define APDS9253_MAIN_STATUS_LS_STATUS BIT(3) + +/* Channels data */ +#define APDS9253_LS_DATA_BASE 0x0A +#define APDS9253_LS_DATA_IR_0 0x0A +#define APDS9253_LS_DATA_IR_1 0x0B +#define APDS9253_LS_DATA_IR_2 0x0C +#define APDS9253_LS_DATA_GREEN_0 0x0D +#define APDS9253_LS_DATA_GREEN_1 0x0E +#define APDS9253_LS_DATA_GREEN_2 0x0F +#define APDS9253_LS_DATA_BLUE_0 0x10 +#define APDS9253_LS_DATA_BLUE_1 0x11 +#define APDS9253_LS_DATA_BLUE_2 0x12 +#define APDS9253_LS_DATA_RED_0 0x13 +#define APDS9253_LS_DATA_RED_1 0x14 +#define APDS9253_LS_DATA_RED_2 0x15 + +#define APDS9253_INT_CFG 0x19 +#define APDS9253_INT_CFG_LS_INT_SEL_IR 0 +#define APDS9253_INT_CFG_LS_INT_SEL_ALS BIT(4) /* default */ +#define APDS9253_INT_CFG_LS_INT_SEL_RED BIT(5) +#define APDS9253_INT_CFG_LS_INT_SEL_BLUE (BIT(5) | BIT(4)) +#define APDS9253_INT_CFG_LS_VAR_MODE_EN BIT(3) +#define APDS9253_INT_CFG_LS_INT_MODE_EN BIT(3) + +#define APDS9253_INT_PST 0x1A +#define APDS9253_LS_THRES_UP_0 0x21 +#define APDS9253_LS_THRES_UP_1 0x22 +#define APDS9253_LS_THRES_UP_2 0x23 +#define APDS9253_LS_THRES_LOW_0 0x24 +#define APDS9253_LS_THRES_LOW_1 0x25 +#define APDS9253_LS_THRES_LOW_2 0x26 +#define APDS9253_LS_THRES_VAR 0x27 +#define APDS9253_DK_CNT_STOR 0x29 + +struct apds9253_config { + struct i2c_dt_spec i2c; + struct gpio_dt_spec int_gpio; + uint8_t ls_gain; + uint8_t ls_rate; + uint8_t ls_resolution; + bool interrupt_enabled; +}; + +struct apds9253_data { + struct gpio_callback gpio_cb; + struct k_work work; + const struct device *dev; + uint32_t sample_crgb[4]; + uint8_t pdata; + struct k_sem data_sem; +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_APDS9253_APDS9253_H_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h index a4b35c64..f8a4f5c7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2023 Google LLC + * Copyright (c) 2024 Florian Weber * SPDX-License-Identifier: Apache-2.0 */ @@ -34,6 +35,13 @@ struct akm09918c_data { int16_t y_sample; int16_t z_sample; uint8_t mode; +#ifdef CONFIG_SENSOR_ASYNC_API + struct akm09918c_async_fetch_ctx { + struct rtio_iodev_sqe *iodev_sqe; + uint64_t timestamp; + struct k_work_delayable async_fetch_work; + } work_ctx; +#endif }; struct akm09918c_config { @@ -74,22 +82,23 @@ static inline void akm09918c_reg_to_hz(uint8_t reg, struct sensor_value *val) break; } } +int akm09918c_start_measurement(const struct device *dev, enum sensor_channel chan); +int akm09918c_fetch_measurement(const struct device *dev, int16_t *x, int16_t *y, int16_t *z); /* * RTIO types */ struct akm09918c_decoder_header { uint64_t timestamp; -} __attribute__((__packed__)); +} __packed; struct akm09918c_encoded_data { struct akm09918c_decoder_header header; int16_t readings[3]; }; -int akm09918c_sample_fetch_helper(const struct device *dev, enum sensor_channel chan, int16_t *x, - int16_t *y, int16_t *z); +void akm09918_async_fetch(struct k_work *work); int akm09918c_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme280/bme280.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme280/bme280.h index b386e623..62fbefec 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme280/bme280.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme280/bme280.h @@ -32,10 +32,9 @@ union bme280_bus { }; typedef int (*bme280_bus_check_fn)(const union bme280_bus *bus); -typedef int (*bme280_reg_read_fn)(const union bme280_bus *bus, - uint8_t start, uint8_t *buf, int size); -typedef int (*bme280_reg_write_fn)(const union bme280_bus *bus, - uint8_t reg, uint8_t val); +typedef int (*bme280_reg_read_fn)(const union bme280_bus *bus, uint8_t start, uint8_t *buf, + int size); +typedef int (*bme280_reg_write_fn)(const union bme280_bus *bus, uint8_t reg, uint8_t val); struct bme280_bus_io { bme280_bus_check_fn check; @@ -44,8 +43,7 @@ struct bme280_bus_io { }; #if BME280_BUS_SPI -#define BME280_SPI_OPERATION (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \ - SPI_MODE_CPOL | SPI_MODE_CPHA) +#define BME280_SPI_OPERATION (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | SPI_MODE_CPOL | SPI_MODE_CPHA) extern const struct bme280_bus_io bme280_bus_io_spi; #endif @@ -53,28 +51,28 @@ extern const struct bme280_bus_io bme280_bus_io_spi; extern const struct bme280_bus_io bme280_bus_io_i2c; #endif -#define BME280_REG_PRESS_MSB 0xF7 -#define BME280_REG_COMP_START 0x88 -#define BME280_REG_HUM_COMP_PART1 0xA1 -#define BME280_REG_HUM_COMP_PART2 0xE1 -#define BME280_REG_ID 0xD0 -#define BME280_REG_CONFIG 0xF5 -#define BME280_REG_CTRL_MEAS 0xF4 -#define BME280_REG_CTRL_HUM 0xF2 -#define BME280_REG_STATUS 0xF3 -#define BME280_REG_RESET 0xE0 - -#define BMP280_CHIP_ID_SAMPLE_1 0x56 -#define BMP280_CHIP_ID_SAMPLE_2 0x57 -#define BMP280_CHIP_ID_MP 0x58 -#define BME280_CHIP_ID 0x60 -#define BME280_MODE_SLEEP 0x00 -#define BME280_MODE_FORCED 0x01 -#define BME280_MODE_NORMAL 0x03 -#define BME280_SPI_3W_DISABLE 0x00 -#define BME280_CMD_SOFT_RESET 0xB6 -#define BME280_STATUS_MEASURING 0x08 -#define BME280_STATUS_IM_UPDATE 0x01 +#define BME280_REG_PRESS_MSB 0xF7 +#define BME280_REG_COMP_START 0x88 +#define BME280_REG_HUM_COMP_PART1 0xA1 +#define BME280_REG_HUM_COMP_PART2 0xE1 +#define BME280_REG_ID 0xD0 +#define BME280_REG_CONFIG 0xF5 +#define BME280_REG_CTRL_MEAS 0xF4 +#define BME280_REG_CTRL_HUM 0xF2 +#define BME280_REG_STATUS 0xF3 +#define BME280_REG_RESET 0xE0 + +#define BMP280_CHIP_ID_SAMPLE_1 0x56 +#define BMP280_CHIP_ID_SAMPLE_2 0x57 +#define BMP280_CHIP_ID_MP 0x58 +#define BME280_CHIP_ID 0x60 +#define BME280_MODE_SLEEP 0x00 +#define BME280_MODE_FORCED 0x01 +#define BME280_MODE_NORMAL 0x03 +#define BME280_SPI_3W_DISABLE 0x00 +#define BME280_CMD_SOFT_RESET 0xB6 +#define BME280_STATUS_MEASURING 0x08 +#define BME280_STATUS_IM_UPDATE 0x01 #if defined CONFIG_BME280_MODE_NORMAL #define BME280_MODE BME280_MODE_NORMAL @@ -83,82 +81,86 @@ extern const struct bme280_bus_io bme280_bus_io_i2c; #endif #if defined CONFIG_BME280_TEMP_OVER_1X -#define BME280_TEMP_OVER (1 << 5) +#define BME280_TEMP_OVER (1 << 5) #elif defined CONFIG_BME280_TEMP_OVER_2X -#define BME280_TEMP_OVER (2 << 5) +#define BME280_TEMP_OVER (2 << 5) #elif defined CONFIG_BME280_TEMP_OVER_4X -#define BME280_TEMP_OVER (3 << 5) +#define BME280_TEMP_OVER (3 << 5) #elif defined CONFIG_BME280_TEMP_OVER_8X -#define BME280_TEMP_OVER (4 << 5) +#define BME280_TEMP_OVER (4 << 5) #elif defined CONFIG_BME280_TEMP_OVER_16X -#define BME280_TEMP_OVER (5 << 5) +#define BME280_TEMP_OVER (5 << 5) #endif #if defined CONFIG_BME280_PRESS_OVER_1X -#define BME280_PRESS_OVER (1 << 2) +#define BME280_PRESS_OVER (1 << 2) #elif defined CONFIG_BME280_PRESS_OVER_2X -#define BME280_PRESS_OVER (2 << 2) +#define BME280_PRESS_OVER (2 << 2) #elif defined CONFIG_BME280_PRESS_OVER_4X -#define BME280_PRESS_OVER (3 << 2) +#define BME280_PRESS_OVER (3 << 2) #elif defined CONFIG_BME280_PRESS_OVER_8X -#define BME280_PRESS_OVER (4 << 2) +#define BME280_PRESS_OVER (4 << 2) #elif defined CONFIG_BME280_PRESS_OVER_16X -#define BME280_PRESS_OVER (5 << 2) +#define BME280_PRESS_OVER (5 << 2) #endif #if defined CONFIG_BME280_HUMIDITY_OVER_1X -#define BME280_HUMIDITY_OVER 1 +#define BME280_HUMIDITY_OVER 1 #elif defined CONFIG_BME280_HUMIDITY_OVER_2X -#define BME280_HUMIDITY_OVER 2 +#define BME280_HUMIDITY_OVER 2 #elif defined CONFIG_BME280_HUMIDITY_OVER_4X -#define BME280_HUMIDITY_OVER 3 +#define BME280_HUMIDITY_OVER 3 #elif defined CONFIG_BME280_HUMIDITY_OVER_8X -#define BME280_HUMIDITY_OVER 4 +#define BME280_HUMIDITY_OVER 4 #elif defined CONFIG_BME280_HUMIDITY_OVER_16X -#define BME280_HUMIDITY_OVER 5 +#define BME280_HUMIDITY_OVER 5 #endif #if defined CONFIG_BME280_STANDBY_05MS -#define BME280_STANDBY 0 +#define BME280_STANDBY 0 #elif defined CONFIG_BME280_STANDBY_62MS -#define BME280_STANDBY (1 << 5) +#define BME280_STANDBY (1 << 5) #elif defined CONFIG_BME280_STANDBY_125MS -#define BME280_STANDBY (2 << 5) +#define BME280_STANDBY (2 << 5) #elif defined CONFIG_BME280_STANDBY_250MS -#define BME280_STANDBY (3 << 5) +#define BME280_STANDBY (3 << 5) #elif defined CONFIG_BME280_STANDBY_500MS -#define BME280_STANDBY (4 << 5) +#define BME280_STANDBY (4 << 5) #elif defined CONFIG_BME280_STANDBY_1000MS -#define BME280_STANDBY (5 << 5) +#define BME280_STANDBY (5 << 5) #elif defined CONFIG_BME280_STANDBY_2000MS -#define BME280_STANDBY (6 << 5) +#define BME280_STANDBY (6 << 5) #elif defined CONFIG_BME280_STANDBY_4000MS -#define BME280_STANDBY (7 << 5) +#define BME280_STANDBY (7 << 5) #endif #if defined CONFIG_BME280_FILTER_OFF -#define BME280_FILTER 0 +#define BME280_FILTER 0 #elif defined CONFIG_BME280_FILTER_2 -#define BME280_FILTER (1 << 2) +#define BME280_FILTER (1 << 2) #elif defined CONFIG_BME280_FILTER_4 -#define BME280_FILTER (2 << 2) +#define BME280_FILTER (2 << 2) #elif defined CONFIG_BME280_FILTER_8 -#define BME280_FILTER (3 << 2) +#define BME280_FILTER (3 << 2) #elif defined CONFIG_BME280_FILTER_16 -#define BME280_FILTER (4 << 2) +#define BME280_FILTER (4 << 2) #endif -#define BME280_CTRL_MEAS_VAL (BME280_PRESS_OVER | \ - BME280_TEMP_OVER | \ - BME280_MODE) -#define BME280_CONFIG_VAL (BME280_STANDBY | \ - BME280_FILTER | \ - BME280_SPI_3W_DISABLE) +#define BME280_CTRL_MEAS_VAL (BME280_PRESS_OVER | BME280_TEMP_OVER | BME280_MODE) +#define BME280_CONFIG_VAL (BME280_STANDBY | BME280_FILTER | BME280_SPI_3W_DISABLE) +#define BME280_CTRL_MEAS_OFF_VAL (BME280_PRESS_OVER | BME280_TEMP_OVER | BME280_MODE_SLEEP) -#define BME280_CTRL_MEAS_OFF_VAL (BME280_PRESS_OVER | \ - BME280_TEMP_OVER | \ - BME280_MODE_SLEEP) +/* Convert to Q15.16 */ +#define BME280_TEMP_CONV 100 +#define BME280_TEMP_SHIFT 16 +/* Treat UQ24.8 as Q23.8 + * Need to divide by 1000 to convert to kPa + */ +#define BME280_PRESS_CONV_KPA 1000 +#define BME280_PRESS_SHIFT 23 +/* Treat UQ22.10 as Q21.10 */ +#define BME280_HUM_SHIFT 21 struct bme280_reading { /* Compensated values. */ @@ -221,11 +223,9 @@ int bme280_get_decoder(const struct device *dev, const struct sensor_decoder_api void bme280_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); -int bme280_sample_fetch(const struct device *dev, - enum sensor_channel chan); +int bme280_sample_fetch(const struct device *dev, enum sensor_channel chan); -int bme280_sample_fetch_helper(const struct device *dev, - enum sensor_channel chan, +int bme280_sample_fetch_helper(const struct device *dev, enum sensor_channel chan, struct bme280_reading *reading); #endif /* ZEPHYR_DRIVERS_SENSOR_BME280_BME280_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme680/bme680.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme680/bme680.h index a0f63fc4..6a4a4aef 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme680/bme680.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bme680/bme680.h @@ -196,6 +196,7 @@ struct bme680_data { uint8_t res_heat_range; int8_t res_heat_val; int8_t range_sw_err; + bool has_read_compensation; /* Calculated sensor values. */ int32_t calc_temp; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmi08x/bmi08x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmi08x/bmi08x.h index 6b8b33f8..83926126 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmi08x/bmi08x.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmi08x/bmi08x.h @@ -427,7 +427,7 @@ enum bmi08x_odr { #define BMI08X_GYR_SCALE(range_dps) ((2 * range_dps * SENSOR_PI) / 180LL / 65536LL) /* report of data sync is selected */ -#define BMI08X_ACCEL_DATA_SYNC_EN(inst) DT_NODE_HAS_STATUS(DT_INST_PHANDLE(inst, data_sync), okay) +#define BMI08X_ACCEL_DATA_SYNC_EN(inst) DT_NODE_HAS_STATUS_OKAY(DT_INST_PHANDLE(inst, data_sync)) /* Macro used for compile time optimization to compile in/out code used for data-sync * if at least 1 bmi08x has data-sync enabled */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmm150/bmm150.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmm150/bmm150.h index 47fb3f73..c606d92a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmm150/bmm150.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmm150/bmm150.h @@ -225,6 +225,8 @@ enum bmm150_presets { int bmm150_trigger_mode_init(const struct device *dev); +int bmm150_trigger_mode_power_ctrl(const struct device *dev, bool enable); + int bmm150_trigger_set(const struct device *dev, const struct sensor_trigger *trig, sensor_trigger_handler_t handler); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp180/bmp180.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp180/bmp180.h new file mode 100644 index 00000000..4893f6ad --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp180/bmp180.h @@ -0,0 +1,49 @@ +/* Bosch BMP180 pressure sensor + * + * Copyright (c) 2024 Chris Ruehl + * + * SPDX-License-Identifier: Apache-2.0 + * + * Datasheet: + * https://www.mouser.hk/datasheet/2/783/BST-BMP180-DS000-1509579.pdf + */ +#ifndef ZEPHYR_DRIVER_SENSORS_BMP180_H +#define ZEPHYR_DRIVER_SENSORS_BMP180_H + +/* Registers */ +#define BMP180_REG_CHIPID 0xD0 +#define BMP180_REG_CMD 0xE0 +#define BMP180_REG_MEAS_CTRL 0xF4 +#define BMP180_REG_MSB 0xF6 +#define BMP180_REG_LSB 0xF7 +#define BMP180_REG_XLSB 0xF8 +#define BMP180_REG_CALIB0 0xAA +#define BMP180_REG_CALIB21 0xBF + +/* BMP180_REG_CHIPID */ +#define BMP180_CHIP_ID 0x55 + +/* BMP180_REG_STATUS */ +#define BMP180_STATUS_CMD_RDY BIT(5) + +/* BMP180_REG_CMD */ +#define BMP180_CMD_SOFT_RESET 0xB6 +#define BMP180_CMD_GET_TEMPERATURE 0x2E +#define BMP180_CMD_GET_OSS0_PRESS 0x34 +#define BMP180_CMD_GET_OSS1_PRESS 0x74 /* 0x34 | OSR<<6 */ +#define BMP180_CMD_GET_OSS2_PRESS 0xB4 +#define BMP180_CMD_GET_OSS3_PRESS 0xF4 + +/* command result waiting time in ms */ +#define BMP180_CMD_GET_TEMP_DELAY 3 +#define BMP180_CMD_GET_OSS0_DELAY 3 +#define BMP180_CMD_GET_OSS1_DELAY 6 +#define BMP180_CMD_GET_OSS2_DELAY 12 +#define BMP180_CMD_GET_OSS3_DELAY 24 + +#define BMP180_ULTRALOWPOWER 0x00 /* oversampling 1x */ +#define BMP180_STANDARD 0x01 /* oversampling 2x */ +#define BMP180_HIGHRES 0x02 /* oversampling 4x */ +#define BMP180_ULTRAHIGH 0x03 /* oversampling 8x */ + +#endif /* ZEPHYR_DRIVER_SENSORS_BMP180_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp388/bmp388.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp388/bmp388.h index 0cc96083..22c74813 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp388/bmp388.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/bosch/bmp388/bmp388.h @@ -8,8 +8,8 @@ * https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmp388-ds001.pdf */ -#ifndef __BMP388_H -#define __BMP388_H +#ifndef ZEPHYR_BMP388_H +#define ZEPHYR_BMP388_H #include #include @@ -19,16 +19,29 @@ #include #include -#define DT_DRV_COMPAT bosch_bmp388 - +#define DT_DRV_COMPAT bosch_bmp388 #define BMP388_BUS_SPI DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) #define BMP388_BUS_I2C DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#undef DT_DRV_COMPAT + +#define DT_DRV_COMPAT bosch_bmp390 +#define BMP390_BUS_SPI DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#define BMP390_BUS_I2C DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#undef DT_DRV_COMPAT + +#if defined(BMP388_BUS_SPI) || defined(BMP390_BUS_SPI) +#define BMP3XX_USE_SPI_BUS +#endif + +#if defined(BMP388_BUS_I2C) || defined(BMP390_BUS_I2C) +#define BMP3XX_USE_I2C_BUS +#endif union bmp388_bus { -#if BMP388_BUS_SPI +#ifdef BMP3XX_USE_SPI_BUS struct spi_dt_spec spi; #endif -#if BMP388_BUS_I2C +#ifdef BMP3XX_USE_I2C_BUS struct i2c_dt_spec i2c; #endif }; @@ -45,13 +58,13 @@ struct bmp388_bus_io { bmp388_reg_write_fn write; }; -#if BMP388_BUS_SPI +#ifdef BMP3XX_USE_SPI_BUS #define BMP388_SPI_OPERATION (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | \ SPI_MODE_CPOL | SPI_MODE_CPHA) extern const struct bmp388_bus_io bmp388_bus_io_spi; #endif -#if BMP388_BUS_I2C +#ifdef BMP3XX_USE_I2C_BUS extern const struct bmp388_bus_io bmp388_bus_io_i2c; #endif @@ -176,6 +189,7 @@ struct bmp388_data { uint8_t odr; uint8_t osr_pressure; uint8_t osr_temp; + uint8_t chip_id; struct bmp388_cal_data cal; #if defined(CONFIG_BMP388_TRIGGER) @@ -212,4 +226,4 @@ int bmp388_reg_field_update(const struct device *dev, uint8_t mask, uint8_t val); -#endif /* __BMP388_H */ +#endif /* ZEPHYR_BMP388_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/jedec/jc42/jc42.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/jedec/jc42/jc42.h new file mode 100644 index 00000000..03108044 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/jedec/jc42/jc42.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2019 Peter Bigot Consulting, LLC + * Copyright (c) 2016 Intel Corporation + * Copyright (c) 2024 Vogl Electronic GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_JEDEC_JC42_H_ +#define ZEPHYR_DRIVERS_SENSOR_JEDEC_JC42_H_ + +#include + +#include +#include +#include +#include +#include +#include + +#define JC42_REG_CONFIG 0x01 +#define JC42_REG_UPPER_LIMIT 0x02 +#define JC42_REG_LOWER_LIMIT 0x03 +#define JC42_REG_CRITICAL 0x04 +#define JC42_REG_TEMP_AMB 0x05 + +/* 16 bits control configuration and state. + * + * * Bit 0 controls alert signal output mode + * * Bit 1 controls interrupt polarity + * * Bit 2 disables upper and lower threshold checking + * * Bit 3 enables alert signal output + * * Bit 4 records alert status + * * Bit 5 records interrupt status + * * Bit 6 locks the upper/lower window registers + * * Bit 7 locks the critical register + * * Bit 8 enters shutdown mode + * * Bits 9-10 control threshold hysteresis + */ +#define JC42_CFG_ALERT_MODE_INT BIT(0) +#define JC42_CFG_ALERT_ENA BIT(3) +#define JC42_CFG_ALERT_STATE BIT(4) +#define JC42_CFG_INT_CLEAR BIT(5) + +/* 16 bits are used for temperature and state encoding: + * * Bits 0..11 encode the temperature in a 2s complement signed value + * in Celsius with 1/16 Cel resolution + * * Bit 12 is set to indicate a negative temperature + * * Bit 13 is set to indicate a temperature below the lower threshold + * * Bit 14 is set to indicate a temperature above the upper threshold + * * Bit 15 is set to indicate a temperature above the critical threshold + */ +#define JC42_TEMP_SCALE_CEL 16 /* signed */ +#define JC42_TEMP_SIGN_BIT BIT(12) +#define JC42_TEMP_ABS_MASK ((uint16_t)(JC42_TEMP_SIGN_BIT - 1U)) +#define JC42_TEMP_LWR_BIT BIT(13) +#define JC42_TEMP_UPR_BIT BIT(14) +#define JC42_TEMP_CRT_BIT BIT(15) + +#define JC42_REG_RESOLUTION 0x08 + +struct jc42_data { + uint16_t reg_val; + +#ifdef CONFIG_JC42_TRIGGER + struct gpio_callback alert_cb; + + const struct device *dev; + + const struct sensor_trigger *trig; + sensor_trigger_handler_t trigger_handler; +#endif + +#ifdef CONFIG_JC42_TRIGGER_OWN_THREAD + struct k_sem sem; +#endif + +#ifdef CONFIG_JC42_TRIGGER_GLOBAL_THREAD + struct k_work work; +#endif +}; + +struct jc42_config { + struct i2c_dt_spec i2c; + uint8_t resolution; +#ifdef CONFIG_JC42_TRIGGER + struct gpio_dt_spec int_gpio; +#endif /* CONFIG_JC42_TRIGGER */ +}; + +int jc42_reg_read(const struct device *dev, uint8_t reg, uint16_t *val); +int jc42_reg_write_16bit(const struct device *dev, uint8_t reg, uint16_t val); +int jc42_reg_write_8bit(const struct device *dev, uint8_t reg, uint8_t val); + +#ifdef CONFIG_JC42_TRIGGER +int jc42_attr_set(const struct device *dev, enum sensor_channel chan, enum sensor_attribute attr, + const struct sensor_value *val); +int jc42_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); +int jc42_setup_interrupt(const struct device *dev); +#endif /* CONFIG_JC42_TRIGGER */ + +/* Encode a signed temperature in scaled Celsius to the format used in + * register values. + */ +static inline uint16_t jc42_temp_reg_from_signed(int temp) +{ + /* Get the 12-bit 2s complement value */ + uint16_t rv = temp & JC42_TEMP_ABS_MASK; + + if (temp < 0) { + rv |= JC42_TEMP_SIGN_BIT; + } + return rv; +} + +/* Decode a register temperature value to a signed temperature in + * scaled Celsius. + */ +static inline int jc42_temp_signed_from_reg(uint16_t reg) +{ + int rv = reg & JC42_TEMP_ABS_MASK; + + if (reg & JC42_TEMP_SIGN_BIT) { + /* Convert 12-bit 2s complement to signed negative + * value. + */ + rv = -(1U + (rv ^ JC42_TEMP_ABS_MASK)); + } + return rv; +} + +#endif /* ZEPHYR_DRIVERS_SENSOR_JEDEC_JC42_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/maxim/max31865/max31865.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/maxim/max31865/max31865.h index 1b8681bf..d5279533 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/maxim/max31865/max31865.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/maxim/max31865/max31865.h @@ -71,7 +71,7 @@ LOG_MODULE_REGISTER(MAX31865, CONFIG_SENSOR_LOG_LEVEL); * For under zero, taken from * https://www.analog.com/media/en/technical-documentation/application-notes/AN709_0.pdf */ -static const float A[6] = {-242.02, 2.2228, 2.5859e-3, 4.8260e-6, 2.8183e-8, 1.5243e-10}; +static const double RTD_C[6] = {-242.02, 2.2228, 2.5859e-3, 4.8260e-6, 2.8183e-8, 1.5243e-10}; struct max31865_data { double temperature; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/memsic/mc3419/mc3419.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/memsic/mc3419/mc3419.h new file mode 100644 index 00000000..e7165c8c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/memsic/mc3419/mc3419.h @@ -0,0 +1,105 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2023 Linumiz + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_MC3419_H_ +#define ZEPHYR_DRIVERS_SENSOR_MC3419_H_ + +#include +#include +#include +#include +#include + +/* Registers */ +#define MC3419_REG_INT_CTRL 0x06 +#define MC3419_REG_OP_MODE 0x07 +#define MC3419_REG_SAMPLE_RATE 0x08 +#define MC3419_REG_MOTION_CTRL 0x09 +#define MC3419_REG_XOUT_L 0x0D +#define MC3419_REG_YOUT_L 0x0F +#define MC3419_REG_ZOUT_L 0x11 +#define MC3419_REG_STATUS 0x13 +#define MC3419_REG_INT_STATUS 0x14 +#define MC3419_REG_RANGE_SELECT_CTRL 0x20 +#define MC3419_REG_SAMPLE_RATE_2 0x30 +#define MC3419_REG_COMM_CTRL 0x31 +#define MC3419_REG_ANY_MOTION_THRES 0x43 + +#define MC3419_RANGE_MASK GENMASK(6, 4) +#define MC3419_LPF_MASK GENMASK(3, 0) +#define MC3419_DATA_READY_MASK BIT(7) +#define MC3419_ANY_MOTION_MASK BIT(2) +#define MC3419_INT_CLEAR 0x00 +#define MC3419_INT_ROUTE 0x10 + +#define MC3419_ANY_MOTION_THRESH_MAX 0x7FFF +#define MC3419_SAMPLE_SIZE 3 +#define MC3419_SAMPLE_READ_SIZE (MC3419_SAMPLE_SIZE * (sizeof(int16_t))) + +#define SENSOR_GRAIN_VALUE (61LL / 1000.0) +#define SENSOR_GRAVITY_DOUBLE (SENSOR_G / 1000000.0) +#define MC3419_BASE_ODR_VAL 0x10 + +#define MC3419_TRIG_DATA_READY 0 +#define MC3419_TRIG_ANY_MOTION 1 +#define MC3419_TRIG_SIZE 2 + +enum mc3419_op_mode { + MC3419_MODE_STANDBY = 0x00, + MC3419_MODE_WAKE = 0x01 +}; + +struct mc3419_odr_map { + int16_t freq; + int16_t mfreq; +}; + +enum mc3419_accl_range { + MC3419_ACCl_RANGE_2G, + MC3419_ACCl_RANGE_4G, + MC3419_ACCl_RANGE_8G, + MC3419_ACCl_RANGE_16G, + MC3419_ACCl_RANGE_12G, + MC3419_ACCL_RANGE_END +}; + +struct mc3419_config { + struct i2c_dt_spec i2c; +#if defined(CONFIG_MC3419_TRIGGER) + struct gpio_dt_spec int_gpio; + bool int_cfg; +#endif + uint8_t lpf_fc_sel; + uint8_t decimation_rate; +}; + +struct mc3419_driver_data { + double sensitivity; + struct k_sem sem; + int16_t samples[MC3419_SAMPLE_SIZE]; +#if defined(CONFIG_MC3419_TRIGGER) + const struct device *gpio_dev; + struct gpio_callback gpio_cb; + sensor_trigger_handler_t handler[MC3419_TRIG_SIZE]; + const struct sensor_trigger *trigger[MC3419_TRIG_SIZE]; +#if defined(CONFIG_MC3419_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_MC3419_THREAD_STACK_SIZE); + struct k_thread thread; + struct k_sem trig_sem; +#else + struct k_work work; +#endif +#endif +}; + +#if defined(CONFIG_MC3419_TRIGGER) +int mc3419_trigger_init(const struct device *dev); +int mc3419_configure_trigger(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); +#endif + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/memsic/mmc56x3/mmc56x3.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/memsic/mmc56x3/mmc56x3.h new file mode 100644 index 00000000..71372c20 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/memsic/mmc56x3/mmc56x3.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_MMC56X3_MMC56X3_H_ +#define ZEPHYR_DRIVERS_SENSOR_MMC56X3_MMC56X3_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define DT_DRV_COMPAT memsic_mmc56x3 + +#define MMC56X3_BUS_I2C DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + +union mmc56x3_bus { + struct i2c_dt_spec i2c; +}; + +typedef int (*mmc56x3_bus_check_fn)(const union mmc56x3_bus *bus); +typedef int (*mmc56x3_reg_read_fn)(const union mmc56x3_bus *bus, uint8_t start, uint8_t *buf, + int size); +typedef int (*mmc56x3_reg_write_fn)(const union mmc56x3_bus *bus, uint8_t reg, uint8_t val); +typedef int (*mmc56x3_raw_read_fn)(const union mmc56x3_bus *bus, uint8_t *buf, size_t size); +typedef int (*mmc56x3_raw_write_fn)(const union mmc56x3_bus *bus, uint8_t *buf, size_t size); + +struct mmc56x3_bus_io { + mmc56x3_bus_check_fn check; + mmc56x3_reg_read_fn read; + mmc56x3_reg_write_fn write; + mmc56x3_raw_read_fn raw_read; + mmc56x3_raw_write_fn raw_write; +}; + +extern const struct mmc56x3_bus_io mmc56x3_bus_io_i2c; + +#define MMC56X3_REG_TEMP 0x09 +#define MMC56X3_CHIP_ID 0x10 +#define MMC56X3_REG_STATUS 0x18 +#define MMC56X3_REG_INTERNAL_ODR 0x1a +#define MMC56X3_REG_INTERNAL_CTRL_0 0x1b +#define MMC56X3_REG_INTERNAL_CTRL_1 0x1c +#define MMC56X3_REG_INTERNAL_CTRL_2 0x1d +#define MMC56X3_REG_ID 0x39 + +#define MMC56X3_CMD_RESET 0x10 +#define MMC56X3_CMD_SET 0x08 +#define MMC56X3_CMD_SW_RESET 0x80 +#define MMC56X3_CMD_TAKE_MEAS_M 0x01 +#define MMC56X3_CMD_TAKE_MEAS_T 0x02 +#define MMC56X3_CMD_AUTO_SELF_RESET_EN 0x20 +#define MMC56X3_CMD_CMM_FREQ_EN 0x80 +#define MMC56X3_CMD_CMM_EN 0x10 +#define MMC56X3_CMD_HPOWER 0x80 + +#define MMC56X3_STATUS_MEAS_M_DONE 0x80 +#define MMC56X3_STATUS_MEAS_T_DONE 0x40 + +#define MMC56X3_REG_MAGN_X_OUT_0 0x00 +/* Range is -30 to 30, sensitivity of raw 20-bit reading is + * 16384 = 1 Gauss. To convert raw reading to + * Q5.26 with range -32 to 32, + * reading * (1/16384) * pow(2, 31)/32 + * = reading * 4096 + */ +#define MMC56X3_MAGN_CONV_Q5_26_20B 4096 +/* 1/16384 */ +#define MMC56X3_MAGN_GAUSS_RES 0.000061035 +/* To convert reading to Q7.24 with range -128, 128, + * (BASE + reading * RES) * pow(2, 31)/128 + * = BASE * pow(2, 31)/128 + reading * RES * pow(2, 31)/128 + * CONV_BASE = BASE * pow(2, 31)/128 + * CONV_RES = RES * pow(2, 31)/128 + * = CONV_BASE + reading * CONV_RES + */ +#define MMC56X3_TEMP_BASE -75 +#define MMC56X3_TEMP_RES 0.8 +#define MMC56X3_TEMP_CONV_Q7_24_BASE -1258291200 +#define MMC56X3_TEMP_CONV_Q7_24_RES 13421773 + +#define MMC56X3_MAGN_SHIFT 5 +#define MMC56X3_TEMP_SHIFT 7 + +#ifdef __cplusplus +extern "C" { +#endif + +struct mmc56x3_config { + uint16_t magn_odr; + bool bw0; + bool bw1; + bool auto_sr; +}; + +struct mmc56x3_data { + struct mmc56x3_config config; + + uint8_t ctrl0_cache; + uint8_t ctrl1_cache; + uint8_t ctrl2_cache; + + uint32_t temp; + int32_t magn_x; + int32_t magn_y; + int32_t magn_z; +}; + +struct mmc56x3_dev_config { + union mmc56x3_bus bus; + const struct mmc56x3_bus_io *bus_io; +}; + +struct mmc56x3_decoder_header { + uint64_t timestamp; +} __attribute__((__packed__)); + +struct mmc56x3_encoded_data { + struct mmc56x3_decoder_header header; + struct { + /** Set if `temp` has data */ + uint8_t has_temp: 1; + /** Set if `magn_x` has data */ + uint8_t has_magn_x: 1; + /** Set if `magn_y` has data */ + uint8_t has_magn_y: 1; + /** Set if `magn_z` has data */ + uint8_t has_magn_z: 1; + } __attribute__((__packed__)); + struct mmc56x3_data data; +}; + +int mmc56x3_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); + +void mmc56x3_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); + +int mmc56x3_sample_fetch(const struct device *dev, enum sensor_channel chan); + +int mmc56x3_sample_fetch_helper(const struct device *dev, enum sensor_channel chan, + struct mmc56x3_data *data); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_SENSOR_MMC56X3_MMC56X3_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ntc_thermistor/ntc_thermistor.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ntc_thermistor/ntc_thermistor.h index 3a202d3b..b500aa38 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ntc_thermistor/ntc_thermistor.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ntc_thermistor/ntc_thermistor.h @@ -7,6 +7,7 @@ #ifndef NTC_THERMISTOR_H #define NTC_THERMISTOR_H +#include #include struct ntc_compensation { @@ -21,30 +22,32 @@ struct ntc_type { struct ntc_config { bool connected_positive; - uint32_t pullup_uv; + uint32_t pullup_mv; uint32_t pullup_ohm; uint32_t pulldown_ohm; struct ntc_type type; }; /** - * @brief Converts ohm to temperature in milli centigrade + * @brief Converts ohm to temperature in milli centigrade. * - * @param type: Pointer to ntc_type table info - * @param ohm: Read resistance of NTC thermistor + * @param[in] type Pointer to ntc_type table info + * @param[in] ohm Read resistance of NTC thermistor * - * @return temperature in milli centigrade + * @return Temperature in milli centigrade */ int32_t ntc_get_temp_mc(const struct ntc_type *type, unsigned int ohm); /** - * @brief Calculate the resistance read from NTC Thermistor + * @brief Calculate the resistance read from NTC thermistor. * - * @param cfg: NTC Thermistor configuration - * @sample_mv: Measured voltage in mV + * @param[in] cfg NTC thermistor configuration + * @param[in] sample_value Measured voltage relative to `sample_value_max` + * @param[in] sample_value_max Maximum of `sample_value` * * @return Thermistor resistance */ -uint32_t ntc_get_ohm_of_thermistor(const struct ntc_config *cfg, int sample_mv); +uint32_t ntc_get_ohm_of_thermistor(const struct ntc_config *cfg, int sample_value, + int sample_value_max); #endif /* NTC_THERMISTOR_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/nxp/fxls8974/fxls8974.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/nxp/fxls8974/fxls8974.h new file mode 100644 index 00000000..e01cc78f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/nxp/fxls8974/fxls8974.h @@ -0,0 +1,204 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif +#include +#include + +#define FXLS8974_BUS_I2C (1<<0) +#define FXLS8974_BUS_SPI (1<<1) +#define FXLS8974_REG_OUTXLSB 0x04 +#define FXLS8974_REG_OUTTEMP 0x01 +#define FXLS8974_REG_WHOAMI 0x13 +#define FXLS8974_REG_CTRLREG1 0x15 +#define FXLS8974_REG_CTRLREG2 0x16 +#define FXLS8974_REG_CTRLREG3 0x17 +#define FXLS8974_REG_CTRLREG4 0x18 +#define FXLS8974_REG_CTRLREG5 0x19 + +#define WHOAMI_ID_FXLS8974 0x86 + +#define FXLS8974_CTRLREG1_ACTIVE_MASK 0x01 +#define FXLS8974_CTRLREG1_RST_MASK 0x80 +#define FXLS8974_CTRLREG1_FSR_MASK 0x06 +#define FXLS8974_CTRLREG1_FSR_2G 0x00 +#define FXLS8974_CTRLREG1_FSR_4G 0x02 +#define FXLS8974_CTRLREG1_FSR_8G 0x04 +#define FXLS8974_CTRLREG1_FSR_16G 0x06 + +#define FXLS8974_CTRLREG2_WAKE_PM_MASK 0xC0 +#define FXLS8974_CTRLREG2_SLEEP_PM_MASK 0x30 + +#define FXLS8974_CTRLREG3_WAKE_ODR_MASK 0xF0 +#define FXLS8974_CTRLREG3_SLEEP_ODR_MASK 0x0F + +#define FXLS8974_CTRLREG3_ODR_RATE_3200 0x00 +#define FXLS8974_CTRLREG3_ODR_RATE_1600 0x01 +#define FXLS8974_CTRLREG3_ODR_RATE_800 0x02 +#define FXLS8974_CTRLREG3_ODR_RATE_400 0x03 +#define FXLS8974_CTRLREG3_ODR_RATE_200 0x04 +#define FXLS8974_CTRLREG3_ODR_RATE_100 0x05 +#define FXLS8974_CTRLREG3_ODR_RATE_50 0x06 +#define FXLS8974_CTRLREG3_ODR_RATE_25 0x07 +#define FXLS8974_CTRLREG3_ODR_RATE_12_5 0x08 +#define FXLS8974_CTRLREG3_ODR_RATE_6_25 0x09 +#define FXLS8974_CTRLREG3_ODR_RATE_3_125 0x0A +#define FXLS8974_CTRLREG3_ODR_RATE_1_563 0x0B +#define FXLS8974_CTRLREG3_ODR_RATE_0_781 0x0C + +#define FXLS8974_CTRLREG4_INT_POL_HIGH 0x01 + +#define FXLS8974_INTREG_EN 0x20 +#define FXLS8974_INT_PIN_SEL_REG 0x21 + +#define FXLS8974_DATA_ACCEL_X_OFFSET 0 +#define FXLS8974_DATA_ACCEL_Y_OFFSET FXLS8974_BYTES_PER_CHANNEL_NORMAL +#define FXLS8974_DATA_ACCEL_Z_OFFSET 2*FXLS8974_BYTES_PER_CHANNEL_NORMAL +#define FXLS8974_DATA_TEMP_OFFSET 3*FXLS8974_BYTES_PER_CHANNEL_NORMAL +#define FXLS8974_ZERO_TEMP 25 + +#define FXLS8974_MAX_NUM_CHANNELS 4 +#define FXLS8974_MAX_ACCEL_CHANNELS 3 +#define FXLS8974_MAX_TEMP_CHANNELS 1 + +#define FXLS8974_BYTES_PER_CHANNEL_NORMAL 2 +#define FXLS8974_BYTES_PER_CHANNEL_FAST 1 + +#define FXLS8974_MAX_ACCEL_BYTES (FXLS8974_MAX_ACCEL_CHANNELS*2) +#define FXLS8974_MAX_NUM_BYTES (FXLS8974_MAX_ACCEL_BYTES + FXLS8974_MAX_TEMP_CHANNELS) + +#define FXLS8974_DRDY_MASK 0x80 + +enum fxls8974_active { + FXLS8974_ACTIVE_OFF = 0, + FXLS8974_ACTIVE_ON, +}; + +enum fxls8974_wake { + FXLS8974_WAKE = 0, + FXLS8974_SLEEP, +}; + +enum fxls8974_channel { + FXLS8974_CHANNEL_ACCEL_X = 0, + FXLS8974_CHANNEL_ACCEL_Y, + FXLS8974_CHANNEL_ACCEL_Z, + FXLS8974_CHANNEL_TEMP, +}; + +struct fxls8974_io_ops { + int (*read)(const struct device *dev, + uint8_t reg, + void *data, + size_t length); + int (*byte_read)(const struct device *dev, + uint8_t reg, + uint8_t *byte); + int (*byte_write)(const struct device *dev, + uint8_t reg, + uint8_t byte); + int (*reg_field_update)(const struct device *dev, + uint8_t reg, + uint8_t mask, + uint8_t val); +}; + +union fxls8974_bus_cfg { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + struct spi_dt_spec spi; +#endif + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + struct i2c_dt_spec i2c; +#endif +}; + +struct fxls8974_config { + const union fxls8974_bus_cfg bus_cfg; + const struct fxls8974_io_ops *ops; + struct gpio_dt_spec reset_gpio; + uint8_t range; + uint8_t inst_on_bus; +#ifdef CONFIG_FXLS8974_TRIGGER + struct gpio_dt_spec int_gpio; +#endif + +}; + +struct fxls8974_data { + struct k_sem sem; + int16_t raw[FXLS8974_MAX_NUM_CHANNELS]; + uint8_t whoami; +#ifdef CONFIG_FXLS8974_TRIGGER + const struct device *dev; + struct gpio_callback gpio_cb; + sensor_trigger_handler_t drdy_handler; + const struct sensor_trigger *drdy_trig; +#endif +#ifdef CONFIG_FXLS8974_TRIGGER_OWN_THREAD + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_FXLS8974_THREAD_STACK_SIZE); + struct k_thread thread; + struct k_sem trig_sem; +#endif +#ifdef CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD + struct k_work work; +#endif +}; + +int fxls8974_get_active(const struct device *dev, enum fxls8974_active *active); +int fxls8974_set_active(const struct device *dev, enum fxls8974_active active); + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +int fxls8974_byte_write_spi(const struct device *dev, + uint8_t reg, + uint8_t byte); + +int fxls8974_byte_read_spi(const struct device *dev, + uint8_t reg, + uint8_t *byte); + +int fxls8974_reg_field_update_spi(const struct device *dev, + uint8_t reg, + uint8_t mask, + uint8_t val); + +int fxls8974_read_spi(const struct device *dev, + uint8_t reg, + void *data, + size_t length); +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +int fxls8974_byte_write_i2c(const struct device *dev, + uint8_t reg, + uint8_t byte); + +int fxls8974_byte_read_i2c(const struct device *dev, + uint8_t reg, + uint8_t *byte); + +int fxls8974_reg_field_update_i2c(const struct device *dev, + uint8_t reg, + uint8_t mask, + uint8_t val); + +int fxls8974_read_i2c(const struct device *dev, + uint8_t reg, + void *data, + size_t length); +#endif +#if CONFIG_FXLS8974_TRIGGER +int fxls8974_trigger_init(const struct device *dev); +int fxls8974_trigger_set(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/nxp/p3t1755/p3t1755.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/nxp/p3t1755/p3t1755.h new file mode 100644 index 00000000..b2ba329f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/nxp/p3t1755/p3t1755.h @@ -0,0 +1,71 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_P3T1755_P3T1755_H_ +#define ZEPHYR_DRIVERS_SENSOR_P3T1755_P3T1755_H_ + +#include + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) */ + +#include + +#define P3T1755_BUS_I2C (1<<0) +#define P3T1755_BUS_I3C (1<<1) +/* Registers. */ +#define P3T1755_TEMPERATURE_REG (0x00U) +#define P3T1755_CONFIG_REG (0x01U) + +#define P3T1755_TEMPERATURE_REG_SHIFT (0x04U) +#define P3T1755_TEMPERATURE_SCALE 62500 +#define P3T1755_TEMPERATURE_SIGN_BIT BIT(12) +#define P3T1755_TEMPERATURE_ABS_MASK ((uint16_t)(P3T1755_TEMPERATURE_SIGN_BIT - 1U)) + +#define P3T1755_CONFIG_REG_OS BIT(7) +#define P3T1755_CONFIG_REG_SD BIT(0) + +struct p3t1755_io_ops { + int (*read)(const struct device *dev, uint8_t reg, uint8_t *byte, uint8_t len); + int (*write)(const struct device *dev, uint8_t reg, uint8_t *byte, uint8_t len); +}; + +union p3t1755_bus_cfg { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + const struct i2c_dt_spec i2c; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) + struct i3c_device_desc **i3c; +#endif +}; + +struct p3t1755_config { + const union p3t1755_bus_cfg bus_cfg; + const struct p3t1755_io_ops ops; +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) + struct { + const struct device *bus; + const struct i3c_device_id dev_id; + } i3c; +#endif + bool oneshot_mode; + uint8_t inst_on_bus; +}; + +struct p3t1755_data { + int16_t sample; + uint8_t config_reg; +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) + struct i3c_device_desc *i3c_dev; +#endif +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_P3T1755_P3T1755_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/renesas/isl29035/isl29035.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/renesas/isl29035/isl29035.h new file mode 100644 index 00000000..e77a9d2e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/renesas/isl29035/isl29035.h @@ -0,0 +1,153 @@ +/* sensor_isl29035.h - header file for ISL29035 light sensor driver */ + +/* + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_ISL29035_ISL29035_H_ +#define ZEPHYR_DRIVERS_SENSOR_ISL29035_ISL29035_H_ + +#include +#include +#include +#include +#include + +#define ISL29035_COMMAND_I_REG 0x00 +#define ISL29035_OPMODE_SHIFT 5 +#define ISL29035_OPMODE_MASK (7 << ISL29035_OPMODE_SHIFT) +#define ISL29035_INT_BIT_SHIFT 2 +#define ISL29035_INT_BIT_MASK (1 << ISL29035_INT_BIT_SHIFT) +#define ISL29035_INT_PRST_SHIFT 0 +#define ISL29035_INT_PRST_MASK (3 << ISL29035_INT_BIT_SHIFT) + +#define ISL29035_OPMODE_OFF 0 +#define ISL29035_OPMODE_ALS_ONCE 1 +#define ISL29035_OPMODE_IR_ONCE 2 +#define ISL29035_OPMODE_ALS_CONT 5 +#define ISL29035_OPMODE_IR_CONT 6 + +#define ISL29035_COMMAND_II_REG 0x01 +#define ISL29035_LUX_RANGE_SHIFT 0 +#define ISL29035_LUX_RANGE_MASK (3 << ISL29035_LUX_RANGE_SHIFT) +#define ISL29035_ADC_RES_SHIFT 2 +#define ISL29035_ADC_RES_MASK (3 << ISL29035_ADC_RES_SHIFT) + +#define ISL29035_DATA_LSB_REG 0x02 +#define ISL29035_DATA_MSB_REG 0x03 +#define ISL29035_INT_LT_LSB_REG 0x04 +#define ISL29035_INT_LT_MSB_REG 0x05 +#define ISL29035_INT_HT_LSB_REG 0x06 +#define ISL29035_INT_HT_MSB_REG 0x07 + +#define ISL29035_ID_REG 0x0F +#define ISL29035_BOUT_SHIFT 7 +#define ISL29035_BOUT_MASK (1 << ISL29035_BOUT_SHIFT) +#define ISL29035_ID_SHIFT 3 +#define ISL29035_ID_MASK (3 << ISL29035_ID_SHIFT) + +#if CONFIG_ISL29035_MODE_ALS + #define ISL29035_ACTIVE_OPMODE ISL29035_OPMODE_ALS_CONT + #define ISL29035_ACTIVE_CHAN SENSOR_CHAN_LIGHT +#elif CONFIG_ISL29035_MODE_IR + #define ISL29035_ACTIVE_OPMODE ISL29035_OPMODE_IR_CONT + #define ISL29035_ACTIVE_CHAN SENSOR_CHAN_IR +#endif + +#define ISL29035_ACTIVE_OPMODE_BITS \ + (ISL29035_ACTIVE_OPMODE << ISL29035_OPMODE_SHIFT) + +#if CONFIG_ISL29035_LUX_RANGE_1K + #define ISL29035_LUX_RANGE_IDX 0 + #define ISL29035_LUX_RANGE 1000 +#elif CONFIG_ISL29035_LUX_RANGE_4K + #define ISL29035_LUX_RANGE_IDX 1 + #define ISL29035_LUX_RANGE 4000 +#elif CONFIG_ISL29035_LUX_RANGE_16K + #define ISL29035_LUX_RANGE_IDX 2 + #define ISL29035_LUX_RANGE 16000 +#elif CONFIG_ISL29035_LUX_RANGE_64K + #define ISL29035_LUX_RANGE_IDX 3 + #define ISL29035_LUX_RANGE 64000 +#endif + +#define ISL29035_LUX_RANGE_BITS \ + (ISL29035_LUX_RANGE_IDX << ISL29035_LUX_RANGE_SHIFT) + +#if CONFIG_ISL29035_INTEGRATION_TIME_26 + #define ISL29035_ADC_RES_IDX 3 +#elif CONFIG_ISL29035_INTEGRATION_TIME_410 + #define ISL29035_ADC_RES_IDX 2 +#elif CONFIG_ISL29035_INTEGRATION_TIME_6500 + #define ISL29035_ADC_RES_IDX 1 +#elif CONFIG_ISL29035_INTEGRATION_TIME_105K + #define ISL29035_ADC_RES_IDX 0 +#endif + +#define ISL29035_ADC_RES_BITS \ + (ISL29035_ADC_RES_IDX << ISL29035_ADC_RES_SHIFT) + +#define ISL29035_ADC_DATA_BITS (16 - 4 * ISL29035_ADC_RES_IDX) +#define ISL29035_ADC_DATA_MASK (0xFFFF >> (16 - ISL29035_ADC_DATA_BITS)) + +#if CONFIG_ISL29035_INT_PERSIST_1 + #define ISL29035_INT_PRST_IDX 0 + #define ISL29035_INT_PRST_CYCLES 1 +#elif CONFIG_ISL29035_INT_PERSIST_4 + #define ISL29035_INT_PRST_IDX 1 + #define ISL29035_INT_PRST_CYCLES 4 +#elif CONFIG_ISL29035_INT_PERSIST_8 + #define ISL29035_INT_PRST_IDX 2 + #define ISL29035_INT_PRST_CYCLES 8 +#elif CONFIG_ISL29035_INT_PERSIST_16 + #define ISL29035_INT_PRST_IDX 3 + #define ISL29035_INT_PRST_CYCLES 16 +#endif + +#define ISL29035_INT_PRST_BITS \ + (ISL29035_INT_PRST_IDX << ISL29035_INT_PRST_SHIFT) + +struct isl29035_driver_data { + uint16_t data_sample; + +#if CONFIG_ISL29035_TRIGGER + const struct device *dev; + struct gpio_callback gpio_cb; + + const struct sensor_trigger *th_trigger; + sensor_trigger_handler_t th_handler; + +#if defined(CONFIG_ISL29035_TRIGGER_OWN_THREAD) + K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ISL29035_THREAD_STACK_SIZE); + struct k_thread thread; + struct k_sem gpio_sem; +#elif defined(CONFIG_ISL29035_TRIGGER_GLOBAL_THREAD) + struct k_work work; +#endif + +#endif /* CONFIG_ISL29035_TRIGGER */ +}; + +struct isl29035_config { + struct i2c_dt_spec i2c; +#if CONFIG_ISL29035_TRIGGER + struct gpio_dt_spec int_gpio; +#endif +}; + +#ifdef CONFIG_ISL29035_TRIGGER +int isl29035_attr_set(const struct device *dev, + enum sensor_channel chan, + enum sensor_attribute attr, + const struct sensor_value *val); + +int isl29035_trigger_set(const struct device *dev, + const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +int isl29035_init_interrupt(const struct device *dev); +#endif + +#endif /* ZEPHYR_DRIVERS_SENSOR_ISL29035_ISL29035_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/scd4x/scd4x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/scd4x/scd4x.h new file mode 100644 index 00000000..3955d202 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/scd4x/scd4x.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2024 Jan Fäh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_SCD4X_SCD4X_H_ +#define ZEPHYR_DRIVERS_SENSOR_SCD4X_SCD4X_H_ + +#include + +#define SCD4X_CMD_REINIT 0 +#define SCD4X_CMD_START_PERIODIC_MEASUREMENT 1 +#define SCD4X_CMD_STOP_PERIODIC_MEASUREMENT 2 +#define SCD4X_CMD_READ_MEASUREMENT 3 +#define SCD4X_CMD_SET_TEMPERATURE_OFFSET 4 +#define SCD4X_CMD_GET_TEMPERATURE_OFFSET 5 +#define SCD4X_CMD_SET_SENSOR_ALTITUDE 6 +#define SCD4X_CMD_GET_SENSOR_ALTITUDE 7 +#define SCD4X_CMD_SET_AMBIENT_PRESSURE 8 +#define SCD4X_CMD_GET_AMBIENT_PRESSURE 9 +#define SCD4X_CMD_FORCED_RECALIB 10 +#define SCD4X_CMD_SET_AUTOMATIC_CALIB_ENABLE 11 +#define SCD4X_CMD_GET_AUTOMATIC_CALIB_ENABLE 12 +#define SCD4X_CMD_LOW_POWER_PERIODIC_MEASUREMENT 13 +#define SCD4X_CMD_GET_DATA_READY_STATUS 14 +#define SCD4X_CMD_PERSIST_SETTINGS 15 +#define SCD4X_CMD_SELF_TEST 16 +#define SCD4X_CMD_FACTORY_RESET 17 +#define SCD4X_CMD_MEASURE_SINGLE_SHOT 18 +#define SCD4X_CMD_MEASURE_SINGLE_SHOT_RHT 19 +#define SCD4X_CMD_POWER_DOWN 10 +#define SCD4X_CMD_WAKE_UP 21 +#define SCD4X_CMD_SET_SELF_CALIB_INITIAL_PERIOD 22 +#define SCD4X_CMD_GET_SELF_CALIB_INITIAL_PERIOD 23 +#define SCD4X_CMD_SET_SELF_CALIB_STANDARD_PERIOD 24 +#define SCD4X_CMD_GET_SELF_CALIB_STANDARD_PERIOD 25 + +#define SCD4X_CRC_POLY 0x31 +#define SCD4X_CRC_INIT 0xFF + +#define SCD4X_STARTUP_TIME_MS 30 + +#define SCD4X_TEMPERATURE_OFFSET_IDX_MAX 20 +#define SCD4X_SENSOR_ALTITUDE_IDX_MAX 3000 +#define SCD4X_AMBIENT_PRESSURE_IDX_MAX 1200 +#define SCD4X_BOOL_IDX_MAX 1 + +#define SCD4X_MAX_TEMP 175 +#define SCD4X_MIN_TEMP -45 + +enum scd4x_model_t { + SCD4X_MODEL_SCD40, + SCD4X_MODEL_SCD41, +}; + +enum scd4x_mode_t { + SCD4X_MODE_NORMAL, + SCD4X_MODE_LOW_POWER, + SCD4X_MODE_SINGLE_SHOT, +}; + +struct scd4x_config { + struct i2c_dt_spec bus; + enum scd4x_model_t model; + enum scd4x_mode_t mode; +}; + +struct scd4x_data { + uint16_t temp_sample; + uint16_t humi_sample; + uint16_t co2_sample; +}; + +struct cmds_t { + uint16_t cmd; + uint16_t cmd_duration_ms; +}; + +const struct cmds_t scd4x_cmds[] = { + {0x3646, 30}, {0x21B1, 0}, {0x3F86, 500}, {0xEC05, 1}, {0x241D, 1}, {0x2318, 1}, + {0x2427, 1}, {0x2322, 1}, {0xE000, 1}, {0xE000, 1}, {0x362F, 400}, {0x2416, 1}, + {0x2313, 1}, {0x21AC, 0}, {0xE4B8, 1}, {0x3615, 800}, {0x3639, 10000}, {0x3632, 1200}, + {0x219D, 5000}, {0x2196, 50}, {0x36E0, 1}, {0x36F6, 30}, {0x2445, 1}, {0x2340, 1}, + {0x244E, 1}, {0x234B, 1}, +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_SCD4X_SCD4X_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/sht4x/sht4x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/sht4x/sht4x.h index 35a11d2f..6409bea2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/sht4x/sht4x.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/sensirion/sht4x/sht4x.h @@ -41,7 +41,7 @@ static const uint8_t measure_cmd[3] = { }; static const uint16_t measure_wait_us[3] = { - 1700, 4500, 8200 + 1600, 4500, 8300 }; /* diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dux12/lis2dux12.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dux12/lis2dux12.h index 82a2a693..7d0d85f3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dux12/lis2dux12.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dux12/lis2dux12.h @@ -51,9 +51,11 @@ struct lis2dux12_data { int sample_y; int sample_z; float gain; + uint8_t range; + uint8_t odr; #ifdef CONFIG_LIS2DUX12_ENABLE_TEMP - int sample_temp; + float sample_temp; #endif #ifdef CONFIG_LIS2DUX12_TRIGGER diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dw12/lis2dw12.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dw12/lis2dw12.h index d5231219..6f9011a4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dw12/lis2dw12.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lis2dw12/lis2dw12.h @@ -58,6 +58,11 @@ #define LIS2DW12_SHIFT_PM1 4 #define LIS2DW12_SHIFT_PMOTHER 2 +/* shift value for 12 bit resolution */ +#define LIS2DW12_SHIFT_TEMP 4 +/* Temperature 12 bit scale factor in uC = 1000000/16 as 1 LSB = C/16 */ +#define LIS2DW12_TEMP_SCALE_FACTOR 62500 + /** * struct lis2dw12_device_config - lis2dw12 hw configuration * @bus_name: Pointer to bus master identifier. @@ -92,18 +97,24 @@ struct lis2dw12_device_config { uint8_t tap_latency; uint8_t tap_quiet; #endif /* CONFIG_LIS2DW12_TAP */ +#ifdef CONFIG_LIS2DW12_SLEEP + uint8_t sleep_duration; +#endif #ifdef CONFIG_LIS2DW12_FREEFALL uint8_t freefall_duration; uint8_t freefall_threshold; #endif /* CONFIG_LIS2DW12_FREEFALL */ -#ifdef CONFIG_LIS2DW12_THRESHOLD +#ifdef CONFIG_LIS2DW12_WAKEUP uint8_t wakeup_duration; -#endif /* CONFIG_LIS2DW12_THRESHOLD */ +#endif /* CONFIG_LIS2DW12_WAKEUP */ #endif /* CONFIG_LIS2DW12_TRIGGER */ }; /* sensor data */ struct lis2dw12_data { + /* temperature raw data */ + int16_t temp; + /* accelerometer raw data */ int16_t acc[3]; /* save sensitivity */ @@ -123,10 +134,14 @@ struct lis2dw12_data { sensor_trigger_handler_t double_tap_handler; const struct sensor_trigger *double_tap_trig; #endif /* CONFIG_LIS2DW12_TAP */ -#ifdef CONFIG_LIS2DW12_THRESHOLD - sensor_trigger_handler_t threshold_handler; - const struct sensor_trigger *threshold_trig; -#endif /* CONFIG_LIS2DW12_THRESHOLD */ +#ifdef CONFIG_LIS2DW12_WAKEUP + sensor_trigger_handler_t motion_handler; + const struct sensor_trigger *motion_trig; +#endif /* CONFIG_LIS2DW12_WAKEUP */ +#ifdef CONFIG_LIS2DW12_SLEEP + sensor_trigger_handler_t stationary_handler; + const struct sensor_trigger *stationary_trig; +#endif #ifdef CONFIG_LIS2DW12_FREEFALL sensor_trigger_handler_t freefall_handler; const struct sensor_trigger *freefall_trig; @@ -148,4 +163,9 @@ int lis2dw12_trigger_set(const struct device *dev, sensor_trigger_handler_t handler); #endif /* CONFIG_LIS2DW12_TRIGGER */ +/* LIS2DW12 specific channels */ +enum sensor_channel_lis2dw12 { + SENSOR_CHAN_LIS2DW12_INT_STATUS = SENSOR_CHAN_PRIV_START, +}; + #endif /* ZEPHYR_DRIVERS_SENSOR_LIS2DW12_LIS2DW12_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/ilps22qs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/ilps22qs.h new file mode 100644 index 00000000..eb2488ee --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/ilps22qs.h @@ -0,0 +1,23 @@ +/* ST Microelectronics ILPS22QS pressure and temperature sensor + * + * Copyright (c) 2023-2024 STMicroelectronics + * Copyright (c) 2023 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "ilps22qs_reg.h" + +#include + +#ifndef ZEPHYR_DRIVERS_SENSOR_ILPS22QS_ILPS22QS_H_ +#define ZEPHYR_DRIVERS_SENSOR_ILPS22QS_ILPS22QS_H_ + +extern const struct lps2xdf_chip_api st_ilps22qs_chip_api; + +int st_ilps22qs_init(const struct device *dev); + +#endif /* ZEPHYR_DRIVERS_SENSOR_ILPS22QS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/lps2xdf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/lps2xdf.h index 10a38a5a..34137d0a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/lps2xdf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lps2xdf/lps2xdf.h @@ -4,10 +4,6 @@ * Copyright (c) 2023 PHYTEC Messtechnik GmbH * * SPDX-License-Identifier: Apache-2.0 - * - * Datasheets: - * https://www.st.com/resource/en/datasheet/lps22df.pdf - * https://www.st.com/resource/en/datasheet/lps28dfw.pdf */ #ifndef ZEPHYR_DRIVERS_SENSOR_LPS2XDF_LPS2XDF_H_ @@ -16,6 +12,10 @@ #include #include +#if DT_HAS_COMPAT_STATUS_OKAY(st_ilps22qs) +#include "ilps22qs_reg.h" +#endif + #if DT_HAS_COMPAT_STATUS_OKAY(st_lps28dfw) #include "lps28dfw_reg.h" #endif @@ -32,6 +32,7 @@ #define LPS2XDF_SWRESET_WAIT_TIME_US 50 #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_ilps22qs, i3c) || \ DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c)) #define ON_I3C_BUS(cfg) (cfg->i3c.bus != NULL) #else @@ -40,8 +41,9 @@ typedef int32_t (*api_lps2xdf_mode_set_odr_raw)(const struct device *dev, uint8_t odr); typedef int32_t (*api_lps2xdf_sample_fetch)(const struct device *dev, enum sensor_channel chan); -typedef void (*api_lps2xdf_handle_interrupt)(const struct device *dev); #ifdef CONFIG_LPS2XDF_TRIGGER +typedef int (*api_lps2xdf_config_interrupt)(const struct device *dev); +typedef void (*api_lps2xdf_handle_interrupt)(const struct device *dev); typedef int (*api_lps2xdf_trigger_set)(const struct device *dev, const struct sensor_trigger *trig, sensor_trigger_handler_t handler); @@ -50,8 +52,9 @@ typedef int (*api_lps2xdf_trigger_set)(const struct device *dev, struct lps2xdf_chip_api { api_lps2xdf_mode_set_odr_raw mode_set_odr_raw; api_lps2xdf_sample_fetch sample_fetch; - api_lps2xdf_handle_interrupt handle_interrupt; #ifdef CONFIG_LPS2XDF_TRIGGER + api_lps2xdf_config_interrupt config_interrupt; + api_lps2xdf_handle_interrupt handle_interrupt; api_lps2xdf_trigger_set trigger_set; #endif }; @@ -60,6 +63,7 @@ struct lps2xdf_chip_api { enum sensor_variant { DEVICE_VARIANT_LPS22DF = 0, DEVICE_VARIANT_LPS28DFW = 1, + DEVICE_VARIANT_ILPS22QS = 2, }; @@ -67,13 +71,16 @@ struct lps2xdf_config { stmdev_ctx_t ctx; union { #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i2c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_ilps22qs, i2c) || \ DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i2c)) const struct i2c_dt_spec i2c; #endif -#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, spi) +#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, spi) ||\ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_ilps22qs, spi)) const struct spi_dt_spec spi; #endif #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_ilps22qs, i3c) || \ DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c)) struct i3c_device_desc **i3c; #endif @@ -89,6 +96,7 @@ struct lps2xdf_config { #endif #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_ilps22qs, i3c) || \ DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c)) struct { const struct device *bus; @@ -120,12 +128,15 @@ struct lps2xdf_data { #endif /* CONFIG_LPS2XDF_TRIGGER */ #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_ilps22qs, i3c) || \ DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c)) struct i3c_device_desc *i3c_dev; #endif }; #ifdef CONFIG_LPS2XDF_TRIGGER +int lps2xdf_config_int(const struct device *dev); + int lps2xdf_trigger_set(const struct device *dev, const struct sensor_trigger *trig, sensor_trigger_handler_t handler); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dso/lsm6dso.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dso/lsm6dso.h index c7f7279d..a721f024 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dso/lsm6dso.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dso/lsm6dso.h @@ -19,13 +19,15 @@ #include #include "lsm6dso_reg.h" -#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso, spi) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso32, spi) #include -#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ +#endif -#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso, i2c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso32, i2c) #include -#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ +#endif #define LSM6DSO_EN_BIT 0x01 #define LSM6DSO_DIS_BIT 0x00 @@ -39,10 +41,12 @@ struct lsm6dso_config { stmdev_ctx_t ctx; union { -#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso, i2c) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso32, i2c) const struct i2c_dt_spec i2c; #endif -#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso, spi) || \ + DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lsm6dso32, spi) const struct spi_dt_spec spi; #endif } stmemsc_cfg; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h index 76132f74..79daeb47 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h @@ -35,6 +35,9 @@ /* Gyro sensor sensitivity grain is 4.375 udps/LSB */ #define GAIN_UNIT_G (4375LL) +int lsm6dsv16x_calc_accel_gain(uint8_t fs); +int lsm6dsv16x_calc_gyro_gain(uint8_t fs); + struct lsm6dsv16x_config { stmdev_ctx_t ctx; union { @@ -52,6 +55,12 @@ struct lsm6dsv16x_config { uint8_t gyro_odr; uint8_t gyro_range; uint8_t drdy_pulsed; +#ifdef CONFIG_LSM6DSV16X_STREAM + uint8_t fifo_wtm; + uint8_t accel_batch : 4; + uint8_t gyro_batch : 4; + uint8_t temp_batch : 2; +#endif #ifdef CONFIG_LSM6DSV16X_TRIGGER const struct gpio_dt_spec int1_gpio; const struct gpio_dt_spec int2_gpio; @@ -98,6 +107,21 @@ struct lsm6dsv16x_data { uint8_t gyro_freq; uint8_t gyro_fs; +#ifdef CONFIG_LSM6DSV16X_STREAM + struct rtio_iodev_sqe *streaming_sqe; + struct rtio *rtio_ctx; + struct rtio_iodev *iodev; + uint64_t fifo_timestamp; + uint8_t fifo_status[2]; + uint16_t fifo_count; + uint8_t fifo_irq; + uint8_t accel_batch_odr : 4; + uint8_t gyro_batch_odr : 4; + uint8_t temp_batch_odr : 2; + uint8_t bus_type : 1; /* I2C is 0, SPI is 1 */ + uint8_t reserved : 5; +#endif + #ifdef CONFIG_LSM6DSV16X_TRIGGER struct gpio_dt_spec *drdy_gpio; @@ -119,6 +143,19 @@ struct lsm6dsv16x_data { #endif /* CONFIG_LSM6DSV16X_TRIGGER */ }; +#ifdef CONFIG_LSM6DSV16X_STREAM +#define BUS_I2C 0 +#define BUS_SPI 1 + +static inline uint8_t lsm6dsv16x_bus_reg(struct lsm6dsv16x_data *data, uint8_t x) +{ + return (data->bus_type == BUS_SPI) ? x | 0x80 : x; +} + +#define LSM6DSV16X_FIFO_ITEM_LEN 7 +#define LSM6DSV16X_FIFO_SIZE(x) (x * LSM6DSV16X_FIFO_ITEM_LEN) +#endif + #if defined(CONFIG_LSM6DSV16X_SENSORHUB) int lsm6dsv16x_shub_init(const struct device *dev); int lsm6dsv16x_shub_fetch_external_devs(const struct device *dev); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h new file mode 100644 index 00000000..1a02af51 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h @@ -0,0 +1,54 @@ +/* ST Microelectronics LSM6DSV16X 6-axis IMU sensor driver + * + * Copyright (c) 2023 Google LLC + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_LSM6DSV16X_DECODER_H_ +#define ZEPHYR_DRIVERS_SENSOR_LSM6DSV16X_DECODER_H_ + +#include +#include + +struct lsm6dsv16x_decoder_header { + uint64_t timestamp; + uint8_t is_fifo: 1; + uint8_t gyro_fs: 4; + uint8_t accel_fs: 2; + uint8_t reserved: 1; +} __attribute__((__packed__)); + +struct lsm6dsv16x_fifo_data { + struct lsm6dsv16x_decoder_header header; + uint8_t int_status; + uint16_t gyro_odr: 4; + uint16_t accel_odr: 4; + uint16_t fifo_count: 11; + uint16_t reserved_1: 5; + uint16_t gyro_batch_odr: 4; + uint16_t accel_batch_odr: 4; + uint16_t temp_batch_odr: 4; + uint16_t reserved_2: 4; +} __attribute__((__packed__)); + +struct lsm6dsv16x_rtio_data { + struct lsm6dsv16x_decoder_header header; + struct { + uint8_t has_accel: 1; /* set if accel channel has data */ + uint8_t has_gyro: 1; /* set if gyro channel has data */ + uint8_t has_temp: 1; /* set if temp channel has data */ + uint8_t reserved: 5; + } __attribute__((__packed__)); + int16_t acc[3]; + int16_t gyro[3]; + int16_t temp; +}; + +int lsm6dsv16x_encode(const struct device *dev, const struct sensor_chan_spec *const channels, + const size_t num_channels, uint8_t *buf); + +int lsm6dsv16x_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder); + +#endif /* ZEPHYR_DRIVERS_SENSOR_LSM6DSV16X_DECODER_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h new file mode 100644 index 00000000..9aa838dd --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h @@ -0,0 +1,20 @@ +/* ST Microelectronics LSM6DSV16X 6-axis IMU sensor driver + * + * Copyright (c) 2023 Google LLC + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_LSM6DSV16X_RTIO_H_ +#define ZEPHYR_DRIVERS_SENSOR_LSM6DSV16X_RTIO_H_ + +#include +#include + +void lsm6dsv16x_submit(const struct device *sensor, struct rtio_iodev_sqe *iodev_sqe); + +void lsm6dsv16x_submit_stream(const struct device *sensor, struct rtio_iodev_sqe *iodev_sqe); +void lsm6dsv16x_stream_irq_handler(const struct device *dev); + +#endif /* ZEPHYR_DRIVERS_SENSOR_LSM6DSV16X_RTIO_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm9ds1/lsm9ds1.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm9ds1/lsm9ds1.h new file mode 100644 index 00000000..a0dde319 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/st/lsm9ds1/lsm9ds1.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Bootlin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_LSM9DS1_LSM9DS1_H_ +#define ZEPHYR_DRIVERS_SENSOR_LSM9DS1_LSM9DS1_H_ + +#include "lsm9ds1_reg.h" + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ + +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) +#include +#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ + +#define GAIN_UNIT_XL (61LL) +#define GAIN_UNIT_G (8750LL) + +#define TEMP_OFFSET 25 /* raw output of zero indicate 25°C */ +#define TEMP_SENSITIVITY 16 /* 16 LSB / °C */ + +#define GYRO_ODR_MASK 0x7 + +struct lsm9ds1_config { + stmdev_ctx_t ctx; + union { +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) + const struct i2c_dt_spec i2c; +#endif +#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) + const struct spi_dt_spec spi; +#endif + } stmemsc_cfg; + uint8_t accel_range; + uint8_t gyro_range; + uint8_t imu_odr; +}; + +struct lsm9ds1_data { + int16_t acc[3]; + uint32_t acc_gain; + int16_t gyro[3]; + uint32_t gyro_gain; + + uint16_t accel_odr; + uint16_t gyro_odr; +#if defined(CONFIG_LSM9DS1_ENABLE_TEMP) + int16_t temp_sample; +#endif +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_LSM9DS1_LSM9DS1_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42670/icm42670.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42670/icm42670.h index e3ca851b..43adc3ef 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42670/icm42670.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42670/icm42670.h @@ -11,8 +11,45 @@ #include #include #include +#include #include +#define ICM42670_BUS_SPI DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm42670, spi) +#define ICM42670_BUS_I2C DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm42670, i2c) + +union icm42670_bus { +#if ICM42670_BUS_SPI + struct spi_dt_spec spi; +#endif +#if ICM42670_BUS_I2C + struct i2c_dt_spec i2c; +#endif +}; + +typedef int (*icm42670_bus_check_fn)(const union icm42670_bus *bus); +typedef int (*icm42670_reg_read_fn)(const union icm42670_bus *bus, + uint16_t reg, uint8_t *data, size_t size); +typedef int (*icm42670_reg_write_fn)(const union icm42670_bus *bus, + uint16_t reg, uint8_t data); + +typedef int (*icm42670_reg_update_fn)(const union icm42670_bus *bus, + uint16_t reg, uint8_t mask, uint8_t data); + +struct icm42670_bus_io { + icm42670_bus_check_fn check; + icm42670_reg_read_fn read; + icm42670_reg_write_fn write; + icm42670_reg_update_fn update; +}; + +#if ICM42670_BUS_SPI +extern const struct icm42670_bus_io icm42670_bus_io_spi; +#endif + +#if ICM42670_BUS_I2C +extern const struct icm42670_bus_io icm42670_bus_io_i2c; +#endif + struct icm42670_data { int16_t accel_x; int16_t accel_y; @@ -45,7 +82,8 @@ struct icm42670_data { }; struct icm42670_config { - struct spi_dt_spec spi; + union icm42670_bus bus; + const struct icm42670_bus_io *bus_io; struct gpio_dt_spec gpio_int; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42688/icm42688.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42688/icm42688.h index 95f0167e..410f0f98 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42688/icm42688.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/tdk/icm42688/icm42688.h @@ -417,7 +417,7 @@ int icm42688_read_all(const struct device *dev, uint8_t data[14]); static inline void icm42688_accel_g(struct icm42688_cfg *cfg, int32_t in, int32_t *out_g, uint32_t *out_ug) { - int32_t sensitivity = 0; /* value equivalent for 1g */ + int32_t sensitivity; switch (cfg->accel_fs) { case ICM42688_DT_ACCEL_FS_2: @@ -432,6 +432,8 @@ static inline void icm42688_accel_g(struct icm42688_cfg *cfg, int32_t in, int32_ case ICM42688_DT_ACCEL_FS_16: sensitivity = 2048; break; + default: + CODE_UNREACHABLE; } /* Whole g's */ @@ -452,7 +454,7 @@ static inline void icm42688_accel_g(struct icm42688_cfg *cfg, int32_t in, int32_ static inline void icm42688_gyro_dps(const struct icm42688_cfg *cfg, int32_t in, int32_t *out_dps, uint32_t *out_udps) { - int64_t sensitivity = 0; /* value equivalent for 10x gyro reading deg/s */ + int64_t sensitivity; switch (cfg->gyro_fs) { case ICM42688_DT_GYRO_FS_2000: @@ -479,6 +481,8 @@ static inline void icm42688_gyro_dps(const struct icm42688_cfg *cfg, int32_t in, case ICM42688_DT_GYRO_FS_15_625: sensitivity = 20972; break; + default: + CODE_UNREACHABLE; } int32_t in10 = in * 10; @@ -502,7 +506,7 @@ static inline void icm42688_gyro_dps(const struct icm42688_cfg *cfg, int32_t in, static inline void icm42688_accel_ms(const struct icm42688_cfg *cfg, int32_t in, int32_t *out_ms, int32_t *out_ums) { - int64_t sensitivity = 0; /* value equivalent for 1g */ + int64_t sensitivity; switch (cfg->accel_fs) { case ICM42688_DT_ACCEL_FS_2: @@ -517,6 +521,8 @@ static inline void icm42688_accel_ms(const struct icm42688_cfg *cfg, int32_t in, case ICM42688_DT_ACCEL_FS_16: sensitivity = 2048; break; + default: + CODE_UNREACHABLE; } /* Convert to micrometers/s^2 */ @@ -540,7 +546,7 @@ static inline void icm42688_accel_ms(const struct icm42688_cfg *cfg, int32_t in, static inline void icm42688_gyro_rads(const struct icm42688_cfg *cfg, int32_t in, int32_t *out_rads, int32_t *out_urads) { - int64_t sensitivity = 0; /* value equivalent for 10x gyro reading deg/s */ + int64_t sensitivity; switch (cfg->gyro_fs) { case ICM42688_DT_GYRO_FS_2000: @@ -567,6 +573,8 @@ static inline void icm42688_gyro_rads(const struct icm42688_cfg *cfg, int32_t in case ICM42688_DT_GYRO_FS_15_625: sensitivity = 20972; break; + default: + CODE_UNREACHABLE; } int64_t in10_rads = (int64_t)in * SENSOR_PI * 10LL; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/ina23x/ina230.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/ina23x/ina230.h index 407c0dd3..1e01283f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/ina23x/ina230.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/ina23x/ina230.h @@ -23,14 +23,16 @@ #include #endif -#define INA230_REG_CONFIG 0x00 -#define INA230_REG_SHUNT_VOLT 0x01 -#define INA230_REG_BUS_VOLT 0x02 -#define INA230_REG_POWER 0x03 -#define INA230_REG_CURRENT 0x04 -#define INA230_REG_CALIB 0x05 -#define INA230_REG_MASK 0x06 -#define INA230_REG_ALERT 0x07 +#define INA230_REG_CONFIG 0x00 +#define INA230_REG_SHUNT_VOLT 0x01 +#define INA230_REG_BUS_VOLT 0x02 +#define INA230_REG_POWER 0x03 +#define INA230_REG_CURRENT 0x04 +#define INA230_REG_CALIB 0x05 +#define INA230_REG_MASK 0x06 +#define INA230_REG_ALERT 0x07 +#define INA236_REG_MANUFACTURER_ID 0x3E +#define INA236_REG_DEVICE_ID 0x3F struct ina230_data { const struct device *dev; @@ -43,7 +45,7 @@ struct ina230_data { struct k_work work; sensor_trigger_handler_t handler_alert; const struct sensor_trigger *trig_alert; -#endif /* CONFIG_INA230_TRIGGER */ +#endif /* CONFIG_INA230_TRIGGER */ }; struct ina230_config { @@ -51,17 +53,18 @@ struct ina230_config { uint16_t config; uint32_t current_lsb; uint16_t cal; + uint8_t power_scale; + uint32_t uv_lsb; #ifdef CONFIG_INA230_TRIGGER bool trig_enabled; uint16_t mask; const struct gpio_dt_spec alert_gpio; uint16_t alert_limit; -#endif /* CONFIG_INA230_TRIGGER */ +#endif /* CONFIG_INA230_TRIGGER */ }; int ina230_trigger_mode_init(const struct device *dev); -int ina230_trigger_set(const struct device *dev, - const struct sensor_trigger *trig, +int ina230_trigger_set(const struct device *dev, const struct sensor_trigger *trig, sensor_trigger_handler_t handler); #endif /* ZEPHYR_DRIVERS_SENSOR_INA23X_INA230_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmag5273/tmag5273.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmag5273/tmag5273.h index cf878a7a..76cc84a9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmag5273/tmag5273.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmag5273/tmag5273.h @@ -195,10 +195,13 @@ /* Register DEVICE_ID */ #define TMAG5273_VER_POS 0 -#define TMAG5273_VER_MSK GENMASK(1, 0) +#define TMAG3001_VER_POS 2 +#define TMAG5273_VER_MSK GENMASK(3, 0) #define TMAG5273_VER_TMAG5273X1 (1 << TMAG5273_VER_POS) #define TMAG5273_VER_TMAG5273X2 (2 << TMAG5273_VER_POS) +#define TMAG5273_VER_TMAG3001X1 (0 << TMAG3001_VER_POS) +#define TMAG5273_VER_TMAG3001X2 (2 << TMAG3001_VER_POS) /* Register CONV_STATUS */ #define TMAG5273_SET_COUNT_POS 5 @@ -242,6 +245,10 @@ #define TMAG5273_MEAS_RANGE_HIGH_MT_VER1 80 #define TMAG5273_MEAS_RANGE_LOW_MT_VER2 133 #define TMAG5273_MEAS_RANGE_HIGH_MT_VER2 266 +#define TMAG3001_MEAS_RANGE_LOW_MT_VER1 40 +#define TMAG3001_MEAS_RANGE_HIGH_MT_VER1 80 +#define TMAG3001_MEAS_RANGE_LOW_MT_VER2 120 +#define TMAG3001_MEAS_RANGE_HIGH_MT_VER2 240 #define TMAG5273_TEMPERATURE_T_SENS_T0 25 #define TMAG5273_TEMPERATURE_T_ADC_T0 17508 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp1075/tmp1075.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp1075/tmp1075.h new file mode 100644 index 00000000..930df939 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp1075/tmp1075.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Arrow Electronics. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_TMP1075_TMP1075_H_ +#define ZEPHYR_DRIVERS_SENSOR_TMP1075_TMP1075_H_ + +#include +#include +#include +#include + +/* Extended resolution is not supported on TMP1075 */ +#define TMP1075_DATA_NORMAL_SHIFT 4 +#define uCELSIUS_IN_CELSIUS 1000000 + +#define TMP1075_REG_TEMPERATURE 0x00 +#define TMP1075_REG_CONFIG 0x01 +#define TMP1075_REG_TLOW 0x02 +#define TMP1075_REG_THIGH 0x03 + +/* Scale in micro degrees Celsius -> 0.0625°C per ADC bit resolution */ +#define TMP1075_TEMP_SCALE 62500 + +/* Macro to set or clear the TMP1075_OS (One-shot conversion mode) bit based on a boolean value */ +#define TMP1075_SET_ONE_SHOT_CONVERSION(reg, enable) \ + ((reg) = ((reg) & ~(1 << 15)) | ((enable) << 15)) + +/* Macro to set the TMP1075_R (Conversion rate) bits */ +#define TMP1075_SET_CONVERSION_RATE(reg, rate) ((reg) |= ((rate) << 13)) + +/* Macro to set the TMP1075_F (Consecutive fault measurements) bits */ +#define TMP1075_SET_CONSECUTIVE_FAULT_MEASUREMENTS(reg, faults) ((reg) |= ((faults) << 11)) + +/* Macro to set or clear the TMP1075_POL (Polarity of output pin) bit based on a boolean value */ +#define TMP1075_SET_ALERT_PIN_POLARITY(reg, activeHigh) \ + ((reg) = ((reg) & ~(1 << 10)) | ((activeHigh) << 10)) + +/* Macro to set or clear the TMP1075_TM (ALERT pin function) bit based on a boolean value */ +#define TMP1075_SET_ALERT_PIN_FUNCTION(reg, interruptMode) \ + ((reg) = ((reg) & ~(1 << 9)) | ((interruptMode) << 9)) + +/* Macro to set or clear the TMP1075_SD (Shutdown mode) bit based on a boolean value */ +#define TMP1075_SET_SHUTDOWN_MODE(reg, shutdown) ((reg) = ((reg) & ~(1 << 8)) | ((shutdown) << 8)) + +struct tmp1075_data { + const struct device *tmp1075_dev; + int16_t sample; + uint16_t config_reg; + const struct sensor_trigger *temp_alert_trigger; + sensor_trigger_handler_t temp_alert_handler; + struct gpio_callback temp_alert_gpio_cb; + bool over_threshold; +}; + +struct tmp1075_config { + const struct i2c_dt_spec bus; + const struct gpio_dt_spec alert_gpio; + uint8_t cr; + uint8_t cf; + bool alert_pol: 1; + bool one_shot: 1; + bool interrupt_mode: 1; + bool shutdown_mode: 1; +}; + +int tmp1075_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +void tmp1075_trigger_handle_alert(const struct device *port, struct gpio_callback *cb, + gpio_port_pins_t pins); + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp116/tmp116.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp116/tmp116.h index 97263af5..6211d9a7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp116/tmp116.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/ti/tmp116/tmp116.h @@ -7,6 +7,8 @@ #ifndef ZEPHYR_DRIVERS_SENSOR_TMP116_TMP116_H_ #define ZEPHYR_DRIVERS_SENSOR_TMP116_TMP116_H_ +#include + #define TMP116_REG_TEMP 0x0 #define TMP116_REG_CFGR 0x1 #define TMP116_REG_HIGH_LIM 0x2 @@ -25,10 +27,21 @@ #define TMP116_DEVICE_ID 0x1116 #define TMP117_DEVICE_ID 0x0117 +#define TMP116_CFGR_AVG (BIT(5) | BIT(6)) +#define TMP116_CFGR_CONV (BIT(7) | BIT(8) | BIT(9)) +#define TMP116_CFGR_MODE (BIT(10) | BIT(11)) #define TMP116_CFGR_DATA_READY BIT(13) #define TMP116_EEPROM_UL_UNLOCK BIT(15) #define TMP116_EEPROM_UL_BUSY BIT(14) +#define TMP116_AVG_1_SAMPLE 0 +#define TMP116_AVG_8_SAMPLES BIT(5) +#define TMP116_AVG_32_SAMPLES BIT(6) +#define TMP116_AVG_64_SAMPLES (BIT(5) | BIT(6)) +#define TMP116_MODE_CONTINUOUS 0 +#define TMP116_MODE_SHUTDOWN BIT(10) +#define TMP116_MODE_ONE_SHOT (BIT(10) | BIT(11)) + struct tmp116_data { uint16_t sample; uint16_t id; @@ -36,6 +49,7 @@ struct tmp116_data { struct tmp116_dev_config { struct i2c_dt_spec bus; + uint16_t odr; }; #endif /* ZEPHYR_DRIVERS_SENSOR_TMP116_TMP116_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/vishay/vcnl36825t/vcnl36825t.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/vishay/vcnl36825t/vcnl36825t.h index e157b14c..beb8a0a9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/vishay/vcnl36825t/vcnl36825t.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/vishay/vcnl36825t/vcnl36825t.h @@ -56,7 +56,10 @@ #define VCNL36825T_PS_MPS_POS 12 #define VCNL36825T_PS_IT_POS 14 -#define VCNL36825T_PS_ST_MSK GENMASK(0, 0) +#define VCNL36825T_PS_ST_MSK GENMASK(0, 0) +#define VCNL36825T_PS_SMART_PERS_MSK GENMASK(1, 1) +#define VCNL36825T_PS_INT_MSK GENMASK(3, 2) +#define VCNL36825T_PS_PERS_MSK GENMASK(5, 4) #define VCNL36825T_PS_ST_START (0 << VCNL36825T_PS_ST_POS) #define VCNL36825T_PS_ST_STOP (1 << VCNL36825T_PS_ST_POS) @@ -65,9 +68,9 @@ #define VCNL36825T_PS_SMART_PERS_ENABLED (1 << VCNL36825T_PS_PS_SMART_PERS_POS) #define VCNL36825T_PS_INT_DISABLE (0 << VCNL36825T_PS_INT_POS) -#define VCNL36825T_PS_INT_THDH_PERS_LATCHED (1 << VCNL36825T_PS_INT_POS) -#define VCNL36825T_PS_INT_THDH_FIRST_LATCHED (2 << VCNL36825T_PS_INT_POS) -#define VCNL36825T_PS_INT_ENABLED (3 << VCNL36825T_PS_INT_POS) +#define VCNL36825T_PS_INT_MODE_LOGIC_HIGH_LOW (1 << VCNL36825T_PS_INT_POS) +#define VCNL36825T_PS_INT_MODE_FIRST_HIGH (2 << VCNL36825T_PS_INT_POS) +#define VCNL36825T_PS_INT_MODE_NORMAL (3 << VCNL36825T_PS_INT_POS) #define VCNL36825T_PS_PERS_1 (0 << VCNL36825T_PS_PERS_POS) #define VCNL36825T_PS_PERS_2 (1 << VCNL36825T_PS_PERS_POS) @@ -105,6 +108,7 @@ #define VCNL36825T_PS_SC_POS 13 #define VCNL36825T_PS_TRIG_MSK GENMASK(5, 5) +#define VCNL36825T_PS_AF_MSK GENMASK(6, 6) #define VCNL36825T_PS_SP_INT_DISABLED (0 << VCNL36825T_PS_SP_INT_POS) #define VCNL36825T_PS_SP_INT_ENABLED (1 << VCNL36825T_PS_SP_INT_POS) @@ -140,6 +144,8 @@ #define VCNL36825T_PS_LPEN_POS 8 #define VCNL36825T_PS_LPPER_POS 9 +#define VCNL36825T_PS_LPEN_MSK GENMASK(8, 8) + #define VCNL36825T_PS_AC_INT_DISABLED (0 << VCNL36825T_PS_AC_INT_POS) #define VCNL36825T_PS_AC_INT_ENABLED (1 << VCNL36825T_PS_AC_INT_POS) @@ -206,21 +212,36 @@ #define VCNL36825T_AC_SUN_MSK GENMASK(14, 14) #define VCNL36825T_AC_BUSY_MSK GENMASK(15, 15) -/* --- */ - #define VCNL36825T_PS_PERIOD_VALUE_MAX_MS 80 #define VCNL36825T_PS_LPPER_VALUE_MIN_MS 40 +/* see application note "Designing the VCNL36825T Into an Application": power up takes 2500 us */ +#define VCNL36825T_POWER_UP_US 2500 + #define VCNL36825T_FORCED_FACTOR_TIME_TO_TRIGGER 0.5 #define VCNL36825T_FORCED_FACTOR_DC_KILL_AMBIENT 3 #define VCNL36825T_FORCED_FACTOR_MEASUREMENT 1 #define VCNL36825T_FORCED_FACTOR_SHUTDOWN 1 -#define VCNL36825T_FORCED_FACTOR_SCALE 10 +#define VCNL36825T_FORCED_FACTOR_SCALE 10 + +/* necessary time to wait before data of a "forced" measurement is available */ #define VCNL36825T_FORCED_FACTOR_SUM \ ((VCNL36825T_FORCED_FACTOR_TIME_TO_TRIGGER + VCNL36825T_FORCED_FACTOR_DC_KILL_AMBIENT + \ VCNL36825T_FORCED_FACTOR_MEASUREMENT + VCNL36825T_FORCED_FACTOR_SHUTDOWN) * \ VCNL36825T_FORCED_FACTOR_SCALE) +#ifdef CONFIG_PM_DEVICE + +#define VCNL36825T_FORCED_WAKEUP_DELAY_MAX_US 1000 +#define VCNL36825T_FORCED_FACTOR_WAKEUP_DELAY 10 + +/* necessary wait time before data for a "forced" measurement is available AFTER the device slept */ +#define VCNL36825T_FORCED_FACTOR_WAKEUP_SUM \ + (VCNL36825T_FORCED_FACTOR_SUM + \ + (VCNL36825T_FORCED_FACTOR_WAKEUP_DELAY * VCNL36825T_FORCED_FACTOR_SCALE)) + +#endif + enum vcnl36825t_operation_mode { VCNL36825T_OPERATION_MODE_AUTO, VCNL36825T_OPERATION_MODE_FORCE, @@ -263,6 +284,12 @@ enum vcnl38625t_laser_current { VCNL36825T_LASER_CURRENT_20MS, }; +enum vcnl36825t_int_mode { + VCNL36825T_INT_MODE_NORMAL, + VCNL36825T_INT_MODE_FIRST_HIGH, + VCNL36825T_INT_MODE_LOGIC_HIGH_LOW, +}; + struct vcnl36825t_config { struct i2c_dt_spec i2c; @@ -279,12 +306,60 @@ struct vcnl36825t_config { enum vcnl38625t_laser_current laser_current; bool high_dynamic_output; bool sunlight_cancellation; + +#if CONFIG_VCNL36825T_TRIGGER + struct gpio_dt_spec int_gpio; + enum vcnl36825t_int_mode int_mode; + uint8_t int_proximity_count; + bool int_smart_persistence; +#endif }; struct vcnl36825t_data { uint16_t proximity; - int meas_timeout_us; /** wait time for finished measurement for "forced" operation mode */ + unsigned int meas_timeout_us; /** wait time for finished measurement in "forced"-mode */ + +#ifdef CONFIG_PM_DEVICE + unsigned int meas_timeout_running_us; + unsigned int meas_timeout_wakeup_us; +#endif + +#if CONFIG_VCNL36825T_TRIGGER + const struct device *dev; + const struct gpio_dt_spec *int_gpio; + + const struct sensor_trigger *int_trigger; + sensor_trigger_handler_t int_handler; + + struct gpio_callback int_gpio_handler; + +#if CONFIG_VCNL36825T_TRIGGER_OWN_THREAD + K_KERNEL_STACK_MEMBER(int_thread_stack, CONFIG_VCNL36825T_THREAD_STACK_SIZE); + struct k_thread int_thread; + struct k_sem int_gpio_sem; +#elif CONFIG_VCNL36825T_TRIGGER_GLOBAL_THREAD + struct k_work int_work; +#endif +#endif }; +int vcnl36825t_read(const struct i2c_dt_spec *spec, uint8_t reg_addr, uint16_t *value); + +int vcnl36825t_write(const struct i2c_dt_spec *spec, uint8_t reg_addr, uint16_t value); + +int vcnl36825t_update(const struct i2c_dt_spec *spec, uint8_t reg_addr, uint16_t mask, + uint16_t value); + +#if CONFIG_VCNL36825T_TRIGGER +int vcnl36825t_trigger_init(const struct device *dev); + +int vcnl36825t_trigger_set(const struct device *dev, const struct sensor_trigger *trig, + sensor_trigger_handler_t handler); + +int vcnl36825t_trigger_attr_set(const struct device *dev, enum sensor_channel chan, + enum sensor_attribute attr, const struct sensor_value *val); + +#endif + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/wsen/wsen_hids_2525020210002/wsen_hids_2525020210002.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/wsen/wsen_hids_2525020210002/wsen_hids_2525020210002.h new file mode 100644 index 00000000..64fba2d4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/sensor/wsen/wsen_hids_2525020210002/wsen_hids_2525020210002.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SENSOR_WSEN_HIDS_2525020210002_WSEN_HIDS_2525020210002_H_ +#define ZEPHYR_DRIVERS_SENSOR_WSEN_HIDS_2525020210002_WSEN_HIDS_2525020210002_H_ + +#include +#include + +#include + +#include "WSEN_HIDS_2525020210002_hal.h" + +#include +#include + +struct hids_2525020210002_data { + /* WE sensor interface configuration */ + WE_sensorInterface_t sensor_interface; + + /* Last humidity sample */ + int32_t humidity; + + /* Last temperature sample */ + int32_t temperature; + + hids_2525020210002_precision_t sensor_precision; + + hids_2525020210002_heater_t sensor_heater; +}; + +struct hids_2525020210002_config { + union { + const struct i2c_dt_spec i2c; + } bus_cfg; + + const hids_2525020210002_precision_t precision; + + const hids_2525020210002_heater_t heater; +}; + +#endif /* ZEPHYR_DRIVERS_SENSOR_WSEN_HIDS_2525020210002_WSEN_HIDS_2525020210002_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_lpc11u6x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_lpc11u6x.h index 8951945e..257846cb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_lpc11u6x.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_lpc11u6x.h @@ -199,20 +199,20 @@ struct lpc11u6x_uartx_shared_irq { }; #if CONFIG_UART_INTERRUPT_DRIVEN && \ - (DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) || \ - DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay)) + (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart1)) || \ + DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart4))) static void lpc11u6x_uartx_isr_config_1(const struct device *dev); #endif /* CONFIG_UART_INTERRUPT_DRIVEN && - * (DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) || - * DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)) + * (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2)) || + * DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))) */ #if CONFIG_UART_INTERRUPT_DRIVEN && \ - (DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) || \ - DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)) + (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2)) || \ + DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))) static void lpc11u6x_uartx_isr_config_2(const struct device *dev); #endif /* CONFIG_UART_INTERRUPT_DRIVEN && - * (DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) || - * DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay)) + * (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart2)) || + * DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart3))) */ #endif /* ZEPHYR_DRIVERS_SERIAL_UART_LPC11U6X_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_ambiq.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_ambiq.h index 62d6d929..5efb0e5e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_ambiq.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_ambiq.h @@ -9,8 +9,11 @@ #include #include +#include +#include #include "uart_pl011_registers.h" +#include #define PWRCTRL_MAX_WAIT_US 5 @@ -50,6 +53,113 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) return pl011_ambiq_clk_set(dev, clk); } +#ifdef CONFIG_PM_DEVICE + +/* Register status record. + * The register status will be preserved to this variable before entering sleep mode, + * and they will be restored after wake up. + */ +typedef struct { + bool bValid; + uint32_t regILPR; + uint32_t regIBRD; + uint32_t regFBRD; + uint32_t regLCRH; + uint32_t regCR; + uint32_t regIFLS; + uint32_t regIER; +} uart_register_state_t; +static uart_register_state_t sRegState[AM_REG_UART_NUM_MODULES]; + +static int uart_ambiq_pm_action(const struct device *dev, enum pm_device_action action) +{ + int key; + + /*Uart module number*/ + uint32_t ui32Module = ((uint32_t)get_uart(dev) == UART0_BASE) ? 0 : 1; + + /*Uart Power module*/ + am_hal_pwrctrl_periph_e eUARTPowerModule = + ((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_UART0 + ui32Module)); + + /*Uart register status*/ + uart_register_state_t *pRegisterStatus = &sRegState[ui32Module]; + + /* Decode the requested power state and update UART operation accordingly.*/ + switch (action) { + + /* Turn on the UART. */ + case PM_DEVICE_ACTION_RESUME: + + /* Make sure we don't try to restore an invalid state.*/ + if (!pRegisterStatus->bValid) { + return -EPERM; + } + + /*The resume and suspend actions may be executed back-to-back, + * so we add a busy wait here for stabilization. + */ + k_busy_wait(100); + + /* Enable power control.*/ + am_hal_pwrctrl_periph_enable(eUARTPowerModule); + + /* Restore UART registers*/ + key = irq_lock(); + + UARTn(ui32Module)->ILPR = pRegisterStatus->regILPR; + UARTn(ui32Module)->IBRD = pRegisterStatus->regIBRD; + UARTn(ui32Module)->FBRD = pRegisterStatus->regFBRD; + UARTn(ui32Module)->LCRH = pRegisterStatus->regLCRH; + UARTn(ui32Module)->CR = pRegisterStatus->regCR; + UARTn(ui32Module)->IFLS = pRegisterStatus->regIFLS; + UARTn(ui32Module)->IER = pRegisterStatus->regIER; + pRegisterStatus->bValid = false; + + irq_unlock(key); + + return 0; + case PM_DEVICE_ACTION_SUSPEND: + + while ((get_uart(dev)->fr & PL011_FR_BUSY) != 0) + ; + + /* Preserve UART registers*/ + key = irq_lock(); + + pRegisterStatus->regILPR = UARTn(ui32Module)->ILPR; + pRegisterStatus->regIBRD = UARTn(ui32Module)->IBRD; + pRegisterStatus->regFBRD = UARTn(ui32Module)->FBRD; + pRegisterStatus->regLCRH = UARTn(ui32Module)->LCRH; + pRegisterStatus->regCR = UARTn(ui32Module)->CR; + pRegisterStatus->regIFLS = UARTn(ui32Module)->IFLS; + pRegisterStatus->regIER = UARTn(ui32Module)->IER; + pRegisterStatus->bValid = true; + + irq_unlock(key); + + /* Clear all interrupts before sleeping as having a pending UART + * interrupt burns power. + */ + UARTn(ui32Module)->IEC = 0xFFFFFFFF; + + /* If the user is going to sleep, certain bits of the CR register + * need to be 0 to be low power and have the UART shut off. + * Since the user either wishes to retain state which takes place + * above or the user does not wish to retain state, it is acceptable + * to set the entire CR register to 0. + */ + UARTn(ui32Module)->CR = 0; + + /* Disable power control.*/ + am_hal_pwrctrl_periph_disable(eUARTPowerModule); + return 0; + default: + return -ENOTSUP; + } +} +#endif /* CONFIG_PM_DEVICE */ + /* Problem: writes to power configure register takes some time to take effective. * Solution: Check device's power status to ensure that register has taken effective. * Note: busy wait is not allowed to use here due to UART is initiated before timer starts. @@ -57,7 +167,8 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) #if defined(CONFIG_SOC_SERIES_APOLLO3X) #define DEVPWRSTATUS_OFFSET 0x10 #define HCPA_MASK 0x4 -#define AMBIQ_UART_DEFINE(n) \ +#define AMBIQ_UART_DEFINE(n) \ + PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \ static int pwr_on_ambiq_uart_##n(void) \ { \ uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \ @@ -75,6 +186,7 @@ static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk) #else #define DEVPWRSTATUS_OFFSET 0x4 #define AMBIQ_UART_DEFINE(n) \ + PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action); \ static int pwr_on_ambiq_uart_##n(void) \ { \ uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_registers.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_registers.h index 7340dd90..6f559d00 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_registers.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/serial/uart_pl011_registers.h @@ -37,9 +37,9 @@ struct pl011_regs { }; static inline -volatile struct pl011_regs *const get_uart(const struct device *dev) +volatile struct pl011_regs *get_uart(const struct device *dev) { - return (volatile struct pl011_regs *const)DEVICE_MMIO_GET(dev); + return (volatile struct pl011_regs *)DEVICE_MMIO_GET(dev); } #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_andes_atcspi200.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_andes_atcspi200.h index e498105f..2790a466 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_andes_atcspi200.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_andes_atcspi200.h @@ -10,6 +10,7 @@ LOG_MODULE_REGISTER(spi_atcspi200); #include "spi_context.h" #include #include +#include #ifdef CONFIG_ANDES_SPI_DMA_MODE #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_context.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_context.h index 1aed4117..b7ade2c3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_context.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_context.h @@ -30,6 +30,10 @@ struct spi_context { const struct spi_config *owner; const struct gpio_dt_spec *cs_gpios; size_t num_cs_gpios; + + /* how to test if the config changed? */ + uint32_t config_frequency; + spi_operation_t config_operation; struct k_sem lock; struct k_sem sync; @@ -78,7 +82,7 @@ struct spi_context { static inline bool spi_context_configured(struct spi_context *ctx, const struct spi_config *config) { - return !!(ctx->config == config); + return !!((ctx->config == config) && (ctx->config_frequency == config->frequency) && (ctx->config_operation == config->operation)); } static inline bool spi_context_is_slave(struct spi_context *ctx) @@ -321,6 +325,10 @@ void spi_context_buffers_setup(struct spi_context *ctx, (void *)ctx->rx_buf, ctx->rx_len); } +/* + * Note: dfs is the number of bytes needed to store a data frame, + * while len is the number of data frames sent. + */ static ALWAYS_INLINE void spi_context_update_tx(struct spi_context *ctx, uint8_t dfs, uint32_t len) { @@ -361,6 +369,10 @@ bool spi_context_tx_buf_on(struct spi_context *ctx) return !!(ctx->tx_buf && ctx->tx_len); } +/* + * Note: dfs is the number of bytes needed to store a data frame, + * while len is the number of data frames received. + */ static ALWAYS_INLINE void spi_context_update_rx(struct spi_context *ctx, uint8_t dfs, uint32_t len) { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_esp32_spim.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_esp32_spim.h index 03da08f6..414e31bb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_esp32_spim.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_esp32_spim.h @@ -30,6 +30,8 @@ struct spi_esp32_config { int duty_cycle; int input_delay_ns; int irq_source; + int irq_priority; + int irq_flags; const struct pinctrl_dev_config *pcfg; clock_control_subsys_t clock_subsys; bool use_iomux; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_litex_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_litex_common.h new file mode 100644 index 00000000..14a52b0a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_litex_common.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2024 Vogl Electronic GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#include "spi_context.h" +#include + +static inline uint8_t get_dfs_value(const struct spi_config *config) +{ + switch (SPI_WORD_SIZE_GET(config->operation)) { + case 8: + return 1; + case 16: + return 2; + case 24: + return 3; + case 32: + return 4; + default: + return 1; + } +} + +static inline void litex_spi_tx_put(uint8_t len, uint32_t *txd, const uint8_t *tx_buf) +{ + switch (len) { + case 4: + *txd = sys_get_be32(tx_buf); + break; + case 3: + *txd = sys_get_be24(tx_buf); + break; + case 2: + *txd = sys_get_be16(tx_buf); + break; + default: + *txd = *tx_buf; + break; + } +} + +static inline void litex_spi_rx_put(uint8_t len, uint32_t *rxd, uint8_t *rx_buf) +{ + switch (len) { + case 4: + sys_put_be32(*rxd, rx_buf); + break; + case 3: + sys_put_be24(*rxd, rx_buf); + break; + case 2: + sys_put_be16(*rxd, rx_buf); + break; + default: + *rx_buf = *rxd; + break; + } +} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_ll_stm32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_ll_stm32.h index d0f6ac46..f37f0b46 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_ll_stm32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_ll_stm32.h @@ -218,27 +218,18 @@ static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi) static inline void ll_func_disable_spi(SPI_TypeDef *spi) { -#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) - if (LL_SPI_IsActiveMasterTransfer(spi)) { - LL_SPI_SuspendMasterTransfer(spi); - while (LL_SPI_IsActiveMasterTransfer(spi)) { - /* NOP */ - } +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_fifo) + /* Flush RX buffer */ + while (ll_func_rx_is_not_empty(spi)) { + (void) LL_SPI_ReceiveData8(spi); } +#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32_spi_fifo) */ LL_SPI_Disable(spi); + while (LL_SPI_IsEnabled(spi)) { /* NOP */ } - - /* Flush RX buffer */ - while (LL_SPI_IsActiveFlag_RXP(spi)) { - (void)LL_SPI_ReceiveData8(spi); - } - LL_SPI_ClearFlag_SUSP(spi); -#else - LL_SPI_Disable(spi); -#endif /* st_stm32h7_spi */ } #endif /* ZEPHYR_DRIVERS_SPI_SPI_LL_STM32_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_nxp_s32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_nxp_s32.h index 68f0943b..4f6fe6a9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_nxp_s32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_nxp_s32.h @@ -7,6 +7,7 @@ #define ZEPHYR_DRIVERS_SPI_SPI_NXP_S32_H_ #include +#include #include #define LOG_LEVEL CONFIG_SPI_LOG_LEVEL diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_sifive.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_sifive.h index 6cb63137..255f76c9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_sifive.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/spi/spi_sifive.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #define SPI_CFG(dev) ((struct spi_sifive_cfg *) ((dev)->config)) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc5xxx_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc5xxx_common.h new file mode 100644 index 00000000..7eafe623 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc5xxx_common.h @@ -0,0 +1,51 @@ +/** + * @file drivers/stepper/adi_tmc/adi_tmc5xxx_common.h + * + * @brief Common TMC5xxx stepper controller driver definitions + */ + +/** + * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_STEPPER_ADI_TMC_ADI_TMC5XXX_COMMON_H_ +#define ZEPHYR_DRIVERS_STEPPER_ADI_TMC_ADI_TMC5XXX_COMMON_H_ + +#include "adi_tmc_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name TMC5xxx module functions + * @anchor TMC5XXX_FUNCTIONS + * + * @{ + */ + +/** + * @brief Calculate the velocity in full clock cycles from the velocity in Hz + * + * @param velocity_hz Velocity in Hz + * @param clock_frequency Clock frequency in Hz + * + * @return Calculated velocity in full clock cycles + */ +static inline uint32_t tmc5xxx_calculate_velocity_from_hz_to_fclk(uint64_t velocity_hz, + uint32_t clock_frequency) +{ + __ASSERT_NO_MSG(clock_frequency); + return (velocity_hz << TMC5XXX_CLOCK_FREQ_SHIFT) / clock_frequency; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_STEPPER_ADI_TMC_ADI_TMC5XXX_COMMON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc_reg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc_reg.h new file mode 100644 index 00000000..eff9f86c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc_reg.h @@ -0,0 +1,151 @@ +/** + * @file drivers/stepper/adi/tmc_reg.h + * + * @brief TMC Registers + * + */ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_STEPPER_ADI_TMC_REG_H_ +#define ZEPHYR_DRIVERS_STEPPER_ADI_TMC_REG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Common Registers for TMC5041 and TMC51XX */ +#if defined(CONFIG_STEPPER_ADI_TMC5041) + +#define TMC5XXX_WRITE_BIT 0x80U +#define TMC5XXX_ADDRESS_MASK 0x7FU + + #define TMC5XXX_CLOCK_FREQ_SHIFT 24 + +#define TMC5XXX_GCONF 0x00 +#define TMC5XXX_GSTAT 0x01 + +#define TMC5XXX_RAMPMODE_POSITIONING_MODE 0 +#define TMC5XXX_RAMPMODE_POSITIVE_VELOCITY_MODE 1 +#define TMC5XXX_RAMPMODE_NEGATIVE_VELOCITY_MODE 2 +#define TMC5XXX_RAMPMODE_HOLD_MODE 3 + +#define TMC5XXX_SG_MIN_VALUE -64 +#define TMC5XXX_SG_MAX_VALUE 63 +#define TMC5XXX_SW_MODE_SG_STOP_ENABLE BIT(10) + +#define TMC5XXX_COOLCONF_SG2_THRESHOLD_VALUE_SHIFT 16 + +#define TMC5XXX_IHOLD_MASK GENMASK(4, 0) +#define TMC5XXX_IHOLD_SHIFT 0 +#define TMC5XXX_IHOLD(n) (((n) << TMC5XXX_IHOLD_SHIFT) & TMC5XXX_IHOLD_MASK) + +#define TMC5XXX_IRUN_MASK GENMASK(12, 8) +#define TMC5XXX_IRUN_SHIFT 8 +#define TMC5XXX_IRUN(n) (((n) << TMC5XXX_IRUN_SHIFT) & TMC5XXX_IRUN_MASK) + +#define TMC5XXX_IHOLDDELAY_MASK GENMASK(19, 16) +#define TMC5XXX_IHOLDDELAY_SHIFT 16 +#define TMC5XXX_IHOLDDELAY(n) (((n) << TMC5XXX_IHOLDDELAY_SHIFT) & TMC5XXX_IHOLDDELAY_MASK) + +#define TMC5XXX_CHOPCONF_DRV_ENABLE_MASK GENMASK(3, 0) +#define TMC5XXX_CHOPCONF_MRES_MASK GENMASK(27, 24) +#define TMC5XXX_CHOPCONF_MRES_SHIFT 24 + +#define TMC5XXX_RAMPSTAT_INT_MASK GENMASK(7, 4) +#define TMC5XXX_RAMPSTAT_INT_SHIFT 4 + +#define TMC5XXX_RAMPSTAT_POS_REACHED_EVENT_MASK BIT(7) +#define TMC5XXX_POS_REACHED_EVENT \ + (TMC5XXX_RAMPSTAT_POS_REACHED_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT) + +#define TMC5XXX_RAMPSTAT_STOP_SG_EVENT_MASK BIT(6) +#define TMC5XXX_STOP_SG_EVENT \ + (TMC5XXX_RAMPSTAT_STOP_SG_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT) + +#define TMC5XXX_RAMPSTAT_STOP_RIGHT_EVENT_MASK BIT(5) +#define TMC5XXX_STOP_RIGHT_EVENT \ + (TMC5XXX_RAMPSTAT_STOP_RIGHT_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT) + +#define TMC5XXX_RAMPSTAT_STOP_LEFT_EVENT_MASK BIT(4) +#define TMC5XXX_STOP_LEFT_EVENT \ + (TMC5XXX_RAMPSTAT_STOP_LEFT_EVENT_MASK >> TMC5XXX_RAMPSTAT_INT_SHIFT) + +#define TMC5XXX_DRV_STATUS_STST_BIT BIT(31) +#define TMC5XXX_DRV_STATUS_SG_RESULT_MASK GENMASK(9, 0) +#define TMC5XXX_DRV_STATUS_SG_STATUS_MASK BIT(24) +#define TMC5XXX_DRV_STATUS_SG_STATUS_SHIFT 24 + +#endif + +#ifdef CONFIG_STEPPER_ADI_TMC5041 + +#define TMC5041_MOTOR_ADDR(m) (0x20 << (m)) +#define TMC5041_MOTOR_ADDR_DRV(m) ((m) << 4) +#define TMC5041_MOTOR_ADDR_PWM(m) ((m) << 3) + +/** + * @name TMC5041 module registers + * @anchor TMC5041_REGISTERS + * + * @{ + */ + +#define TMC5041_GCONF_POSCMP_ENABLE_SHIFT 3 +#define TMC5041_GCONF_TEST_MODE_SHIFT 7 +#define TMC5041_GCONF_SHAFT_SHIFT(n) ((n) ? 8 : 9) +#define TMC5041_LOCK_GCONF_SHIFT 10 + +#define TMC5041_PWMCONF(motor) (0x10 | TMC5041_MOTOR_ADDR_PWM(motor)) +#define TMC5041_PWM_STATUS(motor) (0x11 | TMC5041_MOTOR_ADDR_PWM(motor)) + +#define TMC5041_RAMPMODE(motor) (0x00 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_XACTUAL(motor) (0x01 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_VACTUAL(motor) (0x02 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_VSTART(motor) (0x03 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_A1(motor) (0x04 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_V1(motor) (0x05 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_AMAX(motor) (0x06 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_VMAX(motor) (0x07 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_DMAX(motor) (0x08 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_D1(motor) (0x0A | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_VSTOP(motor) (0x0B | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_TZEROWAIT(motor) (0x0C | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_XTARGET(motor) (0x0D | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_IHOLD_IRUN(motor) (0x10 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_VCOOLTHRS(motor) (0x11 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_VHIGH(motor) (0x12 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_SWMODE(motor) (0x14 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_RAMPSTAT(motor) (0x15 | TMC5041_MOTOR_ADDR(motor)) +#define TMC5041_XLATCH(motor) (0x16 | TMC5041_MOTOR_ADDR(motor)) + +#define TMC5041_MSLUT0(motor) (0x60 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT1(motor) (0x61 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT2(motor) (0x62 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT3(motor) (0x63 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT4(motor) (0x64 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT5(motor) (0x65 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT6(motor) (0x66 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUT7(motor) (0x67 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUTSEL(motor) (0x68 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSLUTSTART(motor) (0x69 | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSCNT(motor) (0x6A | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_MSCURACT(motor) (0x6B | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_CHOPCONF(motor) (0x6C | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_COOLCONF(motor) (0x6D | TMC5041_MOTOR_ADDR_DRV(motor)) +#define TMC5041_DRVSTATUS(motor) (0x6F | TMC5041_MOTOR_ADDR_DRV(motor)) + +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_STEPPER_ADI_TMC_REG_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc_spi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc_spi.h new file mode 100644 index 00000000..c228b619 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/adi_tmc/adi_tmc_spi.h @@ -0,0 +1,63 @@ +/** + * @file drivers/stepper/adi/stepper.h + * + * @brief Private API for Trinamic SPI bus + * + */ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_STEPPER_ADI_TMC_SPI_H_ +#define ZEPHYR_DRIVERS_STEPPER_ADI_TMC_SPI_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief TMC SPI INTERFACE + * @ingroup io_priv_interfaces + * @{ + * + */ + +#include + +/** + * @brief Read a register from the TMC module using the SPI Bus. + * + * @param bus SPI DT information of the bus. + * @param read_address_mask Address Mask for read operation. + * @param register_address Register. + * @param data Pointer to read value. + * + * @return a value from spi_transceive(). + */ +int tmc_spi_read_register(const struct spi_dt_spec *bus, const uint8_t read_address_mask, + const uint8_t register_address, uint32_t *data); + +/** + * @brief Write into a register in the TMC module using the SPI Bus. + * + * @param bus SPI DT information of the bus. + * @param write_bit Write bit for write operation. + * @param register_address Register. + * @param data Value to be written in the register. + * + * @return a value from spi_transceive(). + */ +int tmc_spi_write_register(const struct spi_dt_spec *bus, const uint8_t write_bit, + const uint8_t register_address, const uint32_t data); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_STEPPER_ADI_TMC_SPI_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/step_dir_stepper_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/step_dir_stepper_common.h new file mode 100644 index 00000000..e1cfa773 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/stepper/step_dir_stepper_common.h @@ -0,0 +1,191 @@ +/* + * Copyright 2024 Fabian Blatz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVER_STEPPER_STEP_DIR_STEPPER_COMMON_H_ +#define ZEPHYR_DRIVER_STEPPER_STEP_DIR_STEPPER_COMMON_H_ + +/** + * @brief Stepper Driver APIs + * @defgroup step_dir_stepper Stepper Driver APIs + * @ingroup io_interfaces + * @{ + */ + +#include +#include +#include + +/** + * @brief Common step direction stepper config. + * + * This structure **must** be placed first in the driver's config structure. + */ +struct step_dir_stepper_common_config { + const struct gpio_dt_spec step_pin; + const struct gpio_dt_spec dir_pin; + bool dual_edge; +}; + +/** + * @brief Initialize common step direction stepper config from devicetree instance. + * + * @param node_id The devicetree node identifier. + */ +#define STEP_DIR_STEPPER_DT_COMMON_CONFIG_INIT(node_id) \ + { \ + .step_pin = GPIO_DT_SPEC_GET(node_id, step_gpios), \ + .dir_pin = GPIO_DT_SPEC_GET(node_id, dir_gpios), \ + .dual_edge = DT_PROP_OR(node_id, dual_edge_step, false), \ + } + +/** + * @brief Initialize common step direction stepper config from devicetree instance. + * @param inst Instance. + */ +#define STEP_DIR_STEPPER_DT_INST_COMMON_CONFIG_INIT(inst) \ + STEP_DIR_STEPPER_DT_COMMON_CONFIG_INIT(DT_DRV_INST(inst)) + +/** + * @brief Common step direction stepper data. + * + * This structure **must** be placed first in the driver's data structure. + */ +struct step_dir_stepper_common_data { + const struct device *dev; + struct k_spinlock lock; + enum stepper_direction direction; + enum stepper_run_mode run_mode; + struct k_work_delayable stepper_dwork; + int32_t actual_position; + uint32_t delay_in_us; + int32_t step_count; + stepper_event_callback_t callback; + void *event_cb_user_data; +}; + +/** + * @brief Initialize common step direction stepper data from devicetree instance. + * + * @param node_id The devicetree node identifier. + */ +#define STEP_DIR_STEPPER_DT_COMMON_DATA_INIT(node_id) \ + { \ + .dev = DEVICE_DT_GET(node_id), \ + } + +/** + * @brief Initialize common step direction stepper data from devicetree instance. + * @param inst Instance. + */ +#define STEP_DIR_STEPPER_DT_INST_COMMON_DATA_INIT(inst) \ + STEP_DIR_STEPPER_DT_COMMON_DATA_INIT(DT_DRV_INST(inst)) + +/** + * @brief Validate the offset of the common data structures. + * + * @param config Name of the config structure. + * @param data Name of the data structure. + */ +#define STEP_DIR_STEPPER_STRUCT_CHECK(config, data) \ + BUILD_ASSERT(offsetof(config, common) == 0, \ + "struct step_dir_stepper_common_config must be placed first"); \ + BUILD_ASSERT(offsetof(data, common) == 0, \ + "struct step_dir_stepper_common_data must be placed first"); + +/** + * @brief Common function to initialize a step direction stepper device at init time. + * + * This function must be called at the end of the device init function. + * + * @param dev Step direction stepper device instance. + * + * @retval 0 If initialized successfully. + * @retval -errno Negative errno in case of failure. + */ +int step_dir_stepper_common_init(const struct device *dev); + +/** + * @brief Move the stepper motor by a given number of micro_steps. + * + * @param dev Pointer to the device structure. + * @param micro_steps Number of micro_steps to move. Can be positive or negative. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_move_by(const struct device *dev, const int32_t micro_steps); + +/** + * @brief Set the maximum velocity in micro_steps per second. + * + * @param dev Pointer to the device structure. + * @param velocity Maximum velocity in micro_steps per second. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_set_max_velocity(const struct device *dev, const uint32_t velocity); + +/** + * @brief Set the reference position of the stepper motor. + * + * @param dev Pointer to the device structure. + * @param value The reference position value to set. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_set_reference_position(const struct device *dev, const int32_t value); + +/** + * @brief Get the actual (reference) position of the stepper motor. + * + * @param dev Pointer to the device structure. + * @param value Pointer to a variable where the position value will be stored. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_get_actual_position(const struct device *dev, int32_t *value); + +/** + * @brief Set the absolute target position of the stepper motor. + * + * @param dev Pointer to the device structure. + * @param value The target position to set. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_move_to(const struct device *dev, const int32_t value); + +/** + * @brief Check if the stepper motor is still moving. + * + * @param dev Pointer to the device structure. + * @param is_moving Pointer to a boolean where the movement status will be stored. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_is_moving(const struct device *dev, bool *is_moving); + +/** + * @brief Run the stepper with a given velocity in a given direction. + * + * @param dev Pointer to the device structure. + * @param direction The direction of movement (positive or negative). + * @param velocity The velocity in micro_steps per second. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_run(const struct device *dev, const enum stepper_direction direction, + const uint32_t velocity); + +/** + * @brief Set a callback function for stepper motor events. + * + * This function sets a user-defined callback that will be invoked when a stepper motor event + * occurs. + * + * @param dev Pointer to the device structure. + * @param callback The callback function to set. + * @param user_data Pointer to user-defined data that will be passed to the callback. + * @return 0 on success, or a negative error code on failure. + */ +int step_dir_stepper_common_set_event_callback(const struct device *dev, + stepper_event_callback_t callback, void *user_data); + +/** @} */ + +#endif /* ZEPHYR_DRIVER_STEPPER_STEP_DIR_STEPPER_COMMON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/common/usb_dwc2_hw.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/common/usb_dwc2_hw.h index 88d32a91..fcb35489 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/common/usb_dwc2_hw.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/common/usb_dwc2_hw.h @@ -110,13 +110,12 @@ struct usb_dwc2_reg { volatile uint32_t reserved5[16]; struct usb_dwc2_in_ep in_ep[16]; struct usb_dwc2_out_ep out_ep[16]; + volatile uint32_t reserved6[64]; + volatile uint32_t pcgcctl; }; -/* - * With the maximum number of supported endpoints, register map - * of the controller must be equal to 0x0D00. - */ -BUILD_ASSERT(sizeof(struct usb_dwc2_reg) == 0x0D00); +/* The last register (PCGCCTL) must be at offset 0xE00. */ +BUILD_ASSERT(offsetof(struct usb_dwc2_reg, pcgcctl) == 0x0E00); /* * GET_FIELD/SET_FIELD macros below are intended to be used to define functions @@ -242,6 +241,7 @@ USB_DWC2_SET_FIELD_DEFINE(grstctl_txfnum, GRSTCTL_TXFNUM) #define USB_DWC2_GINTSTS_FETSUSP BIT(USB_DWC2_GINTSTS_FETSUSP_POS) #define USB_DWC2_GINTSTS_INCOMPIP_POS 21UL #define USB_DWC2_GINTSTS_INCOMPIP BIT(USB_DWC2_GINTSTS_INCOMPIP_POS) +#define USB_DWC2_GINTSTS_INCOMPISOOUT USB_DWC2_GINTSTS_INCOMPIP #define USB_DWC2_GINTSTS_INCOMPISOIN_POS 20UL #define USB_DWC2_GINTSTS_INCOMPISOIN BIT(USB_DWC2_GINTSTS_INCOMPISOIN_POS) #define USB_DWC2_GINTSTS_OEPINT_POS 19UL @@ -350,8 +350,27 @@ USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR) /* GHWCFG2 register */ #define USB_DWC2_GHWCFG2 0x0048UL +#define USB_DWC2_GHWCFG2_TKNQDEPTH_POS 26UL +#define USB_DWC2_GHWCFG2_TKNQDEPTH_MASK (0x1FUL << USB_DWC2_GHWCFG2_TKNQDEPTH_POS) +#define USB_DWC2_GHWCFG2_PTXQDEPTH_POS 24UL +#define USB_DWC2_GHWCFG2_PTXQDEPTH_MASK (0x3UL << USB_DWC2_GHWCFG2_PTXQDEPTH_POS) +#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE16 3 +#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE8 2 +#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE4 1 +#define USB_DWC2_GHWCFG2_PTXQDEPTH_QUE2 0 +#define USB_DWC2_GHWCFG2_NPTXQDEPTH_POS 22UL +#define USB_DWC2_GHWCFG2_NPTXQDEPTH_MASK (0x3UL << USB_DWC2_GHWCFG2_NPTXQDEPTH_POS) +#define USB_DWC2_GHWCFG2_NPTXQDEPTH_EIGHT 2 +#define USB_DWC2_GHWCFG2_NPTXQDEPTH_FOUR 1 +#define USB_DWC2_GHWCFG2_NPTXQDEPTH_TWO 0 +#define USB_DWC2_GHWCFG2_MULTIPROCINTRPT_POS 20UL +#define USB_DWC2_GHWCFG2_MULTIPROCINTRPT BIT(USB_DWC2_GHWCFG2_MULTIPROCINTRPT_POS) #define USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS 19UL #define USB_DWC2_GHWCFG2_DYNFIFOSIZING BIT(USB_DWC2_GHWCFG2_DYNFIFOSIZING_POS) +#define USB_DWC2_GHWCFG2_PERIOSUPPORT_POS 18UL +#define USB_DWC2_GHWCFG2_PERIOSUPPORT BIT(USB_DWC2_GHWCFG2_PERIOSUPPORT_POS) +#define USB_DWC2_GHWCFG2_NUMHSTCHNL_POS 14UL +#define USB_DWC2_GHWCFG2_NUMHSTCHNL_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMHSTCHNL_POS) #define USB_DWC2_GHWCFG2_NUMDEVEPS_POS 10UL #define USB_DWC2_GHWCFG2_NUMDEVEPS_MASK (0xFUL << USB_DWC2_GHWCFG2_NUMDEVEPS_POS) #define USB_DWC2_GHWCFG2_FSPHYTYPE_POS 8UL @@ -366,6 +385,8 @@ USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR) #define USB_DWC2_GHWCFG2_HSPHYTYPE_ULPI 2 #define USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUS 1 #define USB_DWC2_GHWCFG2_HSPHYTYPE_NO_HS 0 +#define USB_DWC2_GHWCFG2_SINGPNT_POS 5UL +#define USB_DWC2_GHWCFG2_SINGPNT BIT(USB_DWC2_GHWCFG2_SINGPNT_POS) #define USB_DWC2_GHWCFG2_OTGARCH_POS 3UL #define USB_DWC2_GHWCFG2_OTGARCH_MASK (0x3UL << USB_DWC2_GHWCFG2_OTGARCH_POS) #define USB_DWC2_GHWCFG2_OTGARCH_INTERNALDMA 2 @@ -381,6 +402,10 @@ USB_DWC2_GET_FIELD_AND_IDX_DEFINE(ghwcfg1_epdir, GHWCFG1_EPDIR) #define USB_DWC2_GHWCFG2_OTGMODE_SRPOTG 1 #define USB_DWC2_GHWCFG2_OTGMODE_HNPSRP 0 +USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_tknqdepth, GHWCFG2_TKNQDEPTH) +USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_ptxqdepth, GHWCFG2_PTXQDEPTH) +USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_nptxqdepth, GHWCFG2_NPTXQDEPTH) +USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numhstchnl, GHWCFG2_NUMHSTCHNL) USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_numdeveps, GHWCFG2_NUMDEVEPS) USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_fsphytype, GHWCFG2_FSPHYTYPE) USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_hsphytype, GHWCFG2_HSPHYTYPE) @@ -393,10 +418,20 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg2_otgmode, GHWCFG2_OTGMODE) #define USB_DWC2_GHWCFG3_DFIFODEPTH_MASK (0xFFFFUL << USB_DWC2_GHWCFG3_DFIFODEPTH_POS) #define USB_DWC2_GHWCFG3_LPMMODE_POS 15UL #define USB_DWC2_GHWCFG3_LPMMODE BIT(USB_DWC2_GHWCFG3_LPMMODE_POS) +#define USB_DWC2_GHWCFG3_BCSUPPORT_POS 14UL +#define USB_DWC2_GHWCFG3_BCSUPPORT BIT(USB_DWC2_GHWCFG3_BCSUPPORT_POS) +#define USB_DWC2_GHWCFG3_HSICMODE_POS 13UL +#define USB_DWC2_GHWCFG3_HSICMODE BIT(USB_DWC2_GHWCFG3_HSICMODE_POS) +#define USB_DWC2_GHWCFG3_ADPSUPPORT_POS 12UL +#define USB_DWC2_GHWCFG3_ADPSUPPORT BIT(USB_DWC2_GHWCFG3_ADPSUPPORT_POS) +#define USB_DWC2_GHWCFG3_RSTTYPE_POS 11UL +#define USB_DWC2_GHWCFG3_RSTTYPE BIT(USB_DWC2_GHWCFG3_RSTTYPE_POS) #define USB_DWC2_GHWCFG3_OPTFEATURE_POS 10UL #define USB_DWC2_GHWCFG3_OPTFEATURE BIT(USB_DWC2_GHWCFG3_OPTFEATURE_POS) #define USB_DWC2_GHWCFG3_VNDCTLSUPT_POS 9UL #define USB_DWC2_GHWCFG3_VNDCTLSUPT BIT(USB_DWC2_GHWCFG3_VNDCTLSUPT_POS) +#define USB_DWC2_GHWCFG3_I2CINTSEL_POS 8UL +#define USB_DWC2_GHWCFG3_I2CINTSEL BIT(USB_DWC2_GHWCFG3_I2CINTSEL) #define USB_DWC2_GHWCFG3_OTGEN_POS 7UL #define USB_DWC2_GHWCFG3_OTGEN BIT(USB_DWC2_GHWCFG3_OTGEN_POS) #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_POS 4UL @@ -429,14 +464,46 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_xfersizewidth, GHWCFG3_XFERSIZEWIDTH) /* GHWCFG4 register */ #define USB_DWC2_GHWCFG4 0x0050UL +#define USB_DWC2_GHWCFG4_DESCDMA_POS 31UL +#define USB_DWC2_GHWCFG4_DESCDMA BIT(USB_DWC2_GHWCFG4_DESCDMA_POS) +#define USB_DWC2_GHWCFG4_DESCDMAENABLED_POS 30UL +#define USB_DWC2_GHWCFG4_DESCDMAENABLED BIT(USB_DWC2_GHWCFG4_DESCDMAENABLED_POS) #define USB_DWC2_GHWCFG4_INEPS_POS 26UL #define USB_DWC2_GHWCFG4_INEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_INEPS_POS) #define USB_DWC2_GHWCFG4_DEDFIFOMODE_POS 25UL #define USB_DWC2_GHWCFG4_DEDFIFOMODE BIT(USB_DWC2_GHWCFG4_DEDFIFOMODE_POS) +#define USB_DWC2_GHWCFG4_SESSENDFLTR_POS 24UL +#define USB_DWC2_GHWCFG4_SESSENDFLTR BIT(USB_DWC2_GHWCFG4_SESSENDFLTR_POS) +#define USB_DWC2_GHWCFG4_BVALIDFLTR_POS 23UL +#define USB_DWC2_GHWCFG4_BVALIDFLTR BIT(USB_DWC2_GHWCFG4_BVALIDFLTR_POS) +#define USB_DWC2_GHWCFG4_AVALIDFLTR_POS 22UL +#define USB_DWC2_GHWCFG4_AVALIDFLTR BIT(USB_DWC2_GHWCFG4_AVALIDFLTR_POS) +#define USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS 21UL +#define USB_DWC2_GHWCFG4_VBUSVALIDFLTR BIT(USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS) +#define USB_DWC2_GHWCFG4_IDDGFLTR_POS 20UL +#define USB_DWC2_GHWCFG4_IDDGFLTR BIT(USB_DWC2_GHWCFG4_IDDGFLTR_POS) #define USB_DWC2_GHWCFG4_NUMCTLEPS_POS 16UL #define USB_DWC2_GHWCFG4_NUMCTLEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMCTLEPS_POS) #define USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS 14UL #define USB_DWC2_GHWCFG4_PHYDATAWIDTH_MASK (0x3UL << USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS) +#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS 13UL +#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS) +#define USB_DWC2_GHWCFG4_ACGSUPT_POS 12UL +#define USB_DWC2_GHWCFG4_ACGSUPT BIT(USB_DWC2_GHWCFG4_ACGSUPT_POS) +#define USB_DWC2_GHWCFG4_IPGISOCSUPT_POS 11UL +#define USB_DWC2_GHWCFG4_IPGISOCSUPT BIT(USB_DWC2_GHWCFG4_IPGISOCSUPT_POS) +#define USB_DWC2_GHWCFG4_SERVINTFLOW_POS 10UL +#define USB_DWC2_GHWCFG4_SERVINTFLOW BIT(USB_DWC2_GHWCFG4_SERVINTFLOW_POS) +#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS 9UL +#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1 BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS) +#define USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS 7UL +#define USB_DWC2_GHWCFG4_EXT_HIBERNATION BIT(USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS) +#define USB_DWC2_GHWCFG4_HIBERNATION_POS 6UL +#define USB_DWC2_GHWCFG4_HIBERNATION BIT(USB_DWC2_GHWCFG4_HIBERNATION_POS) +#define USB_DWC2_GHWCFG4_AHBFREQ_POS 5UL +#define USB_DWC2_GHWCFG4_AHBFREQ BIT(USB_DWC2_GHWCFG4_AHBFREQ_POS) +#define USB_DWC2_GHWCFG4_PARTIALPWRDN_POS 4UL +#define USB_DWC2_GHWCFG4_PARTIALPWRDN BIT(USB_DWC2_GHWCFG4_PARTIALPWRDN_POS) #define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS 0UL #define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS) @@ -445,6 +512,130 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numctleps, GHWCFG4_NUMCTLEPS) USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_phydatawidth, GHWCFG4_PHYDATAWIDTH) USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numdevperioeps, GHWCFG4_NUMDEVPERIOEPS) +/* LPM Config Register */ +#define USB_DWC2_GLPMCFG 0x0054UL +#define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS 29UL +#define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS BIT(USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS) +#define USB_DWC2_GLPMCFG_LPM_ENBESL_POS 28UL +#define USB_DWC2_GLPMCFG_LPM_ENBESL BIT(USB_DWC2_GLPMCFG_LPM_ENBESL_POS) +#define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS 25UL +#define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS) +#define USB_DWC2_GLPMCFG_SNDLPM_POS 24UL +#define USB_DWC2_GLPMCFG_SNDLPM BIT(USB_DWC2_GLPMCFG_SNDLPM_POS) +/* Host mode LPM Retry Count and LPM Channel Index */ +#define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS 21UL +#define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS) +#define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS 17UL +#define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_MASK (0xFUL << USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS) +/* Device mode LPM Accept Control */ +#define USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS 23UL +#define USB_DWC2_GLPMCFG_LPM_ACK_BULK BIT(USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS) +#define USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS 22UL +#define USB_DWC2_GLPMCFG_LPM_ACK_ISO BIT(USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS) +#define USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS 21UL +#define USB_DWC2_GLPMCFG_LPM_NYET_CTRL BIT(USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS) +#define USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS 20UL +#define USB_DWC2_GLPMCFG_LPM_ACK_INTR BIT(USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS) +#define USB_DWC2_GLPMCFG_L1RESUMEOK_POS 16UL +#define USB_DWC2_GLPMCFG_L1RESUMEOK BIT(USB_DWC2_GLPMCFG_L1RESUMEOK_POS) +#define USB_DWC2_GLPMCFG_SLPSTS_POS 15UL +#define USB_DWC2_GLPMCFG_SLPSTS BIT(USB_DWC2_GLPMCFG_SLPSTS_POS) +#define USB_DWC2_GLPMCFG_COREL1RES_POS 13UL +#define USB_DWC2_GLPMCFG_COREL1RES_MASK (0x3UL << USB_DWC2_GLPMCFG_COREL1RES_POS) +#define USB_DWC2_GLPMCFG_COREL1RES_ERROR 0 +#define USB_DWC2_GLPMCFG_COREL1RES_STALL 1 +#define USB_DWC2_GLPMCFG_COREL1RES_NYET 2 +#define USB_DWC2_GLPMCFG_COREL1RES_ACK 3 +#define USB_DWC2_GLPMCFG_HIRD_THRES_POS 8UL +#define USB_DWC2_GLPMCFG_HIRD_THRES_MASK (0x1FUL << USB_DWC2_GLPMCFG_HIRD_THRES_POS) +#define USB_DWC2_GLPMCFG_ENBLSLPM_POS 7UL +#define USB_DWC2_GLPMCFG_ENBLSLPM BIT(USB_DWC2_GLPMCFG_ENBLSLPM_POS) +#define USB_DWC2_GLPMCFG_BREMOTEWAKE_POS 6UL +#define USB_DWC2_GLPMCFG_BREMOTEWAKE BIT(USB_DWC2_GLPMCFG_BREMOTEWAKE_POS) +#define USB_DWC2_GLPMCFG_HIRD_POS 2UL +#define USB_DWC2_GLPMCFG_HIRD_MASK (0xFUL << USB_DWC2_GLPMCFG_HIRD_POS) +#define USB_DWC2_GLPMCFG_APPL1RES_POS 1UL +#define USB_DWC2_GLPMCFG_APPL1RES BIT(USB_DWC2_GLPMCFG_APPL1RES_POS) +#define USB_DWC2_GLPMCFG_LPMCAP_POS 0UL +#define USB_DWC2_GLPMCFG_LPMCAP BIT(USB_DWC2_GLPMCFG_LPMCAP_POS) + +USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retrycnt_sts, GLPMCFG_LPM_RETRYCNT_STS) +USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT) +USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX) +USB_DWC2_GET_FIELD_DEFINE(glpmcfg_corel1res, GLPMCFG_COREL1RES) +USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES) +USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD) +USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT) +USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX) +USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES) +USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD) + +/* Global Power Down Register */ +#define USB_DWC2_GPWRDN 0x0058UL +#define USB_DWC2_GPWRDN_MULTVALIDBC_POS 24UL +#define USB_DWC2_GPWRDN_MULTVALIDBC_MASK (0x1FUL << USB_DWC2_GPWRDN_MULTVALIDBC_POS) +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_0 0 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C 1 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B 2 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A 4 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_GND 8 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A_GND 12 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_FLOAT 16 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C_FLOAT 17 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B_FLOAT 18 +#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_1 31 +#define USB_DWC2_GPWRDN_BSESSVLD_POS 22UL +#define USB_DWC2_GPWRDN_BSESSVLD BIT(USB_DWC2_GPWRDN_BSESSVLD_POS) +#define USB_DWC2_GPWRDN_IDDIG_POS 21UL +#define USB_DWC2_GPWRDN_IDDIG BIT(USB_DWC2_GPWRDN_IDDIG_POS) +#define USB_DWC2_GPWRDN_LINESTATE_POS 19UL +#define USB_DWC2_GPWRDN_LINESTATE_MASK (0x3UL << USB_DWC2_GPWRDN_LINESTATE_POS) +#define USB_DWC2_GPWRDN_LINESTATE_DM0DP0 0 +#define USB_DWC2_GPWRDN_LINESTATE_DM0DP1 1 +#define USB_DWC2_GPWRDN_LINESTATE_DM1DP0 2 +#define USB_DWC2_GPWRDN_LINESTATE_NOT_DEFINED 3 +#define USB_DWC2_GPWRDN_STSCHNGINTMSK_POS 18UL +#define USB_DWC2_GPWRDN_STSCHNGINTMSK BIT(USB_DWC2_GPWRDN_STSCHNGINTMSK_POS) +#define USB_DWC2_GPWRDN_STSCHNGINT_POS 17UL +#define USB_DWC2_GPWRDN_STSCHNGINT BIT(USB_DWC2_GPWRDN_STSCHNGINT_POS) +#define USB_DWC2_GPWRDN_SRPDETECTMSK_POS 16UL +#define USB_DWC2_GPWRDN_SRPDETECTMSK BIT(USB_DWC2_GPWRDN_SRPDETECTMSK_POS) +#define USB_DWC2_GPWRDN_SRPDETECT_POS 15UL +#define USB_DWC2_GPWRDN_SRPDETECT BIT(USB_DWC2_GPWRDN_SRPDETECT_POS) +#define USB_DWC2_GPWRDN_CONNDETMSK_POS 14UL +#define USB_DWC2_GPWRDN_CONNDETMSK BIT(USB_DWC2_GPWRDN_CONNDETMSK_POS) +#define USB_DWC2_GPWRDN_CONNECTDET_POS 13UL +#define USB_DWC2_GPWRDN_CONNECTDET BIT(USB_DWC2_GPWRDN_CONNECTDET_POS) +#define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS 12UL +#define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK BIT(USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS) +#define USB_DWC2_GPWRDN_DISCONNECTDETECT_POS 11UL +#define USB_DWC2_GPWRDN_DISCONNECTDETECT BIT(USB_DWC2_GPWRDN_DISCONNECTDETECT_POS) +#define USB_DWC2_GPWRDN_RESETDETMSK_POS 10UL +#define USB_DWC2_GPWRDN_RESETDETMSK BIT(USB_DWC2_GPWRDN_RESETDETMSK_POS) +#define USB_DWC2_GPWRDN_RESETDETECTED_POS 9UL +#define USB_DWC2_GPWRDN_RESETDETECTED BIT(USB_DWC2_GPWRDN_RESETDETECTED_POS) +#define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS 8UL +#define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK BIT(USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS) +#define USB_DWC2_GPWRDN_LNSTSCHNG_POS 7UL +#define USB_DWC2_GPWRDN_LNSTSCHNG BIT(USB_DWC2_GPWRDN_LNSTSCHNG_POS) +#define USB_DWC2_GPWRDN_DISABLEVBUS_POS 6UL +#define USB_DWC2_GPWRDN_DISABLEVBUS BIT(USB_DWC2_GPWRDN_DISABLEVBUS_POS) +#define USB_DWC2_GPWRDN_PWRDNSWTCH_POS 5UL +#define USB_DWC2_GPWRDN_PWRDNSWTCH BIT(USB_DWC2_GPWRDN_PWRDNSWTCH_POS) +#define USB_DWC2_GPWRDN_PWRDNRST_N_POS 4UL +#define USB_DWC2_GPWRDN_PWRDNRST_N BIT(USB_DWC2_GPWRDN_PWRDNRST_N_POS) +#define USB_DWC2_GPWRDN_PWRDNCLMP_POS 3UL +#define USB_DWC2_GPWRDN_PWRDNCLMP BIT(USB_DWC2_GPWRDN_PWRDNCLMP_POS) +#define USB_DWC2_GPWRDN_RESTORE_POS 2UL +#define USB_DWC2_GPWRDN_RESTORE BIT(USB_DWC2_GPWRDN_RESTORE_POS) +#define USB_DWC2_GPWRDN_PMUACTV_POS 1UL +#define USB_DWC2_GPWRDN_PMUACTV BIT(USB_DWC2_GPWRDN_PMUACTV_POS) +#define USB_DWC2_GPWRDN_PMUINTSEL_POS 0UL +#define USB_DWC2_GPWRDN_PMUINTSEL BIT(USB_DWC2_GPWRDN_PMUINTSEL_POS) + +USB_DWC2_GET_FIELD_DEFINE(gpwrdn_multvalidbc, GPWRDN_MULTVALIDBC) +USB_DWC2_GET_FIELD_DEFINE(gpwrdn_linestate, GPWRDN_LINESTATE) + /* GDFIFOCFG register */ #define USB_DWC2_GDFIFOCFG 0x005CUL #define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS 16UL @@ -565,13 +756,23 @@ USB_DWC2_SET_FIELD_DEFINE(dctl_tstctl, DCTL_TSTCTL) /* Device status register */ #define USB_DWC2_DSTS 0x0808UL +#define USB_DWC2_DSTS_DEVLNSTS_POS 22UL +#define USB_DWC2_DSTS_DEVLNSTS_MASK (0x3UL << USB_DWC2_DSTS_DEVLNSTS_POS) +#define USB_DWC2_DSTS_SOFFN_POS 8UL +#define USB_DWC2_DSTS_SOFFN_MASK (0x3FFFUL << USB_DWC2_DSTS_SOFFN_POS) +#define USB_DWC2_DSTS_ERRTICERR_POS 3UL +#define USB_DWC2_DSTS_ERRTICERR BIT(USB_DWC2_DSTS_ERRTICERR_POS) #define USB_DWC2_DSTS_ENUMSPD_POS 1UL #define USB_DWC2_DSTS_ENUMSPD_MASK (0x3UL << USB_DWC2_DSTS_ENUMSPD_POS) #define USB_DWC2_DSTS_ENUMSPD_HS3060 0 #define USB_DWC2_DSTS_ENUMSPD_FS3060 1 #define USB_DWC2_DSTS_ENUMSPD_LS6 2 #define USB_DWC2_DSTS_ENUMSPD_FS48 3 +#define USB_DWC2_DSTS_SUSPSTS_POS 0UL +#define USB_DWC2_DSTS_SUSPSTS BIT(USB_DWC2_DSTS_SUSPSTS_POS) +USB_DWC2_GET_FIELD_DEFINE(dsts_devlnsts, DSTS_DEVLNSTS) +USB_DWC2_GET_FIELD_DEFINE(dsts_soffn, DSTS_SOFFN) USB_DWC2_GET_FIELD_DEFINE(dsts_enumspd, DSTS_ENUMSPD) /* Device all endpoints interrupt registers */ @@ -622,8 +823,10 @@ USB_DWC2_SET_FIELD_DEFINE(dthrctl_txthrlen, DTHRCTL_TXTHRLEN) #define USB_DWC2_DEPCTL_EPDIS BIT(USB_DWC2_DEPCTL_EPDIS_POS) #define USB_DWC2_DEPCTL_SETD1PID_POS 29UL #define USB_DWC2_DEPCTL_SETD1PID BIT(USB_DWC2_DEPCTL_SETD1PID_POS) +#define USB_DWC2_DEPCTL_SETODDFR USB_DWC2_DEPCTL_SETD1PID #define USB_DWC2_DEPCTL_SETD0PID_POS 28UL #define USB_DWC2_DEPCTL_SETD0PID BIT(USB_DWC2_DEPCTL_SETD0PID_POS) +#define USB_DWC2_DEPCTL_SETEVENFR USB_DWC2_DEPCTL_SETD0PID #define USB_DWC2_DEPCTL_SNAK_POS 27UL #define USB_DWC2_DEPCTL_SNAK BIT(USB_DWC2_DEPCTL_SNAK_POS) #define USB_DWC2_DEPCTL_CNAK_POS 26UL @@ -730,40 +933,91 @@ USB_DWC2_SET_FIELD_DEFINE(depctl_mps, DEPCTL_MPS) #define USB_DWC2_DOEPINT_XFERCOMPL_POS 0UL #define USB_DWC2_DOEPINT_XFERCOMPL BIT(USB_DWC2_DOEPINT_XFERCOMPL_POS) -/* - * Device IN/OUT control endpoint transfer size register - */ +/* Device IN control endpoint transfer size register */ #define USB_DWC2_DIEPTSIZ0 0x0910UL +#define USB_DWC2_DIEPTSIZ0_PKTCNT_POS 19UL +#define USB_DWC2_DIEPTSIZ0_PKTCNT_MASK (0x3UL << USB_DWC2_DIEPTSIZ0_PKTCNT_POS) +#define USB_DWC2_DIEPTSIZ0_XFERSIZE_POS 0UL +#define USB_DWC2_DIEPTSIZ0_XFERSIZE_MASK 0x7FUL + +USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_pktcnt, DIEPTSIZ0_PKTCNT) +USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DIEPTSIZ0_XFERSIZE) + +/* Device OUT control endpoint transfer size register */ #define USB_DWC2_DOEPTSIZ0 0x0B10UL #define USB_DWC2_DOEPTSIZ0_SUPCNT_POS 29UL #define USB_DWC2_DOEPTSIZ0_SUPCNT_MASK (0x3UL << USB_DWC2_DOEPTSIZ0_SUPCNT_POS) #define USB_DWC2_DOEPTSIZ0_PKTCNT_POS 19UL #define USB_DWC2_DOEPTSIZ0_PKTCNT_MASK (0x1UL << USB_DWC2_DOEPTSIZ0_PKTCNT_POS) -#define USB_DWC2_DIEPTSIZ0_PKTCNT_POS 19UL -#define USB_DWC2_DIEPTSIZ0_PKTCNT_MASK (0x3UL << USB_DWC2_DIEPTSIZ0_PKTCNT_POS) -#define USB_DWC2_DEPTSIZ0_XFERSIZE_POS 0UL -#define USB_DWC2_DEPTSIZ0_XFERSIZE_MASK 0x7FUL +#define USB_DWC2_DOEPTSIZ0_XFERSIZE_POS 0UL +#define USB_DWC2_DOEPTSIZ0_XFERSIZE_MASK 0x7FUL USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_supcnt, DOEPTSIZ0_SUPCNT) USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_pktcnt, DOEPTSIZ0_PKTCNT) -USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_xfersize, DEPTSIZ0_XFERSIZE) -USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_pktcnt, DIEPTSIZ0_PKTCNT) -USB_DWC2_GET_FIELD_DEFINE(dieptsiz0_xfersize, DEPTSIZ0_XFERSIZE) +USB_DWC2_GET_FIELD_DEFINE(doeptsiz0_xfersize, DOEPTSIZ0_XFERSIZE) /* - * Device IN/OUT endpoint transfer size register - * IN at offsets 0x0910 + (0x20 * n), n = 1 .. x, - * OUT at offsets 0x0B10 + (0x20 * n), n = 1 .. x + * Device IN endpoint transfer size register + * at offsets 0x0910 + (0x20 * n), n = 1 .. x + */ +#define USB_DWC2_DIEPTSIZN_MC_POS 29UL +#define USB_DWC2_DIEPTSIZN_MC_MASK (0x3UL << USB_DWC2_DIEPTSIZN_MC_POS) +#define USB_DWC2_DIEPTSIZN_PKTCNT_POS 19UL +#define USB_DWC2_DIEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DIEPTSIZN_PKTCNT_POS) +#define USB_DWC2_DIEPTSIZN_XFERSIZE_POS 0UL +#define USB_DWC2_DIEPTSIZN_XFERSIZE_MASK 0x7FFFFUL + +USB_DWC2_GET_FIELD_DEFINE(dieptsizn_mc, DIEPTSIZN_MC) +USB_DWC2_GET_FIELD_DEFINE(dieptsizn_pktcnt, DIEPTSIZN_PKTCNT) +USB_DWC2_GET_FIELD_DEFINE(dieptsizn_xfersize, DIEPTSIZN_XFERSIZE) +USB_DWC2_SET_FIELD_DEFINE(dieptsizn_mc, DIEPTSIZN_MC) +USB_DWC2_SET_FIELD_DEFINE(dieptsizn_pktcnt, DIEPTSIZN_PKTCNT) +USB_DWC2_SET_FIELD_DEFINE(dieptsizn_xfersize, DIEPTSIZN_XFERSIZE) + +/* + * Device OUT endpoint transfer size register + * at offsets 0x0B10 + (0x20 * n), n = 1 .. x */ -#define USB_DWC2_DEPTSIZN_PKTCNT_POS 19UL -#define USB_DWC2_DEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DEPTSIZN_PKTCNT_POS) -#define USB_DWC2_DEPTSIZN_XFERSIZE_POS 0UL -#define USB_DWC2_DEPTSIZN_XFERSIZE_MASK 0x7FFFFUL - -USB_DWC2_GET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT) -USB_DWC2_GET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE) -USB_DWC2_SET_FIELD_DEFINE(deptsizn_pktcnt, DEPTSIZN_PKTCNT) -USB_DWC2_SET_FIELD_DEFINE(deptsizn_xfersize, DEPTSIZN_XFERSIZE) +#define USB_DWC2_DOEPTSIZN_RXDPID_POS 29UL +#define USB_DWC2_DOEPTSIZN_RXDPID_MASK (0x3UL << USB_DWC2_DOEPTSIZN_RXDPID_POS) +#define USB_DWC2_DOEPTSIZN_RXDPID_MDATA 3 +#define USB_DWC2_DOEPTSIZN_RXDPID_DATA1 2 +#define USB_DWC2_DOEPTSIZN_RXDPID_DATA2 1 +#define USB_DWC2_DOEPTSIZN_RXDPID_DATA0 0 +#define USB_DWC2_DOEPTSIZN_PKTCNT_POS 19UL +#define USB_DWC2_DOEPTSIZN_PKTCNT_MASK (0x3FFUL << USB_DWC2_DOEPTSIZN_PKTCNT_POS) +#define USB_DWC2_DOEPTSIZN_XFERSIZE_POS 0UL +#define USB_DWC2_DOEPTSIZN_XFERSIZE_MASK 0x7FFFFUL + +USB_DWC2_GET_FIELD_DEFINE(doeptsizn_rxdpid, DOEPTSIZN_RXDPID) +USB_DWC2_GET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT) +USB_DWC2_GET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE) +USB_DWC2_SET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT) +USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE) + +/* Power and Clock Gating Control Register */ +#define USB_DWC2_PCGCCTL 0x0E00UL +#define USB_DWC2_PCGCCTL_RESTOREVALUE_POS 14UL +#define USB_DWC2_PCGCCTL_RESTOREVALUE_MASK (0x3FFFFUL << USB_DWC2_PCGCCTL_RESTOREVALUE_POS) +#define USB_DWC2_PCGCCTL_ESSREGRESTORED_POS 13UL +#define USB_DWC2_PCGCCTL_ESSREGRESTORED BIT(USB_DWC2_PCGCCTL_ESSREGRESTORED_POS) +#define USB_DWC2_PCGCCTL_RESTOREMODE_POS 9UL +#define USB_DWC2_PCGCCTL_RESTOREMODE BIT(USB_DWC2_PCGCCTL_RESTOREMODE_POS) +#define USB_DWC2_PCGCCTL_L1SUSPENDED_POS 7UL +#define USB_DWC2_PCGCCTL_L1SUSPENDED BIT(USB_DWC2_PCGCCTL_L1SUSPENDED_POS) +#define USB_DWC2_PCGCCTL_PHYSLEEP_POS 6UL +#define USB_DWC2_PCGCCTL_PHYSLEEP BIT(USB_DWC2_PCGCCTL_PHYSLEEP_POS) +#define USB_DWC2_PCGCCTL_ENBL_L1GATING_POS 5UL +#define USB_DWC2_PCGCCTL_ENBL_L1GATING BIT(USB_DWC2_PCGCCTL_ENBL_L1GATING_POS) +#define USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS 3UL +#define USB_DWC2_PCGCCTL_RSTPDWNMODULE BIT(USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS) +#define USB_DWC2_PCGCCTL_GATEHCLK_POS 1UL +#define USB_DWC2_PCGCCTL_GATEHCLK BIT(USB_DWC2_PCGCCTL_GATEHCLK_POS) +#define USB_DWC2_PCGCCTL_STOPPCLK_POS 0UL +#define USB_DWC2_PCGCCTL_STOPPCLK BIT(USB_DWC2_PCGCCTL_STOPPCLK_POS) + +USB_DWC2_GET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE) +USB_DWC2_SET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE) /* * Device IN/OUT endpoint transfer size register diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_common.h index 76614ac8..19cad23b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_common.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_common.h @@ -325,7 +325,7 @@ bool udc_ctrl_stage_is_status_in(const struct device *dev); * * @param[in] dev Pointer to device struct of the driver instance * - * @return true if stage is Data Stage IN + * @return true if stage is Data Stage OUT */ bool udc_ctrl_stage_is_status_out(const struct device *dev); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2.h index 07cd71bc..87e71f81 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2.h @@ -30,6 +30,10 @@ struct dwc2_vendor_quirks { int (*caps)(const struct device *dev); /* Called while waiting for bits that require PHY to be clocked */ int (*is_phy_clk_off)(const struct device *dev); + /* Called after hibernation entry sequence */ + int (*post_hibernation_entry)(const struct device *dev); + /* Called before hibernation exit sequence */ + int (*pre_hibernation_exit)(const struct device *dev); }; /* Driver configuration per instance */ @@ -72,5 +76,7 @@ DWC2_QUIRK_FUNC_DEFINE(shutdown) DWC2_QUIRK_FUNC_DEFINE(irq_clear) DWC2_QUIRK_FUNC_DEFINE(caps) DWC2_QUIRK_FUNC_DEFINE(is_phy_clk_off) +DWC2_QUIRK_FUNC_DEFINE(post_hibernation_entry) +DWC2_QUIRK_FUNC_DEFINE(pre_hibernation_exit) #endif /* ZEPHYR_DRIVERS_USB_UDC_DWC2_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2_vendor_quirks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2_vendor_quirks.h index 57ff4c4d..f45404c2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2_vendor_quirks.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb/udc/udc_dwc2_vendor_quirks.h @@ -121,7 +121,8 @@ DT_INST_FOREACH_STATUS_OKAY(QUIRK_STM32F4_FSOTG_DEFINE) * On USBHS, we cannot access the DWC2 register until VBUS is detected and * valid. If the user tries to force usbd_enable() and the corresponding * udc_enable() without a "VBUS ready" notification, the event wait will block - * until a valid VBUS signal is detected. + * until a valid VBUS signal is detected or until the + * CONFIG_UDC_DWC2_USBHS_VBUS_READY_TIMEOUT timeout expires. */ static K_EVENT_DEFINE(usbhs_events); #define USBHS_VBUS_READY BIT(0) @@ -182,15 +183,27 @@ static inline int usbhs_enable_nrfs_service(const struct device *dev) static inline int usbhs_enable_core(const struct device *dev) { NRF_USBHS_Type *wrapper = USBHS_DT_WRAPPER_REG_ADDR(0); + k_timeout_t timeout = K_FOREVER; + + #if CONFIG_NRFS_HAS_VBUS_DETECTOR_SERVICE + if (CONFIG_UDC_DWC2_USBHS_VBUS_READY_TIMEOUT) { + timeout = K_MSEC(CONFIG_UDC_DWC2_USBHS_VBUS_READY_TIMEOUT); + } + #endif if (!k_event_wait(&usbhs_events, USBHS_VBUS_READY, false, K_NO_WAIT)) { LOG_WRN("VBUS is not ready, block udc_enable()"); - k_event_wait(&usbhs_events, USBHS_VBUS_READY, false, K_FOREVER); + if (!k_event_wait(&usbhs_events, USBHS_VBUS_READY, false, timeout)) { + return -ETIMEDOUT; + } } wrapper->ENABLE = USBHS_ENABLE_PHY_Msk | USBHS_ENABLE_CORE_Msk; wrapper->TASKS_START = 1UL; + /* Wait for clock to start to avoid hang on too early register read */ + k_busy_wait(1); + /* Enable interrupts */ wrapper->INTENSET = 1UL; @@ -249,6 +262,36 @@ static inline int usbhs_is_phy_clk_off(const struct device *dev) return !k_event_test(&usbhs_events, USBHS_VBUS_READY); } +static inline int usbhs_post_hibernation_entry(const struct device *dev) +{ + const struct udc_dwc2_config *const config = dev->config; + struct usb_dwc2_reg *const base = config->base; + NRF_USBHS_Type *wrapper = USBHS_DT_WRAPPER_REG_ADDR(0); + + sys_set_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); + + sys_write32(0x87, (mem_addr_t)wrapper + 0xC80); + sys_write32(0x87, (mem_addr_t)wrapper + 0xC84); + sys_write32(1, (mem_addr_t)wrapper + 0x004); + + return 0; +} + +static inline int usbhs_pre_hibernation_exit(const struct device *dev) +{ + const struct udc_dwc2_config *const config = dev->config; + struct usb_dwc2_reg *const base = config->base; + NRF_USBHS_Type *wrapper = USBHS_DT_WRAPPER_REG_ADDR(0); + + sys_clear_bits((mem_addr_t)&base->pcgcctl, USB_DWC2_PCGCCTL_GATEHCLK); + + wrapper->TASKS_START = 1; + sys_write32(0, (mem_addr_t)wrapper + 0xC80); + sys_write32(0, (mem_addr_t)wrapper + 0xC84); + + return 0; +} + #define QUIRK_NRF_USBHS_DEFINE(n) \ struct dwc2_vendor_quirks dwc2_vendor_quirks_##n = { \ .init = usbhs_enable_nrfs_service, \ @@ -258,6 +301,8 @@ static inline int usbhs_is_phy_clk_off(const struct device *dev) .irq_clear = usbhs_irq_clear, \ .caps = usbhs_init_caps, \ .is_phy_clk_off = usbhs_is_phy_clk_off, \ + .post_hibernation_entry = usbhs_post_hibernation_entry, \ + .pre_hibernation_exit = usbhs_pre_hibernation_exit, \ }; DT_INST_FOREACH_STATUS_OKAY(QUIRK_NRF_USBHS_DEFINE) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb_c/tcpc/ps8xxx_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb_c/tcpc/ps8xxx_priv.h new file mode 100644 index 00000000..ed03a4d5 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb_c/tcpc/ps8xxx_priv.h @@ -0,0 +1,18 @@ +/* + * Copyright 2024 Google LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Note: The Product ID will read as 0x8803 if the firmware has malfunctioned in 8705, 8755 and + * 8805. Also the Product ID can be invalid if chip is before or during the power-up and + * initialization process. + */ +#define PS8705_PRODUCT_ID 0x8705 +#define PS8745_PRODUCT_ID 0x8745 +#define PS8751_PRODUCT_ID 0x8751 +#define PS8755_PRODUCT_ID 0x8755 +#define PS8805_PRODUCT_ID 0x8805 +#define PS8815_PRODUCT_ID 0x8815 + +/** PS8815 only - vendor specific register for firmware version */ +#define PS8815_REG_FW_VER 0x82 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb_c/tcpc/ucpd_numaker.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb_c/tcpc/ucpd_numaker.h new file mode 100644 index 00000000..81d6939c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/usb_c/tcpc/ucpd_numaker.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_USBC_TCPC_UCPD_NUMAKER_H_ +#define ZEPHYR_DRIVERS_USBC_TCPC_UCPD_NUMAKER_H_ + +#include +#include + +/* TCPC exported for PPC */ +int numaker_tcpc_ppc_is_dead_battery_mode(const struct device *dev); +int numaker_tcpc_ppc_exit_dead_battery_mode(const struct device *dev); +int numaker_tcpc_ppc_is_vbus_source(const struct device *dev); +int numaker_tcpc_ppc_is_vbus_sink(const struct device *dev); +int numaker_tcpc_ppc_set_snk_ctrl(const struct device *dev, bool enable); +int numaker_tcpc_ppc_set_src_ctrl(const struct device *dev, bool enable); +int numaker_tcpc_ppc_set_vbus_discharge(const struct device *dev, bool enable); +int numaker_tcpc_ppc_is_vbus_present(const struct device *dev); +int numaker_tcpc_ppc_set_event_handler(const struct device *dev, usbc_ppc_event_cb_t handler, + void *data); +int numaker_tcpc_ppc_dump_regs(const struct device *dev); + +/* TCPC exported for VBUS */ +bool numaker_tcpc_vbus_check_level(const struct device *dev, enum tc_vbus_level level); +int numaker_tcpc_vbus_measure(const struct device *dev, int *vbus_meas); +int numaker_tcpc_vbus_discharge(const struct device *dev, bool enable); +int numaker_tcpc_vbus_enable(const struct device *dev, bool enable); + +#endif /* ZEPHYR_DRIVERS_USBC_TCPC_UCPD_NUMAKER_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/watchdog/wdt_dw.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/watchdog/wdt_dw.h index d3af812d..c28ac8d3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/watchdog/wdt_dw.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/watchdog/wdt_dw.h @@ -326,10 +326,11 @@ static inline void dw_wdt_response_mode_set(const uint32_t base, const bool mode { uint32_t control = sys_read32(base + WDT_CR); - if (mode) + if (mode) { control |= WDT_CR_RMOD; - else + } else { control &= ~WDT_CR_RMOD; + } sys_write32(control, base + WDT_CR); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/eswifi/eswifi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/eswifi/eswifi.h index 54bf00f0..0bf4fddb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/eswifi/eswifi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/eswifi/eswifi.h @@ -92,9 +92,9 @@ static inline int eswifi_request(struct eswifi_dev *eswifi, char *cmd, static inline void eswifi_lock(struct eswifi_dev *eswifi) { /* Nested locking */ - if (atomic_get(&eswifi->mutex_owner) != (atomic_t)(uintptr_t)_current) { + if (atomic_get(&eswifi->mutex_owner) != (atomic_t)(uintptr_t)arch_current_thread()) { k_mutex_lock(&eswifi->mutex, K_FOREVER); - atomic_set(&eswifi->mutex_owner, (atomic_t)(uintptr_t)_current); + atomic_set(&eswifi->mutex_owner, (atomic_t)(uintptr_t)arch_current_thread()); eswifi->mutex_depth = 1; } else { eswifi->mutex_depth++; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_whd_hal_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_whd_hal_common.h new file mode 100644 index 00000000..588073d5 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_whd_hal_common.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/** Defines the amount of stack memory available for the wifi thread. */ +#if !defined(CY_WIFI_THREAD_STACK_SIZE) +#define CY_WIFI_THREAD_STACK_SIZE (5120) +#endif + +/** Defines the priority of the thread that services wifi packets. Legal values are defined by the + * RTOS being used. + */ +#if !defined(CY_WIFI_THREAD_PRIORITY) +#define CY_WIFI_THREAD_PRIORITY (CY_RTOS_PRIORITY_HIGH) +#endif + +/** Defines the country this will operate in for wifi initialization parameters. See the + * wifi-host-driver's whd_country_code_t for legal options. + */ +#if !defined(CY_WIFI_COUNTRY) +#define CY_WIFI_COUNTRY (WHD_COUNTRY_AUSTRALIA) +#endif + +/** Defines the priority of the interrupt that handles out-of-band notifications from the wifi + * chip. Legal values are defined by the MCU running this code. + */ +#if !defined(CY_WIFI_OOB_INTR_PRIORITY) +#define CY_WIFI_OOB_INTR_PRIORITY (2) +#endif + +/** Defines whether to use the out-of-band pin to allow the WIFI chip to wake up the MCU. */ +#if defined(CY_WIFI_HOST_WAKE_SW_FORCE) +#define CY_USE_OOB_INTR (CY_WIFI_HOST_WAKE_SW_FORCE) +#else +#define CY_USE_OOB_INTR (1u) +#endif /* defined(CY_WIFI_HOST_WAKE_SW_FORCE) */ + +#define CY_WIFI_HOST_WAKE_IRQ_EVENT GPIO_INT_TRIG_LOW +#define DEFAULT_OOB_PIN (0) +#define WLAN_POWER_UP_DELAY_MS (250) +#define WLAN_CBUCK_DISCHARGE_MS (10) + +extern whd_resource_source_t resource_ops; + +int airoc_wifi_power_on(const struct device *dev); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_wifi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_wifi.h index 1bf688e5..8b308e36 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_wifi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/airoc_wifi.h @@ -6,16 +6,44 @@ */ #include -#include -#include #include #include + +#ifdef CONFIG_AIROC_WIFI_BUS_SDIO +#include +#include +#endif +#ifdef CONFIG_AIROC_WIFI_BUS_SPI +#include +#endif + #include +#define DT_DRV_COMPAT infineon_airoc_wifi + +#if DT_PROP(DT_DRV_INST(0), spi_data_irq_shared) +#define SPI_DATA_IRQ_SHARED +#include + +#define PINCTRL_STATE_HOST_WAKE PINCTRL_STATE_PRIV_START +#endif + +#if defined(CONFIG_AIROC_WIFI_BUS_SPI) +#define AIROC_WIFI_SPI_OPERATION (SPI_WORD_SET(DT_PROP_OR(DT_DRV_INST(0), spi_word_size, 8)) \ + | (DT_PROP(DT_DRV_INST(0), spi_half_duplex) \ + ? SPI_HALF_DUPLEX : SPI_FULL_DUPLEX) \ + | SPI_TRANSFER_MSB) +#endif + struct airoc_wifi_data { +#if defined(CONFIG_AIROC_WIFI_BUS_SDIO) struct sd_card card; struct sdio_func sdio_func1; struct sdio_func sdio_func2; +#endif +#if defined(SPI_DATA_IRQ_SHARED) + uint8_t prev_irq_state; +#endif struct net_if *iface; bool second_interface_init; bool is_ap_up; @@ -34,11 +62,26 @@ struct airoc_wifi_data { uint8_t frame_buf[NET_ETH_MAX_FRAME_SIZE]; }; +union airoc_wifi_bus { +#if defined(CONFIG_AIROC_WIFI_BUS_SDIO) + const struct device *bus_sdio; +#endif +#if defined(CONFIG_AIROC_WIFI_BUS_SPI) + const struct spi_dt_spec bus_spi; +#endif +}; + struct airoc_wifi_config { - const struct device *sdhc_dev; + const union airoc_wifi_bus bus_dev; struct gpio_dt_spec wifi_reg_on_gpio; struct gpio_dt_spec wifi_host_wake_gpio; struct gpio_dt_spec wifi_dev_wake_gpio; +#if defined(CONFIG_AIROC_WIFI_BUS_SPI) + struct gpio_dt_spec bus_select_gpio; +#if defined(SPI_DATA_IRQ_SHARED) + const struct pinctrl_dev_config *pcfg; +#endif +#endif }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/cybsp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/cybsp.h index dfa23ffb..ef371244 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/cybsp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/infineon/cybsp.h @@ -5,4 +5,15 @@ * SPDX-License-Identifier: Apache-2.0 */ -/* This is enpty/stub file used in WHD */ +/* required by whd_* header files. */ + +/* See cybsp_types.h, which is usually required by this file, but not available */ +/* here unless we pull in board-specific headers from the upstream driver. */ +#define CYBSP_SDIO_INTERFACE (0) +#define CYBSP_SPI_INTERFACE (1) + +#ifdef CONFIG_AIROC_WIFI_BUS_SDIO +#define CYBSP_WIFI_INTERFACE_TYPE CYBSP_SDIO_INTERFACE +#elif CONFIG_AIROC_WIFI_BUS_SPI +#define CYBSP_WIFI_INTERFACE_TYPE CYBSP_SPI_INTERFACE +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/coex.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/coex.h new file mode 100644 index 00000000..969a4c96 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/coex.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing Coexistence APIs. + */ + +#ifndef __COEX_H__ +#define __COEX_H__ + +#include + +/* Indicates WLAN frequency band of operation */ +enum nrf_wifi_pta_wlan_op_band { + NRF_WIFI_PTA_WLAN_OP_BAND_2_4_GHZ = 0, + NRF_WIFI_PTA_WLAN_OP_BAND_5_GHZ, + NRF_WIFI_PTA_WLAN_OP_BAND_NONE = 0xFF +}; + +/** + * @function nrf_wifi_coex_config_pta(enum nrf_wifi_pta_wlan_op_band wlan_band, + * bool separate_antennas, bool is_sr_protocol_ble) + * + * @brief Function used to configure PTA tables of coexistence hardware. + * + * @param[in] enum nrf_wifi_pta_wlan_op_band wlan_band + * @param[in] separate_antennas + * Indicates whether separate antenans are used or not. + * @param[in] is_sr_protocol_ble + * Indicates if SR protocol is Bluetooth LE or not. + * @return Returns status of configuration. + * Returns zero upon successful configuration. + * Returns non-zero upon unsuccessful configuration. + */ +int nrf_wifi_coex_config_pta(enum nrf_wifi_pta_wlan_op_band wlan_band, bool separate_antennas, + bool is_sr_protocol_ble); + +#if defined(CONFIG_NRF70_SR_COEX_RF_SWITCH) || defined(__DOXYGEN__) +/** + * @function nrf_wifi_config_sr_switch(bool separate_antennas) + * + * @brief Function used to configure SR side switch (nRF5340 side switch in nRF7002 DK). + * + * @param[in] separate_antennas + * Indicates whether separate antenans are used or not. + * + * @return Returns status of configuration. + * Returns zero upon successful configuration. + * Returns non-zero upon unsuccessful configuration. + */ +int nrf_wifi_config_sr_switch(bool separate_antennas); +#endif /* CONFIG_NRF70_SR_COEX_RF_SWITCH */ + +/** + * @function nrf_wifi_coex_config_non_pta(bool separate_antennas) + * + * @brief Function used to configure non-PTA registers of coexistence hardware. + * + * @param[in] separate_antennas + * Indicates whether separate antenans are used or not. + * @param[in] is_sr_protocol_ble + * Indicates if SR protocol is Bluetooth LE or not. + * + * @return Returns status of configuration. + * Returns zero upon successful configuration. + * Returns non-zero upon unsuccessful configuration. + */ +int nrf_wifi_coex_config_non_pta(bool separate_antennas, bool is_sr_protocol_ble); + +/** + * @function nrf_wifi_coex_hw_reset(void) + * + * @brief Function used to reset coexistence hardware. + * + * @return Returns status of configuration. + * Returns zero upon successful configuration. + * Returns non-zero upon unsuccessful configuration. + */ +int nrf_wifi_coex_hw_reset(void); + +#endif /* __COEX_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/coex_struct.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/coex_struct.h new file mode 100644 index 00000000..a6695b47 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/coex_struct.h @@ -0,0 +1,182 @@ +/** + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Structures and related enumerations used in Coexistence. + */ + +#ifndef __COEX_STRUCT_H__ +#define __COEX_STRUCT_H__ + +#include +#include + +/* Max size of message buffer (exchanged between host and MAC). This is in "bytes" */ +#define MAX_MESSAGE_BUF_SIZE 320 +/* Number of elements in coex_ch_configuration other than configbuf[] */ +#define NUM_ELEMENTS_EXCL_CONFIGBUF 4 +/* Each configuration value is of type uint32_t */ +#define MAX_NUM_CONFIG_VALUES ((MAX_MESSAGE_BUF_SIZE-\ + (NUM_ELEMENTS_EXCL_CONFIGBUF*sizeof(uint32_t)))>>2) +/* Number of elements in coex_sr_traffic_info other than sr_traffic_info[] */ +#define NUM_ELEMENTS_EXCL_SRINFOBUF 1 +/* Each SR Traffic Info is of type uint32_t */ +#define MAX_SR_TRAFFIC_BUF_SIZE 32 + +enum { + /** Used two different values for AGGREGATION module because offset from base is + * beyond supported message buffer size for WAIT_STATE_1_TIME register + */ + COEX_HARDWARE = 1, + MAC_CTRL, + MAC_CTRL_AGG_WAIT_STATE_1_TIME, + MAC_CTRL_AGG, + MAC_CTRL_DEAGG, + WLAN_CTRL, +}; + +/* IDs of different messages posted from Coexistence Driver to Coexistence Manager */ +enum { + /* To insturct Coexistence Manager to collect and post SR traffic information */ + COLLECT_SR_TRAFFIC_INFO = 1, + /* To insturct Coexistence Manager to allocate a priority window to SR */ + ALLOCATE_PTI_WINDOW, + /* To do configuration of hardware related to coexistence */ + HW_CONFIGURATION, + /* To start allocating periodic priority windows to Wi-Fi and SR */ + ALLOCATE_PPW, + /* To start allocating virtual priority windows to Wi-Fi */ + ALLOCATE_VPW, + /* To configure CM SW parameters */ + SW_CONFIGURATION, + /* To control sheliak side switch */ + UPDATE_SWITCH_CONFIG +}; + +/* ID(s) of different messages posted from Coexistence Manager to Coexistence Driver */ +enum { + /* To post SR traffic information */ + SR_TRAFFIC_INFO = 1 +}; + +/** + * struct coex_collect_sr_traffic_info - Message from CD to CM to request SR traffic info. + * @message_id: Indicates message ID. This is to be set to COLLECT_SR_TRAFFIC_INFO. + * @num_sets_requested: Indicates the number of sets of duration and periodicity to be collected. + * + * Message from CD to CM to request SR traffic information. + */ +struct coex_collect_sr_traffic_info { + uint32_t message_id; + uint32_t num_sets_requested; +}; + +/** + * struct coex_ch_configuration -Message from CD to CM to configure CH. + * @message_id: Indicates message ID. This is to be set to HW_CONFIGURATION. + * @num_reg_to_config: Indicates the number of registers to be configured. + * @hw_to_config: Indicates the hardware block that is to be configured. + * @hw_block_base_addr: Base address of the hardware block to be configured. + * @configbuf: Configuration buffer that holds packed offset and configuration value. + * + * Message from CD to CM to configure CH + */ +struct coex_ch_configuration { + uint32_t message_id; + uint32_t num_reg_to_config; + uint32_t hw_to_config; + uint32_t hw_block_base_addr; + uint32_t configbuf[MAX_NUM_CONFIG_VALUES]; +}; + +/** + * struct coex_allocate_pti_window - Message to CM to request a priority window. + * @message_id: Indicates message ID. This is to be set to ALLOCATE_PTI_WINDOW. + * @device_req_window: Indicates device requesting a priority window. + * @window_start_or_end: Indicates if request is posted to START or END a priority window. + * @imp_of_request: Indicates importance of activity for which the window is requested. + * @can_be_deferred: activity of Wi-Fi/SR, for which window is requested can be deferred or not. + * + * Message to CM to request a priority window + */ +struct coex_allocate_pti_window { + uint32_t message_id; + uint32_t device_req_window; + uint32_t window_start_or_end; + uint32_t imp_of_request; + uint32_t can_be_deferred; +}; + +/** + * struct coex_allocate_ppw - Message from CD to CM to allocate Periodic Priority Windows. + * @message_id: Indicates message ID. This is to be set to ALLOCATE_PPW. + * @start_or_stop: Indiates start or stop allocation of PPWs. + * @first_pti_window: Indicates first priority window in the series of PPWs. + * @ps_mechanism: Indicates recommended powersave mechanism for Wi-Fi's downlink. + * @wifi_window_duration: Indicates duration of Wi-Fi priority window. + * @sr_window_duration: Indicates duration of SR priority window. + * + * Message from CD to CM to allocate Periodic Priority Windows. + */ +struct coex_allocate_ppw { + uint32_t message_id; + uint32_t start_or_stop; + uint32_t first_pti_window; + uint32_t ps_mechanism; + uint32_t wifi_window_duration; + uint32_t sr_window_duration; +}; + +/** + * struct coex_allocate_vpw - Message from CD to CM to allocate Virtual Priority Windows. + * @message_id: Indicates message ID. This is to be set to ALLOCATE_VPW. + * @start_or_stop: Indicates start or stop allocation of VPWs. + * @wifi_window_duration: Indicates duration of Wi-Fi virtual priority window. + * @ps_mechanism: Indicates recommended powersave mechanism for Wi-Fi's downlink. + * + * Message from CD to CM to allocate Virtual Priority Windows. + */ +struct coex_allocate_vpw { + uint32_t message_id; + uint32_t start_or_stop; + uint32_t wifi_window_duration; + uint32_t ps_mechanism; +}; + +/** + * struct coex_config_cm_params - Message from CD to CM to configure CM parameters + * @message_id: Indicates message ID. This is to be set to SW_CONFIGURATION. + * @first_isr_trigger_period: microseconds . used to trigger the ISR mechanism. + * @sr_window_poll_periodicity_vpw: microseconds. This is used to poll through SR window. + * that comes after Wi-Fi window ends and next SR activity starts, in the case of VPWs. + * @lead_time_from_end_of_wlan_win: microseconds. Lead time from the end of Wi-Fi window. + * (to inform AP that Wi-Fi is entering powersave) in the case of PPW and VPW generation. + * @sr_window_poll_count_threshold: This is equal to "Wi-Fi contention timeout. + * threshold"/sr_window_poll_periodicity_vpw. + * + * Message from CD to CM to configure CM parameters. + */ +struct coex_config_cm_params { + uint32_t message_id; + uint32_t first_isr_trigger_period; + uint32_t sr_window_poll_periodicity_vpw; + uint32_t lead_time_from_end_of_wlan_win; + uint32_t sr_window_poll_count_threshold; +}; + +/** + * struct coex_sr_traffic_info - Message from CM to CD to post SR traffic information. + * @message_id: Indicates message ID. This is to be set to SR_TRAFFIC_INFO. + * @sr_traffic_info: Traffic information buffer. + * + * Message from CM to CD to post SR traffic inforamtion + */ +struct coex_sr_traffic_info { + uint32_t message_id; + uint32_t sr_traffic_info[MAX_SR_TRAFFIC_BUF_SIZE]; +}; + +#endif /* __COEX_STRUCT_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/fmac_main.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/fmac_main.h new file mode 100644 index 00000000..de678006 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/fmac_main.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing FMAC interface specific declarations for the + * Zephyr OS layer of the Wi-Fi driver. + */ + +#ifndef __ZEPHYR_FMAC_MAIN_H__ +#define __ZEPHYR_FMAC_MAIN_H__ + +#include + +#include + +#include +#include +#ifndef CONFIG_NRF70_RADIO_TEST +#include +#include +#ifdef CONFIG_NETWORKING +#include +#endif /* CONFIG_NETWORKING */ +#ifdef CONFIG_NRF70_STA_MODE +#include +#endif /* CONFIG_NRF70_STA_MODE */ +#endif /* !CONFIG_NRF70_RADIO_TEST */ + +#include +#include + +#define NRF70_DRIVER_VERSION "1."KERNEL_VERSION_STRING + +#ifndef CONFIG_NRF70_OFFLOADED_RAW_TX +#ifndef CONFIG_NRF70_RADIO_TEST +struct nrf_wifi_vif_ctx_zep { + const struct device *zep_dev_ctx; + struct net_if *zep_net_if_ctx; + void *supp_drv_if_ctx; + void *rpu_ctx_zep; + unsigned char vif_idx; + struct k_mutex vif_lock; + + scan_result_cb_t disp_scan_cb; + bool scan_in_progress; + int scan_type; + uint16_t max_bss_cnt; + unsigned int scan_res_cnt; + struct k_work_delayable scan_timeout_work; + + struct net_eth_addr mac_addr; + int if_type; + char ifname[16]; + enum nrf_wifi_fmac_if_op_state if_op_state; + bool set_if_event_received; + int set_if_status; +#ifdef CONFIG_NET_STATISTICS_ETHERNET + struct net_stats_eth eth_stats; +#endif /* CONFIG_NET_STATISTICS_ETHERNET */ +#ifdef CONFIG_NRF70_STA_MODE + unsigned int assoc_freq; + enum nrf_wifi_fmac_if_carr_state if_carr_state; + struct wpa_signal_info *signal_info; + struct wpa_conn_info *conn_info; + struct zep_wpa_supp_dev_callbk_fns supp_callbk_fns; + unsigned char twt_flows_map; + unsigned char twt_flow_in_progress_map; + struct wifi_ps_config *ps_info; + bool ps_config_info_evnt; + bool authorized; + bool cookie_resp_received; +#ifdef CONFIG_NRF70_DATA_TX + struct k_work nrf_wifi_net_iface_work; +#endif /* CONFIG_NRF70_DATA_TX */ + unsigned long rssi_record_timestamp_us; + signed short rssi; +#endif /* CONFIG_NRF70_STA_MODE */ +#ifdef CONFIG_NRF70_AP_MODE + int inactive_time_sec; +#endif /* CONFIG_NRF70_AP_MODE */ +#ifdef CONFIG_NRF_WIFI_RPU_RECOVERY + struct k_work nrf_wifi_rpu_recovery_work; +#endif /* CONFIG_NRF_WIFI_RPU_RECOVERY */ + int rts_threshold_value; +}; + +struct nrf_wifi_vif_ctx_map { + const char *ifname; + struct nrf_wifi_vif_ctx_zep *vif_ctx; +}; +#endif /* !CONFIG_NRF70_RADIO_TEST */ + +struct nrf_wifi_ctx_zep { + void *drv_priv_zep; + void *rpu_ctx; +#ifdef CONFIG_NRF70_RADIO_TEST + struct rpu_conf_params conf_params; + bool rf_test_run; + unsigned char rf_test; +#else /* CONFIG_NRF70_RADIO_TEST */ + struct nrf_wifi_vif_ctx_zep vif_ctx_zep[MAX_NUM_VIFS]; +#ifdef CONFIG_NRF70_UTIL + struct rpu_conf_params conf_params; +#endif /* CONFIG_NRF70_UTIL */ +#endif /* CONFIG_NRF70_RADIO_TEST */ + unsigned char *extended_capa, *extended_capa_mask; + unsigned int extended_capa_len; + struct k_mutex rpu_lock; +#ifdef CONFIG_NRF_WIFI_RPU_RECOVERY + bool rpu_recovery_in_progress; + unsigned long last_rpu_recovery_time_ms; + unsigned int rpu_recovery_retries; + int rpu_recovery_success; + int rpu_recovery_failure; +#endif /* CONFIG_NRF_WIFI_RPU_RECOVERY */ +}; + +struct nrf_wifi_drv_priv_zep { + struct nrf_wifi_fmac_priv *fmac_priv; + /* TODO: Replace with a linked list to handle unlimited RPUs */ + struct nrf_wifi_ctx_zep rpu_ctx_zep; +}; + +extern struct nrf_wifi_drv_priv_zep rpu_drv_priv_zep; + +void nrf_wifi_scan_timeout_work(struct k_work *work); + +void configure_tx_pwr_settings(struct nrf_wifi_tx_pwr_ctrl_params *tx_pwr_ctrl_params, + struct nrf_wifi_tx_pwr_ceil_params *tx_pwr_ceil_params); +void configure_board_dep_params(struct nrf_wifi_board_params *board_params); +void set_tx_pwr_ceil_default(struct nrf_wifi_tx_pwr_ceil_params *pwr_ceil_params); +const char *nrf_wifi_get_drv_version(void); +enum nrf_wifi_status nrf_wifi_fmac_dev_add_zep(struct nrf_wifi_drv_priv_zep *drv_priv_zep); +enum nrf_wifi_status nrf_wifi_fmac_dev_rem_zep(struct nrf_wifi_drv_priv_zep *drv_priv_zep); +struct nrf_wifi_vif_ctx_zep *nrf_wifi_get_vif_ctx(struct net_if *iface); +#ifdef CONFIG_NRF_WIFI_RPU_RECOVERY +void nrf_wifi_rpu_recovery_cb(void *vif_ctx, + void *event_data, + unsigned int event_len); +#endif /* CONFIG_NRF_WIFI_RPU_RECOVERY */ +#endif /* !CONFIG_NRF70_OFFLOADED_RAW_TX */ +#ifdef CONFIG_NRF_WIFI_BUILD_ONLY_MODE +inline enum nrf_wifi_status nrf_wifi_fw_load(void *rpu_ctx) +{ + (void)rpu_ctx; + + return NRF_WIFI_STATUS_SUCCESS; +} +#else +enum nrf_wifi_status nrf_wifi_fw_load(void *rpu_ctx); +#endif /* CONFIG_NRF_WIFI_BUILD_ONLY_MODE */ +#endif /* __ZEPHYR_FMAC_MAIN_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/net_if.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/net_if.h new file mode 100644 index 00000000..8d97802b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/net_if.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing network stack interface specific declarations for + * the Zephyr OS layer of the Wi-Fi driver. + */ + +#ifndef __ZEPHYR_NET_IF_H__ +#define __ZEPHYR_NET_IF_H__ +#include +#include +#include +#include +#include +#include + +#define UNICAST_MASK GENMASK(7, 1) +#define LOCAL_BIT BIT(1) + +void nrf_wifi_if_init_zep(struct net_if *iface); + +int nrf_wifi_if_start_zep(const struct device *dev); + +int nrf_wifi_if_stop_zep(const struct device *dev); + +int nrf_wifi_if_set_config_zep(const struct device *dev, + enum ethernet_config_type type, + const struct ethernet_config *config); + +int nrf_wifi_if_get_config_zep(const struct device *dev, + enum ethernet_config_type type, + struct ethernet_config *config); + +enum ethernet_hw_caps nrf_wifi_if_caps_get(const struct device *dev); + +int nrf_wifi_if_send(const struct device *dev, + struct net_pkt *pkt); + +void nrf_wifi_if_rx_frm(void *os_vif_ctx, + void *frm); + +#if defined(CONFIG_NRF70_RAW_DATA_RX) || defined(CONFIG_NRF70_PROMISC_DATA_RX) +void nrf_wifi_if_sniffer_rx_frm(void *os_vif_ctx, + void *frm, + struct raw_rx_pkt_header *raw_rx_hdr, + bool pkt_free); +#endif /* CONFIG_NRF70_RAW_DATA_RX || CONFIG_NRF70_PROMISC_DATA_RX */ + +enum nrf_wifi_status nrf_wifi_if_carr_state_chg(void *os_vif_ctx, + enum nrf_wifi_fmac_if_carr_state carr_state); + +int nrf_wifi_stats_get(const struct device *dev, + struct net_stats_wifi *stats); + +struct net_stats_eth *nrf_wifi_eth_stats_get(const struct device *dev); + +void nrf_wifi_set_iface_event_handler(void *os_vif_ctx, + struct nrf_wifi_umac_event_set_interface *event, + unsigned int event_len); + +int nrf_wifi_stats_reset(const struct device *dev); +#endif /* __ZEPHYR_NET_IF_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wifi_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wifi_mgmt.h new file mode 100644 index 00000000..e2aa91ca --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wifi_mgmt.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing WiFi management operation implementations + * for the Zephyr OS. + */ + +#ifndef __ZEPHYR_WIFI_MGMT_H__ +#define __ZEPHYR_WIFI_MGMT_H__ +#include + +#include +#include + +#include "osal_api.h" + +/** Filter setting defines for sniffer mode. */ +#define WIFI_MGMT_DATA_CTRL_FILTER_SETTING 0xE +#define WIFI_ALL_FILTER_SETTING 0xF + +struct twt_interval_float { + unsigned short mantissa; + unsigned char exponent; +}; + +int nrf_wifi_set_power_save(const struct device *dev, + struct wifi_ps_params *params); + +int nrf_wifi_set_twt(const struct device *dev, + struct wifi_twt_params *twt_params); + +void nrf_wifi_event_proc_twt_setup_zep(void *vif_ctx, + struct nrf_wifi_umac_cmd_config_twt *twt_setup_info, + unsigned int event_len); + +void nrf_wifi_event_proc_twt_teardown_zep(void *vif_ctx, + struct nrf_wifi_umac_cmd_teardown_twt *twt_teardown_info, + unsigned int event_len); + +void nrf_wifi_event_proc_twt_sleep_zep(void *vif_ctx, + struct nrf_wifi_umac_event_twt_sleep *twt_sleep_info, + unsigned int event_len); + +int nrf_wifi_twt_teardown_flows(struct nrf_wifi_vif_ctx_zep *vif_ctx_zep, + unsigned char start_flow_id, unsigned char end_flow_id); + +int nrf_wifi_get_power_save_config(const struct device *dev, + struct wifi_ps_config *ps_config); + +void nrf_wifi_event_proc_get_power_save_info(void *vif_ctx, + struct nrf_wifi_umac_event_power_save_info *ps_info, + unsigned int event_len); + +#ifdef CONFIG_NRF70_SYSTEM_WITH_RAW_MODES +int nrf_wifi_mode(const struct device *dev, + struct wifi_mode_info *mode); +#endif + +#if defined(CONFIG_NRF70_RAW_DATA_TX) || defined(CONFIG_NRF70_RAW_DATA_RX) +int nrf_wifi_channel(const struct device *dev, + struct wifi_channel_info *channel); +#endif /* CONFIG_NRF70_RAW_DATA_TX || CONFIG_NRF70_RAW_DATA_RX */ + +#if defined(CONFIG_NRF70_RAW_DATA_RX) || defined(CONFIG_NRF70_PROMISC_DATA_RX) +int nrf_wifi_filter(const struct device *dev, + struct wifi_filter_info *filter); +#endif /* CONFIG_NRF70_RAW_DATA_RX || CONFIG_NRF70_PROMISC_DATA_RX */ + +int nrf_wifi_set_rts_threshold(const struct device *dev, + unsigned int rts_threshold); + +int nrf_wifi_get_rts_threshold(const struct device *dev, + unsigned int *rts_threshold); +#endif /* __ZEPHYR_WIFI_MGMT_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wifi_mgmt_scan.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wifi_mgmt_scan.h new file mode 100644 index 00000000..e97f9293 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wifi_mgmt_scan.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing display scan specific declarations for the + * Zephyr OS layer of the Wi-Fi driver. + */ + +#ifndef __ZEPHYR_DISP_SCAN_H__ +#define __ZEPHYR_DISP_SCAN_H__ +#include +#include + +#include "osal_api.h" +int nrf_wifi_disp_scan_zep(const struct device *dev, struct wifi_scan_params *params, + scan_result_cb_t cb); + +enum nrf_wifi_status nrf_wifi_disp_scan_res_get_zep(struct nrf_wifi_vif_ctx_zep *vif_ctx_zep); + +void nrf_wifi_event_proc_disp_scan_res_zep(void *vif_ctx, + struct nrf_wifi_umac_event_new_scan_display_results *scan_res, + unsigned int event_len, + bool is_last); + +#ifdef CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS +void nrf_wifi_rx_bcn_prb_resp_frm(void *vif_ctx, + void *frm, + unsigned short frequency, + signed short signal); +#endif /* CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS */ +#endif /* __ZEPHYR_DISP_SCAN_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wpa_supp_if.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wpa_supp_if.h new file mode 100644 index 00000000..c543644e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/inc/wpa_supp_if.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing WPA supplicant interface specific declarations for + * the Zephyr OS layer of the Wi-Fi driver. + */ + +#ifndef __ZEPHYR_WPA_SUPP_IF_H__ +#define __ZEPHYR_WPA_SUPP_IF_H__ + + +#define RPU_RESP_EVENT_TIMEOUT 5000 +#ifdef CONFIG_NRF70_STA_MODE +#include + +void *nrf_wifi_wpa_supp_dev_init(void *supp_drv_if_ctx, const char *iface_name, + struct zep_wpa_supp_dev_callbk_fns *supp_callbk_fns); + +void nrf_wifi_wpa_supp_dev_deinit(void *if_priv); + +int nrf_wifi_wpa_supp_scan2(void *if_priv, struct wpa_driver_scan_params *params); + +int nrf_wifi_wpa_supp_scan_abort(void *if_priv); + +int nrf_wifi_wpa_supp_scan_results_get(void *if_priv); + +int nrf_wifi_wpa_supp_deauthenticate(void *if_priv, const char *addr, unsigned short reason_code); + +int nrf_wifi_wpa_supp_authenticate(void *if_priv, struct wpa_driver_auth_params *params, + struct wpa_bss *curr_bss); + +int nrf_wifi_wpa_supp_associate(void *if_priv, struct wpa_driver_associate_params *params); + +int nrf_wifi_wpa_set_supp_port(void *if_priv, int authorized, char *bssid); + +int nrf_wifi_wpa_supp_signal_poll(void *if_priv, struct wpa_signal_info *si, + unsigned char *bssid); + +int nrf_wifi_nl80211_send_mlme(void *if_priv, const u8 *data, size_t data_len, int noack, + unsigned int freq, int no_cck, int offchanok, unsigned int wait_time, + int cookie); + +int nrf_wifi_supp_get_wiphy(void *if_priv); + +int nrf_wifi_supp_register_frame(void *if_priv, + u16 type, const u8 *match, size_t match_len, + bool multicast); + +int nrf_wifi_wpa_supp_set_key(void *if_priv, + const unsigned char *ifname, + enum wpa_alg alg, + const unsigned char *addr, + int key_idx, + int set_tx, + const unsigned char *seq, + size_t seq_len, + const unsigned char *key, + size_t key_len, + enum key_flag key_flag); + +void nrf_wifi_wpa_supp_event_proc_scan_start(void *if_priv); + +void nrf_wifi_wpa_supp_event_proc_scan_done(void *if_priv, + struct nrf_wifi_umac_event_trigger_scan *scan_done_event, + unsigned int event_len, + int aborted); + +void nrf_wifi_wpa_supp_event_proc_scan_res(void *if_priv, + struct nrf_wifi_umac_event_new_scan_results *scan_res, + unsigned int event_len, + bool more_res); + +void nrf_wifi_wpa_supp_event_proc_auth_resp(void *if_priv, + struct nrf_wifi_umac_event_mlme *auth_resp, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_proc_assoc_resp(void *if_priv, + struct nrf_wifi_umac_event_mlme *assoc_resp, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_proc_deauth(void *if_priv, + struct nrf_wifi_umac_event_mlme *deauth, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_proc_disassoc(void *if_priv, + struct nrf_wifi_umac_event_mlme *disassoc, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_proc_get_sta(void *if_priv, + struct nrf_wifi_umac_event_new_station *info, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_proc_get_if(void *if_priv, + struct nrf_wifi_interface_info *info, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_mgmt_tx_status(void *if_priv, + struct nrf_wifi_umac_event_mlme *mlme_event, + unsigned int event_len); + + +void nrf_wifi_wpa_supp_event_proc_unprot_mgmt(void *if_priv, + struct nrf_wifi_umac_event_mlme *unprot_mgmt, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_get_wiphy(void *if_priv, + struct nrf_wifi_event_get_wiphy *get_wiphy, + unsigned int event_len); + +void nrf_wifi_wpa_supp_event_mgmt_rx_callbk_fn(void *if_priv, + struct nrf_wifi_umac_event_mlme *mgmt_rx_event, + unsigned int event_len); + +int nrf_wifi_supp_get_capa(void *if_priv, struct wpa_driver_capa *capa); + +void nrf_wifi_wpa_supp_event_mac_chgd(void *if_priv); +int nrf_wifi_supp_get_conn_info(void *if_priv, struct wpa_conn_info *info); + +void nrf_wifi_supp_event_proc_get_conn_info(void *os_vif_ctx, + struct nrf_wifi_umac_event_conn_info *info, + unsigned int event_len); +int nrf_wifi_supp_set_country(void *if_priv, const char *alpha2); +int nrf_wifi_supp_get_country(void *if_priv, char *alpha2); + +#endif /* CONFIG_NRF70_STA_MODE */ +#ifdef CONFIG_NRF70_AP_MODE +int nrf_wifi_wpa_supp_init_ap(void *if_priv, struct wpa_driver_associate_params *params); +int nrf_wifi_wpa_supp_start_ap(void *if_priv, struct wpa_driver_ap_params *params); +int nrf_wifi_wpa_supp_change_beacon(void *if_priv, struct wpa_driver_ap_params *params); +int nrf_wifi_wpa_supp_stop_ap(void *if_priv); +int nrf_wifi_wpa_supp_deinit_ap(void *if_priv); +int nrf_wifi_wpa_supp_sta_add(void *if_priv, struct hostapd_sta_add_params *params); +int nrf_wifi_wpa_supp_sta_remove(void *if_priv, const u8 *addr); +int nrf_wifi_supp_register_mgmt_frame(void *if_priv, + u16 frame_type, size_t match_len, const u8 *match); +int nrf_wifi_wpa_supp_sta_set_flags(void *if_priv, const u8 *addr, + unsigned int total_flags, unsigned int flags_or, + unsigned int flags_and); +int nrf_wifi_wpa_supp_sta_get_inact_sec(void *if_priv, const u8 *addr); +#endif /* CONFIG_NRF70_AP_MODE */ +#endif /* __ZEPHYR_WPA_SUPP_IF_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/off_raw_tx/inc/off_raw_tx.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/off_raw_tx/inc/off_raw_tx.h new file mode 100644 index 00000000..1cb6e258 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/off_raw_tx/inc/off_raw_tx.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief File containing internal structures for the offloaded raw TX feature in the driver. + */ + +#include "fmac_structs_common.h" +#include "osal_api.h" + +struct nrf_wifi_ctx_zep { + void *drv_priv_zep; + void *rpu_ctx; + uint8_t mac_addr[6]; +}; + + +struct nrf_wifi_off_raw_tx_drv_priv { + struct nrf_wifi_fmac_priv *fmac_priv; + /* TODO: Replace with a linked list to handle unlimited RPUs */ + struct nrf_wifi_ctx_zep rpu_ctx_zep; + struct k_spinlock lock; +}; + +enum nrf_wifi_status nrf_wifi_fw_load(void *rpu_ctx); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/src/wifi_util.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/src/wifi_util.h new file mode 100644 index 00000000..2ab188ef --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nrf_wifi/src/wifi_util.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* @file + * @brief nRF Wi-Fi radio-test mode shell module + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct nrf_wifi_ctx_zep_rt { + struct nrf_wifi_fmac_priv *fmac_priv; + struct rpu_conf_params conf_params; +}; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nxp/nxp_wifi_drv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nxp/nxp_wifi_drv.h new file mode 100644 index 00000000..d4c1620e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/drivers/wifi/nxp/nxp_wifi_drv.h @@ -0,0 +1,83 @@ +/** + * Copyright 2023-2024 NXP + * SPDX-License-Identifier: Apache-2.0 + * + * @file nxp_wifi_drv.h + * Shim layer between wifi driver connection manager and zephyr + * Wi-Fi L2 layer + */ + +#ifndef ZEPHYR_DRIVERS_WIFI_NNP_WIFI_DRV_H_ +#define ZEPHYR_DRIVERS_WIFI_NXP_WIFI_DRV_H_ + +#include +#include +#ifdef CONFIG_SDIO_STACK +#include +#include +#endif +#include +#include +#include + +#include "wlan_bt_fw.h" +#include "wlan.h" +#include "wm_net.h" +#if defined(CONFIG_NXP_WIFI_SHELL) +#include "wifi_shell.h" +#endif +#if defined(CONFIG_WIFI_NM_WPA_SUPPLICANT) +#include "wifi_nxp.h" +#include "rtos_wpa_supp_if.h" +#endif + +#define MAX_DATA_SIZE 1600 + +#define NXP_WIFI_SYNC_TIMEOUT_MS K_FOREVER + +#define NXP_WIFI_UAP_NETWORK_NAME "uap-network" + +#define NXP_WIFI_STA_NETWORK_NAME "sta-network" + +#define NXP_WIFI_EVENT_BIT(event) (1 << event) + +#define NXP_WIFI_SYNC_INIT_GROUP \ + NXP_WIFI_EVENT_BIT(WLAN_REASON_INITIALIZED) | \ + NXP_WIFI_EVENT_BIT(WLAN_REASON_INITIALIZATION_FAILED) + +#define NXP_WIFI_SYNC_PS_GROUP \ + NXP_WIFI_EVENT_BIT(WLAN_REASON_PS_ENTER) | NXP_WIFI_EVENT_BIT(WLAN_REASON_PS_EXIT) + +enum nxp_wifi_ret { + NXP_WIFI_RET_SUCCESS, + NXP_WIFI_RET_FAIL, + NXP_WIFI_RET_NOT_FOUND, + NXP_WIFI_RET_AUTH_FAILED, + NXP_WIFI_RET_ADDR_FAILED, + NXP_WIFI_RET_NOT_CONNECTED, + NXP_WIFI_RET_NOT_READY, + NXP_WIFI_RET_TIMEOUT, + NXP_WIFI_RET_BAD_PARAM, +}; + +enum nxp_wifi_state { + NXP_WIFI_NOT_INITIALIZED, + NXP_WIFI_INITIALIZED, + NXP_WIFI_STARTED, +}; + +struct nxp_wifi_dev { + struct net_if *iface; + scan_result_cb_t scan_cb; + struct k_mutex mutex; +}; + +int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data); + +#if defined(CONFIG_NXP_WIFI_SHELL) +void nxp_wifi_shell_register(struct nxp_wifi_dev *dev); +#else +#define nxp_wifi_shell_register(dev) +#endif + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h index 74704a43..bdea1cac 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/syscall_list.h @@ -17,547 +17,563 @@ #define K_SYSCALL_DMA_START 11 #define K_SYSCALL_DMA_STOP 12 #define K_SYSCALL_DMA_SUSPEND 13 -#define K_SYSCALL_FLASH_ERASE 14 -#define K_SYSCALL_FLASH_EX_OP 15 -#define K_SYSCALL_FLASH_FILL 16 -#define K_SYSCALL_FLASH_FLATTEN 17 -#define K_SYSCALL_FLASH_GET_PAGE_COUNT 18 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 19 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 20 -#define K_SYSCALL_FLASH_GET_PARAMETERS 21 -#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 22 -#define K_SYSCALL_FLASH_READ 23 -#define K_SYSCALL_FLASH_READ_JEDEC_ID 24 -#define K_SYSCALL_FLASH_SFDP_READ 25 -#define K_SYSCALL_FLASH_WRITE 26 -#define K_SYSCALL_GPIO_GET_PENDING_INT 27 -#define K_SYSCALL_GPIO_PIN_CONFIGURE 28 -#define K_SYSCALL_GPIO_PIN_GET_CONFIG 29 -#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 30 -#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 31 -#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 32 -#define K_SYSCALL_GPIO_PORT_GET_RAW 33 -#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 34 -#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 35 -#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 36 -#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 37 -#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 38 -#define K_SYSCALL_HWINFO_GET_DEVICE_ID 39 -#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 40 -#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 41 -#define K_SYSCALL_I2C_CONFIGURE 42 -#define K_SYSCALL_I2C_GET_CONFIG 43 -#define K_SYSCALL_I2C_RECOVER_BUS 44 -#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 45 -#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 46 -#define K_SYSCALL_I2C_TRANSFER 47 -#define K_SYSCALL_K_BUSY_WAIT 48 -#define K_SYSCALL_K_CONDVAR_BROADCAST 49 -#define K_SYSCALL_K_CONDVAR_INIT 50 -#define K_SYSCALL_K_CONDVAR_SIGNAL 51 -#define K_SYSCALL_K_CONDVAR_WAIT 52 -#define K_SYSCALL_K_EVENT_CLEAR 53 -#define K_SYSCALL_K_EVENT_INIT 54 -#define K_SYSCALL_K_EVENT_POST 55 -#define K_SYSCALL_K_EVENT_SET 56 -#define K_SYSCALL_K_EVENT_SET_MASKED 57 -#define K_SYSCALL_K_EVENT_WAIT 58 -#define K_SYSCALL_K_EVENT_WAIT_ALL 59 -#define K_SYSCALL_K_FLOAT_DISABLE 60 -#define K_SYSCALL_K_FLOAT_ENABLE 61 -#define K_SYSCALL_K_FUTEX_WAIT 62 -#define K_SYSCALL_K_FUTEX_WAKE 63 -#define K_SYSCALL_K_IS_PREEMPT_THREAD 64 -#define K_SYSCALL_K_MSGQ_ALLOC_INIT 65 -#define K_SYSCALL_K_MSGQ_GET 66 -#define K_SYSCALL_K_MSGQ_GET_ATTRS 67 -#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 68 -#define K_SYSCALL_K_MSGQ_NUM_USED_GET 69 -#define K_SYSCALL_K_MSGQ_PEEK 70 -#define K_SYSCALL_K_MSGQ_PEEK_AT 71 -#define K_SYSCALL_K_MSGQ_PURGE 72 -#define K_SYSCALL_K_MSGQ_PUT 73 -#define K_SYSCALL_K_MUTEX_INIT 74 -#define K_SYSCALL_K_MUTEX_LOCK 75 -#define K_SYSCALL_K_MUTEX_UNLOCK 76 -#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 77 -#define K_SYSCALL_K_OBJECT_ALLOC 78 -#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 79 -#define K_SYSCALL_K_OBJECT_RELEASE 80 -#define K_SYSCALL_K_PIPE_ALLOC_INIT 81 -#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 82 -#define K_SYSCALL_K_PIPE_FLUSH 83 -#define K_SYSCALL_K_PIPE_GET 84 -#define K_SYSCALL_K_PIPE_PUT 85 -#define K_SYSCALL_K_PIPE_READ_AVAIL 86 -#define K_SYSCALL_K_PIPE_WRITE_AVAIL 87 -#define K_SYSCALL_K_POLL 88 -#define K_SYSCALL_K_POLL_SIGNAL_CHECK 89 -#define K_SYSCALL_K_POLL_SIGNAL_INIT 90 -#define K_SYSCALL_K_POLL_SIGNAL_RAISE 91 -#define K_SYSCALL_K_POLL_SIGNAL_RESET 92 -#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 93 -#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 94 -#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 95 -#define K_SYSCALL_K_QUEUE_GET 96 -#define K_SYSCALL_K_QUEUE_INIT 97 -#define K_SYSCALL_K_QUEUE_IS_EMPTY 98 -#define K_SYSCALL_K_QUEUE_PEEK_HEAD 99 -#define K_SYSCALL_K_QUEUE_PEEK_TAIL 100 -#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 101 -#define K_SYSCALL_K_SEM_COUNT_GET 102 -#define K_SYSCALL_K_SEM_GIVE 103 -#define K_SYSCALL_K_SEM_INIT 104 -#define K_SYSCALL_K_SEM_RESET 105 -#define K_SYSCALL_K_SEM_TAKE 106 -#define K_SYSCALL_K_SLEEP 107 -#define K_SYSCALL_K_STACK_ALLOC_INIT 108 -#define K_SYSCALL_K_STACK_POP 109 -#define K_SYSCALL_K_STACK_PUSH 110 -#define K_SYSCALL_K_STR_OUT 111 -#define K_SYSCALL_K_THREAD_ABORT 112 -#define K_SYSCALL_K_THREAD_CREATE 113 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 114 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 115 -#define K_SYSCALL_K_THREAD_DEADLINE_SET 116 -#define K_SYSCALL_K_THREAD_JOIN 117 -#define K_SYSCALL_K_THREAD_NAME_COPY 118 -#define K_SYSCALL_K_THREAD_NAME_SET 119 -#define K_SYSCALL_K_THREAD_PRIORITY_GET 120 -#define K_SYSCALL_K_THREAD_PRIORITY_SET 121 -#define K_SYSCALL_K_THREAD_RESUME 122 -#define K_SYSCALL_K_THREAD_STACK_ALLOC 123 -#define K_SYSCALL_K_THREAD_STACK_FREE 124 -#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 125 -#define K_SYSCALL_K_THREAD_START 126 -#define K_SYSCALL_K_THREAD_SUSPEND 127 -#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 128 -#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 129 -#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 130 -#define K_SYSCALL_K_TIMER_REMAINING_TICKS 131 -#define K_SYSCALL_K_TIMER_START 132 -#define K_SYSCALL_K_TIMER_STATUS_GET 133 -#define K_SYSCALL_K_TIMER_STATUS_SYNC 134 -#define K_SYSCALL_K_TIMER_STOP 135 -#define K_SYSCALL_K_TIMER_USER_DATA_GET 136 -#define K_SYSCALL_K_TIMER_USER_DATA_SET 137 -#define K_SYSCALL_K_UPTIME_TICKS 138 -#define K_SYSCALL_K_USLEEP 139 -#define K_SYSCALL_K_WAKEUP 140 -#define K_SYSCALL_K_YIELD 141 -#define K_SYSCALL_LLEXT_GET_FN_TABLE 142 -#define K_SYSCALL_LOG_BUFFERED_CNT 143 -#define K_SYSCALL_LOG_FILTER_SET 144 -#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 145 -#define K_SYSCALL_LOG_PANIC 146 -#define K_SYSCALL_LOG_PROCESS 147 -#define K_SYSCALL_PWM_CAPTURE_CYCLES 148 -#define K_SYSCALL_PWM_DISABLE_CAPTURE 149 -#define K_SYSCALL_PWM_ENABLE_CAPTURE 150 -#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 151 -#define K_SYSCALL_PWM_SET_CYCLES 152 -#define K_SYSCALL_RESET_LINE_ASSERT 153 -#define K_SYSCALL_RESET_LINE_DEASSERT 154 -#define K_SYSCALL_RESET_LINE_TOGGLE 155 -#define K_SYSCALL_RESET_STATUS 156 -#define K_SYSCALL_SPI_RELEASE 157 -#define K_SYSCALL_SPI_TRANSCEIVE 158 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 159 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 160 -#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 161 -#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 162 -#define K_SYSCALL_UART_CONFIGURE 163 -#define K_SYSCALL_UART_CONFIG_GET 164 -#define K_SYSCALL_UART_DRV_CMD 165 -#define K_SYSCALL_UART_ERR_CHECK 166 -#define K_SYSCALL_UART_IRQ_ERR_DISABLE 167 -#define K_SYSCALL_UART_IRQ_ERR_ENABLE 168 -#define K_SYSCALL_UART_IRQ_IS_PENDING 169 -#define K_SYSCALL_UART_IRQ_RX_DISABLE 170 -#define K_SYSCALL_UART_IRQ_RX_ENABLE 171 -#define K_SYSCALL_UART_IRQ_TX_DISABLE 172 -#define K_SYSCALL_UART_IRQ_TX_ENABLE 173 -#define K_SYSCALL_UART_IRQ_UPDATE 174 -#define K_SYSCALL_UART_LINE_CTRL_GET 175 -#define K_SYSCALL_UART_LINE_CTRL_SET 176 -#define K_SYSCALL_UART_POLL_IN 177 -#define K_SYSCALL_UART_POLL_IN_U16 178 -#define K_SYSCALL_UART_POLL_OUT 179 -#define K_SYSCALL_UART_POLL_OUT_U16 180 -#define K_SYSCALL_UART_RX_DISABLE 181 -#define K_SYSCALL_UART_RX_ENABLE 182 -#define K_SYSCALL_UART_RX_ENABLE_U16 183 -#define K_SYSCALL_UART_TX 184 -#define K_SYSCALL_UART_TX_ABORT 185 -#define K_SYSCALL_UART_TX_U16 186 -#define K_SYSCALL_ZEPHYR_FPUTC 187 -#define K_SYSCALL_ZEPHYR_FWRITE 188 -#define K_SYSCALL_ZEPHYR_READ_STDIN 189 -#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 190 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 191 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 192 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 193 -#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 194 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 195 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 196 -#define K_SYSCALL_BAD 197 -#define K_SYSCALL_LIMIT 198 +#define K_SYSCALL_ENTROPY_GET_ENTROPY 14 +#define K_SYSCALL_FLASH_COPY 15 +#define K_SYSCALL_FLASH_ERASE 16 +#define K_SYSCALL_FLASH_EX_OP 17 +#define K_SYSCALL_FLASH_FILL 18 +#define K_SYSCALL_FLASH_FLATTEN 19 +#define K_SYSCALL_FLASH_GET_PAGE_COUNT 20 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 21 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 22 +#define K_SYSCALL_FLASH_GET_PARAMETERS 23 +#define K_SYSCALL_FLASH_GET_SIZE 24 +#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 25 +#define K_SYSCALL_FLASH_READ 26 +#define K_SYSCALL_FLASH_READ_JEDEC_ID 27 +#define K_SYSCALL_FLASH_SFDP_READ 28 +#define K_SYSCALL_FLASH_WRITE 29 +#define K_SYSCALL_GPIO_GET_PENDING_INT 30 +#define K_SYSCALL_GPIO_PIN_CONFIGURE 31 +#define K_SYSCALL_GPIO_PIN_GET_CONFIG 32 +#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 33 +#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 34 +#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 35 +#define K_SYSCALL_GPIO_PORT_GET_RAW 36 +#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 37 +#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 38 +#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 39 +#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 40 +#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 41 +#define K_SYSCALL_HWINFO_GET_DEVICE_ID 42 +#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 43 +#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 44 +#define K_SYSCALL_I2C_CONFIGURE 45 +#define K_SYSCALL_I2C_GET_CONFIG 46 +#define K_SYSCALL_I2C_RECOVER_BUS 47 +#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 48 +#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 49 +#define K_SYSCALL_I2C_TRANSFER 50 +#define K_SYSCALL_K_BUSY_WAIT 51 +#define K_SYSCALL_K_CONDVAR_BROADCAST 52 +#define K_SYSCALL_K_CONDVAR_INIT 53 +#define K_SYSCALL_K_CONDVAR_SIGNAL 54 +#define K_SYSCALL_K_CONDVAR_WAIT 55 +#define K_SYSCALL_K_EVENT_CLEAR 56 +#define K_SYSCALL_K_EVENT_INIT 57 +#define K_SYSCALL_K_EVENT_POST 58 +#define K_SYSCALL_K_EVENT_SET 59 +#define K_SYSCALL_K_EVENT_SET_MASKED 60 +#define K_SYSCALL_K_EVENT_WAIT 61 +#define K_SYSCALL_K_EVENT_WAIT_ALL 62 +#define K_SYSCALL_K_FLOAT_DISABLE 63 +#define K_SYSCALL_K_FLOAT_ENABLE 64 +#define K_SYSCALL_K_FUTEX_WAIT 65 +#define K_SYSCALL_K_FUTEX_WAKE 66 +#define K_SYSCALL_K_IS_PREEMPT_THREAD 67 +#define K_SYSCALL_K_MSGQ_ALLOC_INIT 68 +#define K_SYSCALL_K_MSGQ_GET 69 +#define K_SYSCALL_K_MSGQ_GET_ATTRS 70 +#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 71 +#define K_SYSCALL_K_MSGQ_NUM_USED_GET 72 +#define K_SYSCALL_K_MSGQ_PEEK 73 +#define K_SYSCALL_K_MSGQ_PEEK_AT 74 +#define K_SYSCALL_K_MSGQ_PURGE 75 +#define K_SYSCALL_K_MSGQ_PUT 76 +#define K_SYSCALL_K_MUTEX_INIT 77 +#define K_SYSCALL_K_MUTEX_LOCK 78 +#define K_SYSCALL_K_MUTEX_UNLOCK 79 +#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 80 +#define K_SYSCALL_K_OBJECT_ALLOC 81 +#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 82 +#define K_SYSCALL_K_OBJECT_RELEASE 83 +#define K_SYSCALL_K_PIPE_ALLOC_INIT 84 +#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 85 +#define K_SYSCALL_K_PIPE_FLUSH 86 +#define K_SYSCALL_K_PIPE_GET 87 +#define K_SYSCALL_K_PIPE_PUT 88 +#define K_SYSCALL_K_PIPE_READ_AVAIL 89 +#define K_SYSCALL_K_PIPE_WRITE_AVAIL 90 +#define K_SYSCALL_K_POLL 91 +#define K_SYSCALL_K_POLL_SIGNAL_CHECK 92 +#define K_SYSCALL_K_POLL_SIGNAL_INIT 93 +#define K_SYSCALL_K_POLL_SIGNAL_RAISE 94 +#define K_SYSCALL_K_POLL_SIGNAL_RESET 95 +#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 96 +#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 97 +#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 98 +#define K_SYSCALL_K_QUEUE_GET 99 +#define K_SYSCALL_K_QUEUE_INIT 100 +#define K_SYSCALL_K_QUEUE_IS_EMPTY 101 +#define K_SYSCALL_K_QUEUE_PEEK_HEAD 102 +#define K_SYSCALL_K_QUEUE_PEEK_TAIL 103 +#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 104 +#define K_SYSCALL_K_SEM_COUNT_GET 105 +#define K_SYSCALL_K_SEM_GIVE 106 +#define K_SYSCALL_K_SEM_INIT 107 +#define K_SYSCALL_K_SEM_RESET 108 +#define K_SYSCALL_K_SEM_TAKE 109 +#define K_SYSCALL_K_SLEEP 110 +#define K_SYSCALL_K_STACK_ALLOC_INIT 111 +#define K_SYSCALL_K_STACK_POP 112 +#define K_SYSCALL_K_STACK_PUSH 113 +#define K_SYSCALL_K_STR_OUT 114 +#define K_SYSCALL_K_THREAD_ABORT 115 +#define K_SYSCALL_K_THREAD_CREATE 116 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 117 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 118 +#define K_SYSCALL_K_THREAD_DEADLINE_SET 119 +#define K_SYSCALL_K_THREAD_JOIN 120 +#define K_SYSCALL_K_THREAD_NAME_COPY 121 +#define K_SYSCALL_K_THREAD_NAME_SET 122 +#define K_SYSCALL_K_THREAD_PRIORITY_GET 123 +#define K_SYSCALL_K_THREAD_PRIORITY_SET 124 +#define K_SYSCALL_K_THREAD_RESUME 125 +#define K_SYSCALL_K_THREAD_STACK_ALLOC 126 +#define K_SYSCALL_K_THREAD_STACK_FREE 127 +#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 128 +#define K_SYSCALL_K_THREAD_SUSPEND 129 +#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 130 +#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 131 +#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 132 +#define K_SYSCALL_K_TIMER_REMAINING_TICKS 133 +#define K_SYSCALL_K_TIMER_START 134 +#define K_SYSCALL_K_TIMER_STATUS_GET 135 +#define K_SYSCALL_K_TIMER_STATUS_SYNC 136 +#define K_SYSCALL_K_TIMER_STOP 137 +#define K_SYSCALL_K_TIMER_USER_DATA_GET 138 +#define K_SYSCALL_K_TIMER_USER_DATA_SET 139 +#define K_SYSCALL_K_UPTIME_TICKS 140 +#define K_SYSCALL_K_USLEEP 141 +#define K_SYSCALL_K_WAKEUP 142 +#define K_SYSCALL_K_YIELD 143 +#define K_SYSCALL_LLEXT_GET_FN_TABLE 144 +#define K_SYSCALL_LOG_BUFFERED_CNT 145 +#define K_SYSCALL_LOG_FILTER_SET 146 +#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 147 +#define K_SYSCALL_LOG_PANIC 148 +#define K_SYSCALL_LOG_PROCESS 149 +#define K_SYSCALL_PWM_CAPTURE_CYCLES 150 +#define K_SYSCALL_PWM_DISABLE_CAPTURE 151 +#define K_SYSCALL_PWM_ENABLE_CAPTURE 152 +#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 153 +#define K_SYSCALL_PWM_SET_CYCLES 154 +#define K_SYSCALL_RESET_LINE_ASSERT 155 +#define K_SYSCALL_RESET_LINE_DEASSERT 156 +#define K_SYSCALL_RESET_LINE_TOGGLE 157 +#define K_SYSCALL_RESET_STATUS 158 +#define K_SYSCALL_SPI_RELEASE 159 +#define K_SYSCALL_SPI_TRANSCEIVE 160 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 161 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 162 +#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 163 +#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 164 +#define K_SYSCALL_SYS_CSRAND_GET 165 +#define K_SYSCALL_SYS_RAND_GET 166 +#define K_SYSCALL_UART_CONFIGURE 167 +#define K_SYSCALL_UART_CONFIG_GET 168 +#define K_SYSCALL_UART_DRV_CMD 169 +#define K_SYSCALL_UART_ERR_CHECK 170 +#define K_SYSCALL_UART_IRQ_ERR_DISABLE 171 +#define K_SYSCALL_UART_IRQ_ERR_ENABLE 172 +#define K_SYSCALL_UART_IRQ_IS_PENDING 173 +#define K_SYSCALL_UART_IRQ_RX_DISABLE 174 +#define K_SYSCALL_UART_IRQ_RX_ENABLE 175 +#define K_SYSCALL_UART_IRQ_TX_DISABLE 176 +#define K_SYSCALL_UART_IRQ_TX_ENABLE 177 +#define K_SYSCALL_UART_IRQ_UPDATE 178 +#define K_SYSCALL_UART_LINE_CTRL_GET 179 +#define K_SYSCALL_UART_LINE_CTRL_SET 180 +#define K_SYSCALL_UART_POLL_IN 181 +#define K_SYSCALL_UART_POLL_IN_U16 182 +#define K_SYSCALL_UART_POLL_OUT 183 +#define K_SYSCALL_UART_POLL_OUT_U16 184 +#define K_SYSCALL_UART_RX_DISABLE 185 +#define K_SYSCALL_UART_RX_ENABLE 186 +#define K_SYSCALL_UART_RX_ENABLE_U16 187 +#define K_SYSCALL_UART_TX 188 +#define K_SYSCALL_UART_TX_ABORT 189 +#define K_SYSCALL_UART_TX_U16 190 +#define K_SYSCALL_ZEPHYR_FPUTC 191 +#define K_SYSCALL_ZEPHYR_FWRITE 192 +#define K_SYSCALL_ZEPHYR_READ_STDIN 193 +#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 194 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 195 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 196 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 197 +#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 198 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 199 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 200 +#define K_SYSCALL_BAD 201 +#define K_SYSCALL_LIMIT 202 /* Following syscalls are not used in image */ -#define K_SYSCALL_ATOMIC_ADD 199 -#define K_SYSCALL_ATOMIC_AND 200 -#define K_SYSCALL_ATOMIC_CAS 201 -#define K_SYSCALL_ATOMIC_NAND 202 -#define K_SYSCALL_ATOMIC_OR 203 -#define K_SYSCALL_ATOMIC_PTR_CAS 204 -#define K_SYSCALL_ATOMIC_PTR_SET 205 -#define K_SYSCALL_ATOMIC_SET 206 -#define K_SYSCALL_ATOMIC_SUB 207 -#define K_SYSCALL_ATOMIC_XOR 208 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 209 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 210 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 211 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 212 -#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 213 -#define K_SYSCALL_AUXDISPLAY_CLEAR 214 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 215 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 216 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 217 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 218 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 219 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 220 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 221 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 222 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 223 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 224 -#define K_SYSCALL_AUXDISPLAY_IS_BUSY 225 -#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 226 -#define K_SYSCALL_AUXDISPLAY_WRITE 227 -#define K_SYSCALL_BBRAM_CHECK_INVALID 228 -#define K_SYSCALL_BBRAM_CHECK_POWER 229 -#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 230 -#define K_SYSCALL_BBRAM_GET_SIZE 231 -#define K_SYSCALL_BBRAM_READ 232 -#define K_SYSCALL_BBRAM_WRITE 233 -#define K_SYSCALL_BC12_SET_RESULT_CB 234 -#define K_SYSCALL_BC12_SET_ROLE 235 -#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 236 -#define K_SYSCALL_CAN_CALC_TIMING 237 -#define K_SYSCALL_CAN_CALC_TIMING_DATA 238 -#define K_SYSCALL_CAN_GET_BITRATE_MAX 239 -#define K_SYSCALL_CAN_GET_BITRATE_MIN 240 -#define K_SYSCALL_CAN_GET_CAPABILITIES 241 -#define K_SYSCALL_CAN_GET_CORE_CLOCK 242 -#define K_SYSCALL_CAN_GET_MAX_FILTERS 243 -#define K_SYSCALL_CAN_GET_MODE 244 -#define K_SYSCALL_CAN_GET_STATE 245 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 246 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 247 -#define K_SYSCALL_CAN_GET_TIMING_MAX 248 -#define K_SYSCALL_CAN_GET_TIMING_MIN 249 -#define K_SYSCALL_CAN_GET_TRANSCEIVER 250 -#define K_SYSCALL_CAN_RECOVER 251 -#define K_SYSCALL_CAN_REMOVE_RX_FILTER 252 -#define K_SYSCALL_CAN_SEND 253 -#define K_SYSCALL_CAN_SET_BITRATE 254 -#define K_SYSCALL_CAN_SET_BITRATE_DATA 255 -#define K_SYSCALL_CAN_SET_MODE 256 -#define K_SYSCALL_CAN_SET_TIMING 257 -#define K_SYSCALL_CAN_SET_TIMING_DATA 258 -#define K_SYSCALL_CAN_START 259 -#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 260 -#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 261 -#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 262 -#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 263 -#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 264 -#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 265 -#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 266 -#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 267 -#define K_SYSCALL_CAN_STOP 268 -#define K_SYSCALL_CHARGER_CHARGE_ENABLE 269 -#define K_SYSCALL_CHARGER_GET_PROP 270 -#define K_SYSCALL_CHARGER_SET_PROP 271 -#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 272 -#define K_SYSCALL_COUNTER_GET_FREQUENCY 273 -#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 274 -#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 275 -#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 276 -#define K_SYSCALL_COUNTER_GET_PENDING_INT 277 -#define K_SYSCALL_COUNTER_GET_TOP_VALUE 278 -#define K_SYSCALL_COUNTER_GET_VALUE 279 -#define K_SYSCALL_COUNTER_GET_VALUE_64 280 -#define K_SYSCALL_COUNTER_IS_COUNTING_UP 281 -#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 282 -#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 283 -#define K_SYSCALL_COUNTER_SET_TOP_VALUE 284 -#define K_SYSCALL_COUNTER_START 285 -#define K_SYSCALL_COUNTER_STOP 286 -#define K_SYSCALL_COUNTER_TICKS_TO_US 287 -#define K_SYSCALL_COUNTER_US_TO_TICKS 288 -#define K_SYSCALL_DAC_CHANNEL_SETUP 289 -#define K_SYSCALL_DAC_WRITE_VALUE 290 -#define K_SYSCALL_DEVMUX_SELECT_GET 291 -#define K_SYSCALL_DEVMUX_SELECT_SET 292 -#define K_SYSCALL_EEPROM_GET_SIZE 293 -#define K_SYSCALL_EEPROM_READ 294 -#define K_SYSCALL_EEPROM_WRITE 295 -#define K_SYSCALL_EMUL_FUEL_GAUGE_IS_BATTERY_CUTOFF 296 -#define K_SYSCALL_EMUL_FUEL_GAUGE_SET_BATTERY_CHARGING 297 -#define K_SYSCALL_ENTROPY_GET_ENTROPY 298 -#define K_SYSCALL_ESPI_CONFIG 299 -#define K_SYSCALL_ESPI_FLASH_ERASE 300 -#define K_SYSCALL_ESPI_GET_CHANNEL_STATUS 301 -#define K_SYSCALL_ESPI_READ_FLASH 302 -#define K_SYSCALL_ESPI_READ_LPC_REQUEST 303 -#define K_SYSCALL_ESPI_READ_REQUEST 304 -#define K_SYSCALL_ESPI_RECEIVE_OOB 305 -#define K_SYSCALL_ESPI_RECEIVE_VWIRE 306 -#define K_SYSCALL_ESPI_SAF_ACTIVATE 307 -#define K_SYSCALL_ESPI_SAF_CONFIG 308 -#define K_SYSCALL_ESPI_SAF_FLASH_ERASE 309 -#define K_SYSCALL_ESPI_SAF_FLASH_READ 310 -#define K_SYSCALL_ESPI_SAF_FLASH_UNSUCCESS 311 -#define K_SYSCALL_ESPI_SAF_FLASH_WRITE 312 -#define K_SYSCALL_ESPI_SAF_GET_CHANNEL_STATUS 313 -#define K_SYSCALL_ESPI_SAF_SET_PROTECTION_REGIONS 314 -#define K_SYSCALL_ESPI_SEND_OOB 315 -#define K_SYSCALL_ESPI_SEND_VWIRE 316 -#define K_SYSCALL_ESPI_WRITE_FLASH 317 -#define K_SYSCALL_ESPI_WRITE_LPC_REQUEST 318 -#define K_SYSCALL_ESPI_WRITE_REQUEST 319 -#define K_SYSCALL_FLASH_SIMULATOR_GET_MEMORY 320 -#define K_SYSCALL_FUEL_GAUGE_BATTERY_CUTOFF 321 -#define K_SYSCALL_FUEL_GAUGE_GET_BUFFER_PROP 322 -#define K_SYSCALL_FUEL_GAUGE_GET_PROP 323 -#define K_SYSCALL_FUEL_GAUGE_GET_PROPS 324 -#define K_SYSCALL_FUEL_GAUGE_SET_PROP 325 -#define K_SYSCALL_FUEL_GAUGE_SET_PROPS 326 -#define K_SYSCALL_GNSS_GET_ENABLED_SYSTEMS 327 -#define K_SYSCALL_GNSS_GET_FIX_RATE 328 -#define K_SYSCALL_GNSS_GET_NAVIGATION_MODE 329 -#define K_SYSCALL_GNSS_GET_PERIODIC_CONFIG 330 -#define K_SYSCALL_GNSS_GET_SUPPORTED_SYSTEMS 331 -#define K_SYSCALL_GNSS_SET_ENABLED_SYSTEMS 332 -#define K_SYSCALL_GNSS_SET_FIX_RATE 333 -#define K_SYSCALL_GNSS_SET_NAVIGATION_MODE 334 -#define K_SYSCALL_GNSS_SET_PERIODIC_CONFIG 335 -#define K_SYSCALL_HWSPINLOCK_GET_MAX_ID 336 -#define K_SYSCALL_HWSPINLOCK_LOCK 337 -#define K_SYSCALL_HWSPINLOCK_TRYLOCK 338 -#define K_SYSCALL_HWSPINLOCK_UNLOCK 339 -#define K_SYSCALL_I2S_BUF_READ 340 -#define K_SYSCALL_I2S_BUF_WRITE 341 -#define K_SYSCALL_I2S_CONFIGURE 342 -#define K_SYSCALL_I2S_TRIGGER 343 -#define K_SYSCALL_I3C_DO_CCC 344 -#define K_SYSCALL_I3C_TRANSFER 345 -#define K_SYSCALL_IPM_COMPLETE 346 -#define K_SYSCALL_IPM_MAX_DATA_SIZE_GET 347 -#define K_SYSCALL_IPM_MAX_ID_VAL_GET 348 -#define K_SYSCALL_IPM_SEND 349 -#define K_SYSCALL_IPM_SET_ENABLED 350 -#define K_SYSCALL_IVSHMEM_ENABLE_INTERRUPTS 351 -#define K_SYSCALL_IVSHMEM_GET_ID 352 -#define K_SYSCALL_IVSHMEM_GET_MAX_PEERS 353 -#define K_SYSCALL_IVSHMEM_GET_MEM 354 -#define K_SYSCALL_IVSHMEM_GET_OUTPUT_MEM_SECTION 355 -#define K_SYSCALL_IVSHMEM_GET_PROTOCOL 356 -#define K_SYSCALL_IVSHMEM_GET_RW_MEM_SECTION 357 -#define K_SYSCALL_IVSHMEM_GET_STATE 358 -#define K_SYSCALL_IVSHMEM_GET_VECTORS 359 -#define K_SYSCALL_IVSHMEM_INT_PEER 360 -#define K_SYSCALL_IVSHMEM_REGISTER_HANDLER 361 -#define K_SYSCALL_IVSHMEM_SET_STATE 362 -#define K_SYSCALL_KSCAN_CONFIG 363 -#define K_SYSCALL_KSCAN_DISABLE_CALLBACK 364 -#define K_SYSCALL_KSCAN_ENABLE_CALLBACK 365 -#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_IN_GET 366 -#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_OUT_GET 367 -#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_EVICTION_GET 368 -#define K_SYSCALL_K_MEM_PAGING_STATS_GET 369 -#define K_SYSCALL_K_MEM_PAGING_THREAD_STATS_GET 370 -#define K_SYSCALL_LED_BLINK 371 -#define K_SYSCALL_LED_GET_INFO 372 -#define K_SYSCALL_LED_OFF 373 -#define K_SYSCALL_LED_ON 374 -#define K_SYSCALL_LED_SET_BRIGHTNESS 375 -#define K_SYSCALL_LED_SET_CHANNEL 376 -#define K_SYSCALL_LED_SET_COLOR 377 -#define K_SYSCALL_LED_WRITE_CHANNELS 378 -#define K_SYSCALL_MAXIM_DS3231_GET_SYNCPOINT 379 -#define K_SYSCALL_MAXIM_DS3231_REQ_SYNCPOINT 380 -#define K_SYSCALL_MBOX_MAX_CHANNELS_GET 381 -#define K_SYSCALL_MBOX_MTU_GET 382 -#define K_SYSCALL_MBOX_SEND 383 -#define K_SYSCALL_MBOX_SET_ENABLED 384 -#define K_SYSCALL_MDIO_BUS_DISABLE 385 -#define K_SYSCALL_MDIO_BUS_ENABLE 386 -#define K_SYSCALL_MDIO_READ 387 -#define K_SYSCALL_MDIO_READ_C45 388 -#define K_SYSCALL_MDIO_WRITE 389 -#define K_SYSCALL_MDIO_WRITE_C45 390 -#define K_SYSCALL_MSPI_CONFIG 391 -#define K_SYSCALL_MSPI_DEV_CONFIG 392 -#define K_SYSCALL_MSPI_GET_CHANNEL_STATUS 393 -#define K_SYSCALL_MSPI_SCRAMBLE_CONFIG 394 -#define K_SYSCALL_MSPI_TIMING_CONFIG 395 -#define K_SYSCALL_MSPI_TRANSCEIVE 396 -#define K_SYSCALL_MSPI_XIP_CONFIG 397 -#define K_SYSCALL_NET_ADDR_NTOP 398 -#define K_SYSCALL_NET_ADDR_PTON 399 -#define K_SYSCALL_NET_ETH_GET_PTP_CLOCK_BY_INDEX 400 -#define K_SYSCALL_NET_IF_GET_BY_INDEX 401 -#define K_SYSCALL_NET_IF_IPV4_ADDR_ADD_BY_INDEX 402 -#define K_SYSCALL_NET_IF_IPV4_ADDR_LOOKUP_BY_INDEX 403 -#define K_SYSCALL_NET_IF_IPV4_ADDR_RM_BY_INDEX 404 -#define K_SYSCALL_NET_IF_IPV4_SET_GW_BY_INDEX 405 -#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_ADDR_BY_INDEX 406 -#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_INDEX 407 -#define K_SYSCALL_NET_IF_IPV6_ADDR_ADD_BY_INDEX 408 -#define K_SYSCALL_NET_IF_IPV6_ADDR_LOOKUP_BY_INDEX 409 -#define K_SYSCALL_NET_IF_IPV6_ADDR_RM_BY_INDEX 410 -#define K_SYSCALL_NET_SOCKET_SERVICE_REGISTER 411 -#define K_SYSCALL_NRF_QSPI_NOR_XIP_ENABLE 412 -#define K_SYSCALL_PECI_CONFIG 413 -#define K_SYSCALL_PECI_DISABLE 414 -#define K_SYSCALL_PECI_ENABLE 415 -#define K_SYSCALL_PECI_TRANSFER 416 -#define K_SYSCALL_PS2_CONFIG 417 -#define K_SYSCALL_PS2_DISABLE_CALLBACK 418 -#define K_SYSCALL_PS2_ENABLE_CALLBACK 419 -#define K_SYSCALL_PS2_READ 420 -#define K_SYSCALL_PS2_WRITE 421 -#define K_SYSCALL_PTP_CLOCK_GET 422 -#define K_SYSCALL_RETAINED_MEM_CLEAR 423 -#define K_SYSCALL_RETAINED_MEM_READ 424 -#define K_SYSCALL_RETAINED_MEM_SIZE 425 -#define K_SYSCALL_RETAINED_MEM_WRITE 426 -#define K_SYSCALL_RTC_ALARM_GET_SUPPORTED_FIELDS 427 -#define K_SYSCALL_RTC_ALARM_GET_TIME 428 -#define K_SYSCALL_RTC_ALARM_IS_PENDING 429 -#define K_SYSCALL_RTC_ALARM_SET_CALLBACK 430 -#define K_SYSCALL_RTC_ALARM_SET_TIME 431 -#define K_SYSCALL_RTC_GET_CALIBRATION 432 -#define K_SYSCALL_RTC_GET_TIME 433 -#define K_SYSCALL_RTC_SET_CALIBRATION 434 -#define K_SYSCALL_RTC_SET_TIME 435 -#define K_SYSCALL_RTC_UPDATE_SET_CALLBACK 436 -#define K_SYSCALL_RTIO_CQE_COPY_OUT 437 -#define K_SYSCALL_RTIO_CQE_GET_MEMPOOL_BUFFER 438 -#define K_SYSCALL_RTIO_RELEASE_BUFFER 439 -#define K_SYSCALL_RTIO_SQE_CANCEL 440 -#define K_SYSCALL_RTIO_SQE_COPY_IN_GET_HANDLES 441 -#define K_SYSCALL_RTIO_SUBMIT 442 -#define K_SYSCALL_SDHC_CARD_BUSY 443 -#define K_SYSCALL_SDHC_CARD_PRESENT 444 -#define K_SYSCALL_SDHC_DISABLE_INTERRUPT 445 -#define K_SYSCALL_SDHC_ENABLE_INTERRUPT 446 -#define K_SYSCALL_SDHC_EXECUTE_TUNING 447 -#define K_SYSCALL_SDHC_GET_HOST_PROPS 448 -#define K_SYSCALL_SDHC_HW_RESET 449 -#define K_SYSCALL_SDHC_REQUEST 450 -#define K_SYSCALL_SDHC_SET_IO 451 -#define K_SYSCALL_SENSOR_ATTR_GET 452 -#define K_SYSCALL_SENSOR_ATTR_SET 453 -#define K_SYSCALL_SENSOR_CHANNEL_GET 454 -#define K_SYSCALL_SENSOR_GET_DECODER 455 -#define K_SYSCALL_SENSOR_RECONFIGURE_READ_IODEV 456 -#define K_SYSCALL_SENSOR_SAMPLE_FETCH 457 -#define K_SYSCALL_SENSOR_SAMPLE_FETCH_CHAN 458 -#define K_SYSCALL_SIP_SUPERVISORY_CALL 459 -#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_REQ 460 -#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_RES 461 -#define K_SYSCALL_SIP_SVC_PLAT_FORMAT_TRANS_ID 462 -#define K_SYSCALL_SIP_SVC_PLAT_FREE_ASYNC_MEMORY 463 -#define K_SYSCALL_SIP_SVC_PLAT_FUNC_ID_VALID 464 -#define K_SYSCALL_SIP_SVC_PLAT_GET_ERROR_CODE 465 -#define K_SYSCALL_SIP_SVC_PLAT_GET_TRANS_IDX 466 -#define K_SYSCALL_SIP_SVC_PLAT_UPDATE_TRANS_ID 467 -#define K_SYSCALL_SMBUS_BLOCK_PCALL 468 -#define K_SYSCALL_SMBUS_BLOCK_READ 469 -#define K_SYSCALL_SMBUS_BLOCK_WRITE 470 -#define K_SYSCALL_SMBUS_BYTE_DATA_READ 471 -#define K_SYSCALL_SMBUS_BYTE_DATA_WRITE 472 -#define K_SYSCALL_SMBUS_BYTE_READ 473 -#define K_SYSCALL_SMBUS_BYTE_WRITE 474 -#define K_SYSCALL_SMBUS_CONFIGURE 475 -#define K_SYSCALL_SMBUS_GET_CONFIG 476 -#define K_SYSCALL_SMBUS_HOST_NOTIFY_REMOVE_CB 477 -#define K_SYSCALL_SMBUS_PCALL 478 -#define K_SYSCALL_SMBUS_QUICK 479 -#define K_SYSCALL_SMBUS_SMBALERT_REMOVE_CB 480 -#define K_SYSCALL_SMBUS_WORD_DATA_READ 481 -#define K_SYSCALL_SMBUS_WORD_DATA_WRITE 482 -#define K_SYSCALL_SYSCON_GET_BASE 483 -#define K_SYSCALL_SYSCON_GET_SIZE 484 -#define K_SYSCALL_SYSCON_READ_REG 485 -#define K_SYSCALL_SYSCON_WRITE_REG 486 -#define K_SYSCALL_SYS_CSRAND_GET 487 -#define K_SYSCALL_SYS_RAND_GET 488 -#define K_SYSCALL_TEE_CANCEL 489 -#define K_SYSCALL_TEE_CLOSE_SESSION 490 -#define K_SYSCALL_TEE_GET_VERSION 491 -#define K_SYSCALL_TEE_INVOKE_FUNC 492 -#define K_SYSCALL_TEE_OPEN_SESSION 493 -#define K_SYSCALL_TEE_SHM_ALLOC 494 -#define K_SYSCALL_TEE_SHM_FREE 495 -#define K_SYSCALL_TEE_SHM_REGISTER 496 -#define K_SYSCALL_TEE_SHM_UNREGISTER 497 -#define K_SYSCALL_TEE_SUPPL_RECV 498 -#define K_SYSCALL_TEE_SUPPL_SEND 499 -#define K_SYSCALL_TGPIO_PIN_CONFIG_EXT_TIMESTAMP 500 -#define K_SYSCALL_TGPIO_PIN_DISABLE 501 -#define K_SYSCALL_TGPIO_PIN_PERIODIC_OUTPUT 502 -#define K_SYSCALL_TGPIO_PIN_READ_TS_EC 503 -#define K_SYSCALL_TGPIO_PORT_GET_CYCLES_PER_SECOND 504 -#define K_SYSCALL_TGPIO_PORT_GET_TIME 505 -#define K_SYSCALL_UPDATEHUB_AUTOHANDLER 506 -#define K_SYSCALL_UPDATEHUB_CONFIRM 507 -#define K_SYSCALL_UPDATEHUB_PROBE 508 -#define K_SYSCALL_UPDATEHUB_REBOOT 509 -#define K_SYSCALL_UPDATEHUB_UPDATE 510 -#define K_SYSCALL_USER_FAULT 511 -#define K_SYSCALL_W1_CHANGE_BUS_LOCK 512 -#define K_SYSCALL_W1_CONFIGURE 513 -#define K_SYSCALL_W1_GET_SLAVE_COUNT 514 -#define K_SYSCALL_W1_READ_BIT 515 -#define K_SYSCALL_W1_READ_BLOCK 516 -#define K_SYSCALL_W1_READ_BYTE 517 -#define K_SYSCALL_W1_RESET_BUS 518 -#define K_SYSCALL_W1_SEARCH_BUS 519 -#define K_SYSCALL_W1_WRITE_BIT 520 -#define K_SYSCALL_W1_WRITE_BLOCK 521 -#define K_SYSCALL_W1_WRITE_BYTE 522 -#define K_SYSCALL_WDT_DISABLE 523 -#define K_SYSCALL_WDT_FEED 524 -#define K_SYSCALL_WDT_SETUP 525 -#define K_SYSCALL_XTENSA_USER_FAULT 526 -#define K_SYSCALL_ZSOCK_ACCEPT 527 -#define K_SYSCALL_ZSOCK_BIND 528 -#define K_SYSCALL_ZSOCK_CLOSE 529 -#define K_SYSCALL_ZSOCK_CONNECT 530 -#define K_SYSCALL_ZSOCK_FCNTL_IMPL 531 -#define K_SYSCALL_ZSOCK_GETHOSTNAME 532 -#define K_SYSCALL_ZSOCK_GETPEERNAME 533 -#define K_SYSCALL_ZSOCK_GETSOCKNAME 534 -#define K_SYSCALL_ZSOCK_GETSOCKOPT 535 -#define K_SYSCALL_ZSOCK_GET_CONTEXT_OBJECT 536 -#define K_SYSCALL_ZSOCK_INET_PTON 537 -#define K_SYSCALL_ZSOCK_IOCTL_IMPL 538 -#define K_SYSCALL_ZSOCK_LISTEN 539 -#define K_SYSCALL_ZSOCK_POLL 540 -#define K_SYSCALL_ZSOCK_RECVFROM 541 -#define K_SYSCALL_ZSOCK_RECVMSG 542 -#define K_SYSCALL_ZSOCK_SELECT 543 -#define K_SYSCALL_ZSOCK_SENDMSG 544 -#define K_SYSCALL_ZSOCK_SENDTO 545 -#define K_SYSCALL_ZSOCK_SETSOCKOPT 546 -#define K_SYSCALL_ZSOCK_SHUTDOWN 547 -#define K_SYSCALL_ZSOCK_SOCKET 548 -#define K_SYSCALL_ZSOCK_SOCKETPAIR 549 -#define K_SYSCALL_Z_ERRNO 550 -#define K_SYSCALL_Z_ZSOCK_GETADDRINFO_INTERNAL 551 +#define K_SYSCALL_ATOMIC_ADD 203 +#define K_SYSCALL_ATOMIC_AND 204 +#define K_SYSCALL_ATOMIC_CAS 205 +#define K_SYSCALL_ATOMIC_NAND 206 +#define K_SYSCALL_ATOMIC_OR 207 +#define K_SYSCALL_ATOMIC_PTR_CAS 208 +#define K_SYSCALL_ATOMIC_PTR_SET 209 +#define K_SYSCALL_ATOMIC_SET 210 +#define K_SYSCALL_ATOMIC_SUB 211 +#define K_SYSCALL_ATOMIC_XOR 212 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 213 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 214 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 215 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 216 +#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 217 +#define K_SYSCALL_AUXDISPLAY_CLEAR 218 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 219 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 220 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 221 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 222 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 223 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 224 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 225 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 226 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 227 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 228 +#define K_SYSCALL_AUXDISPLAY_IS_BUSY 229 +#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 230 +#define K_SYSCALL_AUXDISPLAY_WRITE 231 +#define K_SYSCALL_BBRAM_CHECK_INVALID 232 +#define K_SYSCALL_BBRAM_CHECK_POWER 233 +#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 234 +#define K_SYSCALL_BBRAM_GET_SIZE 235 +#define K_SYSCALL_BBRAM_READ 236 +#define K_SYSCALL_BBRAM_WRITE 237 +#define K_SYSCALL_BC12_SET_RESULT_CB 238 +#define K_SYSCALL_BC12_SET_ROLE 239 +#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 240 +#define K_SYSCALL_CAN_CALC_TIMING 241 +#define K_SYSCALL_CAN_CALC_TIMING_DATA 242 +#define K_SYSCALL_CAN_GET_BITRATE_MAX 243 +#define K_SYSCALL_CAN_GET_BITRATE_MIN 244 +#define K_SYSCALL_CAN_GET_CAPABILITIES 245 +#define K_SYSCALL_CAN_GET_CORE_CLOCK 246 +#define K_SYSCALL_CAN_GET_MAX_FILTERS 247 +#define K_SYSCALL_CAN_GET_MODE 248 +#define K_SYSCALL_CAN_GET_STATE 249 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 250 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 251 +#define K_SYSCALL_CAN_GET_TIMING_MAX 252 +#define K_SYSCALL_CAN_GET_TIMING_MIN 253 +#define K_SYSCALL_CAN_GET_TRANSCEIVER 254 +#define K_SYSCALL_CAN_RECOVER 255 +#define K_SYSCALL_CAN_REMOVE_RX_FILTER 256 +#define K_SYSCALL_CAN_SEND 257 +#define K_SYSCALL_CAN_SET_BITRATE 258 +#define K_SYSCALL_CAN_SET_BITRATE_DATA 259 +#define K_SYSCALL_CAN_SET_MODE 260 +#define K_SYSCALL_CAN_SET_TIMING 261 +#define K_SYSCALL_CAN_SET_TIMING_DATA 262 +#define K_SYSCALL_CAN_START 263 +#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 264 +#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 265 +#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 266 +#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 267 +#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 268 +#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 269 +#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 270 +#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 271 +#define K_SYSCALL_CAN_STOP 272 +#define K_SYSCALL_CHARGER_CHARGE_ENABLE 273 +#define K_SYSCALL_CHARGER_GET_PROP 274 +#define K_SYSCALL_CHARGER_SET_PROP 275 +#define K_SYSCALL_COMPARATOR_GET_OUTPUT 276 +#define K_SYSCALL_COMPARATOR_SET_TRIGGER 277 +#define K_SYSCALL_COMPARATOR_TRIGGER_IS_PENDING 278 +#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 279 +#define K_SYSCALL_COUNTER_GET_FREQUENCY 280 +#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 281 +#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 282 +#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 283 +#define K_SYSCALL_COUNTER_GET_PENDING_INT 284 +#define K_SYSCALL_COUNTER_GET_TOP_VALUE 285 +#define K_SYSCALL_COUNTER_GET_VALUE 286 +#define K_SYSCALL_COUNTER_GET_VALUE_64 287 +#define K_SYSCALL_COUNTER_IS_COUNTING_UP 288 +#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 289 +#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 290 +#define K_SYSCALL_COUNTER_SET_TOP_VALUE 291 +#define K_SYSCALL_COUNTER_START 292 +#define K_SYSCALL_COUNTER_STOP 293 +#define K_SYSCALL_COUNTER_TICKS_TO_US 294 +#define K_SYSCALL_COUNTER_US_TO_TICKS 295 +#define K_SYSCALL_DAC_CHANNEL_SETUP 296 +#define K_SYSCALL_DAC_WRITE_VALUE 297 +#define K_SYSCALL_DEVMUX_SELECT_GET 298 +#define K_SYSCALL_DEVMUX_SELECT_SET 299 +#define K_SYSCALL_EEPROM_GET_SIZE 300 +#define K_SYSCALL_EEPROM_READ 301 +#define K_SYSCALL_EEPROM_WRITE 302 +#define K_SYSCALL_EMUL_FUEL_GAUGE_IS_BATTERY_CUTOFF 303 +#define K_SYSCALL_EMUL_FUEL_GAUGE_SET_BATTERY_CHARGING 304 +#define K_SYSCALL_ESPI_CONFIG 305 +#define K_SYSCALL_ESPI_FLASH_ERASE 306 +#define K_SYSCALL_ESPI_GET_CHANNEL_STATUS 307 +#define K_SYSCALL_ESPI_READ_FLASH 308 +#define K_SYSCALL_ESPI_READ_LPC_REQUEST 309 +#define K_SYSCALL_ESPI_READ_REQUEST 310 +#define K_SYSCALL_ESPI_RECEIVE_OOB 311 +#define K_SYSCALL_ESPI_RECEIVE_VWIRE 312 +#define K_SYSCALL_ESPI_SAF_ACTIVATE 313 +#define K_SYSCALL_ESPI_SAF_CONFIG 314 +#define K_SYSCALL_ESPI_SAF_FLASH_ERASE 315 +#define K_SYSCALL_ESPI_SAF_FLASH_READ 316 +#define K_SYSCALL_ESPI_SAF_FLASH_UNSUCCESS 317 +#define K_SYSCALL_ESPI_SAF_FLASH_WRITE 318 +#define K_SYSCALL_ESPI_SAF_GET_CHANNEL_STATUS 319 +#define K_SYSCALL_ESPI_SAF_SET_PROTECTION_REGIONS 320 +#define K_SYSCALL_ESPI_SEND_OOB 321 +#define K_SYSCALL_ESPI_SEND_VWIRE 322 +#define K_SYSCALL_ESPI_WRITE_FLASH 323 +#define K_SYSCALL_ESPI_WRITE_LPC_REQUEST 324 +#define K_SYSCALL_ESPI_WRITE_REQUEST 325 +#define K_SYSCALL_FLASH_SIMULATOR_GET_MEMORY 326 +#define K_SYSCALL_FUEL_GAUGE_BATTERY_CUTOFF 327 +#define K_SYSCALL_FUEL_GAUGE_GET_BUFFER_PROP 328 +#define K_SYSCALL_FUEL_GAUGE_GET_PROP 329 +#define K_SYSCALL_FUEL_GAUGE_GET_PROPS 330 +#define K_SYSCALL_FUEL_GAUGE_SET_PROP 331 +#define K_SYSCALL_FUEL_GAUGE_SET_PROPS 332 +#define K_SYSCALL_GNSS_GET_ENABLED_SYSTEMS 333 +#define K_SYSCALL_GNSS_GET_FIX_RATE 334 +#define K_SYSCALL_GNSS_GET_LATEST_TIMEPULSE 335 +#define K_SYSCALL_GNSS_GET_NAVIGATION_MODE 336 +#define K_SYSCALL_GNSS_GET_SUPPORTED_SYSTEMS 337 +#define K_SYSCALL_GNSS_SET_ENABLED_SYSTEMS 338 +#define K_SYSCALL_GNSS_SET_FIX_RATE 339 +#define K_SYSCALL_GNSS_SET_NAVIGATION_MODE 340 +#define K_SYSCALL_HAPTICS_START_OUTPUT 341 +#define K_SYSCALL_HAPTICS_STOP_OUTPUT 342 +#define K_SYSCALL_HWSPINLOCK_GET_MAX_ID 343 +#define K_SYSCALL_HWSPINLOCK_LOCK 344 +#define K_SYSCALL_HWSPINLOCK_TRYLOCK 345 +#define K_SYSCALL_HWSPINLOCK_UNLOCK 346 +#define K_SYSCALL_I2S_BUF_READ 347 +#define K_SYSCALL_I2S_BUF_WRITE 348 +#define K_SYSCALL_I2S_CONFIGURE 349 +#define K_SYSCALL_I2S_TRIGGER 350 +#define K_SYSCALL_I3C_DO_CCC 351 +#define K_SYSCALL_I3C_TRANSFER 352 +#define K_SYSCALL_IPM_COMPLETE 353 +#define K_SYSCALL_IPM_MAX_DATA_SIZE_GET 354 +#define K_SYSCALL_IPM_MAX_ID_VAL_GET 355 +#define K_SYSCALL_IPM_SEND 356 +#define K_SYSCALL_IPM_SET_ENABLED 357 +#define K_SYSCALL_IVSHMEM_ENABLE_INTERRUPTS 358 +#define K_SYSCALL_IVSHMEM_GET_ID 359 +#define K_SYSCALL_IVSHMEM_GET_MAX_PEERS 360 +#define K_SYSCALL_IVSHMEM_GET_MEM 361 +#define K_SYSCALL_IVSHMEM_GET_OUTPUT_MEM_SECTION 362 +#define K_SYSCALL_IVSHMEM_GET_PROTOCOL 363 +#define K_SYSCALL_IVSHMEM_GET_RW_MEM_SECTION 364 +#define K_SYSCALL_IVSHMEM_GET_STATE 365 +#define K_SYSCALL_IVSHMEM_GET_VECTORS 366 +#define K_SYSCALL_IVSHMEM_INT_PEER 367 +#define K_SYSCALL_IVSHMEM_REGISTER_HANDLER 368 +#define K_SYSCALL_IVSHMEM_SET_STATE 369 +#define K_SYSCALL_KSCAN_CONFIG 370 +#define K_SYSCALL_KSCAN_DISABLE_CALLBACK 371 +#define K_SYSCALL_KSCAN_ENABLE_CALLBACK 372 +#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_IN_GET 373 +#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_OUT_GET 374 +#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_EVICTION_GET 375 +#define K_SYSCALL_K_MEM_PAGING_STATS_GET 376 +#define K_SYSCALL_K_MEM_PAGING_THREAD_STATS_GET 377 +#define K_SYSCALL_LED_BLINK 378 +#define K_SYSCALL_LED_GET_INFO 379 +#define K_SYSCALL_LED_OFF 380 +#define K_SYSCALL_LED_ON 381 +#define K_SYSCALL_LED_SET_BRIGHTNESS 382 +#define K_SYSCALL_LED_SET_CHANNEL 383 +#define K_SYSCALL_LED_SET_COLOR 384 +#define K_SYSCALL_LED_WRITE_CHANNELS 385 +#define K_SYSCALL_MAXIM_DS3231_GET_SYNCPOINT 386 +#define K_SYSCALL_MAXIM_DS3231_REQ_SYNCPOINT 387 +#define K_SYSCALL_MBOX_MAX_CHANNELS_GET 388 +#define K_SYSCALL_MBOX_MTU_GET 389 +#define K_SYSCALL_MBOX_SEND 390 +#define K_SYSCALL_MBOX_SET_ENABLED 391 +#define K_SYSCALL_MDIO_BUS_DISABLE 392 +#define K_SYSCALL_MDIO_BUS_ENABLE 393 +#define K_SYSCALL_MDIO_READ 394 +#define K_SYSCALL_MDIO_READ_C45 395 +#define K_SYSCALL_MDIO_WRITE 396 +#define K_SYSCALL_MDIO_WRITE_C45 397 +#define K_SYSCALL_MSPI_CONFIG 398 +#define K_SYSCALL_MSPI_DEV_CONFIG 399 +#define K_SYSCALL_MSPI_GET_CHANNEL_STATUS 400 +#define K_SYSCALL_MSPI_SCRAMBLE_CONFIG 401 +#define K_SYSCALL_MSPI_TIMING_CONFIG 402 +#define K_SYSCALL_MSPI_TRANSCEIVE 403 +#define K_SYSCALL_MSPI_XIP_CONFIG 404 +#define K_SYSCALL_NET_ADDR_NTOP 405 +#define K_SYSCALL_NET_ADDR_PTON 406 +#define K_SYSCALL_NET_ETH_GET_PTP_CLOCK_BY_INDEX 407 +#define K_SYSCALL_NET_IF_GET_BY_INDEX 408 +#define K_SYSCALL_NET_IF_IPV4_ADDR_ADD_BY_INDEX 409 +#define K_SYSCALL_NET_IF_IPV4_ADDR_LOOKUP_BY_INDEX 410 +#define K_SYSCALL_NET_IF_IPV4_ADDR_RM_BY_INDEX 411 +#define K_SYSCALL_NET_IF_IPV4_SET_GW_BY_INDEX 412 +#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_ADDR_BY_INDEX 413 +#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_INDEX 414 +#define K_SYSCALL_NET_IF_IPV6_ADDR_ADD_BY_INDEX 415 +#define K_SYSCALL_NET_IF_IPV6_ADDR_LOOKUP_BY_INDEX 416 +#define K_SYSCALL_NET_IF_IPV6_ADDR_RM_BY_INDEX 417 +#define K_SYSCALL_NET_SOCKET_SERVICE_REGISTER 418 +#define K_SYSCALL_NRF_QSPI_NOR_XIP_ENABLE 419 +#define K_SYSCALL_PECI_CONFIG 420 +#define K_SYSCALL_PECI_DISABLE 421 +#define K_SYSCALL_PECI_ENABLE 422 +#define K_SYSCALL_PECI_TRANSFER 423 +#define K_SYSCALL_PS2_CONFIG 424 +#define K_SYSCALL_PS2_DISABLE_CALLBACK 425 +#define K_SYSCALL_PS2_ENABLE_CALLBACK 426 +#define K_SYSCALL_PS2_READ 427 +#define K_SYSCALL_PS2_WRITE 428 +#define K_SYSCALL_PTP_CLOCK_GET 429 +#define K_SYSCALL_RETAINED_MEM_CLEAR 430 +#define K_SYSCALL_RETAINED_MEM_READ 431 +#define K_SYSCALL_RETAINED_MEM_SIZE 432 +#define K_SYSCALL_RETAINED_MEM_WRITE 433 +#define K_SYSCALL_RTC_ALARM_GET_SUPPORTED_FIELDS 434 +#define K_SYSCALL_RTC_ALARM_GET_TIME 435 +#define K_SYSCALL_RTC_ALARM_IS_PENDING 436 +#define K_SYSCALL_RTC_ALARM_SET_CALLBACK 437 +#define K_SYSCALL_RTC_ALARM_SET_TIME 438 +#define K_SYSCALL_RTC_GET_CALIBRATION 439 +#define K_SYSCALL_RTC_GET_TIME 440 +#define K_SYSCALL_RTC_SET_CALIBRATION 441 +#define K_SYSCALL_RTC_SET_TIME 442 +#define K_SYSCALL_RTC_UPDATE_SET_CALLBACK 443 +#define K_SYSCALL_RTIO_CQE_COPY_OUT 444 +#define K_SYSCALL_RTIO_CQE_GET_MEMPOOL_BUFFER 445 +#define K_SYSCALL_RTIO_RELEASE_BUFFER 446 +#define K_SYSCALL_RTIO_SQE_CANCEL 447 +#define K_SYSCALL_RTIO_SQE_COPY_IN_GET_HANDLES 448 +#define K_SYSCALL_RTIO_SUBMIT 449 +#define K_SYSCALL_SDHC_CARD_BUSY 450 +#define K_SYSCALL_SDHC_CARD_PRESENT 451 +#define K_SYSCALL_SDHC_DISABLE_INTERRUPT 452 +#define K_SYSCALL_SDHC_ENABLE_INTERRUPT 453 +#define K_SYSCALL_SDHC_EXECUTE_TUNING 454 +#define K_SYSCALL_SDHC_GET_HOST_PROPS 455 +#define K_SYSCALL_SDHC_HW_RESET 456 +#define K_SYSCALL_SDHC_REQUEST 457 +#define K_SYSCALL_SDHC_SET_IO 458 +#define K_SYSCALL_SENSOR_ATTR_GET 459 +#define K_SYSCALL_SENSOR_ATTR_SET 460 +#define K_SYSCALL_SENSOR_CHANNEL_GET 461 +#define K_SYSCALL_SENSOR_GET_DECODER 462 +#define K_SYSCALL_SENSOR_RECONFIGURE_READ_IODEV 463 +#define K_SYSCALL_SENSOR_SAMPLE_FETCH 464 +#define K_SYSCALL_SENSOR_SAMPLE_FETCH_CHAN 465 +#define K_SYSCALL_SIP_SUPERVISORY_CALL 466 +#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_REQ 467 +#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_RES 468 +#define K_SYSCALL_SIP_SVC_PLAT_FORMAT_TRANS_ID 469 +#define K_SYSCALL_SIP_SVC_PLAT_FREE_ASYNC_MEMORY 470 +#define K_SYSCALL_SIP_SVC_PLAT_FUNC_ID_VALID 471 +#define K_SYSCALL_SIP_SVC_PLAT_GET_ERROR_CODE 472 +#define K_SYSCALL_SIP_SVC_PLAT_GET_TRANS_IDX 473 +#define K_SYSCALL_SIP_SVC_PLAT_UPDATE_TRANS_ID 474 +#define K_SYSCALL_SMBUS_BLOCK_PCALL 475 +#define K_SYSCALL_SMBUS_BLOCK_READ 476 +#define K_SYSCALL_SMBUS_BLOCK_WRITE 477 +#define K_SYSCALL_SMBUS_BYTE_DATA_READ 478 +#define K_SYSCALL_SMBUS_BYTE_DATA_WRITE 479 +#define K_SYSCALL_SMBUS_BYTE_READ 480 +#define K_SYSCALL_SMBUS_BYTE_WRITE 481 +#define K_SYSCALL_SMBUS_CONFIGURE 482 +#define K_SYSCALL_SMBUS_GET_CONFIG 483 +#define K_SYSCALL_SMBUS_HOST_NOTIFY_REMOVE_CB 484 +#define K_SYSCALL_SMBUS_PCALL 485 +#define K_SYSCALL_SMBUS_QUICK 486 +#define K_SYSCALL_SMBUS_SMBALERT_REMOVE_CB 487 +#define K_SYSCALL_SMBUS_WORD_DATA_READ 488 +#define K_SYSCALL_SMBUS_WORD_DATA_WRITE 489 +#define K_SYSCALL_STEPPER_ENABLE 490 +#define K_SYSCALL_STEPPER_GET_ACTUAL_POSITION 491 +#define K_SYSCALL_STEPPER_GET_MICRO_STEP_RES 492 +#define K_SYSCALL_STEPPER_IS_MOVING 493 +#define K_SYSCALL_STEPPER_MOVE_BY 494 +#define K_SYSCALL_STEPPER_MOVE_TO 495 +#define K_SYSCALL_STEPPER_RUN 496 +#define K_SYSCALL_STEPPER_SET_EVENT_CALLBACK 497 +#define K_SYSCALL_STEPPER_SET_MAX_VELOCITY 498 +#define K_SYSCALL_STEPPER_SET_MICRO_STEP_RES 499 +#define K_SYSCALL_STEPPER_SET_REFERENCE_POSITION 500 +#define K_SYSCALL_SYSCON_GET_BASE 501 +#define K_SYSCALL_SYSCON_GET_SIZE 502 +#define K_SYSCALL_SYSCON_READ_REG 503 +#define K_SYSCALL_SYSCON_WRITE_REG 504 +#define K_SYSCALL_TEE_CANCEL 505 +#define K_SYSCALL_TEE_CLOSE_SESSION 506 +#define K_SYSCALL_TEE_GET_VERSION 507 +#define K_SYSCALL_TEE_INVOKE_FUNC 508 +#define K_SYSCALL_TEE_OPEN_SESSION 509 +#define K_SYSCALL_TEE_SHM_ALLOC 510 +#define K_SYSCALL_TEE_SHM_FREE 511 +#define K_SYSCALL_TEE_SHM_REGISTER 512 +#define K_SYSCALL_TEE_SHM_UNREGISTER 513 +#define K_SYSCALL_TEE_SUPPL_RECV 514 +#define K_SYSCALL_TEE_SUPPL_SEND 515 +#define K_SYSCALL_TGPIO_PIN_CONFIG_EXT_TIMESTAMP 516 +#define K_SYSCALL_TGPIO_PIN_DISABLE 517 +#define K_SYSCALL_TGPIO_PIN_PERIODIC_OUTPUT 518 +#define K_SYSCALL_TGPIO_PIN_READ_TS_EC 519 +#define K_SYSCALL_TGPIO_PORT_GET_CYCLES_PER_SECOND 520 +#define K_SYSCALL_TGPIO_PORT_GET_TIME 521 +#define K_SYSCALL_UPDATEHUB_AUTOHANDLER 522 +#define K_SYSCALL_UPDATEHUB_CONFIRM 523 +#define K_SYSCALL_UPDATEHUB_PROBE 524 +#define K_SYSCALL_UPDATEHUB_REBOOT 525 +#define K_SYSCALL_UPDATEHUB_UPDATE 526 +#define K_SYSCALL_USER_FAULT 527 +#define K_SYSCALL_W1_CHANGE_BUS_LOCK 528 +#define K_SYSCALL_W1_CONFIGURE 529 +#define K_SYSCALL_W1_GET_SLAVE_COUNT 530 +#define K_SYSCALL_W1_READ_BIT 531 +#define K_SYSCALL_W1_READ_BLOCK 532 +#define K_SYSCALL_W1_READ_BYTE 533 +#define K_SYSCALL_W1_RESET_BUS 534 +#define K_SYSCALL_W1_SEARCH_BUS 535 +#define K_SYSCALL_W1_WRITE_BIT 536 +#define K_SYSCALL_W1_WRITE_BLOCK 537 +#define K_SYSCALL_W1_WRITE_BYTE 538 +#define K_SYSCALL_WDT_DISABLE 539 +#define K_SYSCALL_WDT_FEED 540 +#define K_SYSCALL_WDT_SETUP 541 +#define K_SYSCALL_XTENSA_USER_FAULT 542 +#define K_SYSCALL_ZSOCK_ACCEPT 543 +#define K_SYSCALL_ZSOCK_BIND 544 +#define K_SYSCALL_ZSOCK_CLOSE 545 +#define K_SYSCALL_ZSOCK_CONNECT 546 +#define K_SYSCALL_ZSOCK_FCNTL_IMPL 547 +#define K_SYSCALL_ZSOCK_GETHOSTNAME 548 +#define K_SYSCALL_ZSOCK_GETPEERNAME 549 +#define K_SYSCALL_ZSOCK_GETSOCKNAME 550 +#define K_SYSCALL_ZSOCK_GETSOCKOPT 551 +#define K_SYSCALL_ZSOCK_GET_CONTEXT_OBJECT 552 +#define K_SYSCALL_ZSOCK_INET_PTON 553 +#define K_SYSCALL_ZSOCK_IOCTL_IMPL 554 +#define K_SYSCALL_ZSOCK_LISTEN 555 +#define K_SYSCALL_ZSOCK_RECVFROM 556 +#define K_SYSCALL_ZSOCK_RECVMSG 557 +#define K_SYSCALL_ZSOCK_SENDMSG 558 +#define K_SYSCALL_ZSOCK_SENDTO 559 +#define K_SYSCALL_ZSOCK_SETSOCKOPT 560 +#define K_SYSCALL_ZSOCK_SHUTDOWN 561 +#define K_SYSCALL_ZSOCK_SOCKET 562 +#define K_SYSCALL_ZSOCK_SOCKETPAIR 563 +#define K_SYSCALL_ZVFS_POLL 564 +#define K_SYSCALL_ZVFS_SELECT 565 +#define K_SYSCALL_Z_ERRNO 566 +#define K_SYSCALL_Z_ZSOCK_GETADDRINFO_INTERNAL 567 #ifndef _ASMLANGUAGE diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h index 45e4e9b2..6b31bcd0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/autoconf.h @@ -8,50 +8,51 @@ #define CONFIG_FLASH_SIZE 1024 #define CONFIG_FLASH_BASE_ADDRESS 0x8000000 #define CONFIG_MP_MAX_NUM_CPUS 1 +#define CONFIG_MAIN_STACK_SIZE 32768 +#define CONFIG_IDLE_STACK_SIZE 320 +#define CONFIG_ISR_STACK_SIZE 2048 +#define CONFIG_CLOCK_CONTROL 1 #define CONFIG_SYS_CLOCK_TICKS_PER_SEC 10000 #define CONFIG_ROM_START_OFFSET 0x0 -#define CONFIG_PINCTRL 1 +#define CONFIG_KERNEL_ENTRY "__start" #define CONFIG_BUILD_OUTPUT_BIN 1 #define CONFIG_XIP 1 -#define CONFIG_MAIN_STACK_SIZE 32768 -#define CONFIG_IDLE_STACK_SIZE 320 #define CONFIG_HAS_FLASH_LOAD_OFFSET 1 #define CONFIG_CPU_HAS_ARM_MPU 1 #define CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION 1 #define CONFIG_STM32H7_DUAL_CORE 1 #define CONFIG_TICKLESS_KERNEL 1 +#define CONFIG_ENTROPY_STM32_CLK_CHECK 1 #define CONFIG_FPU 1 #define CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE 1024 #define CONFIG_CORTEX_M_SYSTICK 1 -#define CONFIG_CLOCK_CONTROL_STM32_CUBE 1 #define CONFIG_CLOCK_CONTROL_INIT_PRIORITY 1 #define CONFIG_USE_DT_CODE_PARTITION 1 #define CONFIG_CACHE_MANAGEMENT 1 +#define CONFIG_GEN_IRQ_VECTOR_TABLE 1 +#define CONFIG_GEN_ISR_TABLES 1 +#define CONFIG_INIT_STACKS 1 +#define CONFIG_TIMESLICE_SIZE 0 #define CONFIG_FLASH_LOAD_OFFSET 0x40000 -#define CONFIG_FLASH 1 -#define CONFIG_HEAP_MEM_POOL_SIZE 32768 -#define CONFIG_SERIAL_INIT_PRIORITY 50 +#define CONFIG_SYS_CLOCK_EXISTS 1 #define CONFIG_FLASH_FILL_BUFFER_SIZE 32 #define CONFIG_GPIO 1 #define CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS 1 #define CONFIG_MEMC 1 -#define CONFIG_KERNEL_ENTRY "__start" #define CONFIG_CACHE 1 #define CONFIG_DCACHE 1 #define CONFIG_LOG 1 #define CONFIG_DCACHE_LINE_SIZE 32 -#define CONFIG_GEN_IRQ_VECTOR_TABLE 1 -#define CONFIG_SOC "stm32h747xx" #define CONFIG_RESET 1 #define CONFIG_ARCH_SW_ISR_TABLE_ALIGN 4 #define CONFIG_LOG_DOMAIN_NAME "" +#define CONFIG_SHELL_BACKEND_SERIAL 1 #define CONFIG_BUILD_OUTPUT_HEX 1 -#define CONFIG_CLOCK_CONTROL 1 #define CONFIG_UART_USE_RUNTIME_CONFIGURE 1 -#define CONFIG_SOC_SERIES "stm32h7x" -#define CONFIG_SOC_FAMILY "stm32" +#define CONFIG_SERIAL_INIT_PRIORITY 50 +#define CONFIG_ENTROPY_INIT_PRIORITY 50 #define CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE -1 -#define CONFIG_GEN_ISR_TABLES 1 +#define CONFIG_SOC_TOOLCHAIN_NAME "amd_acp_6_0_adsp" #define CONFIG_GEN_SW_ISR_TABLE 1 #define CONFIG_REBOOT 1 #define CONFIG_FLASH_INIT_PRIORITY 50 @@ -59,7 +60,6 @@ #define CONFIG_SRAM_OFFSET 0x0 #define CONFIG_CONSOLE 1 #define CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN 4 -#define CONFIG_ISR_STACK_SIZE 2048 #define CONFIG_ICACHE_LINE_SIZE 32 #define CONFIG_DT_HAS_ARDUINO_HEADER_R3_ENABLED 1 #define CONFIG_DT_HAS_ARM_ARMV7M_MPU_ENABLED 1 @@ -113,6 +113,7 @@ #define CONFIG_DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED 1 #define CONFIG_DT_HAS_ZEPHYR_CDC_ACM_UART_ENABLED 1 #define CONFIG_DT_HAS_ZEPHYR_MEMORY_REGION_ENABLED 1 +#define CONFIG_TAINT_BLOBS 1 #define CONFIG_ZEPHYR_ARDUINO_API_MODULE 1 #define CONFIG_ZEPHYR_CMSIS_MODULE 1 #define CONFIG_HAS_CMSIS_CORE 1 @@ -122,13 +123,15 @@ #define CONFIG_ZEPHYR_ATMEL_MODULE 1 #define CONFIG_ZEPHYR_HAL_ESPRESSIF_MODULE 1 #define CONFIG_ZEPHYR_HAL_INFINEON_MODULE 1 +#define CONFIG_ZEPHYR_HAL_INFINEON_MODULE_BLOBS 1 #define CONFIG_ZEPHYR_HAL_INTEL_MODULE 1 #define CONFIG_ZEPHYR_HAL_NORDIC_MODULE 1 #define CONFIG_ZEPHYR_HAL_NXP_MODULE 1 +#define CONFIG_ZEPHYR_HAL_NXP_MODULE_BLOBS 1 #define CONFIG_ZEPHYR_HAL_RENESAS_MODULE 1 #define CONFIG_ZEPHYR_HAL_RPI_PICO_MODULE 1 #define CONFIG_ZEPHYR_HAL_SILABS_MODULE 1 -#define CONFIG_ZEPHYR_STM32_MODULE 1 +#define CONFIG_ZEPHYR_HAL_STM32_MODULE 1 #define CONFIG_ZEPHYR_TI_MODULE 1 #define CONFIG_ZEPHYR_XTENSA_MODULE 1 #define CONFIG_ZEPHYR_LITTLEFS_MODULE 1 @@ -145,8 +148,8 @@ #define CONFIG_USE_STM32_HAL_SDRAM 1 #define CONFIG_USE_STM32_LL_DMA 1 #define CONFIG_USE_STM32_LL_FMC 1 -#define CONFIG_USE_STM32_LL_I2C 1 #define CONFIG_USE_STM32_LL_RCC 1 +#define CONFIG_USE_STM32_LL_RNG 1 #define CONFIG_USE_STM32_LL_SPI 1 #define CONFIG_USE_STM32_LL_TIM 1 #define CONFIG_USE_STM32_LL_USB 1 @@ -157,6 +160,9 @@ #define CONFIG_BOARD_ARDUINO_GIGA_R1 1 #define CONFIG_BOARD_ARDUINO_GIGA_R1_STM32H747XX_M7 1 #define CONFIG_BOARD_QUALIFIERS "stm32h747xx/m7" +#define CONFIG_SOC "stm32h747xx" +#define CONFIG_SOC_SERIES "stm32h7x" +#define CONFIG_SOC_FAMILY "stm32" #define CONFIG_SOC_FAMILY_STM32 1 #define CONFIG_SOC_SERIES_STM32H7X 1 #define CONFIG_SOC_STM32H747XX_M7 1 @@ -206,6 +212,7 @@ #define CONFIG_ARCH_HAS_RAMFUNC_SUPPORT 1 #define CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION 1 #define CONFIG_ARCH_SUPPORTS_COREDUMP 1 +#define CONFIG_ARCH_SUPPORTS_COREDUMP_THREADS 1 #define CONFIG_ARCH_SUPPORTS_ARCH_HW_INIT 1 #define CONFIG_ARCH_SUPPORTS_ROM_START 1 #define CONFIG_ARCH_HAS_EXTRA_EXCEPTION_INFO 1 @@ -221,6 +228,7 @@ #define CONFIG_ICACHE 1 #define CONFIG_ARCH_CACHE 1 #define CONFIG_TOOLCHAIN_HAS_BUILTIN_FFS 1 +#define CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN 1 #define CONFIG_KERNEL_LOG_LEVEL_DEFAULT 1 #define CONFIG_KERNEL_LOG_LEVEL 3 #define CONFIG_MULTITHREADING 1 @@ -237,7 +245,6 @@ #define CONFIG_LIBC_ERRNO 1 #define CONFIG_ERRNO 1 #define CONFIG_CURRENT_THREAD_USE_TLS 1 -#define CONFIG_INIT_STACKS 1 #define CONFIG_BOOT_BANNER 1 #define CONFIG_BOOT_BANNER_STRING "Booting Zephyr OS build" #define CONFIG_BOOT_DELAY 0 @@ -248,37 +255,38 @@ #define CONFIG_BARRIER_OPERATIONS_ARCH 1 #define CONFIG_ATOMIC_OPERATIONS_BUILTIN 1 #define CONFIG_TIMESLICING 1 -#define CONFIG_TIMESLICE_SIZE 0 #define CONFIG_TIMESLICE_PRIORITY 0 #define CONFIG_POLL 1 #define CONFIG_NUM_MBOX_ASYNC_MSGS 10 #define CONFIG_KERNEL_MEM_POOL 1 -#define CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN 1 +#define CONFIG_HEAP_MEM_POOL_SIZE 2048 #define CONFIG_SWAP_NONATOMIC 1 -#define CONFIG_SYS_CLOCK_EXISTS 1 #define CONFIG_TIMEOUT_64BIT 1 #define CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS 365 -#define CONFIG_MP_NUM_CPUS 1 +#define CONFIG_STACK_POINTER_RANDOM 0 #define CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE 1 #define CONFIG_THREAD_LOCAL_STORAGE 1 #define CONFIG_KERNEL_WHOLE_ARCHIVE 1 #define CONFIG_TOOLCHAIN_SUPPORTS_STATIC_INIT_GNU 1 +#define CONFIG_STATIC_INIT_GNU 1 +#define CONFIG_DEVICE_DT_METADATA 1 #define CONFIG_KERNEL_INIT_PRIORITY_OBJECTS 30 #define CONFIG_KERNEL_INIT_PRIORITY_LIBC 35 #define CONFIG_KERNEL_INIT_PRIORITY_DEFAULT 40 #define CONFIG_KERNEL_INIT_PRIORITY_DEVICE 50 #define CONFIG_APPLICATION_INIT_PRIORITY 90 +#define CONFIG_SOC_EARLY_INIT_HOOK 1 #define CONFIG_ADC 1 #define CONFIG_ADC_LOG_LEVEL_DEFAULT 1 #define CONFIG_ADC_LOG_LEVEL 3 #define CONFIG_ADC_STM32 1 +#define CONFIG_FLASH 1 #define CONFIG_CACHE_LOG_LEVEL_DEFAULT 1 #define CONFIG_CACHE_LOG_LEVEL 3 #define CONFIG_CLOCK_CONTROL_LOG_LEVEL_DEFAULT 1 #define CONFIG_CLOCK_CONTROL_LOG_LEVEL 3 +#define CONFIG_CLOCK_CONTROL_STM32_CUBE 1 #define CONFIG_CLOCK_STM32_HSE_CLOCK 16000000 -#define CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK 1 -#define CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK 1 #define CONFIG_CLOCK_CONTROL_PWM 1 #define CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY 51 #define CONFIG_CONSOLE_INPUT_MAX_LINE_LEN 128 @@ -295,15 +303,25 @@ #define CONFIG_DMA_STM32_V1 1 #define CONFIG_DMAMUX_STM32 1 #define CONFIG_DMAMUX_STM32_INIT_PRIORITY 41 +#define CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM 16 +#define CONFIG_ENTROPY_GENERATOR 1 +#define CONFIG_ENTROPY_LOG_LEVEL_DEFAULT 1 +#define CONFIG_ENTROPY_LOG_LEVEL 3 +#define CONFIG_ENTROPY_STM32_RNG 1 +#define CONFIG_ENTROPY_STM32_THR_POOL_SIZE 8 +#define CONFIG_ENTROPY_STM32_THR_THRESHOLD 4 +#define CONFIG_ENTROPY_STM32_ISR_POOL_SIZE 16 +#define CONFIG_ENTROPY_STM32_ISR_THRESHOLD 12 +#define CONFIG_ENTROPY_HAS_DRIVER 1 #define CONFIG_FLASH_HAS_DRIVER_ENABLED 1 #define CONFIG_FLASH_HAS_EXPLICIT_ERASE 1 #define CONFIG_FLASH_HAS_PAGE_LAYOUT 1 #define CONFIG_FLASH_JESD216 1 -#define CONFIG_FLASH_LOG_LEVEL_DEFAULT 1 -#define CONFIG_FLASH_LOG_LEVEL 3 #define CONFIG_FLASH_PAGE_LAYOUT 1 #define CONFIG_SOC_FLASH_STM32 1 #define CONFIG_FLASH_STM32_QSPI 1 +#define CONFIG_FLASH_LOG_LEVEL_DEFAULT 1 +#define CONFIG_FLASH_LOG_LEVEL 3 #define CONFIG_GPIO_LOG_LEVEL_DEFAULT 1 #define CONFIG_GPIO_LOG_LEVEL 3 #define CONFIG_GPIO_STM32 1 @@ -311,10 +329,12 @@ #define CONFIG_HWINFO 1 #define CONFIG_HWINFO_LOG_LEVEL_DEFAULT 1 #define CONFIG_HWINFO_LOG_LEVEL 3 +#define CONFIG_HWINFO_HAS_DRIVER 1 #define CONFIG_HWINFO_STM32 1 #define CONFIG_I2C_STM32 1 #define CONFIG_I2C_STM32_V2 1 #define CONFIG_I2C_STM32_INTERRUPT 1 +#define CONFIG_I2C_SAM0_TRANSFER_TIMEOUT 500 #define CONFIG_I2C_INIT_PRIORITY 50 #define CONFIG_I2C_LOG_LEVEL_DEFAULT 1 #define CONFIG_I2C_LOG_LEVEL 3 @@ -322,11 +342,12 @@ #define CONFIG_INTC_LOG_LEVEL_DEFAULT 1 #define CONFIG_INTC_LOG_LEVEL 3 #define CONFIG_EXTI_STM32 1 -#define CONFIG_MEMC_LOG_LEVEL_DEFAULT 1 -#define CONFIG_MEMC_LOG_LEVEL 3 #define CONFIG_MEMC_INIT_PRIORITY 0 #define CONFIG_MEMC_STM32 1 #define CONFIG_MEMC_STM32_SDRAM 1 +#define CONFIG_MEMC_LOG_LEVEL_DEFAULT 1 +#define CONFIG_MEMC_LOG_LEVEL 3 +#define CONFIG_PINCTRL 1 #define CONFIG_PINCTRL_LOG_LEVEL_DEFAULT 1 #define CONFIG_PINCTRL_LOG_LEVEL 3 #define CONFIG_PINCTRL_STM32 1 @@ -367,6 +388,7 @@ #define CONFIG_NRF_USBD_COMMON_LOG_LEVEL 3 #define CONFIG_USBC_LOG_LEVEL_DEFAULT 1 #define CONFIG_USBC_LOG_LEVEL 3 +#define CONFIG_SHELL_STACK_SIZE 32768 #define CONFIG_FULL_LIBC_SUPPORTED 1 #define CONFIG_MINIMAL_LIBC_SUPPORTED 1 #define CONFIG_NEWLIB_LIBC_SUPPORTED 1 @@ -381,6 +403,9 @@ #define CONFIG_PICOLIBC_IO_FLOAT 1 #define CONFIG_STDOUT_CONSOLE 1 #define CONFIG_NEED_LIBC_MEM_PARTITION 1 +#define CONFIG_CPP 1 +#define CONFIG_STD_CPP17 1 +#define CONFIG_MINIMAL_LIBCPP 1 #define CONFIG_SYS_HEAP_ALLOC_LOOPS 3 #define CONFIG_SYS_HEAP_AUTO 1 #define CONFIG_ZVFS_OPEN_MAX 4 @@ -392,6 +417,7 @@ #define CONFIG_CBPRINTF_PACKAGE_LOG_LEVEL 3 #define CONFIG_CBPRINTF_CONVERT_CHECK_PTR 1 #define CONFIG_POSIX_AEP_CHOICE_NONE 1 +#define CONFIG_POSIX_C_LANG_SUPPORT_R 1 #define CONFIG_POSIX_C_LIB_EXT 1 #define CONFIG_POSIX_OPEN_MAX 4 #define CONFIG_POSIX_PAGE_SIZE 0x40 @@ -406,6 +432,7 @@ #define CONFIG_TIMER_DELAYTIMER_MAX 0 #define CONFIG_SEM_NAMELEN_MAX 0 #define CONFIG_SEM_VALUE_MAX 0 +#define CONFIG_TC_PROVIDES_POSIX_C_LANG_SUPPORT_R 1 #define CONFIG_LIBGCC_RTLIB 1 #define CONFIG_RING_BUFFER 1 #define CONFIG_PRINTK 1 @@ -413,7 +440,7 @@ #define CONFIG_ASSERT_VERBOSE 1 #define CONFIG_LLEXT 1 #define CONFIG_LLEXT_TYPE_ELF_OBJECT 1 -#define CONFIG_LLEXT_HEAP_SIZE 32 +#define CONFIG_LLEXT_HEAP_SIZE 128 #define CONFIG_LLEXT_SHELL 1 #define CONFIG_LLEXT_SHELL_MAX_SIZE 8192 #define CONFIG_LLEXT_EXPORT_DEVICES 1 @@ -429,17 +456,22 @@ #define CONFIG_LOG_PRINTK 1 #define CONFIG_LOG_TRACE_SHORT_TIMESTAMP 1 #define CONFIG_LOG_FUNC_NAME_PREFIX_DBG 1 +#define CONFIG_LOG_BACKEND_SHOW_COLOR 1 #define CONFIG_LOG_TAG_MAX_LEN 0 +#define CONFIG_LOG_OUTPUT_FORMAT_TIME_TIMESTAMP 1 #define CONFIG_LOG_USE_VLA 1 #define CONFIG_LOG_SIMPLE_MSG_OPTIMIZE 1 #define CONFIG_LOG_ALWAYS_RUNTIME 1 #define CONFIG_LOG_OUTPUT 1 +#define CONFIG_TEST_RANDOM_GENERATOR 1 #define CONFIG_TIMER_RANDOM_INITIAL_STATE 123456789 +#define CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR 1 +#define CONFIG_CSPRNG_ENABLED 1 +#define CONFIG_HARDWARE_DEVICE_CS_GENERATOR 1 #define CONFIG_SHELL 1 #define CONFIG_SHELL_LOG_LEVEL_DEFAULT 1 #define CONFIG_SHELL_LOG_LEVEL 3 #define CONFIG_SHELL_BACKENDS 1 -#define CONFIG_SHELL_BACKEND_SERIAL 1 #define CONFIG_SHELL_BACKEND_SERIAL_INIT_PRIORITY 90 #define CONFIG_SHELL_PROMPT_UART "uart:~$ " #define CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN 1 @@ -450,7 +482,7 @@ #define CONFIG_SHELL_BACKEND_SERIAL_LOG_MESSAGE_QUEUE_SIZE 512 #define CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL_DEFAULT 1 #define CONFIG_SHELL_BACKEND_SERIAL_LOG_LEVEL 5 -#define CONFIG_SHELL_STACK_SIZE 2048 +#define CONFIG_SHELL_DEVICE_HELPERS 1 #define CONFIG_SHELL_BACKSPACE_MODE_DELETE 1 #define CONFIG_SHELL_PROMPT_CHANGE 1 #define CONFIG_SHELL_PROMPT_BUFF_SIZE 20 @@ -482,10 +514,13 @@ #define CONFIG_SHELL_LOG_FORMAT_TIMESTAMP 1 #define CONFIG_SHELL_AUTOSTART 1 #define CONFIG_SHELL_CMDS_RETURN_VALUE 1 -#define CONFIG_KERNEL_SHELL 1 -#define CONFIG_KERNEL_SHELL_REBOOT_DELAY 0 #define CONFIG_DEVICE_SHELL 1 #define CONFIG_DEVMEM_SHELL 1 +#define CONFIG_KERNEL_SHELL 1 +#define CONFIG_KERNEL_SHELL_REBOOT_DELAY 0 +#define CONFIG_KERNEL_THREAD_SHELL 1 +#define CONFIG_KERNEL_THREAD_SHELL_LIST 1 +#define CONFIG_KERNEL_THREAD_SHELL_STACKS 1 #define CONFIG_FLASH_MAP 1 #define CONFIG_USB_DEVICE_STACK 1 #define CONFIG_USB_DEVICE_LOG_LEVEL_DEFAULT 1 @@ -540,9 +575,11 @@ #define CONFIG_KERNEL_BIN_NAME "zephyr" #define CONFIG_OUTPUT_STAT 1 #define CONFIG_OUTPUT_PRINT_MEMORY_USAGE 1 +#define CONFIG_BUILD_GAP_FILL_PATTERN 0xFF #define CONFIG_BUILD_OUTPUT_STRIP_PATHS 1 #define CONFIG_CHECK_INIT_PRIORITIES 1 #define CONFIG_WARN_DEPRECATED 1 #define CONFIG_EXPERIMENTAL 1 +#define CONFIG_TAINT 1 #define CONFIG_ENFORCE_ZEPHYR_STDINT 1 #define CONFIG_LEGACY_GENERATED_INCLUDE_PATH 1 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h index 2b6ce66e..0cd264d2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/devicetree_generated.h @@ -2,7 +2,7 @@ * Generated by gen_defines.py * * DTS input file: - * /home/martino/eslov-sk/hardware/arduino-git/zephyr/build/zephyr/zephyr.dts.pre + * /home/my_new_zephyr_folder/ArduinoCore-zephyr/build/zephyr/zephyr.dts.pre * * Directories with bindings: * $ZEPHYR_BASE/dts/bindings @@ -119,183 +119,186 @@ * 108 /leds/led_0 * 109 /leds/led_1 * 110 /leds/led_2 - * 111 /soc/adc@40022100 - * 112 /soc/adc@40022300 - * 113 /soc/bdma@58025400 - * 114 /soc/can@4000a000 - * 115 /soc/pin-controller@58020000/fdcan2_rx_pb5 - * 116 /soc/pin-controller@58020000/fdcan2_tx_pb13 - * 117 /soc/can@4000a400 - * 118 /soc/pin-controller@58020000/dac1_out1_pa4 - * 119 /soc/pin-controller@58020000/dac1_out2_pa5 - * 120 /soc/dac@40007400 - * 121 /soc/display-controller@50001000 - * 122 /soc/dma@40020400 - * 123 /soc/dmamux@58025800 - * 124 /soc/dsihost@50000000 - * 125 /soc/dmamux@40020800 - * 126 /soc/i2s@40003800 - * 127 /soc/i2s@40003c00 - * 128 /soc/i2s@40013000 - * 129 /soc/interrupt-controller@58000000 - * 130 /soc/mailbox@58026400 - * 131 /soc/memory@38800000 - * 132 /soc/rng@48021800 - * 133 /soc/sdmmc@48022400 - * 134 /soc/sdmmc@52007000 - * 135 /soc/serial@40004800 - * 136 /soc/serial@40005000 - * 137 /soc/serial@40007c00 - * 138 /soc/serial@58000c00 - * 139 /soc/spi@40003800 - * 140 /soc/spi@40003c00 - * 141 /soc/spi@40013400 - * 142 /soc/spi@58001400 - * 143 /soc/timer@e000e010 - * 144 /soc/timers@40002400 - * 145 /soc/usb@40040000 - * 146 /soc/watchdog@50003000 - * 147 /soc/watchdog@58004800 - * 148 /soc/adc@40022000/channel@0 - * 149 /soc/adc@40022000/channel@1 - * 150 /soc/adc@40022000/channel@4 - * 151 /soc/adc@40022000/channel@5 - * 152 /soc/adc@40022000/channel@8 - * 153 /soc/adc@40022000/channel@9 - * 154 /soc/adc@40022000/channel@a - * 155 /soc/adc@40022000/channel@c - * 156 /soc/adc@40022000/channel@d - * 157 /soc/adc@40022000/channel@10 - * 158 /soc/adc@40022000/channel@12 - * 159 /soc/adc@40022000/channel@13 - * 160 /soc/adc@58026000/channel@0 - * 161 /soc/adc@58026000/channel@1 - * 162 /soc/dma@40020000 - * 163 /soc/i2c@58001c00/ov7670@21 - * 164 /soc/pin-controller@58020000/dcmi_d0_ph9 - * 165 /soc/pin-controller@58020000/dcmi_d1_ph10 - * 166 /soc/pin-controller@58020000/dcmi_d2_ph11 - * 167 /soc/pin-controller@58020000/dcmi_d3_pg11 - * 168 /soc/pin-controller@58020000/dcmi_d4_ph14 - * 169 /soc/pin-controller@58020000/dcmi_d5_pi4 - * 170 /soc/pin-controller@58020000/dcmi_d6_pi6 - * 171 /soc/pin-controller@58020000/dcmi_d7_pi7 - * 172 /soc/pin-controller@58020000/dcmi_hsync_ph8 - * 173 /soc/pin-controller@58020000/dcmi_pixclk_pa6 - * 174 /soc/pin-controller@58020000/dcmi_vsync_pi5 - * 175 /soc/dcmi@48020000 - * 176 /soc/dcmi@48020000/port - * 177 /soc/dcmi@48020000/port/endpoint - * 178 /soc/ethernet@40028000 - * 179 /soc/ethernet@40028000/mdio - * 180 /soc/flash-controller@52002000 - * 181 /soc/flash-controller@52002000/flash@8000000 - * 182 /soc/flash-controller@52002000/flash@8000000/partitions - * 183 /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 - * 184 /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 - * 185 /soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000 - * 186 /soc/i2c@58001c00/ov7670@21/port - * 187 /soc/i2c@58001c00/ov7670@21/port/endpoint - * 188 /soc/pin-controller@58020000/fmc_a0_pf0 - * 189 /soc/pin-controller@58020000/fmc_a10_pg0 - * 190 /soc/pin-controller@58020000/fmc_a11_pg1 - * 191 /soc/pin-controller@58020000/fmc_a12_pg2 - * 192 /soc/pin-controller@58020000/fmc_a14_pg4 - * 193 /soc/pin-controller@58020000/fmc_a15_pg5 - * 194 /soc/pin-controller@58020000/fmc_a1_pf1 - * 195 /soc/pin-controller@58020000/fmc_a2_pf2 - * 196 /soc/pin-controller@58020000/fmc_a3_pf3 - * 197 /soc/pin-controller@58020000/fmc_a4_pf4 - * 198 /soc/pin-controller@58020000/fmc_a5_pf5 - * 199 /soc/pin-controller@58020000/fmc_a6_pf12 - * 200 /soc/pin-controller@58020000/fmc_a7_pf13 - * 201 /soc/pin-controller@58020000/fmc_a8_pf14 - * 202 /soc/pin-controller@58020000/fmc_a9_pf15 - * 203 /soc/pin-controller@58020000/fmc_d0_pd14 - * 204 /soc/pin-controller@58020000/fmc_d10_pe13 - * 205 /soc/pin-controller@58020000/fmc_d11_pe14 - * 206 /soc/pin-controller@58020000/fmc_d12_pe15 - * 207 /soc/pin-controller@58020000/fmc_d13_pd8 - * 208 /soc/pin-controller@58020000/fmc_d14_pd9 - * 209 /soc/pin-controller@58020000/fmc_d15_pd10 - * 210 /soc/pin-controller@58020000/fmc_d1_pd15 - * 211 /soc/pin-controller@58020000/fmc_d2_pd0 - * 212 /soc/pin-controller@58020000/fmc_d3_pd1 - * 213 /soc/pin-controller@58020000/fmc_d4_pe7 - * 214 /soc/pin-controller@58020000/fmc_d5_pe8 - * 215 /soc/pin-controller@58020000/fmc_d6_pe9 - * 216 /soc/pin-controller@58020000/fmc_d7_pe10 - * 217 /soc/pin-controller@58020000/fmc_d8_pe11 - * 218 /soc/pin-controller@58020000/fmc_d9_pe12 - * 219 /soc/pin-controller@58020000/fmc_nbl0_pe0 - * 220 /soc/pin-controller@58020000/fmc_nbl1_pe1 - * 221 /soc/pin-controller@58020000/fmc_sdcke0_ph2 - * 222 /soc/pin-controller@58020000/fmc_sdclk_pg8 - * 223 /soc/pin-controller@58020000/fmc_sdncas_pg15 - * 224 /soc/pin-controller@58020000/fmc_sdne0_ph3 - * 225 /soc/pin-controller@58020000/fmc_sdnras_pf11 - * 226 /soc/pin-controller@58020000/fmc_sdnwe_ph5 - * 227 /soc/memory-controller@52004000 - * 228 /soc/memory-controller@52004000/sdram - * 229 /soc/memory-controller@52004000/sdram/bank@0 - * 230 /soc/pin-controller@58020000/gpio@58021400 - * 231 /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 - * 232 /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 - * 233 /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 - * 234 /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 - * 235 /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 - * 236 /soc/pin-controller@58020000/quadspi_clk_pf10 - * 237 /soc/quadspi@52005000 - * 238 /soc/quadspi@52005000/qspi-nor-flash@90000000 - * 239 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions - * 240 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 - * 241 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 - * 242 /soc/rtc@58004000 - * 243 /soc/rtc@58004000/backup_regs - * 244 /soc/pin-controller@58020000/uart7_cts_pf9 - * 245 /soc/pin-controller@58020000/uart7_rts_pf8 - * 246 /soc/pin-controller@58020000/uart7_rx_pa8 - * 247 /soc/pin-controller@58020000/uart7_tx_pf7 - * 248 /soc/serial@40007800 - * 249 /soc/serial@40007800/bt_hci_uart - * 250 /soc/serial@40007800/bt_hci_uart/murata-1dx - * 251 /soc/timers@40000000 - * 252 /soc/timers@40000000/counter - * 253 /soc/timers@40000000/pwm - * 254 /soc/timers@40000400 - * 255 /soc/timers@40000400/counter - * 256 /soc/timers@40000400/pwm - * 257 /soc/timers@40000800 - * 258 /soc/timers@40000800/counter - * 259 /soc/timers@40000800/pwm - * 260 /soc/timers@40000c00 - * 261 /soc/timers@40000c00/counter - * 262 /soc/timers@40000c00/pwm - * 263 /soc/timers@40001000 - * 264 /soc/timers@40001000/counter - * 265 /soc/timers@40001400 - * 266 /soc/timers@40001400/counter - * 267 /soc/timers@40001800 - * 268 /soc/timers@40001800/counter - * 269 /soc/timers@40001800/pwm - * 270 /soc/timers@40001c00 - * 271 /soc/timers@40001c00/counter - * 272 /soc/timers@40001c00/pwm - * 273 /soc/timers@40002000 - * 274 /soc/timers@40002000/counter - * 275 /soc/timers@40002000/pwm - * 276 /soc/timers@40010000/pwm/pwmclock - * 277 /soc/timers@40010400 - * 278 /soc/timers@40010400/pwm - * 279 /soc/timers@40014000 - * 280 /soc/timers@40014000/counter - * 281 /soc/timers@40014000/pwm - * 282 /soc/timers@40014400 - * 283 /soc/timers@40014400/counter - * 284 /soc/timers@40014400/pwm - * 285 /soc/timers@40014800 - * 286 /soc/timers@40014800/counter - * 287 /soc/timers@40014800/pwm + * 111 /mcos + * 112 /mcos/mco1 + * 113 /mcos/mco2 + * 114 /soc/adc@40022100 + * 115 /soc/adc@40022300 + * 116 /soc/bdma@58025400 + * 117 /soc/can@4000a000 + * 118 /soc/pin-controller@58020000/fdcan2_rx_pb5 + * 119 /soc/pin-controller@58020000/fdcan2_tx_pb13 + * 120 /soc/can@4000a400 + * 121 /soc/pin-controller@58020000/dac1_out1_pa4 + * 122 /soc/pin-controller@58020000/dac1_out2_pa5 + * 123 /soc/dac@40007400 + * 124 /soc/display-controller@50001000 + * 125 /soc/dma@40020400 + * 126 /soc/dmamux@58025800 + * 127 /soc/dsihost@50000000 + * 128 /soc/dmamux@40020800 + * 129 /soc/i2s@40003800 + * 130 /soc/i2s@40003c00 + * 131 /soc/i2s@40013000 + * 132 /soc/interrupt-controller@58000000 + * 133 /soc/mailbox@58026400 + * 134 /soc/memory@38800000 + * 135 /soc/rng@48021800 + * 136 /soc/sdmmc@48022400 + * 137 /soc/sdmmc@52007000 + * 138 /soc/serial@40004800 + * 139 /soc/serial@40005000 + * 140 /soc/serial@40007c00 + * 141 /soc/serial@58000c00 + * 142 /soc/spi@40003800 + * 143 /soc/spi@40003c00 + * 144 /soc/spi@40013400 + * 145 /soc/spi@58001400 + * 146 /soc/timer@e000e010 + * 147 /soc/timers@40002400 + * 148 /soc/usb@40040000 + * 149 /soc/watchdog@50003000 + * 150 /soc/watchdog@58004800 + * 151 /soc/adc@40022000/channel@0 + * 152 /soc/adc@40022000/channel@1 + * 153 /soc/adc@40022000/channel@4 + * 154 /soc/adc@40022000/channel@5 + * 155 /soc/adc@40022000/channel@8 + * 156 /soc/adc@40022000/channel@9 + * 157 /soc/adc@40022000/channel@a + * 158 /soc/adc@40022000/channel@c + * 159 /soc/adc@40022000/channel@d + * 160 /soc/adc@40022000/channel@10 + * 161 /soc/adc@40022000/channel@12 + * 162 /soc/adc@40022000/channel@13 + * 163 /soc/adc@58026000/channel@0 + * 164 /soc/adc@58026000/channel@1 + * 165 /soc/dma@40020000 + * 166 /soc/i2c@58001c00/ov7670@21 + * 167 /soc/pin-controller@58020000/dcmi_d0_ph9 + * 168 /soc/pin-controller@58020000/dcmi_d1_ph10 + * 169 /soc/pin-controller@58020000/dcmi_d2_ph11 + * 170 /soc/pin-controller@58020000/dcmi_d3_pg11 + * 171 /soc/pin-controller@58020000/dcmi_d4_ph14 + * 172 /soc/pin-controller@58020000/dcmi_d5_pi4 + * 173 /soc/pin-controller@58020000/dcmi_d6_pi6 + * 174 /soc/pin-controller@58020000/dcmi_d7_pi7 + * 175 /soc/pin-controller@58020000/dcmi_hsync_ph8 + * 176 /soc/pin-controller@58020000/dcmi_pixclk_pa6 + * 177 /soc/pin-controller@58020000/dcmi_vsync_pi5 + * 178 /soc/dcmi@48020000 + * 179 /soc/dcmi@48020000/port + * 180 /soc/dcmi@48020000/port/endpoint + * 181 /soc/ethernet@40028000 + * 182 /soc/ethernet@40028000/mdio + * 183 /soc/flash-controller@52002000 + * 184 /soc/flash-controller@52002000/flash@8000000 + * 185 /soc/flash-controller@52002000/flash@8000000/partitions + * 186 /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 + * 187 /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 + * 188 /soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000 + * 189 /soc/i2c@58001c00/ov7670@21/port + * 190 /soc/i2c@58001c00/ov7670@21/port/endpoint + * 191 /soc/pin-controller@58020000/fmc_a0_pf0 + * 192 /soc/pin-controller@58020000/fmc_a10_pg0 + * 193 /soc/pin-controller@58020000/fmc_a11_pg1 + * 194 /soc/pin-controller@58020000/fmc_a12_pg2 + * 195 /soc/pin-controller@58020000/fmc_a14_pg4 + * 196 /soc/pin-controller@58020000/fmc_a15_pg5 + * 197 /soc/pin-controller@58020000/fmc_a1_pf1 + * 198 /soc/pin-controller@58020000/fmc_a2_pf2 + * 199 /soc/pin-controller@58020000/fmc_a3_pf3 + * 200 /soc/pin-controller@58020000/fmc_a4_pf4 + * 201 /soc/pin-controller@58020000/fmc_a5_pf5 + * 202 /soc/pin-controller@58020000/fmc_a6_pf12 + * 203 /soc/pin-controller@58020000/fmc_a7_pf13 + * 204 /soc/pin-controller@58020000/fmc_a8_pf14 + * 205 /soc/pin-controller@58020000/fmc_a9_pf15 + * 206 /soc/pin-controller@58020000/fmc_d0_pd14 + * 207 /soc/pin-controller@58020000/fmc_d10_pe13 + * 208 /soc/pin-controller@58020000/fmc_d11_pe14 + * 209 /soc/pin-controller@58020000/fmc_d12_pe15 + * 210 /soc/pin-controller@58020000/fmc_d13_pd8 + * 211 /soc/pin-controller@58020000/fmc_d14_pd9 + * 212 /soc/pin-controller@58020000/fmc_d15_pd10 + * 213 /soc/pin-controller@58020000/fmc_d1_pd15 + * 214 /soc/pin-controller@58020000/fmc_d2_pd0 + * 215 /soc/pin-controller@58020000/fmc_d3_pd1 + * 216 /soc/pin-controller@58020000/fmc_d4_pe7 + * 217 /soc/pin-controller@58020000/fmc_d5_pe8 + * 218 /soc/pin-controller@58020000/fmc_d6_pe9 + * 219 /soc/pin-controller@58020000/fmc_d7_pe10 + * 220 /soc/pin-controller@58020000/fmc_d8_pe11 + * 221 /soc/pin-controller@58020000/fmc_d9_pe12 + * 222 /soc/pin-controller@58020000/fmc_nbl0_pe0 + * 223 /soc/pin-controller@58020000/fmc_nbl1_pe1 + * 224 /soc/pin-controller@58020000/fmc_sdcke0_ph2 + * 225 /soc/pin-controller@58020000/fmc_sdclk_pg8 + * 226 /soc/pin-controller@58020000/fmc_sdncas_pg15 + * 227 /soc/pin-controller@58020000/fmc_sdne0_ph3 + * 228 /soc/pin-controller@58020000/fmc_sdnras_pf11 + * 229 /soc/pin-controller@58020000/fmc_sdnwe_ph5 + * 230 /soc/memory-controller@52004000 + * 231 /soc/memory-controller@52004000/sdram + * 232 /soc/memory-controller@52004000/sdram/bank@0 + * 233 /soc/pin-controller@58020000/gpio@58021400 + * 234 /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 + * 235 /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 + * 236 /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 + * 237 /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 + * 238 /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 + * 239 /soc/pin-controller@58020000/quadspi_clk_pf10 + * 240 /soc/quadspi@52005000 + * 241 /soc/quadspi@52005000/qspi-nor-flash@90000000 + * 242 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions + * 243 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 + * 244 /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 + * 245 /soc/rtc@58004000 + * 246 /soc/rtc@58004000/backup_regs + * 247 /soc/pin-controller@58020000/uart7_cts_pf9 + * 248 /soc/pin-controller@58020000/uart7_rts_pf8 + * 249 /soc/pin-controller@58020000/uart7_rx_pa8 + * 250 /soc/pin-controller@58020000/uart7_tx_pf7 + * 251 /soc/serial@40007800 + * 252 /soc/serial@40007800/bt_hci_uart + * 253 /soc/serial@40007800/bt_hci_uart/murata-1dx + * 254 /soc/timers@40000000 + * 255 /soc/timers@40000000/counter + * 256 /soc/timers@40000000/pwm + * 257 /soc/timers@40000400 + * 258 /soc/timers@40000400/counter + * 259 /soc/timers@40000400/pwm + * 260 /soc/timers@40000800 + * 261 /soc/timers@40000800/counter + * 262 /soc/timers@40000800/pwm + * 263 /soc/timers@40000c00 + * 264 /soc/timers@40000c00/counter + * 265 /soc/timers@40000c00/pwm + * 266 /soc/timers@40001000 + * 267 /soc/timers@40001000/counter + * 268 /soc/timers@40001400 + * 269 /soc/timers@40001400/counter + * 270 /soc/timers@40001800 + * 271 /soc/timers@40001800/counter + * 272 /soc/timers@40001800/pwm + * 273 /soc/timers@40001c00 + * 274 /soc/timers@40001c00/counter + * 275 /soc/timers@40001c00/pwm + * 276 /soc/timers@40002000 + * 277 /soc/timers@40002000/counter + * 278 /soc/timers@40002000/pwm + * 279 /soc/timers@40010000/pwm/pwmclock + * 280 /soc/timers@40010400 + * 281 /soc/timers@40010400/pwm + * 282 /soc/timers@40014000 + * 283 /soc/timers@40014000/counter + * 284 /soc/timers@40014000/pwm + * 285 /soc/timers@40014400 + * 286 /soc/timers@40014400/counter + * 287 /soc/timers@40014400/pwm + * 288 /soc/timers@40014800 + * 289 /soc/timers@40014800/counter + * 290 /soc/timers@40014800/pwm * * Definitions derived from these nodes in dependency order are next, * followed by /chosen nodes. @@ -315,6 +318,9 @@ /* Node's name with unit-address: */ #define DT_N_FULL_NAME "/" +#define DT_N_FULL_NAME_UNQUOTED / +#define DT_N_FULL_NAME_TOKEN _ +#define DT_N_FULL_NAME_UPPER_TOKEN _ /* Helpers for dealing with node labels: */ #define DT_N_NODELABEL_NUM 0 @@ -322,16 +328,16 @@ #define DT_N_FOREACH_NODELABEL_VARGS(fn, ...) /* Helper macros for child nodes of this node. */ -#define DT_N_CHILD_NUM 25 -#define DT_N_CHILD_NUM_STATUS_OKAY 18 -#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) -#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_CHILD_NUM 26 +#define DT_N_CHILD_NUM_STATUS_OKAY 19 +#define DT_N_FOREACH_CHILD(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_mcos) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_dietemp, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vbat, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_vref, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_smbus4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_FOREACH_CHILD_STATUS_OKAY(fn) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_cpus) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_mcos) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_gpio_keys) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) fn(DT_N_S_chosen) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user) +#define DT_N_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_N_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_chosen, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_aliases, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_cpus, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_90000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_clocks, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_24000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30020000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_30040000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_memory_38000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_connector, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_leds, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_keys, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_sdram_c0000000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_zephyr_user, __VA_ARGS__) /* Node's dependency ordinal: */ #define DT_N_ORD 0 @@ -342,31 +348,32 @@ /* Ordinals for what depends directly on this node: */ #define DT_N_SUPPORTS_ORDS \ - 1, /* /aliases */ \ - 2, /* /chosen */ \ - 3, /* /connector */ \ - 4, /* /soc */ \ - 6, /* /clocks */ \ - 14, /* /dietemp */ \ - 15, /* /memory@24000000 */ \ - 16, /* /memory@30000000 */ \ - 17, /* /memory@30020000 */ \ - 18, /* /memory@30040000 */ \ - 19, /* /memory@38000000 */ \ - 20, /* /memory@90000000 */ \ - 21, /* /sdram@c0000000 */ \ - 25, /* /smbus1 */ \ - 29, /* /smbus2 */ \ - 31, /* /smbus3 */ \ - 35, /* /smbus4 */ \ - 36, /* /vbat */ \ - 37, /* /vref */ \ - 38, /* /gpio@deadbeef */ \ - 88, /* /otghs_fs_phy */ \ - 93, /* /zephyr,user */ \ - 102, /* /cpus */ \ - 105, /* /gpio_keys */ \ - 107, /* /leds */ + 1, \ + 2, \ + 3, \ + 4, \ + 6, \ + 14, \ + 15, \ + 16, \ + 17, \ + 18, \ + 19, \ + 20, \ + 21, \ + 25, \ + 29, \ + 31, \ + 35, \ + 36, \ + 37, \ + 38, \ + 88, \ + 93, \ + 102, \ + 105, \ + 107, \ + 111, /* Existence and alternate IDs: */ #define DT_N_EXISTS 1 @@ -390,11 +397,11 @@ /* Generic property macros: */ #define DT_N_P_compatible {"arduino,giga-r1"} +#define DT_N_P_compatible_IDX_0_EXISTS 1 #define DT_N_P_compatible_IDX_0 "arduino,giga-r1" #define DT_N_P_compatible_IDX_0_STRING_UNQUOTED arduino,giga-r1 #define DT_N_P_compatible_IDX_0_STRING_TOKEN arduino_giga_r1 #define DT_N_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_GIGA_R1 -#define DT_N_P_compatible_IDX_0_EXISTS 1 #define DT_N_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N, compatible, 0) #define DT_N_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N, compatible, 0) #define DT_N_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N, compatible, 0, __VA_ARGS__) @@ -413,6 +420,9 @@ /* Node's name with unit-address: */ #define DT_N_S_aliases_FULL_NAME "aliases" +#define DT_N_S_aliases_FULL_NAME_UNQUOTED aliases +#define DT_N_S_aliases_FULL_NAME_TOKEN aliases +#define DT_N_S_aliases_FULL_NAME_UPPER_TOKEN ALIASES /* Node parent (/) identifier: */ #define DT_N_S_aliases_PARENT DT_N @@ -443,7 +453,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_aliases_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_aliases_SUPPORTS_ORDS /* nothing */ @@ -475,6 +485,9 @@ /* Node's name with unit-address: */ #define DT_N_S_chosen_FULL_NAME "chosen" +#define DT_N_S_chosen_FULL_NAME_UNQUOTED chosen +#define DT_N_S_chosen_FULL_NAME_TOKEN chosen +#define DT_N_S_chosen_FULL_NAME_UPPER_TOKEN CHOSEN /* Node parent (/) identifier: */ #define DT_N_S_chosen_PARENT DT_N @@ -505,7 +518,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_chosen_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_chosen_SUPPORTS_ORDS /* nothing */ @@ -543,12 +556,15 @@ /* Node's name with unit-address: */ #define DT_N_S_connector_FULL_NAME "connector" +#define DT_N_S_connector_FULL_NAME_UNQUOTED connector +#define DT_N_S_connector_FULL_NAME_TOKEN connector +#define DT_N_S_connector_FULL_NAME_UPPER_TOKEN CONNECTOR /* Node parent (/) identifier: */ #define DT_N_S_connector_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_connector_CHILD_IDX 19 +#define DT_N_S_connector_CHILD_IDX 20 /* Helpers for dealing with node labels: */ #define DT_N_S_connector_NODELABEL_NUM 1 @@ -573,7 +589,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_connector_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_connector_SUPPORTS_ORDS /* nothing */ @@ -596,16 +612,12 @@ #define DT_N_S_connector_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_connector_P_wakeup_source 0 -#define DT_N_S_connector_P_wakeup_source_EXISTS 1 -#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_connector_P_compatible {"arduino-header-r3"} +#define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_connector_P_compatible_IDX_0 "arduino-header-r3" #define DT_N_S_connector_P_compatible_IDX_0_STRING_UNQUOTED arduino-header-r3 #define DT_N_S_connector_P_compatible_IDX_0_STRING_TOKEN arduino_header_r3 #define DT_N_S_connector_P_compatible_IDX_0_STRING_UPPER_TOKEN ARDUINO_HEADER_R3 -#define DT_N_S_connector_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_connector, compatible, 0) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_connector, compatible, 0) #define DT_N_S_connector_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_connector, compatible, 0, __VA_ARGS__) @@ -614,6 +626,10 @@ #define DT_N_S_connector_P_compatible_EXISTS 1 #define DT_N_S_connector_P_zephyr_deferred_init 0 #define DT_N_S_connector_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_connector_P_wakeup_source 0 +#define DT_N_S_connector_P_wakeup_source_EXISTS 1 +#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_connector_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc @@ -626,6 +642,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_FULL_NAME "soc" +#define DT_N_S_soc_FULL_NAME_UNQUOTED soc +#define DT_N_S_soc_FULL_NAME_TOKEN soc +#define DT_N_S_soc_FULL_NAME_UPPER_TOKEN SOC /* Node parent (/) identifier: */ #define DT_N_S_soc_PARENT DT_N @@ -656,81 +675,81 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_SUPPORTS_ORDS \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ \ - 13, /* /soc/adc@58026000 */ \ - 24, /* /soc/i2c@40005400 */ \ - 28, /* /soc/i2c@40005800 */ \ - 30, /* /soc/i2c@40005c00 */ \ - 34, /* /soc/i2c@58001c00 */ \ - 51, /* /soc/adc@40022000 */ \ - 55, /* /soc/serial@40004400 */ \ - 58, /* /soc/serial@40004c00 */ \ - 61, /* /soc/serial@40011000 */ \ - 64, /* /soc/serial@40011400 */ \ - 69, /* /soc/spi@40013000 */ \ - 74, /* /soc/spi@40015000 */ \ - 85, /* /soc/timers@40010000 */ \ - 91, /* /soc/usb@40080000 */ \ - 111, /* /soc/adc@40022100 */ \ - 112, /* /soc/adc@40022300 */ \ - 113, /* /soc/bdma@58025400 */ \ - 114, /* /soc/can@4000a000 */ \ - 117, /* /soc/can@4000a400 */ \ - 120, /* /soc/dac@40007400 */ \ - 121, /* /soc/display-controller@50001000 */ \ - 122, /* /soc/dma@40020400 */ \ - 123, /* /soc/dmamux@58025800 */ \ - 124, /* /soc/dsihost@50000000 */ \ - 125, /* /soc/dmamux@40020800 */ \ - 126, /* /soc/i2s@40003800 */ \ - 127, /* /soc/i2s@40003c00 */ \ - 128, /* /soc/i2s@40013000 */ \ - 129, /* /soc/interrupt-controller@58000000 */ \ - 130, /* /soc/mailbox@58026400 */ \ - 131, /* /soc/memory@38800000 */ \ - 132, /* /soc/rng@48021800 */ \ - 133, /* /soc/sdmmc@48022400 */ \ - 134, /* /soc/sdmmc@52007000 */ \ - 135, /* /soc/serial@40004800 */ \ - 136, /* /soc/serial@40005000 */ \ - 137, /* /soc/serial@40007c00 */ \ - 138, /* /soc/serial@58000c00 */ \ - 139, /* /soc/spi@40003800 */ \ - 140, /* /soc/spi@40003c00 */ \ - 141, /* /soc/spi@40013400 */ \ - 142, /* /soc/spi@58001400 */ \ - 143, /* /soc/timer@e000e010 */ \ - 144, /* /soc/timers@40002400 */ \ - 145, /* /soc/usb@40040000 */ \ - 146, /* /soc/watchdog@50003000 */ \ - 147, /* /soc/watchdog@58004800 */ \ - 162, /* /soc/dma@40020000 */ \ - 175, /* /soc/dcmi@48020000 */ \ - 178, /* /soc/ethernet@40028000 */ \ - 180, /* /soc/flash-controller@52002000 */ \ - 227, /* /soc/memory-controller@52004000 */ \ - 237, /* /soc/quadspi@52005000 */ \ - 242, /* /soc/rtc@58004000 */ \ - 248, /* /soc/serial@40007800 */ \ - 251, /* /soc/timers@40000000 */ \ - 254, /* /soc/timers@40000400 */ \ - 257, /* /soc/timers@40000800 */ \ - 260, /* /soc/timers@40000c00 */ \ - 263, /* /soc/timers@40001000 */ \ - 265, /* /soc/timers@40001400 */ \ - 267, /* /soc/timers@40001800 */ \ - 270, /* /soc/timers@40001c00 */ \ - 273, /* /soc/timers@40002000 */ \ - 277, /* /soc/timers@40010400 */ \ - 279, /* /soc/timers@40014000 */ \ - 282, /* /soc/timers@40014400 */ \ - 285, /* /soc/timers@40014800 */ + 5, \ + 9, \ + 10, \ + 13, \ + 24, \ + 28, \ + 30, \ + 34, \ + 51, \ + 55, \ + 58, \ + 61, \ + 64, \ + 69, \ + 74, \ + 85, \ + 91, \ + 114, \ + 115, \ + 116, \ + 117, \ + 120, \ + 123, \ + 124, \ + 125, \ + 126, \ + 127, \ + 128, \ + 129, \ + 130, \ + 131, \ + 132, \ + 133, \ + 134, \ + 135, \ + 136, \ + 137, \ + 138, \ + 139, \ + 140, \ + 141, \ + 142, \ + 143, \ + 144, \ + 145, \ + 146, \ + 147, \ + 148, \ + 149, \ + 150, \ + 165, \ + 178, \ + 181, \ + 183, \ + 230, \ + 240, \ + 245, \ + 251, \ + 254, \ + 257, \ + 260, \ + 263, \ + 266, \ + 268, \ + 270, \ + 273, \ + 276, \ + 280, \ + 282, \ + 285, \ + 288, /* Existence and alternate IDs: */ #define DT_N_S_soc_EXISTS 1 @@ -762,21 +781,21 @@ /* Generic property macros: */ #define DT_N_S_soc_P_compatible {"st,stm32h747", "st,stm32h7", "simple-bus"} +#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_0 "st,stm32h747" #define DT_N_S_soc_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h747 #define DT_N_S_soc_P_compatible_IDX_0_STRING_TOKEN st_stm32h747 #define DT_N_S_soc_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H747 -#define DT_N_S_soc_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_1 "st,stm32h7" #define DT_N_S_soc_P_compatible_IDX_1_STRING_UNQUOTED st,stm32h7 #define DT_N_S_soc_P_compatible_IDX_1_STRING_TOKEN st_stm32h7 #define DT_N_S_soc_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32H7 -#define DT_N_S_soc_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_P_compatible_IDX_2 "simple-bus" #define DT_N_S_soc_P_compatible_IDX_2_STRING_UNQUOTED simple-bus #define DT_N_S_soc_P_compatible_IDX_2_STRING_TOKEN simple_bus #define DT_N_S_soc_P_compatible_IDX_2_STRING_UPPER_TOKEN SIMPLE_BUS -#define DT_N_S_soc_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc, compatible, 0) \ fn(DT_N_S_soc, compatible, 1) \ fn(DT_N_S_soc, compatible, 2) @@ -810,6 +829,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME "interrupt-controller@e000e100" +#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UNQUOTED interrupt-controller@e000e100 +#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_TOKEN interrupt_controller_e000e100 +#define DT_N_S_soc_S_interrupt_controller_e000e100_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_E000E100 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_PARENT DT_N_S_soc @@ -840,72 +862,72 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REQUIRES_ORDS \ - 4, /* /soc */ + 4, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_SUPPORTS_ORDS \ - 13, /* /soc/adc@58026000 */ \ - 24, /* /soc/i2c@40005400 */ \ - 28, /* /soc/i2c@40005800 */ \ - 30, /* /soc/i2c@40005c00 */ \ - 34, /* /soc/i2c@58001c00 */ \ - 51, /* /soc/adc@40022000 */ \ - 55, /* /soc/serial@40004400 */ \ - 58, /* /soc/serial@40004c00 */ \ - 61, /* /soc/serial@40011000 */ \ - 64, /* /soc/serial@40011400 */ \ - 69, /* /soc/spi@40013000 */ \ - 74, /* /soc/spi@40015000 */ \ - 85, /* /soc/timers@40010000 */ \ - 91, /* /soc/usb@40080000 */ \ - 111, /* /soc/adc@40022100 */ \ - 112, /* /soc/adc@40022300 */ \ - 113, /* /soc/bdma@58025400 */ \ - 114, /* /soc/can@4000a000 */ \ - 117, /* /soc/can@4000a400 */ \ - 121, /* /soc/display-controller@50001000 */ \ - 122, /* /soc/dma@40020400 */ \ - 123, /* /soc/dmamux@58025800 */ \ - 125, /* /soc/dmamux@40020800 */ \ - 126, /* /soc/i2s@40003800 */ \ - 127, /* /soc/i2s@40003c00 */ \ - 128, /* /soc/i2s@40013000 */ \ - 129, /* /soc/interrupt-controller@58000000 */ \ - 130, /* /soc/mailbox@58026400 */ \ - 132, /* /soc/rng@48021800 */ \ - 133, /* /soc/sdmmc@48022400 */ \ - 134, /* /soc/sdmmc@52007000 */ \ - 135, /* /soc/serial@40004800 */ \ - 136, /* /soc/serial@40005000 */ \ - 137, /* /soc/serial@40007c00 */ \ - 138, /* /soc/serial@58000c00 */ \ - 139, /* /soc/spi@40003800 */ \ - 140, /* /soc/spi@40003c00 */ \ - 141, /* /soc/spi@40013400 */ \ - 142, /* /soc/spi@58001400 */ \ - 144, /* /soc/timers@40002400 */ \ - 145, /* /soc/usb@40040000 */ \ - 146, /* /soc/watchdog@50003000 */ \ - 162, /* /soc/dma@40020000 */ \ - 175, /* /soc/dcmi@48020000 */ \ - 178, /* /soc/ethernet@40028000 */ \ - 180, /* /soc/flash-controller@52002000 */ \ - 237, /* /soc/quadspi@52005000 */ \ - 242, /* /soc/rtc@58004000 */ \ - 248, /* /soc/serial@40007800 */ \ - 251, /* /soc/timers@40000000 */ \ - 254, /* /soc/timers@40000400 */ \ - 257, /* /soc/timers@40000800 */ \ - 260, /* /soc/timers@40000c00 */ \ - 263, /* /soc/timers@40001000 */ \ - 265, /* /soc/timers@40001400 */ \ - 267, /* /soc/timers@40001800 */ \ - 270, /* /soc/timers@40001c00 */ \ - 273, /* /soc/timers@40002000 */ \ - 277, /* /soc/timers@40010400 */ \ - 279, /* /soc/timers@40014000 */ \ - 282, /* /soc/timers@40014400 */ \ - 285, /* /soc/timers@40014800 */ + 13, \ + 24, \ + 28, \ + 30, \ + 34, \ + 51, \ + 55, \ + 58, \ + 61, \ + 64, \ + 69, \ + 74, \ + 85, \ + 91, \ + 114, \ + 115, \ + 116, \ + 117, \ + 120, \ + 124, \ + 125, \ + 126, \ + 128, \ + 129, \ + 130, \ + 131, \ + 132, \ + 133, \ + 135, \ + 136, \ + 137, \ + 138, \ + 139, \ + 140, \ + 141, \ + 142, \ + 143, \ + 144, \ + 145, \ + 147, \ + 148, \ + 149, \ + 165, \ + 178, \ + 181, \ + 183, \ + 240, \ + 245, \ + 251, \ + 254, \ + 257, \ + 260, \ + 263, \ + 266, \ + 268, \ + 270, \ + 273, \ + 276, \ + 280, \ + 282, \ + 285, \ + 288, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_EXISTS 1 @@ -915,8 +937,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_NUM 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 /* 0xe000e100 */ -#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 /* 0xc00 */ +#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_ADDRESS 3758153984 +#define DT_N_S_soc_S_interrupt_controller_e000e100_REG_IDX_0_VAL_SIZE 3072 #define DT_N_S_soc_S_interrupt_controller_e000e100_RANGES_NUM 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_FOREACH_RANGE(fn) #define DT_N_S_soc_S_interrupt_controller_e000e100_IRQ_NUM 0 @@ -932,34 +954,34 @@ #define DT_N_S_soc_S_interrupt_controller_e000e100_PINCTRL_NUM 0 /* Generic property macros: */ +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984, 3072} +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 4 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_interrupt_controller_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible {"arm,v7m-nvic"} +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0 "arm,v7m-nvic" #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UNQUOTED arm,v7m-nvic #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_TOKEN arm_v7m_nvic #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_V7M_NVIC -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_e000e100, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_LEN 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg {3758153984 /* 0xe000e100 */, 3072 /* 0xc00 */} -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0 3758153984 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1 3072 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_reg_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits 4 -#define DT_N_S_soc_S_interrupt_controller_e000e100_P_arm_num_irq_priority_bits_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source 0 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_interrupt_controller_e000e100_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks @@ -972,6 +994,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_FULL_NAME "clocks" +#define DT_N_S_clocks_FULL_NAME_UNQUOTED clocks +#define DT_N_S_clocks_FULL_NAME_TOKEN clocks +#define DT_N_S_clocks_FULL_NAME_UPPER_TOKEN CLOCKS /* Node parent (/) identifier: */ #define DT_N_S_clocks_PARENT DT_N @@ -1002,20 +1027,20 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_SUPPORTS_ORDS \ - 7, /* /clocks/clk-hse */ \ - 8, /* /clocks/pll@0 */ \ - 94, /* /clocks/clk-csi */ \ - 95, /* /clocks/clk-hsi */ \ - 96, /* /clocks/clk-hsi48 */ \ - 97, /* /clocks/clk-lse */ \ - 98, /* /clocks/clk-lsi */ \ - 99, /* /clocks/perck */ \ - 100, /* /clocks/pll@1 */ \ - 101, /* /clocks/pll@2 */ + 7, \ + 8, \ + 94, \ + 95, \ + 96, \ + 97, \ + 98, \ + 99, \ + 100, \ + 101, /* Existence and alternate IDs: */ #define DT_N_S_clocks_EXISTS 1 @@ -1050,6 +1075,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_clk_hse_FULL_NAME "clk-hse" +#define DT_N_S_clocks_S_clk_hse_FULL_NAME_UNQUOTED clk-hse +#define DT_N_S_clocks_S_clk_hse_FULL_NAME_TOKEN clk_hse +#define DT_N_S_clocks_S_clk_hse_FULL_NAME_UPPER_TOKEN CLK_HSE /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_clk_hse_PARENT DT_N_S_clocks @@ -1080,11 +1108,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_hse_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_clk_hse_SUPPORTS_ORDS \ - 8, /* /clocks/pll@0 */ + 8, /* Existence and alternate IDs: */ #define DT_N_S_clocks_S_clk_hse_EXISTS 1 @@ -1108,12 +1136,44 @@ #define DT_N_S_clocks_S_clk_hse_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_clocks_S_clk_hse_P_clock_frequency 16000000 -#define DT_N_S_clocks_S_clk_hse_P_clock_frequency_EXISTS 1 #define DT_N_S_clocks_S_clk_hse_P_hse_bypass 0 #define DT_N_S_clocks_S_clk_hse_P_hse_bypass_EXISTS 1 #define DT_N_S_clocks_S_clk_hse_P_css_enabled 0 #define DT_N_S_clocks_S_clk_hse_P_css_enabled_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_clock_frequency 16000000 +#define DT_N_S_clocks_S_clk_hse_P_clock_frequency_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_status "okay" +#define DT_N_S_clocks_S_clk_hse_P_status_STRING_UNQUOTED okay +#define DT_N_S_clocks_S_clk_hse_P_status_STRING_TOKEN okay +#define DT_N_S_clocks_S_clk_hse_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0 "okay" +#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_clocks_S_clk_hse_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hse, status, 0) +#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse, status, 0) +#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hse_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hse_P_status_LEN 1 +#define DT_N_S_clocks_S_clk_hse_P_status_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_compatible {"st,stm32-hse-clock"} +#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0 "st,stm32-hse-clock" +#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-hse-clock +#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_TOKEN st_stm32_hse_clock +#define DT_N_S_clocks_S_clk_hse_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_HSE_CLOCK +#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hse, compatible, 0) +#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hse, compatible, 0) +#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hse, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hse_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hse, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hse_P_compatible_LEN 1 +#define DT_N_S_clocks_S_clk_hse_P_compatible_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_zephyr_deferred_init 0 +#define DT_N_S_clocks_S_clk_hse_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_wakeup_source 0 +#define DT_N_S_clocks_S_clk_hse_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_clk_hse_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_clk_hse_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/pll@0 @@ -1132,6 +1192,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_pll_0_FULL_NAME "pll@0" +#define DT_N_S_clocks_S_pll_0_FULL_NAME_UNQUOTED pll@0 +#define DT_N_S_clocks_S_pll_0_FULL_NAME_TOKEN pll_0 +#define DT_N_S_clocks_S_pll_0_FULL_NAME_UPPER_TOKEN PLL_0 /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_pll_0_PARENT DT_N_S_clocks @@ -1162,12 +1225,12 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_pll_0_REQUIRES_ORDS \ - 6, /* /clocks */ \ - 7, /* /clocks/clk-hse */ + 6, \ + 7, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_pll_0_SUPPORTS_ORDS \ - 9, /* /soc/rcc@58024400 */ + 9, /* Existence and alternate IDs: */ #define DT_N_S_clocks_S_pll_0_EXISTS 1 @@ -1177,7 +1240,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_clocks_S_pll_0_REG_NUM 1 #define DT_N_S_clocks_S_pll_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_clocks_S_pll_0_REG_IDX_0_VAL_ADDRESS 0 #define DT_N_S_clocks_S_pll_0_RANGES_NUM 0 #define DT_N_S_clocks_S_pll_0_FOREACH_RANGE(fn) #define DT_N_S_clocks_S_pll_0_IRQ_NUM 0 @@ -1193,20 +1256,32 @@ #define DT_N_S_clocks_S_pll_0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_clocks_S_pll_0_P_wakeup_source 0 -#define DT_N_S_clocks_S_pll_0_P_wakeup_source_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_clocks_S_pll_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_clocks_IDX_0_PH DT_N_S_clocks_S_clk_hse +#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_0, clocks, 0) +#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_0, clocks, 0) +#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_0, clocks, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll_0, clocks, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_pll_0_P_clocks_LEN 1 +#define DT_N_S_clocks_S_pll_0_P_clocks_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_div_m 2 +#define DT_N_S_clocks_S_pll_0_P_div_m_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_mul_n 120 +#define DT_N_S_clocks_S_pll_0_P_mul_n_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_div_p 2 +#define DT_N_S_clocks_S_pll_0_P_div_p_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_div_q 4 +#define DT_N_S_clocks_S_pll_0_P_div_q_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_div_r 2 +#define DT_N_S_clocks_S_pll_0_P_div_r_EXISTS 1 #define DT_N_S_clocks_S_pll_0_P_status "okay" #define DT_N_S_clocks_S_pll_0_P_status_STRING_UNQUOTED okay #define DT_N_S_clocks_S_pll_0_P_status_STRING_TOKEN okay #define DT_N_S_clocks_S_pll_0_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_clocks_S_pll_0_P_status_IDX_0 "okay" #define DT_N_S_clocks_S_pll_0_P_status_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_status_ENUM_IDX 1 -#define DT_N_S_clocks_S_pll_0_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_status_ENUM_TOKEN okay -#define DT_N_S_clocks_S_pll_0_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_clocks_S_pll_0_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_clocks_S_pll_0_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_clocks_S_pll_0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_0, status, 0) #define DT_N_S_clocks_S_pll_0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_0, status, 0) #define DT_N_S_clocks_S_pll_0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_0, status, 0, __VA_ARGS__) @@ -1214,41 +1289,27 @@ #define DT_N_S_clocks_S_pll_0_P_status_LEN 1 #define DT_N_S_clocks_S_pll_0_P_status_EXISTS 1 #define DT_N_S_clocks_S_pll_0_P_compatible {"st,stm32h7-pll-clock"} +#define DT_N_S_clocks_S_pll_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_pll_0_P_compatible_IDX_0 "st,stm32h7-pll-clock" #define DT_N_S_clocks_S_pll_0_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-pll-clock #define DT_N_S_clocks_S_pll_0_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_pll_clock #define DT_N_S_clocks_S_pll_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_PLL_CLOCK -#define DT_N_S_clocks_S_pll_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_pll_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_0, compatible, 0) #define DT_N_S_clocks_S_pll_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_0, compatible, 0) #define DT_N_S_clocks_S_pll_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_0, compatible, 0, __VA_ARGS__) #define DT_N_S_clocks_S_pll_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll_0, compatible, 0, __VA_ARGS__) #define DT_N_S_clocks_S_pll_0_P_compatible_LEN 1 #define DT_N_S_clocks_S_pll_0_P_compatible_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_reg {0 /* 0x0 */} -#define DT_N_S_clocks_S_pll_0_P_reg_IDX_0 0 +#define DT_N_S_clocks_S_pll_0_P_reg {0} #define DT_N_S_clocks_S_pll_0_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_reg_IDX_0 0 #define DT_N_S_clocks_S_pll_0_P_reg_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_clocks_IDX_0_PH DT_N_S_clocks_S_clk_hse -#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_0, clocks, 0) -#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_0, clocks, 0) -#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_0, clocks, 0, __VA_ARGS__) -#define DT_N_S_clocks_S_pll_0_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll_0, clocks, 0, __VA_ARGS__) -#define DT_N_S_clocks_S_pll_0_P_clocks_LEN 1 -#define DT_N_S_clocks_S_pll_0_P_clocks_EXISTS 1 #define DT_N_S_clocks_S_pll_0_P_zephyr_deferred_init 0 #define DT_N_S_clocks_S_pll_0_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_div_m 2 -#define DT_N_S_clocks_S_pll_0_P_div_m_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_mul_n 120 -#define DT_N_S_clocks_S_pll_0_P_mul_n_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_div_p 2 -#define DT_N_S_clocks_S_pll_0_P_div_p_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_div_q 4 -#define DT_N_S_clocks_S_pll_0_P_div_q_EXISTS 1 -#define DT_N_S_clocks_S_pll_0_P_div_r 2 -#define DT_N_S_clocks_S_pll_0_P_div_r_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_wakeup_source 0 +#define DT_N_S_clocks_S_pll_0_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_pll_0_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_pll_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/rcc@58024400 @@ -1267,6 +1328,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_rcc_58024400_FULL_NAME "rcc@58024400" +#define DT_N_S_soc_S_rcc_58024400_FULL_NAME_UNQUOTED rcc@58024400 +#define DT_N_S_soc_S_rcc_58024400_FULL_NAME_TOKEN rcc_58024400 +#define DT_N_S_soc_S_rcc_58024400_FULL_NAME_UPPER_TOKEN RCC_58024400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_rcc_58024400_PARENT DT_N_S_soc @@ -1297,88 +1361,88 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rcc_58024400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 8, /* /clocks/pll@0 */ + 4, \ + 8, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rcc_58024400_SUPPORTS_ORDS \ - 13, /* /soc/adc@58026000 */ \ - 24, /* /soc/i2c@40005400 */ \ - 28, /* /soc/i2c@40005800 */ \ - 30, /* /soc/i2c@40005c00 */ \ - 34, /* /soc/i2c@58001c00 */ \ - 51, /* /soc/adc@40022000 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ \ - 55, /* /soc/serial@40004400 */ \ - 58, /* /soc/serial@40004c00 */ \ - 61, /* /soc/serial@40011000 */ \ - 64, /* /soc/serial@40011400 */ \ - 69, /* /soc/spi@40013000 */ \ - 74, /* /soc/spi@40015000 */ \ - 75, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 76, /* /soc/pin-controller@58020000/gpio@58020400 */ \ - 77, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 78, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ - 79, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 80, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 81, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 82, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 83, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 84, /* /soc/pin-controller@58020000/gpio@58022800 */ \ - 85, /* /soc/timers@40010000 */ \ - 91, /* /soc/usb@40080000 */ \ - 111, /* /soc/adc@40022100 */ \ - 112, /* /soc/adc@40022300 */ \ - 113, /* /soc/bdma@58025400 */ \ - 114, /* /soc/can@4000a000 */ \ - 117, /* /soc/can@4000a400 */ \ - 120, /* /soc/dac@40007400 */ \ - 121, /* /soc/display-controller@50001000 */ \ - 122, /* /soc/dma@40020400 */ \ - 123, /* /soc/dmamux@58025800 */ \ - 124, /* /soc/dsihost@50000000 */ \ - 125, /* /soc/dmamux@40020800 */ \ - 126, /* /soc/i2s@40003800 */ \ - 127, /* /soc/i2s@40003c00 */ \ - 128, /* /soc/i2s@40013000 */ \ - 130, /* /soc/mailbox@58026400 */ \ - 131, /* /soc/memory@38800000 */ \ - 132, /* /soc/rng@48021800 */ \ - 133, /* /soc/sdmmc@48022400 */ \ - 134, /* /soc/sdmmc@52007000 */ \ - 135, /* /soc/serial@40004800 */ \ - 136, /* /soc/serial@40005000 */ \ - 137, /* /soc/serial@40007c00 */ \ - 138, /* /soc/serial@58000c00 */ \ - 139, /* /soc/spi@40003800 */ \ - 140, /* /soc/spi@40003c00 */ \ - 141, /* /soc/spi@40013400 */ \ - 142, /* /soc/spi@58001400 */ \ - 144, /* /soc/timers@40002400 */ \ - 145, /* /soc/usb@40040000 */ \ - 146, /* /soc/watchdog@50003000 */ \ - 162, /* /soc/dma@40020000 */ \ - 175, /* /soc/dcmi@48020000 */ \ - 178, /* /soc/ethernet@40028000 */ \ - 180, /* /soc/flash-controller@52002000 */ \ - 227, /* /soc/memory-controller@52004000 */ \ - 230, /* /soc/pin-controller@58020000/gpio@58021400 */ \ - 237, /* /soc/quadspi@52005000 */ \ - 242, /* /soc/rtc@58004000 */ \ - 248, /* /soc/serial@40007800 */ \ - 251, /* /soc/timers@40000000 */ \ - 254, /* /soc/timers@40000400 */ \ - 257, /* /soc/timers@40000800 */ \ - 260, /* /soc/timers@40000c00 */ \ - 263, /* /soc/timers@40001000 */ \ - 265, /* /soc/timers@40001400 */ \ - 267, /* /soc/timers@40001800 */ \ - 270, /* /soc/timers@40001c00 */ \ - 273, /* /soc/timers@40002000 */ \ - 277, /* /soc/timers@40010400 */ \ - 279, /* /soc/timers@40014000 */ \ - 282, /* /soc/timers@40014400 */ \ - 285, /* /soc/timers@40014800 */ + 13, \ + 24, \ + 28, \ + 30, \ + 34, \ + 51, \ + 54, \ + 55, \ + 58, \ + 61, \ + 64, \ + 69, \ + 74, \ + 75, \ + 76, \ + 77, \ + 78, \ + 79, \ + 80, \ + 81, \ + 82, \ + 83, \ + 84, \ + 85, \ + 91, \ + 114, \ + 115, \ + 116, \ + 117, \ + 120, \ + 123, \ + 124, \ + 125, \ + 126, \ + 127, \ + 128, \ + 129, \ + 130, \ + 131, \ + 133, \ + 134, \ + 135, \ + 136, \ + 137, \ + 138, \ + 139, \ + 140, \ + 141, \ + 142, \ + 143, \ + 144, \ + 145, \ + 147, \ + 148, \ + 149, \ + 165, \ + 178, \ + 181, \ + 183, \ + 230, \ + 233, \ + 240, \ + 245, \ + 251, \ + 254, \ + 257, \ + 260, \ + 263, \ + 266, \ + 268, \ + 270, \ + 273, \ + 276, \ + 280, \ + 282, \ + 285, \ + 288, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_rcc_58024400_EXISTS 1 @@ -1388,8 +1452,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_rcc_58024400_REG_NUM 1 #define DT_N_S_soc_S_rcc_58024400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_REG_IDX_0_VAL_ADDRESS 1476543488 /* 0x58024400 */ -#define DT_N_S_soc_S_rcc_58024400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_rcc_58024400_REG_IDX_0_VAL_ADDRESS 1476543488 +#define DT_N_S_soc_S_rcc_58024400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_rcc_58024400_RANGES_NUM 0 #define DT_N_S_soc_S_rcc_58024400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_rcc_58024400_IRQ_NUM 0 @@ -1405,28 +1469,56 @@ #define DT_N_S_soc_S_rcc_58024400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_rcc_58024400_P_wakeup_source 0 -#define DT_N_S_soc_S_rcc_58024400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_rcc_58024400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_reg {1476543488, 1024} +#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_0 1476543488 +#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_rcc_58024400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_clock_frequency 480000000 +#define DT_N_S_soc_S_rcc_58024400_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1cpre 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_IDX_0_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_hpre 2 +#define DT_N_S_soc_S_rcc_58024400_P_hpre_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_rcc_58024400_P_hpre_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_hpre_IDX_0_ENUM_VAL_2_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_hpre_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1ppre 2 +#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_IDX_0_ENUM_VAL_2_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1 2 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_IDX_0_ENUM_VAL_2_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2 2 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_IDX_0_ENUM_VAL_2_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d3ppre 2 +#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_IDX_0_ENUM_VAL_2_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_compatible {"st,stm32h7-rcc"} +#define DT_N_S_soc_S_rcc_58024400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_compatible_IDX_0 "st,stm32h7-rcc" #define DT_N_S_soc_S_rcc_58024400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-rcc #define DT_N_S_soc_S_rcc_58024400_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_rcc #define DT_N_S_soc_S_rcc_58024400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_RCC -#define DT_N_S_soc_S_rcc_58024400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_58024400, compatible, 0) #define DT_N_S_soc_S_rcc_58024400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_58024400, compatible, 0) #define DT_N_S_soc_S_rcc_58024400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_58024400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_rcc_58024400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rcc_58024400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_rcc_58024400_P_compatible_LEN 1 #define DT_N_S_soc_S_rcc_58024400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_reg {1476543488 /* 0x58024400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_0 1476543488 -#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_rcc_58024400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_reg_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_clocks_IDX_0_PH DT_N_S_clocks_S_pll_0 #define DT_N_S_soc_S_rcc_58024400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_58024400, clocks, 0) @@ -1437,32 +1529,10 @@ #define DT_N_S_soc_S_rcc_58024400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_rcc_58024400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_clock_frequency 480000000 -#define DT_N_S_soc_S_rcc_58024400_P_clock_frequency_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d1cpre 1 -#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_ENUM_IDX 0 -#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_ENUM_VAL_1_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d1cpre_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_hpre 2 -#define DT_N_S_soc_S_rcc_58024400_P_hpre_ENUM_IDX 1 -#define DT_N_S_soc_S_rcc_58024400_P_hpre_ENUM_VAL_2_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_hpre_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d1ppre 2 -#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_ENUM_IDX 1 -#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_ENUM_VAL_2_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d1ppre_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1 2 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_ENUM_IDX 1 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_ENUM_VAL_2_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre1_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2 2 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_ENUM_IDX 1 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_ENUM_VAL_2_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d2ppre2_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d3ppre 2 -#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_ENUM_IDX 1 -#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_ENUM_VAL_2_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_P_d3ppre_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_wakeup_source 0 +#define DT_N_S_soc_S_rcc_58024400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_rcc_58024400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000 @@ -1481,6 +1551,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_FULL_NAME "pin-controller@58020000" +#define DT_N_S_soc_S_pin_controller_58020000_FULL_NAME_UNQUOTED pin-controller@58020000 +#define DT_N_S_soc_S_pin_controller_58020000_FULL_NAME_TOKEN pin_controller_58020000 +#define DT_N_S_soc_S_pin_controller_58020000_FULL_NAME_UPPER_TOKEN PIN_CONTROLLER_58020000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_PARENT DT_N_S_soc @@ -1511,124 +1584,124 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_REQUIRES_ORDS \ - 4, /* /soc */ + 4, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_SUPPORTS_ORDS \ - 11, /* /soc/pin-controller@58020000/adc3_inp0_pc2_c */ \ - 12, /* /soc/pin-controller@58020000/adc3_inp1_pc3_c */ \ - 22, /* /soc/pin-controller@58020000/i2c1_scl_pb8 */ \ - 23, /* /soc/pin-controller@58020000/i2c1_sda_pb9 */ \ - 26, /* /soc/pin-controller@58020000/i2c2_scl_ph4 */ \ - 27, /* /soc/pin-controller@58020000/i2c2_sda_pb11 */ \ - 32, /* /soc/pin-controller@58020000/i2c4_scl_pb6 */ \ - 33, /* /soc/pin-controller@58020000/i2c4_sda_ph12 */ \ - 39, /* /soc/pin-controller@58020000/adc1_inp0_pa0_c */ \ - 40, /* /soc/pin-controller@58020000/adc1_inp10_pc0 */ \ - 41, /* /soc/pin-controller@58020000/adc1_inp12_pc2 */ \ - 42, /* /soc/pin-controller@58020000/adc1_inp13_pc3 */ \ - 43, /* /soc/pin-controller@58020000/adc1_inp16_pa0 */ \ - 44, /* /soc/pin-controller@58020000/adc1_inp18_pa4 */ \ - 45, /* /soc/pin-controller@58020000/adc1_inp19_pa5 */ \ - 46, /* /soc/pin-controller@58020000/adc1_inp1_pa1_c */ \ - 47, /* /soc/pin-controller@58020000/adc1_inp4_pc4 */ \ - 48, /* /soc/pin-controller@58020000/adc1_inp5_pb1 */ \ - 49, /* /soc/pin-controller@58020000/adc1_inp8_pc5 */ \ - 50, /* /soc/pin-controller@58020000/adc1_inp9_pb0 */ \ - 52, /* /soc/pin-controller@58020000/usart2_rx_pd6 */ \ - 53, /* /soc/pin-controller@58020000/usart2_tx_pd5 */ \ - 56, /* /soc/pin-controller@58020000/uart4_rx_pi9 */ \ - 57, /* /soc/pin-controller@58020000/uart4_tx_ph13 */ \ - 59, /* /soc/pin-controller@58020000/usart1_rx_pb7 */ \ - 60, /* /soc/pin-controller@58020000/usart1_tx_pa9 */ \ - 62, /* /soc/pin-controller@58020000/usart6_rx_pc7 */ \ - 63, /* /soc/pin-controller@58020000/usart6_tx_pg14 */ \ - 65, /* /soc/pin-controller@58020000/spi1_miso_pg9 */ \ - 66, /* /soc/pin-controller@58020000/spi1_mosi_pd7 */ \ - 67, /* /soc/pin-controller@58020000/spi1_nss_pa4 */ \ - 68, /* /soc/pin-controller@58020000/spi1_sck_pb3 */ \ - 70, /* /soc/pin-controller@58020000/spi5_miso_pj11 */ \ - 71, /* /soc/pin-controller@58020000/spi5_mosi_pj10 */ \ - 72, /* /soc/pin-controller@58020000/spi5_nss_pk1 */ \ - 73, /* /soc/pin-controller@58020000/spi5_sck_ph6 */ \ - 75, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 76, /* /soc/pin-controller@58020000/gpio@58020400 */ \ - 77, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 78, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ - 79, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 80, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 81, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 82, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 83, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 84, /* /soc/pin-controller@58020000/gpio@58022800 */ \ - 86, /* /soc/pin-controller@58020000/tim1_ch3_pj9 */ \ - 89, /* /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 */ \ - 90, /* /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 */ \ - 115, /* /soc/pin-controller@58020000/fdcan2_rx_pb5 */ \ - 116, /* /soc/pin-controller@58020000/fdcan2_tx_pb13 */ \ - 118, /* /soc/pin-controller@58020000/dac1_out1_pa4 */ \ - 119, /* /soc/pin-controller@58020000/dac1_out2_pa5 */ \ - 164, /* /soc/pin-controller@58020000/dcmi_d0_ph9 */ \ - 165, /* /soc/pin-controller@58020000/dcmi_d1_ph10 */ \ - 166, /* /soc/pin-controller@58020000/dcmi_d2_ph11 */ \ - 167, /* /soc/pin-controller@58020000/dcmi_d3_pg11 */ \ - 168, /* /soc/pin-controller@58020000/dcmi_d4_ph14 */ \ - 169, /* /soc/pin-controller@58020000/dcmi_d5_pi4 */ \ - 170, /* /soc/pin-controller@58020000/dcmi_d6_pi6 */ \ - 171, /* /soc/pin-controller@58020000/dcmi_d7_pi7 */ \ - 172, /* /soc/pin-controller@58020000/dcmi_hsync_ph8 */ \ - 173, /* /soc/pin-controller@58020000/dcmi_pixclk_pa6 */ \ - 174, /* /soc/pin-controller@58020000/dcmi_vsync_pi5 */ \ - 188, /* /soc/pin-controller@58020000/fmc_a0_pf0 */ \ - 189, /* /soc/pin-controller@58020000/fmc_a10_pg0 */ \ - 190, /* /soc/pin-controller@58020000/fmc_a11_pg1 */ \ - 191, /* /soc/pin-controller@58020000/fmc_a12_pg2 */ \ - 192, /* /soc/pin-controller@58020000/fmc_a14_pg4 */ \ - 193, /* /soc/pin-controller@58020000/fmc_a15_pg5 */ \ - 194, /* /soc/pin-controller@58020000/fmc_a1_pf1 */ \ - 195, /* /soc/pin-controller@58020000/fmc_a2_pf2 */ \ - 196, /* /soc/pin-controller@58020000/fmc_a3_pf3 */ \ - 197, /* /soc/pin-controller@58020000/fmc_a4_pf4 */ \ - 198, /* /soc/pin-controller@58020000/fmc_a5_pf5 */ \ - 199, /* /soc/pin-controller@58020000/fmc_a6_pf12 */ \ - 200, /* /soc/pin-controller@58020000/fmc_a7_pf13 */ \ - 201, /* /soc/pin-controller@58020000/fmc_a8_pf14 */ \ - 202, /* /soc/pin-controller@58020000/fmc_a9_pf15 */ \ - 203, /* /soc/pin-controller@58020000/fmc_d0_pd14 */ \ - 204, /* /soc/pin-controller@58020000/fmc_d10_pe13 */ \ - 205, /* /soc/pin-controller@58020000/fmc_d11_pe14 */ \ - 206, /* /soc/pin-controller@58020000/fmc_d12_pe15 */ \ - 207, /* /soc/pin-controller@58020000/fmc_d13_pd8 */ \ - 208, /* /soc/pin-controller@58020000/fmc_d14_pd9 */ \ - 209, /* /soc/pin-controller@58020000/fmc_d15_pd10 */ \ - 210, /* /soc/pin-controller@58020000/fmc_d1_pd15 */ \ - 211, /* /soc/pin-controller@58020000/fmc_d2_pd0 */ \ - 212, /* /soc/pin-controller@58020000/fmc_d3_pd1 */ \ - 213, /* /soc/pin-controller@58020000/fmc_d4_pe7 */ \ - 214, /* /soc/pin-controller@58020000/fmc_d5_pe8 */ \ - 215, /* /soc/pin-controller@58020000/fmc_d6_pe9 */ \ - 216, /* /soc/pin-controller@58020000/fmc_d7_pe10 */ \ - 217, /* /soc/pin-controller@58020000/fmc_d8_pe11 */ \ - 218, /* /soc/pin-controller@58020000/fmc_d9_pe12 */ \ - 219, /* /soc/pin-controller@58020000/fmc_nbl0_pe0 */ \ - 220, /* /soc/pin-controller@58020000/fmc_nbl1_pe1 */ \ - 221, /* /soc/pin-controller@58020000/fmc_sdcke0_ph2 */ \ - 222, /* /soc/pin-controller@58020000/fmc_sdclk_pg8 */ \ - 223, /* /soc/pin-controller@58020000/fmc_sdncas_pg15 */ \ - 224, /* /soc/pin-controller@58020000/fmc_sdne0_ph3 */ \ - 225, /* /soc/pin-controller@58020000/fmc_sdnras_pf11 */ \ - 226, /* /soc/pin-controller@58020000/fmc_sdnwe_ph5 */ \ - 230, /* /soc/pin-controller@58020000/gpio@58021400 */ \ - 231, /* /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 */ \ - 232, /* /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 */ \ - 233, /* /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 */ \ - 234, /* /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 */ \ - 235, /* /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 */ \ - 236, /* /soc/pin-controller@58020000/quadspi_clk_pf10 */ \ - 244, /* /soc/pin-controller@58020000/uart7_cts_pf9 */ \ - 245, /* /soc/pin-controller@58020000/uart7_rts_pf8 */ \ - 246, /* /soc/pin-controller@58020000/uart7_rx_pa8 */ \ - 247, /* /soc/pin-controller@58020000/uart7_tx_pf7 */ + 11, \ + 12, \ + 22, \ + 23, \ + 26, \ + 27, \ + 32, \ + 33, \ + 39, \ + 40, \ + 41, \ + 42, \ + 43, \ + 44, \ + 45, \ + 46, \ + 47, \ + 48, \ + 49, \ + 50, \ + 52, \ + 53, \ + 56, \ + 57, \ + 59, \ + 60, \ + 62, \ + 63, \ + 65, \ + 66, \ + 67, \ + 68, \ + 70, \ + 71, \ + 72, \ + 73, \ + 75, \ + 76, \ + 77, \ + 78, \ + 79, \ + 80, \ + 81, \ + 82, \ + 83, \ + 84, \ + 86, \ + 89, \ + 90, \ + 118, \ + 119, \ + 121, \ + 122, \ + 167, \ + 168, \ + 169, \ + 170, \ + 171, \ + 172, \ + 173, \ + 174, \ + 175, \ + 176, \ + 177, \ + 191, \ + 192, \ + 193, \ + 194, \ + 195, \ + 196, \ + 197, \ + 198, \ + 199, \ + 200, \ + 201, \ + 202, \ + 203, \ + 204, \ + 205, \ + 206, \ + 207, \ + 208, \ + 209, \ + 210, \ + 211, \ + 212, \ + 213, \ + 214, \ + 215, \ + 216, \ + 217, \ + 218, \ + 219, \ + 220, \ + 221, \ + 222, \ + 223, \ + 224, \ + 225, \ + 226, \ + 227, \ + 228, \ + 229, \ + 233, \ + 234, \ + 235, \ + 236, \ + 237, \ + 238, \ + 239, \ + 247, \ + 248, \ + 249, \ + 250, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_EXISTS 1 @@ -1638,8 +1711,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_ADDRESS 1476526080 /* 0x58020000 */ -#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_SIZE 9216 /* 0x2400 */ +#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_ADDRESS 1476526080 +#define DT_N_S_soc_S_pin_controller_58020000_REG_IDX_0_VAL_SIZE 9216 #define DT_N_S_soc_S_pin_controller_58020000_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_IRQ_NUM 0 @@ -1655,36 +1728,36 @@ #define DT_N_S_soc_S_pin_controller_58020000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg {1476526080, 9216} +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0 1476526080 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1 9216 +#define DT_N_S_soc_S_pin_controller_58020000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_P_compatible {"st,stm32-pinctrl"} +#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0 "st,stm32-pinctrl" #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pinctrl #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_pinctrl #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PINCTRL -#define DT_N_S_soc_S_pin_controller_58020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0) #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0) #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg {1476526080 /* 0x58020000 */, 9216 /* 0x2400 */} -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0 1476526080 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1 9216 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa12_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12 0 -#define DT_N_S_soc_S_pin_controller_58020000_P_remap_pa11_pa12_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc3_inp0_pc2_c @@ -1700,6 +1773,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FULL_NAME "adc3_inp0_pc2_c" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FULL_NAME_UNQUOTED adc3_inp0_pc2_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FULL_NAME_TOKEN adc3_inp0_pc2_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_FULL_NAME_UPPER_TOKEN ADC3_INP0_PC2_C /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -1730,11 +1806,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_SUPPORTS_ORDS \ - 13, /* /soc/adc@58026000 */ + 13, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_EXISTS 1 @@ -1752,20 +1828,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_pinmux 1104 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate "low-speed" @@ -1774,16 +1836,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc3_inp1_pc3_c @@ -1799,6 +1873,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FULL_NAME "adc3_inp1_pc3_c" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FULL_NAME_UNQUOTED adc3_inp1_pc3_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FULL_NAME_TOKEN adc3_inp1_pc3_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_FULL_NAME_UPPER_TOKEN ADC3_INP1_PC3_C /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -1829,11 +1906,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_SUPPORTS_ORDS \ - 13, /* /soc/adc@58026000 */ + 13, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_EXISTS 1 @@ -1851,20 +1928,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_pinmux 1136 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate "low-speed" @@ -1873,16 +1936,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c_P_output_high_EXISTS 1 /* * Devicetree node: /soc/adc@58026000 @@ -1901,6 +1976,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_58026000_FULL_NAME "adc@58026000" +#define DT_N_S_soc_S_adc_58026000_FULL_NAME_UNQUOTED adc@58026000 +#define DT_N_S_soc_S_adc_58026000_FULL_NAME_TOKEN adc_58026000 +#define DT_N_S_soc_S_adc_58026000_FULL_NAME_UPPER_TOKEN ADC_58026000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_adc_58026000_PARENT DT_N_S_soc @@ -1931,20 +2009,20 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_58026000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 11, /* /soc/pin-controller@58020000/adc3_inp0_pc2_c */ \ - 12, /* /soc/pin-controller@58020000/adc3_inp1_pc3_c */ + 4, \ + 5, \ + 9, \ + 11, \ + 12, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_58026000_SUPPORTS_ORDS \ - 14, /* /dietemp */ \ - 36, /* /vbat */ \ - 37, /* /vref */ \ - 93, /* /zephyr,user */ \ - 160, /* /soc/adc@58026000/channel@0 */ \ - 161, /* /soc/adc@58026000/channel@1 */ + 14, \ + 36, \ + 37, \ + 93, \ + 163, \ + 164, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_adc_58026000_EXISTS 1 @@ -1954,8 +2032,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_58026000_REG_NUM 1 #define DT_N_S_soc_S_adc_58026000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_REG_IDX_0_VAL_ADDRESS 1476550656 /* 0x58026000 */ -#define DT_N_S_soc_S_adc_58026000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_adc_58026000_REG_IDX_0_VAL_ADDRESS 1476550656 +#define DT_N_S_soc_S_adc_58026000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_adc_58026000_RANGES_NUM 0 #define DT_N_S_soc_S_adc_58026000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_58026000_IRQ_NUM 1 @@ -1985,50 +2063,12 @@ #define DT_N_S_soc_S_adc_58026000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c /* Generic property macros: */ -#define DT_N_S_soc_S_adc_58026000_P_wakeup_source 0 -#define DT_N_S_soc_S_adc_58026000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_adc_58026000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_status "okay" -#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_adc_58026000_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_adc_58026000_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, status, 0) -#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, status, 0) -#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_status_LEN 1 -#define DT_N_S_soc_S_adc_58026000_P_status_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_compatible {"st,stm32-adc"} -#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0 "st,stm32-adc" -#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc -#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc -#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC -#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, compatible, 0) -#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, compatible, 0) -#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_compatible_LEN 1 -#define DT_N_S_soc_S_adc_58026000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_reg {1476550656 /* 0x58026000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_adc_58026000_P_reg_IDX_0 1476550656 +#define DT_N_S_soc_S_adc_58026000_P_reg {1476550656, 1024} #define DT_N_S_soc_S_adc_58026000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_adc_58026000_P_reg_IDX_0 1476550656 #define DT_N_S_soc_S_adc_58026000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_adc_58026000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_interrupts {127 /* 0x7f */, 0 /* 0x0 */} -#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_0 127 -#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_adc_58026000_P_clocks_IDX_0_VAL_bus 224 @@ -2041,57 +2081,35 @@ #define DT_N_S_soc_S_adc_58026000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_58026000_P_clocks_LEN 1 #define DT_N_S_soc_S_adc_58026000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_adc_58026000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_LEN 2 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_interrupts {127, 0} +#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_0 127 +#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_adc_58026000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source 1 -#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_ENUM_IDX 0 -#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_IDX_0_ENUM_VAL_1_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_st_adc_clock_source_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler 4 -#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_ENUM_IDX 2 -#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_ENUM_VAL_4_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_IDX_0_ENUM_VAL_4_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_st_adc_prescaler_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_vref_mv 3300 #define DT_N_S_soc_S_adc_58026000_P_vref_mv_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_resolutions {8446476 /* 0x80e20c */, 7725580 /* 0x75e20c */, 6742540 /* 0x66e20c */, 5497356 /* 0x53e20c */, 4710924 /* 0x47e20c */} -#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_0 8446476 +#define DT_N_S_soc_S_adc_58026000_P_resolutions {8446476, 7725580, 6742540, 5497356, 4710924} #define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_1 7725580 +#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_0 8446476 #define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_2 6742540 +#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_1 7725580 #define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_3 5497356 +#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_2 6742540 #define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_4 4710924 +#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_3 5497356 #define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_resolutions_IDX_4 4710924 #define DT_N_S_soc_S_adc_58026000_P_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, resolutions, 0) \ fn(DT_N_S_soc_S_adc_58026000, resolutions, 1) \ fn(DT_N_S_soc_S_adc_58026000, resolutions, 2) \ @@ -2114,23 +2132,23 @@ fn(DT_N_S_soc_S_adc_58026000, resolutions, 4, __VA_ARGS__) #define DT_N_S_soc_S_adc_58026000_P_resolutions_LEN 5 #define DT_N_S_soc_S_adc_58026000_P_resolutions_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times {2 /* 0x2 */, 3 /* 0x3 */, 9 /* 0x9 */, 17 /* 0x11 */, 33 /* 0x21 */, 65 /* 0x41 */, 388 /* 0x184 */, 811 /* 0x32b */} -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_0 2 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times {2, 3, 9, 17, 33, 65, 388, 811} #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_1 3 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_0 2 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_2 9 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_1 3 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_3 17 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_2 9 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_4 33 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_3 17 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_5 65 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_4 33 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_6 388 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_5 65 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_7 811 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_6 388 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_sampling_times_IDX_7 811 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, sampling_times, 0) \ fn(DT_N_S_soc_S_adc_58026000, sampling_times, 1) \ fn(DT_N_S_soc_S_adc_58026000, sampling_times, 2) \ @@ -2166,9 +2184,70 @@ #define DT_N_S_soc_S_adc_58026000_P_sampling_times_LEN 8 #define DT_N_S_soc_S_adc_58026000_P_sampling_times_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer 1 -#define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer_ENUM_IDX 1 -#define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer_IDX_0_ENUM_VAL_1_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_P_st_adc_sequencer_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_status "okay" +#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_adc_58026000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_adc_58026000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_58026000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, status, 0) +#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, status, 0) +#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_status_LEN 1 +#define DT_N_S_soc_S_adc_58026000_P_status_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_compatible {"st,stm32-adc"} +#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0 "st,stm32-adc" +#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc +#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc +#define DT_N_S_soc_S_adc_58026000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC +#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, compatible, 0) +#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, compatible, 0) +#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_compatible_LEN 1 +#define DT_N_S_soc_S_adc_58026000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_adc_58026000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_wakeup_source 0 +#define DT_N_S_soc_S_adc_58026000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_adc_58026000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_58026000, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_LEN 2 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_58026000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_adc_58026000_P_pinctrl_names_EXISTS 1 /* * Devicetree node: /dietemp @@ -2187,12 +2266,15 @@ /* Node's name with unit-address: */ #define DT_N_S_dietemp_FULL_NAME "dietemp" +#define DT_N_S_dietemp_FULL_NAME_UNQUOTED dietemp +#define DT_N_S_dietemp_FULL_NAME_TOKEN dietemp +#define DT_N_S_dietemp_FULL_NAME_UPPER_TOKEN DIETEMP /* Node parent (/) identifier: */ #define DT_N_S_dietemp_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_dietemp_CHILD_IDX 6 +#define DT_N_S_dietemp_CHILD_IDX 7 /* Helpers for dealing with node labels: */ #define DT_N_S_dietemp_NODELABEL_NUM 1 @@ -2217,8 +2299,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_dietemp_REQUIRES_ORDS \ - 0, /* / */ \ - 13, /* /soc/adc@58026000 */ + 0, \ + 13, /* Ordinals for what depends directly on this node: */ #define DT_N_S_dietemp_SUPPORTS_ORDS /* nothing */ @@ -2245,20 +2327,29 @@ #define DT_N_S_dietemp_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_dietemp_P_wakeup_source 0 -#define DT_N_S_dietemp_P_wakeup_source_EXISTS 1 -#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal2_addr 535947328 +#define DT_N_S_dietemp_P_ts_cal2_addr_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal2_temp 110 +#define DT_N_S_dietemp_P_ts_cal2_temp_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal1_addr 535947296 +#define DT_N_S_dietemp_P_ts_cal1_addr_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal1_temp 30 +#define DT_N_S_dietemp_P_ts_cal1_temp_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal_vrefanalog 3300 +#define DT_N_S_dietemp_P_ts_cal_vrefanalog_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal_resolution 16 +#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_ENUM_IDX 2 +#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal_resolution_IDX_0_ENUM_VAL_16_EXISTS 1 +#define DT_N_S_dietemp_P_ts_cal_resolution_EXISTS 1 #define DT_N_S_dietemp_P_status "disabled" #define DT_N_S_dietemp_P_status_STRING_UNQUOTED disabled #define DT_N_S_dietemp_P_status_STRING_TOKEN disabled #define DT_N_S_dietemp_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_dietemp_P_status_IDX_0 "disabled" #define DT_N_S_dietemp_P_status_IDX_0_EXISTS 1 -#define DT_N_S_dietemp_P_status_ENUM_IDX 2 -#define DT_N_S_dietemp_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_dietemp_P_status_ENUM_TOKEN disabled -#define DT_N_S_dietemp_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_dietemp_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_dietemp_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, status, 0) #define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, status, 0) #define DT_N_S_dietemp_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, status, 0, __VA_ARGS__) @@ -2266,11 +2357,11 @@ #define DT_N_S_dietemp_P_status_LEN 1 #define DT_N_S_dietemp_P_status_EXISTS 1 #define DT_N_S_dietemp_P_compatible {"st,stm32-temp-cal"} +#define DT_N_S_dietemp_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_dietemp_P_compatible_IDX_0 "st,stm32-temp-cal" #define DT_N_S_dietemp_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-temp-cal #define DT_N_S_dietemp_P_compatible_IDX_0_STRING_TOKEN st_stm32_temp_cal #define DT_N_S_dietemp_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TEMP_CAL -#define DT_N_S_dietemp_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_dietemp, compatible, 0) #define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_dietemp, compatible, 0) #define DT_N_S_dietemp_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_dietemp, compatible, 0, __VA_ARGS__) @@ -2289,20 +2380,10 @@ #define DT_N_S_dietemp_P_io_channels_EXISTS 1 #define DT_N_S_dietemp_P_zephyr_deferred_init 0 #define DT_N_S_dietemp_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal1_addr 535947296 -#define DT_N_S_dietemp_P_ts_cal1_addr_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal1_temp 30 -#define DT_N_S_dietemp_P_ts_cal1_temp_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal_vrefanalog 3300 -#define DT_N_S_dietemp_P_ts_cal_vrefanalog_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal_resolution 16 -#define DT_N_S_dietemp_P_ts_cal_resolution_ENUM_IDX 2 -#define DT_N_S_dietemp_P_ts_cal_resolution_ENUM_VAL_16_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal_resolution_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal2_addr 535947328 -#define DT_N_S_dietemp_P_ts_cal2_addr_EXISTS 1 -#define DT_N_S_dietemp_P_ts_cal2_temp 110 -#define DT_N_S_dietemp_P_ts_cal2_temp_EXISTS 1 +#define DT_N_S_dietemp_P_wakeup_source 0 +#define DT_N_S_dietemp_P_wakeup_source_EXISTS 1 +#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_dietemp_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /memory@24000000 @@ -2321,12 +2402,15 @@ /* Node's name with unit-address: */ #define DT_N_S_memory_24000000_FULL_NAME "memory@24000000" +#define DT_N_S_memory_24000000_FULL_NAME_UNQUOTED memory@24000000 +#define DT_N_S_memory_24000000_FULL_NAME_TOKEN memory_24000000 +#define DT_N_S_memory_24000000_FULL_NAME_UPPER_TOKEN MEMORY_24000000 /* Node parent (/) identifier: */ #define DT_N_S_memory_24000000_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_memory_24000000_CHILD_IDX 13 +#define DT_N_S_memory_24000000_CHILD_IDX 14 /* Helpers for dealing with node labels: */ #define DT_N_S_memory_24000000_NODELABEL_NUM 1 @@ -2351,7 +2435,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_24000000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_memory_24000000_SUPPORTS_ORDS /* nothing */ @@ -2364,8 +2448,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_memory_24000000_REG_NUM 1 #define DT_N_S_memory_24000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_memory_24000000_REG_IDX_0_VAL_ADDRESS 603979776 /* 0x24000000 */ -#define DT_N_S_memory_24000000_REG_IDX_0_VAL_SIZE 524288 /* 0x80000 */ +#define DT_N_S_memory_24000000_REG_IDX_0_VAL_ADDRESS 603979776 +#define DT_N_S_memory_24000000_REG_IDX_0_VAL_SIZE 524288 #define DT_N_S_memory_24000000_RANGES_NUM 0 #define DT_N_S_memory_24000000_FOREACH_RANGE(fn) #define DT_N_S_memory_24000000_IRQ_NUM 0 @@ -2377,30 +2461,30 @@ #define DT_N_S_memory_24000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_memory_24000000_P_wakeup_source 0 -#define DT_N_S_memory_24000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_memory_24000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_memory_24000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_memory_24000000_P_reg {603979776, 524288} +#define DT_N_S_memory_24000000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_memory_24000000_P_reg_IDX_0 603979776 +#define DT_N_S_memory_24000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_memory_24000000_P_reg_IDX_1 524288 +#define DT_N_S_memory_24000000_P_reg_EXISTS 1 #define DT_N_S_memory_24000000_P_compatible {"mmio-sram"} +#define DT_N_S_memory_24000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_24000000_P_compatible_IDX_0 "mmio-sram" #define DT_N_S_memory_24000000_P_compatible_IDX_0_STRING_UNQUOTED mmio-sram #define DT_N_S_memory_24000000_P_compatible_IDX_0_STRING_TOKEN mmio_sram #define DT_N_S_memory_24000000_P_compatible_IDX_0_STRING_UPPER_TOKEN MMIO_SRAM -#define DT_N_S_memory_24000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_24000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_24000000, compatible, 0) #define DT_N_S_memory_24000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_24000000, compatible, 0) #define DT_N_S_memory_24000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_24000000, compatible, 0, __VA_ARGS__) #define DT_N_S_memory_24000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_24000000, compatible, 0, __VA_ARGS__) #define DT_N_S_memory_24000000_P_compatible_LEN 1 #define DT_N_S_memory_24000000_P_compatible_EXISTS 1 -#define DT_N_S_memory_24000000_P_reg {603979776 /* 0x24000000 */, 524288 /* 0x80000 */} -#define DT_N_S_memory_24000000_P_reg_IDX_0 603979776 -#define DT_N_S_memory_24000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_memory_24000000_P_reg_IDX_1 524288 -#define DT_N_S_memory_24000000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_memory_24000000_P_reg_EXISTS 1 #define DT_N_S_memory_24000000_P_zephyr_deferred_init 0 #define DT_N_S_memory_24000000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_memory_24000000_P_wakeup_source 0 +#define DT_N_S_memory_24000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_memory_24000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_memory_24000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /memory@30000000 @@ -2419,12 +2503,15 @@ /* Node's name with unit-address: */ #define DT_N_S_memory_30000000_FULL_NAME "memory@30000000" +#define DT_N_S_memory_30000000_FULL_NAME_UNQUOTED memory@30000000 +#define DT_N_S_memory_30000000_FULL_NAME_TOKEN memory_30000000 +#define DT_N_S_memory_30000000_FULL_NAME_UPPER_TOKEN MEMORY_30000000 /* Node parent (/) identifier: */ #define DT_N_S_memory_30000000_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_memory_30000000_CHILD_IDX 14 +#define DT_N_S_memory_30000000_CHILD_IDX 15 /* Helpers for dealing with node labels: */ #define DT_N_S_memory_30000000_NODELABEL_NUM 1 @@ -2449,7 +2536,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_30000000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_memory_30000000_SUPPORTS_ORDS /* nothing */ @@ -2463,8 +2550,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_memory_30000000_REG_NUM 1 #define DT_N_S_memory_30000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_memory_30000000_REG_IDX_0_VAL_ADDRESS 805306368 /* 0x30000000 */ -#define DT_N_S_memory_30000000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */ +#define DT_N_S_memory_30000000_REG_IDX_0_VAL_ADDRESS 805306368 +#define DT_N_S_memory_30000000_REG_IDX_0_VAL_SIZE 131072 #define DT_N_S_memory_30000000_RANGES_NUM 0 #define DT_N_S_memory_30000000_FOREACH_RANGE(fn) #define DT_N_S_memory_30000000_IRQ_NUM 0 @@ -2481,21 +2568,29 @@ #define DT_N_S_memory_30000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_memory_30000000_P_wakeup_source 0 -#define DT_N_S_memory_30000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_memory_30000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_memory_30000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_memory_30000000_P_zephyr_memory_region "SRAM1" +#define DT_N_S_memory_30000000_P_zephyr_memory_region_STRING_UNQUOTED SRAM1 +#define DT_N_S_memory_30000000_P_zephyr_memory_region_STRING_TOKEN SRAM1 +#define DT_N_S_memory_30000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM1 +#define DT_N_S_memory_30000000_P_zephyr_memory_region_IDX_0 "SRAM1" +#define DT_N_S_memory_30000000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0) +#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0) +#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_30000000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_memory_30000000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_memory_30000000_P_compatible {"zephyr,memory-region", "mmio-sram"} +#define DT_N_S_memory_30000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_30000000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_memory_30000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_memory_30000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_memory_30000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_memory_30000000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_memory_30000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_30000000_P_compatible_IDX_1 "mmio-sram" #define DT_N_S_memory_30000000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram #define DT_N_S_memory_30000000_P_compatible_IDX_1_STRING_TOKEN mmio_sram #define DT_N_S_memory_30000000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM -#define DT_N_S_memory_30000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_30000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30000000, compatible, 0) \ fn(DT_N_S_memory_30000000, compatible, 1) #define DT_N_S_memory_30000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -2506,26 +2601,18 @@ fn(DT_N_S_memory_30000000, compatible, 1, __VA_ARGS__) #define DT_N_S_memory_30000000_P_compatible_LEN 2 #define DT_N_S_memory_30000000_P_compatible_EXISTS 1 -#define DT_N_S_memory_30000000_P_reg {805306368 /* 0x30000000 */, 131072 /* 0x20000 */} -#define DT_N_S_memory_30000000_P_reg_IDX_0 805306368 +#define DT_N_S_memory_30000000_P_reg {805306368, 131072} #define DT_N_S_memory_30000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_memory_30000000_P_reg_IDX_1 131072 +#define DT_N_S_memory_30000000_P_reg_IDX_0 805306368 #define DT_N_S_memory_30000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_memory_30000000_P_reg_IDX_1 131072 #define DT_N_S_memory_30000000_P_reg_EXISTS 1 #define DT_N_S_memory_30000000_P_zephyr_deferred_init 0 #define DT_N_S_memory_30000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_memory_30000000_P_zephyr_memory_region "SRAM1" -#define DT_N_S_memory_30000000_P_zephyr_memory_region_STRING_UNQUOTED SRAM1 -#define DT_N_S_memory_30000000_P_zephyr_memory_region_STRING_TOKEN SRAM1 -#define DT_N_S_memory_30000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM1 -#define DT_N_S_memory_30000000_P_zephyr_memory_region_IDX_0 "SRAM1" -#define DT_N_S_memory_30000000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0) -#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0) -#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_30000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_30000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_30000000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_memory_30000000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_memory_30000000_P_wakeup_source 0 +#define DT_N_S_memory_30000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_memory_30000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_memory_30000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /memory@30020000 @@ -2544,12 +2631,15 @@ /* Node's name with unit-address: */ #define DT_N_S_memory_30020000_FULL_NAME "memory@30020000" +#define DT_N_S_memory_30020000_FULL_NAME_UNQUOTED memory@30020000 +#define DT_N_S_memory_30020000_FULL_NAME_TOKEN memory_30020000 +#define DT_N_S_memory_30020000_FULL_NAME_UPPER_TOKEN MEMORY_30020000 /* Node parent (/) identifier: */ #define DT_N_S_memory_30020000_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_memory_30020000_CHILD_IDX 15 +#define DT_N_S_memory_30020000_CHILD_IDX 16 /* Helpers for dealing with node labels: */ #define DT_N_S_memory_30020000_NODELABEL_NUM 1 @@ -2574,7 +2664,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_30020000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_memory_30020000_SUPPORTS_ORDS /* nothing */ @@ -2588,8 +2678,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_memory_30020000_REG_NUM 1 #define DT_N_S_memory_30020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_memory_30020000_REG_IDX_0_VAL_ADDRESS 805437440 /* 0x30020000 */ -#define DT_N_S_memory_30020000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */ +#define DT_N_S_memory_30020000_REG_IDX_0_VAL_ADDRESS 805437440 +#define DT_N_S_memory_30020000_REG_IDX_0_VAL_SIZE 131072 #define DT_N_S_memory_30020000_RANGES_NUM 0 #define DT_N_S_memory_30020000_FOREACH_RANGE(fn) #define DT_N_S_memory_30020000_IRQ_NUM 0 @@ -2606,21 +2696,29 @@ #define DT_N_S_memory_30020000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_memory_30020000_P_wakeup_source 0 -#define DT_N_S_memory_30020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_memory_30020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_memory_30020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_memory_30020000_P_zephyr_memory_region "SRAM2" +#define DT_N_S_memory_30020000_P_zephyr_memory_region_STRING_UNQUOTED SRAM2 +#define DT_N_S_memory_30020000_P_zephyr_memory_region_STRING_TOKEN SRAM2 +#define DT_N_S_memory_30020000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM2 +#define DT_N_S_memory_30020000_P_zephyr_memory_region_IDX_0 "SRAM2" +#define DT_N_S_memory_30020000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0) +#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0) +#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_30020000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_memory_30020000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_memory_30020000_P_compatible {"zephyr,memory-region", "mmio-sram"} +#define DT_N_S_memory_30020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_30020000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_memory_30020000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_memory_30020000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_memory_30020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_memory_30020000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_memory_30020000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_30020000_P_compatible_IDX_1 "mmio-sram" #define DT_N_S_memory_30020000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram #define DT_N_S_memory_30020000_P_compatible_IDX_1_STRING_TOKEN mmio_sram #define DT_N_S_memory_30020000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM -#define DT_N_S_memory_30020000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_30020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30020000, compatible, 0) \ fn(DT_N_S_memory_30020000, compatible, 1) #define DT_N_S_memory_30020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30020000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -2631,26 +2729,18 @@ fn(DT_N_S_memory_30020000, compatible, 1, __VA_ARGS__) #define DT_N_S_memory_30020000_P_compatible_LEN 2 #define DT_N_S_memory_30020000_P_compatible_EXISTS 1 -#define DT_N_S_memory_30020000_P_reg {805437440 /* 0x30020000 */, 131072 /* 0x20000 */} -#define DT_N_S_memory_30020000_P_reg_IDX_0 805437440 +#define DT_N_S_memory_30020000_P_reg {805437440, 131072} #define DT_N_S_memory_30020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_memory_30020000_P_reg_IDX_1 131072 +#define DT_N_S_memory_30020000_P_reg_IDX_0 805437440 #define DT_N_S_memory_30020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_memory_30020000_P_reg_IDX_1 131072 #define DT_N_S_memory_30020000_P_reg_EXISTS 1 #define DT_N_S_memory_30020000_P_zephyr_deferred_init 0 #define DT_N_S_memory_30020000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_memory_30020000_P_zephyr_memory_region "SRAM2" -#define DT_N_S_memory_30020000_P_zephyr_memory_region_STRING_UNQUOTED SRAM2 -#define DT_N_S_memory_30020000_P_zephyr_memory_region_STRING_TOKEN SRAM2 -#define DT_N_S_memory_30020000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM2 -#define DT_N_S_memory_30020000_P_zephyr_memory_region_IDX_0 "SRAM2" -#define DT_N_S_memory_30020000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0) -#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0) -#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_30020000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_30020000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_30020000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_memory_30020000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_memory_30020000_P_wakeup_source 0 +#define DT_N_S_memory_30020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_memory_30020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_memory_30020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /memory@30040000 @@ -2669,12 +2759,15 @@ /* Node's name with unit-address: */ #define DT_N_S_memory_30040000_FULL_NAME "memory@30040000" +#define DT_N_S_memory_30040000_FULL_NAME_UNQUOTED memory@30040000 +#define DT_N_S_memory_30040000_FULL_NAME_TOKEN memory_30040000 +#define DT_N_S_memory_30040000_FULL_NAME_UPPER_TOKEN MEMORY_30040000 /* Node parent (/) identifier: */ #define DT_N_S_memory_30040000_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_memory_30040000_CHILD_IDX 16 +#define DT_N_S_memory_30040000_CHILD_IDX 17 /* Helpers for dealing with node labels: */ #define DT_N_S_memory_30040000_NODELABEL_NUM 1 @@ -2699,7 +2792,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_30040000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_memory_30040000_SUPPORTS_ORDS /* nothing */ @@ -2713,8 +2806,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_memory_30040000_REG_NUM 1 #define DT_N_S_memory_30040000_REG_IDX_0_EXISTS 1 -#define DT_N_S_memory_30040000_REG_IDX_0_VAL_ADDRESS 805568512 /* 0x30040000 */ -#define DT_N_S_memory_30040000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */ +#define DT_N_S_memory_30040000_REG_IDX_0_VAL_ADDRESS 805568512 +#define DT_N_S_memory_30040000_REG_IDX_0_VAL_SIZE 32768 #define DT_N_S_memory_30040000_RANGES_NUM 0 #define DT_N_S_memory_30040000_FOREACH_RANGE(fn) #define DT_N_S_memory_30040000_IRQ_NUM 0 @@ -2731,21 +2824,29 @@ #define DT_N_S_memory_30040000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_memory_30040000_P_wakeup_source 0 -#define DT_N_S_memory_30040000_P_wakeup_source_EXISTS 1 -#define DT_N_S_memory_30040000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_memory_30040000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_memory_30040000_P_zephyr_memory_region "SRAM3" +#define DT_N_S_memory_30040000_P_zephyr_memory_region_STRING_UNQUOTED SRAM3 +#define DT_N_S_memory_30040000_P_zephyr_memory_region_STRING_TOKEN SRAM3 +#define DT_N_S_memory_30040000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM3 +#define DT_N_S_memory_30040000_P_zephyr_memory_region_IDX_0 "SRAM3" +#define DT_N_S_memory_30040000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0) +#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0) +#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_30040000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_memory_30040000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_memory_30040000_P_compatible {"zephyr,memory-region", "mmio-sram"} +#define DT_N_S_memory_30040000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_30040000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_memory_30040000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_memory_30040000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_memory_30040000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_memory_30040000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_memory_30040000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_30040000_P_compatible_IDX_1 "mmio-sram" #define DT_N_S_memory_30040000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram #define DT_N_S_memory_30040000_P_compatible_IDX_1_STRING_TOKEN mmio_sram #define DT_N_S_memory_30040000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM -#define DT_N_S_memory_30040000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_30040000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30040000, compatible, 0) \ fn(DT_N_S_memory_30040000, compatible, 1) #define DT_N_S_memory_30040000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30040000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -2756,26 +2857,18 @@ fn(DT_N_S_memory_30040000, compatible, 1, __VA_ARGS__) #define DT_N_S_memory_30040000_P_compatible_LEN 2 #define DT_N_S_memory_30040000_P_compatible_EXISTS 1 -#define DT_N_S_memory_30040000_P_reg {805568512 /* 0x30040000 */, 32768 /* 0x8000 */} -#define DT_N_S_memory_30040000_P_reg_IDX_0 805568512 +#define DT_N_S_memory_30040000_P_reg {805568512, 32768} #define DT_N_S_memory_30040000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_memory_30040000_P_reg_IDX_1 32768 +#define DT_N_S_memory_30040000_P_reg_IDX_0 805568512 #define DT_N_S_memory_30040000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_memory_30040000_P_reg_IDX_1 32768 #define DT_N_S_memory_30040000_P_reg_EXISTS 1 #define DT_N_S_memory_30040000_P_zephyr_deferred_init 0 #define DT_N_S_memory_30040000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_memory_30040000_P_zephyr_memory_region "SRAM3" -#define DT_N_S_memory_30040000_P_zephyr_memory_region_STRING_UNQUOTED SRAM3 -#define DT_N_S_memory_30040000_P_zephyr_memory_region_STRING_TOKEN SRAM3 -#define DT_N_S_memory_30040000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM3 -#define DT_N_S_memory_30040000_P_zephyr_memory_region_IDX_0 "SRAM3" -#define DT_N_S_memory_30040000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0) -#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0) -#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_30040000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_30040000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_30040000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_memory_30040000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_memory_30040000_P_wakeup_source 0 +#define DT_N_S_memory_30040000_P_wakeup_source_EXISTS 1 +#define DT_N_S_memory_30040000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_memory_30040000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /memory@38000000 @@ -2794,12 +2887,15 @@ /* Node's name with unit-address: */ #define DT_N_S_memory_38000000_FULL_NAME "memory@38000000" +#define DT_N_S_memory_38000000_FULL_NAME_UNQUOTED memory@38000000 +#define DT_N_S_memory_38000000_FULL_NAME_TOKEN memory_38000000 +#define DT_N_S_memory_38000000_FULL_NAME_UPPER_TOKEN MEMORY_38000000 /* Node parent (/) identifier: */ #define DT_N_S_memory_38000000_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_memory_38000000_CHILD_IDX 17 +#define DT_N_S_memory_38000000_CHILD_IDX 18 /* Helpers for dealing with node labels: */ #define DT_N_S_memory_38000000_NODELABEL_NUM 1 @@ -2824,7 +2920,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_38000000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_memory_38000000_SUPPORTS_ORDS /* nothing */ @@ -2838,8 +2934,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_memory_38000000_REG_NUM 1 #define DT_N_S_memory_38000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_memory_38000000_REG_IDX_0_VAL_ADDRESS 939524096 /* 0x38000000 */ -#define DT_N_S_memory_38000000_REG_IDX_0_VAL_SIZE 65536 /* 0x10000 */ +#define DT_N_S_memory_38000000_REG_IDX_0_VAL_ADDRESS 939524096 +#define DT_N_S_memory_38000000_REG_IDX_0_VAL_SIZE 65536 #define DT_N_S_memory_38000000_RANGES_NUM 0 #define DT_N_S_memory_38000000_FOREACH_RANGE(fn) #define DT_N_S_memory_38000000_IRQ_NUM 0 @@ -2856,21 +2952,29 @@ #define DT_N_S_memory_38000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_memory_38000000_P_wakeup_source 0 -#define DT_N_S_memory_38000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_memory_38000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_memory_38000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_memory_38000000_P_zephyr_memory_region "SRAM4" +#define DT_N_S_memory_38000000_P_zephyr_memory_region_STRING_UNQUOTED SRAM4 +#define DT_N_S_memory_38000000_P_zephyr_memory_region_STRING_TOKEN SRAM4 +#define DT_N_S_memory_38000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM4 +#define DT_N_S_memory_38000000_P_zephyr_memory_region_IDX_0 "SRAM4" +#define DT_N_S_memory_38000000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0) +#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0) +#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_38000000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_memory_38000000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_memory_38000000_P_compatible {"zephyr,memory-region", "mmio-sram"} +#define DT_N_S_memory_38000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_38000000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_memory_38000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_memory_38000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_memory_38000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_memory_38000000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_memory_38000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_38000000_P_compatible_IDX_1 "mmio-sram" #define DT_N_S_memory_38000000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram #define DT_N_S_memory_38000000_P_compatible_IDX_1_STRING_TOKEN mmio_sram #define DT_N_S_memory_38000000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM -#define DT_N_S_memory_38000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_memory_38000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_38000000, compatible, 0) \ fn(DT_N_S_memory_38000000, compatible, 1) #define DT_N_S_memory_38000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_38000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -2881,26 +2985,18 @@ fn(DT_N_S_memory_38000000, compatible, 1, __VA_ARGS__) #define DT_N_S_memory_38000000_P_compatible_LEN 2 #define DT_N_S_memory_38000000_P_compatible_EXISTS 1 -#define DT_N_S_memory_38000000_P_reg {939524096 /* 0x38000000 */, 65536 /* 0x10000 */} -#define DT_N_S_memory_38000000_P_reg_IDX_0 939524096 +#define DT_N_S_memory_38000000_P_reg {939524096, 65536} #define DT_N_S_memory_38000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_memory_38000000_P_reg_IDX_1 65536 +#define DT_N_S_memory_38000000_P_reg_IDX_0 939524096 #define DT_N_S_memory_38000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_memory_38000000_P_reg_IDX_1 65536 #define DT_N_S_memory_38000000_P_reg_EXISTS 1 #define DT_N_S_memory_38000000_P_zephyr_deferred_init 0 #define DT_N_S_memory_38000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_memory_38000000_P_zephyr_memory_region "SRAM4" -#define DT_N_S_memory_38000000_P_zephyr_memory_region_STRING_UNQUOTED SRAM4 -#define DT_N_S_memory_38000000_P_zephyr_memory_region_STRING_TOKEN SRAM4 -#define DT_N_S_memory_38000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SRAM4 -#define DT_N_S_memory_38000000_P_zephyr_memory_region_IDX_0 "SRAM4" -#define DT_N_S_memory_38000000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0) -#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0) -#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_38000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_38000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_38000000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_memory_38000000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_memory_38000000_P_wakeup_source 0 +#define DT_N_S_memory_38000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_memory_38000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_memory_38000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /memory@90000000 @@ -2919,6 +3015,9 @@ /* Node's name with unit-address: */ #define DT_N_S_memory_90000000_FULL_NAME "memory@90000000" +#define DT_N_S_memory_90000000_FULL_NAME_UNQUOTED memory@90000000 +#define DT_N_S_memory_90000000_FULL_NAME_TOKEN memory_90000000 +#define DT_N_S_memory_90000000_FULL_NAME_UPPER_TOKEN MEMORY_90000000 /* Node parent (/) identifier: */ #define DT_N_S_memory_90000000_PARENT DT_N @@ -2949,7 +3048,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_memory_90000000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_memory_90000000_SUPPORTS_ORDS /* nothing */ @@ -2962,8 +3061,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_memory_90000000_REG_NUM 1 #define DT_N_S_memory_90000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_memory_90000000_REG_IDX_0_VAL_ADDRESS 2415919104 /* 0x90000000 */ -#define DT_N_S_memory_90000000_REG_IDX_0_VAL_SIZE 268435456 /* 0x10000000 */ +#define DT_N_S_memory_90000000_REG_IDX_0_VAL_ADDRESS 2415919104 +#define DT_N_S_memory_90000000_REG_IDX_0_VAL_SIZE 268435456 #define DT_N_S_memory_90000000_RANGES_NUM 0 #define DT_N_S_memory_90000000_FOREACH_RANGE(fn) #define DT_N_S_memory_90000000_IRQ_NUM 0 @@ -2979,42 +3078,42 @@ #define DT_N_S_memory_90000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_memory_90000000_P_wakeup_source 0 -#define DT_N_S_memory_90000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_memory_90000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_memory_90000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_memory_90000000_P_zephyr_memory_region "EXTMEM" +#define DT_N_S_memory_90000000_P_zephyr_memory_region_STRING_UNQUOTED EXTMEM +#define DT_N_S_memory_90000000_P_zephyr_memory_region_STRING_TOKEN EXTMEM +#define DT_N_S_memory_90000000_P_zephyr_memory_region_STRING_UPPER_TOKEN EXTMEM +#define DT_N_S_memory_90000000_P_zephyr_memory_region_IDX_0 "EXTMEM" +#define DT_N_S_memory_90000000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0) +#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0) +#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_memory_90000000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_memory_90000000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_memory_90000000_P_compatible {"zephyr,memory-region"} +#define DT_N_S_memory_90000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_90000000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_memory_90000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_memory_90000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_memory_90000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_memory_90000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_memory_90000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_90000000, compatible, 0) #define DT_N_S_memory_90000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_90000000, compatible, 0) #define DT_N_S_memory_90000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_90000000, compatible, 0, __VA_ARGS__) #define DT_N_S_memory_90000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_90000000, compatible, 0, __VA_ARGS__) #define DT_N_S_memory_90000000_P_compatible_LEN 1 #define DT_N_S_memory_90000000_P_compatible_EXISTS 1 -#define DT_N_S_memory_90000000_P_reg {2415919104 /* 0x90000000 */, 268435456 /* 0x10000000 */} -#define DT_N_S_memory_90000000_P_reg_IDX_0 2415919104 +#define DT_N_S_memory_90000000_P_reg {2415919104, 268435456} #define DT_N_S_memory_90000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_memory_90000000_P_reg_IDX_1 268435456 +#define DT_N_S_memory_90000000_P_reg_IDX_0 2415919104 #define DT_N_S_memory_90000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_memory_90000000_P_reg_IDX_1 268435456 #define DT_N_S_memory_90000000_P_reg_EXISTS 1 #define DT_N_S_memory_90000000_P_zephyr_deferred_init 0 #define DT_N_S_memory_90000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_memory_90000000_P_zephyr_memory_region "EXTMEM" -#define DT_N_S_memory_90000000_P_zephyr_memory_region_STRING_UNQUOTED EXTMEM -#define DT_N_S_memory_90000000_P_zephyr_memory_region_STRING_TOKEN EXTMEM -#define DT_N_S_memory_90000000_P_zephyr_memory_region_STRING_UPPER_TOKEN EXTMEM -#define DT_N_S_memory_90000000_P_zephyr_memory_region_IDX_0 "EXTMEM" -#define DT_N_S_memory_90000000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0) -#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0) -#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_90000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_memory_90000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_memory_90000000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_memory_90000000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_memory_90000000_P_wakeup_source 0 +#define DT_N_S_memory_90000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_memory_90000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_memory_90000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_memory_90000000_P_zephyr_memory_attr 33554432 #define DT_N_S_memory_90000000_P_zephyr_memory_attr_EXISTS 1 @@ -3035,12 +3134,15 @@ /* Node's name with unit-address: */ #define DT_N_S_sdram_c0000000_FULL_NAME "sdram@c0000000" +#define DT_N_S_sdram_c0000000_FULL_NAME_UNQUOTED sdram@c0000000 +#define DT_N_S_sdram_c0000000_FULL_NAME_TOKEN sdram_c0000000 +#define DT_N_S_sdram_c0000000_FULL_NAME_UPPER_TOKEN SDRAM_C0000000 /* Node parent (/) identifier: */ #define DT_N_S_sdram_c0000000_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_sdram_c0000000_CHILD_IDX 22 +#define DT_N_S_sdram_c0000000_CHILD_IDX 23 /* Helpers for dealing with node labels: */ #define DT_N_S_sdram_c0000000_NODELABEL_NUM 1 @@ -3065,7 +3167,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_sdram_c0000000_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_sdram_c0000000_SUPPORTS_ORDS /* nothing */ @@ -3079,8 +3181,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_sdram_c0000000_REG_NUM 1 #define DT_N_S_sdram_c0000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_sdram_c0000000_REG_IDX_0_VAL_ADDRESS 3221225472 /* 0xc0000000 */ -#define DT_N_S_sdram_c0000000_REG_IDX_0_VAL_SIZE 8388608 /* 0x800000 */ +#define DT_N_S_sdram_c0000000_REG_IDX_0_VAL_ADDRESS 3221225472 +#define DT_N_S_sdram_c0000000_REG_IDX_0_VAL_SIZE 8388608 #define DT_N_S_sdram_c0000000_RANGES_NUM 0 #define DT_N_S_sdram_c0000000_FOREACH_RANGE(fn) #define DT_N_S_sdram_c0000000_IRQ_NUM 0 @@ -3097,21 +3199,29 @@ #define DT_N_S_sdram_c0000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_sdram_c0000000_P_wakeup_source 0 -#define DT_N_S_sdram_c0000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_sdram_c0000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_sdram_c0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region "SDRAM1" +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_STRING_UNQUOTED SDRAM1 +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_STRING_TOKEN SDRAM1 +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SDRAM1 +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_IDX_0 "SDRAM1" +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0) +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0) +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_sdram_c0000000_P_compatible {"zephyr,memory-region", "mmio-sram"} +#define DT_N_S_sdram_c0000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_sdram_c0000000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_sdram_c0000000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_sdram_c0000000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_sdram_c0000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_sdram_c0000000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_sdram_c0000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_sdram_c0000000_P_compatible_IDX_1 "mmio-sram" #define DT_N_S_sdram_c0000000_P_compatible_IDX_1_STRING_UNQUOTED mmio-sram #define DT_N_S_sdram_c0000000_P_compatible_IDX_1_STRING_TOKEN mmio_sram #define DT_N_S_sdram_c0000000_P_compatible_IDX_1_STRING_UPPER_TOKEN MMIO_SRAM -#define DT_N_S_sdram_c0000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_sdram_c0000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sdram_c0000000, compatible, 0) \ fn(DT_N_S_sdram_c0000000, compatible, 1) #define DT_N_S_sdram_c0000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sdram_c0000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -3122,26 +3232,18 @@ fn(DT_N_S_sdram_c0000000, compatible, 1, __VA_ARGS__) #define DT_N_S_sdram_c0000000_P_compatible_LEN 2 #define DT_N_S_sdram_c0000000_P_compatible_EXISTS 1 -#define DT_N_S_sdram_c0000000_P_reg {3221225472 /* 0xc0000000 */, 8388608 /* 0x800000 */} -#define DT_N_S_sdram_c0000000_P_reg_IDX_0 3221225472 +#define DT_N_S_sdram_c0000000_P_reg {3221225472, 8388608} #define DT_N_S_sdram_c0000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_sdram_c0000000_P_reg_IDX_1 8388608 +#define DT_N_S_sdram_c0000000_P_reg_IDX_0 3221225472 #define DT_N_S_sdram_c0000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_sdram_c0000000_P_reg_IDX_1 8388608 #define DT_N_S_sdram_c0000000_P_reg_EXISTS 1 #define DT_N_S_sdram_c0000000_P_zephyr_deferred_init 0 #define DT_N_S_sdram_c0000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region "SDRAM1" -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_STRING_UNQUOTED SDRAM1 -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_STRING_TOKEN SDRAM1 -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_STRING_UPPER_TOKEN SDRAM1 -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_IDX_0 "SDRAM1" -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0) -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0) -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_sdram_c0000000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_sdram_c0000000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_sdram_c0000000_P_wakeup_source 0 +#define DT_N_S_sdram_c0000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_sdram_c0000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_sdram_c0000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_sdram_c0000000_P_zephyr_memory_attr 1048576 #define DT_N_S_sdram_c0000000_P_zephyr_memory_attr_EXISTS 1 @@ -3159,6 +3261,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_FULL_NAME "i2c1_scl_pb8" +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_FULL_NAME_UNQUOTED i2c1_scl_pb8 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_FULL_NAME_TOKEN i2c1_scl_pb8 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_FULL_NAME_UPPER_TOKEN I2C1_SCL_PB8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -3189,11 +3294,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_SUPPORTS_ORDS \ - 24, /* /soc/i2c@40005400 */ + 24, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_EXISTS 1 @@ -3211,20 +3316,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_pinmux 772 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate "low-speed" @@ -3233,16 +3324,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/i2c1_sda_pb9 @@ -3258,6 +3361,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_FULL_NAME "i2c1_sda_pb9" +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_FULL_NAME_UNQUOTED i2c1_sda_pb9 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_FULL_NAME_TOKEN i2c1_sda_pb9 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_FULL_NAME_UPPER_TOKEN I2C1_SDA_PB9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -3288,11 +3394,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_SUPPORTS_ORDS \ - 24, /* /soc/i2c@40005400 */ + 24, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_EXISTS 1 @@ -3310,20 +3416,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_pinmux 804 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate "low-speed" @@ -3332,16 +3424,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/i2c@40005400 @@ -3360,6 +3464,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_40005400_FULL_NAME "i2c@40005400" +#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_UNQUOTED i2c@40005400 +#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_TOKEN i2c_40005400 +#define DT_N_S_soc_S_i2c_40005400_FULL_NAME_UPPER_TOKEN I2C_40005400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2c_40005400_PARENT DT_N_S_soc @@ -3390,16 +3497,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_40005400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 22, /* /soc/pin-controller@58020000/i2c1_scl_pb8 */ \ - 23, /* /soc/pin-controller@58020000/i2c1_sda_pb9 */ + 4, \ + 5, \ + 9, \ + 22, \ + 23, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_40005400_SUPPORTS_ORDS \ - 25, /* /smbus1 */ \ - 93, /* /zephyr,user */ + 25, \ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_40005400_EXISTS 1 @@ -3409,8 +3516,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2c_40005400_REG_NUM 1 #define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_ADDRESS 1073763328 /* 0x40005400 */ -#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_ADDRESS 1073763328 +#define DT_N_S_soc_S_i2c_40005400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2c_40005400_RANGES_NUM 0 #define DT_N_S_soc_S_i2c_40005400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2c_40005400_IRQ_NUM 2 @@ -3457,20 +3564,64 @@ #define DT_N_S_soc_S_i2c_40005400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9 /* Generic property macros: */ -#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source 0 -#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_reg {1073763328, 1024} +#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0 1073763328 +#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2c_40005400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts {31, 0, 32, 0} +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0 31 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2 32 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_i2c_40005400_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_LEN 2 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency 400000 +#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_sq_size 4 +#define DT_N_S_soc_S_i2c_40005400_P_sq_size_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_cq_size 4 +#define DT_N_S_soc_S_i2c_40005400_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_status "okay" #define DT_N_S_soc_S_i2c_40005400_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_i2c_40005400_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_i2c_40005400_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0 "okay" #define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_i2c_40005400_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_i2c_40005400_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_i2c_40005400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, status, 0) #define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, status, 0) #define DT_N_S_soc_S_i2c_40005400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, status, 0, __VA_ARGS__) @@ -3478,44 +3629,28 @@ #define DT_N_S_soc_S_i2c_40005400_P_status_LEN 1 #define DT_N_S_soc_S_i2c_40005400_P_status_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_compatible {"st,stm32-i2c-v2"} +#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0 "st,stm32-i2c-v2" #define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2 #define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2 #define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2 -#define DT_N_S_soc_S_i2c_40005400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0) #define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0) #define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_40005400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_40005400_P_compatible_LEN 1 #define DT_N_S_soc_S_i2c_40005400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_reg {1073763328 /* 0x40005400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0 1073763328 -#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_i2c_40005400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts {31 /* 0x1f */, 0 /* 0x0 */, 32 /* 0x20 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0 31 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2 32 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names {"event", "error"} +#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0 "event" #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_UNQUOTED event #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_TOKEN event #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT -#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1 "error" #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_UNQUOTED error #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_TOKEN error #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR -#define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0) \ fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 1) #define DT_N_S_soc_S_i2c_40005400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -3540,40 +3675,10 @@ #define DT_N_S_soc_S_i2c_40005400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2c_40005400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_i2c_40005400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency 400000 -#define DT_N_S_soc_S_i2c_40005400_P_clock_frequency_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_sq_size 4 -#define DT_N_S_soc_S_i2c_40005400_P_sq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_cq_size 4 -#define DT_N_S_soc_S_i2c_40005400_P_cq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2c_40005400, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_LEN 2 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005400, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_i2c_40005400_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source 0 +#define DT_N_S_soc_S_i2c_40005400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2c_40005400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /smbus1 @@ -3592,12 +3697,15 @@ /* Node's name with unit-address: */ #define DT_N_S_smbus1_FULL_NAME "smbus1" +#define DT_N_S_smbus1_FULL_NAME_UNQUOTED smbus1 +#define DT_N_S_smbus1_FULL_NAME_TOKEN smbus1 +#define DT_N_S_smbus1_FULL_NAME_UPPER_TOKEN SMBUS1 /* Node parent (/) identifier: */ #define DT_N_S_smbus1_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_smbus1_CHILD_IDX 9 +#define DT_N_S_smbus1_CHILD_IDX 10 /* Helpers for dealing with node labels: */ #define DT_N_S_smbus1_NODELABEL_NUM 1 @@ -3622,8 +3730,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus1_REQUIRES_ORDS \ - 0, /* / */ \ - 24, /* /soc/i2c@40005400 */ + 0, \ + 24, /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus1_SUPPORTS_ORDS /* nothing */ @@ -3650,20 +3758,24 @@ #define DT_N_S_smbus1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_smbus1_P_wakeup_source 0 -#define DT_N_S_smbus1_P_wakeup_source_EXISTS 1 -#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_smbus1_P_i2c DT_N_S_soc_S_i2c_40005400 +#define DT_N_S_smbus1_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005400 +#define DT_N_S_smbus1_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005400 +#define DT_N_S_smbus1_P_i2c_IDX_0_EXISTS 1 +#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, i2c, 0) +#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, i2c, 0) +#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus1_P_i2c_LEN 1 +#define DT_N_S_smbus1_P_i2c_EXISTS 1 #define DT_N_S_smbus1_P_status "disabled" #define DT_N_S_smbus1_P_status_STRING_UNQUOTED disabled #define DT_N_S_smbus1_P_status_STRING_TOKEN disabled #define DT_N_S_smbus1_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_smbus1_P_status_IDX_0 "disabled" #define DT_N_S_smbus1_P_status_IDX_0_EXISTS 1 -#define DT_N_S_smbus1_P_status_ENUM_IDX 2 -#define DT_N_S_smbus1_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_smbus1_P_status_ENUM_TOKEN disabled -#define DT_N_S_smbus1_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_smbus1_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_smbus1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, status, 0) #define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, status, 0) #define DT_N_S_smbus1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, status, 0, __VA_ARGS__) @@ -3671,11 +3783,11 @@ #define DT_N_S_smbus1_P_status_LEN 1 #define DT_N_S_smbus1_P_status_EXISTS 1 #define DT_N_S_smbus1_P_compatible {"st,stm32-smbus"} +#define DT_N_S_smbus1_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus1_P_compatible_IDX_0 "st,stm32-smbus" #define DT_N_S_smbus1_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus #define DT_N_S_smbus1_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus #define DT_N_S_smbus1_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS -#define DT_N_S_smbus1_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, compatible, 0) #define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, compatible, 0) #define DT_N_S_smbus1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, compatible, 0, __VA_ARGS__) @@ -3684,16 +3796,10 @@ #define DT_N_S_smbus1_P_compatible_EXISTS 1 #define DT_N_S_smbus1_P_zephyr_deferred_init 0 #define DT_N_S_smbus1_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_smbus1_P_i2c DT_N_S_soc_S_i2c_40005400 -#define DT_N_S_smbus1_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005400 -#define DT_N_S_smbus1_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005400 -#define DT_N_S_smbus1_P_i2c_IDX_0_EXISTS 1 -#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus1, i2c, 0) -#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus1, i2c, 0) -#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus1_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus1, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus1_P_i2c_LEN 1 -#define DT_N_S_smbus1_P_i2c_EXISTS 1 +#define DT_N_S_smbus1_P_wakeup_source 0 +#define DT_N_S_smbus1_P_wakeup_source_EXISTS 1 +#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_smbus1_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/i2c2_scl_ph4 @@ -3709,6 +3815,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_FULL_NAME "i2c2_scl_ph4" +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_FULL_NAME_UNQUOTED i2c2_scl_ph4 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_FULL_NAME_TOKEN i2c2_scl_ph4 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_FULL_NAME_UPPER_TOKEN I2C2_SCL_PH4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -3739,11 +3848,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_SUPPORTS_ORDS \ - 28, /* /soc/i2c@40005800 */ + 28, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_EXISTS 1 @@ -3761,20 +3870,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_pinmux 3716 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate "low-speed" @@ -3783,16 +3878,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/i2c2_sda_pb11 @@ -3808,6 +3915,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_FULL_NAME "i2c2_sda_pb11" +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_FULL_NAME_UNQUOTED i2c2_sda_pb11 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_FULL_NAME_TOKEN i2c2_sda_pb11 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_FULL_NAME_UPPER_TOKEN I2C2_SDA_PB11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -3838,11 +3948,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_SUPPORTS_ORDS \ - 28, /* /soc/i2c@40005800 */ + 28, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_EXISTS 1 @@ -3860,20 +3970,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_pinmux 868 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate "low-speed" @@ -3882,16 +3978,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/i2c@40005800 @@ -3910,6 +4018,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_40005800_FULL_NAME "i2c@40005800" +#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_UNQUOTED i2c@40005800 +#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_TOKEN i2c_40005800 +#define DT_N_S_soc_S_i2c_40005800_FULL_NAME_UPPER_TOKEN I2C_40005800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2c_40005800_PARENT DT_N_S_soc @@ -3940,16 +4051,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_40005800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 26, /* /soc/pin-controller@58020000/i2c2_scl_ph4 */ \ - 27, /* /soc/pin-controller@58020000/i2c2_sda_pb11 */ + 4, \ + 5, \ + 9, \ + 26, \ + 27, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_40005800_SUPPORTS_ORDS \ - 29, /* /smbus2 */ \ - 93, /* /zephyr,user */ + 29, \ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_40005800_EXISTS 1 @@ -3959,8 +4070,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2c_40005800_REG_NUM 1 #define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_ADDRESS 1073764352 /* 0x40005800 */ -#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_ADDRESS 1073764352 +#define DT_N_S_soc_S_i2c_40005800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2c_40005800_RANGES_NUM 0 #define DT_N_S_soc_S_i2c_40005800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2c_40005800_IRQ_NUM 2 @@ -4007,20 +4118,64 @@ #define DT_N_S_soc_S_i2c_40005800_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11 /* Generic property macros: */ -#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source 0 -#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_reg {1073764352, 1024} +#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0 1073764352 +#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2c_40005800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts {33, 0, 34, 0} +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0 33 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2 34 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_i2c_40005800_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_LEN 2 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency 400000 +#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_sq_size 4 +#define DT_N_S_soc_S_i2c_40005800_P_sq_size_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_cq_size 4 +#define DT_N_S_soc_S_i2c_40005800_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_status "okay" #define DT_N_S_soc_S_i2c_40005800_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_i2c_40005800_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_i2c_40005800_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0 "okay" #define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_i2c_40005800_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_i2c_40005800_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_i2c_40005800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, status, 0) #define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, status, 0) #define DT_N_S_soc_S_i2c_40005800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, status, 0, __VA_ARGS__) @@ -4028,44 +4183,28 @@ #define DT_N_S_soc_S_i2c_40005800_P_status_LEN 1 #define DT_N_S_soc_S_i2c_40005800_P_status_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_compatible {"st,stm32-i2c-v2"} +#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0 "st,stm32-i2c-v2" #define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2 #define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2 #define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2 -#define DT_N_S_soc_S_i2c_40005800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0) #define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0) #define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_40005800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_40005800_P_compatible_LEN 1 #define DT_N_S_soc_S_i2c_40005800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_reg {1073764352 /* 0x40005800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0 1073764352 -#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_i2c_40005800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts {33 /* 0x21 */, 0 /* 0x0 */, 34 /* 0x22 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0 33 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2 34 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names {"event", "error"} +#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0 "event" #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_UNQUOTED event #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_TOKEN event #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT -#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1 "error" #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_UNQUOTED error #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_TOKEN error #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR -#define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0) \ fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 1) #define DT_N_S_soc_S_i2c_40005800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -4090,40 +4229,10 @@ #define DT_N_S_soc_S_i2c_40005800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2c_40005800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_i2c_40005800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency 400000 -#define DT_N_S_soc_S_i2c_40005800_P_clock_frequency_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_sq_size 4 -#define DT_N_S_soc_S_i2c_40005800_P_sq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_cq_size 4 -#define DT_N_S_soc_S_i2c_40005800_P_cq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2c_40005800, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_LEN 2 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005800, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_i2c_40005800_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source 0 +#define DT_N_S_soc_S_i2c_40005800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2c_40005800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /smbus2 @@ -4142,12 +4251,15 @@ /* Node's name with unit-address: */ #define DT_N_S_smbus2_FULL_NAME "smbus2" +#define DT_N_S_smbus2_FULL_NAME_UNQUOTED smbus2 +#define DT_N_S_smbus2_FULL_NAME_TOKEN smbus2 +#define DT_N_S_smbus2_FULL_NAME_UPPER_TOKEN SMBUS2 /* Node parent (/) identifier: */ #define DT_N_S_smbus2_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_smbus2_CHILD_IDX 10 +#define DT_N_S_smbus2_CHILD_IDX 11 /* Helpers for dealing with node labels: */ #define DT_N_S_smbus2_NODELABEL_NUM 1 @@ -4172,8 +4284,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus2_REQUIRES_ORDS \ - 0, /* / */ \ - 28, /* /soc/i2c@40005800 */ + 0, \ + 28, /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus2_SUPPORTS_ORDS /* nothing */ @@ -4200,20 +4312,24 @@ #define DT_N_S_smbus2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_smbus2_P_wakeup_source 0 -#define DT_N_S_smbus2_P_wakeup_source_EXISTS 1 -#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_smbus2_P_i2c DT_N_S_soc_S_i2c_40005800 +#define DT_N_S_smbus2_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005800 +#define DT_N_S_smbus2_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005800 +#define DT_N_S_smbus2_P_i2c_IDX_0_EXISTS 1 +#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, i2c, 0) +#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, i2c, 0) +#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus2_P_i2c_LEN 1 +#define DT_N_S_smbus2_P_i2c_EXISTS 1 #define DT_N_S_smbus2_P_status "disabled" #define DT_N_S_smbus2_P_status_STRING_UNQUOTED disabled #define DT_N_S_smbus2_P_status_STRING_TOKEN disabled #define DT_N_S_smbus2_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_smbus2_P_status_IDX_0 "disabled" #define DT_N_S_smbus2_P_status_IDX_0_EXISTS 1 -#define DT_N_S_smbus2_P_status_ENUM_IDX 2 -#define DT_N_S_smbus2_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_smbus2_P_status_ENUM_TOKEN disabled -#define DT_N_S_smbus2_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_smbus2_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_smbus2_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, status, 0) #define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, status, 0) #define DT_N_S_smbus2_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, status, 0, __VA_ARGS__) @@ -4221,11 +4337,11 @@ #define DT_N_S_smbus2_P_status_LEN 1 #define DT_N_S_smbus2_P_status_EXISTS 1 #define DT_N_S_smbus2_P_compatible {"st,stm32-smbus"} +#define DT_N_S_smbus2_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus2_P_compatible_IDX_0 "st,stm32-smbus" #define DT_N_S_smbus2_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus #define DT_N_S_smbus2_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus #define DT_N_S_smbus2_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS -#define DT_N_S_smbus2_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, compatible, 0) #define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, compatible, 0) #define DT_N_S_smbus2_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, compatible, 0, __VA_ARGS__) @@ -4234,16 +4350,10 @@ #define DT_N_S_smbus2_P_compatible_EXISTS 1 #define DT_N_S_smbus2_P_zephyr_deferred_init 0 #define DT_N_S_smbus2_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_smbus2_P_i2c DT_N_S_soc_S_i2c_40005800 -#define DT_N_S_smbus2_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005800 -#define DT_N_S_smbus2_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005800 -#define DT_N_S_smbus2_P_i2c_IDX_0_EXISTS 1 -#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus2, i2c, 0) -#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus2, i2c, 0) -#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus2_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus2, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus2_P_i2c_LEN 1 -#define DT_N_S_smbus2_P_i2c_EXISTS 1 +#define DT_N_S_smbus2_P_wakeup_source 0 +#define DT_N_S_smbus2_P_wakeup_source_EXISTS 1 +#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_smbus2_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/i2c@40005c00 @@ -4262,6 +4372,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_40005c00_FULL_NAME "i2c@40005c00" +#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME_UNQUOTED i2c@40005c00 +#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME_TOKEN i2c_40005c00 +#define DT_N_S_soc_S_i2c_40005c00_FULL_NAME_UPPER_TOKEN I2C_40005C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2c_40005c00_PARENT DT_N_S_soc @@ -4292,13 +4405,13 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_40005c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_40005c00_SUPPORTS_ORDS \ - 31, /* /smbus3 */ + 31, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_40005c00_EXISTS 1 @@ -4308,8 +4421,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2c_40005c00_REG_NUM 1 #define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_VAL_ADDRESS 1073765376 /* 0x40005c00 */ -#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_VAL_ADDRESS 1073765376 +#define DT_N_S_soc_S_i2c_40005c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2c_40005c00_RANGES_NUM 0 #define DT_N_S_soc_S_i2c_40005c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2c_40005c00_IRQ_NUM 2 @@ -4349,20 +4462,36 @@ #define DT_N_S_soc_S_i2c_40005c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_i2c_40005c00_P_wakeup_source 0 -#define DT_N_S_soc_S_i2c_40005c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_reg {1073765376, 1024} +#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_0 1073765376 +#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2c_40005c00_P_reg_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts {72, 0, 73, 0} +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_0 72 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_2 73 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_clock_frequency 100000 +#define DT_N_S_soc_S_i2c_40005c00_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_sq_size 4 +#define DT_N_S_soc_S_i2c_40005c00_P_sq_size_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_cq_size 4 +#define DT_N_S_soc_S_i2c_40005c00_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_status "disabled" #define DT_N_S_soc_S_i2c_40005c00_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_i2c_40005c00_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_i2c_40005c00_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_i2c_40005c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_i2c_40005c00_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_i2c_40005c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, status, 0) #define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, status, 0) #define DT_N_S_soc_S_i2c_40005c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, status, 0, __VA_ARGS__) @@ -4370,44 +4499,28 @@ #define DT_N_S_soc_S_i2c_40005c00_P_status_LEN 1 #define DT_N_S_soc_S_i2c_40005c00_P_status_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_compatible {"st,stm32-i2c-v2"} +#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0 "st,stm32-i2c-v2" #define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2 #define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2 #define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2 -#define DT_N_S_soc_S_i2c_40005c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0) #define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0) #define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_40005c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_40005c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_40005c00_P_compatible_LEN 1 #define DT_N_S_soc_S_i2c_40005c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_reg {1073765376 /* 0x40005c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_0 1073765376 -#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_i2c_40005c00_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts {72 /* 0x48 */, 0 /* 0x0 */, 73 /* 0x49 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_0 72 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_2 73 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names {"event", "error"} +#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0 "event" #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_STRING_UNQUOTED event #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_STRING_TOKEN event #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT -#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1 "error" #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_STRING_UNQUOTED error #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_STRING_TOKEN error #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR -#define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 0) \ fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 1) #define DT_N_S_soc_S_i2c_40005c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_40005c00, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -4432,12 +4545,10 @@ #define DT_N_S_soc_S_i2c_40005c00_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2c_40005c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_i2c_40005c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_clock_frequency 100000 -#define DT_N_S_soc_S_i2c_40005c00_P_clock_frequency_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_sq_size 4 -#define DT_N_S_soc_S_i2c_40005c00_P_sq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_40005c00_P_cq_size 4 -#define DT_N_S_soc_S_i2c_40005c00_P_cq_size_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_wakeup_source 0 +#define DT_N_S_soc_S_i2c_40005c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2c_40005c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /smbus3 @@ -4456,12 +4567,15 @@ /* Node's name with unit-address: */ #define DT_N_S_smbus3_FULL_NAME "smbus3" +#define DT_N_S_smbus3_FULL_NAME_UNQUOTED smbus3 +#define DT_N_S_smbus3_FULL_NAME_TOKEN smbus3 +#define DT_N_S_smbus3_FULL_NAME_UPPER_TOKEN SMBUS3 /* Node parent (/) identifier: */ #define DT_N_S_smbus3_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_smbus3_CHILD_IDX 11 +#define DT_N_S_smbus3_CHILD_IDX 12 /* Helpers for dealing with node labels: */ #define DT_N_S_smbus3_NODELABEL_NUM 1 @@ -4486,8 +4600,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus3_REQUIRES_ORDS \ - 0, /* / */ \ - 30, /* /soc/i2c@40005c00 */ + 0, \ + 30, /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus3_SUPPORTS_ORDS /* nothing */ @@ -4514,20 +4628,24 @@ #define DT_N_S_smbus3_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_smbus3_P_wakeup_source 0 -#define DT_N_S_smbus3_P_wakeup_source_EXISTS 1 -#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_smbus3_P_i2c DT_N_S_soc_S_i2c_40005c00 +#define DT_N_S_smbus3_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005c00 +#define DT_N_S_smbus3_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005c00 +#define DT_N_S_smbus3_P_i2c_IDX_0_EXISTS 1 +#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, i2c, 0) +#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, i2c, 0) +#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus3_P_i2c_LEN 1 +#define DT_N_S_smbus3_P_i2c_EXISTS 1 #define DT_N_S_smbus3_P_status "disabled" #define DT_N_S_smbus3_P_status_STRING_UNQUOTED disabled #define DT_N_S_smbus3_P_status_STRING_TOKEN disabled #define DT_N_S_smbus3_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_smbus3_P_status_IDX_0 "disabled" #define DT_N_S_smbus3_P_status_IDX_0_EXISTS 1 -#define DT_N_S_smbus3_P_status_ENUM_IDX 2 -#define DT_N_S_smbus3_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_smbus3_P_status_ENUM_TOKEN disabled -#define DT_N_S_smbus3_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_smbus3_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_smbus3_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, status, 0) #define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, status, 0) #define DT_N_S_smbus3_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, status, 0, __VA_ARGS__) @@ -4535,11 +4653,11 @@ #define DT_N_S_smbus3_P_status_LEN 1 #define DT_N_S_smbus3_P_status_EXISTS 1 #define DT_N_S_smbus3_P_compatible {"st,stm32-smbus"} +#define DT_N_S_smbus3_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus3_P_compatible_IDX_0 "st,stm32-smbus" #define DT_N_S_smbus3_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus #define DT_N_S_smbus3_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus #define DT_N_S_smbus3_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS -#define DT_N_S_smbus3_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, compatible, 0) #define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, compatible, 0) #define DT_N_S_smbus3_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, compatible, 0, __VA_ARGS__) @@ -4548,16 +4666,10 @@ #define DT_N_S_smbus3_P_compatible_EXISTS 1 #define DT_N_S_smbus3_P_zephyr_deferred_init 0 #define DT_N_S_smbus3_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_smbus3_P_i2c DT_N_S_soc_S_i2c_40005c00 -#define DT_N_S_smbus3_P_i2c_IDX_0 DT_N_S_soc_S_i2c_40005c00 -#define DT_N_S_smbus3_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_40005c00 -#define DT_N_S_smbus3_P_i2c_IDX_0_EXISTS 1 -#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus3, i2c, 0) -#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus3, i2c, 0) -#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus3_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus3, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus3_P_i2c_LEN 1 -#define DT_N_S_smbus3_P_i2c_EXISTS 1 +#define DT_N_S_smbus3_P_wakeup_source 0 +#define DT_N_S_smbus3_P_wakeup_source_EXISTS 1 +#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_smbus3_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/i2c4_scl_pb6 @@ -4573,6 +4685,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_FULL_NAME "i2c4_scl_pb6" +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_FULL_NAME_UNQUOTED i2c4_scl_pb6 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_FULL_NAME_TOKEN i2c4_scl_pb6 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_FULL_NAME_UPPER_TOKEN I2C4_SCL_PB6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -4603,11 +4718,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_SUPPORTS_ORDS \ - 34, /* /soc/i2c@58001c00 */ + 34, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_EXISTS 1 @@ -4625,20 +4740,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_pinmux 710 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate "low-speed" @@ -4647,16 +4748,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/i2c4_sda_ph12 @@ -4672,6 +4785,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_FULL_NAME "i2c4_sda_ph12" +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_FULL_NAME_UNQUOTED i2c4_sda_ph12 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_FULL_NAME_TOKEN i2c4_sda_ph12 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_FULL_NAME_UPPER_TOKEN I2C4_SDA_PH12 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -4702,11 +4818,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_SUPPORTS_ORDS \ - 34, /* /soc/i2c@58001c00 */ + 34, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_EXISTS 1 @@ -4724,20 +4840,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_pinmux 3972 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate "low-speed" @@ -4746,16 +4848,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12_P_output_high_EXISTS 1 /* * Devicetree node: /soc/i2c@58001c00 @@ -4774,6 +4888,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_58001c00_FULL_NAME "i2c@58001c00" +#define DT_N_S_soc_S_i2c_58001c00_FULL_NAME_UNQUOTED i2c@58001c00 +#define DT_N_S_soc_S_i2c_58001c00_FULL_NAME_TOKEN i2c_58001c00 +#define DT_N_S_soc_S_i2c_58001c00_FULL_NAME_UPPER_TOKEN I2C_58001C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2c_58001c00_PARENT DT_N_S_soc @@ -4804,17 +4921,17 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_58001c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 32, /* /soc/pin-controller@58020000/i2c4_scl_pb6 */ \ - 33, /* /soc/pin-controller@58020000/i2c4_sda_ph12 */ + 4, \ + 5, \ + 9, \ + 32, \ + 33, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_58001c00_SUPPORTS_ORDS \ - 35, /* /smbus4 */ \ - 93, /* /zephyr,user */ \ - 163, /* /soc/i2c@58001c00/ov7670@21 */ + 35, \ + 93, \ + 166, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_58001c00_EXISTS 1 @@ -4825,8 +4942,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2c_58001c00_REG_NUM 1 #define DT_N_S_soc_S_i2c_58001c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_REG_IDX_0_VAL_ADDRESS 1476402176 /* 0x58001c00 */ -#define DT_N_S_soc_S_i2c_58001c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2c_58001c00_REG_IDX_0_VAL_ADDRESS 1476402176 +#define DT_N_S_soc_S_i2c_58001c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2c_58001c00_RANGES_NUM 0 #define DT_N_S_soc_S_i2c_58001c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2c_58001c00_IRQ_NUM 2 @@ -4873,20 +4990,64 @@ #define DT_N_S_soc_S_i2c_58001c00_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12 /* Generic property macros: */ -#define DT_N_S_soc_S_i2c_58001c00_P_wakeup_source 0 -#define DT_N_S_soc_S_i2c_58001c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2c_58001c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_reg {1476402176, 1024} +#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_0 1476402176 +#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2c_58001c00_P_reg_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts {95, 0, 96, 0} +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_0 95 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_2 96 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_LEN 2 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_clock_frequency 100000 +#define DT_N_S_soc_S_i2c_58001c00_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_sq_size 4 +#define DT_N_S_soc_S_i2c_58001c00_P_sq_size_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_cq_size 4 +#define DT_N_S_soc_S_i2c_58001c00_P_cq_size_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_status "okay" #define DT_N_S_soc_S_i2c_58001c00_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_i2c_58001c00_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_i2c_58001c00_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_i2c_58001c00_P_status_IDX_0 "okay" #define DT_N_S_soc_S_i2c_58001c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_i2c_58001c00_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_i2c_58001c00_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_i2c_58001c00_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_i2c_58001c00_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, status, 0) #define DT_N_S_soc_S_i2c_58001c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, status, 0) #define DT_N_S_soc_S_i2c_58001c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, status, 0, __VA_ARGS__) @@ -4894,44 +5055,28 @@ #define DT_N_S_soc_S_i2c_58001c00_P_status_LEN 1 #define DT_N_S_soc_S_i2c_58001c00_P_status_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_compatible {"st,stm32-i2c-v2"} +#define DT_N_S_soc_S_i2c_58001c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_compatible_IDX_0 "st,stm32-i2c-v2" #define DT_N_S_soc_S_i2c_58001c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-i2c-v2 #define DT_N_S_soc_S_i2c_58001c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_i2c_v2 #define DT_N_S_soc_S_i2c_58001c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_I2C_V2 -#define DT_N_S_soc_S_i2c_58001c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, compatible, 0) #define DT_N_S_soc_S_i2c_58001c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, compatible, 0) #define DT_N_S_soc_S_i2c_58001c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_58001c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_58001c00_P_compatible_LEN 1 #define DT_N_S_soc_S_i2c_58001c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_reg {1476402176 /* 0x58001c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_0 1476402176 -#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_i2c_58001c00_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts {95 /* 0x5f */, 0 /* 0x0 */, 96 /* 0x60 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_0 95 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_2 96 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names {"event", "error"} +#define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_0 "event" #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_0_STRING_UNQUOTED event #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_0_STRING_TOKEN event #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EVENT -#define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_1 "error" #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_1_STRING_UNQUOTED error #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_1_STRING_TOKEN error #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN ERROR -#define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, interrupt_names, 0) \ fn(DT_N_S_soc_S_i2c_58001c00, interrupt_names, 1) #define DT_N_S_soc_S_i2c_58001c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -4956,40 +5101,10 @@ #define DT_N_S_soc_S_i2c_58001c00_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_i2c_58001c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_clock_frequency 100000 -#define DT_N_S_soc_S_i2c_58001c00_P_clock_frequency_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_sq_size 4 -#define DT_N_S_soc_S_i2c_58001c00_P_sq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_cq_size 4 -#define DT_N_S_soc_S_i2c_58001c00_P_cq_size_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_LEN 2 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_i2c_58001c00_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_wakeup_source 0 +#define DT_N_S_soc_S_i2c_58001c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2c_58001c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /smbus4 @@ -5008,12 +5123,15 @@ /* Node's name with unit-address: */ #define DT_N_S_smbus4_FULL_NAME "smbus4" +#define DT_N_S_smbus4_FULL_NAME_UNQUOTED smbus4 +#define DT_N_S_smbus4_FULL_NAME_TOKEN smbus4 +#define DT_N_S_smbus4_FULL_NAME_UPPER_TOKEN SMBUS4 /* Node parent (/) identifier: */ #define DT_N_S_smbus4_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_smbus4_CHILD_IDX 12 +#define DT_N_S_smbus4_CHILD_IDX 13 /* Helpers for dealing with node labels: */ #define DT_N_S_smbus4_NODELABEL_NUM 1 @@ -5038,8 +5156,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_smbus4_REQUIRES_ORDS \ - 0, /* / */ \ - 34, /* /soc/i2c@58001c00 */ + 0, \ + 34, /* Ordinals for what depends directly on this node: */ #define DT_N_S_smbus4_SUPPORTS_ORDS /* nothing */ @@ -5066,20 +5184,24 @@ #define DT_N_S_smbus4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_smbus4_P_wakeup_source 0 -#define DT_N_S_smbus4_P_wakeup_source_EXISTS 1 -#define DT_N_S_smbus4_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_smbus4_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_smbus4_P_i2c DT_N_S_soc_S_i2c_58001c00 +#define DT_N_S_smbus4_P_i2c_IDX_0 DT_N_S_soc_S_i2c_58001c00 +#define DT_N_S_smbus4_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_58001c00 +#define DT_N_S_smbus4_P_i2c_IDX_0_EXISTS 1 +#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus4, i2c, 0) +#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus4, i2c, 0) +#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus4, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus4, i2c, 0, __VA_ARGS__) +#define DT_N_S_smbus4_P_i2c_LEN 1 +#define DT_N_S_smbus4_P_i2c_EXISTS 1 #define DT_N_S_smbus4_P_status "disabled" #define DT_N_S_smbus4_P_status_STRING_UNQUOTED disabled #define DT_N_S_smbus4_P_status_STRING_TOKEN disabled #define DT_N_S_smbus4_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_smbus4_P_status_IDX_0 "disabled" #define DT_N_S_smbus4_P_status_IDX_0_EXISTS 1 -#define DT_N_S_smbus4_P_status_ENUM_IDX 2 -#define DT_N_S_smbus4_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_smbus4_P_status_ENUM_TOKEN disabled -#define DT_N_S_smbus4_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_smbus4_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_smbus4_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_smbus4_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus4, status, 0) #define DT_N_S_smbus4_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus4, status, 0) #define DT_N_S_smbus4_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus4, status, 0, __VA_ARGS__) @@ -5087,11 +5209,11 @@ #define DT_N_S_smbus4_P_status_LEN 1 #define DT_N_S_smbus4_P_status_EXISTS 1 #define DT_N_S_smbus4_P_compatible {"st,stm32-smbus"} +#define DT_N_S_smbus4_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus4_P_compatible_IDX_0 "st,stm32-smbus" #define DT_N_S_smbus4_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-smbus #define DT_N_S_smbus4_P_compatible_IDX_0_STRING_TOKEN st_stm32_smbus #define DT_N_S_smbus4_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SMBUS -#define DT_N_S_smbus4_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_smbus4_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus4, compatible, 0) #define DT_N_S_smbus4_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus4, compatible, 0) #define DT_N_S_smbus4_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus4, compatible, 0, __VA_ARGS__) @@ -5100,16 +5222,10 @@ #define DT_N_S_smbus4_P_compatible_EXISTS 1 #define DT_N_S_smbus4_P_zephyr_deferred_init 0 #define DT_N_S_smbus4_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_smbus4_P_i2c DT_N_S_soc_S_i2c_58001c00 -#define DT_N_S_smbus4_P_i2c_IDX_0 DT_N_S_soc_S_i2c_58001c00 -#define DT_N_S_smbus4_P_i2c_IDX_0_PH DT_N_S_soc_S_i2c_58001c00 -#define DT_N_S_smbus4_P_i2c_IDX_0_EXISTS 1 -#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM(fn) fn(DT_N_S_smbus4, i2c, 0) -#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_smbus4, i2c, 0) -#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_smbus4, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus4_P_i2c_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_smbus4, i2c, 0, __VA_ARGS__) -#define DT_N_S_smbus4_P_i2c_LEN 1 -#define DT_N_S_smbus4_P_i2c_EXISTS 1 +#define DT_N_S_smbus4_P_wakeup_source 0 +#define DT_N_S_smbus4_P_wakeup_source_EXISTS 1 +#define DT_N_S_smbus4_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_smbus4_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /vbat @@ -5128,12 +5244,15 @@ /* Node's name with unit-address: */ #define DT_N_S_vbat_FULL_NAME "vbat" +#define DT_N_S_vbat_FULL_NAME_UNQUOTED vbat +#define DT_N_S_vbat_FULL_NAME_TOKEN vbat +#define DT_N_S_vbat_FULL_NAME_UPPER_TOKEN VBAT /* Node parent (/) identifier: */ #define DT_N_S_vbat_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_vbat_CHILD_IDX 7 +#define DT_N_S_vbat_CHILD_IDX 8 /* Helpers for dealing with node labels: */ #define DT_N_S_vbat_NODELABEL_NUM 1 @@ -5158,8 +5277,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_vbat_REQUIRES_ORDS \ - 0, /* / */ \ - 13, /* /soc/adc@58026000 */ + 0, \ + 13, /* Ordinals for what depends directly on this node: */ #define DT_N_S_vbat_SUPPORTS_ORDS /* nothing */ @@ -5186,20 +5305,26 @@ #define DT_N_S_vbat_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_vbat_P_wakeup_source 0 -#define DT_N_S_vbat_P_wakeup_source_EXISTS 1 -#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_vbat_P_io_channels_IDX_0_EXISTS 1 +#define DT_N_S_vbat_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_58026000 +#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input 17 +#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input_EXISTS 1 +#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, io_channels, 0) +#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, io_channels, 0) +#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__) +#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__) +#define DT_N_S_vbat_P_io_channels_LEN 1 +#define DT_N_S_vbat_P_io_channels_EXISTS 1 +#define DT_N_S_vbat_P_ratio 4 +#define DT_N_S_vbat_P_ratio_EXISTS 1 #define DT_N_S_vbat_P_status "disabled" #define DT_N_S_vbat_P_status_STRING_UNQUOTED disabled #define DT_N_S_vbat_P_status_STRING_TOKEN disabled #define DT_N_S_vbat_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_vbat_P_status_IDX_0 "disabled" #define DT_N_S_vbat_P_status_IDX_0_EXISTS 1 -#define DT_N_S_vbat_P_status_ENUM_IDX 2 -#define DT_N_S_vbat_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_vbat_P_status_ENUM_TOKEN disabled -#define DT_N_S_vbat_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_vbat_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_vbat_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, status, 0) #define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, status, 0) #define DT_N_S_vbat_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, status, 0, __VA_ARGS__) @@ -5207,31 +5332,23 @@ #define DT_N_S_vbat_P_status_LEN 1 #define DT_N_S_vbat_P_status_EXISTS 1 #define DT_N_S_vbat_P_compatible {"st,stm32-vbat"} +#define DT_N_S_vbat_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_vbat_P_compatible_IDX_0 "st,stm32-vbat" #define DT_N_S_vbat_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-vbat #define DT_N_S_vbat_P_compatible_IDX_0_STRING_TOKEN st_stm32_vbat #define DT_N_S_vbat_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_VBAT -#define DT_N_S_vbat_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, compatible, 0) #define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, compatible, 0) #define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, compatible, 0, __VA_ARGS__) #define DT_N_S_vbat_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, compatible, 0, __VA_ARGS__) #define DT_N_S_vbat_P_compatible_LEN 1 #define DT_N_S_vbat_P_compatible_EXISTS 1 -#define DT_N_S_vbat_P_io_channels_IDX_0_EXISTS 1 -#define DT_N_S_vbat_P_io_channels_IDX_0_PH DT_N_S_soc_S_adc_58026000 -#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input 17 -#define DT_N_S_vbat_P_io_channels_IDX_0_VAL_input_EXISTS 1 -#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vbat, io_channels, 0) -#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vbat, io_channels, 0) -#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__) -#define DT_N_S_vbat_P_io_channels_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_vbat, io_channels, 0, __VA_ARGS__) -#define DT_N_S_vbat_P_io_channels_LEN 1 -#define DT_N_S_vbat_P_io_channels_EXISTS 1 #define DT_N_S_vbat_P_zephyr_deferred_init 0 #define DT_N_S_vbat_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_vbat_P_ratio 4 -#define DT_N_S_vbat_P_ratio_EXISTS 1 +#define DT_N_S_vbat_P_wakeup_source 0 +#define DT_N_S_vbat_P_wakeup_source_EXISTS 1 +#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_vbat_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /vref @@ -5250,12 +5367,15 @@ /* Node's name with unit-address: */ #define DT_N_S_vref_FULL_NAME "vref" +#define DT_N_S_vref_FULL_NAME_UNQUOTED vref +#define DT_N_S_vref_FULL_NAME_TOKEN vref +#define DT_N_S_vref_FULL_NAME_UPPER_TOKEN VREF /* Node parent (/) identifier: */ #define DT_N_S_vref_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_vref_CHILD_IDX 8 +#define DT_N_S_vref_CHILD_IDX 9 /* Helpers for dealing with node labels: */ #define DT_N_S_vref_NODELABEL_NUM 1 @@ -5280,8 +5400,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_vref_REQUIRES_ORDS \ - 0, /* / */ \ - 13, /* /soc/adc@58026000 */ + 0, \ + 13, /* Ordinals for what depends directly on this node: */ #define DT_N_S_vref_SUPPORTS_ORDS /* nothing */ @@ -5308,20 +5428,18 @@ #define DT_N_S_vref_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_vref_P_wakeup_source 0 -#define DT_N_S_vref_P_wakeup_source_EXISTS 1 -#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_vref_P_vrefint_cal_addr 535947360 +#define DT_N_S_vref_P_vrefint_cal_addr_EXISTS 1 +#define DT_N_S_vref_P_vrefint_cal_mv 3300 +#define DT_N_S_vref_P_vrefint_cal_mv_EXISTS 1 #define DT_N_S_vref_P_status "disabled" #define DT_N_S_vref_P_status_STRING_UNQUOTED disabled #define DT_N_S_vref_P_status_STRING_TOKEN disabled #define DT_N_S_vref_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_vref_P_status_IDX_0 "disabled" #define DT_N_S_vref_P_status_IDX_0_EXISTS 1 -#define DT_N_S_vref_P_status_ENUM_IDX 2 -#define DT_N_S_vref_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_vref_P_status_ENUM_TOKEN disabled -#define DT_N_S_vref_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_vref_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_vref_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_vref_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, status, 0) #define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, status, 0) #define DT_N_S_vref_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, status, 0, __VA_ARGS__) @@ -5329,11 +5447,11 @@ #define DT_N_S_vref_P_status_LEN 1 #define DT_N_S_vref_P_status_EXISTS 1 #define DT_N_S_vref_P_compatible {"st,stm32-vref"} +#define DT_N_S_vref_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_vref_P_compatible_IDX_0 "st,stm32-vref" #define DT_N_S_vref_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-vref #define DT_N_S_vref_P_compatible_IDX_0_STRING_TOKEN st_stm32_vref #define DT_N_S_vref_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_VREF -#define DT_N_S_vref_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_vref, compatible, 0) #define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_vref, compatible, 0) #define DT_N_S_vref_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_vref, compatible, 0, __VA_ARGS__) @@ -5352,10 +5470,10 @@ #define DT_N_S_vref_P_io_channels_EXISTS 1 #define DT_N_S_vref_P_zephyr_deferred_init 0 #define DT_N_S_vref_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_vref_P_vrefint_cal_addr 535947360 -#define DT_N_S_vref_P_vrefint_cal_addr_EXISTS 1 -#define DT_N_S_vref_P_vrefint_cal_mv 3300 -#define DT_N_S_vref_P_vrefint_cal_mv_EXISTS 1 +#define DT_N_S_vref_P_wakeup_source 0 +#define DT_N_S_vref_P_wakeup_source_EXISTS 1 +#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_vref_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /gpio@deadbeef @@ -5374,12 +5492,15 @@ /* Node's name with unit-address: */ #define DT_N_S_gpio_deadbeef_FULL_NAME "gpio@deadbeef" +#define DT_N_S_gpio_deadbeef_FULL_NAME_UNQUOTED gpio@deadbeef +#define DT_N_S_gpio_deadbeef_FULL_NAME_TOKEN gpio_deadbeef +#define DT_N_S_gpio_deadbeef_FULL_NAME_UPPER_TOKEN GPIO_DEADBEEF /* Node parent (/) identifier: */ #define DT_N_S_gpio_deadbeef_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_gpio_deadbeef_CHILD_IDX 23 +#define DT_N_S_gpio_deadbeef_CHILD_IDX 24 /* Helpers for dealing with node labels: */ #define DT_N_S_gpio_deadbeef_NODELABEL_NUM 1 @@ -5404,11 +5525,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_deadbeef_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_deadbeef_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_gpio_deadbeef_EXISTS 1 @@ -5418,8 +5539,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_gpio_deadbeef_REG_NUM 1 #define DT_N_S_gpio_deadbeef_REG_IDX_0_EXISTS 1 -#define DT_N_S_gpio_deadbeef_REG_IDX_0_VAL_ADDRESS 3735928559 /* 0xdeadbeef */ -#define DT_N_S_gpio_deadbeef_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ +#define DT_N_S_gpio_deadbeef_REG_IDX_0_VAL_ADDRESS 3735928559 +#define DT_N_S_gpio_deadbeef_REG_IDX_0_VAL_SIZE 4096 #define DT_N_S_gpio_deadbeef_RANGES_NUM 0 #define DT_N_S_gpio_deadbeef_FOREACH_RANGE(fn) #define DT_N_S_gpio_deadbeef_IRQ_NUM 0 @@ -5435,24 +5556,24 @@ #define DT_N_S_gpio_deadbeef_PINCTRL_NUM 0 /* Generic property macros: */ +#define DT_N_S_gpio_deadbeef_P_reg {3735928559, 4096} +#define DT_N_S_gpio_deadbeef_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_reg_IDX_0 3735928559 +#define DT_N_S_gpio_deadbeef_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_reg_IDX_1 4096 +#define DT_N_S_gpio_deadbeef_P_reg_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_gpio_controller 1 #define DT_N_S_gpio_deadbeef_P_gpio_controller_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_ngpios 32 #define DT_N_S_gpio_deadbeef_P_ngpios_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_wakeup_source 0 -#define DT_N_S_gpio_deadbeef_P_wakeup_source_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_gpio_deadbeef_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_status "okay" #define DT_N_S_gpio_deadbeef_P_status_STRING_UNQUOTED okay #define DT_N_S_gpio_deadbeef_P_status_STRING_TOKEN okay #define DT_N_S_gpio_deadbeef_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_gpio_deadbeef_P_status_IDX_0 "okay" #define DT_N_S_gpio_deadbeef_P_status_IDX_0_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_status_ENUM_IDX 1 -#define DT_N_S_gpio_deadbeef_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_status_ENUM_TOKEN okay -#define DT_N_S_gpio_deadbeef_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_gpio_deadbeef_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_gpio_deadbeef_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_deadbeef, status, 0) #define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_deadbeef, status, 0) #define DT_N_S_gpio_deadbeef_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_deadbeef, status, 0, __VA_ARGS__) @@ -5460,25 +5581,23 @@ #define DT_N_S_gpio_deadbeef_P_status_LEN 1 #define DT_N_S_gpio_deadbeef_P_status_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_compatible {"vnd,gpio"} +#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_compatible_IDX_0 "vnd,gpio" #define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_STRING_UNQUOTED vnd,gpio #define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_STRING_TOKEN vnd_gpio #define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_STRING_UPPER_TOKEN VND_GPIO -#define DT_N_S_gpio_deadbeef_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_deadbeef, compatible, 0) #define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_deadbeef, compatible, 0) #define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_deadbeef, compatible, 0, __VA_ARGS__) #define DT_N_S_gpio_deadbeef_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_gpio_deadbeef, compatible, 0, __VA_ARGS__) #define DT_N_S_gpio_deadbeef_P_compatible_LEN 1 #define DT_N_S_gpio_deadbeef_P_compatible_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_reg {3735928559 /* 0xdeadbeef */, 4096 /* 0x1000 */} -#define DT_N_S_gpio_deadbeef_P_reg_IDX_0 3735928559 -#define DT_N_S_gpio_deadbeef_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_reg_IDX_1 4096 -#define DT_N_S_gpio_deadbeef_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_gpio_deadbeef_P_reg_EXISTS 1 #define DT_N_S_gpio_deadbeef_P_zephyr_deferred_init 0 #define DT_N_S_gpio_deadbeef_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_wakeup_source 0 +#define DT_N_S_gpio_deadbeef_P_wakeup_source_EXISTS 1 +#define DT_N_S_gpio_deadbeef_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_gpio_deadbeef_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp0_pa0_c @@ -5494,6 +5613,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FULL_NAME "adc1_inp0_pa0_c" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FULL_NAME_UNQUOTED adc1_inp0_pa0_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FULL_NAME_TOKEN adc1_inp0_pa0_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_FULL_NAME_UPPER_TOKEN ADC1_INP0_PA0_C /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -5524,11 +5646,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_EXISTS 1 @@ -5546,20 +5668,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_pinmux 16 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate "low-speed" @@ -5568,16 +5676,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp10_pc0 @@ -5593,6 +5713,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_FULL_NAME "adc1_inp10_pc0" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_FULL_NAME_UNQUOTED adc1_inp10_pc0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_FULL_NAME_TOKEN adc1_inp10_pc0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_FULL_NAME_UPPER_TOKEN ADC1_INP10_PC0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -5623,11 +5746,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_EXISTS 1 @@ -5645,20 +5768,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_pinmux 1040 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate "low-speed" @@ -5667,16 +5776,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp12_pc2 @@ -5692,6 +5813,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_FULL_NAME "adc1_inp12_pc2" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_FULL_NAME_UNQUOTED adc1_inp12_pc2 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_FULL_NAME_TOKEN adc1_inp12_pc2 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_FULL_NAME_UPPER_TOKEN ADC1_INP12_PC2 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -5722,11 +5846,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_EXISTS 1 @@ -5744,20 +5868,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_pinmux 1104 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate "low-speed" @@ -5766,16 +5876,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp13_pc3 @@ -5791,6 +5913,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_FULL_NAME "adc1_inp13_pc3" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_FULL_NAME_UNQUOTED adc1_inp13_pc3 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_FULL_NAME_TOKEN adc1_inp13_pc3 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_FULL_NAME_UPPER_TOKEN ADC1_INP13_PC3 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -5821,11 +5946,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_EXISTS 1 @@ -5843,20 +5968,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_pinmux 1136 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate "low-speed" @@ -5865,16 +5976,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp16_pa0 @@ -5890,6 +6013,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_FULL_NAME "adc1_inp16_pa0" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_FULL_NAME_UNQUOTED adc1_inp16_pa0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_FULL_NAME_TOKEN adc1_inp16_pa0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_FULL_NAME_UPPER_TOKEN ADC1_INP16_PA0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -5920,11 +6046,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_EXISTS 1 @@ -5942,20 +6068,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_pinmux 16 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate "low-speed" @@ -5964,16 +6076,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp18_pa4 @@ -5989,6 +6113,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FULL_NAME "adc1_inp18_pa4" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FULL_NAME_UNQUOTED adc1_inp18_pa4 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FULL_NAME_TOKEN adc1_inp18_pa4 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_FULL_NAME_UPPER_TOKEN ADC1_INP18_PA4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6019,11 +6146,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_EXISTS 1 @@ -6041,20 +6168,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_pinmux 144 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate "low-speed" @@ -6063,16 +6176,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp19_pa5 @@ -6088,6 +6213,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FULL_NAME "adc1_inp19_pa5" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FULL_NAME_UNQUOTED adc1_inp19_pa5 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FULL_NAME_TOKEN adc1_inp19_pa5 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_FULL_NAME_UPPER_TOKEN ADC1_INP19_PA5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6118,11 +6246,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_EXISTS 1 @@ -6140,20 +6268,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_pinmux 176 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate "low-speed" @@ -6162,16 +6276,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp1_pa1_c @@ -6187,6 +6313,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FULL_NAME "adc1_inp1_pa1_c" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FULL_NAME_UNQUOTED adc1_inp1_pa1_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FULL_NAME_TOKEN adc1_inp1_pa1_c +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_FULL_NAME_UPPER_TOKEN ADC1_INP1_PA1_C /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6217,11 +6346,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_EXISTS 1 @@ -6239,20 +6368,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_pinmux 48 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate "low-speed" @@ -6261,16 +6376,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp4_pc4 @@ -6286,6 +6413,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_FULL_NAME "adc1_inp4_pc4" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_FULL_NAME_UNQUOTED adc1_inp4_pc4 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_FULL_NAME_TOKEN adc1_inp4_pc4 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_FULL_NAME_UPPER_TOKEN ADC1_INP4_PC4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6316,11 +6446,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_EXISTS 1 @@ -6338,20 +6468,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_pinmux 1168 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate "low-speed" @@ -6360,16 +6476,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp5_pb1 @@ -6385,6 +6513,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_FULL_NAME "adc1_inp5_pb1" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_FULL_NAME_UNQUOTED adc1_inp5_pb1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_FULL_NAME_TOKEN adc1_inp5_pb1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_FULL_NAME_UPPER_TOKEN ADC1_INP5_PB1 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6415,11 +6546,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_EXISTS 1 @@ -6437,20 +6568,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_pinmux 560 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate "low-speed" @@ -6459,16 +6576,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp8_pc5 @@ -6484,6 +6613,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_FULL_NAME "adc1_inp8_pc5" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_FULL_NAME_UNQUOTED adc1_inp8_pc5 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_FULL_NAME_TOKEN adc1_inp8_pc5 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_FULL_NAME_UPPER_TOKEN ADC1_INP8_PC5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6514,11 +6646,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_EXISTS 1 @@ -6536,20 +6668,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_pinmux 1200 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate "low-speed" @@ -6558,16 +6676,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/adc1_inp9_pb0 @@ -6583,6 +6713,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_FULL_NAME "adc1_inp9_pb0" +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_FULL_NAME_UNQUOTED adc1_inp9_pb0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_FULL_NAME_TOKEN adc1_inp9_pb0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_FULL_NAME_UPPER_TOKEN ADC1_INP9_PB0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -6613,11 +6746,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_SUPPORTS_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_EXISTS 1 @@ -6635,20 +6768,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_pinmux 528 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate "low-speed" @@ -6657,16 +6776,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/adc@40022000 @@ -6685,6 +6816,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_FULL_NAME "adc@40022000" +#define DT_N_S_soc_S_adc_40022000_FULL_NAME_UNQUOTED adc@40022000 +#define DT_N_S_soc_S_adc_40022000_FULL_NAME_TOKEN adc_40022000 +#define DT_N_S_soc_S_adc_40022000_FULL_NAME_UPPER_TOKEN ADC_40022000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_adc_40022000_PARENT DT_N_S_soc @@ -6715,37 +6849,37 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 39, /* /soc/pin-controller@58020000/adc1_inp0_pa0_c */ \ - 40, /* /soc/pin-controller@58020000/adc1_inp10_pc0 */ \ - 41, /* /soc/pin-controller@58020000/adc1_inp12_pc2 */ \ - 42, /* /soc/pin-controller@58020000/adc1_inp13_pc3 */ \ - 43, /* /soc/pin-controller@58020000/adc1_inp16_pa0 */ \ - 44, /* /soc/pin-controller@58020000/adc1_inp18_pa4 */ \ - 45, /* /soc/pin-controller@58020000/adc1_inp19_pa5 */ \ - 46, /* /soc/pin-controller@58020000/adc1_inp1_pa1_c */ \ - 47, /* /soc/pin-controller@58020000/adc1_inp4_pc4 */ \ - 48, /* /soc/pin-controller@58020000/adc1_inp5_pb1 */ \ - 49, /* /soc/pin-controller@58020000/adc1_inp8_pc5 */ \ - 50, /* /soc/pin-controller@58020000/adc1_inp9_pb0 */ + 4, \ + 5, \ + 9, \ + 39, \ + 40, \ + 41, \ + 42, \ + 43, \ + 44, \ + 45, \ + 46, \ + 47, \ + 48, \ + 49, \ + 50, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 148, /* /soc/adc@40022000/channel@0 */ \ - 149, /* /soc/adc@40022000/channel@1 */ \ - 150, /* /soc/adc@40022000/channel@4 */ \ - 151, /* /soc/adc@40022000/channel@5 */ \ - 152, /* /soc/adc@40022000/channel@8 */ \ - 153, /* /soc/adc@40022000/channel@9 */ \ - 154, /* /soc/adc@40022000/channel@a */ \ - 155, /* /soc/adc@40022000/channel@c */ \ - 156, /* /soc/adc@40022000/channel@d */ \ - 157, /* /soc/adc@40022000/channel@10 */ \ - 158, /* /soc/adc@40022000/channel@12 */ \ - 159, /* /soc/adc@40022000/channel@13 */ + 93, \ + 151, \ + 152, \ + 153, \ + 154, \ + 155, \ + 156, \ + 157, \ + 158, \ + 159, \ + 160, \ + 161, \ + 162, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_adc_40022000_EXISTS 1 @@ -6755,8 +6889,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_REG_IDX_0_VAL_ADDRESS 1073881088 /* 0x40022000 */ -#define DT_N_S_soc_S_adc_40022000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_adc_40022000_REG_IDX_0_VAL_ADDRESS 1073881088 +#define DT_N_S_soc_S_adc_40022000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_adc_40022000_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_IRQ_NUM 1 @@ -6796,20 +6930,139 @@ #define DT_N_S_soc_S_adc_40022000_PINCTRL_NAME_default_IDX_11_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_P_wakeup_source 0 -#define DT_N_S_soc_S_adc_40022000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_adc_40022000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_reg {1073881088, 1024} +#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_0 1073881088 +#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_adc_40022000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bus 216 +#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bits 32 +#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, clocks, 0) +#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, clocks, 0) +#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_clocks_LEN 1 +#define DT_N_S_soc_S_adc_40022000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_interrupts {18, 0} +#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_0 18 +#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_adc_40022000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_IDX_0_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler 4 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_IDX_0_ENUM_VAL_4_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_vref_mv 3300 +#define DT_N_S_soc_S_adc_40022000_P_vref_mv_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_resolutions {8446476, 7725580, 6742540, 5497356, 4710924} +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_0 8446476 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_1 7725580 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_2 6742540 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_3 5497356 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_4 4710924 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 1) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 2) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 3) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 4) +#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 3) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 4) +#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 3, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 4, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, resolutions, 4, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_resolutions_LEN 5 +#define DT_N_S_soc_S_adc_40022000_P_resolutions_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times {2, 3, 9, 17, 33, 65, 388, 811} +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_0 2 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_1 3 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_2 9 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_3 17 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_4 33 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_5 65 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_6 388 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_7 811 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7) +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7) +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6, __VA_ARGS__) \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_LEN 8 +#define DT_N_S_soc_S_adc_40022000_P_sampling_times_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_IDX_0_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_status "okay" #define DT_N_S_soc_S_adc_40022000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_adc_40022000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_adc_40022000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_adc_40022000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_adc_40022000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_adc_40022000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_adc_40022000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_adc_40022000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_40022000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, status, 0) #define DT_N_S_soc_S_adc_40022000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, status, 0) #define DT_N_S_soc_S_adc_40022000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, status, 0, __VA_ARGS__) @@ -6817,43 +7070,23 @@ #define DT_N_S_soc_S_adc_40022000_P_status_LEN 1 #define DT_N_S_soc_S_adc_40022000_P_status_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_compatible {"st,stm32-adc"} +#define DT_N_S_soc_S_adc_40022000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_compatible_IDX_0 "st,stm32-adc" #define DT_N_S_soc_S_adc_40022000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc #define DT_N_S_soc_S_adc_40022000_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc #define DT_N_S_soc_S_adc_40022000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC -#define DT_N_S_soc_S_adc_40022000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, compatible, 0) #define DT_N_S_soc_S_adc_40022000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, compatible, 0) #define DT_N_S_soc_S_adc_40022000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022000_P_compatible_LEN 1 #define DT_N_S_soc_S_adc_40022000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_reg {1073881088 /* 0x40022000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_0 1073881088 -#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_adc_40022000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_0 18 -#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_adc_40022000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bus 216 -#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bits 32 -#define DT_N_S_soc_S_adc_40022000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, clocks, 0) -#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, clocks, 0) -#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_clocks_LEN 1 -#define DT_N_S_soc_S_adc_40022000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_adc_40022000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_wakeup_source 0 +#define DT_N_S_soc_S_adc_40022000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_adc_40022000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_IDX_0_EXISTS 1 @@ -6941,115 +7174,17 @@ #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_LEN 12 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, pinctrl_names, 0) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, pinctrl_names, 0) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_adc_40022000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_ENUM_IDX 0 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_ENUM_VAL_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_clock_source_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler 4 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_ENUM_IDX 2 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_ENUM_VAL_4_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_prescaler_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_vref_mv 3300 -#define DT_N_S_soc_S_adc_40022000_P_vref_mv_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_resolutions {8446476 /* 0x80e20c */, 7725580 /* 0x75e20c */, 6742540 /* 0x66e20c */, 5497356 /* 0x53e20c */, 4710924 /* 0x47e20c */} -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_0 8446476 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_1 7725580 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_2 6742540 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_3 5497356 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_4 4710924 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 1) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 2) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 3) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 4) -#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 1) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 2) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 3) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 4) -#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 1, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 2, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 3, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 4, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_resolutions_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, resolutions, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, resolutions, 4, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_resolutions_LEN 5 -#define DT_N_S_soc_S_adc_40022000_P_resolutions_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times {2 /* 0x2 */, 3 /* 0x3 */, 9 /* 0x9 */, 17 /* 0x11 */, 33 /* 0x21 */, 65 /* 0x41 */, 388 /* 0x184 */, 811 /* 0x32b */} -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_0 2 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_1 3 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_2 9 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_3 17 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_4 33 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_5 65 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_6 388 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_7 811 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7) -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7) -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6, __VA_ARGS__) \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022000, sampling_times, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 3, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 4, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 5, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 6, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_adc_40022000, sampling_times, 7, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_LEN 8 -#define DT_N_S_soc_S_adc_40022000_P_sampling_times_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_ENUM_IDX 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_ENUM_VAL_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_P_st_adc_sequencer_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usart2_rx_pd6 @@ -7065,6 +7200,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_FULL_NAME "usart2_rx_pd6" +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_FULL_NAME_UNQUOTED usart2_rx_pd6 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_FULL_NAME_TOKEN usart2_rx_pd6 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_FULL_NAME_UPPER_TOKEN USART2_RX_PD6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -7095,11 +7233,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_SUPPORTS_ORDS \ - 55, /* /soc/serial@40004400 */ + 55, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_EXISTS 1 @@ -7117,20 +7255,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_pinmux 1735 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate "low-speed" @@ -7139,16 +7263,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usart2_tx_pd5 @@ -7164,6 +7300,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_FULL_NAME "usart2_tx_pd5" +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_FULL_NAME_UNQUOTED usart2_tx_pd5 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_FULL_NAME_TOKEN usart2_tx_pd5 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_FULL_NAME_UPPER_TOKEN USART2_TX_PD5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -7194,11 +7333,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_SUPPORTS_ORDS \ - 55, /* /soc/serial@40004400 */ + 55, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_EXISTS 1 @@ -7216,20 +7355,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_pinmux 1703 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate "low-speed" @@ -7238,16 +7363,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/rcc@58024400/reset-controller @@ -7266,6 +7403,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_FULL_NAME "reset-controller" +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_FULL_NAME_UNQUOTED reset-controller +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_FULL_NAME_TOKEN reset_controller +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_FULL_NAME_UPPER_TOKEN RESET_CONTROLLER /* Node parent (/soc/rcc@58024400) identifier: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_PARENT DT_N_S_soc_S_rcc_58024400 @@ -7296,36 +7436,37 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_SUPPORTS_ORDS \ - 55, /* /soc/serial@40004400 */ \ - 58, /* /soc/serial@40004c00 */ \ - 61, /* /soc/serial@40011000 */ \ - 64, /* /soc/serial@40011400 */ \ - 85, /* /soc/timers@40010000 */ \ - 124, /* /soc/dsihost@50000000 */ \ - 133, /* /soc/sdmmc@48022400 */ \ - 134, /* /soc/sdmmc@52007000 */ \ - 135, /* /soc/serial@40004800 */ \ - 136, /* /soc/serial@40005000 */ \ - 137, /* /soc/serial@40007c00 */ \ - 138, /* /soc/serial@58000c00 */ \ - 248, /* /soc/serial@40007800 */ \ - 251, /* /soc/timers@40000000 */ \ - 254, /* /soc/timers@40000400 */ \ - 257, /* /soc/timers@40000800 */ \ - 260, /* /soc/timers@40000c00 */ \ - 263, /* /soc/timers@40001000 */ \ - 265, /* /soc/timers@40001400 */ \ - 267, /* /soc/timers@40001800 */ \ - 270, /* /soc/timers@40001c00 */ \ - 273, /* /soc/timers@40002000 */ \ - 277, /* /soc/timers@40010400 */ \ - 279, /* /soc/timers@40014000 */ \ - 282, /* /soc/timers@40014400 */ \ - 285, /* /soc/timers@40014800 */ + 55, \ + 58, \ + 61, \ + 64, \ + 85, \ + 124, \ + 127, \ + 136, \ + 137, \ + 138, \ + 139, \ + 140, \ + 141, \ + 251, \ + 254, \ + 257, \ + 260, \ + 263, \ + 266, \ + 268, \ + 270, \ + 273, \ + 276, \ + 280, \ + 282, \ + 285, \ + 288, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_EXISTS 1 @@ -7349,16 +7490,14 @@ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_wakeup_source 0 -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_set_bit_to_deassert 0 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_set_bit_to_deassert_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible {"st,stm32-rcc-rctl"} +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_IDX_0 "st,stm32-rcc-rctl" #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rcc-rctl #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_IDX_0_STRING_TOKEN st_stm32_rcc_rctl #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RCC_RCTL -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, compatible, 0) #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, compatible, 0) #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, compatible, 0, __VA_ARGS__) @@ -7367,8 +7506,10 @@ #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_compatible_EXISTS 1 #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_set_bit_to_deassert 0 -#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_set_bit_to_deassert_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_wakeup_source 0 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_rcc_58024400_S_reset_controller_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/serial@40004400 @@ -7387,6 +7528,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40004400_FULL_NAME "serial@40004400" +#define DT_N_S_soc_S_serial_40004400_FULL_NAME_UNQUOTED serial@40004400 +#define DT_N_S_soc_S_serial_40004400_FULL_NAME_TOKEN serial_40004400 +#define DT_N_S_soc_S_serial_40004400_FULL_NAME_UPPER_TOKEN SERIAL_40004400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40004400_PARENT DT_N_S_soc @@ -7417,16 +7561,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40004400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 52, /* /soc/pin-controller@58020000/usart2_rx_pd6 */ \ - 53, /* /soc/pin-controller@58020000/usart2_tx_pd5 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 52, \ + 53, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40004400_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40004400_EXISTS 1 @@ -7437,8 +7581,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40004400_REG_NUM 1 #define DT_N_S_soc_S_serial_40004400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_ADDRESS 1073759232 /* 0x40004400 */ -#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_ADDRESS 1073759232 +#define DT_N_S_soc_S_serial_40004400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40004400_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40004400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40004400_IRQ_NUM 1 @@ -7473,59 +7617,12 @@ #define DT_N_S_soc_S_serial_40004400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40004400_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40004400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_status "okay" -#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_serial_40004400_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_serial_40004400_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_serial_40004400_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, status, 0) -#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, status, 0) -#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004400_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40004400_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_compatible {"st,stm32-usart", "st,stm32-uart"} -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0 "st,stm32-usart" -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) \ - fn(DT_N_S_soc_S_serial_40004400, compatible, 1) -#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40004400, compatible, 1) -#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004400_P_compatible_LEN 2 -#define DT_N_S_soc_S_serial_40004400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_reg {1073759232 /* 0x40004400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0 1073759232 +#define DT_N_S_soc_S_serial_40004400_P_reg {1073759232, 1024} #define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_0 1073759232 #define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40004400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_interrupts {38 /* 0x26 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0 38 -#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40004400_P_clocks_IDX_0_VAL_bus 232 @@ -7538,12 +7635,26 @@ #define DT_N_S_soc_S_serial_40004400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004400_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40004400_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_current_speed 115200 -#define DT_N_S_soc_S_serial_40004400_P_current_speed_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id 4625 +#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, resets, 0) +#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, resets, 0) +#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004400_P_resets_LEN 1 +#define DT_N_S_soc_S_serial_40004400_P_resets_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_interrupts {38, 0} +#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_0 38 +#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40004400_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_single_wire 0 +#define DT_N_S_soc_S_serial_40004400_P_single_wire_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap 0 +#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_0_IDX_0_EXISTS 1 @@ -7561,35 +7672,17 @@ #define DT_N_S_soc_S_serial_40004400_P_pinctrl_0_LEN 2 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_serial_40004400_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id 4625 -#define DT_N_S_soc_S_serial_40004400_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, resets, 0) -#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, resets, 0) -#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004400_P_resets_LEN 1 -#define DT_N_S_soc_S_serial_40004400_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40004400_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40004400_P_rx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_single_wire 0 -#define DT_N_S_soc_S_serial_40004400_P_single_wire_EXISTS 1 -#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap 0 -#define DT_N_S_soc_S_serial_40004400_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_de_enable 0 #define DT_N_S_soc_S_serial_40004400_P_de_enable_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_de_assert_time 0 @@ -7600,6 +7693,55 @@ #define DT_N_S_soc_S_serial_40004400_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40004400_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40004400_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_current_speed 115200 +#define DT_N_S_soc_S_serial_40004400_P_current_speed_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40004400_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_status "okay" +#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_serial_40004400_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_serial_40004400_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_serial_40004400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, status, 0) +#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, status, 0) +#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004400_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40004400_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_compatible {"st,stm32-usart", "st,stm32-uart"} +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0 "st,stm32-usart" +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40004400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) \ + fn(DT_N_S_soc_S_serial_40004400, compatible, 1) +#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004400, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40004400, compatible, 1) +#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40004400, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004400_P_compatible_LEN 2 +#define DT_N_S_soc_S_serial_40004400_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40004400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40004400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40004400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40004400_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40004400_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40004400_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/uart4_rx_pi9 @@ -7615,6 +7757,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_FULL_NAME "uart4_rx_pi9" +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_FULL_NAME_UNQUOTED uart4_rx_pi9 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_FULL_NAME_TOKEN uart4_rx_pi9 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_FULL_NAME_UPPER_TOKEN UART4_RX_PI9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -7645,11 +7790,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_SUPPORTS_ORDS \ - 58, /* /soc/serial@40004c00 */ + 58, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_EXISTS 1 @@ -7667,20 +7812,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_pinmux 4392 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate "low-speed" @@ -7689,16 +7820,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/uart4_tx_ph13 @@ -7714,6 +7857,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_FULL_NAME "uart4_tx_ph13" +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_FULL_NAME_UNQUOTED uart4_tx_ph13 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_FULL_NAME_TOKEN uart4_tx_ph13 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_FULL_NAME_UPPER_TOKEN UART4_TX_PH13 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -7744,11 +7890,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_SUPPORTS_ORDS \ - 58, /* /soc/serial@40004c00 */ + 58, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_EXISTS 1 @@ -7766,20 +7912,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_pinmux 4008 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate "low-speed" @@ -7788,16 +7920,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13_P_output_high_EXISTS 1 /* * Devicetree node: /soc/serial@40004c00 @@ -7816,6 +7960,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40004c00_FULL_NAME "serial@40004c00" +#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_UNQUOTED serial@40004c00 +#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_TOKEN serial_40004c00 +#define DT_N_S_soc_S_serial_40004c00_FULL_NAME_UPPER_TOKEN SERIAL_40004C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40004c00_PARENT DT_N_S_soc @@ -7846,16 +7993,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40004c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ \ - 56, /* /soc/pin-controller@58020000/uart4_rx_pi9 */ \ - 57, /* /soc/pin-controller@58020000/uart4_tx_ph13 */ + 4, \ + 5, \ + 9, \ + 54, \ + 56, \ + 57, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40004c00_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40004c00_EXISTS 1 @@ -7865,8 +8012,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40004c00_REG_NUM 1 #define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_ADDRESS 1073761280 /* 0x40004c00 */ -#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_ADDRESS 1073761280 +#define DT_N_S_soc_S_serial_40004c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40004c00_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40004c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40004c00_IRQ_NUM 1 @@ -7896,50 +8043,12 @@ #define DT_N_S_soc_S_serial_40004c00_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_status "okay" -#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_serial_40004c00_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_serial_40004c00_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, status, 0) -#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, status, 0) -#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004c00_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40004c00_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_compatible {"st,stm32-uart"} -#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0) -#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0) -#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004c00_P_compatible_LEN 1 -#define DT_N_S_soc_S_serial_40004c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_reg {1073761280 /* 0x40004c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0 1073761280 +#define DT_N_S_soc_S_serial_40004c00_P_reg {1073761280, 1024} #define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_0 1073761280 #define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40004c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_interrupts {52 /* 0x34 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0 52 -#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40004c00_P_clocks_IDX_0_VAL_bus 232 @@ -7952,12 +8061,26 @@ #define DT_N_S_soc_S_serial_40004c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004c00_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40004c00_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_current_speed 115200 -#define DT_N_S_soc_S_serial_40004c00_P_current_speed_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id 4627 +#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, resets, 0) +#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, resets, 0) +#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004c00_P_resets_LEN 1 +#define DT_N_S_soc_S_serial_40004c00_P_resets_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_interrupts {52, 0} +#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_0 52 +#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40004c00_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_single_wire 0 +#define DT_N_S_soc_S_serial_40004c00_P_single_wire_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap 0 +#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_0_IDX_0_EXISTS 1 @@ -7975,35 +8098,17 @@ #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_0_LEN 2 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_serial_40004c00_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id 4627 -#define DT_N_S_soc_S_serial_40004c00_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, resets, 0) -#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, resets, 0) -#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004c00_P_resets_LEN 1 -#define DT_N_S_soc_S_serial_40004c00_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40004c00_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40004c00_P_rx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_single_wire 0 -#define DT_N_S_soc_S_serial_40004c00_P_single_wire_EXISTS 1 -#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap 0 -#define DT_N_S_soc_S_serial_40004c00_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_de_enable 0 #define DT_N_S_soc_S_serial_40004c00_P_de_enable_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_de_assert_time 0 @@ -8014,6 +8119,46 @@ #define DT_N_S_soc_S_serial_40004c00_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40004c00_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40004c00_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_current_speed 115200 +#define DT_N_S_soc_S_serial_40004c00_P_current_speed_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40004c00_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_status "okay" +#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_serial_40004c00_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_serial_40004c00_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, status, 0) +#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, status, 0) +#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004c00_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40004c00_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_compatible {"st,stm32-uart"} +#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40004c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0) +#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0) +#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004c00_P_compatible_LEN 1 +#define DT_N_S_soc_S_serial_40004c00_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40004c00_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40004c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40004c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40004c00_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40004c00_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40004c00_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usart1_rx_pb7 @@ -8029,6 +8174,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_FULL_NAME "usart1_rx_pb7" +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_FULL_NAME_UNQUOTED usart1_rx_pb7 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_FULL_NAME_TOKEN usart1_rx_pb7 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_FULL_NAME_UPPER_TOKEN USART1_RX_PB7 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -8059,11 +8207,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_SUPPORTS_ORDS \ - 61, /* /soc/serial@40011000 */ + 61, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_EXISTS 1 @@ -8081,20 +8229,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_pinmux 743 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate "low-speed" @@ -8103,16 +8237,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usart1_tx_pa9 @@ -8128,6 +8274,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_FULL_NAME "usart1_tx_pa9" +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_FULL_NAME_UNQUOTED usart1_tx_pa9 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_FULL_NAME_TOKEN usart1_tx_pa9 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_FULL_NAME_UPPER_TOKEN USART1_TX_PA9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -8158,11 +8307,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_SUPPORTS_ORDS \ - 61, /* /soc/serial@40011000 */ + 61, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_EXISTS 1 @@ -8180,20 +8329,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_pinmux 295 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate "low-speed" @@ -8202,16 +8337,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/serial@40011000 @@ -8230,6 +8377,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40011000_FULL_NAME "serial@40011000" +#define DT_N_S_soc_S_serial_40011000_FULL_NAME_UNQUOTED serial@40011000 +#define DT_N_S_soc_S_serial_40011000_FULL_NAME_TOKEN serial_40011000 +#define DT_N_S_soc_S_serial_40011000_FULL_NAME_UPPER_TOKEN SERIAL_40011000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40011000_PARENT DT_N_S_soc @@ -8260,16 +8410,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40011000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ \ - 59, /* /soc/pin-controller@58020000/usart1_rx_pb7 */ \ - 60, /* /soc/pin-controller@58020000/usart1_tx_pa9 */ + 4, \ + 5, \ + 9, \ + 54, \ + 59, \ + 60, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40011000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40011000_EXISTS 1 @@ -8281,8 +8431,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40011000_REG_NUM 1 #define DT_N_S_soc_S_serial_40011000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_VAL_ADDRESS 1073811456 /* 0x40011000 */ -#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_VAL_ADDRESS 1073811456 +#define DT_N_S_soc_S_serial_40011000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40011000_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40011000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40011000_IRQ_NUM 1 @@ -8317,59 +8467,12 @@ #define DT_N_S_soc_S_serial_40011000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40011000_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40011000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40011000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_status "okay" -#define DT_N_S_soc_S_serial_40011000_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_serial_40011000_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_serial_40011000_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_serial_40011000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_serial_40011000_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, status, 0) -#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, status, 0) -#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011000_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40011000_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_compatible {"st,stm32-usart", "st,stm32-uart"} -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0 "st,stm32-usart" -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, compatible, 0) \ - fn(DT_N_S_soc_S_serial_40011000, compatible, 1) -#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40011000, compatible, 1) -#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_serial_40011000, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40011000, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011000_P_compatible_LEN 2 -#define DT_N_S_soc_S_serial_40011000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_reg {1073811456 /* 0x40011000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_0 1073811456 +#define DT_N_S_soc_S_serial_40011000_P_reg {1073811456, 1024} #define DT_N_S_soc_S_serial_40011000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_0 1073811456 #define DT_N_S_soc_S_serial_40011000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40011000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_interrupts {37 /* 0x25 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_0 37 -#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40011000_P_clocks_IDX_0_VAL_bus 240 @@ -8382,12 +8485,26 @@ #define DT_N_S_soc_S_serial_40011000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40011000_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40011000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40011000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_current_speed 115200 -#define DT_N_S_soc_S_serial_40011000_P_current_speed_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40011000_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_VAL_id 4868 +#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, resets, 0) +#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, resets, 0) +#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011000_P_resets_LEN 1 +#define DT_N_S_soc_S_serial_40011000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_interrupts {37, 0} +#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_0 37 +#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40011000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_single_wire 0 +#define DT_N_S_soc_S_serial_40011000_P_single_wire_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_tx_rx_swap 0 +#define DT_N_S_soc_S_serial_40011000_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_0_IDX_0_EXISTS 1 @@ -8405,35 +8522,17 @@ #define DT_N_S_soc_S_serial_40011000_P_pinctrl_0_LEN 2 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_serial_40011000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_VAL_id 4868 -#define DT_N_S_soc_S_serial_40011000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, resets, 0) -#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, resets, 0) -#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011000_P_resets_LEN 1 -#define DT_N_S_soc_S_serial_40011000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40011000_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40011000_P_rx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_single_wire 0 -#define DT_N_S_soc_S_serial_40011000_P_single_wire_EXISTS 1 -#define DT_N_S_soc_S_serial_40011000_P_tx_rx_swap 0 -#define DT_N_S_soc_S_serial_40011000_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_de_enable 0 #define DT_N_S_soc_S_serial_40011000_P_de_enable_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_de_assert_time 0 @@ -8444,6 +8543,55 @@ #define DT_N_S_soc_S_serial_40011000_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40011000_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40011000_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_current_speed 115200 +#define DT_N_S_soc_S_serial_40011000_P_current_speed_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40011000_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_status "okay" +#define DT_N_S_soc_S_serial_40011000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_serial_40011000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_serial_40011000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_serial_40011000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, status, 0) +#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, status, 0) +#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011000_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40011000_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_compatible {"st,stm32-usart", "st,stm32-uart"} +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0 "st,stm32-usart" +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40011000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011000, compatible, 0) \ + fn(DT_N_S_soc_S_serial_40011000, compatible, 1) +#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40011000, compatible, 1) +#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011000, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_serial_40011000, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40011000, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011000_P_compatible_LEN 2 +#define DT_N_S_soc_S_serial_40011000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40011000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40011000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40011000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40011000_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40011000_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40011000_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usart6_rx_pc7 @@ -8459,6 +8607,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_FULL_NAME "usart6_rx_pc7" +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_FULL_NAME_UNQUOTED usart6_rx_pc7 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_FULL_NAME_TOKEN usart6_rx_pc7 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_FULL_NAME_UPPER_TOKEN USART6_RX_PC7 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -8489,11 +8640,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_SUPPORTS_ORDS \ - 64, /* /soc/serial@40011400 */ + 64, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_EXISTS 1 @@ -8511,20 +8662,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_pinmux 1255 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate "low-speed" @@ -8533,16 +8670,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usart6_tx_pg14 @@ -8558,6 +8707,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_FULL_NAME "usart6_tx_pg14" +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_FULL_NAME_UNQUOTED usart6_tx_pg14 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_FULL_NAME_TOKEN usart6_tx_pg14 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_FULL_NAME_UPPER_TOKEN USART6_TX_PG14 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -8588,11 +8740,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_SUPPORTS_ORDS \ - 64, /* /soc/serial@40011400 */ + 64, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_EXISTS 1 @@ -8610,20 +8762,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_pinmux 3527 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate "low-speed" @@ -8632,16 +8770,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14_P_output_high_EXISTS 1 /* * Devicetree node: /soc/serial@40011400 @@ -8660,6 +8810,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40011400_FULL_NAME "serial@40011400" +#define DT_N_S_soc_S_serial_40011400_FULL_NAME_UNQUOTED serial@40011400 +#define DT_N_S_soc_S_serial_40011400_FULL_NAME_TOKEN serial_40011400 +#define DT_N_S_soc_S_serial_40011400_FULL_NAME_UPPER_TOKEN SERIAL_40011400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40011400_PARENT DT_N_S_soc @@ -8690,16 +8843,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40011400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ \ - 62, /* /soc/pin-controller@58020000/usart6_rx_pc7 */ \ - 63, /* /soc/pin-controller@58020000/usart6_tx_pg14 */ + 4, \ + 5, \ + 9, \ + 54, \ + 62, \ + 63, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40011400_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40011400_EXISTS 1 @@ -8710,8 +8863,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40011400_REG_NUM 1 #define DT_N_S_soc_S_serial_40011400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_VAL_ADDRESS 1073812480 /* 0x40011400 */ -#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_VAL_ADDRESS 1073812480 +#define DT_N_S_soc_S_serial_40011400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40011400_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40011400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40011400_IRQ_NUM 1 @@ -8746,59 +8899,12 @@ #define DT_N_S_soc_S_serial_40011400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40011400_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40011400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40011400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_status "okay" -#define DT_N_S_soc_S_serial_40011400_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_serial_40011400_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_serial_40011400_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_serial_40011400_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_serial_40011400_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, status, 0) -#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, status, 0) -#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011400_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40011400_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_compatible {"st,stm32-usart", "st,stm32-uart"} -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0 "st,stm32-usart" -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, compatible, 0) \ - fn(DT_N_S_soc_S_serial_40011400, compatible, 1) -#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40011400, compatible, 1) -#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_serial_40011400, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40011400, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011400_P_compatible_LEN 2 -#define DT_N_S_soc_S_serial_40011400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_reg {1073812480 /* 0x40011400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_0 1073812480 +#define DT_N_S_soc_S_serial_40011400_P_reg {1073812480, 1024} #define DT_N_S_soc_S_serial_40011400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_0 1073812480 #define DT_N_S_soc_S_serial_40011400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40011400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_interrupts {71 /* 0x47 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_0 71 -#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40011400_P_clocks_IDX_0_VAL_bus 240 @@ -8811,12 +8917,26 @@ #define DT_N_S_soc_S_serial_40011400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40011400_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40011400_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40011400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_current_speed 115200 -#define DT_N_S_soc_S_serial_40011400_P_current_speed_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40011400_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_VAL_id 4869 +#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, resets, 0) +#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, resets, 0) +#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011400_P_resets_LEN 1 +#define DT_N_S_soc_S_serial_40011400_P_resets_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_interrupts {71, 0} +#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_0 71 +#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40011400_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_single_wire 0 +#define DT_N_S_soc_S_serial_40011400_P_single_wire_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_tx_rx_swap 0 +#define DT_N_S_soc_S_serial_40011400_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_IDX_0_EXISTS 1 @@ -8834,35 +8954,17 @@ #define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_LEN 2 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_serial_40011400_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_VAL_id 4869 -#define DT_N_S_soc_S_serial_40011400_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, resets, 0) -#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, resets, 0) -#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40011400_P_resets_LEN 1 -#define DT_N_S_soc_S_serial_40011400_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40011400_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40011400_P_rx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_single_wire 0 -#define DT_N_S_soc_S_serial_40011400_P_single_wire_EXISTS 1 -#define DT_N_S_soc_S_serial_40011400_P_tx_rx_swap 0 -#define DT_N_S_soc_S_serial_40011400_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_de_enable 0 #define DT_N_S_soc_S_serial_40011400_P_de_enable_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_de_assert_time 0 @@ -8873,6 +8975,55 @@ #define DT_N_S_soc_S_serial_40011400_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40011400_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40011400_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_current_speed 115200 +#define DT_N_S_soc_S_serial_40011400_P_current_speed_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40011400_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_status "okay" +#define DT_N_S_soc_S_serial_40011400_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_serial_40011400_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_serial_40011400_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_serial_40011400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, status, 0) +#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, status, 0) +#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011400_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40011400_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_compatible {"st,stm32-usart", "st,stm32-uart"} +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0 "st,stm32-usart" +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40011400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40011400, compatible, 0) \ + fn(DT_N_S_soc_S_serial_40011400, compatible, 1) +#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40011400, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40011400, compatible, 1) +#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40011400, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_serial_40011400, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40011400, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40011400, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40011400_P_compatible_LEN 2 +#define DT_N_S_soc_S_serial_40011400_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40011400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40011400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40011400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40011400_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40011400_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40011400_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi1_miso_pg9 @@ -8888,6 +9039,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_FULL_NAME "spi1_miso_pg9" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_FULL_NAME_UNQUOTED spi1_miso_pg9 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_FULL_NAME_TOKEN spi1_miso_pg9 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_FULL_NAME_UPPER_TOKEN SPI1_MISO_PG9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -8918,11 +9072,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_SUPPORTS_ORDS \ - 69, /* /soc/spi@40013000 */ + 69, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_EXISTS 1 @@ -8940,20 +9094,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_down 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_pinmux 3365 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate "low-speed" @@ -8962,16 +9102,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_down 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi1_mosi_pd7 @@ -8987,6 +9139,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_FULL_NAME "spi1_mosi_pd7" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_FULL_NAME_UNQUOTED spi1_mosi_pd7 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_FULL_NAME_TOKEN spi1_mosi_pd7 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_FULL_NAME_UPPER_TOKEN SPI1_MOSI_PD7 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9017,11 +9172,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_SUPPORTS_ORDS \ - 69, /* /soc/spi@40013000 */ + 69, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_EXISTS 1 @@ -9039,20 +9194,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_down 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_pinmux 1765 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate "low-speed" @@ -9061,16 +9202,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_down 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi1_nss_pa4 @@ -9086,6 +9239,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_FULL_NAME "spi1_nss_pa4" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_FULL_NAME_UNQUOTED spi1_nss_pa4 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_FULL_NAME_TOKEN spi1_nss_pa4 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_FULL_NAME_UPPER_TOKEN SPI1_NSS_PA4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9116,11 +9272,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_SUPPORTS_ORDS \ - 69, /* /soc/spi@40013000 */ + 69, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_EXISTS 1 @@ -9138,20 +9294,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_pinmux 133 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate "low-speed" @@ -9160,16 +9302,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi1_sck_pb3 @@ -9185,6 +9339,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_FULL_NAME "spi1_sck_pb3" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_FULL_NAME_UNQUOTED spi1_sck_pb3 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_FULL_NAME_TOKEN spi1_sck_pb3 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_FULL_NAME_UPPER_TOKEN SPI1_SCK_PB3 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9215,11 +9372,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_SUPPORTS_ORDS \ - 69, /* /soc/spi@40013000 */ + 69, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_EXISTS 1 @@ -9237,20 +9394,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_down 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_pinmux 613 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate "very-high-speed" @@ -9259,16 +9402,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_down 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3_P_output_high_EXISTS 1 /* * Devicetree node: /soc/spi@40013000 @@ -9287,6 +9442,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_spi_40013000_FULL_NAME "spi@40013000" +#define DT_N_S_soc_S_spi_40013000_FULL_NAME_UNQUOTED spi@40013000 +#define DT_N_S_soc_S_spi_40013000_FULL_NAME_TOKEN spi_40013000 +#define DT_N_S_soc_S_spi_40013000_FULL_NAME_UPPER_TOKEN SPI_40013000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spi_40013000_PARENT DT_N_S_soc @@ -9317,17 +9475,17 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40013000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 65, /* /soc/pin-controller@58020000/spi1_miso_pg9 */ \ - 66, /* /soc/pin-controller@58020000/spi1_mosi_pd7 */ \ - 67, /* /soc/pin-controller@58020000/spi1_nss_pa4 */ \ - 68, /* /soc/pin-controller@58020000/spi1_sck_pb3 */ + 4, \ + 5, \ + 9, \ + 65, \ + 66, \ + 67, \ + 68, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40013000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_spi_40013000_EXISTS 1 @@ -9339,8 +9497,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spi_40013000_REG_NUM 1 #define DT_N_S_soc_S_spi_40013000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 /* 0x40013000 */ -#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 +#define DT_N_S_soc_S_spi_40013000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_spi_40013000_RANGES_NUM 0 #define DT_N_S_soc_S_spi_40013000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spi_40013000_IRQ_NUM 1 @@ -9382,20 +9540,74 @@ #define DT_N_S_soc_S_spi_40013000_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7 /* Generic property macros: */ -#define DT_N_S_soc_S_spi_40013000_P_wakeup_source 0 -#define DT_N_S_soc_S_spi_40013000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_midi_clock 0 +#define DT_N_S_soc_S_spi_40013000_P_midi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_mssi_clock 0 +#define DT_N_S_soc_S_spi_40013000_P_mssi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_fifo_enable 0 +#define DT_N_S_soc_S_spi_40013000_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_reg {1073819648, 1024} +#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0 1073819648 +#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_spi_40013000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_interrupts {35, 0} +#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0 35 +#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_spi_40013000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2) \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_LEN 4 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_status "okay" #define DT_N_S_soc_S_spi_40013000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_spi_40013000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_spi_40013000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_spi_40013000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_spi_40013000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_spi_40013000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_spi_40013000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, status, 0) #define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, status, 0) #define DT_N_S_soc_S_spi_40013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, status, 0, __VA_ARGS__) @@ -9403,21 +9615,21 @@ #define DT_N_S_soc_S_spi_40013000_P_status_LEN 1 #define DT_N_S_soc_S_spi_40013000_P_status_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_compatible {"st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"} +#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0 "st,stm32h7-spi" #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-spi #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_spi #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_SPI -#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1 "st,stm32-spi-fifo" #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi-fifo #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi_fifo #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO -#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_2 "st,stm32-spi" #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_2_STRING_UNQUOTED st,stm32-spi #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_2_STRING_TOKEN st_stm32_spi #define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_2_STRING_UPPER_TOKEN ST_STM32_SPI -#define DT_N_S_soc_S_spi_40013000_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, compatible, 0) \ fn(DT_N_S_soc_S_spi_40013000, compatible, 1) \ fn(DT_N_S_soc_S_spi_40013000, compatible, 2) @@ -9432,18 +9644,6 @@ fn(DT_N_S_soc_S_spi_40013000, compatible, 2, __VA_ARGS__) #define DT_N_S_soc_S_spi_40013000_P_compatible_LEN 3 #define DT_N_S_soc_S_spi_40013000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_reg {1073819648 /* 0x40013000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0 1073819648 -#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_spi_40013000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_interrupts {35 /* 0x23 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0 35 -#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_spi_40013000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_spi_40013000_P_clocks_IDX_0_VAL_bus 240 @@ -9468,54 +9668,10 @@ #define DT_N_S_soc_S_spi_40013000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_spi_40013000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spi_40013000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2) \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__) \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40013000, pinctrl_0, 3, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_LEN 4 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40013000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_spi_40013000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_midi_clock 0 -#define DT_N_S_soc_S_spi_40013000_P_midi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_mssi_clock 0 -#define DT_N_S_soc_S_spi_40013000_P_mssi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40013000_P_fifo_enable 0 -#define DT_N_S_soc_S_spi_40013000_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_wakeup_source 0 +#define DT_N_S_soc_S_spi_40013000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_spi_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi5_miso_pj11 @@ -9531,6 +9687,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_FULL_NAME "spi5_miso_pj11" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_FULL_NAME_UNQUOTED spi5_miso_pj11 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_FULL_NAME_TOKEN spi5_miso_pj11 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_FULL_NAME_UPPER_TOKEN SPI5_MISO_PJ11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9561,11 +9720,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_SUPPORTS_ORDS \ - 74, /* /soc/spi@40015000 */ + 74, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_EXISTS 1 @@ -9583,20 +9742,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_down 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_pinmux 4965 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate "low-speed" @@ -9605,16 +9750,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_down 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi5_mosi_pj10 @@ -9630,6 +9787,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_FULL_NAME "spi5_mosi_pj10" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_FULL_NAME_UNQUOTED spi5_mosi_pj10 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_FULL_NAME_TOKEN spi5_mosi_pj10 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_FULL_NAME_UPPER_TOKEN SPI5_MOSI_PJ10 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9660,11 +9820,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_SUPPORTS_ORDS \ - 74, /* /soc/spi@40015000 */ + 74, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_EXISTS 1 @@ -9682,20 +9842,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_down 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_pinmux 4933 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate "low-speed" @@ -9704,16 +9850,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_down 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi5_nss_pk1 @@ -9729,6 +9887,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_FULL_NAME "spi5_nss_pk1" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_FULL_NAME_UNQUOTED spi5_nss_pk1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_FULL_NAME_TOKEN spi5_nss_pk1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_FULL_NAME_UPPER_TOKEN SPI5_NSS_PK1 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9759,11 +9920,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_SUPPORTS_ORDS \ - 74, /* /soc/spi@40015000 */ + 74, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_EXISTS 1 @@ -9781,20 +9942,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_pinmux 5157 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate "low-speed" @@ -9803,16 +9950,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/spi5_sck_ph6 @@ -9828,6 +9987,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_FULL_NAME "spi5_sck_ph6" +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_FULL_NAME_UNQUOTED spi5_sck_ph6 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_FULL_NAME_TOKEN spi5_sck_ph6 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_FULL_NAME_UPPER_TOKEN SPI5_SCK_PH6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -9858,11 +10020,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_SUPPORTS_ORDS \ - 74, /* /soc/spi@40015000 */ + 74, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_EXISTS 1 @@ -9880,20 +10042,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_down 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_pinmux 3781 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate "very-high-speed" @@ -9902,16 +10050,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_down 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/spi@40015000 @@ -9930,6 +10090,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_spi_40015000_FULL_NAME "spi@40015000" +#define DT_N_S_soc_S_spi_40015000_FULL_NAME_UNQUOTED spi@40015000 +#define DT_N_S_soc_S_spi_40015000_FULL_NAME_TOKEN spi_40015000 +#define DT_N_S_soc_S_spi_40015000_FULL_NAME_UPPER_TOKEN SPI_40015000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spi_40015000_PARENT DT_N_S_soc @@ -9960,17 +10123,17 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40015000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 70, /* /soc/pin-controller@58020000/spi5_miso_pj11 */ \ - 71, /* /soc/pin-controller@58020000/spi5_mosi_pj10 */ \ - 72, /* /soc/pin-controller@58020000/spi5_nss_pk1 */ \ - 73, /* /soc/pin-controller@58020000/spi5_sck_ph6 */ + 4, \ + 5, \ + 9, \ + 70, \ + 71, \ + 72, \ + 73, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40015000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_spi_40015000_EXISTS 1 @@ -9983,8 +10146,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spi_40015000_REG_NUM 1 #define DT_N_S_soc_S_spi_40015000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_VAL_ADDRESS 1073827840 /* 0x40015000 */ -#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_VAL_ADDRESS 1073827840 +#define DT_N_S_soc_S_spi_40015000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_spi_40015000_RANGES_NUM 0 #define DT_N_S_soc_S_spi_40015000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spi_40015000_IRQ_NUM 1 @@ -10026,20 +10189,74 @@ #define DT_N_S_soc_S_spi_40015000_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10 /* Generic property macros: */ -#define DT_N_S_soc_S_spi_40015000_P_wakeup_source 0 -#define DT_N_S_soc_S_spi_40015000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_spi_40015000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_midi_clock 0 +#define DT_N_S_soc_S_spi_40015000_P_midi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_mssi_clock 0 +#define DT_N_S_soc_S_spi_40015000_P_mssi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_fifo_enable 0 +#define DT_N_S_soc_S_spi_40015000_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_reg {1073827840, 1024} +#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_0 1073827840 +#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_spi_40015000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_interrupts {85, 0} +#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_0 85 +#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_spi_40015000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1) \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2) \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_LEN 4 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_status "okay" #define DT_N_S_soc_S_spi_40015000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_spi_40015000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_spi_40015000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_spi_40015000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_spi_40015000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_spi_40015000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_spi_40015000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_spi_40015000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_spi_40015000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, status, 0) #define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, status, 0) #define DT_N_S_soc_S_spi_40015000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, status, 0, __VA_ARGS__) @@ -10047,21 +10264,21 @@ #define DT_N_S_soc_S_spi_40015000_P_status_LEN 1 #define DT_N_S_soc_S_spi_40015000_P_status_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_compatible {"st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"} +#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0 "st,stm32h7-spi" #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-spi #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_spi #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_SPI -#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_1 "st,stm32-spi-fifo" #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi-fifo #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi_fifo #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO -#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_2 "st,stm32-spi" #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_2_STRING_UNQUOTED st,stm32-spi #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_2_STRING_TOKEN st_stm32_spi #define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_2_STRING_UPPER_TOKEN ST_STM32_SPI -#define DT_N_S_soc_S_spi_40015000_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, compatible, 0) \ fn(DT_N_S_soc_S_spi_40015000, compatible, 1) \ fn(DT_N_S_soc_S_spi_40015000, compatible, 2) @@ -10076,18 +10293,6 @@ fn(DT_N_S_soc_S_spi_40015000, compatible, 2, __VA_ARGS__) #define DT_N_S_soc_S_spi_40015000_P_compatible_LEN 3 #define DT_N_S_soc_S_spi_40015000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_reg {1073827840 /* 0x40015000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_0 1073827840 -#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_spi_40015000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_interrupts {85 /* 0x55 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_0 85 -#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_spi_40015000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_spi_40015000_P_clocks_IDX_0_VAL_bus 240 @@ -10102,54 +10307,10 @@ #define DT_N_S_soc_S_spi_40015000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_spi_40015000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spi_40015000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_2 DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_2_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_3 DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1) \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2) \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1, __VA_ARGS__) \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2, __VA_ARGS__) \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_spi_40015000, pinctrl_0, 3, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_LEN 4 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_spi_40015000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_spi_40015000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_midi_clock 0 -#define DT_N_S_soc_S_spi_40015000_P_midi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_mssi_clock 0 -#define DT_N_S_soc_S_spi_40015000_P_mssi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40015000_P_fifo_enable 0 -#define DT_N_S_soc_S_spi_40015000_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_wakeup_source 0 +#define DT_N_S_soc_S_spi_40015000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_spi_40015000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_spi_40015000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58020000 @@ -10168,6 +10329,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_FULL_NAME "gpio@58020000" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_FULL_NAME_UNQUOTED gpio@58020000 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_FULL_NAME_TOKEN gpio_58020000 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_FULL_NAME_UPPER_TOKEN GPIO_58020000 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10198,14 +10362,14 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 163, /* /soc/i2c@58001c00/ov7670@21 */ \ - 250, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 93, \ + 166, \ + 253, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_EXISTS 1 @@ -10215,8 +10379,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REG_IDX_0_VAL_ADDRESS 1476526080 /* 0x58020000 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REG_IDX_0_VAL_ADDRESS 1476526080 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_IRQ_NUM 0 @@ -10232,31 +10396,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg {1476526080 /* 0x58020000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_IDX_0 1476526080 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg {1476526080, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_IDX_0 1476526080 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10270,8 +10414,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58020400 @@ -10290,6 +10454,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_FULL_NAME "gpio@58020400" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_FULL_NAME_UNQUOTED gpio@58020400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_FULL_NAME_TOKEN gpio_58020400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_FULL_NAME_UPPER_TOKEN GPIO_58020400 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10320,12 +10487,12 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_EXISTS 1 @@ -10335,8 +10502,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REG_IDX_0_VAL_ADDRESS 1476527104 /* 0x58020400 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REG_IDX_0_VAL_ADDRESS 1476527104 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_IRQ_NUM 0 @@ -10352,31 +10519,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg {1476527104 /* 0x58020400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_IDX_0 1476527104 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg {1476527104, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_IDX_0 1476527104 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10390,8 +10537,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58020800 @@ -10410,6 +10577,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_FULL_NAME "gpio@58020800" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_FULL_NAME_UNQUOTED gpio@58020800 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_FULL_NAME_TOKEN gpio_58020800 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_FULL_NAME_UPPER_TOKEN GPIO_58020800 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10440,14 +10610,14 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 105, /* /gpio_keys */ \ - 106, /* /gpio_keys/button_0 */ + 93, \ + 105, \ + 106, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_EXISTS 1 @@ -10457,8 +10627,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REG_IDX_0_VAL_ADDRESS 1476528128 /* 0x58020800 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REG_IDX_0_VAL_ADDRESS 1476528128 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_IRQ_NUM 0 @@ -10474,31 +10644,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg {1476528128 /* 0x58020800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_IDX_0 1476528128 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg {1476528128, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_IDX_0 1476528128 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10512,8 +10662,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58020C00 @@ -10532,6 +10702,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_FULL_NAME "gpio@58020C00" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_FULL_NAME_UNQUOTED gpio@58020C00 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_FULL_NAME_TOKEN gpio_58020C00 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_FULL_NAME_UPPER_TOKEN GPIO_58020C00 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10562,13 +10735,13 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 163, /* /soc/i2c@58001c00/ov7670@21 */ + 93, \ + 166, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_EXISTS 1 @@ -10578,8 +10751,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REG_IDX_0_VAL_ADDRESS 1476529152 /* 0x58020c00 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REG_IDX_0_VAL_ADDRESS 1476529152 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_IRQ_NUM 0 @@ -10595,31 +10768,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg {1476529152 /* 0x58020c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_IDX_0 1476529152 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg {1476529152, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_IDX_0 1476529152 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10633,8 +10786,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58021000 @@ -10653,6 +10826,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_FULL_NAME "gpio@58021000" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_FULL_NAME_UNQUOTED gpio@58021000 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_FULL_NAME_TOKEN gpio_58021000 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_FULL_NAME_UPPER_TOKEN GPIO_58021000 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10683,14 +10859,14 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 107, /* /leds */ \ - 110, /* /leds/led_2 */ + 93, \ + 107, \ + 110, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_EXISTS 1 @@ -10700,8 +10876,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REG_IDX_0_VAL_ADDRESS 1476530176 /* 0x58021000 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REG_IDX_0_VAL_ADDRESS 1476530176 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_IRQ_NUM 0 @@ -10717,31 +10893,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg {1476530176 /* 0x58021000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_IDX_0 1476530176 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg {1476530176, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_IDX_0 1476530176 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10755,8 +10911,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58021800 @@ -10775,6 +10951,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FULL_NAME "gpio@58021800" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FULL_NAME_UNQUOTED gpio@58021800 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FULL_NAME_TOKEN gpio_58021800 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FULL_NAME_UPPER_TOKEN GPIO_58021800 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10805,13 +10984,13 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 250, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 93, \ + 253, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_EXISTS 1 @@ -10821,8 +11000,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_ADDRESS 1476532224 /* 0x58021800 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_ADDRESS 1476532224 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_IRQ_NUM 0 @@ -10838,31 +11017,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg {1476532224 /* 0x58021800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0 1476532224 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg {1476532224, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_0 1476532224 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10876,8 +11035,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58021C00 @@ -10896,6 +11075,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_FULL_NAME "gpio@58021C00" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_FULL_NAME_UNQUOTED gpio@58021C00 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_FULL_NAME_TOKEN gpio_58021C00 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_FULL_NAME_UPPER_TOKEN GPIO_58021C00 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -10926,13 +11108,13 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 250, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 93, \ + 253, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_EXISTS 1 @@ -10942,8 +11124,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REG_IDX_0_VAL_ADDRESS 1476533248 /* 0x58021c00 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REG_IDX_0_VAL_ADDRESS 1476533248 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_IRQ_NUM 0 @@ -10959,31 +11141,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg {1476533248 /* 0x58021c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_IDX_0 1476533248 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg {1476533248, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_IDX_0 1476533248 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -10997,8 +11159,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58022000 @@ -11017,6 +11199,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_FULL_NAME "gpio@58022000" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_FULL_NAME_UNQUOTED gpio@58022000 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_FULL_NAME_TOKEN gpio_58022000 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_FULL_NAME_UPPER_TOKEN GPIO_58022000 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -11047,14 +11232,14 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 107, /* /leds */ \ - 108, /* /leds/led_0 */ + 93, \ + 107, \ + 108, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_EXISTS 1 @@ -11064,8 +11249,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REG_IDX_0_VAL_ADDRESS 1476534272 /* 0x58022000 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REG_IDX_0_VAL_ADDRESS 1476534272 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_IRQ_NUM 0 @@ -11081,31 +11266,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg {1476534272 /* 0x58022000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_IDX_0 1476534272 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg {1476534272, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_IDX_0 1476534272 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -11119,8 +11284,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58022400 @@ -11139,6 +11324,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_FULL_NAME "gpio@58022400" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_FULL_NAME_UNQUOTED gpio@58022400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_FULL_NAME_TOKEN gpio_58022400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_FULL_NAME_UPPER_TOKEN GPIO_58022400 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -11169,14 +11357,14 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 107, /* /leds */ \ - 109, /* /leds/led_1 */ + 93, \ + 107, \ + 109, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_EXISTS 1 @@ -11186,8 +11374,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REG_IDX_0_VAL_ADDRESS 1476535296 /* 0x58022400 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REG_IDX_0_VAL_ADDRESS 1476535296 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_IRQ_NUM 0 @@ -11203,31 +11391,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg {1476535296 /* 0x58022400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_IDX_0 1476535296 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg {1476535296, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_IDX_0 1476535296 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -11241,8 +11409,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/gpio@58022800 @@ -11261,6 +11449,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_FULL_NAME "gpio@58022800" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_FULL_NAME_UNQUOTED gpio@58022800 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_FULL_NAME_TOKEN gpio_58022800 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_FULL_NAME_UPPER_TOKEN GPIO_58022800 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -11291,12 +11482,12 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_EXISTS 1 @@ -11306,8 +11497,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REG_IDX_0_VAL_ADDRESS 1476536320 /* 0x58022800 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REG_IDX_0_VAL_ADDRESS 1476536320 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_IRQ_NUM 0 @@ -11323,31 +11514,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg {1476536320 /* 0x58022800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_IDX_0 1476536320 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg {1476536320, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_IDX_0 1476536320 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -11361,8 +11532,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40010000 @@ -11381,6 +11572,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40010000_FULL_NAME "timers@40010000" +#define DT_N_S_soc_S_timers_40010000_FULL_NAME_UNQUOTED timers@40010000 +#define DT_N_S_soc_S_timers_40010000_FULL_NAME_TOKEN timers_40010000 +#define DT_N_S_soc_S_timers_40010000_FULL_NAME_UPPER_TOKEN TIMERS_40010000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40010000_PARENT DT_N_S_soc @@ -11411,14 +11605,14 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010000_SUPPORTS_ORDS \ - 87, /* /soc/timers@40010000/pwm */ + 87, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40010000_EXISTS 1 @@ -11428,8 +11622,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40010000_REG_NUM 1 #define DT_N_S_soc_S_timers_40010000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_ADDRESS 1073807360 /* 0x40010000 */ -#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_ADDRESS 1073807360 +#define DT_N_S_soc_S_timers_40010000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40010000_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40010000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40010000_IRQ_NUM 4 @@ -11493,20 +11687,46 @@ #define DT_N_S_soc_S_timers_40010000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010000_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_reg {1073807360, 1024} +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0 1073807360 +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40010000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40010000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id 4864 +#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, resets, 0) +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, resets, 0) +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40010000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40010000_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40010000_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_status "okay" #define DT_N_S_soc_S_timers_40010000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_timers_40010000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_timers_40010000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_timers_40010000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_timers_40010000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_timers_40010000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, status, 0) #define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, status, 0) #define DT_N_S_soc_S_timers_40010000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, status, 0, __VA_ARGS__) @@ -11514,62 +11734,56 @@ #define DT_N_S_soc_S_timers_40010000_P_status_LEN 1 #define DT_N_S_soc_S_timers_40010000_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40010000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, compatible, 0) #define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, compatible, 0) #define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40010000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40010000_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40010000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_reg {1073807360 /* 0x40010000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0 1073807360 -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40010000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts {24 /* 0x18 */, 0 /* 0x0 */, 25 /* 0x19 */, 0 /* 0x0 */, 26 /* 0x1a */, 0 /* 0x0 */, 27 /* 0x1b */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0 24 +#define DT_N_S_soc_S_timers_40010000_P_interrupts {24, 0, 25, 0, 26, 0, 27, 0} #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_0 24 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2 25 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_2 25 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4 26 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_3 0 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_4 26 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6 27 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_5 0 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_6 27 #define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupts_IDX_7 0 #define DT_N_S_soc_S_timers_40010000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names {"brk", "up", "trgcom", "cc"} +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0 "brk" #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UNQUOTED brk #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_TOKEN brk #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1 "up" #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UNQUOTED up #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_TOKEN up #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2 "trgcom" #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_TOKEN trgcom #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3 "cc" #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UNQUOTED cc #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_TOKEN cc #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC -#define DT_N_S_soc_S_timers_40010000_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 0) \ fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 1) \ fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 2) \ @@ -11588,34 +11802,12 @@ fn(DT_N_S_soc_S_timers_40010000, interrupt_names, 3, __VA_ARGS__) #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_LEN 4 #define DT_N_S_soc_S_timers_40010000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, clocks, 0) -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40010000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40010000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id 4864 -#define DT_N_S_soc_S_timers_40010000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000, resets, 0) -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000, resets, 0) -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40010000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40010000_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40010000_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/tim1_ch3_pj9 @@ -11631,6 +11823,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FULL_NAME "tim1_ch3_pj9" +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FULL_NAME_UNQUOTED tim1_ch3_pj9 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FULL_NAME_TOKEN tim1_ch3_pj9 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_FULL_NAME_UPPER_TOKEN TIM1_CH3_PJ9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -11661,11 +11856,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_SUPPORTS_ORDS \ - 87, /* /soc/timers@40010000/pwm */ + 87, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_EXISTS 1 @@ -11683,20 +11878,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_pinmux 4897 #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate "low-speed" @@ -11705,16 +11886,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/timers@40010000/pwm @@ -11733,6 +11926,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40010000) identifier: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_PARENT DT_N_S_soc_S_timers_40010000 @@ -11763,13 +11959,13 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_REQUIRES_ORDS \ - 85, /* /soc/timers@40010000 */ \ - 86, /* /soc/pin-controller@58020000/tim1_ch3_pj9 */ + 85, \ + 86, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ \ - 276, /* /soc/timers@40010000/pwm/pwmclock */ + 93, \ + 279, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_EXISTS 1 @@ -11799,20 +11995,37 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_PINCTRL_NAME_default_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status "okay" #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0 "okay" #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, status, 0, __VA_ARGS__) @@ -11820,11 +12033,11 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, compatible, 0, __VA_ARGS__) @@ -11833,29 +12046,10 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_0, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_LEN 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /otghs_fs_phy @@ -11874,12 +12068,15 @@ /* Node's name with unit-address: */ #define DT_N_S_otghs_fs_phy_FULL_NAME "otghs_fs_phy" +#define DT_N_S_otghs_fs_phy_FULL_NAME_UNQUOTED otghs_fs_phy +#define DT_N_S_otghs_fs_phy_FULL_NAME_TOKEN otghs_fs_phy +#define DT_N_S_otghs_fs_phy_FULL_NAME_UPPER_TOKEN OTGHS_FS_PHY /* Node parent (/) identifier: */ #define DT_N_S_otghs_fs_phy_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_otghs_fs_phy_CHILD_IDX 18 +#define DT_N_S_otghs_fs_phy_CHILD_IDX 19 /* Helpers for dealing with node labels: */ #define DT_N_S_otghs_fs_phy_NODELABEL_NUM 1 @@ -11904,12 +12101,12 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_otghs_fs_phy_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_otghs_fs_phy_SUPPORTS_ORDS \ - 91, /* /soc/usb@40080000 */ \ - 145, /* /soc/usb@40040000 */ + 91, \ + 148, /* Existence and alternate IDs: */ #define DT_N_S_otghs_fs_phy_EXISTS 1 @@ -11929,16 +12126,12 @@ #define DT_N_S_otghs_fs_phy_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_otghs_fs_phy_P_wakeup_source 0 -#define DT_N_S_otghs_fs_phy_P_wakeup_source_EXISTS 1 -#define DT_N_S_otghs_fs_phy_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_otghs_fs_phy_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_otghs_fs_phy_P_compatible {"usb-nop-xceiv"} +#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_otghs_fs_phy_P_compatible_IDX_0 "usb-nop-xceiv" #define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_STRING_UNQUOTED usb-nop-xceiv #define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_STRING_TOKEN usb_nop_xceiv #define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_STRING_UPPER_TOKEN USB_NOP_XCEIV -#define DT_N_S_otghs_fs_phy_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_otghs_fs_phy, compatible, 0) #define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_otghs_fs_phy, compatible, 0) #define DT_N_S_otghs_fs_phy_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_otghs_fs_phy, compatible, 0, __VA_ARGS__) @@ -11947,6 +12140,10 @@ #define DT_N_S_otghs_fs_phy_P_compatible_EXISTS 1 #define DT_N_S_otghs_fs_phy_P_zephyr_deferred_init 0 #define DT_N_S_otghs_fs_phy_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_otghs_fs_phy_P_wakeup_source 0 +#define DT_N_S_otghs_fs_phy_P_wakeup_source_EXISTS 1 +#define DT_N_S_otghs_fs_phy_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_otghs_fs_phy_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 @@ -11962,6 +12159,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_FULL_NAME "usb_otg_fs_dm_pa11" +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_FULL_NAME_UNQUOTED usb_otg_fs_dm_pa11 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_FULL_NAME_TOKEN usb_otg_fs_dm_pa11 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_FULL_NAME_UPPER_TOKEN USB_OTG_FS_DM_PA11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -11992,11 +12192,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_SUPPORTS_ORDS \ - 91, /* /soc/usb@40080000 */ + 91, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_EXISTS 1 @@ -12014,20 +12214,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_pinmux 362 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate "low-speed" @@ -12036,16 +12222,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 @@ -12061,6 +12259,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_FULL_NAME "usb_otg_fs_dp_pa12" +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_FULL_NAME_UNQUOTED usb_otg_fs_dp_pa12 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_FULL_NAME_TOKEN usb_otg_fs_dp_pa12 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_FULL_NAME_UPPER_TOKEN USB_OTG_FS_DP_PA12 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -12091,11 +12292,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_SUPPORTS_ORDS \ - 91, /* /soc/usb@40080000 */ + 91, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_EXISTS 1 @@ -12113,20 +12314,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_pinmux 394 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate "low-speed" @@ -12135,16 +12322,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12_P_output_high_EXISTS 1 /* * Devicetree node: /soc/usb@40080000 @@ -12163,6 +12362,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_usb_40080000_FULL_NAME "usb@40080000" +#define DT_N_S_soc_S_usb_40080000_FULL_NAME_UNQUOTED usb@40080000 +#define DT_N_S_soc_S_usb_40080000_FULL_NAME_TOKEN usb_40080000 +#define DT_N_S_soc_S_usb_40080000_FULL_NAME_UPPER_TOKEN USB_40080000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_usb_40080000_PARENT DT_N_S_soc @@ -12193,16 +12395,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_usb_40080000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 88, /* /otghs_fs_phy */ \ - 89, /* /soc/pin-controller@58020000/usb_otg_fs_dm_pa11 */ \ - 90, /* /soc/pin-controller@58020000/usb_otg_fs_dp_pa12 */ + 4, \ + 5, \ + 9, \ + 88, \ + 89, \ + 90, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_usb_40080000_SUPPORTS_ORDS \ - 92, /* /soc/usb@40080000/cdc_acm_uart0 */ + 92, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_usb_40080000_EXISTS 1 @@ -12213,8 +12415,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_usb_40080000_REG_NUM 1 #define DT_N_S_soc_S_usb_40080000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_REG_IDX_0_VAL_ADDRESS 1074266112 /* 0x40080000 */ -#define DT_N_S_soc_S_usb_40080000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ +#define DT_N_S_soc_S_usb_40080000_REG_IDX_0_VAL_ADDRESS 1074266112 +#define DT_N_S_soc_S_usb_40080000_REG_IDX_0_VAL_SIZE 262144 #define DT_N_S_soc_S_usb_40080000_RANGES_NUM 0 #define DT_N_S_soc_S_usb_40080000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_usb_40080000_IRQ_NUM 4 @@ -12285,20 +12487,116 @@ #define DT_N_S_soc_S_usb_40080000_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12 /* Generic property macros: */ -#define DT_N_S_soc_S_usb_40080000_P_wakeup_source 0 -#define DT_N_S_soc_S_usb_40080000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_usb_40080000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_reg {1074266112, 262144} +#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_0 1074266112 +#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_1 262144 +#define DT_N_S_soc_S_usb_40080000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts {98, 0, 99, 0, 100, 0, 101, 0} +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_0 98 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_2 99 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_4 100 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_6 101 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_usb_40080000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0) \ + fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_LEN 2 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0 "default" +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_STRING_TOKEN default +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_LEN 1 +#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_ram_size 4096 +#define DT_N_S_soc_S_usb_40080000_P_ram_size_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_phys DT_N_S_otghs_fs_phy +#define DT_N_S_soc_S_usb_40080000_P_phys_IDX_0 DT_N_S_otghs_fs_phy +#define DT_N_S_soc_S_usb_40080000_P_phys_IDX_0_PH DT_N_S_otghs_fs_phy +#define DT_N_S_soc_S_usb_40080000_P_phys_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, phys, 0) +#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, phys, 0) +#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, phys, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, phys, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_phys_LEN 1 +#define DT_N_S_soc_S_usb_40080000_P_phys_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bus 216 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bits 134217728 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bus 5 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bits 226388 +#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, clocks, 0) \ + fn(DT_N_S_soc_S_usb_40080000, clocks, 1) +#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, clocks, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40080000, clocks, 1) +#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, clocks, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_usb_40080000, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40080000, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_clocks_LEN 2 +#define DT_N_S_soc_S_usb_40080000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_num_bidir_endpoints 9 +#define DT_N_S_soc_S_usb_40080000_P_num_bidir_endpoints_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed "full-speed" +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_STRING_UNQUOTED full-speed +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_STRING_TOKEN full_speed +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_STRING_UPPER_TOKEN FULL_SPEED +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_IDX_0 "full-speed" +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_IDX_0_ENUM_VAL_full_speed_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0) +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0) +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_LEN 1 +#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_status "okay" #define DT_N_S_soc_S_usb_40080000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_usb_40080000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_usb_40080000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_usb_40080000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_usb_40080000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_usb_40080000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_usb_40080000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_usb_40080000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_usb_40080000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, status, 0) #define DT_N_S_soc_S_usb_40080000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, status, 0) #define DT_N_S_soc_S_usb_40080000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, status, 0, __VA_ARGS__) @@ -12306,62 +12604,38 @@ #define DT_N_S_soc_S_usb_40080000_P_status_LEN 1 #define DT_N_S_soc_S_usb_40080000_P_status_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_compatible {"st,stm32-otgfs"} +#define DT_N_S_soc_S_usb_40080000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_compatible_IDX_0 "st,stm32-otgfs" #define DT_N_S_soc_S_usb_40080000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-otgfs #define DT_N_S_soc_S_usb_40080000_P_compatible_IDX_0_STRING_TOKEN st_stm32_otgfs #define DT_N_S_soc_S_usb_40080000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_OTGFS -#define DT_N_S_soc_S_usb_40080000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, compatible, 0) #define DT_N_S_soc_S_usb_40080000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, compatible, 0) #define DT_N_S_soc_S_usb_40080000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_usb_40080000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_usb_40080000_P_compatible_LEN 1 #define DT_N_S_soc_S_usb_40080000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_reg {1074266112 /* 0x40080000 */, 262144 /* 0x40000 */} -#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_0 1074266112 -#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_1 262144 -#define DT_N_S_soc_S_usb_40080000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts {98 /* 0x62 */, 0 /* 0x0 */, 99 /* 0x63 */, 0 /* 0x0 */, 100 /* 0x64 */, 0 /* 0x0 */, 101 /* 0x65 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_0 98 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_2 99 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_4 100 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_5 0 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_6 101 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_7 0 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names {"ep1_out", "ep1_in", "wkup", "otgfs"} +#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_0 "ep1_out" #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_0_STRING_UNQUOTED ep1_out #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_0_STRING_TOKEN ep1_out #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EP1_OUT -#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_1 "ep1_in" #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_1_STRING_UNQUOTED ep1_in #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_1_STRING_TOKEN ep1_in #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN EP1_IN -#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_2 "wkup" #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_2_STRING_UNQUOTED wkup #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_2_STRING_TOKEN wkup #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN WKUP -#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_3 "otgfs" #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_3_STRING_UNQUOTED otgfs #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_3_STRING_TOKEN otgfs #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN OTGFS -#define DT_N_S_soc_S_usb_40080000_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, interrupt_names, 0) \ fn(DT_N_S_soc_S_usb_40080000, interrupt_names, 1) \ fn(DT_N_S_soc_S_usb_40080000, interrupt_names, 2) \ @@ -12380,88 +12654,12 @@ fn(DT_N_S_soc_S_usb_40080000, interrupt_names, 3, __VA_ARGS__) #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_LEN 4 #define DT_N_S_soc_S_usb_40080000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bus 216 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bits 134217728 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bus 5 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bits 226388 -#define DT_N_S_soc_S_usb_40080000_P_clocks_IDX_1_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, clocks, 0) \ - fn(DT_N_S_soc_S_usb_40080000, clocks, 1) -#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, clocks, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40080000, clocks, 1) -#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, clocks, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_usb_40080000, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40080000, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_clocks_LEN 2 -#define DT_N_S_soc_S_usb_40080000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_usb_40080000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed "full-speed" -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_STRING_UNQUOTED full-speed -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_STRING_TOKEN full_speed -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_STRING_UPPER_TOKEN FULL_SPEED -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_IDX_0 "full-speed" -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_ENUM_IDX 1 -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_ENUM_VAL_full_speed_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_ENUM_TOKEN full_speed -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_ENUM_UPPER_TOKEN FULL_SPEED -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0) -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0) -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, maximum_speed, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_LEN 1 -#define DT_N_S_soc_S_usb_40080000_P_maximum_speed_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_num_bidir_endpoints 9 -#define DT_N_S_soc_S_usb_40080000_P_num_bidir_endpoints_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_1 DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0) \ - fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40080000, pinctrl_0, 1, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_LEN 2 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names {"default"} -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0 "default" -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_STRING_TOKEN default -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, pinctrl_names, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_LEN 1 -#define DT_N_S_soc_S_usb_40080000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_ram_size 4096 -#define DT_N_S_soc_S_usb_40080000_P_ram_size_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_phys DT_N_S_otghs_fs_phy -#define DT_N_S_soc_S_usb_40080000_P_phys_IDX_0 DT_N_S_otghs_fs_phy -#define DT_N_S_soc_S_usb_40080000_P_phys_IDX_0_PH DT_N_S_otghs_fs_phy -#define DT_N_S_soc_S_usb_40080000_P_phys_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000, phys, 0) -#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000, phys, 0) -#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000, phys, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40080000, phys, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40080000_P_phys_LEN 1 -#define DT_N_S_soc_S_usb_40080000_P_phys_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_wakeup_source 0 +#define DT_N_S_soc_S_usb_40080000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_usb_40080000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/usb@40080000/cdc_acm_uart0 @@ -12480,6 +12678,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_FULL_NAME "cdc_acm_uart0" +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_FULL_NAME_UNQUOTED cdc_acm_uart0 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_FULL_NAME_TOKEN cdc_acm_uart0 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_FULL_NAME_UPPER_TOKEN CDC_ACM_UART0 /* Node parent (/soc/usb@40080000) identifier: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_PARENT DT_N_S_soc_S_usb_40080000 @@ -12510,11 +12711,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_REQUIRES_ORDS \ - 91, /* /soc/usb@40080000 */ + 91, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_SUPPORTS_ORDS \ - 93, /* /zephyr,user */ + 93, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_EXISTS 1 @@ -12542,20 +12743,20 @@ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_wakeup_source 0 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_tx_fifo_size 1024 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_tx_fifo_size_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_rx_fifo_size 1024 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_rx_fifo_size_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_hw_flow_control 0 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status "okay" #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_IDX_0 "okay" #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, status, 0) #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, status, 0) #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, status, 0, __VA_ARGS__) @@ -12563,11 +12764,11 @@ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_LEN 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_status_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible {"zephyr,cdc-acm-uart"} +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_IDX_0 "zephyr,cdc-acm-uart" #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_IDX_0_STRING_UNQUOTED zephyr,cdc-acm-uart #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_IDX_0_STRING_TOKEN zephyr_cdc_acm_uart #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_CDC_ACM_UART -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, compatible, 0) #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, compatible, 0) #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, compatible, 0, __VA_ARGS__) @@ -12576,12 +12777,10 @@ #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_compatible_EXISTS 1 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_hw_flow_control 0 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_hw_flow_control_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_tx_fifo_size 1024 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_tx_fifo_size_EXISTS 1 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_rx_fifo_size 1024 -#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_rx_fifo_size_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_wakeup_source 0 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /zephyr,user @@ -12597,12 +12796,15 @@ /* Node's name with unit-address: */ #define DT_N_S_zephyr_user_FULL_NAME "zephyr,user" +#define DT_N_S_zephyr_user_FULL_NAME_UNQUOTED zephyr,user +#define DT_N_S_zephyr_user_FULL_NAME_TOKEN zephyr_user +#define DT_N_S_zephyr_user_FULL_NAME_UPPER_TOKEN ZEPHYR_USER /* Node parent (/) identifier: */ #define DT_N_S_zephyr_user_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_zephyr_user_CHILD_IDX 24 +#define DT_N_S_zephyr_user_CHILD_IDX 25 /* Helpers for dealing with node labels: */ #define DT_N_S_zephyr_user_NODELABEL_NUM 0 @@ -12627,31 +12829,31 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_zephyr_user_REQUIRES_ORDS \ - 0, /* / */ \ - 13, /* /soc/adc@58026000 */ \ - 24, /* /soc/i2c@40005400 */ \ - 28, /* /soc/i2c@40005800 */ \ - 34, /* /soc/i2c@58001c00 */ \ - 38, /* /gpio@deadbeef */ \ - 51, /* /soc/adc@40022000 */ \ - 55, /* /soc/serial@40004400 */ \ - 58, /* /soc/serial@40004c00 */ \ - 61, /* /soc/serial@40011000 */ \ - 64, /* /soc/serial@40011400 */ \ - 69, /* /soc/spi@40013000 */ \ - 74, /* /soc/spi@40015000 */ \ - 75, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 76, /* /soc/pin-controller@58020000/gpio@58020400 */ \ - 77, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 78, /* /soc/pin-controller@58020000/gpio@58020C00 */ \ - 79, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 80, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 81, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 82, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 83, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 84, /* /soc/pin-controller@58020000/gpio@58022800 */ \ - 87, /* /soc/timers@40010000/pwm */ \ - 92, /* /soc/usb@40080000/cdc_acm_uart0 */ + 0, \ + 13, \ + 24, \ + 28, \ + 34, \ + 38, \ + 51, \ + 55, \ + 58, \ + 61, \ + 64, \ + 69, \ + 74, \ + 75, \ + 76, \ + 77, \ + 78, \ + 79, \ + 80, \ + 81, \ + 82, \ + 83, \ + 84, \ + 87, \ + 92, /* Ordinals for what depends directly on this node: */ #define DT_N_S_zephyr_user_SUPPORTS_ORDS /* nothing */ @@ -14141,6 +14343,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_clk_csi_FULL_NAME "clk-csi" +#define DT_N_S_clocks_S_clk_csi_FULL_NAME_UNQUOTED clk-csi +#define DT_N_S_clocks_S_clk_csi_FULL_NAME_TOKEN clk_csi +#define DT_N_S_clocks_S_clk_csi_FULL_NAME_UPPER_TOKEN CLK_CSI /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_clk_csi_PARENT DT_N_S_clocks @@ -14171,7 +14376,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_csi_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_clk_csi_SUPPORTS_ORDS /* nothing */ @@ -14196,6 +14401,38 @@ /* Generic property macros: */ #define DT_N_S_clocks_S_clk_csi_P_clock_frequency 4000000 #define DT_N_S_clocks_S_clk_csi_P_clock_frequency_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_status "disabled" +#define DT_N_S_clocks_S_clk_csi_P_status_STRING_UNQUOTED disabled +#define DT_N_S_clocks_S_clk_csi_P_status_STRING_TOKEN disabled +#define DT_N_S_clocks_S_clk_csi_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_clocks_S_clk_csi_P_status_IDX_0 "disabled" +#define DT_N_S_clocks_S_clk_csi_P_status_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_clocks_S_clk_csi_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_csi, status, 0) +#define DT_N_S_clocks_S_clk_csi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_csi, status, 0) +#define DT_N_S_clocks_S_clk_csi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_csi, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_csi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_csi, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_csi_P_status_LEN 1 +#define DT_N_S_clocks_S_clk_csi_P_status_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_compatible {"fixed-clock"} +#define DT_N_S_clocks_S_clk_csi_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_compatible_IDX_0 "fixed-clock" +#define DT_N_S_clocks_S_clk_csi_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock +#define DT_N_S_clocks_S_clk_csi_P_compatible_IDX_0_STRING_TOKEN fixed_clock +#define DT_N_S_clocks_S_clk_csi_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK +#define DT_N_S_clocks_S_clk_csi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_csi, compatible, 0) +#define DT_N_S_clocks_S_clk_csi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_csi, compatible, 0) +#define DT_N_S_clocks_S_clk_csi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_csi, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_csi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_csi, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_csi_P_compatible_LEN 1 +#define DT_N_S_clocks_S_clk_csi_P_compatible_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_zephyr_deferred_init 0 +#define DT_N_S_clocks_S_clk_csi_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_wakeup_source 0 +#define DT_N_S_clocks_S_clk_csi_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_clk_csi_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_clk_csi_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/clk-hsi @@ -14214,6 +14451,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_clk_hsi_FULL_NAME "clk-hsi" +#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_UNQUOTED clk-hsi +#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_TOKEN clk_hsi +#define DT_N_S_clocks_S_clk_hsi_FULL_NAME_UPPER_TOKEN CLK_HSI /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_clk_hsi_PARENT DT_N_S_clocks @@ -14244,7 +14484,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_hsi_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_clk_hsi_SUPPORTS_ORDS /* nothing */ @@ -14271,8 +14511,45 @@ #define DT_N_S_clocks_S_clk_hsi_PINCTRL_NUM 0 /* Generic property macros: */ +#define DT_N_S_clocks_S_clk_hsi_P_hsi_div 1 +#define DT_N_S_clocks_S_clk_hsi_P_hsi_div_IDX_0_ENUM_IDX 0 +#define DT_N_S_clocks_S_clk_hsi_P_hsi_div_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_hsi_div_IDX_0_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_hsi_div_EXISTS 1 #define DT_N_S_clocks_S_clk_hsi_P_clock_frequency 64000000 #define DT_N_S_clocks_S_clk_hsi_P_clock_frequency_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_status "disabled" +#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_UNQUOTED disabled +#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_TOKEN disabled +#define DT_N_S_clocks_S_clk_hsi_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0 "disabled" +#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_clocks_S_clk_hsi_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi, status, 0) +#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi, status, 0) +#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi_P_status_LEN 1 +#define DT_N_S_clocks_S_clk_hsi_P_status_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_compatible {"st,stm32h7-hsi-clock"} +#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0 "st,stm32h7-hsi-clock" +#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-hsi-clock +#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_hsi_clock +#define DT_N_S_clocks_S_clk_hsi_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_HSI_CLOCK +#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0) +#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0) +#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi_P_compatible_LEN 1 +#define DT_N_S_clocks_S_clk_hsi_P_compatible_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_zephyr_deferred_init 0 +#define DT_N_S_clocks_S_clk_hsi_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_wakeup_source 0 +#define DT_N_S_clocks_S_clk_hsi_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_clk_hsi_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/clk-hsi48 @@ -14291,6 +14568,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_clk_hsi48_FULL_NAME "clk-hsi48" +#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME_UNQUOTED clk-hsi48 +#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME_TOKEN clk_hsi48 +#define DT_N_S_clocks_S_clk_hsi48_FULL_NAME_UPPER_TOKEN CLK_HSI48 /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_clk_hsi48_PARENT DT_N_S_clocks @@ -14321,7 +14601,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_hsi48_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_clk_hsi48_SUPPORTS_ORDS /* nothing */ @@ -14346,6 +14626,38 @@ /* Generic property macros: */ #define DT_N_S_clocks_S_clk_hsi48_P_clock_frequency 48000000 #define DT_N_S_clocks_S_clk_hsi48_P_clock_frequency_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_status "okay" +#define DT_N_S_clocks_S_clk_hsi48_P_status_STRING_UNQUOTED okay +#define DT_N_S_clocks_S_clk_hsi48_P_status_STRING_TOKEN okay +#define DT_N_S_clocks_S_clk_hsi48_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0 "okay" +#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_clocks_S_clk_hsi48_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi48, status, 0) +#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi48, status, 0) +#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi48, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi48_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi48, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi48_P_status_LEN 1 +#define DT_N_S_clocks_S_clk_hsi48_P_status_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_compatible {"fixed-clock"} +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0 "fixed-clock" +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_STRING_TOKEN fixed_clock +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0) +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0) +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_hsi48, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_LEN 1 +#define DT_N_S_clocks_S_clk_hsi48_P_compatible_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_deferred_init 0 +#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_wakeup_source 0 +#define DT_N_S_clocks_S_clk_hsi48_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_clk_hsi48_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/clk-lse @@ -14364,6 +14676,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_clk_lse_FULL_NAME "clk-lse" +#define DT_N_S_clocks_S_clk_lse_FULL_NAME_UNQUOTED clk-lse +#define DT_N_S_clocks_S_clk_lse_FULL_NAME_TOKEN clk_lse +#define DT_N_S_clocks_S_clk_lse_FULL_NAME_UPPER_TOKEN CLK_LSE /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_clk_lse_PARENT DT_N_S_clocks @@ -14394,7 +14709,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_lse_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_clk_lse_SUPPORTS_ORDS /* nothing */ @@ -14421,14 +14736,47 @@ #define DT_N_S_clocks_S_clk_lse_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_clocks_S_clk_lse_P_clock_frequency 32768 -#define DT_N_S_clocks_S_clk_lse_P_clock_frequency_EXISTS 1 #define DT_N_S_clocks_S_clk_lse_P_driving_capability 0 -#define DT_N_S_clocks_S_clk_lse_P_driving_capability_ENUM_IDX 0 -#define DT_N_S_clocks_S_clk_lse_P_driving_capability_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_driving_capability_IDX_0_ENUM_IDX 0 +#define DT_N_S_clocks_S_clk_lse_P_driving_capability_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_driving_capability_IDX_0_ENUM_VAL_0_EXISTS 1 #define DT_N_S_clocks_S_clk_lse_P_driving_capability_EXISTS 1 #define DT_N_S_clocks_S_clk_lse_P_lse_bypass 0 #define DT_N_S_clocks_S_clk_lse_P_lse_bypass_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_clock_frequency 32768 +#define DT_N_S_clocks_S_clk_lse_P_clock_frequency_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_status "okay" +#define DT_N_S_clocks_S_clk_lse_P_status_STRING_UNQUOTED okay +#define DT_N_S_clocks_S_clk_lse_P_status_STRING_TOKEN okay +#define DT_N_S_clocks_S_clk_lse_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0 "okay" +#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_clocks_S_clk_lse_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lse, status, 0) +#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lse, status, 0) +#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lse, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lse_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lse, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lse_P_status_LEN 1 +#define DT_N_S_clocks_S_clk_lse_P_status_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_compatible {"st,stm32-lse-clock"} +#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0 "st,stm32-lse-clock" +#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lse-clock +#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_TOKEN st_stm32_lse_clock +#define DT_N_S_clocks_S_clk_lse_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LSE_CLOCK +#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lse, compatible, 0) +#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lse, compatible, 0) +#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lse, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lse_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lse, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lse_P_compatible_LEN 1 +#define DT_N_S_clocks_S_clk_lse_P_compatible_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_zephyr_deferred_init 0 +#define DT_N_S_clocks_S_clk_lse_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_wakeup_source 0 +#define DT_N_S_clocks_S_clk_lse_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_clk_lse_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_clk_lse_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/clk-lsi @@ -14447,6 +14795,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_clk_lsi_FULL_NAME "clk-lsi" +#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_UNQUOTED clk-lsi +#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_TOKEN clk_lsi +#define DT_N_S_clocks_S_clk_lsi_FULL_NAME_UPPER_TOKEN CLK_LSI /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_clk_lsi_PARENT DT_N_S_clocks @@ -14477,7 +14828,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_clk_lsi_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_clk_lsi_SUPPORTS_ORDS /* nothing */ @@ -14502,6 +14853,38 @@ /* Generic property macros: */ #define DT_N_S_clocks_S_clk_lsi_P_clock_frequency 32000 #define DT_N_S_clocks_S_clk_lsi_P_clock_frequency_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_status "disabled" +#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_UNQUOTED disabled +#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_TOKEN disabled +#define DT_N_S_clocks_S_clk_lsi_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0 "disabled" +#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_clocks_S_clk_lsi_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lsi, status, 0) +#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lsi, status, 0) +#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lsi_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lsi, status, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lsi_P_status_LEN 1 +#define DT_N_S_clocks_S_clk_lsi_P_status_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_compatible {"fixed-clock"} +#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0 "fixed-clock" +#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_UNQUOTED fixed-clock +#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_TOKEN fixed_clock +#define DT_N_S_clocks_S_clk_lsi_P_compatible_IDX_0_STRING_UPPER_TOKEN FIXED_CLOCK +#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0) +#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0) +#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lsi_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_clk_lsi, compatible, 0, __VA_ARGS__) +#define DT_N_S_clocks_S_clk_lsi_P_compatible_LEN 1 +#define DT_N_S_clocks_S_clk_lsi_P_compatible_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_zephyr_deferred_init 0 +#define DT_N_S_clocks_S_clk_lsi_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_wakeup_source 0 +#define DT_N_S_clocks_S_clk_lsi_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_clk_lsi_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_clk_lsi_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/perck @@ -14520,6 +14903,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_perck_FULL_NAME "perck" +#define DT_N_S_clocks_S_perck_FULL_NAME_UNQUOTED perck +#define DT_N_S_clocks_S_perck_FULL_NAME_TOKEN perck +#define DT_N_S_clocks_S_perck_FULL_NAME_UPPER_TOKEN PERCK /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_perck_PARENT DT_N_S_clocks @@ -14550,7 +14936,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_perck_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_perck_SUPPORTS_ORDS /* nothing */ @@ -14583,10 +14969,8 @@ #define DT_N_S_clocks_S_perck_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_clocks_S_perck_P_status_IDX_0 "disabled" #define DT_N_S_clocks_S_perck_P_status_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_perck_P_status_ENUM_IDX 2 -#define DT_N_S_clocks_S_perck_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_clocks_S_perck_P_status_ENUM_TOKEN disabled -#define DT_N_S_clocks_S_perck_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_clocks_S_perck_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_clocks_S_perck_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_clocks_S_perck_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_perck, status, 0) #define DT_N_S_clocks_S_perck_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_perck, status, 0) #define DT_N_S_clocks_S_perck_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_perck, status, 0, __VA_ARGS__) @@ -14594,11 +14978,11 @@ #define DT_N_S_clocks_S_perck_P_status_LEN 1 #define DT_N_S_clocks_S_perck_P_status_EXISTS 1 #define DT_N_S_clocks_S_perck_P_compatible {"st,stm32-clock-mux"} +#define DT_N_S_clocks_S_perck_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_perck_P_compatible_IDX_0 "st,stm32-clock-mux" #define DT_N_S_clocks_S_perck_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-clock-mux #define DT_N_S_clocks_S_perck_P_compatible_IDX_0_STRING_TOKEN st_stm32_clock_mux #define DT_N_S_clocks_S_perck_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_CLOCK_MUX -#define DT_N_S_clocks_S_perck_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_perck_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_perck, compatible, 0) #define DT_N_S_clocks_S_perck_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_perck, compatible, 0) #define DT_N_S_clocks_S_perck_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_perck, compatible, 0, __VA_ARGS__) @@ -14623,6 +15007,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_pll_1_FULL_NAME "pll@1" +#define DT_N_S_clocks_S_pll_1_FULL_NAME_UNQUOTED pll@1 +#define DT_N_S_clocks_S_pll_1_FULL_NAME_TOKEN pll_1 +#define DT_N_S_clocks_S_pll_1_FULL_NAME_UPPER_TOKEN PLL_1 /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_pll_1_PARENT DT_N_S_clocks @@ -14653,7 +15040,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_pll_1_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_pll_1_SUPPORTS_ORDS /* nothing */ @@ -14666,7 +15053,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_clocks_S_pll_1_REG_NUM 1 #define DT_N_S_clocks_S_pll_1_REG_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */ +#define DT_N_S_clocks_S_pll_1_REG_IDX_0_VAL_ADDRESS 1 #define DT_N_S_clocks_S_pll_1_RANGES_NUM 0 #define DT_N_S_clocks_S_pll_1_FOREACH_RANGE(fn) #define DT_N_S_clocks_S_pll_1_IRQ_NUM 0 @@ -14682,20 +15069,14 @@ #define DT_N_S_clocks_S_pll_1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_clocks_S_pll_1_P_wakeup_source 0 -#define DT_N_S_clocks_S_pll_1_P_wakeup_source_EXISTS 1 -#define DT_N_S_clocks_S_pll_1_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_clocks_S_pll_1_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_clocks_S_pll_1_P_status "disabled" #define DT_N_S_clocks_S_pll_1_P_status_STRING_UNQUOTED disabled #define DT_N_S_clocks_S_pll_1_P_status_STRING_TOKEN disabled #define DT_N_S_clocks_S_pll_1_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_clocks_S_pll_1_P_status_IDX_0 "disabled" #define DT_N_S_clocks_S_pll_1_P_status_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_1_P_status_ENUM_IDX 2 -#define DT_N_S_clocks_S_pll_1_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_clocks_S_pll_1_P_status_ENUM_TOKEN disabled -#define DT_N_S_clocks_S_pll_1_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_clocks_S_pll_1_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_clocks_S_pll_1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_clocks_S_pll_1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_1, status, 0) #define DT_N_S_clocks_S_pll_1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_1, status, 0) #define DT_N_S_clocks_S_pll_1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_1, status, 0, __VA_ARGS__) @@ -14703,23 +15084,27 @@ #define DT_N_S_clocks_S_pll_1_P_status_LEN 1 #define DT_N_S_clocks_S_pll_1_P_status_EXISTS 1 #define DT_N_S_clocks_S_pll_1_P_compatible {"st,stm32h7-pll-clock"} +#define DT_N_S_clocks_S_pll_1_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_pll_1_P_compatible_IDX_0 "st,stm32h7-pll-clock" #define DT_N_S_clocks_S_pll_1_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-pll-clock #define DT_N_S_clocks_S_pll_1_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_pll_clock #define DT_N_S_clocks_S_pll_1_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_PLL_CLOCK -#define DT_N_S_clocks_S_pll_1_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_pll_1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_1, compatible, 0) #define DT_N_S_clocks_S_pll_1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_1, compatible, 0) #define DT_N_S_clocks_S_pll_1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_1, compatible, 0, __VA_ARGS__) #define DT_N_S_clocks_S_pll_1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll_1, compatible, 0, __VA_ARGS__) #define DT_N_S_clocks_S_pll_1_P_compatible_LEN 1 #define DT_N_S_clocks_S_pll_1_P_compatible_EXISTS 1 -#define DT_N_S_clocks_S_pll_1_P_reg {1 /* 0x1 */} -#define DT_N_S_clocks_S_pll_1_P_reg_IDX_0 1 +#define DT_N_S_clocks_S_pll_1_P_reg {1} #define DT_N_S_clocks_S_pll_1_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_pll_1_P_reg_IDX_0 1 #define DT_N_S_clocks_S_pll_1_P_reg_EXISTS 1 #define DT_N_S_clocks_S_pll_1_P_zephyr_deferred_init 0 #define DT_N_S_clocks_S_pll_1_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_pll_1_P_wakeup_source 0 +#define DT_N_S_clocks_S_pll_1_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_pll_1_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_pll_1_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /clocks/pll@2 @@ -14738,6 +15123,9 @@ /* Node's name with unit-address: */ #define DT_N_S_clocks_S_pll_2_FULL_NAME "pll@2" +#define DT_N_S_clocks_S_pll_2_FULL_NAME_UNQUOTED pll@2 +#define DT_N_S_clocks_S_pll_2_FULL_NAME_TOKEN pll_2 +#define DT_N_S_clocks_S_pll_2_FULL_NAME_UPPER_TOKEN PLL_2 /* Node parent (/clocks) identifier: */ #define DT_N_S_clocks_S_pll_2_PARENT DT_N_S_clocks @@ -14768,7 +15156,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_clocks_S_pll_2_REQUIRES_ORDS \ - 6, /* /clocks */ + 6, /* Ordinals for what depends directly on this node: */ #define DT_N_S_clocks_S_pll_2_SUPPORTS_ORDS /* nothing */ @@ -14781,7 +15169,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_clocks_S_pll_2_REG_NUM 1 #define DT_N_S_clocks_S_pll_2_REG_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_2_REG_IDX_0_VAL_ADDRESS 2 /* 0x2 */ +#define DT_N_S_clocks_S_pll_2_REG_IDX_0_VAL_ADDRESS 2 #define DT_N_S_clocks_S_pll_2_RANGES_NUM 0 #define DT_N_S_clocks_S_pll_2_FOREACH_RANGE(fn) #define DT_N_S_clocks_S_pll_2_IRQ_NUM 0 @@ -14797,20 +15185,14 @@ #define DT_N_S_clocks_S_pll_2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_clocks_S_pll_2_P_wakeup_source 0 -#define DT_N_S_clocks_S_pll_2_P_wakeup_source_EXISTS 1 -#define DT_N_S_clocks_S_pll_2_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_clocks_S_pll_2_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_clocks_S_pll_2_P_status "disabled" #define DT_N_S_clocks_S_pll_2_P_status_STRING_UNQUOTED disabled #define DT_N_S_clocks_S_pll_2_P_status_STRING_TOKEN disabled #define DT_N_S_clocks_S_pll_2_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_clocks_S_pll_2_P_status_IDX_0 "disabled" #define DT_N_S_clocks_S_pll_2_P_status_IDX_0_EXISTS 1 -#define DT_N_S_clocks_S_pll_2_P_status_ENUM_IDX 2 -#define DT_N_S_clocks_S_pll_2_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_clocks_S_pll_2_P_status_ENUM_TOKEN disabled -#define DT_N_S_clocks_S_pll_2_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_clocks_S_pll_2_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_clocks_S_pll_2_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_clocks_S_pll_2_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_2, status, 0) #define DT_N_S_clocks_S_pll_2_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_2, status, 0) #define DT_N_S_clocks_S_pll_2_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_2, status, 0, __VA_ARGS__) @@ -14818,23 +15200,27 @@ #define DT_N_S_clocks_S_pll_2_P_status_LEN 1 #define DT_N_S_clocks_S_pll_2_P_status_EXISTS 1 #define DT_N_S_clocks_S_pll_2_P_compatible {"st,stm32h7-pll-clock"} +#define DT_N_S_clocks_S_pll_2_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_pll_2_P_compatible_IDX_0 "st,stm32h7-pll-clock" #define DT_N_S_clocks_S_pll_2_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-pll-clock #define DT_N_S_clocks_S_pll_2_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_pll_clock #define DT_N_S_clocks_S_pll_2_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_PLL_CLOCK -#define DT_N_S_clocks_S_pll_2_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_clocks_S_pll_2_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_clocks_S_pll_2, compatible, 0) #define DT_N_S_clocks_S_pll_2_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_clocks_S_pll_2, compatible, 0) #define DT_N_S_clocks_S_pll_2_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_clocks_S_pll_2, compatible, 0, __VA_ARGS__) #define DT_N_S_clocks_S_pll_2_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_clocks_S_pll_2, compatible, 0, __VA_ARGS__) #define DT_N_S_clocks_S_pll_2_P_compatible_LEN 1 #define DT_N_S_clocks_S_pll_2_P_compatible_EXISTS 1 -#define DT_N_S_clocks_S_pll_2_P_reg {2 /* 0x2 */} -#define DT_N_S_clocks_S_pll_2_P_reg_IDX_0 2 +#define DT_N_S_clocks_S_pll_2_P_reg {2} #define DT_N_S_clocks_S_pll_2_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_clocks_S_pll_2_P_reg_IDX_0 2 #define DT_N_S_clocks_S_pll_2_P_reg_EXISTS 1 #define DT_N_S_clocks_S_pll_2_P_zephyr_deferred_init 0 #define DT_N_S_clocks_S_pll_2_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_clocks_S_pll_2_P_wakeup_source 0 +#define DT_N_S_clocks_S_pll_2_P_wakeup_source_EXISTS 1 +#define DT_N_S_clocks_S_pll_2_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_clocks_S_pll_2_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /cpus @@ -14847,6 +15233,9 @@ /* Node's name with unit-address: */ #define DT_N_S_cpus_FULL_NAME "cpus" +#define DT_N_S_cpus_FULL_NAME_UNQUOTED cpus +#define DT_N_S_cpus_FULL_NAME_TOKEN cpus +#define DT_N_S_cpus_FULL_NAME_UPPER_TOKEN CPUS /* Node parent (/) identifier: */ #define DT_N_S_cpus_PARENT DT_N @@ -14877,11 +15266,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_REQUIRES_ORDS \ - 0, /* / */ + 0, /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_SUPPORTS_ORDS \ - 103, /* /cpus/cpu@0 */ + 103, /* Existence and alternate IDs: */ #define DT_N_S_cpus_EXISTS 1 @@ -14916,6 +15305,9 @@ /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_FULL_NAME "cpu@0" +#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UNQUOTED cpu@0 +#define DT_N_S_cpus_S_cpu_0_FULL_NAME_TOKEN cpu_0 +#define DT_N_S_cpus_S_cpu_0_FULL_NAME_UPPER_TOKEN CPU_0 /* Node parent (/cpus) identifier: */ #define DT_N_S_cpus_S_cpu_0_PARENT DT_N_S_cpus @@ -14946,11 +15338,11 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_REQUIRES_ORDS \ - 102, /* /cpus */ + 102, /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_SUPPORTS_ORDS \ - 104, /* /cpus/cpu@0/mpu@e000ed90 */ + 104, /* Existence and alternate IDs: */ #define DT_N_S_cpus_S_cpu_0_EXISTS 1 @@ -14960,7 +15352,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_cpus_S_cpu_0_REG_IDX_0_VAL_ADDRESS 0 #define DT_N_S_cpus_S_cpu_0_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_IRQ_NUM 0 @@ -14976,28 +15368,28 @@ #define DT_N_S_cpus_S_cpu_0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0 -#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_compatible {"arm,cortex-m7"} +#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0 "arm,cortex-m7" #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UNQUOTED arm,cortex-m7 #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_TOKEN arm_cortex_m7 #define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_CORTEX_M7 -#define DT_N_S_cpus_S_cpu_0_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0, compatible, 0) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_P_compatible_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_P_reg {0 /* 0x0 */} -#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0 +#define DT_N_S_cpus_S_cpu_0_P_reg {0} #define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_P_reg_IDX_0 0 #define DT_N_S_cpus_S_cpu_0_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_P_wakeup_source 0 +#define DT_N_S_cpus_S_cpu_0_P_wakeup_source_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_cpus_S_cpu_0_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /cpus/cpu@0/mpu@e000ed90 @@ -15016,6 +15408,9 @@ /* Node's name with unit-address: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME "mpu@e000ed90" +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME_UNQUOTED mpu@e000ed90 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME_TOKEN mpu_e000ed90 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FULL_NAME_UPPER_TOKEN MPU_E000ED90 /* Node parent (/cpus/cpu@0) identifier: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PARENT DT_N_S_cpus_S_cpu_0 @@ -15046,7 +15441,7 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REQUIRES_ORDS \ - 103, /* /cpus/cpu@0 */ + 103, /* Ordinals for what depends directly on this node: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_SUPPORTS_ORDS /* nothing */ @@ -15059,8 +15454,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_NUM 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 /* 0xe000ed90 */ -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 /* 0x40 */ +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_ADDRESS 3758157200 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_REG_IDX_0_VAL_SIZE 64 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_RANGES_NUM 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_FOREACH_RANGE(fn) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_IRQ_NUM 0 @@ -15076,30 +15471,30 @@ #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200, 64} +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible {"arm,armv7m-mpu"} +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0 "arm,armv7m-mpu" #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UNQUOTED arm,armv7m-mpu #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_TOKEN arm_armv7m_mpu #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV7M_MPU -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, compatible, 0, __VA_ARGS__) #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_LEN 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_compatible_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg {3758157200 /* 0xe000ed90 */, 64 /* 0x40 */} -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0 3758157200 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1 64 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_reg_EXISTS 1 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init 0 #define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source 0 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_wakeup_source_EXISTS 1 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /gpio_keys @@ -15118,12 +15513,15 @@ /* Node's name with unit-address: */ #define DT_N_S_gpio_keys_FULL_NAME "gpio_keys" +#define DT_N_S_gpio_keys_FULL_NAME_UNQUOTED gpio_keys +#define DT_N_S_gpio_keys_FULL_NAME_TOKEN gpio_keys +#define DT_N_S_gpio_keys_FULL_NAME_UPPER_TOKEN GPIO_KEYS /* Node parent (/) identifier: */ #define DT_N_S_gpio_keys_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_gpio_keys_CHILD_IDX 21 +#define DT_N_S_gpio_keys_CHILD_IDX 22 /* Helpers for dealing with node labels: */ #define DT_N_S_gpio_keys_NODELABEL_NUM 0 @@ -15148,12 +15546,12 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_keys_REQUIRES_ORDS \ - 0, /* / */ \ - 77, /* /soc/pin-controller@58020000/gpio@58020800 */ + 0, \ + 77, /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_keys_SUPPORTS_ORDS \ - 106, /* /gpio_keys/button_0 */ + 106, /* Existence and alternate IDs: */ #define DT_N_S_gpio_keys_EXISTS 1 @@ -15172,16 +15570,18 @@ #define DT_N_S_gpio_keys_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_gpio_keys_P_wakeup_source 0 -#define DT_N_S_gpio_keys_P_wakeup_source_EXISTS 1 -#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_gpio_keys_P_debounce_interval_ms 30 +#define DT_N_S_gpio_keys_P_debounce_interval_ms_EXISTS 1 +#define DT_N_S_gpio_keys_P_polling_mode 0 +#define DT_N_S_gpio_keys_P_polling_mode_EXISTS 1 +#define DT_N_S_gpio_keys_P_no_disconnect 0 +#define DT_N_S_gpio_keys_P_no_disconnect_EXISTS 1 #define DT_N_S_gpio_keys_P_compatible {"gpio-keys"} +#define DT_N_S_gpio_keys_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_gpio_keys_P_compatible_IDX_0 "gpio-keys" #define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_UNQUOTED gpio-keys #define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_TOKEN gpio_keys #define DT_N_S_gpio_keys_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_KEYS -#define DT_N_S_gpio_keys_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_gpio_keys, compatible, 0) #define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_gpio_keys, compatible, 0) #define DT_N_S_gpio_keys_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_gpio_keys, compatible, 0, __VA_ARGS__) @@ -15190,10 +15590,10 @@ #define DT_N_S_gpio_keys_P_compatible_EXISTS 1 #define DT_N_S_gpio_keys_P_zephyr_deferred_init 0 #define DT_N_S_gpio_keys_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_gpio_keys_P_debounce_interval_ms 30 -#define DT_N_S_gpio_keys_P_debounce_interval_ms_EXISTS 1 -#define DT_N_S_gpio_keys_P_polling_mode 0 -#define DT_N_S_gpio_keys_P_polling_mode_EXISTS 1 +#define DT_N_S_gpio_keys_P_wakeup_source 0 +#define DT_N_S_gpio_keys_P_wakeup_source_EXISTS 1 +#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_gpio_keys_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /gpio_keys/button_0 @@ -15209,6 +15609,9 @@ /* Node's name with unit-address: */ #define DT_N_S_gpio_keys_S_button_0_FULL_NAME "button_0" +#define DT_N_S_gpio_keys_S_button_0_FULL_NAME_UNQUOTED button_0 +#define DT_N_S_gpio_keys_S_button_0_FULL_NAME_TOKEN button_0 +#define DT_N_S_gpio_keys_S_button_0_FULL_NAME_UPPER_TOKEN BUTTON_0 /* Node parent (/gpio_keys) identifier: */ #define DT_N_S_gpio_keys_S_button_0_PARENT DT_N_S_gpio_keys @@ -15239,8 +15642,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_gpio_keys_S_button_0_REQUIRES_ORDS \ - 77, /* /soc/pin-controller@58020000/gpio@58020800 */ \ - 105, /* /gpio_keys */ + 77, \ + 105, /* Ordinals for what depends directly on this node: */ #define DT_N_S_gpio_keys_S_button_0_SUPPORTS_ORDS /* nothing */ @@ -15294,12 +15697,15 @@ /* Node's name with unit-address: */ #define DT_N_S_leds_FULL_NAME "leds" +#define DT_N_S_leds_FULL_NAME_UNQUOTED leds +#define DT_N_S_leds_FULL_NAME_TOKEN leds +#define DT_N_S_leds_FULL_NAME_UPPER_TOKEN LEDS /* Node parent (/) identifier: */ #define DT_N_S_leds_PARENT DT_N /* Node's index in its parent's list of children: */ -#define DT_N_S_leds_CHILD_IDX 20 +#define DT_N_S_leds_CHILD_IDX 21 /* Helpers for dealing with node labels: */ #define DT_N_S_leds_NODELABEL_NUM 0 @@ -15324,16 +15730,16 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_REQUIRES_ORDS \ - 0, /* / */ \ - 79, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 82, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 83, /* /soc/pin-controller@58020000/gpio@58022400 */ + 0, \ + 79, \ + 82, \ + 83, /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_SUPPORTS_ORDS \ - 108, /* /leds/led_0 */ \ - 109, /* /leds/led_1 */ \ - 110, /* /leds/led_2 */ + 108, \ + 109, \ + 110, /* Existence and alternate IDs: */ #define DT_N_S_leds_EXISTS 1 @@ -15353,11 +15759,11 @@ /* Generic property macros: */ #define DT_N_S_leds_P_compatible {"gpio-leds"} +#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_leds_P_compatible_IDX_0 "gpio-leds" #define DT_N_S_leds_P_compatible_IDX_0_STRING_UNQUOTED gpio-leds #define DT_N_S_leds_P_compatible_IDX_0_STRING_TOKEN gpio_leds #define DT_N_S_leds_P_compatible_IDX_0_STRING_UPPER_TOKEN GPIO_LEDS -#define DT_N_S_leds_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_leds, compatible, 0) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_leds, compatible, 0) #define DT_N_S_leds_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_leds, compatible, 0, __VA_ARGS__) @@ -15379,6 +15785,9 @@ /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_0_FULL_NAME "led_0" +#define DT_N_S_leds_S_led_0_FULL_NAME_UNQUOTED led_0 +#define DT_N_S_leds_S_led_0_FULL_NAME_TOKEN led_0 +#define DT_N_S_leds_S_led_0_FULL_NAME_UPPER_TOKEN LED_0 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_0_PARENT DT_N_S_leds @@ -15409,8 +15818,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_0_REQUIRES_ORDS \ - 82, /* /soc/pin-controller@58020000/gpio@58022000 */ \ - 107, /* /leds */ + 82, \ + 107, /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_0_SUPPORTS_ORDS /* nothing */ @@ -15459,6 +15868,9 @@ /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_1_FULL_NAME "led_1" +#define DT_N_S_leds_S_led_1_FULL_NAME_UNQUOTED led_1 +#define DT_N_S_leds_S_led_1_FULL_NAME_TOKEN led_1 +#define DT_N_S_leds_S_led_1_FULL_NAME_UPPER_TOKEN LED_1 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_1_PARENT DT_N_S_leds @@ -15489,8 +15901,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_1_REQUIRES_ORDS \ - 83, /* /soc/pin-controller@58020000/gpio@58022400 */ \ - 107, /* /leds */ + 83, \ + 107, /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_1_SUPPORTS_ORDS /* nothing */ @@ -15539,6 +15951,9 @@ /* Node's name with unit-address: */ #define DT_N_S_leds_S_led_2_FULL_NAME "led_2" +#define DT_N_S_leds_S_led_2_FULL_NAME_UNQUOTED led_2 +#define DT_N_S_leds_S_led_2_FULL_NAME_TOKEN led_2 +#define DT_N_S_leds_S_led_2_FULL_NAME_UPPER_TOKEN LED_2 /* Node parent (/leds) identifier: */ #define DT_N_S_leds_S_led_2_PARENT DT_N_S_leds @@ -15569,8 +15984,8 @@ /* Ordinals for what this node depends on directly: */ #define DT_N_S_leds_S_led_2_REQUIRES_ORDS \ - 79, /* /soc/pin-controller@58020000/gpio@58021000 */ \ - 107, /* /leds */ + 79, \ + 107, /* Ordinals for what depends directly on this node: */ #define DT_N_S_leds_S_led_2_SUPPORTS_ORDS /* nothing */ @@ -15604,6 +16019,293 @@ #define DT_N_S_leds_S_led_2_P_gpios_LEN 1 #define DT_N_S_leds_S_led_2_P_gpios_EXISTS 1 +/* + * Devicetree node: /mcos + * + * Node identifier: DT_N_S_mcos + */ + +/* Node's full path: */ +#define DT_N_S_mcos_PATH "/mcos" + +/* Node's name with unit-address: */ +#define DT_N_S_mcos_FULL_NAME "mcos" +#define DT_N_S_mcos_FULL_NAME_UNQUOTED mcos +#define DT_N_S_mcos_FULL_NAME_TOKEN mcos +#define DT_N_S_mcos_FULL_NAME_UPPER_TOKEN MCOS + +/* Node parent (/) identifier: */ +#define DT_N_S_mcos_PARENT DT_N + +/* Node's index in its parent's list of children: */ +#define DT_N_S_mcos_CHILD_IDX 6 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_mcos_NODELABEL_NUM 0 +#define DT_N_S_mcos_FOREACH_NODELABEL(fn) +#define DT_N_S_mcos_FOREACH_NODELABEL_VARGS(fn, ...) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_mcos_CHILD_NUM 2 +#define DT_N_S_mcos_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_mcos_FOREACH_CHILD(fn) fn(DT_N_S_mcos_S_mco1) fn(DT_N_S_mcos_S_mco2) +#define DT_N_S_mcos_FOREACH_CHILD_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos_S_mco2) +#define DT_N_S_mcos_FOREACH_CHILD_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, __VA_ARGS__) fn(DT_N_S_mcos_S_mco2, __VA_ARGS__) +#define DT_N_S_mcos_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_mcos_S_mco2, __VA_ARGS__) +#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_mcos_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_mcos_ORD 111 +#define DT_N_S_mcos_ORD_STR_SORTABLE 00111 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_mcos_REQUIRES_ORDS \ + 0, + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_mcos_SUPPORTS_ORDS \ + 112, \ + 113, + +/* Existence and alternate IDs: */ +#define DT_N_S_mcos_EXISTS 1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_mcos_REG_NUM 0 +#define DT_N_S_mcos_RANGES_NUM 0 +#define DT_N_S_mcos_FOREACH_RANGE(fn) +#define DT_N_S_mcos_IRQ_NUM 0 +#define DT_N_S_mcos_IRQ_LEVEL 0 +#define DT_N_S_mcos_STATUS_okay 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_mcos_PINCTRL_NUM 0 + +/* (No generic property macros) */ + +/* + * Devicetree node: /mcos/mco1 + * + * Node identifier: DT_N_S_mcos_S_mco1 + * + * Binding (compatible = st,stm32-clock-mco): + * $ZEPHYR_BASE/dts/bindings/clock/st,stm32-clock-mco.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_mcos_S_mco1_PATH "/mcos/mco1" + +/* Node's name with unit-address: */ +#define DT_N_S_mcos_S_mco1_FULL_NAME "mco1" +#define DT_N_S_mcos_S_mco1_FULL_NAME_UNQUOTED mco1 +#define DT_N_S_mcos_S_mco1_FULL_NAME_TOKEN mco1 +#define DT_N_S_mcos_S_mco1_FULL_NAME_UPPER_TOKEN MCO1 + +/* Node parent (/mcos) identifier: */ +#define DT_N_S_mcos_S_mco1_PARENT DT_N_S_mcos + +/* Node's index in its parent's list of children: */ +#define DT_N_S_mcos_S_mco1_CHILD_IDX 0 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_mcos_S_mco1_NODELABEL_NUM 1 +#define DT_N_S_mcos_S_mco1_FOREACH_NODELABEL(fn) fn(mco1) +#define DT_N_S_mcos_S_mco1_FOREACH_NODELABEL_VARGS(fn, ...) fn(mco1, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_mcos_S_mco1_CHILD_NUM 0 +#define DT_N_S_mcos_S_mco1_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD(fn) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_mcos_S_mco1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_mcos_S_mco1_ORD 112 +#define DT_N_S_mcos_S_mco1_ORD_STR_SORTABLE 00112 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_mcos_S_mco1_REQUIRES_ORDS \ + 111, + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_mcos_S_mco1_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_mcos_S_mco1_EXISTS 1 +#define DT_N_INST_0_st_stm32_clock_mco DT_N_S_mcos_S_mco1 +#define DT_N_NODELABEL_mco1 DT_N_S_mcos_S_mco1 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_mcos_S_mco1_REG_NUM 0 +#define DT_N_S_mcos_S_mco1_RANGES_NUM 0 +#define DT_N_S_mcos_S_mco1_FOREACH_RANGE(fn) +#define DT_N_S_mcos_S_mco1_IRQ_NUM 0 +#define DT_N_S_mcos_S_mco1_IRQ_LEVEL 0 +#define DT_N_S_mcos_S_mco1_COMPAT_MATCHES_st_stm32_clock_mco 1 +#define DT_N_S_mcos_S_mco1_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco1_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_mcos_S_mco1_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco1_COMPAT_MODEL_IDX_0 "stm32-clock-mco" +#define DT_N_S_mcos_S_mco1_STATUS_disabled 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_mcos_S_mco1_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_mcos_S_mco1_P_status "disabled" +#define DT_N_S_mcos_S_mco1_P_status_STRING_UNQUOTED disabled +#define DT_N_S_mcos_S_mco1_P_status_STRING_TOKEN disabled +#define DT_N_S_mcos_S_mco1_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_mcos_S_mco1_P_status_IDX_0 "disabled" +#define DT_N_S_mcos_S_mco1_P_status_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_mcos_S_mco1_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco1, status, 0) +#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1, status, 0) +#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, status, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco1_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, status, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco1_P_status_LEN 1 +#define DT_N_S_mcos_S_mco1_P_status_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_compatible {"st,stm32-clock-mco"} +#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0 "st,stm32-clock-mco" +#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-clock-mco +#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_STRING_TOKEN st_stm32_clock_mco +#define DT_N_S_mcos_S_mco1_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_CLOCK_MCO +#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco1, compatible, 0) +#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco1, compatible, 0) +#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco1, compatible, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco1_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco1, compatible, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco1_P_compatible_LEN 1 +#define DT_N_S_mcos_S_mco1_P_compatible_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_zephyr_deferred_init 0 +#define DT_N_S_mcos_S_mco1_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_wakeup_source 0 +#define DT_N_S_mcos_S_mco1_P_wakeup_source_EXISTS 1 +#define DT_N_S_mcos_S_mco1_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_mcos_S_mco1_P_zephyr_pm_device_runtime_auto_EXISTS 1 + +/* + * Devicetree node: /mcos/mco2 + * + * Node identifier: DT_N_S_mcos_S_mco2 + * + * Binding (compatible = st,stm32-clock-mco): + * $ZEPHYR_BASE/dts/bindings/clock/st,stm32-clock-mco.yaml + * + * (Descriptions have moved to the Devicetree Bindings Index + * in the documentation.) + */ + +/* Node's full path: */ +#define DT_N_S_mcos_S_mco2_PATH "/mcos/mco2" + +/* Node's name with unit-address: */ +#define DT_N_S_mcos_S_mco2_FULL_NAME "mco2" +#define DT_N_S_mcos_S_mco2_FULL_NAME_UNQUOTED mco2 +#define DT_N_S_mcos_S_mco2_FULL_NAME_TOKEN mco2 +#define DT_N_S_mcos_S_mco2_FULL_NAME_UPPER_TOKEN MCO2 + +/* Node parent (/mcos) identifier: */ +#define DT_N_S_mcos_S_mco2_PARENT DT_N_S_mcos + +/* Node's index in its parent's list of children: */ +#define DT_N_S_mcos_S_mco2_CHILD_IDX 1 + +/* Helpers for dealing with node labels: */ +#define DT_N_S_mcos_S_mco2_NODELABEL_NUM 1 +#define DT_N_S_mcos_S_mco2_FOREACH_NODELABEL(fn) fn(mco2) +#define DT_N_S_mcos_S_mco2_FOREACH_NODELABEL_VARGS(fn, ...) fn(mco2, __VA_ARGS__) + +/* Helper macros for child nodes of this node. */ +#define DT_N_S_mcos_S_mco2_CHILD_NUM 0 +#define DT_N_S_mcos_S_mco2_CHILD_NUM_STATUS_OKAY 0 +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD(fn) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_SEP(fn, sep) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_VARGS(fn, ...) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_SEP_VARGS(fn, sep, ...) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY(fn) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY_SEP(fn, sep) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY_VARGS(fn, ...) +#define DT_N_S_mcos_S_mco2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) + +/* Node's dependency ordinal: */ +#define DT_N_S_mcos_S_mco2_ORD 113 +#define DT_N_S_mcos_S_mco2_ORD_STR_SORTABLE 00113 + +/* Ordinals for what this node depends on directly: */ +#define DT_N_S_mcos_S_mco2_REQUIRES_ORDS \ + 111, + +/* Ordinals for what depends directly on this node: */ +#define DT_N_S_mcos_S_mco2_SUPPORTS_ORDS /* nothing */ + +/* Existence and alternate IDs: */ +#define DT_N_S_mcos_S_mco2_EXISTS 1 +#define DT_N_INST_1_st_stm32_clock_mco DT_N_S_mcos_S_mco2 +#define DT_N_NODELABEL_mco2 DT_N_S_mcos_S_mco2 + +/* Macros for properties that are special in the specification: */ +#define DT_N_S_mcos_S_mco2_REG_NUM 0 +#define DT_N_S_mcos_S_mco2_RANGES_NUM 0 +#define DT_N_S_mcos_S_mco2_FOREACH_RANGE(fn) +#define DT_N_S_mcos_S_mco2_IRQ_NUM 0 +#define DT_N_S_mcos_S_mco2_IRQ_LEVEL 0 +#define DT_N_S_mcos_S_mco2_COMPAT_MATCHES_st_stm32_clock_mco 1 +#define DT_N_S_mcos_S_mco2_COMPAT_VENDOR_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco2_COMPAT_VENDOR_IDX_0 "STMicroelectronics" +#define DT_N_S_mcos_S_mco2_COMPAT_MODEL_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco2_COMPAT_MODEL_IDX_0 "stm32-clock-mco" +#define DT_N_S_mcos_S_mco2_STATUS_disabled 1 + +/* Pin control (pinctrl-, pinctrl-names) properties: */ +#define DT_N_S_mcos_S_mco2_PINCTRL_NUM 0 + +/* Generic property macros: */ +#define DT_N_S_mcos_S_mco2_P_status "disabled" +#define DT_N_S_mcos_S_mco2_P_status_STRING_UNQUOTED disabled +#define DT_N_S_mcos_S_mco2_P_status_STRING_TOKEN disabled +#define DT_N_S_mcos_S_mco2_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_mcos_S_mco2_P_status_IDX_0 "disabled" +#define DT_N_S_mcos_S_mco2_P_status_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_mcos_S_mco2_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco2, status, 0) +#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco2, status, 0) +#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco2, status, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco2_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco2, status, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco2_P_status_LEN 1 +#define DT_N_S_mcos_S_mco2_P_status_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_compatible {"st,stm32-clock-mco"} +#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0 "st,stm32-clock-mco" +#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-clock-mco +#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_STRING_TOKEN st_stm32_clock_mco +#define DT_N_S_mcos_S_mco2_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_CLOCK_MCO +#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_mcos_S_mco2, compatible, 0) +#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_mcos_S_mco2, compatible, 0) +#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_mcos_S_mco2, compatible, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco2_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_mcos_S_mco2, compatible, 0, __VA_ARGS__) +#define DT_N_S_mcos_S_mco2_P_compatible_LEN 1 +#define DT_N_S_mcos_S_mco2_P_compatible_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_zephyr_deferred_init 0 +#define DT_N_S_mcos_S_mco2_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_wakeup_source 0 +#define DT_N_S_mcos_S_mco2_P_wakeup_source_EXISTS 1 +#define DT_N_S_mcos_S_mco2_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_mcos_S_mco2_P_zephyr_pm_device_runtime_auto_EXISTS 1 + /* * Devicetree node: /soc/adc@40022100 * @@ -15621,6 +16323,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022100_FULL_NAME "adc@40022100" +#define DT_N_S_soc_S_adc_40022100_FULL_NAME_UNQUOTED adc@40022100 +#define DT_N_S_soc_S_adc_40022100_FULL_NAME_TOKEN adc_40022100 +#define DT_N_S_soc_S_adc_40022100_FULL_NAME_UPPER_TOKEN ADC_40022100 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_adc_40022100_PARENT DT_N_S_soc @@ -15646,14 +16351,14 @@ #define DT_N_S_soc_S_adc_40022100_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022100_ORD 111 -#define DT_N_S_soc_S_adc_40022100_ORD_STR_SORTABLE 00111 +#define DT_N_S_soc_S_adc_40022100_ORD 114 +#define DT_N_S_soc_S_adc_40022100_ORD_STR_SORTABLE 00114 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022100_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022100_SUPPORTS_ORDS /* nothing */ @@ -15666,8 +16371,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022100_REG_NUM 1 #define DT_N_S_soc_S_adc_40022100_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_REG_IDX_0_VAL_ADDRESS 1073881344 /* 0x40022100 */ -#define DT_N_S_soc_S_adc_40022100_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_adc_40022100_REG_IDX_0_VAL_ADDRESS 1073881344 +#define DT_N_S_soc_S_adc_40022100_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_adc_40022100_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022100_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022100_IRQ_NUM 1 @@ -15690,50 +16395,12 @@ #define DT_N_S_soc_S_adc_40022100_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022100_P_wakeup_source 0 -#define DT_N_S_soc_S_adc_40022100_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_adc_40022100_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_status "disabled" -#define DT_N_S_soc_S_adc_40022100_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_adc_40022100_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_adc_40022100_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_adc_40022100_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_adc_40022100_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_adc_40022100_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_adc_40022100_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022100, status, 0) -#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022100, status, 0) -#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022100, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022100, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022100_P_status_LEN 1 -#define DT_N_S_soc_S_adc_40022100_P_status_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_compatible {"st,stm32-adc"} -#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0 "st,stm32-adc" -#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc -#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc -#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC -#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022100, compatible, 0) -#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022100, compatible, 0) -#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022100, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022100, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022100_P_compatible_LEN 1 -#define DT_N_S_soc_S_adc_40022100_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_reg {1073881344 /* 0x40022100 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_adc_40022100_P_reg_IDX_0 1073881344 +#define DT_N_S_soc_S_adc_40022100_P_reg {1073881344, 1024} #define DT_N_S_soc_S_adc_40022100_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_adc_40022100_P_reg_IDX_0 1073881344 #define DT_N_S_soc_S_adc_40022100_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_reg_IDX_1 1024 #define DT_N_S_soc_S_adc_40022100_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_0 18 -#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_adc_40022100_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022100_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_adc_40022100_P_clocks_IDX_0_VAL_bus 216 @@ -15746,21 +16413,25 @@ #define DT_N_S_soc_S_adc_40022100_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022100, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022100_P_clocks_LEN 1 #define DT_N_S_soc_S_adc_40022100_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_adc_40022100_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_interrupts {18, 0} +#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_0 18 +#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_adc_40022100_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_adc_40022100_P_vref_mv 3300 #define DT_N_S_soc_S_adc_40022100_P_vref_mv_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_resolutions {8446476 /* 0x80e20c */, 7725580 /* 0x75e20c */, 6742540 /* 0x66e20c */, 5497356 /* 0x53e20c */, 4710924 /* 0x47e20c */} -#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_0 8446476 +#define DT_N_S_soc_S_adc_40022100_P_resolutions {8446476, 7725580, 6742540, 5497356, 4710924} #define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_1 7725580 +#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_0 8446476 #define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_2 6742540 +#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_1 7725580 #define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_3 5497356 +#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_2 6742540 #define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_4 4710924 +#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_3 5497356 #define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_resolutions_IDX_4 4710924 #define DT_N_S_soc_S_adc_40022100_P_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022100, resolutions, 0) \ fn(DT_N_S_soc_S_adc_40022100, resolutions, 1) \ fn(DT_N_S_soc_S_adc_40022100, resolutions, 2) \ @@ -15783,23 +16454,23 @@ fn(DT_N_S_soc_S_adc_40022100, resolutions, 4, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022100_P_resolutions_LEN 5 #define DT_N_S_soc_S_adc_40022100_P_resolutions_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times {2 /* 0x2 */, 3 /* 0x3 */, 9 /* 0x9 */, 17 /* 0x11 */, 33 /* 0x21 */, 65 /* 0x41 */, 388 /* 0x184 */, 811 /* 0x32b */} -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_0 2 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times {2, 3, 9, 17, 33, 65, 388, 811} #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_1 3 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_0 2 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_2 9 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_1 3 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_3 17 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_2 9 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_4 33 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_3 17 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_5 65 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_4 33 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_6 388 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_5 65 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_7 811 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_6 388 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_sampling_times_IDX_7 811 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022100, sampling_times, 0) \ fn(DT_N_S_soc_S_adc_40022100, sampling_times, 1) \ fn(DT_N_S_soc_S_adc_40022100, sampling_times, 2) \ @@ -15835,9 +16506,42 @@ #define DT_N_S_soc_S_adc_40022100_P_sampling_times_LEN 8 #define DT_N_S_soc_S_adc_40022100_P_sampling_times_EXISTS 1 #define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer 1 -#define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer_ENUM_IDX 1 -#define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer_IDX_0_ENUM_VAL_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022100_P_st_adc_sequencer_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_status "disabled" +#define DT_N_S_soc_S_adc_40022100_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_adc_40022100_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_adc_40022100_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_adc_40022100_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_adc_40022100_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_adc_40022100_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022100, status, 0) +#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022100, status, 0) +#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022100, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022100_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022100, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022100_P_status_LEN 1 +#define DT_N_S_soc_S_adc_40022100_P_status_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_compatible {"st,stm32-adc"} +#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0 "st,stm32-adc" +#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc +#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc +#define DT_N_S_soc_S_adc_40022100_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC +#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022100, compatible, 0) +#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022100, compatible, 0) +#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022100, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022100_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022100, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022100_P_compatible_LEN 1 +#define DT_N_S_soc_S_adc_40022100_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_adc_40022100_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_wakeup_source 0 +#define DT_N_S_soc_S_adc_40022100_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_adc_40022100_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_adc_40022100_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/adc@40022300 @@ -15856,6 +16560,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022300_FULL_NAME "adc@40022300" +#define DT_N_S_soc_S_adc_40022300_FULL_NAME_UNQUOTED adc@40022300 +#define DT_N_S_soc_S_adc_40022300_FULL_NAME_TOKEN adc_40022300 +#define DT_N_S_soc_S_adc_40022300_FULL_NAME_UPPER_TOKEN ADC_40022300 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_adc_40022300_PARENT DT_N_S_soc @@ -15881,14 +16588,14 @@ #define DT_N_S_soc_S_adc_40022300_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022300_ORD 112 -#define DT_N_S_soc_S_adc_40022300_ORD_STR_SORTABLE 00112 +#define DT_N_S_soc_S_adc_40022300_ORD 115 +#define DT_N_S_soc_S_adc_40022300_ORD_STR_SORTABLE 00115 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022300_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022300_SUPPORTS_ORDS /* nothing */ @@ -15901,8 +16608,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022300_REG_NUM 1 #define DT_N_S_soc_S_adc_40022300_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_REG_IDX_0_VAL_ADDRESS 1073881856 /* 0x40022300 */ -#define DT_N_S_soc_S_adc_40022300_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_adc_40022300_REG_IDX_0_VAL_ADDRESS 1073881856 +#define DT_N_S_soc_S_adc_40022300_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_adc_40022300_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022300_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022300_IRQ_NUM 1 @@ -15925,50 +16632,12 @@ #define DT_N_S_soc_S_adc_40022300_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022300_P_wakeup_source 0 -#define DT_N_S_soc_S_adc_40022300_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_adc_40022300_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_status "disabled" -#define DT_N_S_soc_S_adc_40022300_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_adc_40022300_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_adc_40022300_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_adc_40022300_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_adc_40022300_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_adc_40022300_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_adc_40022300_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022300, status, 0) -#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022300, status, 0) -#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022300, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022300, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022300_P_status_LEN 1 -#define DT_N_S_soc_S_adc_40022300_P_status_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_compatible {"st,stm32-adc"} -#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0 "st,stm32-adc" -#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc -#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc -#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC -#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022300, compatible, 0) -#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022300, compatible, 0) -#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022300, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022300, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_adc_40022300_P_compatible_LEN 1 -#define DT_N_S_soc_S_adc_40022300_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_reg {1073881856 /* 0x40022300 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_adc_40022300_P_reg_IDX_0 1073881856 +#define DT_N_S_soc_S_adc_40022300_P_reg {1073881856, 1024} #define DT_N_S_soc_S_adc_40022300_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_adc_40022300_P_reg_IDX_0 1073881856 #define DT_N_S_soc_S_adc_40022300_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_reg_IDX_1 1024 #define DT_N_S_soc_S_adc_40022300_P_reg_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_interrupts {18 /* 0x12 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_0 18 -#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_adc_40022300_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_adc_40022300_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_adc_40022300_P_clocks_IDX_0_VAL_bus 216 @@ -15981,21 +16650,25 @@ #define DT_N_S_soc_S_adc_40022300_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022300, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022300_P_clocks_LEN 1 #define DT_N_S_soc_S_adc_40022300_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_adc_40022300_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_interrupts {18, 0} +#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_0 18 +#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_adc_40022300_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_adc_40022300_P_vref_mv 3300 #define DT_N_S_soc_S_adc_40022300_P_vref_mv_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_resolutions {8446476 /* 0x80e20c */, 7725580 /* 0x75e20c */, 6742540 /* 0x66e20c */, 5497356 /* 0x53e20c */, 4710924 /* 0x47e20c */} -#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_0 8446476 +#define DT_N_S_soc_S_adc_40022300_P_resolutions {8446476, 7725580, 6742540, 5497356, 4710924} #define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_1 7725580 +#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_0 8446476 #define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_2 6742540 +#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_1 7725580 #define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_3 5497356 +#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_2 6742540 #define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_4 4710924 +#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_3 5497356 #define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_resolutions_IDX_4 4710924 #define DT_N_S_soc_S_adc_40022300_P_resolutions_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022300, resolutions, 0) \ fn(DT_N_S_soc_S_adc_40022300, resolutions, 1) \ fn(DT_N_S_soc_S_adc_40022300, resolutions, 2) \ @@ -16018,23 +16691,23 @@ fn(DT_N_S_soc_S_adc_40022300, resolutions, 4, __VA_ARGS__) #define DT_N_S_soc_S_adc_40022300_P_resolutions_LEN 5 #define DT_N_S_soc_S_adc_40022300_P_resolutions_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times {2 /* 0x2 */, 3 /* 0x3 */, 9 /* 0x9 */, 17 /* 0x11 */, 33 /* 0x21 */, 65 /* 0x41 */, 388 /* 0x184 */, 811 /* 0x32b */} -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_0 2 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times {2, 3, 9, 17, 33, 65, 388, 811} #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_1 3 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_0 2 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_2 9 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_1 3 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_3 17 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_2 9 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_4 33 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_3 17 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_5 65 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_4 33 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_6 388 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_5 65 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_7 811 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_6 388 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_sampling_times_IDX_7 811 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022300, sampling_times, 0) \ fn(DT_N_S_soc_S_adc_40022300, sampling_times, 1) \ fn(DT_N_S_soc_S_adc_40022300, sampling_times, 2) \ @@ -16070,9 +16743,42 @@ #define DT_N_S_soc_S_adc_40022300_P_sampling_times_LEN 8 #define DT_N_S_soc_S_adc_40022300_P_sampling_times_EXISTS 1 #define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer 1 -#define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer_ENUM_IDX 1 -#define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer_IDX_0_ENUM_VAL_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022300_P_st_adc_sequencer_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_status "disabled" +#define DT_N_S_soc_S_adc_40022300_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_adc_40022300_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_adc_40022300_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_adc_40022300_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_adc_40022300_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_adc_40022300_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022300, status, 0) +#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022300, status, 0) +#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022300, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022300_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022300, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022300_P_status_LEN 1 +#define DT_N_S_soc_S_adc_40022300_P_status_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_compatible {"st,stm32-adc"} +#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0 "st,stm32-adc" +#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-adc +#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_STRING_TOKEN st_stm32_adc +#define DT_N_S_soc_S_adc_40022300_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ADC +#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022300, compatible, 0) +#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022300, compatible, 0) +#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022300, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022300_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_adc_40022300, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_adc_40022300_P_compatible_LEN 1 +#define DT_N_S_soc_S_adc_40022300_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_adc_40022300_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_wakeup_source 0 +#define DT_N_S_soc_S_adc_40022300_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_adc_40022300_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_adc_40022300_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/bdma@58025400 @@ -16091,6 +16797,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_bdma_58025400_FULL_NAME "bdma@58025400" +#define DT_N_S_soc_S_bdma_58025400_FULL_NAME_UNQUOTED bdma@58025400 +#define DT_N_S_soc_S_bdma_58025400_FULL_NAME_TOKEN bdma_58025400 +#define DT_N_S_soc_S_bdma_58025400_FULL_NAME_UPPER_TOKEN BDMA_58025400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_bdma_58025400_PARENT DT_N_S_soc @@ -16116,14 +16825,14 @@ #define DT_N_S_soc_S_bdma_58025400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_bdma_58025400_ORD 113 -#define DT_N_S_soc_S_bdma_58025400_ORD_STR_SORTABLE 00113 +#define DT_N_S_soc_S_bdma_58025400_ORD 116 +#define DT_N_S_soc_S_bdma_58025400_ORD_STR_SORTABLE 00116 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_bdma_58025400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_bdma_58025400_SUPPORTS_ORDS /* nothing */ @@ -16136,8 +16845,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_bdma_58025400_REG_NUM 1 #define DT_N_S_soc_S_bdma_58025400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_REG_IDX_0_VAL_ADDRESS 1476547584 /* 0x58025400 */ -#define DT_N_S_soc_S_bdma_58025400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_bdma_58025400_REG_IDX_0_VAL_ADDRESS 1476547584 +#define DT_N_S_soc_S_bdma_58025400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_bdma_58025400_RANGES_NUM 0 #define DT_N_S_soc_S_bdma_58025400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_bdma_58025400_IRQ_NUM 8 @@ -16209,20 +16918,60 @@ #define DT_N_S_soc_S_bdma_58025400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_bdma_58025400_P_wakeup_source 0 -#define DT_N_S_soc_S_bdma_58025400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_bdma_58025400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_reg {1476547584, 1024} +#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_0 1476547584 +#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_bdma_58025400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts {129, 0, 130, 0, 131, 0, 132, 0, 133, 0, 134, 0, 135, 0, 136, 0} +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_0 129 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_2 130 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_4 131 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_6 132 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_8_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_8 133 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_9_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_9 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_10_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_10 134 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_11_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_11 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_12_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_12 135 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_13_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_13 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_14_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_14 136 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_15_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_15 0 +#define DT_N_S_soc_S_bdma_58025400_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_st_mem2mem 1 +#define DT_N_S_soc_S_bdma_58025400_P_st_mem2mem_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_dma_offset 0 +#define DT_N_S_soc_S_bdma_58025400_P_dma_offset_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_dma_requests 8 +#define DT_N_S_soc_S_bdma_58025400_P_dma_requests_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_status "disabled" #define DT_N_S_soc_S_bdma_58025400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_bdma_58025400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_bdma_58025400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_bdma_58025400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_bdma_58025400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_bdma_58025400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_bdma_58025400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_bdma_58025400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_bdma_58025400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_bdma_58025400, status, 0) #define DT_N_S_soc_S_bdma_58025400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_bdma_58025400, status, 0) #define DT_N_S_soc_S_bdma_58025400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_bdma_58025400, status, 0, __VA_ARGS__) @@ -16230,57 +16979,17 @@ #define DT_N_S_soc_S_bdma_58025400_P_status_LEN 1 #define DT_N_S_soc_S_bdma_58025400_P_status_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_compatible {"st,stm32-bdma"} +#define DT_N_S_soc_S_bdma_58025400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_compatible_IDX_0 "st,stm32-bdma" #define DT_N_S_soc_S_bdma_58025400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-bdma #define DT_N_S_soc_S_bdma_58025400_P_compatible_IDX_0_STRING_TOKEN st_stm32_bdma #define DT_N_S_soc_S_bdma_58025400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_BDMA -#define DT_N_S_soc_S_bdma_58025400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_bdma_58025400, compatible, 0) #define DT_N_S_soc_S_bdma_58025400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_bdma_58025400, compatible, 0) #define DT_N_S_soc_S_bdma_58025400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_bdma_58025400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_bdma_58025400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_bdma_58025400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_bdma_58025400_P_compatible_LEN 1 #define DT_N_S_soc_S_bdma_58025400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_reg {1476547584 /* 0x58025400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_0 1476547584 -#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_bdma_58025400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts {129 /* 0x81 */, 0 /* 0x0 */, 130 /* 0x82 */, 0 /* 0x0 */, 131 /* 0x83 */, 0 /* 0x0 */, 132 /* 0x84 */, 0 /* 0x0 */, 133 /* 0x85 */, 0 /* 0x0 */, 134 /* 0x86 */, 0 /* 0x0 */, 135 /* 0x87 */, 0 /* 0x0 */, 136 /* 0x88 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_0 129 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_2 130 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_4 131 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_5 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_6 132 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_7 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_8 133 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_8_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_9 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_9_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_10 134 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_10_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_11 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_11_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_12 135 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_12_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_13 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_13_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_14 136 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_14_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_15 0 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_IDX_15_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_bdma_58025400_P_clocks_IDX_0_VAL_bus 224 @@ -16295,12 +17004,10 @@ #define DT_N_S_soc_S_bdma_58025400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_bdma_58025400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_bdma_58025400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_dma_requests 8 -#define DT_N_S_soc_S_bdma_58025400_P_dma_requests_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_st_mem2mem 1 -#define DT_N_S_soc_S_bdma_58025400_P_st_mem2mem_EXISTS 1 -#define DT_N_S_soc_S_bdma_58025400_P_dma_offset 0 -#define DT_N_S_soc_S_bdma_58025400_P_dma_offset_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_wakeup_source 0 +#define DT_N_S_soc_S_bdma_58025400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_bdma_58025400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_bdma_58025400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/can@4000a000 @@ -16319,6 +17026,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_can_4000a000_FULL_NAME "can@4000a000" +#define DT_N_S_soc_S_can_4000a000_FULL_NAME_UNQUOTED can@4000a000 +#define DT_N_S_soc_S_can_4000a000_FULL_NAME_TOKEN can_4000a000 +#define DT_N_S_soc_S_can_4000a000_FULL_NAME_UPPER_TOKEN CAN_4000A000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_can_4000a000_PARENT DT_N_S_soc @@ -16344,14 +17054,14 @@ #define DT_N_S_soc_S_can_4000a000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_can_4000a000_ORD 114 -#define DT_N_S_soc_S_can_4000a000_ORD_STR_SORTABLE 00114 +#define DT_N_S_soc_S_can_4000a000_ORD 117 +#define DT_N_S_soc_S_can_4000a000_ORD_STR_SORTABLE 00117 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_can_4000a000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_can_4000a000_SUPPORTS_ORDS /* nothing */ @@ -16364,11 +17074,11 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_can_4000a000_REG_NUM 2 #define DT_N_S_soc_S_can_4000a000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_REG_IDX_0_VAL_ADDRESS 1073782784 /* 0x4000a000 */ -#define DT_N_S_soc_S_can_4000a000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_can_4000a000_REG_IDX_0_VAL_ADDRESS 1073782784 +#define DT_N_S_soc_S_can_4000a000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_can_4000a000_REG_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_REG_IDX_1_VAL_ADDRESS 1073785856 /* 0x4000ac00 */ -#define DT_N_S_soc_S_can_4000a000_REG_IDX_1_VAL_SIZE 848 /* 0x350 */ +#define DT_N_S_soc_S_can_4000a000_REG_IDX_1_VAL_ADDRESS 1073785856 +#define DT_N_S_soc_S_can_4000a000_REG_IDX_1_VAL_SIZE 848 #define DT_N_S_soc_S_can_4000a000_REG_NAME_m_can_EXISTS 1 #define DT_N_S_soc_S_can_4000a000_REG_NAME_m_can_VAL_ADDRESS DT_N_S_soc_S_can_4000a000_REG_IDX_0_VAL_ADDRESS #define DT_N_S_soc_S_can_4000a000_REG_NAME_m_can_VAL_SIZE DT_N_S_soc_S_can_4000a000_REG_IDX_0_VAL_SIZE @@ -16426,99 +17136,58 @@ #define DT_N_S_soc_S_can_4000a000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_can_4000a000_P_wakeup_source 0 -#define DT_N_S_soc_S_can_4000a000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_can_4000a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_status "disabled" -#define DT_N_S_soc_S_can_4000a000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_can_4000a000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_can_4000a000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_can_4000a000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_can_4000a000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_can_4000a000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_can_4000a000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, status, 0) -#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, status, 0) -#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_status_LEN 1 -#define DT_N_S_soc_S_can_4000a000_P_status_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_compatible {"st,stm32h7-fdcan"} -#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0 "st,stm32h7-fdcan" -#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-fdcan -#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_fdcan -#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_FDCAN -#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, compatible, 0) -#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, compatible, 0) -#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_compatible_LEN 1 -#define DT_N_S_soc_S_can_4000a000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg {1073782784 /* 0x4000a000 */, 1024 /* 0x400 */, 1073785856 /* 0x4000ac00 */, 848 /* 0x350 */} -#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_0 1073782784 +#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bus 236 +#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bits 256 +#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, clocks, 0) +#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, clocks, 0) +#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_clocks_LEN 1 +#define DT_N_S_soc_S_can_4000a000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_reg {1073782784, 1024, 1073785856, 848} #define DT_N_S_soc_S_can_4000a000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_0 1073782784 #define DT_N_S_soc_S_can_4000a000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_2 1073785856 +#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_can_4000a000_P_reg_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_3 848 +#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_2 1073785856 #define DT_N_S_soc_S_can_4000a000_P_reg_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_reg_IDX_3 848 #define DT_N_S_soc_S_can_4000a000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg_names {"m_can", "message_ram"} -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0 "m_can" -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_STRING_UNQUOTED m_can -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_STRING_TOKEN m_can -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_STRING_UPPER_TOKEN M_CAN -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1 "message_ram" -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_STRING_UNQUOTED message_ram -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_STRING_TOKEN message_ram -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_STRING_UPPER_TOKEN MESSAGE_RAM -#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0) \ - fn(DT_N_S_soc_S_can_4000a000, reg_names, 1) -#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_can_4000a000, reg_names, 1) -#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_can_4000a000, reg_names, 1, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_can_4000a000, reg_names, 1, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_reg_names_LEN 2 -#define DT_N_S_soc_S_can_4000a000_P_reg_names_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_interrupts {19 /* 0x13 */, 0 /* 0x0 */, 21 /* 0x15 */, 0 /* 0x0 */, 63 /* 0x3f */, 0 /* 0x0 */} -#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_0 19 +#define DT_N_S_soc_S_can_4000a000_P_interrupts {19, 0, 21, 0, 63, 0} #define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_0 19 #define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_2 21 +#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_2 21 #define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_4 63 +#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_3 0 #define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_4 63 #define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_interrupts_IDX_5 0 #define DT_N_S_soc_S_can_4000a000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names {"int0", "int1", "calib"} +#define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_0 "int0" #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_0_STRING_UNQUOTED int0 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_0_STRING_TOKEN int0 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN INT0 -#define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_1 "int1" #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_1_STRING_UNQUOTED int1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_1_STRING_TOKEN int1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN INT1 -#define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_2 "calib" #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_2_STRING_UNQUOTED calib #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_2_STRING_TOKEN calib #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN CALIB -#define DT_N_S_soc_S_can_4000a000_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, interrupt_names, 0) \ fn(DT_N_S_soc_S_can_4000a000, interrupt_names, 1) \ fn(DT_N_S_soc_S_can_4000a000, interrupt_names, 2) @@ -16533,37 +17202,23 @@ fn(DT_N_S_soc_S_can_4000a000, interrupt_names, 2, __VA_ARGS__) #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_LEN 3 #define DT_N_S_soc_S_can_4000a000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bus 236 -#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bits 256 -#define DT_N_S_soc_S_can_4000a000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, clocks, 0) -#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, clocks, 0) -#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a000_P_clocks_LEN 1 -#define DT_N_S_soc_S_can_4000a000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_can_4000a000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg {0 /* 0x0 */, 28 /* 0x1c */, 8 /* 0x8 */, 3 /* 0x3 */, 3 /* 0x3 */, 0 /* 0x0 */, 3 /* 0x3 */, 3 /* 0x3 */} -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_0 0 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg {0, 28, 8, 3, 3, 0, 3, 3} #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_1 28 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_0 0 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_2 8 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_1 28 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_3 3 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_2 8 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_4 3 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_3 3 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_5 0 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_4 3 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_6 3 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_5 0 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_7 3 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_6 3 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_IDX_7 3 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, bosch_mram_cfg, 0) \ fn(DT_N_S_soc_S_can_4000a000, bosch_mram_cfg, 1) \ fn(DT_N_S_soc_S_can_4000a000, bosch_mram_cfg, 2) \ @@ -16598,6 +17253,59 @@ fn(DT_N_S_soc_S_can_4000a000, bosch_mram_cfg, 7, __VA_ARGS__) #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_LEN 8 #define DT_N_S_soc_S_can_4000a000_P_bosch_mram_cfg_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_status "disabled" +#define DT_N_S_soc_S_can_4000a000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_can_4000a000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_can_4000a000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_can_4000a000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_can_4000a000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_can_4000a000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, status, 0) +#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, status, 0) +#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_status_LEN 1 +#define DT_N_S_soc_S_can_4000a000_P_status_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_compatible {"st,stm32h7-fdcan"} +#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0 "st,stm32h7-fdcan" +#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-fdcan +#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_fdcan +#define DT_N_S_soc_S_can_4000a000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_FDCAN +#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, compatible, 0) +#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, compatible, 0) +#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_compatible_LEN 1 +#define DT_N_S_soc_S_can_4000a000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_reg_names {"m_can", "message_ram"} +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0 "m_can" +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_STRING_UNQUOTED m_can +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_STRING_TOKEN m_can +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_0_STRING_UPPER_TOKEN M_CAN +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1 "message_ram" +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_STRING_UNQUOTED message_ram +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_STRING_TOKEN message_ram +#define DT_N_S_soc_S_can_4000a000_P_reg_names_IDX_1_STRING_UPPER_TOKEN MESSAGE_RAM +#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0) \ + fn(DT_N_S_soc_S_can_4000a000, reg_names, 1) +#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_can_4000a000, reg_names, 1) +#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_can_4000a000, reg_names, 1, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a000, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_can_4000a000, reg_names, 1, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a000_P_reg_names_LEN 2 +#define DT_N_S_soc_S_can_4000a000_P_reg_names_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_can_4000a000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_wakeup_source 0 +#define DT_N_S_soc_S_can_4000a000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_can_4000a000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_can_4000a000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fdcan2_rx_pb5 @@ -16613,6 +17321,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_FULL_NAME "fdcan2_rx_pb5" +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_FULL_NAME_UNQUOTED fdcan2_rx_pb5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_FULL_NAME_TOKEN fdcan2_rx_pb5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_FULL_NAME_UPPER_TOKEN FDCAN2_RX_PB5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -16638,16 +17349,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD 115 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD_STR_SORTABLE 00115 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD 118 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_ORD_STR_SORTABLE 00118 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_SUPPORTS_ORDS \ - 117, /* /soc/can@4000a400 */ + 120, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_EXISTS 1 @@ -16665,20 +17376,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_pinmux 681 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate "low-speed" @@ -16687,16 +17384,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fdcan2_tx_pb13 @@ -16712,6 +17421,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_FULL_NAME "fdcan2_tx_pb13" +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_FULL_NAME_UNQUOTED fdcan2_tx_pb13 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_FULL_NAME_TOKEN fdcan2_tx_pb13 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_FULL_NAME_UPPER_TOKEN FDCAN2_TX_PB13 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -16737,16 +17449,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD 116 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD_STR_SORTABLE 00116 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD 119 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_ORD_STR_SORTABLE 00119 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_SUPPORTS_ORDS \ - 117, /* /soc/can@4000a400 */ + 120, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_EXISTS 1 @@ -16764,20 +17476,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_pinmux 937 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate "low-speed" @@ -16786,16 +17484,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13_P_output_high_EXISTS 1 /* * Devicetree node: /soc/can@4000a400 @@ -16814,6 +17524,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_can_4000a400_FULL_NAME "can@4000a400" +#define DT_N_S_soc_S_can_4000a400_FULL_NAME_UNQUOTED can@4000a400 +#define DT_N_S_soc_S_can_4000a400_FULL_NAME_TOKEN can_4000a400 +#define DT_N_S_soc_S_can_4000a400_FULL_NAME_UPPER_TOKEN CAN_4000A400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_can_4000a400_PARENT DT_N_S_soc @@ -16839,16 +17552,16 @@ #define DT_N_S_soc_S_can_4000a400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_can_4000a400_ORD 117 -#define DT_N_S_soc_S_can_4000a400_ORD_STR_SORTABLE 00117 +#define DT_N_S_soc_S_can_4000a400_ORD 120 +#define DT_N_S_soc_S_can_4000a400_ORD_STR_SORTABLE 00120 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_can_4000a400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 115, /* /soc/pin-controller@58020000/fdcan2_rx_pb5 */ \ - 116, /* /soc/pin-controller@58020000/fdcan2_tx_pb13 */ + 4, \ + 5, \ + 9, \ + 118, \ + 119, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_can_4000a400_SUPPORTS_ORDS /* nothing */ @@ -16861,11 +17574,11 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_can_4000a400_REG_NUM 2 #define DT_N_S_soc_S_can_4000a400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_REG_IDX_0_VAL_ADDRESS 1073783808 /* 0x4000a400 */ -#define DT_N_S_soc_S_can_4000a400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_can_4000a400_REG_IDX_0_VAL_ADDRESS 1073783808 +#define DT_N_S_soc_S_can_4000a400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_can_4000a400_REG_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_REG_IDX_1_VAL_ADDRESS 1073785856 /* 0x4000ac00 */ -#define DT_N_S_soc_S_can_4000a400_REG_IDX_1_VAL_SIZE 1696 /* 0x6a0 */ +#define DT_N_S_soc_S_can_4000a400_REG_IDX_1_VAL_ADDRESS 1073785856 +#define DT_N_S_soc_S_can_4000a400_REG_IDX_1_VAL_SIZE 1696 #define DT_N_S_soc_S_can_4000a400_REG_NAME_m_can_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_REG_NAME_m_can_VAL_ADDRESS DT_N_S_soc_S_can_4000a400_REG_IDX_0_VAL_ADDRESS #define DT_N_S_soc_S_can_4000a400_REG_NAME_m_can_VAL_SIZE DT_N_S_soc_S_can_4000a400_REG_IDX_0_VAL_SIZE @@ -16930,99 +17643,68 @@ #define DT_N_S_soc_S_can_4000a400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5 /* Generic property macros: */ -#define DT_N_S_soc_S_can_4000a400_P_wakeup_source 0 -#define DT_N_S_soc_S_can_4000a400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_can_4000a400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_status "okay" -#define DT_N_S_soc_S_can_4000a400_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_can_4000a400_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_can_4000a400_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_can_4000a400_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_can_4000a400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_can_4000a400_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_can_4000a400_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, status, 0) -#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, status, 0) -#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_status_LEN 1 -#define DT_N_S_soc_S_can_4000a400_P_status_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_compatible {"st,stm32h7-fdcan"} -#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0 "st,stm32h7-fdcan" -#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-fdcan -#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_fdcan -#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_FDCAN -#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, compatible, 0) -#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, compatible, 0) -#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_compatible_LEN 1 -#define DT_N_S_soc_S_can_4000a400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg {1073783808 /* 0x4000a400 */, 1024 /* 0x400 */, 1073785856 /* 0x4000ac00 */, 1696 /* 0x6a0 */} -#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_0 1073783808 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bus 236 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bits 256 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bus 9 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bits 97360 +#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, clocks, 0) \ + fn(DT_N_S_soc_S_can_4000a400, clocks, 1) +#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, clocks, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_can_4000a400, clocks, 1) +#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, clocks, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_can_4000a400, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_can_4000a400, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_clocks_LEN 2 +#define DT_N_S_soc_S_can_4000a400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_reg {1073783808, 1024, 1073785856, 1696} #define DT_N_S_soc_S_can_4000a400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_0 1073783808 #define DT_N_S_soc_S_can_4000a400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_2 1073785856 +#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_can_4000a400_P_reg_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_3 1696 +#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_2 1073785856 #define DT_N_S_soc_S_can_4000a400_P_reg_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_reg_IDX_3 1696 #define DT_N_S_soc_S_can_4000a400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg_names {"m_can", "message_ram"} -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0 "m_can" -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_STRING_UNQUOTED m_can -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_STRING_TOKEN m_can -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_STRING_UPPER_TOKEN M_CAN -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1 "message_ram" -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_STRING_UNQUOTED message_ram -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_STRING_TOKEN message_ram -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_STRING_UPPER_TOKEN MESSAGE_RAM -#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0) \ - fn(DT_N_S_soc_S_can_4000a400, reg_names, 1) -#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_can_4000a400, reg_names, 1) -#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_can_4000a400, reg_names, 1, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_can_4000a400, reg_names, 1, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_reg_names_LEN 2 -#define DT_N_S_soc_S_can_4000a400_P_reg_names_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_interrupts {20 /* 0x14 */, 0 /* 0x0 */, 22 /* 0x16 */, 0 /* 0x0 */, 63 /* 0x3f */, 0 /* 0x0 */} -#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_0 20 +#define DT_N_S_soc_S_can_4000a400_P_interrupts {20, 0, 22, 0, 63, 0} #define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_0 20 #define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_2 22 +#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_2 22 #define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_4 63 +#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_3 0 #define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_4 63 #define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_interrupts_IDX_5 0 #define DT_N_S_soc_S_can_4000a400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names {"int0", "int1", "calib"} +#define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_0 "int0" #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_0_STRING_UNQUOTED int0 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_0_STRING_TOKEN int0 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN INT0 -#define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_1 "int1" #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_1_STRING_UNQUOTED int1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_1_STRING_TOKEN int1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN INT1 -#define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_2 "calib" #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_2_STRING_UNQUOTED calib #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_2_STRING_TOKEN calib #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN CALIB -#define DT_N_S_soc_S_can_4000a400_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, interrupt_names, 0) \ fn(DT_N_S_soc_S_can_4000a400, interrupt_names, 1) \ fn(DT_N_S_soc_S_can_4000a400, interrupt_names, 2) @@ -17037,47 +17719,23 @@ fn(DT_N_S_soc_S_can_4000a400, interrupt_names, 2, __VA_ARGS__) #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_LEN 3 #define DT_N_S_soc_S_can_4000a400_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bus 236 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bits 256 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bus 9 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bits 97360 -#define DT_N_S_soc_S_can_4000a400_P_clocks_IDX_1_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, clocks, 0) \ - fn(DT_N_S_soc_S_can_4000a400, clocks, 1) -#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, clocks, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_can_4000a400, clocks, 1) -#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, clocks, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_can_4000a400, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_can_4000a400, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_can_4000a400_P_clocks_LEN 2 -#define DT_N_S_soc_S_can_4000a400_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_can_4000a400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg {848 /* 0x350 */, 28 /* 0x1c */, 8 /* 0x8 */, 3 /* 0x3 */, 3 /* 0x3 */, 0 /* 0x0 */, 3 /* 0x3 */, 3 /* 0x3 */} -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_0 848 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg {848, 28, 8, 3, 3, 0, 3, 3} #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_1 28 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_0 848 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_2 8 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_1 28 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_3 3 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_2 8 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_4 3 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_3 3 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_5 0 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_4 3 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_6 3 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_5 0 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_7 3 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_6 3 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_IDX_7 3 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, bosch_mram_cfg, 0) \ fn(DT_N_S_soc_S_can_4000a400, bosch_mram_cfg, 1) \ fn(DT_N_S_soc_S_can_4000a400, bosch_mram_cfg, 2) \ @@ -17112,6 +17770,59 @@ fn(DT_N_S_soc_S_can_4000a400, bosch_mram_cfg, 7, __VA_ARGS__) #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_LEN 8 #define DT_N_S_soc_S_can_4000a400_P_bosch_mram_cfg_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_status "okay" +#define DT_N_S_soc_S_can_4000a400_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_can_4000a400_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_can_4000a400_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_can_4000a400_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_can_4000a400_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_can_4000a400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, status, 0) +#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, status, 0) +#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_status_LEN 1 +#define DT_N_S_soc_S_can_4000a400_P_status_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_compatible {"st,stm32h7-fdcan"} +#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0 "st,stm32h7-fdcan" +#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-fdcan +#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_fdcan +#define DT_N_S_soc_S_can_4000a400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_FDCAN +#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, compatible, 0) +#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, compatible, 0) +#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_compatible_LEN 1 +#define DT_N_S_soc_S_can_4000a400_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_reg_names {"m_can", "message_ram"} +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0 "m_can" +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_STRING_UNQUOTED m_can +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_STRING_TOKEN m_can +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_0_STRING_UPPER_TOKEN M_CAN +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1 "message_ram" +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_STRING_UNQUOTED message_ram +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_STRING_TOKEN message_ram +#define DT_N_S_soc_S_can_4000a400_P_reg_names_IDX_1_STRING_UPPER_TOKEN MESSAGE_RAM +#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0) \ + fn(DT_N_S_soc_S_can_4000a400, reg_names, 1) +#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_can_4000a400, reg_names, 1) +#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_can_4000a400, reg_names, 1, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_reg_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_can_4000a400, reg_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_can_4000a400, reg_names, 1, __VA_ARGS__) +#define DT_N_S_soc_S_can_4000a400_P_reg_names_LEN 2 +#define DT_N_S_soc_S_can_4000a400_P_reg_names_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_can_4000a400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_wakeup_source 0 +#define DT_N_S_soc_S_can_4000a400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_can_4000a400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_can_4000a400_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_0_IDX_0_EXISTS 1 @@ -17129,11 +17840,11 @@ #define DT_N_S_soc_S_can_4000a400_P_pinctrl_0_LEN 2 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_can_4000a400, pinctrl_names, 0) #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_can_4000a400, pinctrl_names, 0) #define DT_N_S_soc_S_can_4000a400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_can_4000a400, pinctrl_names, 0, __VA_ARGS__) @@ -17155,6 +17866,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_FULL_NAME "dac1_out1_pa4" +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_FULL_NAME_UNQUOTED dac1_out1_pa4 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_FULL_NAME_TOKEN dac1_out1_pa4 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_FULL_NAME_UPPER_TOKEN DAC1_OUT1_PA4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -17180,16 +17894,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD 118 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD_STR_SORTABLE 00118 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD 121 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_ORD_STR_SORTABLE 00121 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_SUPPORTS_ORDS \ - 120, /* /soc/dac@40007400 */ + 123, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_EXISTS 1 @@ -17207,20 +17921,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_pinmux 144 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate "low-speed" @@ -17229,16 +17929,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dac1_out2_pa5 @@ -17254,6 +17966,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_FULL_NAME "dac1_out2_pa5" +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_FULL_NAME_UNQUOTED dac1_out2_pa5 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_FULL_NAME_TOKEN dac1_out2_pa5 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_FULL_NAME_UPPER_TOKEN DAC1_OUT2_PA5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -17279,16 +17994,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD 119 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD_STR_SORTABLE 00119 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD 122 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_ORD_STR_SORTABLE 00122 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_SUPPORTS_ORDS \ - 120, /* /soc/dac@40007400 */ + 123, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_EXISTS 1 @@ -17306,20 +18021,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_pinmux 176 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate "low-speed" @@ -17328,16 +18029,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/dac@40007400 @@ -17356,6 +18069,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dac_40007400_FULL_NAME "dac@40007400" +#define DT_N_S_soc_S_dac_40007400_FULL_NAME_UNQUOTED dac@40007400 +#define DT_N_S_soc_S_dac_40007400_FULL_NAME_TOKEN dac_40007400 +#define DT_N_S_soc_S_dac_40007400_FULL_NAME_UPPER_TOKEN DAC_40007400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dac_40007400_PARENT DT_N_S_soc @@ -17381,15 +18097,15 @@ #define DT_N_S_soc_S_dac_40007400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dac_40007400_ORD 120 -#define DT_N_S_soc_S_dac_40007400_ORD_STR_SORTABLE 00120 +#define DT_N_S_soc_S_dac_40007400_ORD 123 +#define DT_N_S_soc_S_dac_40007400_ORD_STR_SORTABLE 00123 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dac_40007400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 9, /* /soc/rcc@58024400 */ \ - 118, /* /soc/pin-controller@58020000/dac1_out1_pa4 */ \ - 119, /* /soc/pin-controller@58020000/dac1_out2_pa5 */ + 4, \ + 9, \ + 121, \ + 122, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dac_40007400_SUPPORTS_ORDS /* nothing */ @@ -17402,8 +18118,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dac_40007400_REG_NUM 1 #define DT_N_S_soc_S_dac_40007400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_VAL_ADDRESS 1073771520 /* 0x40007400 */ -#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_VAL_ADDRESS 1073771520 +#define DT_N_S_soc_S_dac_40007400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_dac_40007400_RANGES_NUM 0 #define DT_N_S_soc_S_dac_40007400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dac_40007400_IRQ_NUM 0 @@ -17426,20 +18142,32 @@ #define DT_N_S_soc_S_dac_40007400_PINCTRL_NAME_default_IDX_1_PH DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5 /* Generic property macros: */ -#define DT_N_S_soc_S_dac_40007400_P_wakeup_source 0 -#define DT_N_S_soc_S_dac_40007400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dac_40007400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_reg {1073771520, 1024} +#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_0 1073771520 +#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dac_40007400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bits 536870912 +#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, clocks, 0) +#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, clocks, 0) +#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dac_40007400_P_clocks_LEN 1 +#define DT_N_S_soc_S_dac_40007400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_status "okay" #define DT_N_S_soc_S_dac_40007400_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_dac_40007400_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_dac_40007400_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_dac_40007400_P_status_IDX_0 "okay" #define DT_N_S_soc_S_dac_40007400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_dac_40007400_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_dac_40007400_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dac_40007400_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_dac_40007400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, status, 0) #define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, status, 0) #define DT_N_S_soc_S_dac_40007400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, status, 0, __VA_ARGS__) @@ -17447,37 +18175,23 @@ #define DT_N_S_soc_S_dac_40007400_P_status_LEN 1 #define DT_N_S_soc_S_dac_40007400_P_status_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_compatible {"st,stm32-dac"} +#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0 "st,stm32-dac" #define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dac #define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_STRING_TOKEN st_stm32_dac #define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DAC -#define DT_N_S_soc_S_dac_40007400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, compatible, 0) #define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, compatible, 0) #define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dac_40007400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dac_40007400_P_compatible_LEN 1 #define DT_N_S_soc_S_dac_40007400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_reg {1073771520 /* 0x40007400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_0 1073771520 -#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dac_40007400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bits 536870912 -#define DT_N_S_soc_S_dac_40007400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, clocks, 0) -#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, clocks, 0) -#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dac_40007400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dac_40007400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dac_40007400_P_clocks_LEN 1 -#define DT_N_S_soc_S_dac_40007400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_dac_40007400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_wakeup_source 0 +#define DT_N_S_soc_S_dac_40007400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dac_40007400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dac_40007400_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_IDX_0_EXISTS 1 @@ -17495,11 +18209,11 @@ #define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_LEN 2 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0) #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0) #define DT_N_S_soc_S_dac_40007400_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dac_40007400, pinctrl_names, 0, __VA_ARGS__) @@ -17524,6 +18238,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_display_controller_50001000_FULL_NAME "display-controller@50001000" +#define DT_N_S_soc_S_display_controller_50001000_FULL_NAME_UNQUOTED display-controller@50001000 +#define DT_N_S_soc_S_display_controller_50001000_FULL_NAME_TOKEN display_controller_50001000 +#define DT_N_S_soc_S_display_controller_50001000_FULL_NAME_UPPER_TOKEN DISPLAY_CONTROLLER_50001000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_display_controller_50001000_PARENT DT_N_S_soc @@ -17549,14 +18266,15 @@ #define DT_N_S_soc_S_display_controller_50001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_display_controller_50001000_ORD 121 -#define DT_N_S_soc_S_display_controller_50001000_ORD_STR_SORTABLE 00121 +#define DT_N_S_soc_S_display_controller_50001000_ORD 124 +#define DT_N_S_soc_S_display_controller_50001000_ORD_STR_SORTABLE 00124 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_display_controller_50001000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_display_controller_50001000_SUPPORTS_ORDS /* nothing */ @@ -17569,8 +18287,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_display_controller_50001000_REG_NUM 1 #define DT_N_S_soc_S_display_controller_50001000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_REG_IDX_0_VAL_ADDRESS 1342181376 /* 0x50001000 */ -#define DT_N_S_soc_S_display_controller_50001000_REG_IDX_0_VAL_SIZE 512 /* 0x200 */ +#define DT_N_S_soc_S_display_controller_50001000_REG_IDX_0_VAL_ADDRESS 1342181376 +#define DT_N_S_soc_S_display_controller_50001000_REG_IDX_0_VAL_SIZE 512 #define DT_N_S_soc_S_display_controller_50001000_RANGES_NUM 0 #define DT_N_S_soc_S_display_controller_50001000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_display_controller_50001000_IRQ_NUM 2 @@ -17610,20 +18328,46 @@ #define DT_N_S_soc_S_display_controller_50001000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_display_controller_50001000_P_wakeup_source 0 -#define DT_N_S_soc_S_display_controller_50001000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_display_controller_50001000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bus 228 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bits 8 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0) +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0) +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_LEN 1 +#define DT_N_S_soc_S_display_controller_50001000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_display_controller_50001000_P_resets_IDX_0_VAL_id 4484 +#define DT_N_S_soc_S_display_controller_50001000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_50001000, resets, 0) +#define DT_N_S_soc_S_display_controller_50001000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_50001000, resets, 0) +#define DT_N_S_soc_S_display_controller_50001000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_50001000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_display_controller_50001000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_50001000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_display_controller_50001000_P_resets_LEN 1 +#define DT_N_S_soc_S_display_controller_50001000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts {88, 0, 89, 0} +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_0 88 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_2 89 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_status "disabled" #define DT_N_S_soc_S_display_controller_50001000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_display_controller_50001000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_display_controller_50001000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_display_controller_50001000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_display_controller_50001000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_display_controller_50001000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_display_controller_50001000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_display_controller_50001000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_display_controller_50001000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_50001000, status, 0) #define DT_N_S_soc_S_display_controller_50001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_50001000, status, 0) #define DT_N_S_soc_S_display_controller_50001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_50001000, status, 0, __VA_ARGS__) @@ -17631,44 +18375,34 @@ #define DT_N_S_soc_S_display_controller_50001000_P_status_LEN 1 #define DT_N_S_soc_S_display_controller_50001000_P_status_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_compatible {"st,stm32-ltdc"} +#define DT_N_S_soc_S_display_controller_50001000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_compatible_IDX_0 "st,stm32-ltdc" #define DT_N_S_soc_S_display_controller_50001000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-ltdc #define DT_N_S_soc_S_display_controller_50001000_P_compatible_IDX_0_STRING_TOKEN st_stm32_ltdc #define DT_N_S_soc_S_display_controller_50001000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LTDC -#define DT_N_S_soc_S_display_controller_50001000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_50001000, compatible, 0) #define DT_N_S_soc_S_display_controller_50001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_50001000, compatible, 0) #define DT_N_S_soc_S_display_controller_50001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_50001000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_display_controller_50001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_50001000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_display_controller_50001000_P_compatible_LEN 1 #define DT_N_S_soc_S_display_controller_50001000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_reg {1342181376 /* 0x50001000 */, 512 /* 0x200 */} -#define DT_N_S_soc_S_display_controller_50001000_P_reg_IDX_0 1342181376 +#define DT_N_S_soc_S_display_controller_50001000_P_reg {1342181376, 512} #define DT_N_S_soc_S_display_controller_50001000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_reg_IDX_1 512 +#define DT_N_S_soc_S_display_controller_50001000_P_reg_IDX_0 1342181376 #define DT_N_S_soc_S_display_controller_50001000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_reg_IDX_1 512 #define DT_N_S_soc_S_display_controller_50001000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts {88 /* 0x58 */, 0 /* 0x0 */, 89 /* 0x59 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_0 88 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_2 89 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names {"ltdc", "ltdc_er"} +#define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_0 "ltdc" #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_0_STRING_UNQUOTED ltdc #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_0_STRING_TOKEN ltdc #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN LTDC -#define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_1 "ltdc_er" #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_1_STRING_UNQUOTED ltdc_er #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_1_STRING_TOKEN ltdc_er #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN LTDC_ER -#define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_50001000, interrupt_names, 0) \ fn(DT_N_S_soc_S_display_controller_50001000, interrupt_names, 1) #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_50001000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -17679,20 +18413,12 @@ fn(DT_N_S_soc_S_display_controller_50001000, interrupt_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_LEN 2 #define DT_N_S_soc_S_display_controller_50001000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bus 228 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bits 8 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0) -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0) -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_display_controller_50001000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_LEN 1 -#define DT_N_S_soc_S_display_controller_50001000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_display_controller_50001000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_display_controller_50001000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_wakeup_source 0 +#define DT_N_S_soc_S_display_controller_50001000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_display_controller_50001000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_display_controller_50001000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/dma@40020400 @@ -17711,6 +18437,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dma_40020400_FULL_NAME "dma@40020400" +#define DT_N_S_soc_S_dma_40020400_FULL_NAME_UNQUOTED dma@40020400 +#define DT_N_S_soc_S_dma_40020400_FULL_NAME_TOKEN dma_40020400 +#define DT_N_S_soc_S_dma_40020400_FULL_NAME_UPPER_TOKEN DMA_40020400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dma_40020400_PARENT DT_N_S_soc @@ -17736,14 +18465,14 @@ #define DT_N_S_soc_S_dma_40020400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dma_40020400_ORD 122 -#define DT_N_S_soc_S_dma_40020400_ORD_STR_SORTABLE 00122 +#define DT_N_S_soc_S_dma_40020400_ORD 125 +#define DT_N_S_soc_S_dma_40020400_ORD_STR_SORTABLE 00125 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dma_40020400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dma_40020400_SUPPORTS_ORDS /* nothing */ @@ -17756,8 +18485,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dma_40020400_REG_NUM 1 #define DT_N_S_soc_S_dma_40020400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_VAL_ADDRESS 1073873920 /* 0x40020400 */ -#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_VAL_ADDRESS 1073873920 +#define DT_N_S_soc_S_dma_40020400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_dma_40020400_RANGES_NUM 0 #define DT_N_S_soc_S_dma_40020400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dma_40020400_IRQ_NUM 8 @@ -17829,20 +18558,60 @@ #define DT_N_S_soc_S_dma_40020400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_dma_40020400_P_wakeup_source 0 -#define DT_N_S_soc_S_dma_40020400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dma_40020400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_reg {1073873920, 1024} +#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_0 1073873920 +#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dma_40020400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts {56, 0, 57, 0, 58, 0, 59, 0, 60, 0, 68, 0, 69, 0, 70, 0} +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_0 56 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_2 57 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_4 58 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_6 59 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_8_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_8 60 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_9_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_9 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_10_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_10 68 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_11_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_11 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_12_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_12 69 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_13_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_13 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_14_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_14 70 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_15_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_15 0 +#define DT_N_S_soc_S_dma_40020400_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_st_mem2mem 1 +#define DT_N_S_soc_S_dma_40020400_P_st_mem2mem_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_dma_offset 8 +#define DT_N_S_soc_S_dma_40020400_P_dma_offset_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_dma_requests 8 +#define DT_N_S_soc_S_dma_40020400_P_dma_requests_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_status "disabled" #define DT_N_S_soc_S_dma_40020400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_dma_40020400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_dma_40020400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_dma_40020400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_dma_40020400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_dma_40020400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_dma_40020400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_dma_40020400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_dma_40020400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020400, status, 0) #define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, status, 0) #define DT_N_S_soc_S_dma_40020400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020400, status, 0, __VA_ARGS__) @@ -17850,57 +18619,17 @@ #define DT_N_S_soc_S_dma_40020400_P_status_LEN 1 #define DT_N_S_soc_S_dma_40020400_P_status_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_compatible {"st,stm32-dma-v1"} +#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0 "st,stm32-dma-v1" #define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v1 #define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v1 #define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V1 -#define DT_N_S_soc_S_dma_40020400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020400, compatible, 0) #define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020400, compatible, 0) #define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dma_40020400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dma_40020400_P_compatible_LEN 1 #define DT_N_S_soc_S_dma_40020400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_reg {1073873920 /* 0x40020400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_0 1073873920 -#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dma_40020400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts {56 /* 0x38 */, 0 /* 0x0 */, 57 /* 0x39 */, 0 /* 0x0 */, 58 /* 0x3a */, 0 /* 0x0 */, 59 /* 0x3b */, 0 /* 0x0 */, 60 /* 0x3c */, 0 /* 0x0 */, 68 /* 0x44 */, 0 /* 0x0 */, 69 /* 0x45 */, 0 /* 0x0 */, 70 /* 0x46 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_0 56 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_2 57 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_4 58 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_5 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_6 59 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_7 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_8 60 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_8_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_9 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_9_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_10 68 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_10_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_11 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_11_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_12 69 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_12_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_13 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_13_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_14 70 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_14_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_15 0 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_IDX_15_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_dma_40020400_P_clocks_IDX_0_VAL_bus 216 @@ -17915,12 +18644,10 @@ #define DT_N_S_soc_S_dma_40020400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dma_40020400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_dma_40020400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_dma_requests 8 -#define DT_N_S_soc_S_dma_40020400_P_dma_requests_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_st_mem2mem 1 -#define DT_N_S_soc_S_dma_40020400_P_st_mem2mem_EXISTS 1 -#define DT_N_S_soc_S_dma_40020400_P_dma_offset 8 -#define DT_N_S_soc_S_dma_40020400_P_dma_offset_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_wakeup_source 0 +#define DT_N_S_soc_S_dma_40020400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dma_40020400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dma_40020400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/dmamux@58025800 @@ -17939,6 +18666,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dmamux_58025800_FULL_NAME "dmamux@58025800" +#define DT_N_S_soc_S_dmamux_58025800_FULL_NAME_UNQUOTED dmamux@58025800 +#define DT_N_S_soc_S_dmamux_58025800_FULL_NAME_TOKEN dmamux_58025800 +#define DT_N_S_soc_S_dmamux_58025800_FULL_NAME_UPPER_TOKEN DMAMUX_58025800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dmamux_58025800_PARENT DT_N_S_soc @@ -17964,14 +18694,14 @@ #define DT_N_S_soc_S_dmamux_58025800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dmamux_58025800_ORD 123 -#define DT_N_S_soc_S_dmamux_58025800_ORD_STR_SORTABLE 00123 +#define DT_N_S_soc_S_dmamux_58025800_ORD 126 +#define DT_N_S_soc_S_dmamux_58025800_ORD_STR_SORTABLE 00126 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dmamux_58025800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dmamux_58025800_SUPPORTS_ORDS /* nothing */ @@ -17984,8 +18714,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dmamux_58025800_REG_NUM 1 #define DT_N_S_soc_S_dmamux_58025800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_REG_IDX_0_VAL_ADDRESS 1476548608 /* 0x58025800 */ -#define DT_N_S_soc_S_dmamux_58025800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dmamux_58025800_REG_IDX_0_VAL_ADDRESS 1476548608 +#define DT_N_S_soc_S_dmamux_58025800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_dmamux_58025800_RANGES_NUM 0 #define DT_N_S_soc_S_dmamux_58025800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dmamux_58025800_IRQ_NUM 1 @@ -18008,20 +18738,26 @@ #define DT_N_S_soc_S_dmamux_58025800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_dmamux_58025800_P_wakeup_source 0 -#define DT_N_S_soc_S_dmamux_58025800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dmamux_58025800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_reg {1476548608, 1024} +#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_0 1476548608 +#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dmamux_58025800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_dma_channels 8 +#define DT_N_S_soc_S_dmamux_58025800_P_dma_channels_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_dma_generators 8 +#define DT_N_S_soc_S_dmamux_58025800_P_dma_generators_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_dma_requests 107 +#define DT_N_S_soc_S_dmamux_58025800_P_dma_requests_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_status "disabled" #define DT_N_S_soc_S_dmamux_58025800_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_dmamux_58025800_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_dmamux_58025800_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_dmamux_58025800_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_dmamux_58025800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_dmamux_58025800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_dmamux_58025800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_dmamux_58025800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_dmamux_58025800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_58025800, status, 0) #define DT_N_S_soc_S_dmamux_58025800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_58025800, status, 0) #define DT_N_S_soc_S_dmamux_58025800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_58025800, status, 0, __VA_ARGS__) @@ -18029,28 +18765,22 @@ #define DT_N_S_soc_S_dmamux_58025800_P_status_LEN 1 #define DT_N_S_soc_S_dmamux_58025800_P_status_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_compatible {"st,stm32-dmamux"} +#define DT_N_S_soc_S_dmamux_58025800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_compatible_IDX_0 "st,stm32-dmamux" #define DT_N_S_soc_S_dmamux_58025800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dmamux #define DT_N_S_soc_S_dmamux_58025800_P_compatible_IDX_0_STRING_TOKEN st_stm32_dmamux #define DT_N_S_soc_S_dmamux_58025800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMAMUX -#define DT_N_S_soc_S_dmamux_58025800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_58025800, compatible, 0) #define DT_N_S_soc_S_dmamux_58025800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_58025800, compatible, 0) #define DT_N_S_soc_S_dmamux_58025800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_58025800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dmamux_58025800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dmamux_58025800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dmamux_58025800_P_compatible_LEN 1 #define DT_N_S_soc_S_dmamux_58025800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_reg {1476548608 /* 0x58025800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_0 1476548608 -#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dmamux_58025800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_interrupts {128 /* 0x80 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dmamux_58025800_P_interrupts_IDX_0 128 +#define DT_N_S_soc_S_dmamux_58025800_P_interrupts {128, 0} #define DT_N_S_soc_S_dmamux_58025800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dmamux_58025800_P_interrupts_IDX_0 128 #define DT_N_S_soc_S_dmamux_58025800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_dmamux_58025800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -18066,12 +18796,10 @@ #define DT_N_S_soc_S_dmamux_58025800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dmamux_58025800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_dmamux_58025800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_dma_channels 8 -#define DT_N_S_soc_S_dmamux_58025800_P_dma_channels_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_dma_generators 8 -#define DT_N_S_soc_S_dmamux_58025800_P_dma_generators_EXISTS 1 -#define DT_N_S_soc_S_dmamux_58025800_P_dma_requests 107 -#define DT_N_S_soc_S_dmamux_58025800_P_dma_requests_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_wakeup_source 0 +#define DT_N_S_soc_S_dmamux_58025800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dmamux_58025800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dmamux_58025800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/dsihost@50000000 @@ -18090,6 +18818,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dsihost_50000000_FULL_NAME "dsihost@50000000" +#define DT_N_S_soc_S_dsihost_50000000_FULL_NAME_UNQUOTED dsihost@50000000 +#define DT_N_S_soc_S_dsihost_50000000_FULL_NAME_TOKEN dsihost_50000000 +#define DT_N_S_soc_S_dsihost_50000000_FULL_NAME_UPPER_TOKEN DSIHOST_50000000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dsihost_50000000_PARENT DT_N_S_soc @@ -18115,14 +18846,14 @@ #define DT_N_S_soc_S_dsihost_50000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dsihost_50000000_ORD 124 -#define DT_N_S_soc_S_dsihost_50000000_ORD_STR_SORTABLE 00124 +#define DT_N_S_soc_S_dsihost_50000000_ORD 127 +#define DT_N_S_soc_S_dsihost_50000000_ORD_STR_SORTABLE 00127 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dsihost_50000000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dsihost_50000000_SUPPORTS_ORDS /* nothing */ @@ -18135,8 +18866,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dsihost_50000000_REG_NUM 1 #define DT_N_S_soc_S_dsihost_50000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_REG_IDX_0_VAL_ADDRESS 1342177280 /* 0x50000000 */ -#define DT_N_S_soc_S_dsihost_50000000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ +#define DT_N_S_soc_S_dsihost_50000000_REG_IDX_0_VAL_ADDRESS 1342177280 +#define DT_N_S_soc_S_dsihost_50000000_REG_IDX_0_VAL_SIZE 4096 #define DT_N_S_soc_S_dsihost_50000000_RANGES_NUM 0 #define DT_N_S_soc_S_dsihost_50000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dsihost_50000000_IRQ_NUM 0 @@ -18152,44 +18883,6 @@ #define DT_N_S_soc_S_dsihost_50000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_dsihost_50000000_P_wakeup_source 0 -#define DT_N_S_soc_S_dsihost_50000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_status "disabled" -#define DT_N_S_soc_S_dsihost_50000000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_dsihost_50000000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_dsihost_50000000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dsihost_50000000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_dsihost_50000000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_dsihost_50000000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_dsihost_50000000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dsihost_50000000, status, 0) -#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dsihost_50000000, status, 0) -#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dsihost_50000000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dsihost_50000000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dsihost_50000000_P_status_LEN 1 -#define DT_N_S_soc_S_dsihost_50000000_P_status_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_compatible {"st,stm32-mipi-dsi"} -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0 "st,stm32-mipi-dsi" -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-mipi-dsi -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_mipi_dsi -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_MIPI_DSI -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0) -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0) -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_LEN 1 -#define DT_N_S_soc_S_dsihost_50000000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_reg {1342177280 /* 0x50000000 */, 4096 /* 0x1000 */} -#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_0 1342177280 -#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_1 4096 -#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_reg_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_dsihost_50000000_P_clocks_IDX_0_VAL_bus 228 @@ -18244,21 +18937,21 @@ #define DT_N_S_soc_S_dsihost_50000000_P_clocks_LEN 3 #define DT_N_S_soc_S_dsihost_50000000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clock_names {"dsiclk", "refclk", "pixelclk"} +#define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_0 "dsiclk" #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_0_STRING_UNQUOTED dsiclk #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_0_STRING_TOKEN dsiclk #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_0_STRING_UPPER_TOKEN DSICLK -#define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_1 "refclk" #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_1_STRING_UNQUOTED refclk #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_1_STRING_TOKEN refclk #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_1_STRING_UPPER_TOKEN REFCLK -#define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_2 "pixelclk" #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_2_STRING_UNQUOTED pixelclk #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_2_STRING_TOKEN pixelclk #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_2_STRING_UPPER_TOKEN PIXELCLK -#define DT_N_S_soc_S_dsihost_50000000_P_clock_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dsihost_50000000, clock_names, 0) \ fn(DT_N_S_soc_S_dsihost_50000000, clock_names, 1) \ fn(DT_N_S_soc_S_dsihost_50000000, clock_names, 2) @@ -18273,8 +18966,6 @@ fn(DT_N_S_soc_S_dsihost_50000000, clock_names, 2, __VA_ARGS__) #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_LEN 3 #define DT_N_S_soc_S_dsihost_50000000_P_clock_names_EXISTS 1 -#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_dsihost_50000000_P_resets_IDX_0_VAL_id 4484 @@ -18297,6 +18988,44 @@ #define DT_N_S_soc_S_dsihost_50000000_P_bta_ack_disable_EXISTS 1 #define DT_N_S_soc_S_dsihost_50000000_P_non_continuous 0 #define DT_N_S_soc_S_dsihost_50000000_P_non_continuous_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_status "disabled" +#define DT_N_S_soc_S_dsihost_50000000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_dsihost_50000000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_dsihost_50000000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_dsihost_50000000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_dsihost_50000000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_dsihost_50000000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dsihost_50000000, status, 0) +#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dsihost_50000000, status, 0) +#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dsihost_50000000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dsihost_50000000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dsihost_50000000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dsihost_50000000_P_status_LEN 1 +#define DT_N_S_soc_S_dsihost_50000000_P_status_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_compatible {"st,stm32-mipi-dsi"} +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0 "st,stm32-mipi-dsi" +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-mipi-dsi +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_mipi_dsi +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_MIPI_DSI +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0) +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0) +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dsihost_50000000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_LEN 1 +#define DT_N_S_soc_S_dsihost_50000000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_reg {1342177280, 4096} +#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_0 1342177280 +#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_reg_IDX_1 4096 +#define DT_N_S_soc_S_dsihost_50000000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_wakeup_source 0 +#define DT_N_S_soc_S_dsihost_50000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dsihost_50000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/dmamux@40020800 @@ -18315,6 +19044,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dmamux_40020800_FULL_NAME "dmamux@40020800" +#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME_UNQUOTED dmamux@40020800 +#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME_TOKEN dmamux_40020800 +#define DT_N_S_soc_S_dmamux_40020800_FULL_NAME_UPPER_TOKEN DMAMUX_40020800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dmamux_40020800_PARENT DT_N_S_soc @@ -18340,20 +19072,20 @@ #define DT_N_S_soc_S_dmamux_40020800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dmamux_40020800_ORD 125 -#define DT_N_S_soc_S_dmamux_40020800_ORD_STR_SORTABLE 00125 +#define DT_N_S_soc_S_dmamux_40020800_ORD 128 +#define DT_N_S_soc_S_dmamux_40020800_ORD_STR_SORTABLE 00128 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dmamux_40020800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dmamux_40020800_SUPPORTS_ORDS \ - 126, /* /soc/i2s@40003800 */ \ - 127, /* /soc/i2s@40003c00 */ \ - 128, /* /soc/i2s@40013000 */ + 129, \ + 130, \ + 131, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_dmamux_40020800_EXISTS 1 @@ -18363,8 +19095,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dmamux_40020800_REG_NUM 1 #define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_VAL_ADDRESS 1073874944 /* 0x40020800 */ -#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_VAL_ADDRESS 1073874944 +#define DT_N_S_soc_S_dmamux_40020800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_dmamux_40020800_RANGES_NUM 0 #define DT_N_S_soc_S_dmamux_40020800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dmamux_40020800_IRQ_NUM 1 @@ -18387,20 +19119,26 @@ #define DT_N_S_soc_S_dmamux_40020800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source 0 -#define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_reg {1073874944, 1024} +#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_0 1073874944 +#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dmamux_40020800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_dma_channels 16 +#define DT_N_S_soc_S_dmamux_40020800_P_dma_channels_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_dma_generators 8 +#define DT_N_S_soc_S_dmamux_40020800_P_dma_generators_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_dma_requests 107 +#define DT_N_S_soc_S_dmamux_40020800_P_dma_requests_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_status "okay" #define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_dmamux_40020800_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0 "okay" #define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_dmamux_40020800_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_dmamux_40020800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_40020800, status, 0) #define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, status, 0) #define DT_N_S_soc_S_dmamux_40020800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, status, 0, __VA_ARGS__) @@ -18408,28 +19146,22 @@ #define DT_N_S_soc_S_dmamux_40020800_P_status_LEN 1 #define DT_N_S_soc_S_dmamux_40020800_P_status_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_compatible {"st,stm32-dmamux"} +#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0 "st,stm32-dmamux" #define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dmamux #define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_STRING_TOKEN st_stm32_dmamux #define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMAMUX -#define DT_N_S_soc_S_dmamux_40020800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0) #define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0) #define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dmamux_40020800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dmamux_40020800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dmamux_40020800_P_compatible_LEN 1 #define DT_N_S_soc_S_dmamux_40020800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_reg {1073874944 /* 0x40020800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_0 1073874944 -#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dmamux_40020800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_interrupts {102 /* 0x66 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_0 102 +#define DT_N_S_soc_S_dmamux_40020800_P_interrupts {102, 0} #define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_0 102 #define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_dmamux_40020800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -18445,12 +19177,10 @@ #define DT_N_S_soc_S_dmamux_40020800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dmamux_40020800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_dmamux_40020800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_dma_channels 16 -#define DT_N_S_soc_S_dmamux_40020800_P_dma_channels_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_dma_generators 8 -#define DT_N_S_soc_S_dmamux_40020800_P_dma_generators_EXISTS 1 -#define DT_N_S_soc_S_dmamux_40020800_P_dma_requests 107 -#define DT_N_S_soc_S_dmamux_40020800_P_dma_requests_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source 0 +#define DT_N_S_soc_S_dmamux_40020800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dmamux_40020800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/i2s@40003800 @@ -18469,6 +19199,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2s_40003800_FULL_NAME "i2s@40003800" +#define DT_N_S_soc_S_i2s_40003800_FULL_NAME_UNQUOTED i2s@40003800 +#define DT_N_S_soc_S_i2s_40003800_FULL_NAME_TOKEN i2s_40003800 +#define DT_N_S_soc_S_i2s_40003800_FULL_NAME_UPPER_TOKEN I2S_40003800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2s_40003800_PARENT DT_N_S_soc @@ -18494,15 +19227,15 @@ #define DT_N_S_soc_S_i2s_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2s_40003800_ORD 126 -#define DT_N_S_soc_S_i2s_40003800_ORD_STR_SORTABLE 00126 +#define DT_N_S_soc_S_i2s_40003800_ORD 129 +#define DT_N_S_soc_S_i2s_40003800_ORD_STR_SORTABLE 00129 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2s_40003800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 125, /* /soc/dmamux@40020800 */ + 4, \ + 5, \ + 9, \ + 128, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2s_40003800_SUPPORTS_ORDS /* nothing */ @@ -18516,8 +19249,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2s_40003800_REG_NUM 1 #define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 /* 0x40003800 */ -#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 +#define DT_N_S_soc_S_i2s_40003800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2s_40003800_RANGES_NUM 0 #define DT_N_S_soc_S_i2s_40003800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2s_40003800_IRQ_NUM 1 @@ -18545,81 +19278,18 @@ #define DT_N_S_soc_S_i2s_40003800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_i2s_40003800_P_wakeup_source 0 -#define DT_N_S_soc_S_i2s_40003800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2s_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_status "disabled" -#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_i2s_40003800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_i2s_40003800_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, status, 0) -#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, status, 0) -#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003800_P_status_LEN 1 -#define DT_N_S_soc_S_i2s_40003800_P_status_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_compatible {"st,stm32h7-i2s", "st,stm32-i2s"} -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0 "st,stm32h7-i2s" -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-i2s -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_i2s -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_I2S -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1 "st,stm32-i2s" -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-i2s -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_STRING_TOKEN st_stm32_i2s -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_I2S -#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0) \ - fn(DT_N_S_soc_S_i2s_40003800, compatible, 1) -#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003800, compatible, 1) -#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2s_40003800, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003800, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003800_P_compatible_LEN 2 -#define DT_N_S_soc_S_i2s_40003800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_reg {1073756160 /* 0x40003800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_0 1073756160 +#define DT_N_S_soc_S_i2s_40003800_P_reg {1073756160, 1024} #define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_0 1073756160 #define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_reg_IDX_1 1024 #define DT_N_S_soc_S_i2s_40003800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_interrupts {36 /* 0x24 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_0 36 +#define DT_N_S_soc_S_i2s_40003800_P_interrupts {36, 0} #define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_0 36 #define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_i2s_40003800_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bits 16384 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bus 9 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bits 60496 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0) \ - fn(DT_N_S_soc_S_i2s_40003800, clocks, 1) -#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003800, clocks, 1) -#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2s_40003800, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003800, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003800_P_clocks_LEN 2 -#define DT_N_S_soc_S_i2s_40003800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_PH DT_N_S_soc_S_dmamux_40020800 #define DT_N_S_soc_S_i2s_40003800_P_dmas_IDX_0_VAL_channel 0 @@ -18665,16 +19335,16 @@ #define DT_N_S_soc_S_i2s_40003800_P_dmas_LEN 2 #define DT_N_S_soc_S_i2s_40003800_P_dmas_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_dma_names {"tx", "rx"} +#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0 "tx" #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_STRING_UNQUOTED tx #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_STRING_TOKEN tx #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_STRING_UPPER_TOKEN TX -#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1 "rx" #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_STRING_UNQUOTED rx #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_STRING_TOKEN rx #define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_STRING_UPPER_TOKEN RX -#define DT_N_S_soc_S_i2s_40003800_P_dma_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, dma_names, 0) \ fn(DT_N_S_soc_S_i2s_40003800, dma_names, 1) #define DT_N_S_soc_S_i2s_40003800_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, dma_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -18685,10 +19355,71 @@ fn(DT_N_S_soc_S_i2s_40003800, dma_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_i2s_40003800_P_dma_names_LEN 2 #define DT_N_S_soc_S_i2s_40003800_P_dma_names_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003800_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_i2s_40003800_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_i2s_40003800_P_mck_enabled 0 #define DT_N_S_soc_S_i2s_40003800_P_mck_enabled_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_status "disabled" +#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_i2s_40003800_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_i2s_40003800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, status, 0) +#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, status, 0) +#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003800_P_status_LEN 1 +#define DT_N_S_soc_S_i2s_40003800_P_status_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_compatible {"st,stm32h7-i2s", "st,stm32-i2s"} +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0 "st,stm32h7-i2s" +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-i2s +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_i2s +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_I2S +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1 "st,stm32-i2s" +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-i2s +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_STRING_TOKEN st_stm32_i2s +#define DT_N_S_soc_S_i2s_40003800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_I2S +#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0) \ + fn(DT_N_S_soc_S_i2s_40003800, compatible, 1) +#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003800, compatible, 1) +#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2s_40003800, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003800, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003800_P_compatible_LEN 2 +#define DT_N_S_soc_S_i2s_40003800_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bits 16384 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bus 9 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bits 60496 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_IDX_1_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0) \ + fn(DT_N_S_soc_S_i2s_40003800, clocks, 1) +#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003800, clocks, 1) +#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2s_40003800, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003800, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003800, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003800_P_clocks_LEN 2 +#define DT_N_S_soc_S_i2s_40003800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_i2s_40003800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_wakeup_source 0 +#define DT_N_S_soc_S_i2s_40003800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2s_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/i2s@40003c00 @@ -18707,6 +19438,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2s_40003c00_FULL_NAME "i2s@40003c00" +#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME_UNQUOTED i2s@40003c00 +#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME_TOKEN i2s_40003c00 +#define DT_N_S_soc_S_i2s_40003c00_FULL_NAME_UPPER_TOKEN I2S_40003C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2s_40003c00_PARENT DT_N_S_soc @@ -18732,15 +19466,15 @@ #define DT_N_S_soc_S_i2s_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2s_40003c00_ORD 127 -#define DT_N_S_soc_S_i2s_40003c00_ORD_STR_SORTABLE 00127 +#define DT_N_S_soc_S_i2s_40003c00_ORD 130 +#define DT_N_S_soc_S_i2s_40003c00_ORD_STR_SORTABLE 00130 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2s_40003c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 125, /* /soc/dmamux@40020800 */ + 4, \ + 5, \ + 9, \ + 128, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2s_40003c00_SUPPORTS_ORDS /* nothing */ @@ -18754,8 +19488,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2s_40003c00_REG_NUM 1 #define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 /* 0x40003c00 */ -#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 +#define DT_N_S_soc_S_i2s_40003c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2s_40003c00_RANGES_NUM 0 #define DT_N_S_soc_S_i2s_40003c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2s_40003c00_IRQ_NUM 1 @@ -18783,81 +19517,18 @@ #define DT_N_S_soc_S_i2s_40003c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_i2s_40003c00_P_wakeup_source 0 -#define DT_N_S_soc_S_i2s_40003c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_status "disabled" -#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_i2s_40003c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_i2s_40003c00_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, status, 0) -#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, status, 0) -#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003c00_P_status_LEN 1 -#define DT_N_S_soc_S_i2s_40003c00_P_status_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_compatible {"st,stm32h7-i2s", "st,stm32-i2s"} -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0 "st,stm32h7-i2s" -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-i2s -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_i2s -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_I2S -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1 "st,stm32-i2s" -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-i2s -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_STRING_TOKEN st_stm32_i2s -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_I2S -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0) \ - fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1) -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1) -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_LEN 2 -#define DT_N_S_soc_S_i2s_40003c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_reg {1073757184 /* 0x40003c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_0 1073757184 +#define DT_N_S_soc_S_i2s_40003c00_P_reg {1073757184, 1024} #define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_0 1073757184 #define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_reg_IDX_1 1024 #define DT_N_S_soc_S_i2s_40003c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_interrupts {51 /* 0x33 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_0 51 +#define DT_N_S_soc_S_i2s_40003c00_P_interrupts {51, 0} #define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_0 51 #define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_i2s_40003c00_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bits 32768 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bus 9 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bits 60496 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0) \ - fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1) -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1) -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_LEN 2 -#define DT_N_S_soc_S_i2s_40003c00_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_PH DT_N_S_soc_S_dmamux_40020800 #define DT_N_S_soc_S_i2s_40003c00_P_dmas_IDX_0_VAL_channel 0 @@ -18903,16 +19574,16 @@ #define DT_N_S_soc_S_i2s_40003c00_P_dmas_LEN 2 #define DT_N_S_soc_S_i2s_40003c00_P_dmas_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_dma_names {"tx", "rx"} +#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0 "tx" #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_STRING_UNQUOTED tx #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_STRING_TOKEN tx #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_STRING_UPPER_TOKEN TX -#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1 "rx" #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_STRING_UNQUOTED rx #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_STRING_TOKEN rx #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_STRING_UPPER_TOKEN RX -#define DT_N_S_soc_S_i2s_40003c00_P_dma_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 0) \ fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 1) #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -18923,10 +19594,71 @@ fn(DT_N_S_soc_S_i2s_40003c00, dma_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_LEN 2 #define DT_N_S_soc_S_i2s_40003c00_P_dma_names_EXISTS 1 -#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_i2s_40003c00_P_mck_enabled 0 #define DT_N_S_soc_S_i2s_40003c00_P_mck_enabled_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_status "disabled" +#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_i2s_40003c00_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_i2s_40003c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, status, 0) +#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, status, 0) +#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003c00_P_status_LEN 1 +#define DT_N_S_soc_S_i2s_40003c00_P_status_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_compatible {"st,stm32h7-i2s", "st,stm32-i2s"} +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0 "st,stm32h7-i2s" +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-i2s +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_i2s +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_I2S +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1 "st,stm32-i2s" +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-i2s +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_STRING_TOKEN st_stm32_i2s +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_I2S +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0) \ + fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1) +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1) +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003c00, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_LEN 2 +#define DT_N_S_soc_S_i2s_40003c00_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bits 32768 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bus 9 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bits 60496 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_IDX_1_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0) \ + fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1) +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1) +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40003c00, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40003c00, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_LEN 2 +#define DT_N_S_soc_S_i2s_40003c00_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_wakeup_source 0 +#define DT_N_S_soc_S_i2s_40003c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2s_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/i2s@40013000 @@ -18945,6 +19677,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2s_40013000_FULL_NAME "i2s@40013000" +#define DT_N_S_soc_S_i2s_40013000_FULL_NAME_UNQUOTED i2s@40013000 +#define DT_N_S_soc_S_i2s_40013000_FULL_NAME_TOKEN i2s_40013000 +#define DT_N_S_soc_S_i2s_40013000_FULL_NAME_UPPER_TOKEN I2S_40013000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_i2s_40013000_PARENT DT_N_S_soc @@ -18970,15 +19705,15 @@ #define DT_N_S_soc_S_i2s_40013000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2s_40013000_ORD 128 -#define DT_N_S_soc_S_i2s_40013000_ORD_STR_SORTABLE 00128 +#define DT_N_S_soc_S_i2s_40013000_ORD 131 +#define DT_N_S_soc_S_i2s_40013000_ORD_STR_SORTABLE 00131 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2s_40013000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 125, /* /soc/dmamux@40020800 */ + 4, \ + 5, \ + 9, \ + 128, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2s_40013000_SUPPORTS_ORDS /* nothing */ @@ -18992,8 +19727,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2s_40013000_REG_NUM 1 #define DT_N_S_soc_S_i2s_40013000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 /* 0x40013000 */ -#define DT_N_S_soc_S_i2s_40013000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_i2s_40013000_REG_IDX_0_VAL_ADDRESS 1073819648 +#define DT_N_S_soc_S_i2s_40013000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_i2s_40013000_RANGES_NUM 0 #define DT_N_S_soc_S_i2s_40013000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2s_40013000_IRQ_NUM 1 @@ -19021,81 +19756,18 @@ #define DT_N_S_soc_S_i2s_40013000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_i2s_40013000_P_wakeup_source 0 -#define DT_N_S_soc_S_i2s_40013000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2s_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_status "disabled" -#define DT_N_S_soc_S_i2s_40013000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_i2s_40013000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_i2s_40013000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_i2s_40013000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_i2s_40013000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_i2s_40013000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_i2s_40013000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, status, 0) -#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, status, 0) -#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40013000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40013000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40013000_P_status_LEN 1 -#define DT_N_S_soc_S_i2s_40013000_P_status_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_compatible {"st,stm32h7-i2s", "st,stm32-i2s"} -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0 "st,stm32h7-i2s" -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-i2s -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_i2s -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_I2S -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1 "st,stm32-i2s" -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-i2s -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_STRING_TOKEN st_stm32_i2s -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_I2S -#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0) \ - fn(DT_N_S_soc_S_i2s_40013000, compatible, 1) -#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40013000, compatible, 1) -#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2s_40013000, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40013000, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40013000_P_compatible_LEN 2 -#define DT_N_S_soc_S_i2s_40013000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_reg {1073819648 /* 0x40013000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_i2s_40013000_P_reg_IDX_0 1073819648 +#define DT_N_S_soc_S_i2s_40013000_P_reg {1073819648, 1024} #define DT_N_S_soc_S_i2s_40013000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_i2s_40013000_P_reg_IDX_0 1073819648 #define DT_N_S_soc_S_i2s_40013000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_i2s_40013000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_interrupts {35 /* 0x23 */, 3 /* 0x3 */} -#define DT_N_S_soc_S_i2s_40013000_P_interrupts_IDX_0 35 +#define DT_N_S_soc_S_i2s_40013000_P_interrupts {35, 3} #define DT_N_S_soc_S_i2s_40013000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_interrupts_IDX_1 3 +#define DT_N_S_soc_S_i2s_40013000_P_interrupts_IDX_0 35 #define DT_N_S_soc_S_i2s_40013000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_interrupts_IDX_1 3 #define DT_N_S_soc_S_i2s_40013000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bits 4096 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bus 9 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bits 60496 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0) \ - fn(DT_N_S_soc_S_i2s_40013000, clocks, 1) -#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40013000, clocks, 1) -#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_i2s_40013000, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_i2s_40013000, clocks, 1, __VA_ARGS__) -#define DT_N_S_soc_S_i2s_40013000_P_clocks_LEN 2 -#define DT_N_S_soc_S_i2s_40013000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_dmas_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_dmas_IDX_0_PH DT_N_S_soc_S_dmamux_40020800 #define DT_N_S_soc_S_i2s_40013000_P_dmas_IDX_0_VAL_channel 0 @@ -19141,16 +19813,16 @@ #define DT_N_S_soc_S_i2s_40013000_P_dmas_LEN 2 #define DT_N_S_soc_S_i2s_40013000_P_dmas_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_dma_names {"tx", "rx"} +#define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_0 "tx" #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_0_STRING_UNQUOTED tx #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_0_STRING_TOKEN tx #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_0_STRING_UPPER_TOKEN TX -#define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_1 "rx" #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_1_STRING_UNQUOTED rx #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_1_STRING_TOKEN rx #define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_1_STRING_UPPER_TOKEN RX -#define DT_N_S_soc_S_i2s_40013000_P_dma_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_dma_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, dma_names, 0) \ fn(DT_N_S_soc_S_i2s_40013000, dma_names, 1) #define DT_N_S_soc_S_i2s_40013000_P_dma_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, dma_names, 0) DT_DEBRACKET_INTERNAL sep \ @@ -19161,10 +19833,71 @@ fn(DT_N_S_soc_S_i2s_40013000, dma_names, 1, __VA_ARGS__) #define DT_N_S_soc_S_i2s_40013000_P_dma_names_LEN 2 #define DT_N_S_soc_S_i2s_40013000_P_dma_names_EXISTS 1 -#define DT_N_S_soc_S_i2s_40013000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_i2s_40013000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_i2s_40013000_P_mck_enabled 0 #define DT_N_S_soc_S_i2s_40013000_P_mck_enabled_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_status "disabled" +#define DT_N_S_soc_S_i2s_40013000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_i2s_40013000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_i2s_40013000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_i2s_40013000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_i2s_40013000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_i2s_40013000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, status, 0) +#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, status, 0) +#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40013000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40013000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40013000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40013000_P_status_LEN 1 +#define DT_N_S_soc_S_i2s_40013000_P_status_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_compatible {"st,stm32h7-i2s", "st,stm32-i2s"} +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0 "st,stm32h7-i2s" +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-i2s +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_i2s +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_I2S +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1 "st,stm32-i2s" +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-i2s +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_STRING_TOKEN st_stm32_i2s +#define DT_N_S_soc_S_i2s_40013000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_I2S +#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0) \ + fn(DT_N_S_soc_S_i2s_40013000, compatible, 1) +#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40013000, compatible, 1) +#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2s_40013000, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40013000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40013000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40013000, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40013000_P_compatible_LEN 2 +#define DT_N_S_soc_S_i2s_40013000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bits 4096 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bus 9 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bits 60496 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_IDX_1_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0) \ + fn(DT_N_S_soc_S_i2s_40013000, clocks, 1) +#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40013000, clocks, 1) +#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_i2s_40013000, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40013000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2s_40013000, clocks, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_i2s_40013000, clocks, 1, __VA_ARGS__) +#define DT_N_S_soc_S_i2s_40013000_P_clocks_LEN 2 +#define DT_N_S_soc_S_i2s_40013000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_i2s_40013000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_wakeup_source 0 +#define DT_N_S_soc_S_i2s_40013000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2s_40013000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2s_40013000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/interrupt-controller@58000000 @@ -19183,6 +19916,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_interrupt_controller_58000000_FULL_NAME "interrupt-controller@58000000" +#define DT_N_S_soc_S_interrupt_controller_58000000_FULL_NAME_UNQUOTED interrupt-controller@58000000 +#define DT_N_S_soc_S_interrupt_controller_58000000_FULL_NAME_TOKEN interrupt_controller_58000000 +#define DT_N_S_soc_S_interrupt_controller_58000000_FULL_NAME_UPPER_TOKEN INTERRUPT_CONTROLLER_58000000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_interrupt_controller_58000000_PARENT DT_N_S_soc @@ -19208,13 +19944,13 @@ #define DT_N_S_soc_S_interrupt_controller_58000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_interrupt_controller_58000000_ORD 129 -#define DT_N_S_soc_S_interrupt_controller_58000000_ORD_STR_SORTABLE 00129 +#define DT_N_S_soc_S_interrupt_controller_58000000_ORD 132 +#define DT_N_S_soc_S_interrupt_controller_58000000_ORD_STR_SORTABLE 00132 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_interrupt_controller_58000000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ + 4, \ + 5, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_interrupt_controller_58000000_SUPPORTS_ORDS /* nothing */ @@ -19227,8 +19963,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_interrupt_controller_58000000_REG_NUM 1 #define DT_N_S_soc_S_interrupt_controller_58000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_REG_IDX_0_VAL_ADDRESS 1476395008 /* 0x58000000 */ -#define DT_N_S_soc_S_interrupt_controller_58000000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_interrupt_controller_58000000_REG_IDX_0_VAL_ADDRESS 1476395008 +#define DT_N_S_soc_S_interrupt_controller_58000000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_interrupt_controller_58000000_RANGES_NUM 0 #define DT_N_S_soc_S_interrupt_controller_58000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_interrupt_controller_58000000_IRQ_NUM 7 @@ -19328,94 +20064,78 @@ #define DT_N_S_soc_S_interrupt_controller_58000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_interrupt_controller_58000000_P_wakeup_source 0 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible {"st,stm32-exti"} -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0 "st,stm32-exti" -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-exti -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_exti -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_EXTI -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0) -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0) -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_LEN 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_reg {1476395008 /* 0x58000000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_IDX_0 1476395008 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_reg {1476395008, 1024} #define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_IDX_0 1476395008 #define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_interrupt_controller_58000000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts {6 /* 0x6 */, 0 /* 0x0 */, 7 /* 0x7 */, 0 /* 0x0 */, 8 /* 0x8 */, 0 /* 0x0 */, 9 /* 0x9 */, 0 /* 0x0 */, 10 /* 0xa */, 0 /* 0x0 */, 23 /* 0x17 */, 0 /* 0x0 */, 40 /* 0x28 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_0 6 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts {6, 0, 7, 0, 8, 0, 9, 0, 10, 0, 23, 0, 40, 0} #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_0 6 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_2 7 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_2 7 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_4 8 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_3 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_4 8 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_6 9 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_5 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_6 9 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_8 10 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_7 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_8_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_9 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_8 10 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_9_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_10 23 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_9 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_10_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_11 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_10 23 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_11_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_12 40 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_11 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_12_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_13 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_12 40 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_13_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_IDX_13 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names {"line0", "line1", "line2", "line3", "line4", "line5-9", "line10-15"} +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_0 "line0" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_0_STRING_UNQUOTED line0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_0_STRING_TOKEN line0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN LINE0 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_1 "line1" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_1_STRING_UNQUOTED line1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_1_STRING_TOKEN line1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN LINE1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_2 "line2" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_2_STRING_UNQUOTED line2 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_2_STRING_TOKEN line2 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN LINE2 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_3 "line3" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_3_STRING_UNQUOTED line3 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_3_STRING_TOKEN line3 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN LINE3 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_4_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_4 "line4" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_4_STRING_UNQUOTED line4 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_4_STRING_TOKEN line4 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_4_STRING_UPPER_TOKEN LINE4 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_5_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_5 "line5-9" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_5_STRING_UNQUOTED line5-9 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_5_STRING_TOKEN line5_9 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_5_STRING_UPPER_TOKEN LINE5_9 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_6_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_6 "line10-15" #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_6_STRING_UNQUOTED line10-15 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_6_STRING_TOKEN line10_15 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_6_STRING_UPPER_TOKEN LINE10_15 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_IDX_6_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_58000000, interrupt_names, 0) \ fn(DT_N_S_soc_S_interrupt_controller_58000000, interrupt_names, 1) \ fn(DT_N_S_soc_S_interrupt_controller_58000000, interrupt_names, 2) \ @@ -19446,41 +20166,37 @@ fn(DT_N_S_soc_S_interrupt_controller_58000000, interrupt_names, 6, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_LEN 7 #define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_controller 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_controller_EXISTS 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_num_lines 16 #define DT_N_S_soc_S_interrupt_controller_58000000_P_num_lines_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges {0 /* 0x0 */, 1 /* 0x1 */, 1 /* 0x1 */, 1 /* 0x1 */, 2 /* 0x2 */, 1 /* 0x1 */, 3 /* 0x3 */, 1 /* 0x1 */, 4 /* 0x4 */, 1 /* 0x1 */, 5 /* 0x5 */, 5 /* 0x5 */, 10 /* 0xa */, 6 /* 0x6 */} -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_0 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges {0, 1, 1, 1, 2, 1, 3, 1, 4, 1, 5, 5, 10, 6} #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_1 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_0 0 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_2 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_1 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_3 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_2 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_4 2 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_3 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_5 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_4 2 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_6 3 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_5 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_7 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_6 3 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_8 4 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_7 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_8_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_9 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_8 4 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_9_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_10 5 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_9 1 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_10_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_11 5 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_10 5 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_11_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_12 10 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_11 5 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_12_EXISTS 1 -#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_13 6 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_12 10 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_13_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_IDX_13 6 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_58000000, line_ranges, 0) \ fn(DT_N_S_soc_S_interrupt_controller_58000000, line_ranges, 1) \ fn(DT_N_S_soc_S_interrupt_controller_58000000, line_ranges, 2) \ @@ -19539,6 +20255,26 @@ fn(DT_N_S_soc_S_interrupt_controller_58000000, line_ranges, 13, __VA_ARGS__) #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_LEN 14 #define DT_N_S_soc_S_interrupt_controller_58000000_P_line_ranges_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible {"st,stm32-exti"} +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0 "st,stm32-exti" +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-exti +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_exti +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_EXTI +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0) +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0) +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_interrupt_controller_58000000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_LEN 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_wakeup_source 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_controller 1 +#define DT_N_S_soc_S_interrupt_controller_58000000_P_interrupt_controller_EXISTS 1 /* * Devicetree node: /soc/mailbox@58026400 @@ -19557,6 +20293,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_mailbox_58026400_FULL_NAME "mailbox@58026400" +#define DT_N_S_soc_S_mailbox_58026400_FULL_NAME_UNQUOTED mailbox@58026400 +#define DT_N_S_soc_S_mailbox_58026400_FULL_NAME_TOKEN mailbox_58026400 +#define DT_N_S_soc_S_mailbox_58026400_FULL_NAME_UPPER_TOKEN MAILBOX_58026400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_mailbox_58026400_PARENT DT_N_S_soc @@ -19582,14 +20321,14 @@ #define DT_N_S_soc_S_mailbox_58026400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_mailbox_58026400_ORD 130 -#define DT_N_S_soc_S_mailbox_58026400_ORD_STR_SORTABLE 00130 +#define DT_N_S_soc_S_mailbox_58026400_ORD 133 +#define DT_N_S_soc_S_mailbox_58026400_ORD_STR_SORTABLE 00133 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_mailbox_58026400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_mailbox_58026400_SUPPORTS_ORDS /* nothing */ @@ -19603,8 +20342,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_mailbox_58026400_REG_NUM 1 #define DT_N_S_soc_S_mailbox_58026400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_REG_IDX_0_VAL_ADDRESS 1476551680 /* 0x58026400 */ -#define DT_N_S_soc_S_mailbox_58026400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_mailbox_58026400_REG_IDX_0_VAL_ADDRESS 1476551680 +#define DT_N_S_soc_S_mailbox_58026400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_mailbox_58026400_RANGES_NUM 0 #define DT_N_S_soc_S_mailbox_58026400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_mailbox_58026400_IRQ_NUM 1 @@ -19632,20 +20371,32 @@ #define DT_N_S_soc_S_mailbox_58026400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_mailbox_58026400_P_wakeup_source 0 -#define DT_N_S_soc_S_mailbox_58026400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_mailbox_58026400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bus 224 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bits 33554432 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0) +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0) +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_LEN 1 +#define DT_N_S_soc_S_mailbox_58026400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_interrupts {125, 0} +#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_0 125 +#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_status "okay" #define DT_N_S_soc_S_mailbox_58026400_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_mailbox_58026400_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_mailbox_58026400_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_mailbox_58026400_P_status_IDX_0 "okay" #define DT_N_S_soc_S_mailbox_58026400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_mailbox_58026400_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_mailbox_58026400_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_mailbox_58026400_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_mailbox_58026400_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mailbox_58026400, status, 0) #define DT_N_S_soc_S_mailbox_58026400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mailbox_58026400, status, 0) #define DT_N_S_soc_S_mailbox_58026400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mailbox_58026400, status, 0, __VA_ARGS__) @@ -19653,16 +20404,16 @@ #define DT_N_S_soc_S_mailbox_58026400_P_status_LEN 1 #define DT_N_S_soc_S_mailbox_58026400_P_status_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_compatible {"st,stm32-hsem-mailbox", "st,mbox-stm32-hsem"} +#define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_0 "st,stm32-hsem-mailbox" #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-hsem-mailbox #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_0_STRING_TOKEN st_stm32_hsem_mailbox #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_HSEM_MAILBOX -#define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_1 "st,mbox-stm32-hsem" #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_1_STRING_UNQUOTED st,mbox-stm32-hsem #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_1_STRING_TOKEN st_mbox_stm32_hsem #define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_MBOX_STM32_HSEM -#define DT_N_S_soc_S_mailbox_58026400_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mailbox_58026400, compatible, 0) \ fn(DT_N_S_soc_S_mailbox_58026400, compatible, 1) #define DT_N_S_soc_S_mailbox_58026400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mailbox_58026400, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -19673,32 +20424,18 @@ fn(DT_N_S_soc_S_mailbox_58026400, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_mailbox_58026400_P_compatible_LEN 2 #define DT_N_S_soc_S_mailbox_58026400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_reg {1476551680 /* 0x58026400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_mailbox_58026400_P_reg_IDX_0 1476551680 +#define DT_N_S_soc_S_mailbox_58026400_P_reg {1476551680, 1024} #define DT_N_S_soc_S_mailbox_58026400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_mailbox_58026400_P_reg_IDX_0 1476551680 #define DT_N_S_soc_S_mailbox_58026400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_mailbox_58026400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_interrupts {125 /* 0x7d */, 0 /* 0x0 */} -#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_0 125 -#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bus 224 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bits 33554432 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0) -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0) -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_mailbox_58026400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_LEN 1 -#define DT_N_S_soc_S_mailbox_58026400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_mailbox_58026400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_mailbox_58026400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_wakeup_source 0 +#define DT_N_S_soc_S_mailbox_58026400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_mailbox_58026400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_mailbox_58026400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/memory@38800000 @@ -19717,6 +20454,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_memory_38800000_FULL_NAME "memory@38800000" +#define DT_N_S_soc_S_memory_38800000_FULL_NAME_UNQUOTED memory@38800000 +#define DT_N_S_soc_S_memory_38800000_FULL_NAME_TOKEN memory_38800000 +#define DT_N_S_soc_S_memory_38800000_FULL_NAME_UPPER_TOKEN MEMORY_38800000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_memory_38800000_PARENT DT_N_S_soc @@ -19742,13 +20482,13 @@ #define DT_N_S_soc_S_memory_38800000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_38800000_ORD 131 -#define DT_N_S_soc_S_memory_38800000_ORD_STR_SORTABLE 00131 +#define DT_N_S_soc_S_memory_38800000_ORD 134 +#define DT_N_S_soc_S_memory_38800000_ORD_STR_SORTABLE 00134 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_38800000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_38800000_SUPPORTS_ORDS /* nothing */ @@ -19762,8 +20502,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_memory_38800000_REG_NUM 1 #define DT_N_S_soc_S_memory_38800000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_REG_IDX_0_VAL_ADDRESS 947912704 /* 0x38800000 */ -#define DT_N_S_soc_S_memory_38800000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ +#define DT_N_S_soc_S_memory_38800000_REG_IDX_0_VAL_ADDRESS 947912704 +#define DT_N_S_soc_S_memory_38800000_REG_IDX_0_VAL_SIZE 4096 #define DT_N_S_soc_S_memory_38800000_RANGES_NUM 0 #define DT_N_S_soc_S_memory_38800000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_memory_38800000_IRQ_NUM 0 @@ -19784,20 +20524,26 @@ #define DT_N_S_soc_S_memory_38800000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_memory_38800000_P_wakeup_source 0 -#define DT_N_S_soc_S_memory_38800000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_memory_38800000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region "BACKUP_SRAM" +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_STRING_UNQUOTED BACKUP_SRAM +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_STRING_TOKEN BACKUP_SRAM +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_STRING_UPPER_TOKEN BACKUP_SRAM +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_IDX_0 "BACKUP_SRAM" +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0) +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0) +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_LEN 1 +#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_status "disabled" #define DT_N_S_soc_S_memory_38800000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_memory_38800000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_memory_38800000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_memory_38800000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_memory_38800000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_memory_38800000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_memory_38800000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_memory_38800000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_memory_38800000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_38800000, status, 0) #define DT_N_S_soc_S_memory_38800000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_38800000, status, 0) #define DT_N_S_soc_S_memory_38800000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_38800000, status, 0, __VA_ARGS__) @@ -19805,16 +20551,16 @@ #define DT_N_S_soc_S_memory_38800000_P_status_LEN 1 #define DT_N_S_soc_S_memory_38800000_P_status_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_compatible {"zephyr,memory-region", "st,stm32-backup-sram"} +#define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_0 "zephyr,memory-region" #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_0_STRING_UNQUOTED zephyr,memory-region #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_0_STRING_TOKEN zephyr_memory_region #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_MEMORY_REGION -#define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_1 "st,stm32-backup-sram" #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-backup-sram #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_1_STRING_TOKEN st_stm32_backup_sram #define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_BACKUP_SRAM -#define DT_N_S_soc_S_memory_38800000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_38800000, compatible, 0) \ fn(DT_N_S_soc_S_memory_38800000, compatible, 1) #define DT_N_S_soc_S_memory_38800000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_38800000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -19825,11 +20571,11 @@ fn(DT_N_S_soc_S_memory_38800000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_memory_38800000_P_compatible_LEN 2 #define DT_N_S_soc_S_memory_38800000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_reg {947912704 /* 0x38800000 */, 4096 /* 0x1000 */} -#define DT_N_S_soc_S_memory_38800000_P_reg_IDX_0 947912704 +#define DT_N_S_soc_S_memory_38800000_P_reg {947912704, 4096} #define DT_N_S_soc_S_memory_38800000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_reg_IDX_1 4096 +#define DT_N_S_soc_S_memory_38800000_P_reg_IDX_0 947912704 #define DT_N_S_soc_S_memory_38800000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_memory_38800000_P_reg_IDX_1 4096 #define DT_N_S_soc_S_memory_38800000_P_reg_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -19845,18 +20591,10 @@ #define DT_N_S_soc_S_memory_38800000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_memory_38800000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_memory_38800000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region "BACKUP_SRAM" -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_STRING_UNQUOTED BACKUP_SRAM -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_STRING_TOKEN BACKUP_SRAM -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_STRING_UPPER_TOKEN BACKUP_SRAM -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_IDX_0 "BACKUP_SRAM" -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0) -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0) -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_38800000, zephyr_memory_region, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_LEN 1 -#define DT_N_S_soc_S_memory_38800000_P_zephyr_memory_region_EXISTS 1 +#define DT_N_S_soc_S_memory_38800000_P_wakeup_source 0 +#define DT_N_S_soc_S_memory_38800000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_memory_38800000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_memory_38800000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/rng@48021800 @@ -19875,6 +20613,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_rng_48021800_FULL_NAME "rng@48021800" +#define DT_N_S_soc_S_rng_48021800_FULL_NAME_UNQUOTED rng@48021800 +#define DT_N_S_soc_S_rng_48021800_FULL_NAME_TOKEN rng_48021800 +#define DT_N_S_soc_S_rng_48021800_FULL_NAME_UPPER_TOKEN RNG_48021800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_rng_48021800_PARENT DT_N_S_soc @@ -19900,14 +20641,14 @@ #define DT_N_S_soc_S_rng_48021800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rng_48021800_ORD 132 -#define DT_N_S_soc_S_rng_48021800_ORD_STR_SORTABLE 00132 +#define DT_N_S_soc_S_rng_48021800_ORD 135 +#define DT_N_S_soc_S_rng_48021800_ORD_STR_SORTABLE 00135 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rng_48021800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rng_48021800_SUPPORTS_ORDS /* nothing */ @@ -19920,8 +20661,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_rng_48021800_REG_NUM 1 #define DT_N_S_soc_S_rng_48021800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_REG_IDX_0_VAL_ADDRESS 1208096768 /* 0x48021800 */ -#define DT_N_S_soc_S_rng_48021800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_rng_48021800_REG_IDX_0_VAL_ADDRESS 1208096768 +#define DT_N_S_soc_S_rng_48021800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_rng_48021800_RANGES_NUM 0 #define DT_N_S_soc_S_rng_48021800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_rng_48021800_IRQ_NUM 1 @@ -19944,20 +20685,32 @@ #define DT_N_S_soc_S_rng_48021800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_rng_48021800_P_wakeup_source 0 -#define DT_N_S_soc_S_rng_48021800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_rng_48021800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_reg {1208096768, 1024} +#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_0 1208096768 +#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_rng_48021800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bus 220 +#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bits 64 +#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_48021800, clocks, 0) +#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_48021800, clocks, 0) +#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_48021800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_48021800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_rng_48021800_P_clocks_LEN 1 +#define DT_N_S_soc_S_rng_48021800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_rng_48021800_P_status "okay" #define DT_N_S_soc_S_rng_48021800_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_rng_48021800_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_rng_48021800_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_rng_48021800_P_status_IDX_0 "okay" #define DT_N_S_soc_S_rng_48021800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_rng_48021800_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_rng_48021800_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_rng_48021800_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_rng_48021800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_rng_48021800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_48021800, status, 0) #define DT_N_S_soc_S_rng_48021800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_48021800, status, 0) #define DT_N_S_soc_S_rng_48021800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_48021800, status, 0, __VA_ARGS__) @@ -19965,43 +20718,29 @@ #define DT_N_S_soc_S_rng_48021800_P_status_LEN 1 #define DT_N_S_soc_S_rng_48021800_P_status_EXISTS 1 #define DT_N_S_soc_S_rng_48021800_P_compatible {"st,stm32-rng"} +#define DT_N_S_soc_S_rng_48021800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rng_48021800_P_compatible_IDX_0 "st,stm32-rng" #define DT_N_S_soc_S_rng_48021800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rng #define DT_N_S_soc_S_rng_48021800_P_compatible_IDX_0_STRING_TOKEN st_stm32_rng #define DT_N_S_soc_S_rng_48021800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RNG -#define DT_N_S_soc_S_rng_48021800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rng_48021800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_48021800, compatible, 0) #define DT_N_S_soc_S_rng_48021800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_48021800, compatible, 0) #define DT_N_S_soc_S_rng_48021800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_48021800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_rng_48021800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_48021800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_rng_48021800_P_compatible_LEN 1 #define DT_N_S_soc_S_rng_48021800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_reg {1208096768 /* 0x48021800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_0 1208096768 -#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_rng_48021800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_interrupts {80 /* 0x50 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_rng_48021800_P_interrupts_IDX_0 80 +#define DT_N_S_soc_S_rng_48021800_P_interrupts {80, 0} #define DT_N_S_soc_S_rng_48021800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_rng_48021800_P_interrupts_IDX_0 80 #define DT_N_S_soc_S_rng_48021800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_rng_48021800_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bus 220 -#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bits 64 -#define DT_N_S_soc_S_rng_48021800_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rng_48021800, clocks, 0) -#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rng_48021800, clocks, 0) -#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rng_48021800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_rng_48021800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rng_48021800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_rng_48021800_P_clocks_LEN 1 -#define DT_N_S_soc_S_rng_48021800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_rng_48021800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_rng_48021800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_wakeup_source 0 +#define DT_N_S_soc_S_rng_48021800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_rng_48021800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_rng_48021800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/sdmmc@48022400 @@ -20020,6 +20759,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_sdmmc_48022400_FULL_NAME "sdmmc@48022400" +#define DT_N_S_soc_S_sdmmc_48022400_FULL_NAME_UNQUOTED sdmmc@48022400 +#define DT_N_S_soc_S_sdmmc_48022400_FULL_NAME_TOKEN sdmmc_48022400 +#define DT_N_S_soc_S_sdmmc_48022400_FULL_NAME_UPPER_TOKEN SDMMC_48022400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_sdmmc_48022400_PARENT DT_N_S_soc @@ -20045,15 +20787,15 @@ #define DT_N_S_soc_S_sdmmc_48022400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_sdmmc_48022400_ORD 133 -#define DT_N_S_soc_S_sdmmc_48022400_ORD_STR_SORTABLE 00133 +#define DT_N_S_soc_S_sdmmc_48022400_ORD 136 +#define DT_N_S_soc_S_sdmmc_48022400_ORD_STR_SORTABLE 00136 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_sdmmc_48022400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_sdmmc_48022400_SUPPORTS_ORDS /* nothing */ @@ -20066,8 +20808,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_sdmmc_48022400_REG_NUM 1 #define DT_N_S_soc_S_sdmmc_48022400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_REG_IDX_0_VAL_ADDRESS 1208099840 /* 0x48022400 */ -#define DT_N_S_soc_S_sdmmc_48022400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_sdmmc_48022400_REG_IDX_0_VAL_ADDRESS 1208099840 +#define DT_N_S_soc_S_sdmmc_48022400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_sdmmc_48022400_RANGES_NUM 0 #define DT_N_S_soc_S_sdmmc_48022400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_sdmmc_48022400_IRQ_NUM 1 @@ -20090,50 +20832,6 @@ #define DT_N_S_soc_S_sdmmc_48022400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_sdmmc_48022400_P_wakeup_source 0 -#define DT_N_S_soc_S_sdmmc_48022400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_status "disabled" -#define DT_N_S_soc_S_sdmmc_48022400_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_sdmmc_48022400_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_sdmmc_48022400_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_sdmmc_48022400_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_sdmmc_48022400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_sdmmc_48022400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_sdmmc_48022400_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0) -#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0) -#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_48022400_P_status_LEN 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_status_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible {"st,stm32-sdmmc"} -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0 "st,stm32-sdmmc" -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sdmmc -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_STRING_TOKEN st_stm32_sdmmc -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SDMMC -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0) -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0) -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_LEN 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_reg {1208099840 /* 0x48022400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_0 1208099840 -#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts {124 /* 0x7c */, 0 /* 0x0 */} -#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_0 124 -#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_sdmmc_48022400_P_clocks_IDX_0_VAL_bus 220 @@ -20156,8 +20854,12 @@ fn(DT_N_S_soc_S_sdmmc_48022400, clocks, 1, __VA_ARGS__) #define DT_N_S_soc_S_sdmmc_48022400_P_clocks_LEN 2 #define DT_N_S_soc_S_sdmmc_48022400_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_reg {1208099840, 1024} +#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_0 1208099840 +#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_sdmmc_48022400_P_reg_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_sdmmc_48022400_P_resets_IDX_0_VAL_id 4233 @@ -20169,13 +20871,52 @@ #define DT_N_S_soc_S_sdmmc_48022400_P_resets_LEN 1 #define DT_N_S_soc_S_sdmmc_48022400_P_resets_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_bus_width 1 -#define DT_N_S_soc_S_sdmmc_48022400_P_bus_width_ENUM_IDX 0 -#define DT_N_S_soc_S_sdmmc_48022400_P_bus_width_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_bus_width_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_sdmmc_48022400_P_bus_width_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_bus_width_IDX_0_ENUM_VAL_1_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_bus_width_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_clk_div 0 #define DT_N_S_soc_S_sdmmc_48022400_P_clk_div_EXISTS 1 #define DT_N_S_soc_S_sdmmc_48022400_P_idma 0 #define DT_N_S_soc_S_sdmmc_48022400_P_idma_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_status "disabled" +#define DT_N_S_soc_S_sdmmc_48022400_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_sdmmc_48022400_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_sdmmc_48022400_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_sdmmc_48022400_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_sdmmc_48022400_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_sdmmc_48022400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0) +#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0) +#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_48022400_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_48022400, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_48022400_P_status_LEN 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_status_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible {"st,stm32-sdmmc"} +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0 "st,stm32-sdmmc" +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sdmmc +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_STRING_TOKEN st_stm32_sdmmc +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SDMMC +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0) +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0) +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_48022400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_LEN 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts {124, 0} +#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_0 124 +#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_sdmmc_48022400_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_wakeup_source 0 +#define DT_N_S_soc_S_sdmmc_48022400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_sdmmc_48022400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/sdmmc@52007000 @@ -20194,6 +20935,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_sdmmc_52007000_FULL_NAME "sdmmc@52007000" +#define DT_N_S_soc_S_sdmmc_52007000_FULL_NAME_UNQUOTED sdmmc@52007000 +#define DT_N_S_soc_S_sdmmc_52007000_FULL_NAME_TOKEN sdmmc_52007000 +#define DT_N_S_soc_S_sdmmc_52007000_FULL_NAME_UPPER_TOKEN SDMMC_52007000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_sdmmc_52007000_PARENT DT_N_S_soc @@ -20219,15 +20963,15 @@ #define DT_N_S_soc_S_sdmmc_52007000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_sdmmc_52007000_ORD 134 -#define DT_N_S_soc_S_sdmmc_52007000_ORD_STR_SORTABLE 00134 +#define DT_N_S_soc_S_sdmmc_52007000_ORD 137 +#define DT_N_S_soc_S_sdmmc_52007000_ORD_STR_SORTABLE 00137 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_sdmmc_52007000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_sdmmc_52007000_SUPPORTS_ORDS /* nothing */ @@ -20240,8 +20984,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_sdmmc_52007000_REG_NUM 1 #define DT_N_S_soc_S_sdmmc_52007000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_REG_IDX_0_VAL_ADDRESS 1375760384 /* 0x52007000 */ -#define DT_N_S_soc_S_sdmmc_52007000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_sdmmc_52007000_REG_IDX_0_VAL_ADDRESS 1375760384 +#define DT_N_S_soc_S_sdmmc_52007000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_sdmmc_52007000_RANGES_NUM 0 #define DT_N_S_soc_S_sdmmc_52007000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_sdmmc_52007000_IRQ_NUM 1 @@ -20264,50 +21008,6 @@ #define DT_N_S_soc_S_sdmmc_52007000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_sdmmc_52007000_P_wakeup_source 0 -#define DT_N_S_soc_S_sdmmc_52007000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_status "disabled" -#define DT_N_S_soc_S_sdmmc_52007000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_sdmmc_52007000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_sdmmc_52007000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_sdmmc_52007000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_sdmmc_52007000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_sdmmc_52007000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_sdmmc_52007000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0) -#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0) -#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_52007000_P_status_LEN 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_status_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible {"st,stm32-sdmmc"} -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0 "st,stm32-sdmmc" -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sdmmc -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_STRING_TOKEN st_stm32_sdmmc -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SDMMC -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0) -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0) -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_LEN 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_reg {1375760384 /* 0x52007000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_0 1375760384 -#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts {49 /* 0x31 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_0 49 -#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_sdmmc_52007000_P_clocks_IDX_0_VAL_bus 212 @@ -20330,8 +21030,12 @@ fn(DT_N_S_soc_S_sdmmc_52007000, clocks, 1, __VA_ARGS__) #define DT_N_S_soc_S_sdmmc_52007000_P_clocks_LEN 2 #define DT_N_S_soc_S_sdmmc_52007000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_reg {1375760384, 1024} +#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_0 1375760384 +#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_sdmmc_52007000_P_reg_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_sdmmc_52007000_P_resets_IDX_0_VAL_id 3984 @@ -20343,13 +21047,52 @@ #define DT_N_S_soc_S_sdmmc_52007000_P_resets_LEN 1 #define DT_N_S_soc_S_sdmmc_52007000_P_resets_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_bus_width 1 -#define DT_N_S_soc_S_sdmmc_52007000_P_bus_width_ENUM_IDX 0 -#define DT_N_S_soc_S_sdmmc_52007000_P_bus_width_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_bus_width_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_sdmmc_52007000_P_bus_width_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_bus_width_IDX_0_ENUM_VAL_1_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_bus_width_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_clk_div 0 #define DT_N_S_soc_S_sdmmc_52007000_P_clk_div_EXISTS 1 #define DT_N_S_soc_S_sdmmc_52007000_P_idma 0 #define DT_N_S_soc_S_sdmmc_52007000_P_idma_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_status "disabled" +#define DT_N_S_soc_S_sdmmc_52007000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_sdmmc_52007000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_sdmmc_52007000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_sdmmc_52007000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_sdmmc_52007000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_sdmmc_52007000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0) +#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0) +#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_52007000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_52007000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_52007000_P_status_LEN 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_status_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible {"st,stm32-sdmmc"} +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0 "st,stm32-sdmmc" +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-sdmmc +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_STRING_TOKEN st_stm32_sdmmc +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_SDMMC +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0) +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0) +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_sdmmc_52007000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_LEN 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts {49, 0} +#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_0 49 +#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_sdmmc_52007000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_wakeup_source 0 +#define DT_N_S_soc_S_sdmmc_52007000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_sdmmc_52007000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/serial@40004800 @@ -20368,6 +21111,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40004800_FULL_NAME "serial@40004800" +#define DT_N_S_soc_S_serial_40004800_FULL_NAME_UNQUOTED serial@40004800 +#define DT_N_S_soc_S_serial_40004800_FULL_NAME_TOKEN serial_40004800 +#define DT_N_S_soc_S_serial_40004800_FULL_NAME_UPPER_TOKEN SERIAL_40004800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40004800_PARENT DT_N_S_soc @@ -20393,15 +21139,15 @@ #define DT_N_S_soc_S_serial_40004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40004800_ORD 135 -#define DT_N_S_soc_S_serial_40004800_ORD_STR_SORTABLE 00135 +#define DT_N_S_soc_S_serial_40004800_ORD 138 +#define DT_N_S_soc_S_serial_40004800_ORD_STR_SORTABLE 00138 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40004800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40004800_SUPPORTS_ORDS /* nothing */ @@ -20415,8 +21161,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40004800_REG_NUM 1 #define DT_N_S_soc_S_serial_40004800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_ADDRESS 1073760256 /* 0x40004800 */ -#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_ADDRESS 1073760256 +#define DT_N_S_soc_S_serial_40004800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40004800_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40004800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40004800_IRQ_NUM 1 @@ -20444,59 +21190,12 @@ #define DT_N_S_soc_S_serial_40004800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40004800_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40004800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_status "disabled" -#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_serial_40004800_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_serial_40004800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_serial_40004800_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, status, 0) -#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, status, 0) -#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004800_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40004800_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_compatible {"st,stm32-usart", "st,stm32-uart"} -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0 "st,stm32-usart" -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) \ - fn(DT_N_S_soc_S_serial_40004800, compatible, 1) -#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40004800, compatible, 1) -#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40004800_P_compatible_LEN 2 -#define DT_N_S_soc_S_serial_40004800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_reg {1073760256 /* 0x40004800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0 1073760256 +#define DT_N_S_soc_S_serial_40004800_P_reg {1073760256, 1024} #define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_0 1073760256 #define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40004800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_interrupts {39 /* 0x27 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0 39 -#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40004800_P_clocks_IDX_0_VAL_bus 232 @@ -20509,10 +21208,6 @@ #define DT_N_S_soc_S_serial_40004800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004800_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40004800_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_serial_40004800_P_resets_IDX_0_VAL_id 4626 @@ -20523,10 +21218,12 @@ #define DT_N_S_soc_S_serial_40004800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, resets, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40004800_P_resets_LEN 1 #define DT_N_S_soc_S_serial_40004800_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40004800_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40004800_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40004800_P_rx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_interrupts {39, 0} +#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_0 39 +#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40004800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_single_wire 0 #define DT_N_S_soc_S_serial_40004800_P_single_wire_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_tx_rx_swap 0 @@ -20541,6 +21238,53 @@ #define DT_N_S_soc_S_serial_40004800_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40004800_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40004800_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40004800_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_status "disabled" +#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_serial_40004800_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_serial_40004800_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_serial_40004800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, status, 0) +#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, status, 0) +#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004800_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40004800_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_compatible {"st,stm32-usart", "st,stm32-uart"} +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0 "st,stm32-usart" +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-usart +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_TOKEN st_stm32_usart +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_USART +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40004800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) \ + fn(DT_N_S_soc_S_serial_40004800, compatible, 1) +#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40004800, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40004800, compatible, 1) +#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40004800, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_40004800, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40004800_P_compatible_LEN 2 +#define DT_N_S_soc_S_serial_40004800_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40004800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40004800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40004800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40004800_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40004800_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40004800_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/serial@40005000 @@ -20559,6 +21303,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40005000_FULL_NAME "serial@40005000" +#define DT_N_S_soc_S_serial_40005000_FULL_NAME_UNQUOTED serial@40005000 +#define DT_N_S_soc_S_serial_40005000_FULL_NAME_TOKEN serial_40005000 +#define DT_N_S_soc_S_serial_40005000_FULL_NAME_UPPER_TOKEN SERIAL_40005000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40005000_PARENT DT_N_S_soc @@ -20584,15 +21331,15 @@ #define DT_N_S_soc_S_serial_40005000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40005000_ORD 136 -#define DT_N_S_soc_S_serial_40005000_ORD_STR_SORTABLE 00136 +#define DT_N_S_soc_S_serial_40005000_ORD 139 +#define DT_N_S_soc_S_serial_40005000_ORD_STR_SORTABLE 00139 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40005000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40005000_SUPPORTS_ORDS /* nothing */ @@ -20605,8 +21352,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40005000_REG_NUM 1 #define DT_N_S_soc_S_serial_40005000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_VAL_ADDRESS 1073762304 /* 0x40005000 */ -#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_VAL_ADDRESS 1073762304 +#define DT_N_S_soc_S_serial_40005000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40005000_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40005000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40005000_IRQ_NUM 1 @@ -20629,50 +21376,12 @@ #define DT_N_S_soc_S_serial_40005000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40005000_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40005000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40005000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_status "disabled" -#define DT_N_S_soc_S_serial_40005000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_serial_40005000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_serial_40005000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_serial_40005000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_serial_40005000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, status, 0) -#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, status, 0) -#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40005000_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40005000_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_compatible {"st,stm32-uart"} -#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, compatible, 0) -#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, compatible, 0) -#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40005000_P_compatible_LEN 1 -#define DT_N_S_soc_S_serial_40005000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_reg {1073762304 /* 0x40005000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_0 1073762304 +#define DT_N_S_soc_S_serial_40005000_P_reg {1073762304, 1024} #define DT_N_S_soc_S_serial_40005000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_0 1073762304 #define DT_N_S_soc_S_serial_40005000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40005000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_interrupts {53 /* 0x35 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_0 53 -#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40005000_P_clocks_IDX_0_VAL_bus 232 @@ -20685,10 +21394,6 @@ #define DT_N_S_soc_S_serial_40005000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40005000_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40005000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40005000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40005000_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_serial_40005000_P_resets_IDX_0_VAL_id 4628 @@ -20699,10 +21404,12 @@ #define DT_N_S_soc_S_serial_40005000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, resets, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40005000_P_resets_LEN 1 #define DT_N_S_soc_S_serial_40005000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40005000_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40005000_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40005000_P_rx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_interrupts {53, 0} +#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_0 53 +#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40005000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_single_wire 0 #define DT_N_S_soc_S_serial_40005000_P_single_wire_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_tx_rx_swap 0 @@ -20717,6 +21424,44 @@ #define DT_N_S_soc_S_serial_40005000_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40005000_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40005000_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40005000_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_status "disabled" +#define DT_N_S_soc_S_serial_40005000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_serial_40005000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_serial_40005000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_serial_40005000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, status, 0) +#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, status, 0) +#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40005000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40005000_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40005000_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_compatible {"st,stm32-uart"} +#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40005000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40005000, compatible, 0) +#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40005000, compatible, 0) +#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40005000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40005000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40005000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40005000_P_compatible_LEN 1 +#define DT_N_S_soc_S_serial_40005000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40005000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40005000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40005000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40005000_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40005000_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40005000_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/serial@40007c00 @@ -20735,6 +21480,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40007c00_FULL_NAME "serial@40007c00" +#define DT_N_S_soc_S_serial_40007c00_FULL_NAME_UNQUOTED serial@40007c00 +#define DT_N_S_soc_S_serial_40007c00_FULL_NAME_TOKEN serial_40007c00 +#define DT_N_S_soc_S_serial_40007c00_FULL_NAME_UPPER_TOKEN SERIAL_40007C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40007c00_PARENT DT_N_S_soc @@ -20760,15 +21508,15 @@ #define DT_N_S_soc_S_serial_40007c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007c00_ORD 137 -#define DT_N_S_soc_S_serial_40007c00_ORD_STR_SORTABLE 00137 +#define DT_N_S_soc_S_serial_40007c00_ORD 140 +#define DT_N_S_soc_S_serial_40007c00_ORD_STR_SORTABLE 00140 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007c00_SUPPORTS_ORDS /* nothing */ @@ -20781,8 +21529,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40007c00_REG_NUM 1 #define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_VAL_ADDRESS 1073773568 /* 0x40007c00 */ -#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_VAL_ADDRESS 1073773568 +#define DT_N_S_soc_S_serial_40007c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40007c00_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40007c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40007c00_IRQ_NUM 1 @@ -20805,50 +21553,12 @@ #define DT_N_S_soc_S_serial_40007c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40007c00_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40007c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40007c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_status "disabled" -#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_serial_40007c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_serial_40007c00_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, status, 0) -#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, status, 0) -#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007c00_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40007c00_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_compatible {"st,stm32-uart"} -#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0) -#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0) -#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007c00_P_compatible_LEN 1 -#define DT_N_S_soc_S_serial_40007c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_reg {1073773568 /* 0x40007c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_0 1073773568 +#define DT_N_S_soc_S_serial_40007c00_P_reg {1073773568, 1024} #define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_0 1073773568 #define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40007c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_interrupts {83 /* 0x53 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_0 83 -#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40007c00_P_clocks_IDX_0_VAL_bus 232 @@ -20861,10 +21571,6 @@ #define DT_N_S_soc_S_serial_40007c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40007c00_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40007c00_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40007c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_40007c00_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_serial_40007c00_P_resets_IDX_0_VAL_id 4639 @@ -20875,10 +21581,12 @@ #define DT_N_S_soc_S_serial_40007c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, resets, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40007c00_P_resets_LEN 1 #define DT_N_S_soc_S_serial_40007c00_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40007c00_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40007c00_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40007c00_P_rx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_interrupts {83, 0} +#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_0 83 +#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40007c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_single_wire 0 #define DT_N_S_soc_S_serial_40007c00_P_single_wire_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_tx_rx_swap 0 @@ -20893,6 +21601,44 @@ #define DT_N_S_soc_S_serial_40007c00_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40007c00_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40007c00_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_40007c00_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_status "disabled" +#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_serial_40007c00_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_serial_40007c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, status, 0) +#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, status, 0) +#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007c00_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40007c00_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_compatible {"st,stm32-uart"} +#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40007c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0) +#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0) +#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007c00, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007c00_P_compatible_LEN 1 +#define DT_N_S_soc_S_serial_40007c00_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40007c00_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40007c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40007c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40007c00_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40007c00_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40007c00_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/serial@58000c00 @@ -20911,6 +21657,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_58000c00_FULL_NAME "serial@58000c00" +#define DT_N_S_soc_S_serial_58000c00_FULL_NAME_UNQUOTED serial@58000c00 +#define DT_N_S_soc_S_serial_58000c00_FULL_NAME_TOKEN serial_58000c00 +#define DT_N_S_soc_S_serial_58000c00_FULL_NAME_UPPER_TOKEN SERIAL_58000C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_58000c00_PARENT DT_N_S_soc @@ -20936,15 +21685,15 @@ #define DT_N_S_soc_S_serial_58000c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_58000c00_ORD 138 -#define DT_N_S_soc_S_serial_58000c00_ORD_STR_SORTABLE 00138 +#define DT_N_S_soc_S_serial_58000c00_ORD 141 +#define DT_N_S_soc_S_serial_58000c00_ORD_STR_SORTABLE 00141 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_58000c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_58000c00_SUPPORTS_ORDS /* nothing */ @@ -20958,8 +21707,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_58000c00_REG_NUM 1 #define DT_N_S_soc_S_serial_58000c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_REG_IDX_0_VAL_ADDRESS 1476398080 /* 0x58000c00 */ -#define DT_N_S_soc_S_serial_58000c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_58000c00_REG_IDX_0_VAL_ADDRESS 1476398080 +#define DT_N_S_soc_S_serial_58000c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_58000c00_RANGES_NUM 0 #define DT_N_S_soc_S_serial_58000c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_58000c00_IRQ_NUM 1 @@ -20987,59 +21736,12 @@ #define DT_N_S_soc_S_serial_58000c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_58000c00_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_58000c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_58000c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_status "disabled" -#define DT_N_S_soc_S_serial_58000c00_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_serial_58000c00_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_serial_58000c00_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_58000c00_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_serial_58000c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_serial_58000c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_serial_58000c00_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_58000c00, status, 0) -#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_58000c00, status, 0) -#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_58000c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_58000c00, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_58000c00_P_status_LEN 1 -#define DT_N_S_soc_S_serial_58000c00_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_compatible {"st,stm32-lpuart", "st,stm32-uart"} -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0 "st,stm32-lpuart" -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lpuart -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_lpuart -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LPUART -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1 "st,stm32-uart" -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0) \ - fn(DT_N_S_soc_S_serial_58000c00, compatible, 1) -#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_58000c00, compatible, 1) -#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_serial_58000c00, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_serial_58000c00, compatible, 1, __VA_ARGS__) -#define DT_N_S_soc_S_serial_58000c00_P_compatible_LEN 2 -#define DT_N_S_soc_S_serial_58000c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_reg {1476398080 /* 0x58000c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_58000c00_P_reg_IDX_0 1476398080 +#define DT_N_S_soc_S_serial_58000c00_P_reg {1476398080, 1024} #define DT_N_S_soc_S_serial_58000c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_58000c00_P_reg_IDX_0 1476398080 #define DT_N_S_soc_S_serial_58000c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_58000c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_interrupts {142 /* 0x8e */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_0 142 -#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_58000c00_P_clocks_IDX_0_VAL_bus 244 @@ -21052,10 +21754,6 @@ #define DT_N_S_soc_S_serial_58000c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_58000c00, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_58000c00_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_58000c00_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_58000c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_hw_flow_control 0 -#define DT_N_S_soc_S_serial_58000c00_P_hw_flow_control_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_resets_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller #define DT_N_S_soc_S_serial_58000c00_P_resets_IDX_0_VAL_id 4995 @@ -21066,10 +21764,12 @@ #define DT_N_S_soc_S_serial_58000c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_58000c00, resets, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_58000c00_P_resets_LEN 1 #define DT_N_S_soc_S_serial_58000c00_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_tx_invert 0 -#define DT_N_S_soc_S_serial_58000c00_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_58000c00_P_rx_invert 0 -#define DT_N_S_soc_S_serial_58000c00_P_rx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_interrupts {142, 0} +#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_0 142 +#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_58000c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_single_wire 0 #define DT_N_S_soc_S_serial_58000c00_P_single_wire_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_tx_rx_swap 0 @@ -21084,6 +21784,53 @@ #define DT_N_S_soc_S_serial_58000c00_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_58000c00_P_fifo_enable 0 #define DT_N_S_soc_S_serial_58000c00_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_hw_flow_control 0 +#define DT_N_S_soc_S_serial_58000c00_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_status "disabled" +#define DT_N_S_soc_S_serial_58000c00_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_serial_58000c00_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_serial_58000c00_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_serial_58000c00_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_serial_58000c00_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_serial_58000c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_58000c00, status, 0) +#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_58000c00, status, 0) +#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_58000c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_58000c00_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_58000c00, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_58000c00_P_status_LEN 1 +#define DT_N_S_soc_S_serial_58000c00_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_compatible {"st,stm32-lpuart", "st,stm32-uart"} +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0 "st,stm32-lpuart" +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lpuart +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_lpuart +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LPUART +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1 "st,stm32-uart" +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_58000c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0) \ + fn(DT_N_S_soc_S_serial_58000c00, compatible, 1) +#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_58000c00, compatible, 1) +#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_serial_58000c00, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_58000c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_58000c00, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_serial_58000c00, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_serial_58000c00_P_compatible_LEN 2 +#define DT_N_S_soc_S_serial_58000c00_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_58000c00_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_58000c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_58000c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_tx_invert 0 +#define DT_N_S_soc_S_serial_58000c00_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_58000c00_P_rx_invert 0 +#define DT_N_S_soc_S_serial_58000c00_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/spi@40003800 @@ -21102,6 +21849,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_spi_40003800_FULL_NAME "spi@40003800" +#define DT_N_S_soc_S_spi_40003800_FULL_NAME_UNQUOTED spi@40003800 +#define DT_N_S_soc_S_spi_40003800_FULL_NAME_TOKEN spi_40003800 +#define DT_N_S_soc_S_spi_40003800_FULL_NAME_UPPER_TOKEN SPI_40003800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spi_40003800_PARENT DT_N_S_soc @@ -21127,14 +21877,14 @@ #define DT_N_S_soc_S_spi_40003800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40003800_ORD 139 -#define DT_N_S_soc_S_spi_40003800_ORD_STR_SORTABLE 00139 +#define DT_N_S_soc_S_spi_40003800_ORD 142 +#define DT_N_S_soc_S_spi_40003800_ORD_STR_SORTABLE 00142 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40003800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40003800_SUPPORTS_ORDS /* nothing */ @@ -21149,8 +21899,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spi_40003800_REG_NUM 1 #define DT_N_S_soc_S_spi_40003800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 /* 0x40003800 */ -#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_ADDRESS 1073756160 +#define DT_N_S_soc_S_spi_40003800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_spi_40003800_RANGES_NUM 0 #define DT_N_S_soc_S_spi_40003800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spi_40003800_IRQ_NUM 1 @@ -21183,20 +21933,32 @@ #define DT_N_S_soc_S_spi_40003800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_spi_40003800_P_wakeup_source 0 -#define DT_N_S_soc_S_spi_40003800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_midi_clock 0 +#define DT_N_S_soc_S_spi_40003800_P_midi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_mssi_clock 0 +#define DT_N_S_soc_S_spi_40003800_P_mssi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_fifo_enable 0 +#define DT_N_S_soc_S_spi_40003800_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_reg {1073756160, 1024} +#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0 1073756160 +#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_spi_40003800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_interrupts {36, 0} +#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0 36 +#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_spi_40003800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_status "disabled" #define DT_N_S_soc_S_spi_40003800_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_spi_40003800_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_spi_40003800_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_spi_40003800_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_spi_40003800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_spi_40003800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_spi_40003800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, status, 0) #define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003800, status, 0) #define DT_N_S_soc_S_spi_40003800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003800, status, 0, __VA_ARGS__) @@ -21204,21 +21966,21 @@ #define DT_N_S_soc_S_spi_40003800_P_status_LEN 1 #define DT_N_S_soc_S_spi_40003800_P_status_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_compatible {"st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"} +#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0 "st,stm32h7-spi" #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-spi #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_spi #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_SPI -#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1 "st,stm32-spi-fifo" #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi-fifo #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi_fifo #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO -#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_2 "st,stm32-spi" #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_2_STRING_UNQUOTED st,stm32-spi #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_2_STRING_TOKEN st_stm32_spi #define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_2_STRING_UPPER_TOKEN ST_STM32_SPI -#define DT_N_S_soc_S_spi_40003800_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003800, compatible, 0) \ fn(DT_N_S_soc_S_spi_40003800, compatible, 1) \ fn(DT_N_S_soc_S_spi_40003800, compatible, 2) @@ -21233,18 +21995,6 @@ fn(DT_N_S_soc_S_spi_40003800, compatible, 2, __VA_ARGS__) #define DT_N_S_soc_S_spi_40003800_P_compatible_LEN 3 #define DT_N_S_soc_S_spi_40003800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_reg {1073756160 /* 0x40003800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0 1073756160 -#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_spi_40003800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_interrupts {36 /* 0x24 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0 36 -#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_spi_40003800_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_spi_40003800_P_clocks_IDX_0_VAL_bus 232 @@ -21269,12 +22019,10 @@ #define DT_N_S_soc_S_spi_40003800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_spi_40003800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spi_40003800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_midi_clock 0 -#define DT_N_S_soc_S_spi_40003800_P_midi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_mssi_clock 0 -#define DT_N_S_soc_S_spi_40003800_P_mssi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40003800_P_fifo_enable 0 -#define DT_N_S_soc_S_spi_40003800_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_wakeup_source 0 +#define DT_N_S_soc_S_spi_40003800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_spi_40003800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/spi@40003c00 @@ -21293,6 +22041,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_spi_40003c00_FULL_NAME "spi@40003c00" +#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_UNQUOTED spi@40003c00 +#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_TOKEN spi_40003c00 +#define DT_N_S_soc_S_spi_40003c00_FULL_NAME_UPPER_TOKEN SPI_40003C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spi_40003c00_PARENT DT_N_S_soc @@ -21318,14 +22069,14 @@ #define DT_N_S_soc_S_spi_40003c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40003c00_ORD 140 -#define DT_N_S_soc_S_spi_40003c00_ORD_STR_SORTABLE 00140 +#define DT_N_S_soc_S_spi_40003c00_ORD 143 +#define DT_N_S_soc_S_spi_40003c00_ORD_STR_SORTABLE 00143 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40003c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40003c00_SUPPORTS_ORDS /* nothing */ @@ -21340,8 +22091,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spi_40003c00_REG_NUM 1 #define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 /* 0x40003c00 */ -#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_ADDRESS 1073757184 +#define DT_N_S_soc_S_spi_40003c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_spi_40003c00_RANGES_NUM 0 #define DT_N_S_soc_S_spi_40003c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spi_40003c00_IRQ_NUM 1 @@ -21374,20 +22125,32 @@ #define DT_N_S_soc_S_spi_40003c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source 0 -#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_midi_clock 0 +#define DT_N_S_soc_S_spi_40003c00_P_midi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_mssi_clock 0 +#define DT_N_S_soc_S_spi_40003c00_P_mssi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_fifo_enable 0 +#define DT_N_S_soc_S_spi_40003c00_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_reg {1073757184, 1024} +#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0 1073757184 +#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_spi_40003c00_P_reg_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_interrupts {51, 0} +#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0 51 +#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_spi_40003c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_status "disabled" #define DT_N_S_soc_S_spi_40003c00_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_spi_40003c00_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_spi_40003c00_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_spi_40003c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_spi_40003c00_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_spi_40003c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, status, 0) #define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40003c00, status, 0) #define DT_N_S_soc_S_spi_40003c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40003c00, status, 0, __VA_ARGS__) @@ -21395,21 +22158,21 @@ #define DT_N_S_soc_S_spi_40003c00_P_status_LEN 1 #define DT_N_S_soc_S_spi_40003c00_P_status_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_compatible {"st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"} +#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0 "st,stm32h7-spi" #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-spi #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_spi #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_SPI -#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1 "st,stm32-spi-fifo" #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi-fifo #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi_fifo #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO -#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_2 "st,stm32-spi" #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_2_STRING_UNQUOTED st,stm32-spi #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_2_STRING_TOKEN st_stm32_spi #define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_2_STRING_UPPER_TOKEN ST_STM32_SPI -#define DT_N_S_soc_S_spi_40003c00_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40003c00, compatible, 0) \ fn(DT_N_S_soc_S_spi_40003c00, compatible, 1) \ fn(DT_N_S_soc_S_spi_40003c00, compatible, 2) @@ -21424,18 +22187,6 @@ fn(DT_N_S_soc_S_spi_40003c00, compatible, 2, __VA_ARGS__) #define DT_N_S_soc_S_spi_40003c00_P_compatible_LEN 3 #define DT_N_S_soc_S_spi_40003c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_reg {1073757184 /* 0x40003c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0 1073757184 -#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_spi_40003c00_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_interrupts {51 /* 0x33 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0 51 -#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_spi_40003c00_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_spi_40003c00_P_clocks_IDX_0_VAL_bus 232 @@ -21460,12 +22211,10 @@ #define DT_N_S_soc_S_spi_40003c00_P_clocks_EXISTS 1 #define DT_N_S_soc_S_spi_40003c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spi_40003c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_midi_clock 0 -#define DT_N_S_soc_S_spi_40003c00_P_midi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_mssi_clock 0 -#define DT_N_S_soc_S_spi_40003c00_P_mssi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40003c00_P_fifo_enable 0 -#define DT_N_S_soc_S_spi_40003c00_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source 0 +#define DT_N_S_soc_S_spi_40003c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_spi_40003c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/spi@40013400 @@ -21484,6 +22233,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_spi_40013400_FULL_NAME "spi@40013400" +#define DT_N_S_soc_S_spi_40013400_FULL_NAME_UNQUOTED spi@40013400 +#define DT_N_S_soc_S_spi_40013400_FULL_NAME_TOKEN spi_40013400 +#define DT_N_S_soc_S_spi_40013400_FULL_NAME_UPPER_TOKEN SPI_40013400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spi_40013400_PARENT DT_N_S_soc @@ -21509,14 +22261,14 @@ #define DT_N_S_soc_S_spi_40013400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_40013400_ORD 141 -#define DT_N_S_soc_S_spi_40013400_ORD_STR_SORTABLE 00141 +#define DT_N_S_soc_S_spi_40013400_ORD 144 +#define DT_N_S_soc_S_spi_40013400_ORD_STR_SORTABLE 00144 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_40013400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_40013400_SUPPORTS_ORDS /* nothing */ @@ -21531,8 +22283,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spi_40013400_REG_NUM 1 #define DT_N_S_soc_S_spi_40013400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_VAL_ADDRESS 1073820672 /* 0x40013400 */ -#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_VAL_ADDRESS 1073820672 +#define DT_N_S_soc_S_spi_40013400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_spi_40013400_RANGES_NUM 0 #define DT_N_S_soc_S_spi_40013400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spi_40013400_IRQ_NUM 1 @@ -21565,20 +22317,32 @@ #define DT_N_S_soc_S_spi_40013400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_spi_40013400_P_wakeup_source 0 -#define DT_N_S_soc_S_spi_40013400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_spi_40013400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_midi_clock 0 +#define DT_N_S_soc_S_spi_40013400_P_midi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_mssi_clock 0 +#define DT_N_S_soc_S_spi_40013400_P_mssi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_fifo_enable 0 +#define DT_N_S_soc_S_spi_40013400_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_reg {1073820672, 1024} +#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_0 1073820672 +#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_spi_40013400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_interrupts {84, 0} +#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_0 84 +#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_spi_40013400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_status "disabled" #define DT_N_S_soc_S_spi_40013400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_spi_40013400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_spi_40013400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_spi_40013400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_spi_40013400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_spi_40013400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_spi_40013400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_spi_40013400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_spi_40013400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013400, status, 0) #define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_40013400, status, 0) #define DT_N_S_soc_S_spi_40013400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_40013400, status, 0, __VA_ARGS__) @@ -21586,21 +22350,21 @@ #define DT_N_S_soc_S_spi_40013400_P_status_LEN 1 #define DT_N_S_soc_S_spi_40013400_P_status_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_compatible {"st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"} +#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0 "st,stm32h7-spi" #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-spi #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_spi #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_SPI -#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_1 "st,stm32-spi-fifo" #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi-fifo #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi_fifo #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO -#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_2 "st,stm32-spi" #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_2_STRING_UNQUOTED st,stm32-spi #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_2_STRING_TOKEN st_stm32_spi #define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_2_STRING_UPPER_TOKEN ST_STM32_SPI -#define DT_N_S_soc_S_spi_40013400_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_40013400, compatible, 0) \ fn(DT_N_S_soc_S_spi_40013400, compatible, 1) \ fn(DT_N_S_soc_S_spi_40013400, compatible, 2) @@ -21615,18 +22379,6 @@ fn(DT_N_S_soc_S_spi_40013400, compatible, 2, __VA_ARGS__) #define DT_N_S_soc_S_spi_40013400_P_compatible_LEN 3 #define DT_N_S_soc_S_spi_40013400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_reg {1073820672 /* 0x40013400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_0 1073820672 -#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_spi_40013400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_interrupts {84 /* 0x54 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_0 84 -#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_spi_40013400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_spi_40013400_P_clocks_IDX_0_VAL_bus 240 @@ -21641,12 +22393,10 @@ #define DT_N_S_soc_S_spi_40013400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_spi_40013400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spi_40013400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_midi_clock 0 -#define DT_N_S_soc_S_spi_40013400_P_midi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_mssi_clock 0 -#define DT_N_S_soc_S_spi_40013400_P_mssi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_40013400_P_fifo_enable 0 -#define DT_N_S_soc_S_spi_40013400_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_wakeup_source 0 +#define DT_N_S_soc_S_spi_40013400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_spi_40013400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_spi_40013400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/spi@58001400 @@ -21665,6 +22415,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_spi_58001400_FULL_NAME "spi@58001400" +#define DT_N_S_soc_S_spi_58001400_FULL_NAME_UNQUOTED spi@58001400 +#define DT_N_S_soc_S_spi_58001400_FULL_NAME_TOKEN spi_58001400 +#define DT_N_S_soc_S_spi_58001400_FULL_NAME_UPPER_TOKEN SPI_58001400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_spi_58001400_PARENT DT_N_S_soc @@ -21690,14 +22443,14 @@ #define DT_N_S_soc_S_spi_58001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_spi_58001400_ORD 142 -#define DT_N_S_soc_S_spi_58001400_ORD_STR_SORTABLE 00142 +#define DT_N_S_soc_S_spi_58001400_ORD 145 +#define DT_N_S_soc_S_spi_58001400_ORD_STR_SORTABLE 00145 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_spi_58001400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_spi_58001400_SUPPORTS_ORDS /* nothing */ @@ -21712,8 +22465,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_spi_58001400_REG_NUM 1 #define DT_N_S_soc_S_spi_58001400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_REG_IDX_0_VAL_ADDRESS 1476400128 /* 0x58001400 */ -#define DT_N_S_soc_S_spi_58001400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_spi_58001400_REG_IDX_0_VAL_ADDRESS 1476400128 +#define DT_N_S_soc_S_spi_58001400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_spi_58001400_RANGES_NUM 0 #define DT_N_S_soc_S_spi_58001400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_spi_58001400_IRQ_NUM 1 @@ -21746,20 +22499,32 @@ #define DT_N_S_soc_S_spi_58001400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_spi_58001400_P_wakeup_source 0 -#define DT_N_S_soc_S_spi_58001400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_spi_58001400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_midi_clock 0 +#define DT_N_S_soc_S_spi_58001400_P_midi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_mssi_clock 0 +#define DT_N_S_soc_S_spi_58001400_P_mssi_clock_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_fifo_enable 0 +#define DT_N_S_soc_S_spi_58001400_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_reg {1476400128, 1024} +#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_0 1476400128 +#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_spi_58001400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_interrupts {86, 0} +#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_0 86 +#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_spi_58001400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_status "disabled" #define DT_N_S_soc_S_spi_58001400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_spi_58001400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_spi_58001400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_spi_58001400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_spi_58001400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_spi_58001400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_spi_58001400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_spi_58001400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_spi_58001400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_58001400, status, 0) #define DT_N_S_soc_S_spi_58001400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_spi_58001400, status, 0) #define DT_N_S_soc_S_spi_58001400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_spi_58001400, status, 0, __VA_ARGS__) @@ -21767,21 +22532,21 @@ #define DT_N_S_soc_S_spi_58001400_P_status_LEN 1 #define DT_N_S_soc_S_spi_58001400_P_status_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_compatible {"st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"} +#define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_0 "st,stm32h7-spi" #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-spi #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_spi #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_SPI -#define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_1 "st,stm32-spi-fifo" #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-spi-fifo #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_1_STRING_TOKEN st_stm32_spi_fifo #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_SPI_FIFO -#define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_2 "st,stm32-spi" #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_2_STRING_UNQUOTED st,stm32-spi #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_2_STRING_TOKEN st_stm32_spi #define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_2_STRING_UPPER_TOKEN ST_STM32_SPI -#define DT_N_S_soc_S_spi_58001400_P_compatible_IDX_2_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_spi_58001400, compatible, 0) \ fn(DT_N_S_soc_S_spi_58001400, compatible, 1) \ fn(DT_N_S_soc_S_spi_58001400, compatible, 2) @@ -21796,18 +22561,6 @@ fn(DT_N_S_soc_S_spi_58001400, compatible, 2, __VA_ARGS__) #define DT_N_S_soc_S_spi_58001400_P_compatible_LEN 3 #define DT_N_S_soc_S_spi_58001400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_reg {1476400128 /* 0x58001400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_0 1476400128 -#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_spi_58001400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_interrupts {86 /* 0x56 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_0 86 -#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_spi_58001400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_spi_58001400_P_clocks_IDX_0_VAL_bus 244 @@ -21822,12 +22575,10 @@ #define DT_N_S_soc_S_spi_58001400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_spi_58001400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_spi_58001400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_midi_clock 0 -#define DT_N_S_soc_S_spi_58001400_P_midi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_mssi_clock 0 -#define DT_N_S_soc_S_spi_58001400_P_mssi_clock_EXISTS 1 -#define DT_N_S_soc_S_spi_58001400_P_fifo_enable 0 -#define DT_N_S_soc_S_spi_58001400_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_wakeup_source 0 +#define DT_N_S_soc_S_spi_58001400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_spi_58001400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_spi_58001400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timer@e000e010 @@ -21846,6 +22597,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timer_e000e010_FULL_NAME "timer@e000e010" +#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UNQUOTED timer@e000e010 +#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_TOKEN timer_e000e010 +#define DT_N_S_soc_S_timer_e000e010_FULL_NAME_UPPER_TOKEN TIMER_E000E010 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timer_e000e010_PARENT DT_N_S_soc @@ -21871,12 +22625,12 @@ #define DT_N_S_soc_S_timer_e000e010_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timer_e000e010_ORD 143 -#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00143 +#define DT_N_S_soc_S_timer_e000e010_ORD 146 +#define DT_N_S_soc_S_timer_e000e010_ORD_STR_SORTABLE 00146 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timer_e000e010_REQUIRES_ORDS \ - 4, /* /soc */ + 4, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timer_e000e010_SUPPORTS_ORDS /* nothing */ @@ -21889,8 +22643,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timer_e000e010_REG_NUM 1 #define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 /* 0xe000e010 */ -#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 /* 0x10 */ +#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_ADDRESS 3758153744 +#define DT_N_S_soc_S_timer_e000e010_REG_IDX_0_VAL_SIZE 16 #define DT_N_S_soc_S_timer_e000e010_RANGES_NUM 0 #define DT_N_S_soc_S_timer_e000e010_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timer_e000e010_IRQ_NUM 0 @@ -21906,30 +22660,30 @@ #define DT_N_S_soc_S_timer_e000e010_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0 -#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744, 16} +#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744 +#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16 +#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible {"arm,armv7m-systick"} +#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0 "arm,armv7m-systick" #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UNQUOTED arm,armv7m-systick #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_TOKEN arm_armv7m_systick #define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_STRING_UPPER_TOKEN ARM_ARMV7M_SYSTICK -#define DT_N_S_soc_S_timer_e000e010_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timer_e000e010, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timer_e000e010_P_compatible_LEN 1 #define DT_N_S_soc_S_timer_e000e010_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timer_e000e010_P_reg {3758153744 /* 0xe000e010 */, 16 /* 0x10 */} -#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0 3758153744 -#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1 16 -#define DT_N_S_soc_S_timer_e000e010_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timer_e000e010_P_reg_EXISTS 1 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timer_e000e010_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source 0 +#define DT_N_S_soc_S_timer_e000e010_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timer_e000e010_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40002400 @@ -21948,6 +22702,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40002400_FULL_NAME "timers@40002400" +#define DT_N_S_soc_S_timers_40002400_FULL_NAME_UNQUOTED timers@40002400 +#define DT_N_S_soc_S_timers_40002400_FULL_NAME_TOKEN timers_40002400 +#define DT_N_S_soc_S_timers_40002400_FULL_NAME_UPPER_TOKEN TIMERS_40002400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40002400_PARENT DT_N_S_soc @@ -21973,14 +22730,14 @@ #define DT_N_S_soc_S_timers_40002400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002400_ORD 144 -#define DT_N_S_soc_S_timers_40002400_ORD_STR_SORTABLE 00144 +#define DT_N_S_soc_S_timers_40002400_ORD 147 +#define DT_N_S_soc_S_timers_40002400_ORD_STR_SORTABLE 00147 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002400_SUPPORTS_ORDS /* nothing */ @@ -21993,8 +22750,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40002400_REG_NUM 1 #define DT_N_S_soc_S_timers_40002400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_REG_IDX_0_VAL_ADDRESS 1073751040 /* 0x40002400 */ -#define DT_N_S_soc_S_timers_40002400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40002400_REG_IDX_0_VAL_ADDRESS 1073751040 +#define DT_N_S_soc_S_timers_40002400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40002400_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40002400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40002400_IRQ_NUM 1 @@ -22022,20 +22779,37 @@ #define DT_N_S_soc_S_timers_40002400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40002400_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40002400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40002400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_st_prescaler 1 +#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_IDX_0_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_reg {1073751040, 1024} +#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_0 1073751040 +#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40002400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bits 512 +#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002400, clocks, 0) +#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002400, clocks, 0) +#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40002400_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40002400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_status "disabled" #define DT_N_S_soc_S_timers_40002400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40002400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40002400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40002400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40002400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40002400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40002400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40002400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40002400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002400, status, 0) #define DT_N_S_soc_S_timers_40002400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002400, status, 0) #define DT_N_S_soc_S_timers_40002400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002400, status, 0, __VA_ARGS__) @@ -22043,59 +22817,41 @@ #define DT_N_S_soc_S_timers_40002400_P_status_LEN 1 #define DT_N_S_soc_S_timers_40002400_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_compatible {"st,stm32-lptim"} +#define DT_N_S_soc_S_timers_40002400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_compatible_IDX_0 "st,stm32-lptim" #define DT_N_S_soc_S_timers_40002400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-lptim #define DT_N_S_soc_S_timers_40002400_P_compatible_IDX_0_STRING_TOKEN st_stm32_lptim #define DT_N_S_soc_S_timers_40002400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_LPTIM -#define DT_N_S_soc_S_timers_40002400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002400, compatible, 0) #define DT_N_S_soc_S_timers_40002400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002400, compatible, 0) #define DT_N_S_soc_S_timers_40002400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002400_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40002400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_reg {1073751040 /* 0x40002400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_0 1073751040 -#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40002400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_interrupts {93 /* 0x5d */, 1 /* 0x1 */} -#define DT_N_S_soc_S_timers_40002400_P_interrupts_IDX_0 93 +#define DT_N_S_soc_S_timers_40002400_P_interrupts {93, 1} #define DT_N_S_soc_S_timers_40002400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_interrupts_IDX_1 1 +#define DT_N_S_soc_S_timers_40002400_P_interrupts_IDX_0 93 #define DT_N_S_soc_S_timers_40002400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_interrupts_IDX_1 1 #define DT_N_S_soc_S_timers_40002400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_interrupt_names {"wakeup"} +#define DT_N_S_soc_S_timers_40002400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_IDX_0 "wakeup" #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_IDX_0_STRING_UNQUOTED wakeup #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_IDX_0_STRING_TOKEN wakeup #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN WAKEUP -#define DT_N_S_soc_S_timers_40002400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40002400_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bits 512 -#define DT_N_S_soc_S_timers_40002400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002400, clocks, 0) -#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002400, clocks, 0) -#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40002400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40002400_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40002400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40002400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40002400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_st_prescaler 1 -#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_ENUM_IDX 0 -#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_ENUM_VAL_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40002400_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40002400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40002400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40002400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/usb@40040000 @@ -22114,6 +22870,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_usb_40040000_FULL_NAME "usb@40040000" +#define DT_N_S_soc_S_usb_40040000_FULL_NAME_UNQUOTED usb@40040000 +#define DT_N_S_soc_S_usb_40040000_FULL_NAME_TOKEN usb_40040000 +#define DT_N_S_soc_S_usb_40040000_FULL_NAME_UPPER_TOKEN USB_40040000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_usb_40040000_PARENT DT_N_S_soc @@ -22139,15 +22898,15 @@ #define DT_N_S_soc_S_usb_40040000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_usb_40040000_ORD 145 -#define DT_N_S_soc_S_usb_40040000_ORD_STR_SORTABLE 00145 +#define DT_N_S_soc_S_usb_40040000_ORD 148 +#define DT_N_S_soc_S_usb_40040000_ORD_STR_SORTABLE 00148 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_usb_40040000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 88, /* /otghs_fs_phy */ + 4, \ + 5, \ + 9, \ + 88, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_usb_40040000_SUPPORTS_ORDS /* nothing */ @@ -22160,8 +22919,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_usb_40040000_REG_NUM 1 #define DT_N_S_soc_S_usb_40040000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_VAL_ADDRESS 1074003968 /* 0x40040000 */ -#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ +#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_VAL_ADDRESS 1074003968 +#define DT_N_S_soc_S_usb_40040000_REG_IDX_0_VAL_SIZE 262144 #define DT_N_S_soc_S_usb_40040000_RANGES_NUM 0 #define DT_N_S_soc_S_usb_40040000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_usb_40040000_IRQ_NUM 4 @@ -22225,101 +22984,42 @@ #define DT_N_S_soc_S_usb_40040000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_usb_40040000_P_wakeup_source 0 -#define DT_N_S_soc_S_usb_40040000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_usb_40040000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_status "disabled" -#define DT_N_S_soc_S_usb_40040000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_usb_40040000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_usb_40040000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_usb_40040000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_usb_40040000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, status, 0) -#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, status, 0) -#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_status_LEN 1 -#define DT_N_S_soc_S_usb_40040000_P_status_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_compatible {"st,stm32-otghs"} -#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0 "st,stm32-otghs" -#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-otghs -#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_TOKEN st_stm32_otghs -#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_OTGHS -#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, compatible, 0) -#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, compatible, 0) -#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_compatible_LEN 1 -#define DT_N_S_soc_S_usb_40040000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_reg {1074003968 /* 0x40040000 */, 262144 /* 0x40000 */} -#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_0 1074003968 +#define DT_N_S_soc_S_usb_40040000_P_reg {1074003968, 262144} #define DT_N_S_soc_S_usb_40040000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_1 262144 +#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_0 1074003968 #define DT_N_S_soc_S_usb_40040000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_reg_IDX_1 262144 #define DT_N_S_soc_S_usb_40040000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts {74 /* 0x4a */, 0 /* 0x0 */, 75 /* 0x4b */, 0 /* 0x0 */, 76 /* 0x4c */, 0 /* 0x0 */, 77 /* 0x4d */, 0 /* 0x0 */} -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_0 74 +#define DT_N_S_soc_S_usb_40040000_P_interrupts {74, 0, 75, 0, 76, 0, 77, 0} #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_0 74 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_2 75 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_2 75 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_4 76 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_3 0 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_4 76 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_6 77 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_5 0 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_6 77 #define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_interrupts_IDX_7 0 #define DT_N_S_soc_S_usb_40040000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names {"ep1_out", "ep1_in", "wkup", "otghs"} -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0 "ep1_out" -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_UNQUOTED ep1_out -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_TOKEN ep1_out -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EP1_OUT -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1 "ep1_in" -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_UNQUOTED ep1_in -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_TOKEN ep1_in -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN EP1_IN -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2 "wkup" -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_UNQUOTED wkup -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_TOKEN wkup -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN WKUP -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3 "otghs" -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_STRING_UNQUOTED otghs -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_STRING_TOKEN otghs -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN OTGHS -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0) \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1) \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2) \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3) -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3) -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0, __VA_ARGS__) \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1, __VA_ARGS__) \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2, __VA_ARGS__) \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ - fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_LEN 4 -#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_ram_size 4096 +#define DT_N_S_soc_S_usb_40040000_P_ram_size_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_phys DT_N_S_otghs_fs_phy +#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0 DT_N_S_otghs_fs_phy +#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0_PH DT_N_S_otghs_fs_phy +#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, phys, 0) +#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, phys, 0) +#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, phys, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, phys, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_phys_LEN 1 +#define DT_N_S_soc_S_usb_40040000_P_phys_EXISTS 1 #define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_usb_40040000_P_clocks_IDX_0_VAL_bus 216 @@ -22342,38 +23042,93 @@ fn(DT_N_S_soc_S_usb_40040000, clocks, 1, __VA_ARGS__) #define DT_N_S_soc_S_usb_40040000_P_clocks_LEN 2 #define DT_N_S_soc_S_usb_40040000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_usb_40040000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_num_bidir_endpoints 9 +#define DT_N_S_soc_S_usb_40040000_P_num_bidir_endpoints_EXISTS 1 #define DT_N_S_soc_S_usb_40040000_P_maximum_speed "full-speed" #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_STRING_UNQUOTED full-speed #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_STRING_TOKEN full_speed #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_STRING_UPPER_TOKEN FULL_SPEED #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0 "full-speed" #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_ENUM_IDX 1 -#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_ENUM_VAL_full_speed_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_ENUM_TOKEN full_speed -#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_ENUM_UPPER_TOKEN FULL_SPEED +#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_usb_40040000_P_maximum_speed_IDX_0_ENUM_VAL_full_speed_EXISTS 1 #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0) #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0) #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0, __VA_ARGS__) #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, maximum_speed, 0, __VA_ARGS__) #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_LEN 1 #define DT_N_S_soc_S_usb_40040000_P_maximum_speed_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_num_bidir_endpoints 9 -#define DT_N_S_soc_S_usb_40040000_P_num_bidir_endpoints_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_ram_size 4096 -#define DT_N_S_soc_S_usb_40040000_P_ram_size_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_phys DT_N_S_otghs_fs_phy -#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0 DT_N_S_otghs_fs_phy -#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0_PH DT_N_S_otghs_fs_phy -#define DT_N_S_soc_S_usb_40040000_P_phys_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, phys, 0) -#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, phys, 0) -#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, phys, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_phys_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, phys, 0, __VA_ARGS__) -#define DT_N_S_soc_S_usb_40040000_P_phys_LEN 1 -#define DT_N_S_soc_S_usb_40040000_P_phys_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_status "disabled" +#define DT_N_S_soc_S_usb_40040000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_usb_40040000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_usb_40040000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_usb_40040000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, status, 0) +#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, status, 0) +#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_status_LEN 1 +#define DT_N_S_soc_S_usb_40040000_P_status_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_compatible {"st,stm32-otghs"} +#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0 "st,stm32-otghs" +#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-otghs +#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_TOKEN st_stm32_otghs +#define DT_N_S_soc_S_usb_40040000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_OTGHS +#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, compatible, 0) +#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, compatible, 0) +#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_compatible_LEN 1 +#define DT_N_S_soc_S_usb_40040000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names {"ep1_out", "ep1_in", "wkup", "otghs"} +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0 "ep1_out" +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_UNQUOTED ep1_out +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_TOKEN ep1_out +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN EP1_OUT +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1 "ep1_in" +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_UNQUOTED ep1_in +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_TOKEN ep1_in +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN EP1_IN +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2 "wkup" +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_UNQUOTED wkup +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_TOKEN wkup +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN WKUP +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3 "otghs" +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_STRING_UNQUOTED otghs +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_STRING_TOKEN otghs +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN OTGHS +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0) \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1) \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2) \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3) +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3) +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1, __VA_ARGS__) \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2, __VA_ARGS__) \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 1, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 2, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_usb_40040000, interrupt_names, 3, __VA_ARGS__) +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_LEN 4 +#define DT_N_S_soc_S_usb_40040000_P_interrupt_names_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_usb_40040000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_wakeup_source 0 +#define DT_N_S_soc_S_usb_40040000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_usb_40040000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_usb_40040000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/watchdog@50003000 @@ -22392,6 +23147,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_watchdog_50003000_FULL_NAME "watchdog@50003000" +#define DT_N_S_soc_S_watchdog_50003000_FULL_NAME_UNQUOTED watchdog@50003000 +#define DT_N_S_soc_S_watchdog_50003000_FULL_NAME_TOKEN watchdog_50003000 +#define DT_N_S_soc_S_watchdog_50003000_FULL_NAME_UPPER_TOKEN WATCHDOG_50003000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_watchdog_50003000_PARENT DT_N_S_soc @@ -22417,14 +23175,14 @@ #define DT_N_S_soc_S_watchdog_50003000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_watchdog_50003000_ORD 146 -#define DT_N_S_soc_S_watchdog_50003000_ORD_STR_SORTABLE 00146 +#define DT_N_S_soc_S_watchdog_50003000_ORD 149 +#define DT_N_S_soc_S_watchdog_50003000_ORD_STR_SORTABLE 00149 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_watchdog_50003000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_watchdog_50003000_SUPPORTS_ORDS /* nothing */ @@ -22438,8 +23196,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_watchdog_50003000_REG_NUM 1 #define DT_N_S_soc_S_watchdog_50003000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 /* 0x50003000 */ -#define DT_N_S_soc_S_watchdog_50003000_REG_IDX_0_VAL_SIZE 4096 /* 0x1000 */ +#define DT_N_S_soc_S_watchdog_50003000_REG_IDX_0_VAL_ADDRESS 1342189568 +#define DT_N_S_soc_S_watchdog_50003000_REG_IDX_0_VAL_SIZE 4096 #define DT_N_S_soc_S_watchdog_50003000_RANGES_NUM 0 #define DT_N_S_soc_S_watchdog_50003000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_watchdog_50003000_IRQ_NUM 1 @@ -22462,20 +23220,32 @@ #define DT_N_S_soc_S_watchdog_50003000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_watchdog_50003000_P_wakeup_source 0 -#define DT_N_S_soc_S_watchdog_50003000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_watchdog_50003000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_reg {1342189568, 4096} +#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_0 1342189568 +#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_1 4096 +#define DT_N_S_soc_S_watchdog_50003000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bus 228 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bits 64 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0) +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0) +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_LEN 1 +#define DT_N_S_soc_S_watchdog_50003000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_watchdog_50003000_P_status "disabled" #define DT_N_S_soc_S_watchdog_50003000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_watchdog_50003000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_watchdog_50003000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_watchdog_50003000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_watchdog_50003000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_watchdog_50003000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_watchdog_50003000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_watchdog_50003000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_watchdog_50003000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_watchdog_50003000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_50003000, status, 0) #define DT_N_S_soc_S_watchdog_50003000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_50003000, status, 0) #define DT_N_S_soc_S_watchdog_50003000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_50003000, status, 0, __VA_ARGS__) @@ -22483,43 +23253,29 @@ #define DT_N_S_soc_S_watchdog_50003000_P_status_LEN 1 #define DT_N_S_soc_S_watchdog_50003000_P_status_EXISTS 1 #define DT_N_S_soc_S_watchdog_50003000_P_compatible {"st,stm32-window-watchdog"} +#define DT_N_S_soc_S_watchdog_50003000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_watchdog_50003000_P_compatible_IDX_0 "st,stm32-window-watchdog" #define DT_N_S_soc_S_watchdog_50003000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-window-watchdog #define DT_N_S_soc_S_watchdog_50003000_P_compatible_IDX_0_STRING_TOKEN st_stm32_window_watchdog #define DT_N_S_soc_S_watchdog_50003000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_WINDOW_WATCHDOG -#define DT_N_S_soc_S_watchdog_50003000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_watchdog_50003000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_50003000, compatible, 0) #define DT_N_S_soc_S_watchdog_50003000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_50003000, compatible, 0) #define DT_N_S_soc_S_watchdog_50003000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_50003000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_watchdog_50003000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_50003000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_watchdog_50003000_P_compatible_LEN 1 #define DT_N_S_soc_S_watchdog_50003000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_reg {1342189568 /* 0x50003000 */, 4096 /* 0x1000 */} -#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_0 1342189568 -#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_1 4096 -#define DT_N_S_soc_S_watchdog_50003000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_interrupts {0 /* 0x0 */, 7 /* 0x7 */} -#define DT_N_S_soc_S_watchdog_50003000_P_interrupts_IDX_0 0 +#define DT_N_S_soc_S_watchdog_50003000_P_interrupts {0, 7} #define DT_N_S_soc_S_watchdog_50003000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_interrupts_IDX_1 7 +#define DT_N_S_soc_S_watchdog_50003000_P_interrupts_IDX_0 0 #define DT_N_S_soc_S_watchdog_50003000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_interrupts_IDX_1 7 #define DT_N_S_soc_S_watchdog_50003000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bus 228 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bits 64 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0) -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0) -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_50003000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_LEN 1 -#define DT_N_S_soc_S_watchdog_50003000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_watchdog_50003000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_watchdog_50003000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_wakeup_source 0 +#define DT_N_S_soc_S_watchdog_50003000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_watchdog_50003000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_watchdog_50003000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/watchdog@58004800 @@ -22538,6 +23294,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_watchdog_58004800_FULL_NAME "watchdog@58004800" +#define DT_N_S_soc_S_watchdog_58004800_FULL_NAME_UNQUOTED watchdog@58004800 +#define DT_N_S_soc_S_watchdog_58004800_FULL_NAME_TOKEN watchdog_58004800 +#define DT_N_S_soc_S_watchdog_58004800_FULL_NAME_UPPER_TOKEN WATCHDOG_58004800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_watchdog_58004800_PARENT DT_N_S_soc @@ -22563,12 +23322,12 @@ #define DT_N_S_soc_S_watchdog_58004800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_watchdog_58004800_ORD 147 -#define DT_N_S_soc_S_watchdog_58004800_ORD_STR_SORTABLE 00147 +#define DT_N_S_soc_S_watchdog_58004800_ORD 150 +#define DT_N_S_soc_S_watchdog_58004800_ORD_STR_SORTABLE 00150 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_watchdog_58004800_REQUIRES_ORDS \ - 4, /* /soc */ + 4, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_watchdog_58004800_SUPPORTS_ORDS /* nothing */ @@ -22582,8 +23341,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_watchdog_58004800_REG_NUM 1 #define DT_N_S_soc_S_watchdog_58004800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_REG_IDX_0_VAL_ADDRESS 1476413440 /* 0x58004800 */ -#define DT_N_S_soc_S_watchdog_58004800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_watchdog_58004800_REG_IDX_0_VAL_ADDRESS 1476413440 +#define DT_N_S_soc_S_watchdog_58004800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_watchdog_58004800_RANGES_NUM 0 #define DT_N_S_soc_S_watchdog_58004800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_watchdog_58004800_IRQ_NUM 0 @@ -22599,20 +23358,20 @@ #define DT_N_S_soc_S_watchdog_58004800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_watchdog_58004800_P_wakeup_source 0 -#define DT_N_S_soc_S_watchdog_58004800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_watchdog_58004800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_watchdog_58004800_P_reg {1476413440, 1024} +#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_0 1476413440 +#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_watchdog_58004800_P_reg_EXISTS 1 #define DT_N_S_soc_S_watchdog_58004800_P_status "disabled" #define DT_N_S_soc_S_watchdog_58004800_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_watchdog_58004800_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_watchdog_58004800_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_watchdog_58004800_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_watchdog_58004800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_watchdog_58004800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_watchdog_58004800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_watchdog_58004800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_watchdog_58004800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_watchdog_58004800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_58004800, status, 0) #define DT_N_S_soc_S_watchdog_58004800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_58004800, status, 0) #define DT_N_S_soc_S_watchdog_58004800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_58004800, status, 0, __VA_ARGS__) @@ -22620,25 +23379,23 @@ #define DT_N_S_soc_S_watchdog_58004800_P_status_LEN 1 #define DT_N_S_soc_S_watchdog_58004800_P_status_EXISTS 1 #define DT_N_S_soc_S_watchdog_58004800_P_compatible {"st,stm32-watchdog"} +#define DT_N_S_soc_S_watchdog_58004800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_watchdog_58004800_P_compatible_IDX_0 "st,stm32-watchdog" #define DT_N_S_soc_S_watchdog_58004800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-watchdog #define DT_N_S_soc_S_watchdog_58004800_P_compatible_IDX_0_STRING_TOKEN st_stm32_watchdog #define DT_N_S_soc_S_watchdog_58004800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_WATCHDOG -#define DT_N_S_soc_S_watchdog_58004800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_watchdog_58004800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_watchdog_58004800, compatible, 0) #define DT_N_S_soc_S_watchdog_58004800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_watchdog_58004800, compatible, 0) #define DT_N_S_soc_S_watchdog_58004800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_watchdog_58004800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_watchdog_58004800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_watchdog_58004800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_watchdog_58004800_P_compatible_LEN 1 #define DT_N_S_soc_S_watchdog_58004800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_P_reg {1476413440 /* 0x58004800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_0 1476413440 -#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_watchdog_58004800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_watchdog_58004800_P_reg_EXISTS 1 #define DT_N_S_soc_S_watchdog_58004800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_watchdog_58004800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_watchdog_58004800_P_wakeup_source 0 +#define DT_N_S_soc_S_watchdog_58004800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_watchdog_58004800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_watchdog_58004800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/adc@40022000/channel@0 @@ -22654,6 +23411,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_0_FULL_NAME "channel@0" +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FULL_NAME_UNQUOTED channel@0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FULL_NAME_TOKEN channel_0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_FULL_NAME_UPPER_TOKEN CHANNEL_0 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_0_PARENT DT_N_S_soc_S_adc_40022000 @@ -22679,12 +23439,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_0_ORD 148 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_ORD_STR_SORTABLE 00148 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_ORD 151 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_ORD_STR_SORTABLE 00151 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_0_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_0_SUPPORTS_ORDS /* nothing */ @@ -22695,7 +23455,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_0_REG_IDX_0_VAL_ADDRESS 0 #define DT_N_S_soc_S_adc_40022000_S_channel_0_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_0_IRQ_NUM 0 @@ -22706,9 +23466,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg {0 /* 0x0 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_IDX_0 0 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg {0} #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -22716,10 +23476,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) @@ -22732,10 +23490,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) @@ -22763,6 +23519,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_1_FULL_NAME "channel@1" +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FULL_NAME_UNQUOTED channel@1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FULL_NAME_TOKEN channel_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_FULL_NAME_UPPER_TOKEN CHANNEL_1 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_1_PARENT DT_N_S_soc_S_adc_40022000 @@ -22788,12 +23547,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_1_ORD 149 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_ORD_STR_SORTABLE 00149 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_ORD 152 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_ORD_STR_SORTABLE 00152 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_1_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_1_SUPPORTS_ORDS /* nothing */ @@ -22804,7 +23563,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_1_REG_IDX_0_VAL_ADDRESS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_1_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_1_IRQ_NUM 0 @@ -22815,9 +23574,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg {1 /* 0x1 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_IDX_0 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg {1} #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_IDX_0 1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -22825,10 +23584,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_gain, 0, __VA_ARGS__) @@ -22841,10 +23598,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, zephyr_reference, 0, __VA_ARGS__) @@ -22872,6 +23627,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_FULL_NAME "channel@4" +#define DT_N_S_soc_S_adc_40022000_S_channel_4_FULL_NAME_UNQUOTED channel@4 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_FULL_NAME_TOKEN channel_4 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_FULL_NAME_UPPER_TOKEN CHANNEL_4 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_PARENT DT_N_S_soc_S_adc_40022000 @@ -22897,12 +23655,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD 150 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD_STR_SORTABLE 00150 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD 153 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_ORD_STR_SORTABLE 00153 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_SUPPORTS_ORDS /* nothing */ @@ -22913,7 +23671,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_4_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_4_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_REG_IDX_0_VAL_ADDRESS 4 /* 0x4 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_4_REG_IDX_0_VAL_ADDRESS 4 #define DT_N_S_soc_S_adc_40022000_S_channel_4_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_4_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_4_IRQ_NUM 0 @@ -22924,9 +23682,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_reg {4 /* 0x4 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_reg_IDX_0 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_reg {4} #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_reg_IDX_0 4 #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -22934,10 +23692,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, zephyr_gain, 0, __VA_ARGS__) @@ -22950,10 +23706,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_4_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, zephyr_reference, 0, __VA_ARGS__) @@ -22981,6 +23735,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_FULL_NAME "channel@5" +#define DT_N_S_soc_S_adc_40022000_S_channel_5_FULL_NAME_UNQUOTED channel@5 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_FULL_NAME_TOKEN channel_5 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_FULL_NAME_UPPER_TOKEN CHANNEL_5 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_PARENT DT_N_S_soc_S_adc_40022000 @@ -23006,12 +23763,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD 151 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD_STR_SORTABLE 00151 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD 154 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_ORD_STR_SORTABLE 00154 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_SUPPORTS_ORDS /* nothing */ @@ -23022,7 +23779,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_5_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_5_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_REG_IDX_0_VAL_ADDRESS 5 /* 0x5 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_5_REG_IDX_0_VAL_ADDRESS 5 #define DT_N_S_soc_S_adc_40022000_S_channel_5_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_5_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_5_IRQ_NUM 0 @@ -23033,9 +23790,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_reg {5 /* 0x5 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_reg_IDX_0 5 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_reg {5} #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_reg_IDX_0 5 #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23043,10 +23800,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, zephyr_gain, 0, __VA_ARGS__) @@ -23059,10 +23814,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_5_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, zephyr_reference, 0, __VA_ARGS__) @@ -23090,6 +23843,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_FULL_NAME "channel@8" +#define DT_N_S_soc_S_adc_40022000_S_channel_8_FULL_NAME_UNQUOTED channel@8 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_FULL_NAME_TOKEN channel_8 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_FULL_NAME_UPPER_TOKEN CHANNEL_8 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_PARENT DT_N_S_soc_S_adc_40022000 @@ -23115,12 +23871,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD 152 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD_STR_SORTABLE 00152 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD 155 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_ORD_STR_SORTABLE 00155 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_SUPPORTS_ORDS /* nothing */ @@ -23131,7 +23887,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_8_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_8_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_REG_IDX_0_VAL_ADDRESS 8 /* 0x8 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_8_REG_IDX_0_VAL_ADDRESS 8 #define DT_N_S_soc_S_adc_40022000_S_channel_8_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_8_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_8_IRQ_NUM 0 @@ -23142,9 +23898,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_reg {8 /* 0x8 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_reg_IDX_0 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_reg {8} #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_reg_IDX_0 8 #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23152,10 +23908,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, zephyr_gain, 0, __VA_ARGS__) @@ -23168,10 +23922,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_8_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, zephyr_reference, 0, __VA_ARGS__) @@ -23199,6 +23951,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_FULL_NAME "channel@9" +#define DT_N_S_soc_S_adc_40022000_S_channel_9_FULL_NAME_UNQUOTED channel@9 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_FULL_NAME_TOKEN channel_9 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_FULL_NAME_UPPER_TOKEN CHANNEL_9 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_PARENT DT_N_S_soc_S_adc_40022000 @@ -23224,12 +23979,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD 153 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD_STR_SORTABLE 00153 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD 156 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_ORD_STR_SORTABLE 00156 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_SUPPORTS_ORDS /* nothing */ @@ -23240,7 +23995,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_9_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_9_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_REG_IDX_0_VAL_ADDRESS 9 /* 0x9 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_9_REG_IDX_0_VAL_ADDRESS 9 #define DT_N_S_soc_S_adc_40022000_S_channel_9_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_9_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_9_IRQ_NUM 0 @@ -23251,9 +24006,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_reg {9 /* 0x9 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_reg_IDX_0 9 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_reg {9} #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_reg_IDX_0 9 #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23261,10 +24016,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, zephyr_gain, 0, __VA_ARGS__) @@ -23277,10 +24030,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_9_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, zephyr_reference, 0, __VA_ARGS__) @@ -23308,6 +24059,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_a_FULL_NAME "channel@a" +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FULL_NAME_UNQUOTED channel@a +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FULL_NAME_TOKEN channel_a +#define DT_N_S_soc_S_adc_40022000_S_channel_a_FULL_NAME_UPPER_TOKEN CHANNEL_A /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_a_PARENT DT_N_S_soc_S_adc_40022000 @@ -23333,12 +24087,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_a_ORD 154 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_ORD_STR_SORTABLE 00154 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_ORD 157 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_ORD_STR_SORTABLE 00157 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_a_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_a_SUPPORTS_ORDS /* nothing */ @@ -23349,7 +24103,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_IDX_0_VAL_ADDRESS 10 /* 0xa */ +#define DT_N_S_soc_S_adc_40022000_S_channel_a_REG_IDX_0_VAL_ADDRESS 10 #define DT_N_S_soc_S_adc_40022000_S_channel_a_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_a_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_a_IRQ_NUM 0 @@ -23360,9 +24114,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_a_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg {10 /* 0xa */} -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_IDX_0 10 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg {10} #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_IDX_0 10 #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23370,10 +24124,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_gain, 0, __VA_ARGS__) @@ -23386,10 +24138,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_a_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, zephyr_reference, 0, __VA_ARGS__) @@ -23417,6 +24167,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_c_FULL_NAME "channel@c" +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FULL_NAME_UNQUOTED channel@c +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FULL_NAME_TOKEN channel_c +#define DT_N_S_soc_S_adc_40022000_S_channel_c_FULL_NAME_UPPER_TOKEN CHANNEL_C /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_c_PARENT DT_N_S_soc_S_adc_40022000 @@ -23442,12 +24195,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_c_ORD 155 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_ORD_STR_SORTABLE 00155 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_ORD 158 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_ORD_STR_SORTABLE 00158 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_c_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_c_SUPPORTS_ORDS /* nothing */ @@ -23458,7 +24211,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_IDX_0_VAL_ADDRESS 12 /* 0xc */ +#define DT_N_S_soc_S_adc_40022000_S_channel_c_REG_IDX_0_VAL_ADDRESS 12 #define DT_N_S_soc_S_adc_40022000_S_channel_c_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_c_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_c_IRQ_NUM 0 @@ -23469,9 +24222,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_c_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg {12 /* 0xc */} -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_IDX_0 12 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg {12} #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_IDX_0 12 #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23479,10 +24232,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_gain, 0, __VA_ARGS__) @@ -23495,10 +24246,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_c_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, zephyr_reference, 0, __VA_ARGS__) @@ -23526,6 +24275,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_d_FULL_NAME "channel@d" +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FULL_NAME_UNQUOTED channel@d +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FULL_NAME_TOKEN channel_d +#define DT_N_S_soc_S_adc_40022000_S_channel_d_FULL_NAME_UPPER_TOKEN CHANNEL_D /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_d_PARENT DT_N_S_soc_S_adc_40022000 @@ -23551,12 +24303,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_d_ORD 156 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_ORD_STR_SORTABLE 00156 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_ORD 159 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_ORD_STR_SORTABLE 00159 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_d_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_d_SUPPORTS_ORDS /* nothing */ @@ -23567,7 +24319,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_IDX_0_VAL_ADDRESS 13 /* 0xd */ +#define DT_N_S_soc_S_adc_40022000_S_channel_d_REG_IDX_0_VAL_ADDRESS 13 #define DT_N_S_soc_S_adc_40022000_S_channel_d_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_d_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_d_IRQ_NUM 0 @@ -23578,9 +24330,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_d_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg {13 /* 0xd */} -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_IDX_0 13 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg {13} #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_IDX_0 13 #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23588,10 +24340,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_gain, 0, __VA_ARGS__) @@ -23604,10 +24354,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_d_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, zephyr_reference, 0, __VA_ARGS__) @@ -23635,6 +24383,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_FULL_NAME "channel@10" +#define DT_N_S_soc_S_adc_40022000_S_channel_10_FULL_NAME_UNQUOTED channel@10 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_FULL_NAME_TOKEN channel_10 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_FULL_NAME_UPPER_TOKEN CHANNEL_10 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_PARENT DT_N_S_soc_S_adc_40022000 @@ -23660,12 +24411,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD 157 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD_STR_SORTABLE 00157 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD 160 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_ORD_STR_SORTABLE 00160 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_SUPPORTS_ORDS /* nothing */ @@ -23676,7 +24427,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_IDX_0_VAL_ADDRESS 16 /* 0x10 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_10_REG_IDX_0_VAL_ADDRESS 16 #define DT_N_S_soc_S_adc_40022000_S_channel_10_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_10_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_10_IRQ_NUM 0 @@ -23687,9 +24438,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg {16 /* 0x10 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_IDX_0 16 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg {16} #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_IDX_0 16 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23697,10 +24448,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, zephyr_gain, 0, __VA_ARGS__) @@ -23713,10 +24462,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_10_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, zephyr_reference, 0, __VA_ARGS__) @@ -23744,6 +24491,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_12_FULL_NAME "channel@12" +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FULL_NAME_UNQUOTED channel@12 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FULL_NAME_TOKEN channel_12 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_FULL_NAME_UPPER_TOKEN CHANNEL_12 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_12_PARENT DT_N_S_soc_S_adc_40022000 @@ -23769,12 +24519,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD 158 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD_STR_SORTABLE 00158 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD 161 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_ORD_STR_SORTABLE 00161 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_12_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_12_SUPPORTS_ORDS /* nothing */ @@ -23785,7 +24535,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_VAL_ADDRESS 18 /* 0x12 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_12_REG_IDX_0_VAL_ADDRESS 18 #define DT_N_S_soc_S_adc_40022000_S_channel_12_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_12_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_12_IRQ_NUM 0 @@ -23796,9 +24546,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_12_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg {18 /* 0x12 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0 18 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg {18} #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_IDX_0 18 #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23806,10 +24556,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_gain, 0, __VA_ARGS__) @@ -23822,10 +24570,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_12_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, zephyr_reference, 0, __VA_ARGS__) @@ -23853,6 +24599,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_40022000_S_channel_13_FULL_NAME "channel@13" +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FULL_NAME_UNQUOTED channel@13 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FULL_NAME_TOKEN channel_13 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_FULL_NAME_UPPER_TOKEN CHANNEL_13 /* Node parent (/soc/adc@40022000) identifier: */ #define DT_N_S_soc_S_adc_40022000_S_channel_13_PARENT DT_N_S_soc_S_adc_40022000 @@ -23878,12 +24627,12 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD 159 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD_STR_SORTABLE 00159 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD 162 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_ORD_STR_SORTABLE 00162 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_40022000_S_channel_13_REQUIRES_ORDS \ - 51, /* /soc/adc@40022000 */ + 51, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_40022000_S_channel_13_SUPPORTS_ORDS /* nothing */ @@ -23894,7 +24643,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_NUM 1 #define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_VAL_ADDRESS 19 /* 0x13 */ +#define DT_N_S_soc_S_adc_40022000_S_channel_13_REG_IDX_0_VAL_ADDRESS 19 #define DT_N_S_soc_S_adc_40022000_S_channel_13_RANGES_NUM 0 #define DT_N_S_soc_S_adc_40022000_S_channel_13_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_40022000_S_channel_13_IRQ_NUM 0 @@ -23905,9 +24654,9 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_13_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg {19 /* 0x13 */} -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0 19 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg {19} #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_IDX_0 19 #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -23915,10 +24664,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_gain, 0, __VA_ARGS__) @@ -23931,10 +24678,8 @@ #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0) #define DT_N_S_soc_S_adc_40022000_S_channel_13_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, zephyr_reference, 0, __VA_ARGS__) @@ -23962,6 +24707,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_58026000_S_channel_0_FULL_NAME "channel@0" +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FULL_NAME_UNQUOTED channel@0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FULL_NAME_TOKEN channel_0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_FULL_NAME_UPPER_TOKEN CHANNEL_0 /* Node parent (/soc/adc@58026000) identifier: */ #define DT_N_S_soc_S_adc_58026000_S_channel_0_PARENT DT_N_S_soc_S_adc_58026000 @@ -23987,12 +24735,12 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_58026000_S_channel_0_ORD 160 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_ORD_STR_SORTABLE 00160 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_ORD 163 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_ORD_STR_SORTABLE 00163 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_58026000_S_channel_0_REQUIRES_ORDS \ - 13, /* /soc/adc@58026000 */ + 13, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_58026000_S_channel_0_SUPPORTS_ORDS /* nothing */ @@ -24003,7 +24751,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_NUM 1 #define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_soc_S_adc_58026000_S_channel_0_REG_IDX_0_VAL_ADDRESS 0 #define DT_N_S_soc_S_adc_58026000_S_channel_0_RANGES_NUM 0 #define DT_N_S_soc_S_adc_58026000_S_channel_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_58026000_S_channel_0_IRQ_NUM 0 @@ -24014,9 +24762,9 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg {0 /* 0x0 */} -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_IDX_0 0 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg {0} #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -24024,10 +24772,8 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_gain, 0, __VA_ARGS__) @@ -24040,10 +24786,8 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_0_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, zephyr_reference, 0, __VA_ARGS__) @@ -24071,6 +24815,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_adc_58026000_S_channel_1_FULL_NAME "channel@1" +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FULL_NAME_UNQUOTED channel@1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FULL_NAME_TOKEN channel_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_FULL_NAME_UPPER_TOKEN CHANNEL_1 /* Node parent (/soc/adc@58026000) identifier: */ #define DT_N_S_soc_S_adc_58026000_S_channel_1_PARENT DT_N_S_soc_S_adc_58026000 @@ -24096,12 +24843,12 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_adc_58026000_S_channel_1_ORD 161 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_ORD_STR_SORTABLE 00161 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_ORD 164 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_ORD_STR_SORTABLE 00164 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_adc_58026000_S_channel_1_REQUIRES_ORDS \ - 13, /* /soc/adc@58026000 */ + 13, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_adc_58026000_S_channel_1_SUPPORTS_ORDS /* nothing */ @@ -24112,7 +24859,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_NUM 1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_IDX_0_VAL_ADDRESS 1 /* 0x1 */ +#define DT_N_S_soc_S_adc_58026000_S_channel_1_REG_IDX_0_VAL_ADDRESS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_RANGES_NUM 0 #define DT_N_S_soc_S_adc_58026000_S_channel_1_FOREACH_RANGE(fn) #define DT_N_S_soc_S_adc_58026000_S_channel_1_IRQ_NUM 0 @@ -24123,9 +24870,9 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg {1 /* 0x1 */} -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_IDX_0 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg {1} #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_IDX_0 1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_reg_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain "ADC_GAIN_1" #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_STRING_UNQUOTED ADC_GAIN_1 @@ -24133,10 +24880,8 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_STRING_UPPER_TOKEN ADC_GAIN_1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_IDX_0 "ADC_GAIN_1" #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_IDX 8 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_VAL_ADC_GAIN_1_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_TOKEN ADC_GAIN_1 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_ENUM_UPPER_TOKEN ADC_GAIN_1 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_IDX_0_ENUM_IDX 8 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_IDX_0_ENUM_VAL_ADC_GAIN_1_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_gain_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_gain, 0, __VA_ARGS__) @@ -24149,10 +24894,8 @@ #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_STRING_UPPER_TOKEN ADC_REF_INTERNAL #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_IDX_0 "ADC_REF_INTERNAL" #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_IDX 4 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_TOKEN ADC_REF_INTERNAL -#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_ENUM_UPPER_TOKEN ADC_REF_INTERNAL +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_IDX_0_ENUM_IDX 4 +#define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_IDX_0_ENUM_VAL_ADC_REF_INTERNAL_EXISTS 1 #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0) #define DT_N_S_soc_S_adc_58026000_S_channel_1_P_zephyr_reference_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, zephyr_reference, 0, __VA_ARGS__) @@ -24183,6 +24926,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dma_40020000_FULL_NAME "dma@40020000" +#define DT_N_S_soc_S_dma_40020000_FULL_NAME_UNQUOTED dma@40020000 +#define DT_N_S_soc_S_dma_40020000_FULL_NAME_TOKEN dma_40020000 +#define DT_N_S_soc_S_dma_40020000_FULL_NAME_UPPER_TOKEN DMA_40020000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dma_40020000_PARENT DT_N_S_soc @@ -24208,18 +24954,18 @@ #define DT_N_S_soc_S_dma_40020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dma_40020000_ORD 162 -#define DT_N_S_soc_S_dma_40020000_ORD_STR_SORTABLE 00162 +#define DT_N_S_soc_S_dma_40020000_ORD 165 +#define DT_N_S_soc_S_dma_40020000_ORD_STR_SORTABLE 00165 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dma_40020000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dma_40020000_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_dma_40020000_EXISTS 1 @@ -24229,8 +24975,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dma_40020000_REG_NUM 1 #define DT_N_S_soc_S_dma_40020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 /* 0x40020000 */ -#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_ADDRESS 1073872896 +#define DT_N_S_soc_S_dma_40020000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_dma_40020000_RANGES_NUM 0 #define DT_N_S_soc_S_dma_40020000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dma_40020000_IRQ_NUM 8 @@ -24302,20 +25048,60 @@ #define DT_N_S_soc_S_dma_40020000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_dma_40020000_P_wakeup_source 0 -#define DT_N_S_soc_S_dma_40020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_reg {1073872896, 1024} +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0 1073872896 +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dma_40020000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts {11, 0, 12, 0, 13, 0, 14, 0, 15, 0, 16, 0, 17, 0, 47, 0} +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0 11 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2 12 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4 13 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6 14 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8 15 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10 16 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12 17 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14 47 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15 0 +#define DT_N_S_soc_S_dma_40020000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem 1 +#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_dma_offset 0 +#define DT_N_S_soc_S_dma_40020000_P_dma_offset_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_dma_requests 8 +#define DT_N_S_soc_S_dma_40020000_P_dma_requests_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_status "okay" #define DT_N_S_soc_S_dma_40020000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_dma_40020000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_dma_40020000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_dma_40020000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_dma_40020000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_dma_40020000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, status, 0) #define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, status, 0) #define DT_N_S_soc_S_dma_40020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, status, 0, __VA_ARGS__) @@ -24323,57 +25109,17 @@ #define DT_N_S_soc_S_dma_40020000_P_status_LEN 1 #define DT_N_S_soc_S_dma_40020000_P_status_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_compatible {"st,stm32-dma-v1"} +#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0 "st,stm32-dma-v1" #define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dma-v1 #define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dma_v1 #define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DMA_V1 -#define DT_N_S_soc_S_dma_40020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dma_40020000, compatible, 0) #define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dma_40020000, compatible, 0) #define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dma_40020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dma_40020000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dma_40020000_P_compatible_LEN 1 #define DT_N_S_soc_S_dma_40020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_reg {1073872896 /* 0x40020000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0 1073872896 -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_dma_40020000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts {11 /* 0xb */, 0 /* 0x0 */, 12 /* 0xc */, 0 /* 0x0 */, 13 /* 0xd */, 0 /* 0x0 */, 14 /* 0xe */, 0 /* 0x0 */, 15 /* 0xf */, 0 /* 0x0 */, 16 /* 0x10 */, 0 /* 0x0 */, 17 /* 0x11 */, 0 /* 0x0 */, 47 /* 0x2f */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0 11 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2 12 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4 13 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6 14 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_7_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8 15 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_8_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_9_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10 16 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_10_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_11_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12 17 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_12_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_13_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14 47 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_14_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15 0 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_IDX_15_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_dma_40020000_P_clocks_IDX_0_VAL_bus 216 @@ -24388,12 +25134,10 @@ #define DT_N_S_soc_S_dma_40020000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_dma_40020000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_dma_requests 8 -#define DT_N_S_soc_S_dma_40020000_P_dma_requests_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem 1 -#define DT_N_S_soc_S_dma_40020000_P_st_mem2mem_EXISTS 1 -#define DT_N_S_soc_S_dma_40020000_P_dma_offset 0 -#define DT_N_S_soc_S_dma_40020000_P_dma_offset_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_wakeup_source 0 +#define DT_N_S_soc_S_dma_40020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dma_40020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/i2c@58001c00/ov7670@21 @@ -24412,6 +25156,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FULL_NAME "ov7670@21" +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FULL_NAME_UNQUOTED ov7670@21 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FULL_NAME_TOKEN ov7670_21 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FULL_NAME_UPPER_TOKEN OV7670_21 /* Node parent (/soc/i2c@58001c00) identifier: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_PARENT DT_N_S_soc_S_i2c_58001c00 @@ -24437,19 +25184,19 @@ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_ORD 163 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_ORD_STR_SORTABLE 00163 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_ORD 166 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_ORD_STR_SORTABLE 00166 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REQUIRES_ORDS \ - 34, /* /soc/i2c@58001c00 */ \ - 75, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 78, /* /soc/pin-controller@58020000/gpio@58020C00 */ + 34, \ + 75, \ + 78, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ \ - 186, /* /soc/i2c@58001c00/ov7670@21/port */ + 178, \ + 189, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_EXISTS 1 @@ -24463,7 +25210,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_NUM 1 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_IDX_0_VAL_ADDRESS 33 /* 0x21 */ +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_REG_IDX_0_VAL_ADDRESS 33 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_RANGES_NUM 0 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_FOREACH_RANGE(fn) #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_IRQ_NUM 0 @@ -24479,28 +25226,6 @@ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_wakeup_source 0 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible {"ovti,ov7670"} -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0 "ovti,ov7670" -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_UNQUOTED ovti,ov7670 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_TOKEN ovti_ov7670 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_UPPER_TOKEN OVTI_OV7670 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0) -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0) -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_LEN 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg {33 /* 0x21 */} -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_IDX_0 33 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_EXISTS 1 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reset_gpios_IDX_0_VAL_pin 4 @@ -24525,6 +25250,28 @@ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, pwdn_gpios, 0, __VA_ARGS__) #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_LEN 1 #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_pwdn_gpios_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg {33} +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_IDX_0 33 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_reg_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible {"ovti,ov7670"} +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0 "ovti,ov7670" +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_UNQUOTED ovti,ov7670 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_TOKEN ovti_ov7670 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_IDX_0_STRING_UPPER_TOKEN OVTI_OV7670 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_LEN 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_wakeup_source 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d0_ph9 @@ -24540,6 +25287,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FULL_NAME "dcmi_d0_ph9" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FULL_NAME_UNQUOTED dcmi_d0_ph9 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FULL_NAME_TOKEN dcmi_d0_ph9 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FULL_NAME_UPPER_TOKEN DCMI_D0_PH9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -24565,16 +25315,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_ORD 164 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_ORD_STR_SORTABLE 00164 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_ORD 167 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_ORD_STR_SORTABLE 00167 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_EXISTS 1 @@ -24592,20 +25342,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_pinmux 3885 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate "very-high-speed" @@ -24614,16 +25350,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d1_ph10 @@ -24639,6 +25387,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FULL_NAME "dcmi_d1_ph10" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FULL_NAME_UNQUOTED dcmi_d1_ph10 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FULL_NAME_TOKEN dcmi_d1_ph10 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FULL_NAME_UPPER_TOKEN DCMI_D1_PH10 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -24664,16 +25415,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_ORD 165 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_ORD_STR_SORTABLE 00165 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_ORD 168 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_ORD_STR_SORTABLE 00168 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_EXISTS 1 @@ -24691,20 +25442,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_pinmux 3917 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate "very-high-speed" @@ -24713,16 +25450,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d2_ph11 @@ -24738,6 +25487,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FULL_NAME "dcmi_d2_ph11" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FULL_NAME_UNQUOTED dcmi_d2_ph11 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FULL_NAME_TOKEN dcmi_d2_ph11 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FULL_NAME_UPPER_TOKEN DCMI_D2_PH11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -24763,16 +25515,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_ORD 166 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_ORD_STR_SORTABLE 00166 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_ORD 169 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_ORD_STR_SORTABLE 00169 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_EXISTS 1 @@ -24790,20 +25542,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_pinmux 3949 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate "very-high-speed" @@ -24812,16 +25550,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d3_pg11 @@ -24837,6 +25587,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FULL_NAME "dcmi_d3_pg11" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FULL_NAME_UNQUOTED dcmi_d3_pg11 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FULL_NAME_TOKEN dcmi_d3_pg11 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FULL_NAME_UPPER_TOKEN DCMI_D3_PG11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -24862,16 +25615,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_ORD 167 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_ORD_STR_SORTABLE 00167 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_ORD 170 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_ORD_STR_SORTABLE 00170 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_EXISTS 1 @@ -24889,20 +25642,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_pinmux 3437 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate "very-high-speed" @@ -24911,16 +25650,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d4_ph14 @@ -24936,6 +25687,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FULL_NAME "dcmi_d4_ph14" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FULL_NAME_UNQUOTED dcmi_d4_ph14 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FULL_NAME_TOKEN dcmi_d4_ph14 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FULL_NAME_UPPER_TOKEN DCMI_D4_PH14 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -24961,16 +25715,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_ORD 168 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_ORD_STR_SORTABLE 00168 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_ORD 171 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_ORD_STR_SORTABLE 00171 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_EXISTS 1 @@ -24988,20 +25742,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_pinmux 4045 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate "very-high-speed" @@ -25010,16 +25750,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d5_pi4 @@ -25035,6 +25787,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FULL_NAME "dcmi_d5_pi4" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FULL_NAME_UNQUOTED dcmi_d5_pi4 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FULL_NAME_TOKEN dcmi_d5_pi4 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FULL_NAME_UPPER_TOKEN DCMI_D5_PI4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -25060,16 +25815,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_ORD 169 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_ORD_STR_SORTABLE 00169 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_ORD 172 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_ORD_STR_SORTABLE 00172 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_EXISTS 1 @@ -25087,20 +25842,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_pinmux 4237 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate "very-high-speed" @@ -25109,16 +25850,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d6_pi6 @@ -25134,6 +25887,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FULL_NAME "dcmi_d6_pi6" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FULL_NAME_UNQUOTED dcmi_d6_pi6 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FULL_NAME_TOKEN dcmi_d6_pi6 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FULL_NAME_UPPER_TOKEN DCMI_D6_PI6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -25159,16 +25915,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_ORD 170 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_ORD_STR_SORTABLE 00170 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_ORD 173 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_ORD_STR_SORTABLE 00173 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_EXISTS 1 @@ -25186,20 +25942,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_pinmux 4301 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate "very-high-speed" @@ -25208,16 +25950,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_d7_pi7 @@ -25233,6 +25987,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FULL_NAME "dcmi_d7_pi7" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FULL_NAME_UNQUOTED dcmi_d7_pi7 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FULL_NAME_TOKEN dcmi_d7_pi7 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FULL_NAME_UPPER_TOKEN DCMI_D7_PI7 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -25258,16 +26015,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_ORD 171 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_ORD_STR_SORTABLE 00171 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_ORD 174 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_ORD_STR_SORTABLE 00174 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_EXISTS 1 @@ -25285,20 +26042,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_pinmux 4333 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate "very-high-speed" @@ -25307,16 +26050,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_hsync_ph8 @@ -25332,6 +26087,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FULL_NAME "dcmi_hsync_ph8" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FULL_NAME_UNQUOTED dcmi_hsync_ph8 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FULL_NAME_TOKEN dcmi_hsync_ph8 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FULL_NAME_UPPER_TOKEN DCMI_HSYNC_PH8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -25357,16 +26115,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_ORD 172 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_ORD_STR_SORTABLE 00172 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_ORD 175 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_ORD_STR_SORTABLE 00175 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_EXISTS 1 @@ -25384,20 +26142,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_pinmux 3853 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate "very-high-speed" @@ -25406,16 +26150,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_pixclk_pa6 @@ -25431,6 +26187,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FULL_NAME "dcmi_pixclk_pa6" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FULL_NAME_UNQUOTED dcmi_pixclk_pa6 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FULL_NAME_TOKEN dcmi_pixclk_pa6 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FULL_NAME_UPPER_TOKEN DCMI_PIXCLK_PA6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -25456,16 +26215,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_ORD 173 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_ORD_STR_SORTABLE 00173 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_ORD 176 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_ORD_STR_SORTABLE 00176 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_EXISTS 1 @@ -25483,20 +26242,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_pinmux 205 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate "very-high-speed" @@ -25505,16 +26250,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/dcmi_vsync_pi5 @@ -25530,6 +26287,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FULL_NAME "dcmi_vsync_pi5" +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FULL_NAME_UNQUOTED dcmi_vsync_pi5 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FULL_NAME_TOKEN dcmi_vsync_pi5 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FULL_NAME_UPPER_TOKEN DCMI_VSYNC_PI5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -25555,16 +26315,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_ORD 174 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_ORD_STR_SORTABLE 00174 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_ORD 177 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_ORD_STR_SORTABLE 00177 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_SUPPORTS_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_EXISTS 1 @@ -25582,20 +26342,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_pinmux 4269 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate "very-high-speed" @@ -25604,16 +26350,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/dcmi@48020000 @@ -25632,6 +26390,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dcmi_48020000_FULL_NAME "dcmi@48020000" +#define DT_N_S_soc_S_dcmi_48020000_FULL_NAME_UNQUOTED dcmi@48020000 +#define DT_N_S_soc_S_dcmi_48020000_FULL_NAME_TOKEN dcmi_48020000 +#define DT_N_S_soc_S_dcmi_48020000_FULL_NAME_UPPER_TOKEN DCMI_48020000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_dcmi_48020000_PARENT DT_N_S_soc @@ -25657,31 +26418,31 @@ #define DT_N_S_soc_S_dcmi_48020000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dcmi_48020000_ORD 175 -#define DT_N_S_soc_S_dcmi_48020000_ORD_STR_SORTABLE 00175 +#define DT_N_S_soc_S_dcmi_48020000_ORD 178 +#define DT_N_S_soc_S_dcmi_48020000_ORD_STR_SORTABLE 00178 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dcmi_48020000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 162, /* /soc/dma@40020000 */ \ - 163, /* /soc/i2c@58001c00/ov7670@21 */ \ - 164, /* /soc/pin-controller@58020000/dcmi_d0_ph9 */ \ - 165, /* /soc/pin-controller@58020000/dcmi_d1_ph10 */ \ - 166, /* /soc/pin-controller@58020000/dcmi_d2_ph11 */ \ - 167, /* /soc/pin-controller@58020000/dcmi_d3_pg11 */ \ - 168, /* /soc/pin-controller@58020000/dcmi_d4_ph14 */ \ - 169, /* /soc/pin-controller@58020000/dcmi_d5_pi4 */ \ - 170, /* /soc/pin-controller@58020000/dcmi_d6_pi6 */ \ - 171, /* /soc/pin-controller@58020000/dcmi_d7_pi7 */ \ - 172, /* /soc/pin-controller@58020000/dcmi_hsync_ph8 */ \ - 173, /* /soc/pin-controller@58020000/dcmi_pixclk_pa6 */ \ - 174, /* /soc/pin-controller@58020000/dcmi_vsync_pi5 */ + 4, \ + 5, \ + 9, \ + 165, \ + 166, \ + 167, \ + 168, \ + 169, \ + 170, \ + 171, \ + 172, \ + 173, \ + 174, \ + 175, \ + 176, \ + 177, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dcmi_48020000_SUPPORTS_ORDS \ - 176, /* /soc/dcmi@48020000/port */ + 179, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_dcmi_48020000_EXISTS 1 @@ -25691,8 +26452,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_dcmi_48020000_REG_NUM 1 #define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_ADDRESS 1208090624 /* 0x48020000 */ -#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_ADDRESS 1208090624 +#define DT_N_S_soc_S_dcmi_48020000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_dcmi_48020000_RANGES_NUM 0 #define DT_N_S_soc_S_dcmi_48020000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_dcmi_48020000_IRQ_NUM 1 @@ -25736,20 +26497,71 @@ #define DT_N_S_soc_S_dcmi_48020000_PINCTRL_NAME_default_IDX_10_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7 /* Generic property macros: */ -#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source 0 -#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts {78, 0} +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0 78 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0 DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0_PH DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_sensor_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width 8 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_IDX_0_ENUM_VAL_8_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active 0 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_IDX_0_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active 0 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_IDX_0_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active 0 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_IDX_0_ENUM_VAL_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_IDX_0_ENUM_VAL_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40020000 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel 0 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_slot 75 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_slot_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_config 148608 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_config_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_features 0 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_features_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0, __VA_ARGS__) +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_LEN 1 +#define DT_N_S_soc_S_dcmi_48020000_P_dmas_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_status "okay" #define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_dcmi_48020000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_dcmi_48020000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_dcmi_48020000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, status, 0) #define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, status, 0) #define DT_N_S_soc_S_dcmi_48020000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, status, 0, __VA_ARGS__) @@ -25757,35 +26569,29 @@ #define DT_N_S_soc_S_dcmi_48020000_P_status_LEN 1 #define DT_N_S_soc_S_dcmi_48020000_P_status_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_compatible {"st,stm32-dcmi"} +#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0 "st,stm32-dcmi" #define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-dcmi #define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_TOKEN st_stm32_dcmi #define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_DCMI -#define DT_N_S_soc_S_dcmi_48020000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0) #define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0) #define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dcmi_48020000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_dcmi_48020000_P_compatible_LEN 1 #define DT_N_S_soc_S_dcmi_48020000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_reg {1208090624 /* 0x48020000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0 1208090624 +#define DT_N_S_soc_S_dcmi_48020000_P_reg {1208090624, 1024} #define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_0 1208090624 #define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_dcmi_48020000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts {78 /* 0x4e */, 0 /* 0x0 */} -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0 78 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names {"dcmi"} +#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0 "dcmi" #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_UNQUOTED dcmi #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_TOKEN dcmi #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN DCMI -#define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0) #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0) #define DT_N_S_soc_S_dcmi_48020000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, interrupt_names, 0, __VA_ARGS__) @@ -25804,24 +26610,12 @@ #define DT_N_S_soc_S_dcmi_48020000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_dcmi_48020000_P_clocks_LEN 1 #define DT_N_S_soc_S_dcmi_48020000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_PH DT_N_S_soc_S_dma_40020000 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel 0 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_slot 75 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_slot_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_config 148608 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_channel_config_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_features 0 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_IDX_0_VAL_features_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, dmas, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_LEN 1 -#define DT_N_S_soc_S_dcmi_48020000_P_dmas_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_dcmi_48020000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source 0 +#define DT_N_S_soc_S_dcmi_48020000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_dcmi_48020000_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_IDX_0_EXISTS 1 @@ -25902,47 +26696,17 @@ #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_LEN 11 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0) #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0) #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_dcmi_48020000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_sensor DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0 DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0_PH DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0) -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000, sensor, 0, __VA_ARGS__) -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_LEN 1 -#define DT_N_S_soc_S_dcmi_48020000_P_sensor_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width 8 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_ENUM_VAL_8_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_bus_width_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active 0 -#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_ENUM_VAL_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_hsync_active_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active 0 -#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_ENUM_VAL_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_vsync_active_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active 0 -#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_ENUM_VAL_0_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_pixelclk_active_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate 1 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_ENUM_VAL_1_EXISTS 1 -#define DT_N_S_soc_S_dcmi_48020000_P_capture_rate_EXISTS 1 /* * Devicetree node: /soc/dcmi@48020000/port @@ -25955,6 +26719,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_FULL_NAME "port" +#define DT_N_S_soc_S_dcmi_48020000_S_port_FULL_NAME_UNQUOTED port +#define DT_N_S_soc_S_dcmi_48020000_S_port_FULL_NAME_TOKEN port +#define DT_N_S_soc_S_dcmi_48020000_S_port_FULL_NAME_UPPER_TOKEN PORT /* Node parent (/soc/dcmi@48020000) identifier: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_PARENT DT_N_S_soc_S_dcmi_48020000 @@ -25980,16 +26747,16 @@ #define DT_N_S_soc_S_dcmi_48020000_S_port_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dcmi_48020000_S_port_ORD 176 -#define DT_N_S_soc_S_dcmi_48020000_S_port_ORD_STR_SORTABLE 00176 +#define DT_N_S_soc_S_dcmi_48020000_S_port_ORD 179 +#define DT_N_S_soc_S_dcmi_48020000_S_port_ORD_STR_SORTABLE 00179 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_REQUIRES_ORDS \ - 175, /* /soc/dcmi@48020000 */ + 178, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_SUPPORTS_ORDS \ - 177, /* /soc/dcmi@48020000/port/endpoint */ + 180, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_EXISTS 1 @@ -26018,6 +26785,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FULL_NAME "endpoint" +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FULL_NAME_UNQUOTED endpoint +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FULL_NAME_TOKEN endpoint +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FULL_NAME_UPPER_TOKEN ENDPOINT /* Node parent (/soc/dcmi@48020000/port) identifier: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_PARENT DT_N_S_soc_S_dcmi_48020000_S_port @@ -26043,12 +26813,12 @@ #define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_ORD 177 -#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_ORD_STR_SORTABLE 00177 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_ORD 180 +#define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_ORD_STR_SORTABLE 00180 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_REQUIRES_ORDS \ - 176, /* /soc/dcmi@48020000/port */ + 179, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint_SUPPORTS_ORDS /* nothing */ @@ -26075,8 +26845,8 @@ * * Node identifier: DT_N_S_soc_S_ethernet_40028000 * - * Binding (compatible = st,stm32-ethernet): - * $ZEPHYR_BASE/dts/bindings/ethernet/st,stm32-ethernet.yaml + * Binding (compatible = st,stm32h7-ethernet): + * $ZEPHYR_BASE/dts/bindings/ethernet/st,stm32h7-ethernet.yaml * * (Descriptions have moved to the Devicetree Bindings Index * in the documentation.) @@ -26087,6 +26857,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_ethernet_40028000_FULL_NAME "ethernet@40028000" +#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME_UNQUOTED ethernet@40028000 +#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME_TOKEN ethernet_40028000 +#define DT_N_S_soc_S_ethernet_40028000_FULL_NAME_UPPER_TOKEN ETHERNET_40028000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_ethernet_40028000_PARENT DT_N_S_soc @@ -26112,29 +26885,30 @@ #define DT_N_S_soc_S_ethernet_40028000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_ethernet_40028000_ORD 178 -#define DT_N_S_soc_S_ethernet_40028000_ORD_STR_SORTABLE 00178 +#define DT_N_S_soc_S_ethernet_40028000_ORD 181 +#define DT_N_S_soc_S_ethernet_40028000_ORD_STR_SORTABLE 00181 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ethernet_40028000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ethernet_40028000_SUPPORTS_ORDS \ - 179, /* /soc/ethernet@40028000/mdio */ + 182, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_ethernet_40028000_EXISTS 1 -#define DT_N_INST_0_st_stm32_ethernet DT_N_S_soc_S_ethernet_40028000 -#define DT_N_NODELABEL_mac DT_N_S_soc_S_ethernet_40028000 +#define DT_N_INST_0_st_stm32h7_ethernet DT_N_S_soc_S_ethernet_40028000 +#define DT_N_INST_0_st_stm32_ethernet DT_N_S_soc_S_ethernet_40028000 +#define DT_N_NODELABEL_mac DT_N_S_soc_S_ethernet_40028000 /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_ethernet_40028000_REG_NUM 1 #define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_VAL_ADDRESS 1073905664 /* 0x40028000 */ -#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_VAL_SIZE 32768 /* 0x8000 */ +#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_VAL_ADDRESS 1073905664 +#define DT_N_S_soc_S_ethernet_40028000_REG_IDX_0_VAL_SIZE 32768 #define DT_N_S_soc_S_ethernet_40028000_RANGES_NUM 0 #define DT_N_S_soc_S_ethernet_40028000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_ethernet_40028000_IRQ_NUM 1 @@ -26146,60 +26920,33 @@ #define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_VAL_priority_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_IRQ_IDX_0_CONTROLLER DT_N_S_soc_S_interrupt_controller_e000e100 #define DT_N_S_soc_S_ethernet_40028000_IRQ_LEVEL 1 -#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MATCHES_st_stm32_ethernet 1 +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MATCHES_st_stm32h7_ethernet 1 #define DT_N_S_soc_S_ethernet_40028000_COMPAT_VENDOR_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_COMPAT_VENDOR_IDX_0 "STMicroelectronics" #define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_0 "stm32-ethernet" +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_0 "stm32h7-ethernet" +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MATCHES_st_stm32_ethernet 1 +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_VENDOR_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_VENDOR_IDX_1 "STMicroelectronics" +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_COMPAT_MODEL_IDX_1 "stm32-ethernet" #define DT_N_S_soc_S_ethernet_40028000_STATUS_disabled 1 /* Pin control (pinctrl-, pinctrl-names) properties: */ #define DT_N_S_soc_S_ethernet_40028000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_ethernet_40028000_P_wakeup_source 0 -#define DT_N_S_soc_S_ethernet_40028000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_status "disabled" -#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_UNQUOTED disabled -#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_TOKEN disabled -#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0 "disabled" -#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_ethernet_40028000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_ethernet_40028000_P_status_ENUM_UPPER_TOKEN DISABLED -#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, status, 0) -#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, status, 0) -#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_ethernet_40028000_P_status_LEN 1 -#define DT_N_S_soc_S_ethernet_40028000_P_status_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_compatible {"st,stm32-ethernet"} -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0 "st,stm32-ethernet" -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-ethernet -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_TOKEN st_stm32_ethernet -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_ETHERNET -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0) -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0) -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_LEN 1 -#define DT_N_S_soc_S_ethernet_40028000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_reg {1073905664 /* 0x40028000 */, 32768 /* 0x8000 */} -#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_0 1073905664 +#define DT_N_S_soc_S_ethernet_40028000_P_reg {1073905664, 32768} #define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_1 32768 +#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_0 1073905664 #define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_reg_IDX_1 32768 #define DT_N_S_soc_S_ethernet_40028000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_interrupts {61 /* 0x3d */, 0 /* 0x0 */} -#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_0 61 +#define DT_N_S_soc_S_ethernet_40028000_P_interrupts {61, 0} #define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_0 61 #define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_ethernet_40028000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -26255,21 +27002,21 @@ #define DT_N_S_soc_S_ethernet_40028000_P_clocks_LEN 3 #define DT_N_S_soc_S_ethernet_40028000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clock_names {"stmmaceth", "mac-clk-tx", "mac-clk-rx"} +#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0 "stmmaceth" #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_STRING_UNQUOTED stmmaceth #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_STRING_TOKEN stmmaceth #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_STRING_UPPER_TOKEN STMMACETH -#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1 "mac-clk-tx" #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_STRING_UNQUOTED mac-clk-tx #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_STRING_TOKEN mac_clk_tx #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_STRING_UPPER_TOKEN MAC_CLK_TX -#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2 "mac-clk-rx" #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_STRING_UNQUOTED mac-clk-rx #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_STRING_TOKEN mac_clk_rx #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_STRING_UPPER_TOKEN MAC_CLK_RX -#define DT_N_S_soc_S_ethernet_40028000_P_clock_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 0) \ fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 1) \ fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 2) @@ -26284,10 +27031,49 @@ fn(DT_N_S_soc_S_ethernet_40028000, clock_names, 2, __VA_ARGS__) #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_LEN 3 #define DT_N_S_soc_S_ethernet_40028000_P_clock_names_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_P_zephyr_random_mac_address 0 #define DT_N_S_soc_S_ethernet_40028000_P_zephyr_random_mac_address_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_status "disabled" +#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_UNQUOTED disabled +#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_TOKEN disabled +#define DT_N_S_soc_S_ethernet_40028000_P_status_STRING_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0 "disabled" +#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_ethernet_40028000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, status, 0) +#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, status, 0) +#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_ethernet_40028000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_ethernet_40028000_P_status_LEN 1 +#define DT_N_S_soc_S_ethernet_40028000_P_status_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_compatible {"st,stm32h7-ethernet", "st,stm32-ethernet"} +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0 "st,stm32h7-ethernet" +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-ethernet +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_ethernet +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_ETHERNET +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_1 "st,stm32-ethernet" +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32-ethernet +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_1_STRING_TOKEN st_stm32_ethernet +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32_ETHERNET +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0) \ + fn(DT_N_S_soc_S_ethernet_40028000, compatible, 1) +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_ethernet_40028000, compatible, 1) +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0, __VA_ARGS__) \ + fn(DT_N_S_soc_S_ethernet_40028000, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_ethernet_40028000, compatible, 0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep \ + fn(DT_N_S_soc_S_ethernet_40028000, compatible, 1, __VA_ARGS__) +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_LEN 2 +#define DT_N_S_soc_S_ethernet_40028000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_wakeup_source 0 +#define DT_N_S_soc_S_ethernet_40028000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_ethernet_40028000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/ethernet@40028000/mdio @@ -26306,6 +27092,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME "mdio" +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME_UNQUOTED mdio +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME_TOKEN mdio +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_FULL_NAME_UPPER_TOKEN MDIO /* Node parent (/soc/ethernet@40028000) identifier: */ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_PARENT DT_N_S_soc_S_ethernet_40028000 @@ -26331,12 +27120,12 @@ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD 179 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD_STR_SORTABLE 00179 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD 182 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_ORD_STR_SORTABLE 00182 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_REQUIRES_ORDS \ - 178, /* /soc/ethernet@40028000 */ + 181, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_SUPPORTS_ORDS /* nothing */ @@ -26363,20 +27152,18 @@ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_wakeup_source 0 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_suppress_preamble 0 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_suppress_preamble_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_clock_frequency 2500000 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_clock_frequency_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status "disabled" #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0) #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0) #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, status, 0, __VA_ARGS__) @@ -26384,11 +27171,11 @@ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_LEN 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_status_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible {"st,stm32-mdio"} +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0 "st,stm32-mdio" #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-mdio #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_STRING_TOKEN st_stm32_mdio #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_MDIO -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0) #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0) #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, compatible, 0, __VA_ARGS__) @@ -26397,10 +27184,10 @@ #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_compatible_EXISTS 1 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_suppress_preamble 0 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_suppress_preamble_EXISTS 1 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_clock_frequency 2500000 -#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_wakeup_source 0 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_ethernet_40028000_S_mdio_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/flash-controller@52002000 @@ -26419,6 +27206,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_flash_controller_52002000_FULL_NAME "flash-controller@52002000" +#define DT_N_S_soc_S_flash_controller_52002000_FULL_NAME_UNQUOTED flash-controller@52002000 +#define DT_N_S_soc_S_flash_controller_52002000_FULL_NAME_TOKEN flash_controller_52002000 +#define DT_N_S_soc_S_flash_controller_52002000_FULL_NAME_UPPER_TOKEN FLASH_CONTROLLER_52002000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_flash_controller_52002000_PARENT DT_N_S_soc @@ -26444,18 +27234,18 @@ #define DT_N_S_soc_S_flash_controller_52002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_ORD 180 -#define DT_N_S_soc_S_flash_controller_52002000_ORD_STR_SORTABLE 00180 +#define DT_N_S_soc_S_flash_controller_52002000_ORD 183 +#define DT_N_S_soc_S_flash_controller_52002000_ORD_STR_SORTABLE 00183 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_SUPPORTS_ORDS \ - 181, /* /soc/flash-controller@52002000/flash@8000000 */ + 184, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_EXISTS 1 @@ -26466,8 +27256,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_flash_controller_52002000_REG_NUM 1 #define DT_N_S_soc_S_flash_controller_52002000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_REG_IDX_0_VAL_ADDRESS 1375739904 /* 0x52002000 */ -#define DT_N_S_soc_S_flash_controller_52002000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_flash_controller_52002000_REG_IDX_0_VAL_ADDRESS 1375739904 +#define DT_N_S_soc_S_flash_controller_52002000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_flash_controller_52002000_RANGES_NUM 0 #define DT_N_S_soc_S_flash_controller_52002000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_flash_controller_52002000_IRQ_NUM 1 @@ -26495,21 +27285,25 @@ #define DT_N_S_soc_S_flash_controller_52002000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_flash_controller_52002000_P_wakeup_source 0 -#define DT_N_S_soc_S_flash_controller_52002000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_flash_controller_52002000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_st_rdp1_enable_byte 85 +#define DT_N_S_soc_S_flash_controller_52002000_P_st_rdp1_enable_byte_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_reg {1375739904, 1024} +#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_0 1375739904 +#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_flash_controller_52002000_P_reg_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_compatible {"st,stm32-flash-controller", "st,stm32h7-flash-controller"} +#define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_0 "st,stm32-flash-controller" #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-flash-controller #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_0_STRING_TOKEN st_stm32_flash_controller #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FLASH_CONTROLLER -#define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_1 "st,stm32h7-flash-controller" #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_1_STRING_UNQUOTED st,stm32h7-flash-controller #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_1_STRING_TOKEN st_stm32h7_flash_controller #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_1_STRING_UPPER_TOKEN ST_STM32H7_FLASH_CONTROLLER -#define DT_N_S_soc_S_flash_controller_52002000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_52002000, compatible, 0) \ fn(DT_N_S_soc_S_flash_controller_52002000, compatible, 1) #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -26520,17 +27314,11 @@ fn(DT_N_S_soc_S_flash_controller_52002000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_LEN 2 #define DT_N_S_soc_S_flash_controller_52002000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_reg {1375739904 /* 0x52002000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_0 1375739904 -#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_flash_controller_52002000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_interrupts {4 /* 0x4 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_IDX_0 4 +#define DT_N_S_soc_S_flash_controller_52002000_P_interrupts {4, 0} #define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_IDX_0 4 #define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_flash_controller_52002000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -26546,8 +27334,10 @@ #define DT_N_S_soc_S_flash_controller_52002000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_flash_controller_52002000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_P_st_rdp1_enable_byte 85 -#define DT_N_S_soc_S_flash_controller_52002000_P_st_rdp1_enable_byte_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_wakeup_source 0 +#define DT_N_S_soc_S_flash_controller_52002000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_flash_controller_52002000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/flash-controller@52002000/flash@8000000 @@ -26566,6 +27356,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FULL_NAME "flash@8000000" +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FULL_NAME_UNQUOTED flash@8000000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FULL_NAME_TOKEN flash_8000000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FULL_NAME_UPPER_TOKEN FLASH_8000000 /* Node parent (/soc/flash-controller@52002000) identifier: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_PARENT DT_N_S_soc_S_flash_controller_52002000 @@ -26591,16 +27384,16 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD 181 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD_STR_SORTABLE 00181 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD 184 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_ORD_STR_SORTABLE 00184 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REQUIRES_ORDS \ - 180, /* /soc/flash-controller@52002000 */ + 183, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_SUPPORTS_ORDS \ - 182, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 185, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_EXISTS 1 @@ -26611,8 +27404,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REG_NUM 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REG_IDX_0_VAL_ADDRESS 134217728 /* 0x8000000 */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REG_IDX_0_VAL_ADDRESS 134217728 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_REG_IDX_0_VAL_SIZE 1048576 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_RANGES_NUM 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_IRQ_NUM 0 @@ -26629,20 +27422,20 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_wakeup_source 0 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_max_erase_time 4000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_max_erase_time_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_erase_block_size 131072 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_erase_block_size_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_write_block_size 32 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_write_block_size_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status "okay" #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, status, 0) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, status, 0) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, status, 0, __VA_ARGS__) @@ -26650,16 +27443,16 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_LEN 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_status_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible {"st,stm32-nv-flash", "soc-nv-flash"} +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_0 "st,stm32-nv-flash" #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-nv-flash #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_nv_flash #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_NV_FLASH -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_1 "soc-nv-flash" #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_1_STRING_UNQUOTED soc-nv-flash #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_1_STRING_TOKEN soc_nv_flash #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_1_STRING_UPPER_TOKEN SOC_NV_FLASH -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_IDX_1_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, compatible, 0) \ fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, compatible, 1) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, compatible, 0) DT_DEBRACKET_INTERNAL sep \ @@ -26670,20 +27463,18 @@ fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, compatible, 1, __VA_ARGS__) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_LEN 2 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg {134217728 /* 0x8000000 */, 1048576 /* 0x100000 */} -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_IDX_0 134217728 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg {134217728, 1048576} #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_IDX_1 1048576 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_IDX_0 134217728 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_IDX_1 1048576 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_reg_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_erase_block_size 131072 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_erase_block_size_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_write_block_size 32 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_write_block_size_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_max_erase_time 4000 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_max_erase_time_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_wakeup_source 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/flash-controller@52002000/flash@8000000/partitions @@ -26702,6 +27493,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FULL_NAME "partitions" +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FULL_NAME_UNQUOTED partitions +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FULL_NAME_TOKEN partitions +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FULL_NAME_UPPER_TOKEN PARTITIONS /* Node parent (/soc/flash-controller@52002000/flash@8000000) identifier: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_PARENT DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000 @@ -26727,18 +27521,18 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD 182 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD_STR_SORTABLE 00182 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD 185 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_ORD_STR_SORTABLE 00185 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_REQUIRES_ORDS \ - 181, /* /soc/flash-controller@52002000/flash@8000000 */ + 184, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_SUPPORTS_ORDS \ - 183, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@0 */ \ - 184, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@40000 */ \ - 185, /* /soc/flash-controller@52002000/flash@8000000/partitions/partition@e0000 */ + 186, \ + 187, \ + 188, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_EXISTS 1 @@ -26772,6 +27566,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME "partition@0" +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_UNQUOTED partition@0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_TOKEN partition_0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FULL_NAME_UPPER_TOKEN PARTITION_0 /* Node parent (/soc/flash-controller@52002000/flash@8000000/partitions) identifier: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions @@ -26797,12 +27594,12 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD 183 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00183 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD 186 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00186 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REQUIRES_ORDS \ - 182, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 185, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */ @@ -26814,8 +27611,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_NUM 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 262144 /* 0x40000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 262144 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_RANGES_NUM 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_IRQ_NUM 0 @@ -26843,11 +27640,11 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_label_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_read_only 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_read_only_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 262144 /* 0x40000 */} -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0 0 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg {0, 262144} #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1 262144 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_IDX_1 262144 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0_P_reg_EXISTS 1 /* @@ -26864,6 +27661,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FULL_NAME "partition@40000" +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FULL_NAME_UNQUOTED partition@40000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FULL_NAME_TOKEN partition_40000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FULL_NAME_UPPER_TOKEN PARTITION_40000 /* Node parent (/soc/flash-controller@52002000/flash@8000000/partitions) identifier: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_PARENT DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions @@ -26889,12 +27689,12 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD 184 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD_STR_SORTABLE 00184 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD 187 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_ORD_STR_SORTABLE 00187 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REQUIRES_ORDS \ - 182, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 185, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_SUPPORTS_ORDS /* nothing */ @@ -26906,8 +27706,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REG_NUM 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REG_IDX_0_VAL_ADDRESS 262144 /* 0x40000 */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REG_IDX_0_VAL_SIZE 786432 /* 0xc0000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REG_IDX_0_VAL_ADDRESS 262144 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_REG_IDX_0_VAL_SIZE 786432 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_RANGES_NUM 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_IRQ_NUM 0 @@ -26935,11 +27735,11 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_label_EXISTS 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_read_only 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_read_only_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg {262144 /* 0x40000 */, 786432 /* 0xc0000 */} -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_0 262144 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg {262144, 786432} #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_1 786432 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_0 262144 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_IDX_1 786432 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000_P_reg_EXISTS 1 /* @@ -26956,6 +27756,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FULL_NAME "partition@e0000" +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FULL_NAME_UNQUOTED partition@e0000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FULL_NAME_TOKEN partition_e0000 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FULL_NAME_UPPER_TOKEN PARTITION_E0000 /* Node parent (/soc/flash-controller@52002000/flash@8000000/partitions) identifier: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_PARENT DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions @@ -26981,12 +27784,12 @@ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_ORD 185 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_ORD_STR_SORTABLE 00185 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_ORD 188 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_ORD_STR_SORTABLE 00188 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REQUIRES_ORDS \ - 182, /* /soc/flash-controller@52002000/flash@8000000/partitions */ + 185, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_SUPPORTS_ORDS /* nothing */ @@ -26998,8 +27801,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_NUM 1 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_VAL_ADDRESS 917504 /* 0xe0000 */ -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_VAL_SIZE 131072 /* 0x20000 */ +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_VAL_ADDRESS 917504 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_REG_IDX_0_VAL_SIZE 131072 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_RANGES_NUM 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_IRQ_NUM 0 @@ -27015,11 +27818,11 @@ /* Generic property macros: */ #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_read_only 0 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_read_only_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg {917504 /* 0xe0000 */, 131072 /* 0x20000 */} -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_0 917504 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg {917504, 131072} #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_1 131072 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_0 917504 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_IDX_1 131072 #define DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000_P_reg_EXISTS 1 /* @@ -27033,6 +27836,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FULL_NAME "port" +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FULL_NAME_UNQUOTED port +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FULL_NAME_TOKEN port +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FULL_NAME_UPPER_TOKEN PORT /* Node parent (/soc/i2c@58001c00/ov7670@21) identifier: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_PARENT DT_N_S_soc_S_i2c_58001c00_S_ov7670_21 @@ -27058,16 +27864,16 @@ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_ORD 186 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_ORD_STR_SORTABLE 00186 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_ORD 189 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_ORD_STR_SORTABLE 00189 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_REQUIRES_ORDS \ - 163, /* /soc/i2c@58001c00/ov7670@21 */ + 166, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_SUPPORTS_ORDS \ - 187, /* /soc/i2c@58001c00/ov7670@21/port/endpoint */ + 190, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_EXISTS 1 @@ -27100,6 +27906,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FULL_NAME "endpoint" +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FULL_NAME_UNQUOTED endpoint +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FULL_NAME_TOKEN endpoint +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FULL_NAME_UPPER_TOKEN ENDPOINT /* Node parent (/soc/i2c@58001c00/ov7670@21/port) identifier: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_PARENT DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port @@ -27125,12 +27934,12 @@ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_ORD 187 -#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_ORD_STR_SORTABLE 00187 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_ORD 190 +#define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_ORD_STR_SORTABLE 00190 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_REQUIRES_ORDS \ - 186, /* /soc/i2c@58001c00/ov7670@21/port */ + 189, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint_SUPPORTS_ORDS /* nothing */ @@ -27170,6 +27979,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_FULL_NAME "fmc_a0_pf0" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_FULL_NAME_UNQUOTED fmc_a0_pf0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_FULL_NAME_TOKEN fmc_a0_pf0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_FULL_NAME_UPPER_TOKEN FMC_A0_PF0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27195,16 +28007,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD 188 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD_STR_SORTABLE 00188 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD 191 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_ORD_STR_SORTABLE 00191 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_EXISTS 1 @@ -27222,20 +28034,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_pinmux 2572 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate "very-high-speed" @@ -27244,16 +28042,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a10_pg0 @@ -27269,6 +28079,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_FULL_NAME "fmc_a10_pg0" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_FULL_NAME_UNQUOTED fmc_a10_pg0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_FULL_NAME_TOKEN fmc_a10_pg0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_FULL_NAME_UPPER_TOKEN FMC_A10_PG0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27294,16 +28107,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD 189 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD_STR_SORTABLE 00189 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD 192 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_ORD_STR_SORTABLE 00192 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_EXISTS 1 @@ -27321,20 +28134,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_pinmux 3084 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate "very-high-speed" @@ -27343,16 +28142,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a11_pg1 @@ -27368,6 +28179,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_FULL_NAME "fmc_a11_pg1" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_FULL_NAME_UNQUOTED fmc_a11_pg1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_FULL_NAME_TOKEN fmc_a11_pg1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_FULL_NAME_UPPER_TOKEN FMC_A11_PG1 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27393,16 +28207,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD 190 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD_STR_SORTABLE 00190 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD 193 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_ORD_STR_SORTABLE 00193 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_EXISTS 1 @@ -27420,20 +28234,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_pinmux 3116 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate "very-high-speed" @@ -27442,16 +28242,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a12_pg2 @@ -27467,6 +28279,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_FULL_NAME "fmc_a12_pg2" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_FULL_NAME_UNQUOTED fmc_a12_pg2 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_FULL_NAME_TOKEN fmc_a12_pg2 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_FULL_NAME_UPPER_TOKEN FMC_A12_PG2 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27492,16 +28307,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD 191 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD_STR_SORTABLE 00191 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD 194 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_ORD_STR_SORTABLE 00194 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_EXISTS 1 @@ -27519,20 +28334,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_pinmux 3148 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate "very-high-speed" @@ -27541,16 +28342,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a14_pg4 @@ -27566,6 +28379,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_FULL_NAME "fmc_a14_pg4" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_FULL_NAME_UNQUOTED fmc_a14_pg4 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_FULL_NAME_TOKEN fmc_a14_pg4 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_FULL_NAME_UPPER_TOKEN FMC_A14_PG4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27591,16 +28407,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD 192 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD_STR_SORTABLE 00192 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD 195 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_ORD_STR_SORTABLE 00195 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_EXISTS 1 @@ -27618,20 +28434,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_pinmux 3212 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate "very-high-speed" @@ -27640,16 +28442,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a15_pg5 @@ -27665,6 +28479,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_FULL_NAME "fmc_a15_pg5" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_FULL_NAME_UNQUOTED fmc_a15_pg5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_FULL_NAME_TOKEN fmc_a15_pg5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_FULL_NAME_UPPER_TOKEN FMC_A15_PG5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27690,16 +28507,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD 193 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD_STR_SORTABLE 00193 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD 196 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_ORD_STR_SORTABLE 00196 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_EXISTS 1 @@ -27717,20 +28534,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_pinmux 3244 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate "very-high-speed" @@ -27739,16 +28542,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a1_pf1 @@ -27764,6 +28579,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_FULL_NAME "fmc_a1_pf1" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_FULL_NAME_UNQUOTED fmc_a1_pf1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_FULL_NAME_TOKEN fmc_a1_pf1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_FULL_NAME_UPPER_TOKEN FMC_A1_PF1 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27789,16 +28607,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD 194 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD_STR_SORTABLE 00194 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD 197 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_ORD_STR_SORTABLE 00197 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_EXISTS 1 @@ -27816,20 +28634,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_pinmux 2604 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate "very-high-speed" @@ -27838,16 +28642,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a2_pf2 @@ -27863,6 +28679,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_FULL_NAME "fmc_a2_pf2" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_FULL_NAME_UNQUOTED fmc_a2_pf2 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_FULL_NAME_TOKEN fmc_a2_pf2 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_FULL_NAME_UPPER_TOKEN FMC_A2_PF2 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27888,16 +28707,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD 195 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD_STR_SORTABLE 00195 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD 198 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_ORD_STR_SORTABLE 00198 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_EXISTS 1 @@ -27915,20 +28734,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_pinmux 2636 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate "very-high-speed" @@ -27937,16 +28742,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a3_pf3 @@ -27962,6 +28779,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_FULL_NAME "fmc_a3_pf3" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_FULL_NAME_UNQUOTED fmc_a3_pf3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_FULL_NAME_TOKEN fmc_a3_pf3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_FULL_NAME_UPPER_TOKEN FMC_A3_PF3 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -27987,16 +28807,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD 196 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD_STR_SORTABLE 00196 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD 199 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_ORD_STR_SORTABLE 00199 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_EXISTS 1 @@ -28014,20 +28834,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_pinmux 2668 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate "very-high-speed" @@ -28036,16 +28842,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a4_pf4 @@ -28061,6 +28879,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_FULL_NAME "fmc_a4_pf4" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_FULL_NAME_UNQUOTED fmc_a4_pf4 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_FULL_NAME_TOKEN fmc_a4_pf4 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_FULL_NAME_UPPER_TOKEN FMC_A4_PF4 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28086,16 +28907,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD 197 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD_STR_SORTABLE 00197 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD 200 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_ORD_STR_SORTABLE 00200 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_EXISTS 1 @@ -28113,20 +28934,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_pinmux 2700 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate "very-high-speed" @@ -28135,16 +28942,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a5_pf5 @@ -28160,6 +28979,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_FULL_NAME "fmc_a5_pf5" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_FULL_NAME_UNQUOTED fmc_a5_pf5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_FULL_NAME_TOKEN fmc_a5_pf5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_FULL_NAME_UPPER_TOKEN FMC_A5_PF5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28185,16 +29007,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD 198 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD_STR_SORTABLE 00198 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD 201 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_ORD_STR_SORTABLE 00201 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_EXISTS 1 @@ -28212,20 +29034,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_pinmux 2732 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate "very-high-speed" @@ -28234,16 +29042,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a6_pf12 @@ -28259,6 +29079,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_FULL_NAME "fmc_a6_pf12" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_FULL_NAME_UNQUOTED fmc_a6_pf12 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_FULL_NAME_TOKEN fmc_a6_pf12 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_FULL_NAME_UPPER_TOKEN FMC_A6_PF12 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28284,16 +29107,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD 199 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD_STR_SORTABLE 00199 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD 202 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_ORD_STR_SORTABLE 00202 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_EXISTS 1 @@ -28311,20 +29134,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_pinmux 2956 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate "very-high-speed" @@ -28333,16 +29142,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a7_pf13 @@ -28358,6 +29179,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_FULL_NAME "fmc_a7_pf13" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_FULL_NAME_UNQUOTED fmc_a7_pf13 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_FULL_NAME_TOKEN fmc_a7_pf13 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_FULL_NAME_UPPER_TOKEN FMC_A7_PF13 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28383,16 +29207,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD 200 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD_STR_SORTABLE 00200 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD 203 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_ORD_STR_SORTABLE 00203 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_EXISTS 1 @@ -28410,20 +29234,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_pinmux 2988 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate "very-high-speed" @@ -28432,16 +29242,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a8_pf14 @@ -28457,6 +29279,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_FULL_NAME "fmc_a8_pf14" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_FULL_NAME_UNQUOTED fmc_a8_pf14 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_FULL_NAME_TOKEN fmc_a8_pf14 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_FULL_NAME_UPPER_TOKEN FMC_A8_PF14 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28482,16 +29307,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD 201 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD_STR_SORTABLE 00201 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD 204 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_ORD_STR_SORTABLE 00204 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_EXISTS 1 @@ -28509,20 +29334,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_pinmux 3020 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate "very-high-speed" @@ -28531,16 +29342,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_a9_pf15 @@ -28556,6 +29379,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_FULL_NAME "fmc_a9_pf15" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_FULL_NAME_UNQUOTED fmc_a9_pf15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_FULL_NAME_TOKEN fmc_a9_pf15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_FULL_NAME_UPPER_TOKEN FMC_A9_PF15 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28581,16 +29407,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD 202 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD_STR_SORTABLE 00202 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD 205 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_ORD_STR_SORTABLE 00205 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_EXISTS 1 @@ -28608,20 +29434,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_pinmux 3052 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate "very-high-speed" @@ -28630,16 +29442,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d0_pd14 @@ -28655,6 +29479,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_FULL_NAME "fmc_d0_pd14" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_FULL_NAME_UNQUOTED fmc_d0_pd14 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_FULL_NAME_TOKEN fmc_d0_pd14 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_FULL_NAME_UPPER_TOKEN FMC_D0_PD14 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28680,16 +29507,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD 203 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD_STR_SORTABLE 00203 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD 206 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_ORD_STR_SORTABLE 00206 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_EXISTS 1 @@ -28707,20 +29534,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_pinmux 1996 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate "very-high-speed" @@ -28729,16 +29542,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d10_pe13 @@ -28754,6 +29579,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_FULL_NAME "fmc_d10_pe13" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_FULL_NAME_UNQUOTED fmc_d10_pe13 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_FULL_NAME_TOKEN fmc_d10_pe13 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_FULL_NAME_UPPER_TOKEN FMC_D10_PE13 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28779,16 +29607,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD 204 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD_STR_SORTABLE 00204 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD 207 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_ORD_STR_SORTABLE 00207 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_EXISTS 1 @@ -28806,20 +29634,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_pinmux 2476 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate "very-high-speed" @@ -28828,16 +29642,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d11_pe14 @@ -28853,6 +29679,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_FULL_NAME "fmc_d11_pe14" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_FULL_NAME_UNQUOTED fmc_d11_pe14 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_FULL_NAME_TOKEN fmc_d11_pe14 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_FULL_NAME_UPPER_TOKEN FMC_D11_PE14 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28878,16 +29707,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD 205 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD_STR_SORTABLE 00205 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD 208 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_ORD_STR_SORTABLE 00208 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_EXISTS 1 @@ -28905,20 +29734,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_pinmux 2508 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate "very-high-speed" @@ -28927,16 +29742,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d12_pe15 @@ -28952,6 +29779,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_FULL_NAME "fmc_d12_pe15" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_FULL_NAME_UNQUOTED fmc_d12_pe15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_FULL_NAME_TOKEN fmc_d12_pe15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_FULL_NAME_UPPER_TOKEN FMC_D12_PE15 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -28977,16 +29807,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD 206 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD_STR_SORTABLE 00206 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD 209 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_ORD_STR_SORTABLE 00209 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_EXISTS 1 @@ -29004,20 +29834,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_pinmux 2540 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate "very-high-speed" @@ -29026,16 +29842,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d13_pd8 @@ -29051,6 +29879,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_FULL_NAME "fmc_d13_pd8" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_FULL_NAME_UNQUOTED fmc_d13_pd8 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_FULL_NAME_TOKEN fmc_d13_pd8 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_FULL_NAME_UPPER_TOKEN FMC_D13_PD8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29076,16 +29907,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD 207 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD_STR_SORTABLE 00207 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD 210 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_ORD_STR_SORTABLE 00210 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_EXISTS 1 @@ -29103,20 +29934,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_pinmux 1804 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate "very-high-speed" @@ -29125,16 +29942,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d14_pd9 @@ -29150,6 +29979,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_FULL_NAME "fmc_d14_pd9" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_FULL_NAME_UNQUOTED fmc_d14_pd9 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_FULL_NAME_TOKEN fmc_d14_pd9 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_FULL_NAME_UPPER_TOKEN FMC_D14_PD9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29175,16 +30007,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD 208 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD_STR_SORTABLE 00208 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD 211 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_ORD_STR_SORTABLE 00211 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_EXISTS 1 @@ -29202,20 +30034,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_pinmux 1836 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate "very-high-speed" @@ -29224,16 +30042,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d15_pd10 @@ -29249,6 +30079,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_FULL_NAME "fmc_d15_pd10" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_FULL_NAME_UNQUOTED fmc_d15_pd10 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_FULL_NAME_TOKEN fmc_d15_pd10 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_FULL_NAME_UPPER_TOKEN FMC_D15_PD10 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29274,16 +30107,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD 209 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD_STR_SORTABLE 00209 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD 212 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_ORD_STR_SORTABLE 00212 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_EXISTS 1 @@ -29301,20 +30134,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_pinmux 1868 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate "very-high-speed" @@ -29323,16 +30142,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d1_pd15 @@ -29348,6 +30179,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_FULL_NAME "fmc_d1_pd15" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_FULL_NAME_UNQUOTED fmc_d1_pd15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_FULL_NAME_TOKEN fmc_d1_pd15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_FULL_NAME_UPPER_TOKEN FMC_D1_PD15 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29373,16 +30207,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD 210 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD_STR_SORTABLE 00210 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD 213 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_ORD_STR_SORTABLE 00213 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_EXISTS 1 @@ -29400,20 +30234,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_pinmux 2028 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate "very-high-speed" @@ -29422,16 +30242,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d2_pd0 @@ -29447,6 +30279,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_FULL_NAME "fmc_d2_pd0" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_FULL_NAME_UNQUOTED fmc_d2_pd0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_FULL_NAME_TOKEN fmc_d2_pd0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_FULL_NAME_UPPER_TOKEN FMC_D2_PD0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29472,16 +30307,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD 211 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD_STR_SORTABLE 00211 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD 214 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_ORD_STR_SORTABLE 00214 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_EXISTS 1 @@ -29499,20 +30334,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_pinmux 1548 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate "very-high-speed" @@ -29521,16 +30342,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d3_pd1 @@ -29546,6 +30379,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_FULL_NAME "fmc_d3_pd1" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_FULL_NAME_UNQUOTED fmc_d3_pd1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_FULL_NAME_TOKEN fmc_d3_pd1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_FULL_NAME_UPPER_TOKEN FMC_D3_PD1 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29571,16 +30407,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD 212 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD_STR_SORTABLE 00212 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD 215 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_ORD_STR_SORTABLE 00215 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_EXISTS 1 @@ -29598,20 +30434,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_pinmux 1580 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate "very-high-speed" @@ -29620,16 +30442,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d4_pe7 @@ -29645,6 +30479,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_FULL_NAME "fmc_d4_pe7" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_FULL_NAME_UNQUOTED fmc_d4_pe7 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_FULL_NAME_TOKEN fmc_d4_pe7 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_FULL_NAME_UPPER_TOKEN FMC_D4_PE7 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29670,16 +30507,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD 213 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD_STR_SORTABLE 00213 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD 216 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_ORD_STR_SORTABLE 00216 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_EXISTS 1 @@ -29697,20 +30534,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_pinmux 2284 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate "very-high-speed" @@ -29719,16 +30542,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d5_pe8 @@ -29744,6 +30579,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_FULL_NAME "fmc_d5_pe8" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_FULL_NAME_UNQUOTED fmc_d5_pe8 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_FULL_NAME_TOKEN fmc_d5_pe8 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_FULL_NAME_UPPER_TOKEN FMC_D5_PE8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29769,16 +30607,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD 214 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD_STR_SORTABLE 00214 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD 217 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_ORD_STR_SORTABLE 00217 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_EXISTS 1 @@ -29796,20 +30634,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_pinmux 2316 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate "very-high-speed" @@ -29818,16 +30642,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d6_pe9 @@ -29843,6 +30679,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_FULL_NAME "fmc_d6_pe9" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_FULL_NAME_UNQUOTED fmc_d6_pe9 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_FULL_NAME_TOKEN fmc_d6_pe9 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_FULL_NAME_UPPER_TOKEN FMC_D6_PE9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29868,16 +30707,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD 215 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD_STR_SORTABLE 00215 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD 218 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_ORD_STR_SORTABLE 00218 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_EXISTS 1 @@ -29895,20 +30734,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_pinmux 2348 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate "very-high-speed" @@ -29917,16 +30742,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d7_pe10 @@ -29942,6 +30779,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_FULL_NAME "fmc_d7_pe10" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_FULL_NAME_UNQUOTED fmc_d7_pe10 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_FULL_NAME_TOKEN fmc_d7_pe10 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_FULL_NAME_UPPER_TOKEN FMC_D7_PE10 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -29967,16 +30807,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD 216 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD_STR_SORTABLE 00216 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD 219 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_ORD_STR_SORTABLE 00219 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_EXISTS 1 @@ -29994,20 +30834,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_pinmux 2380 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate "very-high-speed" @@ -30016,16 +30842,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d8_pe11 @@ -30041,6 +30879,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_FULL_NAME "fmc_d8_pe11" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_FULL_NAME_UNQUOTED fmc_d8_pe11 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_FULL_NAME_TOKEN fmc_d8_pe11 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_FULL_NAME_UPPER_TOKEN FMC_D8_PE11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30066,16 +30907,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD 217 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD_STR_SORTABLE 00217 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD 220 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_ORD_STR_SORTABLE 00220 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_EXISTS 1 @@ -30093,20 +30934,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_pinmux 2412 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate "very-high-speed" @@ -30115,16 +30942,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_d9_pe12 @@ -30140,6 +30979,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_FULL_NAME "fmc_d9_pe12" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_FULL_NAME_UNQUOTED fmc_d9_pe12 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_FULL_NAME_TOKEN fmc_d9_pe12 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_FULL_NAME_UPPER_TOKEN FMC_D9_PE12 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30165,16 +31007,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD 218 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD_STR_SORTABLE 00218 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD 221 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_ORD_STR_SORTABLE 00221 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_EXISTS 1 @@ -30192,20 +31034,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_pinmux 2444 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate "very-high-speed" @@ -30214,16 +31042,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_nbl0_pe0 @@ -30239,6 +31079,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_FULL_NAME "fmc_nbl0_pe0" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_FULL_NAME_UNQUOTED fmc_nbl0_pe0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_FULL_NAME_TOKEN fmc_nbl0_pe0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_FULL_NAME_UPPER_TOKEN FMC_NBL0_PE0 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30264,16 +31107,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD 219 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD_STR_SORTABLE 00219 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD 222 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_ORD_STR_SORTABLE 00222 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_EXISTS 1 @@ -30291,20 +31134,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_pinmux 2060 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate "very-high-speed" @@ -30313,16 +31142,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_nbl1_pe1 @@ -30338,6 +31179,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_FULL_NAME "fmc_nbl1_pe1" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_FULL_NAME_UNQUOTED fmc_nbl1_pe1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_FULL_NAME_TOKEN fmc_nbl1_pe1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_FULL_NAME_UPPER_TOKEN FMC_NBL1_PE1 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30363,16 +31207,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD 220 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD_STR_SORTABLE 00220 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD 223 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_ORD_STR_SORTABLE 00223 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_EXISTS 1 @@ -30390,20 +31234,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_pinmux 2092 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate "very-high-speed" @@ -30412,16 +31242,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_sdcke0_ph2 @@ -30437,6 +31279,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_FULL_NAME "fmc_sdcke0_ph2" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_FULL_NAME_UNQUOTED fmc_sdcke0_ph2 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_FULL_NAME_TOKEN fmc_sdcke0_ph2 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_FULL_NAME_UPPER_TOKEN FMC_SDCKE0_PH2 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30462,16 +31307,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD 221 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD_STR_SORTABLE 00221 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD 224 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_ORD_STR_SORTABLE 00224 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_EXISTS 1 @@ -30489,20 +31334,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_pinmux 3660 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate "very-high-speed" @@ -30511,16 +31342,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_sdclk_pg8 @@ -30536,6 +31379,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_FULL_NAME "fmc_sdclk_pg8" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_FULL_NAME_UNQUOTED fmc_sdclk_pg8 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_FULL_NAME_TOKEN fmc_sdclk_pg8 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_FULL_NAME_UPPER_TOKEN FMC_SDCLK_PG8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30561,16 +31407,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD 222 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD_STR_SORTABLE 00222 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD 225 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_ORD_STR_SORTABLE 00225 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_EXISTS 1 @@ -30588,20 +31434,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_pinmux 3340 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate "very-high-speed" @@ -30610,16 +31442,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_sdncas_pg15 @@ -30635,6 +31479,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_FULL_NAME "fmc_sdncas_pg15" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_FULL_NAME_UNQUOTED fmc_sdncas_pg15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_FULL_NAME_TOKEN fmc_sdncas_pg15 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_FULL_NAME_UPPER_TOKEN FMC_SDNCAS_PG15 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30660,16 +31507,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD 223 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD_STR_SORTABLE 00223 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD 226 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_ORD_STR_SORTABLE 00226 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_EXISTS 1 @@ -30687,20 +31534,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_pinmux 3564 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate "very-high-speed" @@ -30709,16 +31542,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_sdne0_ph3 @@ -30734,6 +31579,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_FULL_NAME "fmc_sdne0_ph3" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_FULL_NAME_UNQUOTED fmc_sdne0_ph3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_FULL_NAME_TOKEN fmc_sdne0_ph3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_FULL_NAME_UPPER_TOKEN FMC_SDNE0_PH3 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30759,16 +31607,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD 224 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD_STR_SORTABLE 00224 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD 227 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_ORD_STR_SORTABLE 00227 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_EXISTS 1 @@ -30786,20 +31634,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_pinmux 3692 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate "very-high-speed" @@ -30808,16 +31642,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_sdnras_pf11 @@ -30833,6 +31679,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_FULL_NAME "fmc_sdnras_pf11" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_FULL_NAME_UNQUOTED fmc_sdnras_pf11 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_FULL_NAME_TOKEN fmc_sdnras_pf11 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_FULL_NAME_UPPER_TOKEN FMC_SDNRAS_PF11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30858,16 +31707,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD 225 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD_STR_SORTABLE 00225 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD 228 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_ORD_STR_SORTABLE 00228 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_EXISTS 1 @@ -30885,20 +31734,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_pinmux 2924 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate "very-high-speed" @@ -30907,16 +31742,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/fmc_sdnwe_ph5 @@ -30932,6 +31779,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_FULL_NAME "fmc_sdnwe_ph5" +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_FULL_NAME_UNQUOTED fmc_sdnwe_ph5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_FULL_NAME_TOKEN fmc_sdnwe_ph5 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_FULL_NAME_UPPER_TOKEN FMC_SDNWE_PH5 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -30957,16 +31807,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD 226 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD_STR_SORTABLE 00226 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD 229 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_ORD_STR_SORTABLE 00229 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_SUPPORTS_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_EXISTS 1 @@ -30984,20 +31834,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_pinmux 3756 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate "very-high-speed" @@ -31006,16 +31842,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5_P_output_high_EXISTS 1 /* * Devicetree node: /soc/memory-controller@52004000 @@ -31034,6 +31882,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_memory_controller_52004000_FULL_NAME "memory-controller@52004000" +#define DT_N_S_soc_S_memory_controller_52004000_FULL_NAME_UNQUOTED memory-controller@52004000 +#define DT_N_S_soc_S_memory_controller_52004000_FULL_NAME_TOKEN memory_controller_52004000 +#define DT_N_S_soc_S_memory_controller_52004000_FULL_NAME_UPPER_TOKEN MEMORY_CONTROLLER_52004000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_memory_controller_52004000_PARENT DT_N_S_soc @@ -31059,56 +31910,56 @@ #define DT_N_S_soc_S_memory_controller_52004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_controller_52004000_ORD 227 -#define DT_N_S_soc_S_memory_controller_52004000_ORD_STR_SORTABLE 00227 +#define DT_N_S_soc_S_memory_controller_52004000_ORD 230 +#define DT_N_S_soc_S_memory_controller_52004000_ORD_STR_SORTABLE 00230 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_controller_52004000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 9, /* /soc/rcc@58024400 */ \ - 188, /* /soc/pin-controller@58020000/fmc_a0_pf0 */ \ - 189, /* /soc/pin-controller@58020000/fmc_a10_pg0 */ \ - 190, /* /soc/pin-controller@58020000/fmc_a11_pg1 */ \ - 191, /* /soc/pin-controller@58020000/fmc_a12_pg2 */ \ - 192, /* /soc/pin-controller@58020000/fmc_a14_pg4 */ \ - 193, /* /soc/pin-controller@58020000/fmc_a15_pg5 */ \ - 194, /* /soc/pin-controller@58020000/fmc_a1_pf1 */ \ - 195, /* /soc/pin-controller@58020000/fmc_a2_pf2 */ \ - 196, /* /soc/pin-controller@58020000/fmc_a3_pf3 */ \ - 197, /* /soc/pin-controller@58020000/fmc_a4_pf4 */ \ - 198, /* /soc/pin-controller@58020000/fmc_a5_pf5 */ \ - 199, /* /soc/pin-controller@58020000/fmc_a6_pf12 */ \ - 200, /* /soc/pin-controller@58020000/fmc_a7_pf13 */ \ - 201, /* /soc/pin-controller@58020000/fmc_a8_pf14 */ \ - 202, /* /soc/pin-controller@58020000/fmc_a9_pf15 */ \ - 203, /* /soc/pin-controller@58020000/fmc_d0_pd14 */ \ - 204, /* /soc/pin-controller@58020000/fmc_d10_pe13 */ \ - 205, /* /soc/pin-controller@58020000/fmc_d11_pe14 */ \ - 206, /* /soc/pin-controller@58020000/fmc_d12_pe15 */ \ - 207, /* /soc/pin-controller@58020000/fmc_d13_pd8 */ \ - 208, /* /soc/pin-controller@58020000/fmc_d14_pd9 */ \ - 209, /* /soc/pin-controller@58020000/fmc_d15_pd10 */ \ - 210, /* /soc/pin-controller@58020000/fmc_d1_pd15 */ \ - 211, /* /soc/pin-controller@58020000/fmc_d2_pd0 */ \ - 212, /* /soc/pin-controller@58020000/fmc_d3_pd1 */ \ - 213, /* /soc/pin-controller@58020000/fmc_d4_pe7 */ \ - 214, /* /soc/pin-controller@58020000/fmc_d5_pe8 */ \ - 215, /* /soc/pin-controller@58020000/fmc_d6_pe9 */ \ - 216, /* /soc/pin-controller@58020000/fmc_d7_pe10 */ \ - 217, /* /soc/pin-controller@58020000/fmc_d8_pe11 */ \ - 218, /* /soc/pin-controller@58020000/fmc_d9_pe12 */ \ - 219, /* /soc/pin-controller@58020000/fmc_nbl0_pe0 */ \ - 220, /* /soc/pin-controller@58020000/fmc_nbl1_pe1 */ \ - 221, /* /soc/pin-controller@58020000/fmc_sdcke0_ph2 */ \ - 222, /* /soc/pin-controller@58020000/fmc_sdclk_pg8 */ \ - 223, /* /soc/pin-controller@58020000/fmc_sdncas_pg15 */ \ - 224, /* /soc/pin-controller@58020000/fmc_sdne0_ph3 */ \ - 225, /* /soc/pin-controller@58020000/fmc_sdnras_pf11 */ \ - 226, /* /soc/pin-controller@58020000/fmc_sdnwe_ph5 */ + 4, \ + 9, \ + 191, \ + 192, \ + 193, \ + 194, \ + 195, \ + 196, \ + 197, \ + 198, \ + 199, \ + 200, \ + 201, \ + 202, \ + 203, \ + 204, \ + 205, \ + 206, \ + 207, \ + 208, \ + 209, \ + 210, \ + 211, \ + 212, \ + 213, \ + 214, \ + 215, \ + 216, \ + 217, \ + 218, \ + 219, \ + 220, \ + 221, \ + 222, \ + 223, \ + 224, \ + 225, \ + 226, \ + 227, \ + 228, \ + 229, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_controller_52004000_SUPPORTS_ORDS \ - 228, /* /soc/memory-controller@52004000/sdram */ + 231, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_memory_controller_52004000_EXISTS 1 @@ -31118,8 +31969,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_memory_controller_52004000_REG_NUM 1 #define DT_N_S_soc_S_memory_controller_52004000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_REG_IDX_0_VAL_ADDRESS 1375748096 /* 0x52004000 */ -#define DT_N_S_soc_S_memory_controller_52004000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_memory_controller_52004000_REG_IDX_0_VAL_ADDRESS 1375748096 +#define DT_N_S_soc_S_memory_controller_52004000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_memory_controller_52004000_RANGES_NUM 0 #define DT_N_S_soc_S_memory_controller_52004000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_memory_controller_52004000_IRQ_NUM 0 @@ -31179,43 +32030,25 @@ #define DT_N_S_soc_S_memory_controller_52004000_PINCTRL_NAME_default_IDX_38_PH DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10 /* Generic property macros: */ -#define DT_N_S_soc_S_memory_controller_52004000_P_wakeup_source 0 -#define DT_N_S_soc_S_memory_controller_52004000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_status "okay" -#define DT_N_S_soc_S_memory_controller_52004000_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_memory_controller_52004000_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_memory_controller_52004000_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_memory_controller_52004000_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_memory_controller_52004000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_memory_controller_52004000_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0) -#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0) -#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_controller_52004000_P_status_LEN 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_status_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible {"st,stm32h7-fmc"} -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0 "st,stm32h7-fmc" -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-fmc -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_fmc -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_FMC -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0) -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0) -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_LEN 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_reg {1375748096 /* 0x52004000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_memory_controller_52004000_P_reg_IDX_0 1375748096 +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap "disable" +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_STRING_UNQUOTED disable +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_STRING_TOKEN disable +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_STRING_UPPER_TOKEN DISABLE +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_IDX_0 "disable" +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_IDX_0_ENUM_VAL_disable_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0) +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0) +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_LEN 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_reg {1375748096, 1024} #define DT_N_S_soc_S_memory_controller_52004000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_memory_controller_52004000_P_reg_IDX_0 1375748096 #define DT_N_S_soc_S_memory_controller_52004000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_reg_IDX_1 1024 #define DT_N_S_soc_S_memory_controller_52004000_P_reg_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -31229,8 +32062,6 @@ #define DT_N_S_soc_S_memory_controller_52004000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_controller_52004000_P_clocks_LEN 1 #define DT_N_S_soc_S_memory_controller_52004000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_0_IDX_0_EXISTS 1 @@ -31507,33 +32338,49 @@ #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_0_LEN 39 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, pinctrl_names, 0) #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, pinctrl_names, 0) #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_memory_controller_52004000_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap "disable" -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_STRING_UNQUOTED disable -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_STRING_TOKEN disable -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_STRING_UPPER_TOKEN DISABLE -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_IDX_0 "disable" -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_ENUM_IDX 0 -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_ENUM_VAL_disable_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_ENUM_TOKEN disable -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_ENUM_UPPER_TOKEN DISABLE -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0) -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0) -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, st_mem_swap, 0, __VA_ARGS__) -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_LEN 1 -#define DT_N_S_soc_S_memory_controller_52004000_P_st_mem_swap_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_status "okay" +#define DT_N_S_soc_S_memory_controller_52004000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_memory_controller_52004000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_memory_controller_52004000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_memory_controller_52004000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_memory_controller_52004000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0) +#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0) +#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_controller_52004000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_controller_52004000_P_status_LEN 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_status_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible {"st,stm32h7-fmc"} +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0 "st,stm32h7-fmc" +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32h7-fmc +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_STRING_TOKEN st_stm32h7_fmc +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32H7_FMC +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0) +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0) +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_LEN 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_wakeup_source 0 +#define DT_N_S_soc_S_memory_controller_52004000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_memory_controller_52004000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/memory-controller@52004000/sdram @@ -31552,6 +32399,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_FULL_NAME "sdram" +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_FULL_NAME_UNQUOTED sdram +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_FULL_NAME_TOKEN sdram +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_FULL_NAME_UPPER_TOKEN SDRAM /* Node parent (/soc/memory-controller@52004000) identifier: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_PARENT DT_N_S_soc_S_memory_controller_52004000 @@ -31577,16 +32427,16 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD 228 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD_STR_SORTABLE 00228 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD 231 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_ORD_STR_SORTABLE 00231 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_REQUIRES_ORDS \ - 227, /* /soc/memory-controller@52004000 */ + 230, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_SUPPORTS_ORDS \ - 229, /* /soc/memory-controller@52004000/sdram/bank@0 */ + 232, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_EXISTS 1 @@ -31610,20 +32460,22 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_wakeup_source 0 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_power_up_delay 100 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_power_up_delay_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_num_auto_refresh 8 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_num_auto_refresh_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_mode_register 544 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_mode_register_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_refresh_rate 603 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_refresh_rate_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status "okay" #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_IDX_0 "okay" #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, status, 0) #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, status, 0) #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, status, 0, __VA_ARGS__) @@ -31631,11 +32483,11 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_LEN 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_status_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible {"st,stm32-fmc-sdram"} +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_IDX_0 "st,stm32-fmc-sdram" #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-fmc-sdram #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_IDX_0_STRING_TOKEN st_stm32_fmc_sdram #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_FMC_SDRAM -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, compatible, 0) #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, compatible, 0) #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, compatible, 0, __VA_ARGS__) @@ -31644,14 +32496,10 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_compatible_EXISTS 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_power_up_delay 100 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_power_up_delay_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_num_auto_refresh 8 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_num_auto_refresh_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_mode_register 544 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_mode_register_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_refresh_rate 603 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_refresh_rate_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_wakeup_source 0 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/memory-controller@52004000/sdram/bank@0 @@ -31667,6 +32515,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FULL_NAME "bank@0" +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FULL_NAME_UNQUOTED bank@0 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FULL_NAME_TOKEN bank_0 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FULL_NAME_UPPER_TOKEN BANK_0 /* Node parent (/soc/memory-controller@52004000/sdram) identifier: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_PARENT DT_N_S_soc_S_memory_controller_52004000_S_sdram @@ -31692,12 +32543,12 @@ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD 229 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD_STR_SORTABLE 00229 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD 232 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_ORD_STR_SORTABLE 00232 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_REQUIRES_ORDS \ - 228, /* /soc/memory-controller@52004000/sdram */ + 231, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_SUPPORTS_ORDS /* nothing */ @@ -31708,7 +32559,7 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_REG_NUM 1 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_REG_IDX_0_VAL_ADDRESS 0 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_RANGES_NUM 0 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_IRQ_NUM 0 @@ -31721,23 +32572,23 @@ /* Generic property macros: */ #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_reg 0 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_reg_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control {0 /* 0x0 */, 4 /* 0x4 */, 16 /* 0x10 */, 64 /* 0x40 */, 256 /* 0x100 */, 2048 /* 0x800 */, 4096 /* 0x1000 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_0 0 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control {0, 4, 16, 64, 256, 2048, 4096, 0} #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_1 4 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_0 0 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_2 16 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_1 4 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_3 64 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_2 16 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_4 256 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_3 64 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_5 2048 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_4 256 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_6 4096 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_5 2048 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_7 0 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_6 4096 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_IDX_7 0 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_control, 0) \ fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_control, 1) \ fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_control, 2) \ @@ -31772,21 +32623,21 @@ fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_control, 7, __VA_ARGS__) #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_LEN 8 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_control_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing {2 /* 0x2 */, 6 /* 0x6 */, 4 /* 0x4 */, 6 /* 0x6 */, 2 /* 0x2 */, 2 /* 0x2 */, 2 /* 0x2 */} -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_0 2 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing {2, 6, 4, 6, 2, 2, 2} #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_1 6 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_0 2 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_2 4 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_1 6 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_3 6 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_2 4 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_4 2 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_3 6 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_5 2 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_4 2 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_6 2 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_5 2 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_6_EXISTS 1 +#define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_IDX_6 2 #define DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0_P_st_sdram_timing_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_timing, 0) \ fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_timing, 1) \ fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, st_sdram_timing, 2) \ @@ -31835,6 +32686,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FULL_NAME "gpio@58021400" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FULL_NAME_UNQUOTED gpio@58021400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FULL_NAME_TOKEN gpio_58021400 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FULL_NAME_UPPER_TOKEN GPIO_58021400 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -31860,13 +32714,13 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD 230 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD_STR_SORTABLE 00230 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD 233 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_ORD_STR_SORTABLE 00233 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REQUIRES_ORDS \ - 9, /* /soc/rcc@58024400 */ \ - 10, /* /soc/pin-controller@58020000 */ + 9, \ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_SUPPORTS_ORDS /* nothing */ @@ -31879,8 +32733,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REG_NUM 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REG_IDX_0_VAL_ADDRESS 1476531200 /* 0x58021400 */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REG_IDX_0_VAL_ADDRESS 1476531200 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_RANGES_NUM 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_IRQ_NUM 0 @@ -31896,31 +32750,11 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_gpio_controller 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_gpio_controller_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_ngpios 32 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_ngpios_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_wakeup_source 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible {"st,stm32-gpio"} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0 "st,stm32-gpio" -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_LEN 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg {1476531200 /* 0x58021400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_IDX_0 1476531200 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg {1476531200, 1024} #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_IDX_0 1476531200 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_IDX_1 1024 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_reg_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 @@ -31934,8 +32768,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_clocks_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_ngpios 16 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_ngpios_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_gpio_controller 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_gpio_controller_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible {"st,stm32-gpio"} +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0 "st,stm32-gpio" +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_STRING_TOKEN st_stm32_gpio +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_GPIO +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_LEN 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_compatible_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_wakeup_source 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 @@ -31951,6 +32805,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_FULL_NAME "quadspi_bk1_io0_pd11" +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_FULL_NAME_UNQUOTED quadspi_bk1_io0_pd11 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_FULL_NAME_TOKEN quadspi_bk1_io0_pd11 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_FULL_NAME_UPPER_TOKEN QUADSPI_BK1_IO0_PD11 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -31976,16 +32833,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD 231 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD_STR_SORTABLE 00231 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD 234 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_ORD_STR_SORTABLE 00234 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_SUPPORTS_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_EXISTS 1 @@ -32003,20 +32860,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_pinmux 1897 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate "very-high-speed" @@ -32025,16 +32868,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 @@ -32050,6 +32905,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_FULL_NAME "quadspi_bk1_io1_pd12" +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_FULL_NAME_UNQUOTED quadspi_bk1_io1_pd12 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_FULL_NAME_TOKEN quadspi_bk1_io1_pd12 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_FULL_NAME_UPPER_TOKEN QUADSPI_BK1_IO1_PD12 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -32075,16 +32933,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD 232 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD_STR_SORTABLE 00232 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD 235 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_ORD_STR_SORTABLE 00235 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_SUPPORTS_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_EXISTS 1 @@ -32102,20 +32960,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_pinmux 1929 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate "very-high-speed" @@ -32124,16 +32968,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 @@ -32149,6 +33005,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_FULL_NAME "quadspi_bk1_io2_pe2" +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_FULL_NAME_UNQUOTED quadspi_bk1_io2_pe2 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_FULL_NAME_TOKEN quadspi_bk1_io2_pe2 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_FULL_NAME_UPPER_TOKEN QUADSPI_BK1_IO2_PE2 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -32174,16 +33033,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD 233 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD_STR_SORTABLE 00233 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD 236 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_ORD_STR_SORTABLE 00236 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_SUPPORTS_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_EXISTS 1 @@ -32201,20 +33060,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_pinmux 2121 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate "very-high-speed" @@ -32223,16 +33068,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 @@ -32248,6 +33105,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_FULL_NAME "quadspi_bk1_io3_pf6" +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_FULL_NAME_UNQUOTED quadspi_bk1_io3_pf6 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_FULL_NAME_TOKEN quadspi_bk1_io3_pf6 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_FULL_NAME_UPPER_TOKEN QUADSPI_BK1_IO3_PF6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -32273,16 +33133,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD 234 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD_STR_SORTABLE 00234 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD 237 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_ORD_STR_SORTABLE 00237 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_SUPPORTS_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_EXISTS 1 @@ -32300,20 +33160,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_pinmux 2761 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate "very-high-speed" @@ -32322,16 +33168,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 @@ -32347,6 +33205,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_FULL_NAME "quadspi_bk1_ncs_pg6" +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_FULL_NAME_UNQUOTED quadspi_bk1_ncs_pg6 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_FULL_NAME_TOKEN quadspi_bk1_ncs_pg6 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_FULL_NAME_UPPER_TOKEN QUADSPI_BK1_NCS_PG6 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -32372,16 +33233,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD 235 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD_STR_SORTABLE 00235 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD 238 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_ORD_STR_SORTABLE 00238 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_SUPPORTS_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_EXISTS 1 @@ -32399,20 +33260,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_pinmux 3274 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate "very-high-speed" @@ -32421,16 +33268,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/quadspi_clk_pf10 @@ -32446,6 +33305,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_FULL_NAME "quadspi_clk_pf10" +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_FULL_NAME_UNQUOTED quadspi_clk_pf10 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_FULL_NAME_TOKEN quadspi_clk_pf10 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_FULL_NAME_UPPER_TOKEN QUADSPI_CLK_PF10 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -32471,16 +33333,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD 236 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD_STR_SORTABLE 00236 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD 239 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_ORD_STR_SORTABLE 00239 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_SUPPORTS_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_EXISTS 1 @@ -32498,20 +33360,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_pinmux 2889 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate "very-high-speed" @@ -32520,16 +33368,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_STRING_UPPER_TOKEN VERY_HIGH_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_IDX_0 "very-high-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_ENUM_IDX 3 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_ENUM_VAL_very_high_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_ENUM_TOKEN very_high_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_ENUM_UPPER_TOKEN VERY_HIGH_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_IDX_0_ENUM_VAL_very_high_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10_P_output_high_EXISTS 1 /* * Devicetree node: /soc/quadspi@52005000 @@ -32548,6 +33408,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_quadspi_52005000_FULL_NAME "quadspi@52005000" +#define DT_N_S_soc_S_quadspi_52005000_FULL_NAME_UNQUOTED quadspi@52005000 +#define DT_N_S_soc_S_quadspi_52005000_FULL_NAME_TOKEN quadspi_52005000 +#define DT_N_S_soc_S_quadspi_52005000_FULL_NAME_UPPER_TOKEN QUADSPI_52005000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_quadspi_52005000_PARENT DT_N_S_soc @@ -32573,24 +33436,24 @@ #define DT_N_S_soc_S_quadspi_52005000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_ORD 237 -#define DT_N_S_soc_S_quadspi_52005000_ORD_STR_SORTABLE 00237 +#define DT_N_S_soc_S_quadspi_52005000_ORD 240 +#define DT_N_S_soc_S_quadspi_52005000_ORD_STR_SORTABLE 00240 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 231, /* /soc/pin-controller@58020000/quadspi_bk1_io0_pd11 */ \ - 232, /* /soc/pin-controller@58020000/quadspi_bk1_io1_pd12 */ \ - 233, /* /soc/pin-controller@58020000/quadspi_bk1_io2_pe2 */ \ - 234, /* /soc/pin-controller@58020000/quadspi_bk1_io3_pf6 */ \ - 235, /* /soc/pin-controller@58020000/quadspi_bk1_ncs_pg6 */ \ - 236, /* /soc/pin-controller@58020000/quadspi_clk_pf10 */ + 4, \ + 5, \ + 9, \ + 234, \ + 235, \ + 236, \ + 237, \ + 238, \ + 239, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_SUPPORTS_ORDS \ - 238, /* /soc/quadspi@52005000/qspi-nor-flash@90000000 */ + 241, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_quadspi_52005000_EXISTS 1 @@ -32600,8 +33463,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_quadspi_52005000_REG_NUM 1 #define DT_N_S_soc_S_quadspi_52005000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_REG_IDX_0_VAL_ADDRESS 1375752192 /* 0x52005000 */ -#define DT_N_S_soc_S_quadspi_52005000_REG_IDX_0_VAL_SIZE 52 /* 0x34 */ +#define DT_N_S_soc_S_quadspi_52005000_REG_IDX_0_VAL_ADDRESS 1375752192 +#define DT_N_S_soc_S_quadspi_52005000_REG_IDX_0_VAL_SIZE 52 #define DT_N_S_soc_S_quadspi_52005000_RANGES_NUM 0 #define DT_N_S_soc_S_quadspi_52005000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_quadspi_52005000_IRQ_NUM 1 @@ -32635,64 +33498,18 @@ #define DT_N_S_soc_S_quadspi_52005000_PINCTRL_NAME_default_IDX_5_PH DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6 /* Generic property macros: */ -#define DT_N_S_soc_S_quadspi_52005000_P_wakeup_source 0 -#define DT_N_S_soc_S_quadspi_52005000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_status "okay" -#define DT_N_S_soc_S_quadspi_52005000_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_quadspi_52005000_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_quadspi_52005000_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_quadspi_52005000_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_quadspi_52005000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_quadspi_52005000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_quadspi_52005000_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, status, 0) -#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, status, 0) -#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_quadspi_52005000_P_status_LEN 1 -#define DT_N_S_soc_S_quadspi_52005000_P_status_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_compatible {"st,stm32-qspi"} -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0 "st,stm32-qspi" -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qspi -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_STRING_TOKEN st_stm32_qspi -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QSPI -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0) -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0) -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_LEN 1 -#define DT_N_S_soc_S_quadspi_52005000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_reg {1375752192 /* 0x52005000 */, 52 /* 0x34 */} -#define DT_N_S_soc_S_quadspi_52005000_P_reg_IDX_0 1375752192 +#define DT_N_S_soc_S_quadspi_52005000_P_reg {1375752192, 52} #define DT_N_S_soc_S_quadspi_52005000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_reg_IDX_1 52 +#define DT_N_S_soc_S_quadspi_52005000_P_reg_IDX_0 1375752192 #define DT_N_S_soc_S_quadspi_52005000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_reg_IDX_1 52 #define DT_N_S_soc_S_quadspi_52005000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_interrupts {92 /* 0x5c */, 0 /* 0x0 */} -#define DT_N_S_soc_S_quadspi_52005000_P_interrupts_IDX_0 92 +#define DT_N_S_soc_S_quadspi_52005000_P_interrupts {92, 0} #define DT_N_S_soc_S_quadspi_52005000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_quadspi_52005000_P_interrupts_IDX_0 92 #define DT_N_S_soc_S_quadspi_52005000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_quadspi_52005000_P_interrupts_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bus 212 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bits 16384 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0) -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0) -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_LEN 1 -#define DT_N_S_soc_S_quadspi_52005000_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_0_IDX_0_EXISTS 1 @@ -32738,11 +33555,11 @@ #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_0_LEN 6 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, pinctrl_names, 0) #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, pinctrl_names, 0) #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, pinctrl_names, 0, __VA_ARGS__) @@ -32751,6 +33568,50 @@ #define DT_N_S_soc_S_quadspi_52005000_P_pinctrl_names_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_P_dual_flash 0 #define DT_N_S_soc_S_quadspi_52005000_P_dual_flash_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_status "okay" +#define DT_N_S_soc_S_quadspi_52005000_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_quadspi_52005000_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_quadspi_52005000_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_quadspi_52005000_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_quadspi_52005000_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_quadspi_52005000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, status, 0) +#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, status, 0) +#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_quadspi_52005000_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_quadspi_52005000_P_status_LEN 1 +#define DT_N_S_soc_S_quadspi_52005000_P_status_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_compatible {"st,stm32-qspi"} +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0 "st,stm32-qspi" +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qspi +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_STRING_TOKEN st_stm32_qspi +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QSPI +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0) +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0) +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_LEN 1 +#define DT_N_S_soc_S_quadspi_52005000_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bus 212 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bits 16384 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0) +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0) +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_LEN 1 +#define DT_N_S_soc_S_quadspi_52005000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_wakeup_source 0 +#define DT_N_S_soc_S_quadspi_52005000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_quadspi_52005000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/quadspi@52005000/qspi-nor-flash@90000000 @@ -32769,6 +33630,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FULL_NAME "qspi-nor-flash@90000000" +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FULL_NAME_UNQUOTED qspi-nor-flash@90000000 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FULL_NAME_TOKEN qspi_nor_flash_90000000 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FULL_NAME_UPPER_TOKEN QSPI_NOR_FLASH_90000000 /* Node parent (/soc/quadspi@52005000) identifier: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_PARENT DT_N_S_soc_S_quadspi_52005000 @@ -32794,16 +33658,16 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD 238 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD_STR_SORTABLE 00238 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD 241 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_ORD_STR_SORTABLE 00241 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REQUIRES_ORDS \ - 237, /* /soc/quadspi@52005000 */ + 240, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_SUPPORTS_ORDS \ - 239, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ + 242, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_EXISTS 1 @@ -32817,9 +33681,9 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_NUM 2 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_IDX_0_VAL_ADDRESS 2415919104 /* 0x90000000 */ +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_IDX_0_VAL_ADDRESS 2415919104 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_IDX_1_VAL_ADDRESS 16777216 /* 0x1000000 */ +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_REG_IDX_1_VAL_ADDRESS 16777216 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_RANGES_NUM 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_IRQ_NUM 0 @@ -32835,20 +33699,28 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_wakeup_source 0 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg {2415919104, 16777216} +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_0 2415919104 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_1 16777216 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_qspi_max_frequency 72000000 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_qspi_max_frequency_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd 0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd_wait 10 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd_wait_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_requires_ulbpr 0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_requires_ulbpr_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status "okay" #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_IDX_0 "okay" #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, status, 0) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, status, 0) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, status, 0, __VA_ARGS__) @@ -32856,31 +33728,23 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_LEN 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_status_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible {"st,stm32-qspi-nor"} +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_IDX_0 "st,stm32-qspi-nor" #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-qspi-nor #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_qspi_nor #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_QSPI_NOR -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, compatible, 0) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, compatible, 0) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_LEN 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg {2415919104 /* 0x90000000 */, 16777216 /* 0x1000000 */} -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_0 2415919104 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_1 16777216 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reg_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_qspi_max_frequency 72000000 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_qspi_max_frequency_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd 0 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd_wait 10 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_reset_cmd_wait_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_wakeup_source 0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions @@ -32899,6 +33763,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_FULL_NAME "partitions" +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_FULL_NAME_UNQUOTED partitions +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_FULL_NAME_TOKEN partitions +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_FULL_NAME_UPPER_TOKEN PARTITIONS /* Node parent (/soc/quadspi@52005000/qspi-nor-flash@90000000) identifier: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_PARENT DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000 @@ -32924,17 +33791,17 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) DT_DEBRACKET_INTERNAL sep fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD 239 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD_STR_SORTABLE 00239 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD 242 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_ORD_STR_SORTABLE 00242 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_REQUIRES_ORDS \ - 238, /* /soc/quadspi@52005000/qspi-nor-flash@90000000 */ + 241, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_SUPPORTS_ORDS \ - 240, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@0 */ \ - 241, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions/partition@100000 */ + 243, \ + 244, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_EXISTS 1 @@ -32968,6 +33835,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FULL_NAME "partition@0" +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FULL_NAME_UNQUOTED partition@0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FULL_NAME_TOKEN partition_0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FULL_NAME_UPPER_TOKEN PARTITION_0 /* Node parent (/soc/quadspi@52005000/qspi-nor-flash@90000000/partitions) identifier: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_PARENT DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions @@ -32993,12 +33863,12 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD 240 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00240 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD 243 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_ORD_STR_SORTABLE 00243 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REQUIRES_ORDS \ - 239, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ + 242, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_SUPPORTS_ORDS /* nothing */ @@ -33010,8 +33880,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REG_NUM 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 /* 0x0 */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 1048576 /* 0x100000 */ +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REG_IDX_0_VAL_ADDRESS 0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_REG_IDX_0_VAL_SIZE 1048576 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_RANGES_NUM 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_FOREACH_RANGE(fn) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_IRQ_NUM 0 @@ -33039,11 +33909,11 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_label_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_read_only 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_read_only_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg {0 /* 0x0 */, 1048576 /* 0x100000 */} -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_IDX_0 0 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg {0, 1048576} #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_IDX_1 1048576 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_IDX_0 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_IDX_1 1048576 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0_P_reg_EXISTS 1 /* @@ -33060,6 +33930,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FULL_NAME "partition@100000" +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FULL_NAME_UNQUOTED partition@100000 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FULL_NAME_TOKEN partition_100000 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FULL_NAME_UPPER_TOKEN PARTITION_100000 /* Node parent (/soc/quadspi@52005000/qspi-nor-flash@90000000/partitions) identifier: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_PARENT DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions @@ -33085,12 +33958,12 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD 241 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD_STR_SORTABLE 00241 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD 244 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_ORD_STR_SORTABLE 00244 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REQUIRES_ORDS \ - 239, /* /soc/quadspi@52005000/qspi-nor-flash@90000000/partitions */ + 242, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_SUPPORTS_ORDS /* nothing */ @@ -33102,8 +33975,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REG_NUM 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REG_IDX_0_VAL_ADDRESS 1048576 /* 0x100000 */ -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REG_IDX_0_VAL_SIZE 15728640 /* 0xf00000 */ +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REG_IDX_0_VAL_ADDRESS 1048576 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_REG_IDX_0_VAL_SIZE 15728640 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_RANGES_NUM 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_IRQ_NUM 0 @@ -33131,11 +34004,11 @@ #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_label_EXISTS 1 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_read_only 0 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_read_only_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg {1048576 /* 0x100000 */, 15728640 /* 0xf00000 */} -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_IDX_0 1048576 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg {1048576, 15728640} #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_IDX_1 15728640 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_IDX_0 1048576 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_IDX_1 15728640 #define DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000_P_reg_EXISTS 1 /* @@ -33155,6 +34028,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_rtc_58004000_FULL_NAME "rtc@58004000" +#define DT_N_S_soc_S_rtc_58004000_FULL_NAME_UNQUOTED rtc@58004000 +#define DT_N_S_soc_S_rtc_58004000_FULL_NAME_TOKEN rtc_58004000 +#define DT_N_S_soc_S_rtc_58004000_FULL_NAME_UPPER_TOKEN RTC_58004000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_rtc_58004000_PARENT DT_N_S_soc @@ -33180,18 +34056,18 @@ #define DT_N_S_soc_S_rtc_58004000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rtc_58004000_ORD 242 -#define DT_N_S_soc_S_rtc_58004000_ORD_STR_SORTABLE 00242 +#define DT_N_S_soc_S_rtc_58004000_ORD 245 +#define DT_N_S_soc_S_rtc_58004000_ORD_STR_SORTABLE 00245 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rtc_58004000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ + 4, \ + 5, \ + 9, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rtc_58004000_SUPPORTS_ORDS \ - 243, /* /soc/rtc@58004000/backup_regs */ + 246, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_rtc_58004000_EXISTS 1 @@ -33201,8 +34077,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_rtc_58004000_REG_NUM 1 #define DT_N_S_soc_S_rtc_58004000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_REG_IDX_0_VAL_ADDRESS 1476411392 /* 0x58004000 */ -#define DT_N_S_soc_S_rtc_58004000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_rtc_58004000_REG_IDX_0_VAL_ADDRESS 1476411392 +#define DT_N_S_soc_S_rtc_58004000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_rtc_58004000_RANGES_NUM 0 #define DT_N_S_soc_S_rtc_58004000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_rtc_58004000_IRQ_NUM 1 @@ -33225,20 +34101,32 @@ #define DT_N_S_soc_S_rtc_58004000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_rtc_58004000_P_wakeup_source 0 -#define DT_N_S_soc_S_rtc_58004000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_rtc_58004000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_reg {1476411392, 1024} +#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_0 1476411392 +#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_rtc_58004000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_alarms_count 2 +#define DT_N_S_soc_S_rtc_58004000_P_alarms_count_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_alrm_exti_line 17 +#define DT_N_S_soc_S_rtc_58004000_P_alrm_exti_line_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_interrupts {41, 0} +#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_0 41 +#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_rtc_58004000_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_prescaler 32768 +#define DT_N_S_soc_S_rtc_58004000_P_prescaler_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_status "disabled" #define DT_N_S_soc_S_rtc_58004000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_rtc_58004000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_rtc_58004000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_rtc_58004000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_rtc_58004000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_rtc_58004000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_rtc_58004000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_rtc_58004000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_rtc_58004000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_58004000, status, 0) #define DT_N_S_soc_S_rtc_58004000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_58004000, status, 0) #define DT_N_S_soc_S_rtc_58004000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_58004000, status, 0, __VA_ARGS__) @@ -33246,29 +34134,17 @@ #define DT_N_S_soc_S_rtc_58004000_P_status_LEN 1 #define DT_N_S_soc_S_rtc_58004000_P_status_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_compatible {"st,stm32-rtc"} +#define DT_N_S_soc_S_rtc_58004000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_compatible_IDX_0 "st,stm32-rtc" #define DT_N_S_soc_S_rtc_58004000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-rtc #define DT_N_S_soc_S_rtc_58004000_P_compatible_IDX_0_STRING_TOKEN st_stm32_rtc #define DT_N_S_soc_S_rtc_58004000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_RTC -#define DT_N_S_soc_S_rtc_58004000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_58004000, compatible, 0) #define DT_N_S_soc_S_rtc_58004000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_58004000, compatible, 0) #define DT_N_S_soc_S_rtc_58004000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_58004000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_rtc_58004000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_rtc_58004000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_rtc_58004000_P_compatible_LEN 1 #define DT_N_S_soc_S_rtc_58004000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_reg {1476411392 /* 0x58004000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_0 1476411392 -#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_rtc_58004000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_interrupts {41 /* 0x29 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_0 41 -#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_rtc_58004000_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_rtc_58004000_P_clocks_IDX_0_VAL_bus 244 @@ -33283,12 +34159,10 @@ #define DT_N_S_soc_S_rtc_58004000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_rtc_58004000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_prescaler 32768 -#define DT_N_S_soc_S_rtc_58004000_P_prescaler_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_alarms_count 2 -#define DT_N_S_soc_S_rtc_58004000_P_alarms_count_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_P_alrm_exti_line 17 -#define DT_N_S_soc_S_rtc_58004000_P_alrm_exti_line_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_wakeup_source 0 +#define DT_N_S_soc_S_rtc_58004000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_rtc_58004000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/rtc@58004000/backup_regs @@ -33307,6 +34181,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_FULL_NAME "backup_regs" +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_FULL_NAME_UNQUOTED backup_regs +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_FULL_NAME_TOKEN backup_regs +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_FULL_NAME_UPPER_TOKEN BACKUP_REGS /* Node parent (/soc/rtc@58004000) identifier: */ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_PARENT DT_N_S_soc_S_rtc_58004000 @@ -33332,12 +34209,12 @@ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD 243 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD_STR_SORTABLE 00243 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD 246 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_ORD_STR_SORTABLE 00246 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_REQUIRES_ORDS \ - 242, /* /soc/rtc@58004000 */ + 245, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_SUPPORTS_ORDS /* nothing */ @@ -33364,20 +34241,16 @@ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_wakeup_source 0 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_st_backup_regs 32 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_st_backup_regs_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status "disabled" #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, status, 0) #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, status, 0) #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, status, 0, __VA_ARGS__) @@ -33385,11 +34258,11 @@ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_LEN 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_status_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible {"st,stm32-bbram"} +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_IDX_0 "st,stm32-bbram" #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-bbram #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_IDX_0_STRING_TOKEN st_stm32_bbram #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_BBRAM -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, compatible, 0) #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, compatible, 0) #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, compatible, 0, __VA_ARGS__) @@ -33398,8 +34271,10 @@ #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_compatible_EXISTS 1 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_st_backup_regs 32 -#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_st_backup_regs_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_wakeup_source 0 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_rtc_58004000_S_backup_regs_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/uart7_cts_pf9 @@ -33415,6 +34290,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_FULL_NAME "uart7_cts_pf9" +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_FULL_NAME_UNQUOTED uart7_cts_pf9 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_FULL_NAME_TOKEN uart7_cts_pf9 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_FULL_NAME_UPPER_TOKEN UART7_CTS_PF9 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -33440,16 +34318,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD 244 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD_STR_SORTABLE 00244 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD 247 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_ORD_STR_SORTABLE 00247 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_SUPPORTS_ORDS \ - 248, /* /soc/serial@40007800 */ + 251, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_EXISTS 1 @@ -33467,20 +34345,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_pinmux 2855 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate "low-speed" @@ -33489,16 +34353,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/uart7_rts_pf8 @@ -33514,6 +34390,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_FULL_NAME "uart7_rts_pf8" +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_FULL_NAME_UNQUOTED uart7_rts_pf8 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_FULL_NAME_TOKEN uart7_rts_pf8 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_FULL_NAME_UPPER_TOKEN UART7_RTS_PF8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -33539,16 +34418,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD 245 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD_STR_SORTABLE 00245 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD 248 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_ORD_STR_SORTABLE 00248 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_SUPPORTS_ORDS \ - 248, /* /soc/serial@40007800 */ + 251, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_EXISTS 1 @@ -33566,20 +34445,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_open_drain 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_pinmux 2823 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate "low-speed" @@ -33588,16 +34453,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_open_drain 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/uart7_rx_pa8 @@ -33613,6 +34490,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_FULL_NAME "uart7_rx_pa8" +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_FULL_NAME_UNQUOTED uart7_rx_pa8 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_FULL_NAME_TOKEN uart7_rx_pa8 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_FULL_NAME_UPPER_TOKEN UART7_RX_PA8 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -33638,16 +34518,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD 246 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD_STR_SORTABLE 00246 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD 249 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_ORD_STR_SORTABLE 00249 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_SUPPORTS_ORDS \ - 248, /* /soc/serial@40007800 */ + 251, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_EXISTS 1 @@ -33665,20 +34545,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_up 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_pinmux 267 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate "low-speed" @@ -33687,16 +34553,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_up 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8_P_output_high_EXISTS 1 /* * Devicetree node: /soc/pin-controller@58020000/uart7_tx_pf7 @@ -33712,6 +34590,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_FULL_NAME "uart7_tx_pf7" +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_FULL_NAME_UNQUOTED uart7_tx_pf7 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_FULL_NAME_TOKEN uart7_tx_pf7 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_FULL_NAME_UPPER_TOKEN UART7_TX_PF7 /* Node parent (/soc/pin-controller@58020000) identifier: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_PARENT DT_N_S_soc_S_pin_controller_58020000 @@ -33737,16 +34618,16 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD 247 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD_STR_SORTABLE 00247 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD 250 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_ORD_STR_SORTABLE 00250 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_REQUIRES_ORDS \ - 10, /* /soc/pin-controller@58020000 */ + 10, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_SUPPORTS_ORDS \ - 248, /* /soc/serial@40007800 */ + 251, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_EXISTS 1 @@ -33764,20 +34645,6 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_disable 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_disable_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_up 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_up_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_down 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_down_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_push_pull 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_push_pull_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_open_drain 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_open_drain_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_low 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_low_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_high 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_high_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_pinmux 2791 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_pinmux_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate "low-speed" @@ -33786,16 +34653,28 @@ #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_STRING_UPPER_TOKEN LOW_SPEED #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_IDX_0 "low-speed" #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_ENUM_IDX 0 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_ENUM_VAL_low_speed_EXISTS 1 -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_ENUM_TOKEN low_speed -#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_ENUM_UPPER_TOKEN LOW_SPEED +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_IDX_0_ENUM_IDX 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_IDX_0_ENUM_VAL_low_speed_EXISTS 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, slew_rate, 0) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, slew_rate, 0, __VA_ARGS__) #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_LEN 1 #define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_slew_rate_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_disable 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_disable_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_up 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_up_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_down 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_bias_pull_down_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_push_pull 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_push_pull_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_open_drain 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_drive_open_drain_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_low 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_low_EXISTS 1 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_high 0 +#define DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7_P_output_high_EXISTS 1 /* * Devicetree node: /soc/serial@40007800 @@ -33814,6 +34693,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40007800_FULL_NAME "serial@40007800" +#define DT_N_S_soc_S_serial_40007800_FULL_NAME_UNQUOTED serial@40007800 +#define DT_N_S_soc_S_serial_40007800_FULL_NAME_TOKEN serial_40007800 +#define DT_N_S_soc_S_serial_40007800_FULL_NAME_UPPER_TOKEN SERIAL_40007800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_serial_40007800_PARENT DT_N_S_soc @@ -33839,23 +34721,23 @@ #define DT_N_S_soc_S_serial_40007800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007800_ORD 248 -#define DT_N_S_soc_S_serial_40007800_ORD_STR_SORTABLE 00248 +#define DT_N_S_soc_S_serial_40007800_ORD 251 +#define DT_N_S_soc_S_serial_40007800_ORD_STR_SORTABLE 00251 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ \ - 244, /* /soc/pin-controller@58020000/uart7_cts_pf9 */ \ - 245, /* /soc/pin-controller@58020000/uart7_rts_pf8 */ \ - 246, /* /soc/pin-controller@58020000/uart7_rx_pa8 */ \ - 247, /* /soc/pin-controller@58020000/uart7_tx_pf7 */ + 4, \ + 5, \ + 9, \ + 54, \ + 247, \ + 248, \ + 249, \ + 250, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007800_SUPPORTS_ORDS \ - 249, /* /soc/serial@40007800/bt_hci_uart */ + 252, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40007800_EXISTS 1 @@ -33865,8 +34747,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_serial_40007800_REG_NUM 1 #define DT_N_S_soc_S_serial_40007800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_VAL_ADDRESS 1073772544 /* 0x40007800 */ -#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_VAL_ADDRESS 1073772544 +#define DT_N_S_soc_S_serial_40007800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_serial_40007800_RANGES_NUM 0 #define DT_N_S_soc_S_serial_40007800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_serial_40007800_IRQ_NUM 1 @@ -33898,50 +34780,12 @@ #define DT_N_S_soc_S_serial_40007800_PINCTRL_NAME_default_IDX_3_PH DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40007800_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40007800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40007800_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_status "okay" -#define DT_N_S_soc_S_serial_40007800_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_serial_40007800_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_serial_40007800_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_serial_40007800_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_serial_40007800_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, status, 0) -#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, status, 0) -#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40007800_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_compatible {"st,stm32-uart"} -#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0 "st,stm32-uart" -#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart -#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart -#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART -#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, compatible, 0) -#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, compatible, 0) -#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_P_compatible_LEN 1 -#define DT_N_S_soc_S_serial_40007800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_reg {1073772544 /* 0x40007800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_0 1073772544 +#define DT_N_S_soc_S_serial_40007800_P_reg {1073772544, 1024} #define DT_N_S_soc_S_serial_40007800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_0 1073772544 #define DT_N_S_soc_S_serial_40007800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_reg_IDX_1 1024 #define DT_N_S_soc_S_serial_40007800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_interrupts {82 /* 0x52 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_0 82 -#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_1 0 -#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 #define DT_N_S_soc_S_serial_40007800_P_clocks_IDX_0_VAL_bus 232 @@ -33954,12 +34798,26 @@ #define DT_N_S_soc_S_serial_40007800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, clocks, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40007800_P_clocks_LEN 1 #define DT_N_S_soc_S_serial_40007800_P_clocks_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40007800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_current_speed 115200 -#define DT_N_S_soc_S_serial_40007800_P_current_speed_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_hw_flow_control 1 -#define DT_N_S_soc_S_serial_40007800_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_VAL_id 4638 +#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, resets, 0) +#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, resets, 0) +#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_P_resets_LEN 1 +#define DT_N_S_soc_S_serial_40007800_P_resets_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_interrupts {82, 0} +#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_0 82 +#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_serial_40007800_P_interrupts_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_single_wire 0 +#define DT_N_S_soc_S_serial_40007800_P_single_wire_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_tx_rx_swap 0 +#define DT_N_S_soc_S_serial_40007800_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_0_IDX_0 DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_0_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_0_IDX_0_EXISTS 1 @@ -33991,35 +34849,17 @@ #define DT_N_S_soc_S_serial_40007800_P_pinctrl_0_LEN 4 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names {"default"} +#define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_IDX_0 "default" #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_IDX_0_STRING_UNQUOTED default #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_IDX_0_STRING_TOKEN default #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_IDX_0_STRING_UPPER_TOKEN DEFAULT -#define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, pinctrl_names, 0) #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, pinctrl_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_LEN 1 #define DT_N_S_soc_S_serial_40007800_P_pinctrl_names_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_VAL_id 4638 -#define DT_N_S_soc_S_serial_40007800_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, resets, 0) -#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, resets, 0) -#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_P_resets_LEN 1 -#define DT_N_S_soc_S_serial_40007800_P_resets_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_tx_invert 0 -#define DT_N_S_soc_S_serial_40007800_P_tx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_rx_invert 0 -#define DT_N_S_soc_S_serial_40007800_P_rx_invert_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_single_wire 0 -#define DT_N_S_soc_S_serial_40007800_P_single_wire_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_P_tx_rx_swap 0 -#define DT_N_S_soc_S_serial_40007800_P_tx_rx_swap_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_de_enable 0 #define DT_N_S_soc_S_serial_40007800_P_de_enable_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_de_assert_time 0 @@ -34030,6 +34870,46 @@ #define DT_N_S_soc_S_serial_40007800_P_de_invert_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_P_fifo_enable 0 #define DT_N_S_soc_S_serial_40007800_P_fifo_enable_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_current_speed 115200 +#define DT_N_S_soc_S_serial_40007800_P_current_speed_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_hw_flow_control 1 +#define DT_N_S_soc_S_serial_40007800_P_hw_flow_control_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_status "okay" +#define DT_N_S_soc_S_serial_40007800_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_serial_40007800_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_serial_40007800_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_serial_40007800_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, status, 0) +#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, status, 0) +#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40007800_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_compatible {"st,stm32-uart"} +#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0 "st,stm32-uart" +#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-uart +#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_TOKEN st_stm32_uart +#define DT_N_S_soc_S_serial_40007800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_UART +#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800, compatible, 0) +#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800, compatible, 0) +#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_P_compatible_LEN 1 +#define DT_N_S_soc_S_serial_40007800_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40007800_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40007800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40007800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_tx_invert 0 +#define DT_N_S_soc_S_serial_40007800_P_tx_invert_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_P_rx_invert 0 +#define DT_N_S_soc_S_serial_40007800_P_rx_invert_EXISTS 1 /* * Devicetree node: /soc/serial@40007800/bt_hci_uart @@ -34048,6 +34928,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_FULL_NAME "bt_hci_uart" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_FULL_NAME_UNQUOTED bt_hci_uart +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_FULL_NAME_TOKEN bt_hci_uart +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_FULL_NAME_UPPER_TOKEN BT_HCI_UART /* Node parent (/soc/serial@40007800) identifier: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_PARENT DT_N_S_soc_S_serial_40007800 @@ -34073,16 +34956,16 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD 249 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD_STR_SORTABLE 00249 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD 252 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_ORD_STR_SORTABLE 00252 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_REQUIRES_ORDS \ - 248, /* /soc/serial@40007800 */ + 251, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_SUPPORTS_ORDS \ - 250, /* /soc/serial@40007800/bt_hci_uart/murata-1dx */ + 253, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_EXISTS 1 @@ -34110,40 +34993,6 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status "okay" -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_STRING_UNQUOTED okay -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_STRING_TOKEN okay -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_STRING_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_IDX_0 "okay" -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_ENUM_UPPER_TOKEN OKAY -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_LEN 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible {"zephyr,bt-hci-uart"} -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0 "zephyr,bt-hci-uart" -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-uart -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_uart -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_UART -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_LEN 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_name "H:4" #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_name_STRING_UNQUOTED H:4 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_name_STRING_TOKEN H_4 @@ -34156,16 +35005,14 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_name_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, bt_hci_name, 0, __VA_ARGS__) #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_name_LEN 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_name_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus "BT_HCI_BUS_UART" -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_STRING_UNQUOTED BT_HCI_BUS_UART -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_STRING_TOKEN BT_HCI_BUS_UART -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_STRING_UPPER_TOKEN BT_HCI_BUS_UART -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_IDX_0 "BT_HCI_BUS_UART" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus "uart" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_STRING_UNQUOTED uart +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_STRING_TOKEN uart +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_STRING_UPPER_TOKEN UART +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_IDX_0 "uart" #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_ENUM_IDX 3 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_ENUM_VAL_BT_HCI_BUS_UART_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_ENUM_TOKEN BT_HCI_BUS_UART -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_ENUM_UPPER_TOKEN BT_HCI_BUS_UART +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_IDX_0_ENUM_IDX 3 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_IDX_0_ENUM_VAL_uart_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, bt_hci_bus, 0) #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, bt_hci_bus, 0) #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, bt_hci_bus, 0, __VA_ARGS__) @@ -34174,6 +35021,38 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_bus_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_vs_ext 0 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_bt_hci_vs_ext_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status "okay" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_STRING_UNQUOTED okay +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_STRING_TOKEN okay +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_STRING_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_IDX_0 "okay" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, status, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_LEN 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_status_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible {"zephyr,bt-hci-uart"} +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0 "zephyr,bt-hci-uart" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_STRING_UNQUOTED zephyr,bt-hci-uart +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_STRING_TOKEN zephyr_bt_hci_uart +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_IDX_0_STRING_UPPER_TOKEN ZEPHYR_BT_HCI_UART +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_LEN 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/serial@40007800/bt_hci_uart/murata-1dx @@ -34192,6 +35071,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_FULL_NAME "murata-1dx" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_FULL_NAME_UNQUOTED murata-1dx +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_FULL_NAME_TOKEN murata_1dx +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_FULL_NAME_UPPER_TOKEN MURATA_1DX /* Node parent (/soc/serial@40007800/bt_hci_uart) identifier: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_PARENT DT_N_S_soc_S_serial_40007800_S_bt_hci_uart @@ -34217,15 +35099,15 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD 250 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD_STR_SORTABLE 00250 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD 253 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_ORD_STR_SORTABLE 00253 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_REQUIRES_ORDS \ - 75, /* /soc/pin-controller@58020000/gpio@58020000 */ \ - 80, /* /soc/pin-controller@58020000/gpio@58021800 */ \ - 81, /* /soc/pin-controller@58020000/gpio@58021C00 */ \ - 249, /* /soc/serial@40007800/bt_hci_uart */ + 75, \ + 80, \ + 81, \ + 252, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_SUPPORTS_ORDS /* nothing */ @@ -34255,24 +35137,6 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_wakeup_source 0 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_pm_device_runtime_auto_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible {"infineon,cyw43xxx-bt-hci"} -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0 "infineon,cyw43xxx-bt-hci" -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_STRING_UNQUOTED infineon,cyw43xxx-bt-hci -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_STRING_TOKEN infineon_cyw43xxx_bt_hci -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_STRING_UPPER_TOKEN INFINEON_CYW43XXX_BT_HCI -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0, __VA_ARGS__) -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_LEN 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_deferred_init 0 -#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_deferred_init_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_bt_reg_on_gpios_IDX_0_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_bt_reg_on_gpios_IDX_0_PH DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_bt_reg_on_gpios_IDX_0_VAL_pin 10 @@ -34311,6 +35175,24 @@ #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_bt_host_wake_gpios_EXISTS 1 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_fw_download_speed 115200 #define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_fw_download_speed_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible {"infineon,cyw43xxx-bt-hci"} +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0 "infineon,cyw43xxx-bt-hci" +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_STRING_UNQUOTED infineon,cyw43xxx-bt-hci +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_STRING_TOKEN infineon_cyw43xxx_bt_hci +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_IDX_0_STRING_UPPER_TOKEN INFINEON_CYW43XXX_BT_HCI +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, compatible, 0, __VA_ARGS__) +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_LEN 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_compatible_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_deferred_init 0 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_wakeup_source 0 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000000 @@ -34329,6 +35211,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000000_FULL_NAME "timers@40000000" +#define DT_N_S_soc_S_timers_40000000_FULL_NAME_UNQUOTED timers@40000000 +#define DT_N_S_soc_S_timers_40000000_FULL_NAME_TOKEN timers_40000000 +#define DT_N_S_soc_S_timers_40000000_FULL_NAME_UPPER_TOKEN TIMERS_40000000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40000000_PARENT DT_N_S_soc @@ -34354,20 +35239,20 @@ #define DT_N_S_soc_S_timers_40000000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000000_ORD 251 -#define DT_N_S_soc_S_timers_40000000_ORD_STR_SORTABLE 00251 +#define DT_N_S_soc_S_timers_40000000_ORD 254 +#define DT_N_S_soc_S_timers_40000000_ORD_STR_SORTABLE 00254 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000000_SUPPORTS_ORDS \ - 252, /* /soc/timers@40000000/counter */ \ - 253, /* /soc/timers@40000000/pwm */ + 255, \ + 256, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000000_EXISTS 1 @@ -34377,8 +35262,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40000000_REG_NUM 1 #define DT_N_S_soc_S_timers_40000000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_ADDRESS 1073741824 /* 0x40000000 */ -#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_ADDRESS 1073741824 +#define DT_N_S_soc_S_timers_40000000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40000000_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40000000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40000000_IRQ_NUM 1 @@ -34406,20 +35291,46 @@ #define DT_N_S_soc_S_timers_40000000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000000_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_reg {1073741824, 1024} +#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0 1073741824 +#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40000000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits 1 +#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) +#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) +#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000000_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40000000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id 4608 +#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, resets, 0) +#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, resets, 0) +#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000000_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40000000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40000000_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40000000_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_status "disabled" #define DT_N_S_soc_S_timers_40000000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, status, 0) #define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, status, 0) #define DT_N_S_soc_S_timers_40000000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, status, 0, __VA_ARGS__) @@ -34427,69 +35338,41 @@ #define DT_N_S_soc_S_timers_40000000_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000000_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40000000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, compatible, 0) #define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, compatible, 0) #define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000000_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40000000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_reg {1073741824 /* 0x40000000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0 1073741824 -#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40000000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_interrupts {28 /* 0x1c */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0 28 +#define DT_N_S_soc_S_timers_40000000_P_interrupts {28, 0} #define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_0 28 #define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40000000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40000000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40000000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits 1 -#define DT_N_S_soc_S_timers_40000000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) -#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, clocks, 0) -#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000000_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40000000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id 4608 -#define DT_N_S_soc_S_timers_40000000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000, resets, 0) -#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000, resets, 0) -#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000000_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40000000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40000000_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40000000_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000000/counter @@ -34508,6 +35391,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40000000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40000000) identifier: */ #define DT_N_S_soc_S_timers_40000000_S_counter_PARENT DT_N_S_soc_S_timers_40000000 @@ -34533,12 +35419,12 @@ #define DT_N_S_soc_S_timers_40000000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000000_S_counter_ORD 252 -#define DT_N_S_soc_S_timers_40000000_S_counter_ORD_STR_SORTABLE 00252 +#define DT_N_S_soc_S_timers_40000000_S_counter_ORD 255 +#define DT_N_S_soc_S_timers_40000000_S_counter_ORD_STR_SORTABLE 00255 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000000_S_counter_REQUIRES_ORDS \ - 251, /* /soc/timers@40000000 */ + 254, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -34564,20 +35450,14 @@ #define DT_N_S_soc_S_timers_40000000_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, status, 0, __VA_ARGS__) @@ -34585,11 +35465,11 @@ #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_counter, compatible, 0, __VA_ARGS__) @@ -34598,6 +35478,10 @@ #define DT_N_S_soc_S_timers_40000000_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000000_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000000/pwm @@ -34616,6 +35500,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40000000_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40000000) identifier: */ #define DT_N_S_soc_S_timers_40000000_S_pwm_PARENT DT_N_S_soc_S_timers_40000000 @@ -34641,12 +35528,12 @@ #define DT_N_S_soc_S_timers_40000000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD 253 -#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD_STR_SORTABLE 00253 +#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD 256 +#define DT_N_S_soc_S_timers_40000000_S_pwm_ORD_STR_SORTABLE 00256 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000000_S_pwm_REQUIRES_ORDS \ - 251, /* /soc/timers@40000000 */ + 254, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000000_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -34672,20 +35559,16 @@ #define DT_N_S_soc_S_timers_40000000_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, status, 0, __VA_ARGS__) @@ -34693,11 +35576,11 @@ #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000000_S_pwm, compatible, 0, __VA_ARGS__) @@ -34706,8 +35589,10 @@ #define DT_N_S_soc_S_timers_40000000_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40000000_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000400 @@ -34726,6 +35611,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000400_FULL_NAME "timers@40000400" +#define DT_N_S_soc_S_timers_40000400_FULL_NAME_UNQUOTED timers@40000400 +#define DT_N_S_soc_S_timers_40000400_FULL_NAME_TOKEN timers_40000400 +#define DT_N_S_soc_S_timers_40000400_FULL_NAME_UPPER_TOKEN TIMERS_40000400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40000400_PARENT DT_N_S_soc @@ -34751,20 +35639,20 @@ #define DT_N_S_soc_S_timers_40000400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000400_ORD 254 -#define DT_N_S_soc_S_timers_40000400_ORD_STR_SORTABLE 00254 +#define DT_N_S_soc_S_timers_40000400_ORD 257 +#define DT_N_S_soc_S_timers_40000400_ORD_STR_SORTABLE 00257 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000400_SUPPORTS_ORDS \ - 255, /* /soc/timers@40000400/counter */ \ - 256, /* /soc/timers@40000400/pwm */ + 258, \ + 259, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000400_EXISTS 1 @@ -34774,8 +35662,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40000400_REG_NUM 1 #define DT_N_S_soc_S_timers_40000400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_ADDRESS 1073742848 /* 0x40000400 */ -#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_ADDRESS 1073742848 +#define DT_N_S_soc_S_timers_40000400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40000400_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40000400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40000400_IRQ_NUM 1 @@ -34803,20 +35691,46 @@ #define DT_N_S_soc_S_timers_40000400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000400_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_reg {1073742848, 1024} +#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0 1073742848 +#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40000400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits 2 +#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) +#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) +#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000400_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40000400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id 4609 +#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, resets, 0) +#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, resets, 0) +#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000400_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40000400_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40000400_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40000400_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_status "disabled" #define DT_N_S_soc_S_timers_40000400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, status, 0) #define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, status, 0) #define DT_N_S_soc_S_timers_40000400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, status, 0, __VA_ARGS__) @@ -34824,69 +35738,41 @@ #define DT_N_S_soc_S_timers_40000400_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000400_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40000400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, compatible, 0) #define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, compatible, 0) #define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000400_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40000400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_reg {1073742848 /* 0x40000400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0 1073742848 -#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40000400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_interrupts {29 /* 0x1d */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0 29 +#define DT_N_S_soc_S_timers_40000400_P_interrupts {29, 0} #define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_0 29 #define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40000400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40000400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40000400_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits 2 -#define DT_N_S_soc_S_timers_40000400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) -#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, clocks, 0) -#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000400_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40000400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id 4609 -#define DT_N_S_soc_S_timers_40000400_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400, resets, 0) -#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400, resets, 0) -#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000400_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40000400_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40000400_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40000400_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000400/counter @@ -34905,6 +35791,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40000400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40000400) identifier: */ #define DT_N_S_soc_S_timers_40000400_S_counter_PARENT DT_N_S_soc_S_timers_40000400 @@ -34930,12 +35819,12 @@ #define DT_N_S_soc_S_timers_40000400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000400_S_counter_ORD 255 -#define DT_N_S_soc_S_timers_40000400_S_counter_ORD_STR_SORTABLE 00255 +#define DT_N_S_soc_S_timers_40000400_S_counter_ORD 258 +#define DT_N_S_soc_S_timers_40000400_S_counter_ORD_STR_SORTABLE 00258 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000400_S_counter_REQUIRES_ORDS \ - 254, /* /soc/timers@40000400 */ + 257, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000400_S_counter_SUPPORTS_ORDS /* nothing */ @@ -34961,20 +35850,14 @@ #define DT_N_S_soc_S_timers_40000400_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, status, 0, __VA_ARGS__) @@ -34982,11 +35865,11 @@ #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_counter, compatible, 0, __VA_ARGS__) @@ -34995,6 +35878,10 @@ #define DT_N_S_soc_S_timers_40000400_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000400_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000400/pwm @@ -35013,6 +35900,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40000400_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40000400) identifier: */ #define DT_N_S_soc_S_timers_40000400_S_pwm_PARENT DT_N_S_soc_S_timers_40000400 @@ -35038,12 +35928,12 @@ #define DT_N_S_soc_S_timers_40000400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD 256 -#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD_STR_SORTABLE 00256 +#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD 259 +#define DT_N_S_soc_S_timers_40000400_S_pwm_ORD_STR_SORTABLE 00259 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000400_S_pwm_REQUIRES_ORDS \ - 254, /* /soc/timers@40000400 */ + 257, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000400_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -35069,20 +35959,16 @@ #define DT_N_S_soc_S_timers_40000400_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, status, 0, __VA_ARGS__) @@ -35090,11 +35976,11 @@ #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000400_S_pwm, compatible, 0, __VA_ARGS__) @@ -35103,8 +35989,10 @@ #define DT_N_S_soc_S_timers_40000400_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40000400_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000800 @@ -35123,6 +36011,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000800_FULL_NAME "timers@40000800" +#define DT_N_S_soc_S_timers_40000800_FULL_NAME_UNQUOTED timers@40000800 +#define DT_N_S_soc_S_timers_40000800_FULL_NAME_TOKEN timers_40000800 +#define DT_N_S_soc_S_timers_40000800_FULL_NAME_UPPER_TOKEN TIMERS_40000800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40000800_PARENT DT_N_S_soc @@ -35148,20 +36039,20 @@ #define DT_N_S_soc_S_timers_40000800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000800_ORD 257 -#define DT_N_S_soc_S_timers_40000800_ORD_STR_SORTABLE 00257 +#define DT_N_S_soc_S_timers_40000800_ORD 260 +#define DT_N_S_soc_S_timers_40000800_ORD_STR_SORTABLE 00260 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000800_SUPPORTS_ORDS \ - 258, /* /soc/timers@40000800/counter */ \ - 259, /* /soc/timers@40000800/pwm */ + 261, \ + 262, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000800_EXISTS 1 @@ -35171,8 +36062,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40000800_REG_NUM 1 #define DT_N_S_soc_S_timers_40000800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_ADDRESS 1073743872 /* 0x40000800 */ -#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_ADDRESS 1073743872 +#define DT_N_S_soc_S_timers_40000800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40000800_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40000800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40000800_IRQ_NUM 1 @@ -35200,20 +36091,46 @@ #define DT_N_S_soc_S_timers_40000800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000800_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_reg {1073743872, 1024} +#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0 1073743872 +#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40000800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits 4 +#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) +#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) +#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000800_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40000800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id 4610 +#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, resets, 0) +#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, resets, 0) +#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000800_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40000800_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40000800_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40000800_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_status "disabled" #define DT_N_S_soc_S_timers_40000800_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000800_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000800_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000800_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, status, 0) #define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, status, 0) #define DT_N_S_soc_S_timers_40000800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, status, 0, __VA_ARGS__) @@ -35221,69 +36138,41 @@ #define DT_N_S_soc_S_timers_40000800_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000800_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40000800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, compatible, 0) #define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, compatible, 0) #define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000800_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40000800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_reg {1073743872 /* 0x40000800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0 1073743872 -#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40000800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_interrupts {30 /* 0x1e */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0 30 +#define DT_N_S_soc_S_timers_40000800_P_interrupts {30, 0} #define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_0 30 #define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40000800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40000800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40000800_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits 4 -#define DT_N_S_soc_S_timers_40000800_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) -#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, clocks, 0) -#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000800_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40000800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id 4610 -#define DT_N_S_soc_S_timers_40000800_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800, resets, 0) -#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800, resets, 0) -#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000800_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40000800_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40000800_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40000800_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000800/counter @@ -35302,6 +36191,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40000800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40000800) identifier: */ #define DT_N_S_soc_S_timers_40000800_S_counter_PARENT DT_N_S_soc_S_timers_40000800 @@ -35327,12 +36219,12 @@ #define DT_N_S_soc_S_timers_40000800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000800_S_counter_ORD 258 -#define DT_N_S_soc_S_timers_40000800_S_counter_ORD_STR_SORTABLE 00258 +#define DT_N_S_soc_S_timers_40000800_S_counter_ORD 261 +#define DT_N_S_soc_S_timers_40000800_S_counter_ORD_STR_SORTABLE 00261 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000800_S_counter_REQUIRES_ORDS \ - 257, /* /soc/timers@40000800 */ + 260, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000800_S_counter_SUPPORTS_ORDS /* nothing */ @@ -35358,20 +36250,14 @@ #define DT_N_S_soc_S_timers_40000800_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, status, 0, __VA_ARGS__) @@ -35379,11 +36265,11 @@ #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_counter, compatible, 0, __VA_ARGS__) @@ -35392,6 +36278,10 @@ #define DT_N_S_soc_S_timers_40000800_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000800_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000800/pwm @@ -35410,6 +36300,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40000800_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40000800) identifier: */ #define DT_N_S_soc_S_timers_40000800_S_pwm_PARENT DT_N_S_soc_S_timers_40000800 @@ -35435,12 +36328,12 @@ #define DT_N_S_soc_S_timers_40000800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD 259 -#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD_STR_SORTABLE 00259 +#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD 262 +#define DT_N_S_soc_S_timers_40000800_S_pwm_ORD_STR_SORTABLE 00262 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000800_S_pwm_REQUIRES_ORDS \ - 257, /* /soc/timers@40000800 */ + 260, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000800_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -35466,20 +36359,16 @@ #define DT_N_S_soc_S_timers_40000800_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, status, 0, __VA_ARGS__) @@ -35487,11 +36376,11 @@ #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000800_S_pwm, compatible, 0, __VA_ARGS__) @@ -35500,8 +36389,10 @@ #define DT_N_S_soc_S_timers_40000800_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40000800_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000c00 @@ -35520,6 +36411,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000c00_FULL_NAME "timers@40000c00" +#define DT_N_S_soc_S_timers_40000c00_FULL_NAME_UNQUOTED timers@40000c00 +#define DT_N_S_soc_S_timers_40000c00_FULL_NAME_TOKEN timers_40000c00 +#define DT_N_S_soc_S_timers_40000c00_FULL_NAME_UPPER_TOKEN TIMERS_40000C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40000c00_PARENT DT_N_S_soc @@ -35545,20 +36439,20 @@ #define DT_N_S_soc_S_timers_40000c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000c00_ORD 260 -#define DT_N_S_soc_S_timers_40000c00_ORD_STR_SORTABLE 00260 +#define DT_N_S_soc_S_timers_40000c00_ORD 263 +#define DT_N_S_soc_S_timers_40000c00_ORD_STR_SORTABLE 00263 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000c00_SUPPORTS_ORDS \ - 261, /* /soc/timers@40000c00/counter */ \ - 262, /* /soc/timers@40000c00/pwm */ + 264, \ + 265, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40000c00_EXISTS 1 @@ -35568,8 +36462,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40000c00_REG_NUM 1 #define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_VAL_ADDRESS 1073744896 /* 0x40000c00 */ -#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_VAL_ADDRESS 1073744896 +#define DT_N_S_soc_S_timers_40000c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40000c00_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40000c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40000c00_IRQ_NUM 1 @@ -35597,20 +36491,46 @@ #define DT_N_S_soc_S_timers_40000c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000c00_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_reg {1073744896, 1024} +#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_0 1073744896 +#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40000c00_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bits 8 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0) +#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0) +#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000c00_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40000c00_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_VAL_id 4611 +#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, resets, 0) +#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, resets, 0) +#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40000c00_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40000c00_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40000c00_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40000c00_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_status "disabled" #define DT_N_S_soc_S_timers_40000c00_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000c00_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000c00_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000c00_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, status, 0) #define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, status, 0) #define DT_N_S_soc_S_timers_40000c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, status, 0, __VA_ARGS__) @@ -35618,69 +36538,41 @@ #define DT_N_S_soc_S_timers_40000c00_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000c00_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40000c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0) #define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0) #define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000c00_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40000c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_reg {1073744896 /* 0x40000c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_0 1073744896 -#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40000c00_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_interrupts {50 /* 0x32 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_0 50 +#define DT_N_S_soc_S_timers_40000c00_P_interrupts {50, 0} #define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_0 50 #define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40000c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0) #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40000c00_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bits 8 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0) -#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0) -#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000c00_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40000c00_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_VAL_id 4611 -#define DT_N_S_soc_S_timers_40000c00_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00, resets, 0) -#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00, resets, 0) -#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40000c00, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40000c00_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40000c00_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40000c00_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40000c00_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000c00/counter @@ -35699,6 +36591,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40000c00_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40000c00) identifier: */ #define DT_N_S_soc_S_timers_40000c00_S_counter_PARENT DT_N_S_soc_S_timers_40000c00 @@ -35724,12 +36619,12 @@ #define DT_N_S_soc_S_timers_40000c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD 261 -#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD_STR_SORTABLE 00261 +#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD 264 +#define DT_N_S_soc_S_timers_40000c00_S_counter_ORD_STR_SORTABLE 00264 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000c00_S_counter_REQUIRES_ORDS \ - 260, /* /soc/timers@40000c00 */ + 263, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000c00_S_counter_SUPPORTS_ORDS /* nothing */ @@ -35755,20 +36650,14 @@ #define DT_N_S_soc_S_timers_40000c00_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0) #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_counter, status, 0, __VA_ARGS__) @@ -35776,11 +36665,11 @@ #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_counter, compatible, 0, __VA_ARGS__) @@ -35789,6 +36678,10 @@ #define DT_N_S_soc_S_timers_40000c00_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40000c00/pwm @@ -35807,6 +36700,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40000c00_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40000c00) identifier: */ #define DT_N_S_soc_S_timers_40000c00_S_pwm_PARENT DT_N_S_soc_S_timers_40000c00 @@ -35832,12 +36728,12 @@ #define DT_N_S_soc_S_timers_40000c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD 262 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD_STR_SORTABLE 00262 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD 265 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_ORD_STR_SORTABLE 00265 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40000c00_S_pwm_REQUIRES_ORDS \ - 260, /* /soc/timers@40000c00 */ + 263, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40000c00_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -35863,20 +36759,16 @@ #define DT_N_S_soc_S_timers_40000c00_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, status, 0, __VA_ARGS__) @@ -35884,11 +36776,11 @@ #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, compatible, 0, __VA_ARGS__) @@ -35897,8 +36789,10 @@ #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40000c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001000 @@ -35917,6 +36811,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001000_FULL_NAME "timers@40001000" +#define DT_N_S_soc_S_timers_40001000_FULL_NAME_UNQUOTED timers@40001000 +#define DT_N_S_soc_S_timers_40001000_FULL_NAME_TOKEN timers_40001000 +#define DT_N_S_soc_S_timers_40001000_FULL_NAME_UPPER_TOKEN TIMERS_40001000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40001000_PARENT DT_N_S_soc @@ -35942,19 +36839,19 @@ #define DT_N_S_soc_S_timers_40001000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001000_ORD 263 -#define DT_N_S_soc_S_timers_40001000_ORD_STR_SORTABLE 00263 +#define DT_N_S_soc_S_timers_40001000_ORD 266 +#define DT_N_S_soc_S_timers_40001000_ORD_STR_SORTABLE 00266 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001000_SUPPORTS_ORDS \ - 264, /* /soc/timers@40001000/counter */ + 267, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001000_EXISTS 1 @@ -35964,8 +36861,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40001000_REG_NUM 1 #define DT_N_S_soc_S_timers_40001000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_ADDRESS 1073745920 /* 0x40001000 */ -#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_ADDRESS 1073745920 +#define DT_N_S_soc_S_timers_40001000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40001000_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40001000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40001000_IRQ_NUM 1 @@ -35993,20 +36890,46 @@ #define DT_N_S_soc_S_timers_40001000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001000_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_reg {1073745920, 1024} +#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0 1073745920 +#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40001000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits 16 +#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) +#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) +#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001000_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40001000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id 4612 +#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, resets, 0) +#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, resets, 0) +#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001000_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40001000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40001000_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40001000_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_status "disabled" #define DT_N_S_soc_S_timers_40001000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, status, 0) #define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, status, 0) #define DT_N_S_soc_S_timers_40001000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, status, 0, __VA_ARGS__) @@ -36014,69 +36937,41 @@ #define DT_N_S_soc_S_timers_40001000_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001000_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40001000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, compatible, 0) #define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, compatible, 0) #define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001000_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40001000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_reg {1073745920 /* 0x40001000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0 1073745920 -#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40001000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_interrupts {54 /* 0x36 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0 54 +#define DT_N_S_soc_S_timers_40001000_P_interrupts {54, 0} #define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_0 54 #define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40001000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40001000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40001000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits 16 -#define DT_N_S_soc_S_timers_40001000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) -#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, clocks, 0) -#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001000_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40001000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id 4612 -#define DT_N_S_soc_S_timers_40001000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000, resets, 0) -#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000, resets, 0) -#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001000_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40001000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40001000_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40001000_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001000/counter @@ -36095,6 +36990,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40001000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40001000) identifier: */ #define DT_N_S_soc_S_timers_40001000_S_counter_PARENT DT_N_S_soc_S_timers_40001000 @@ -36120,12 +37018,12 @@ #define DT_N_S_soc_S_timers_40001000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001000_S_counter_ORD 264 -#define DT_N_S_soc_S_timers_40001000_S_counter_ORD_STR_SORTABLE 00264 +#define DT_N_S_soc_S_timers_40001000_S_counter_ORD 267 +#define DT_N_S_soc_S_timers_40001000_S_counter_ORD_STR_SORTABLE 00267 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001000_S_counter_REQUIRES_ORDS \ - 263, /* /soc/timers@40001000 */ + 266, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -36151,20 +37049,14 @@ #define DT_N_S_soc_S_timers_40001000_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, status, 0, __VA_ARGS__) @@ -36172,11 +37064,11 @@ #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001000_S_counter, compatible, 0, __VA_ARGS__) @@ -36185,6 +37077,10 @@ #define DT_N_S_soc_S_timers_40001000_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001000_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001400 @@ -36203,6 +37099,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001400_FULL_NAME "timers@40001400" +#define DT_N_S_soc_S_timers_40001400_FULL_NAME_UNQUOTED timers@40001400 +#define DT_N_S_soc_S_timers_40001400_FULL_NAME_TOKEN timers_40001400 +#define DT_N_S_soc_S_timers_40001400_FULL_NAME_UPPER_TOKEN TIMERS_40001400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40001400_PARENT DT_N_S_soc @@ -36228,19 +37127,19 @@ #define DT_N_S_soc_S_timers_40001400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001400_ORD 265 -#define DT_N_S_soc_S_timers_40001400_ORD_STR_SORTABLE 00265 +#define DT_N_S_soc_S_timers_40001400_ORD 268 +#define DT_N_S_soc_S_timers_40001400_ORD_STR_SORTABLE 00268 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001400_SUPPORTS_ORDS \ - 266, /* /soc/timers@40001400/counter */ + 269, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001400_EXISTS 1 @@ -36250,8 +37149,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40001400_REG_NUM 1 #define DT_N_S_soc_S_timers_40001400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_ADDRESS 1073746944 /* 0x40001400 */ -#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_ADDRESS 1073746944 +#define DT_N_S_soc_S_timers_40001400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40001400_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40001400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40001400_IRQ_NUM 1 @@ -36279,20 +37178,46 @@ #define DT_N_S_soc_S_timers_40001400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001400_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_reg {1073746944, 1024} +#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0 1073746944 +#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40001400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits 32 +#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) +#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) +#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001400_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40001400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id 4613 +#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, resets, 0) +#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, resets, 0) +#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001400_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40001400_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40001400_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40001400_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_status "disabled" #define DT_N_S_soc_S_timers_40001400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, status, 0) #define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, status, 0) #define DT_N_S_soc_S_timers_40001400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, status, 0, __VA_ARGS__) @@ -36300,69 +37225,41 @@ #define DT_N_S_soc_S_timers_40001400_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001400_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40001400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, compatible, 0) #define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, compatible, 0) #define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001400_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40001400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_reg {1073746944 /* 0x40001400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0 1073746944 -#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40001400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_interrupts {55 /* 0x37 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0 55 +#define DT_N_S_soc_S_timers_40001400_P_interrupts {55, 0} #define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_0 55 #define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40001400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40001400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40001400_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits 32 -#define DT_N_S_soc_S_timers_40001400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) -#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, clocks, 0) -#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001400_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40001400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id 4613 -#define DT_N_S_soc_S_timers_40001400_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400, resets, 0) -#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400, resets, 0) -#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001400_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40001400_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40001400_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40001400_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001400/counter @@ -36381,6 +37278,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40001400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40001400) identifier: */ #define DT_N_S_soc_S_timers_40001400_S_counter_PARENT DT_N_S_soc_S_timers_40001400 @@ -36406,12 +37306,12 @@ #define DT_N_S_soc_S_timers_40001400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001400_S_counter_ORD 266 -#define DT_N_S_soc_S_timers_40001400_S_counter_ORD_STR_SORTABLE 00266 +#define DT_N_S_soc_S_timers_40001400_S_counter_ORD 269 +#define DT_N_S_soc_S_timers_40001400_S_counter_ORD_STR_SORTABLE 00269 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001400_S_counter_REQUIRES_ORDS \ - 265, /* /soc/timers@40001400 */ + 268, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001400_S_counter_SUPPORTS_ORDS /* nothing */ @@ -36437,20 +37337,14 @@ #define DT_N_S_soc_S_timers_40001400_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, status, 0, __VA_ARGS__) @@ -36458,11 +37352,11 @@ #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001400_S_counter, compatible, 0, __VA_ARGS__) @@ -36471,6 +37365,10 @@ #define DT_N_S_soc_S_timers_40001400_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001400_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001800 @@ -36489,6 +37387,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001800_FULL_NAME "timers@40001800" +#define DT_N_S_soc_S_timers_40001800_FULL_NAME_UNQUOTED timers@40001800 +#define DT_N_S_soc_S_timers_40001800_FULL_NAME_TOKEN timers_40001800 +#define DT_N_S_soc_S_timers_40001800_FULL_NAME_UPPER_TOKEN TIMERS_40001800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40001800_PARENT DT_N_S_soc @@ -36514,20 +37415,20 @@ #define DT_N_S_soc_S_timers_40001800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001800_ORD 267 -#define DT_N_S_soc_S_timers_40001800_ORD_STR_SORTABLE 00267 +#define DT_N_S_soc_S_timers_40001800_ORD 270 +#define DT_N_S_soc_S_timers_40001800_ORD_STR_SORTABLE 00270 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001800_SUPPORTS_ORDS \ - 268, /* /soc/timers@40001800/counter */ \ - 269, /* /soc/timers@40001800/pwm */ + 271, \ + 272, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001800_EXISTS 1 @@ -36537,8 +37438,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40001800_REG_NUM 1 #define DT_N_S_soc_S_timers_40001800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_VAL_ADDRESS 1073747968 /* 0x40001800 */ -#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_VAL_ADDRESS 1073747968 +#define DT_N_S_soc_S_timers_40001800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40001800_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40001800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40001800_IRQ_NUM 1 @@ -36566,20 +37467,46 @@ #define DT_N_S_soc_S_timers_40001800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001800_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_reg {1073747968, 1024} +#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_0 1073747968 +#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40001800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bits 64 +#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, clocks, 0) +#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, clocks, 0) +#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001800_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40001800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_VAL_id 4614 +#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, resets, 0) +#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, resets, 0) +#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001800_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40001800_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40001800_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40001800_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_status "disabled" #define DT_N_S_soc_S_timers_40001800_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001800_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001800_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001800_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, status, 0) #define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, status, 0) #define DT_N_S_soc_S_timers_40001800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, status, 0, __VA_ARGS__) @@ -36587,69 +37514,41 @@ #define DT_N_S_soc_S_timers_40001800_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001800_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40001800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, compatible, 0) #define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, compatible, 0) #define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001800_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40001800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_reg {1073747968 /* 0x40001800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_0 1073747968 -#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40001800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_interrupts {43 /* 0x2b */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_0 43 +#define DT_N_S_soc_S_timers_40001800_P_interrupts {43, 0} #define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_0 43 #define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40001800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40001800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40001800_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bits 64 -#define DT_N_S_soc_S_timers_40001800_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, clocks, 0) -#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, clocks, 0) -#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001800_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40001800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_VAL_id 4614 -#define DT_N_S_soc_S_timers_40001800_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800, resets, 0) -#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800, resets, 0) -#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001800_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40001800_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40001800_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40001800_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001800/counter @@ -36668,6 +37567,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40001800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40001800) identifier: */ #define DT_N_S_soc_S_timers_40001800_S_counter_PARENT DT_N_S_soc_S_timers_40001800 @@ -36693,12 +37595,12 @@ #define DT_N_S_soc_S_timers_40001800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001800_S_counter_ORD 268 -#define DT_N_S_soc_S_timers_40001800_S_counter_ORD_STR_SORTABLE 00268 +#define DT_N_S_soc_S_timers_40001800_S_counter_ORD 271 +#define DT_N_S_soc_S_timers_40001800_S_counter_ORD_STR_SORTABLE 00271 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001800_S_counter_REQUIRES_ORDS \ - 267, /* /soc/timers@40001800 */ + 270, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001800_S_counter_SUPPORTS_ORDS /* nothing */ @@ -36724,20 +37626,14 @@ #define DT_N_S_soc_S_timers_40001800_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001800_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001800_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_counter, status, 0, __VA_ARGS__) @@ -36745,11 +37641,11 @@ #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_counter, compatible, 0, __VA_ARGS__) @@ -36758,6 +37654,10 @@ #define DT_N_S_soc_S_timers_40001800_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001800_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001800/pwm @@ -36776,6 +37676,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40001800_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40001800) identifier: */ #define DT_N_S_soc_S_timers_40001800_S_pwm_PARENT DT_N_S_soc_S_timers_40001800 @@ -36801,12 +37704,12 @@ #define DT_N_S_soc_S_timers_40001800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD 269 -#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD_STR_SORTABLE 00269 +#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD 272 +#define DT_N_S_soc_S_timers_40001800_S_pwm_ORD_STR_SORTABLE 00272 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001800_S_pwm_REQUIRES_ORDS \ - 267, /* /soc/timers@40001800 */ + 270, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001800_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -36832,20 +37735,16 @@ #define DT_N_S_soc_S_timers_40001800_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, status, 0, __VA_ARGS__) @@ -36853,11 +37752,11 @@ #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001800_S_pwm, compatible, 0, __VA_ARGS__) @@ -36866,8 +37765,10 @@ #define DT_N_S_soc_S_timers_40001800_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40001800_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001c00 @@ -36886,6 +37787,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001c00_FULL_NAME "timers@40001c00" +#define DT_N_S_soc_S_timers_40001c00_FULL_NAME_UNQUOTED timers@40001c00 +#define DT_N_S_soc_S_timers_40001c00_FULL_NAME_TOKEN timers_40001c00 +#define DT_N_S_soc_S_timers_40001c00_FULL_NAME_UPPER_TOKEN TIMERS_40001C00 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40001c00_PARENT DT_N_S_soc @@ -36911,20 +37815,20 @@ #define DT_N_S_soc_S_timers_40001c00_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001c00_ORD 270 -#define DT_N_S_soc_S_timers_40001c00_ORD_STR_SORTABLE 00270 +#define DT_N_S_soc_S_timers_40001c00_ORD 273 +#define DT_N_S_soc_S_timers_40001c00_ORD_STR_SORTABLE 00273 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001c00_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001c00_SUPPORTS_ORDS \ - 271, /* /soc/timers@40001c00/counter */ \ - 272, /* /soc/timers@40001c00/pwm */ + 274, \ + 275, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40001c00_EXISTS 1 @@ -36934,8 +37838,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40001c00_REG_NUM 1 #define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_VAL_ADDRESS 1073748992 /* 0x40001c00 */ -#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_VAL_ADDRESS 1073748992 +#define DT_N_S_soc_S_timers_40001c00_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40001c00_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40001c00_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40001c00_IRQ_NUM 1 @@ -36963,20 +37867,46 @@ #define DT_N_S_soc_S_timers_40001c00_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001c00_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001c00_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_reg {1073748992, 1024} +#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_0 1073748992 +#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40001c00_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bits 128 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0) +#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0) +#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001c00_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40001c00_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_VAL_id 4615 +#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, resets, 0) +#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, resets, 0) +#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40001c00_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40001c00_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40001c00_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40001c00_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_status "disabled" #define DT_N_S_soc_S_timers_40001c00_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001c00_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001c00_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001c00_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001c00_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001c00_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, status, 0) #define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, status, 0) #define DT_N_S_soc_S_timers_40001c00_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, status, 0, __VA_ARGS__) @@ -36984,69 +37914,41 @@ #define DT_N_S_soc_S_timers_40001c00_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001c00_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40001c00_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0) #define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0) #define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001c00_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001c00_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40001c00_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_reg {1073748992 /* 0x40001c00 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_0 1073748992 -#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40001c00_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_interrupts {44 /* 0x2c */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_0 44 +#define DT_N_S_soc_S_timers_40001c00_P_interrupts {44, 0} #define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_0 44 #define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40001c00_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0) #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40001c00_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bits 128 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0) -#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0) -#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001c00_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001c00_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40001c00_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001c00_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_VAL_id 4615 -#define DT_N_S_soc_S_timers_40001c00_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00, resets, 0) -#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00, resets, 0) -#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001c00_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40001c00, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40001c00_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40001c00_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40001c00_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40001c00_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001c00_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001c00_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001c00/counter @@ -37065,6 +37967,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40001c00_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40001c00) identifier: */ #define DT_N_S_soc_S_timers_40001c00_S_counter_PARENT DT_N_S_soc_S_timers_40001c00 @@ -37090,12 +37995,12 @@ #define DT_N_S_soc_S_timers_40001c00_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD 271 -#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD_STR_SORTABLE 00271 +#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD 274 +#define DT_N_S_soc_S_timers_40001c00_S_counter_ORD_STR_SORTABLE 00274 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001c00_S_counter_REQUIRES_ORDS \ - 270, /* /soc/timers@40001c00 */ + 273, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001c00_S_counter_SUPPORTS_ORDS /* nothing */ @@ -37121,20 +38026,14 @@ #define DT_N_S_soc_S_timers_40001c00_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0) #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_counter, status, 0, __VA_ARGS__) @@ -37142,11 +38041,11 @@ #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_counter, compatible, 0, __VA_ARGS__) @@ -37155,6 +38054,10 @@ #define DT_N_S_soc_S_timers_40001c00_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001c00_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40001c00/pwm @@ -37173,6 +38076,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40001c00_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40001c00) identifier: */ #define DT_N_S_soc_S_timers_40001c00_S_pwm_PARENT DT_N_S_soc_S_timers_40001c00 @@ -37198,12 +38104,12 @@ #define DT_N_S_soc_S_timers_40001c00_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD 272 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD_STR_SORTABLE 00272 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD 275 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_ORD_STR_SORTABLE 00275 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40001c00_S_pwm_REQUIRES_ORDS \ - 270, /* /soc/timers@40001c00 */ + 273, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40001c00_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -37229,20 +38135,16 @@ #define DT_N_S_soc_S_timers_40001c00_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, status, 0, __VA_ARGS__) @@ -37250,11 +38152,11 @@ #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, compatible, 0, __VA_ARGS__) @@ -37263,8 +38165,10 @@ #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40001c00_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40002000 @@ -37283,6 +38187,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40002000_FULL_NAME "timers@40002000" +#define DT_N_S_soc_S_timers_40002000_FULL_NAME_UNQUOTED timers@40002000 +#define DT_N_S_soc_S_timers_40002000_FULL_NAME_TOKEN timers_40002000 +#define DT_N_S_soc_S_timers_40002000_FULL_NAME_UPPER_TOKEN TIMERS_40002000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40002000_PARENT DT_N_S_soc @@ -37308,20 +38215,20 @@ #define DT_N_S_soc_S_timers_40002000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002000_ORD 273 -#define DT_N_S_soc_S_timers_40002000_ORD_STR_SORTABLE 00273 +#define DT_N_S_soc_S_timers_40002000_ORD 276 +#define DT_N_S_soc_S_timers_40002000_ORD_STR_SORTABLE 00276 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002000_SUPPORTS_ORDS \ - 274, /* /soc/timers@40002000/counter */ \ - 275, /* /soc/timers@40002000/pwm */ + 277, \ + 278, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40002000_EXISTS 1 @@ -37331,8 +38238,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40002000_REG_NUM 1 #define DT_N_S_soc_S_timers_40002000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_VAL_ADDRESS 1073750016 /* 0x40002000 */ -#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_VAL_ADDRESS 1073750016 +#define DT_N_S_soc_S_timers_40002000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40002000_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40002000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40002000_IRQ_NUM 1 @@ -37360,20 +38267,46 @@ #define DT_N_S_soc_S_timers_40002000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40002000_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40002000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40002000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_reg {1073750016, 1024} +#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_0 1073750016 +#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40002000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bus 232 +#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bits 256 +#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, clocks, 0) +#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, clocks, 0) +#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40002000_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40002000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_VAL_id 4616 +#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, resets, 0) +#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, resets, 0) +#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40002000_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40002000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40002000_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40002000_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_status "disabled" #define DT_N_S_soc_S_timers_40002000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40002000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40002000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40002000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40002000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40002000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40002000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40002000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40002000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, status, 0) #define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, status, 0) #define DT_N_S_soc_S_timers_40002000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, status, 0, __VA_ARGS__) @@ -37381,69 +38314,41 @@ #define DT_N_S_soc_S_timers_40002000_P_status_LEN 1 #define DT_N_S_soc_S_timers_40002000_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40002000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, compatible, 0) #define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, compatible, 0) #define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002000_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40002000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_reg {1073750016 /* 0x40002000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_0 1073750016 -#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40002000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_interrupts {45 /* 0x2d */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_0 45 +#define DT_N_S_soc_S_timers_40002000_P_interrupts {45, 0} #define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_0 45 #define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40002000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40002000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40002000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bus 232 -#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bits 256 -#define DT_N_S_soc_S_timers_40002000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, clocks, 0) -#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, clocks, 0) -#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40002000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40002000_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40002000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40002000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_VAL_id 4616 -#define DT_N_S_soc_S_timers_40002000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000, resets, 0) -#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000, resets, 0) -#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40002000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40002000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40002000_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40002000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40002000_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40002000_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40002000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40002000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40002000/counter @@ -37462,6 +38367,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40002000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40002000) identifier: */ #define DT_N_S_soc_S_timers_40002000_S_counter_PARENT DT_N_S_soc_S_timers_40002000 @@ -37487,12 +38395,12 @@ #define DT_N_S_soc_S_timers_40002000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002000_S_counter_ORD 274 -#define DT_N_S_soc_S_timers_40002000_S_counter_ORD_STR_SORTABLE 00274 +#define DT_N_S_soc_S_timers_40002000_S_counter_ORD 277 +#define DT_N_S_soc_S_timers_40002000_S_counter_ORD_STR_SORTABLE 00277 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002000_S_counter_REQUIRES_ORDS \ - 273, /* /soc/timers@40002000 */ + 276, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -37518,20 +38426,14 @@ #define DT_N_S_soc_S_timers_40002000_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40002000_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40002000_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40002000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_counter, status, 0, __VA_ARGS__) @@ -37539,11 +38441,11 @@ #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_counter, compatible, 0, __VA_ARGS__) @@ -37552,6 +38454,10 @@ #define DT_N_S_soc_S_timers_40002000_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40002000_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40002000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40002000/pwm @@ -37570,6 +38476,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40002000_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40002000) identifier: */ #define DT_N_S_soc_S_timers_40002000_S_pwm_PARENT DT_N_S_soc_S_timers_40002000 @@ -37595,12 +38504,12 @@ #define DT_N_S_soc_S_timers_40002000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD 275 -#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD_STR_SORTABLE 00275 +#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD 278 +#define DT_N_S_soc_S_timers_40002000_S_pwm_ORD_STR_SORTABLE 00278 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40002000_S_pwm_REQUIRES_ORDS \ - 273, /* /soc/timers@40002000 */ + 276, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40002000_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -37626,20 +38535,16 @@ #define DT_N_S_soc_S_timers_40002000_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, status, 0, __VA_ARGS__) @@ -37647,11 +38552,11 @@ #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40002000_S_pwm, compatible, 0, __VA_ARGS__) @@ -37660,8 +38565,10 @@ #define DT_N_S_soc_S_timers_40002000_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40002000_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40002000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40010000/pwm/pwmclock @@ -37680,6 +38587,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FULL_NAME "pwmclock" +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FULL_NAME_UNQUOTED pwmclock +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FULL_NAME_TOKEN pwmclock +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FULL_NAME_UPPER_TOKEN PWMCLOCK /* Node parent (/soc/timers@40010000/pwm) identifier: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_PARENT DT_N_S_soc_S_timers_40010000_S_pwm @@ -37705,12 +38615,12 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_ORD 276 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_ORD_STR_SORTABLE 00276 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_ORD 279 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_ORD_STR_SORTABLE 00279 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_REQUIRES_ORDS \ - 87, /* /soc/timers@40010000/pwm */ + 87, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_SUPPORTS_ORDS /* nothing */ @@ -37733,20 +38643,32 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_PH DT_N_S_soc_S_timers_40010000_S_pwm +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_channel 3 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_channel_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_period 166 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_period_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_flags 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_flags_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_LEN 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_clock_frequency 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_clock_frequency_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwm_on_delay 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwm_on_delay_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status "okay" #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_STRING_UNQUOTED okay #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_STRING_TOKEN okay #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_STRING_UPPER_TOKEN OKAY #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_IDX_0 "okay" #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_IDX 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_VAL_okay_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_TOKEN okay -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_ENUM_UPPER_TOKEN OKAY +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_IDX_0_ENUM_IDX 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_IDX_0_ENUM_VAL_okay_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, status, 0, __VA_ARGS__) @@ -37754,11 +38676,11 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_LEN 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible {"pwm-clock"} +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0 "pwm-clock" #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_STRING_UNQUOTED pwm-clock #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_STRING_TOKEN pwm_clock #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_STRING_UPPER_TOKEN PWM_CLOCK -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0) #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, compatible, 0, __VA_ARGS__) @@ -37767,24 +38689,10 @@ #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_PH DT_N_S_soc_S_timers_40010000_S_pwm -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_channel 3 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_channel_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_period 166 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_period_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_flags 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_IDX_0_VAL_flags_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0) -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, pwms, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_LEN 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwms_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_clock_frequency 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_clock_frequency_EXISTS 1 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwm_on_delay 0 -#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_pwm_on_delay_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40010400 @@ -37803,6 +38711,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40010400_FULL_NAME "timers@40010400" +#define DT_N_S_soc_S_timers_40010400_FULL_NAME_UNQUOTED timers@40010400 +#define DT_N_S_soc_S_timers_40010400_FULL_NAME_TOKEN timers_40010400 +#define DT_N_S_soc_S_timers_40010400_FULL_NAME_UPPER_TOKEN TIMERS_40010400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40010400_PARENT DT_N_S_soc @@ -37828,19 +38739,19 @@ #define DT_N_S_soc_S_timers_40010400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010400_ORD 277 -#define DT_N_S_soc_S_timers_40010400_ORD_STR_SORTABLE 00277 +#define DT_N_S_soc_S_timers_40010400_ORD 280 +#define DT_N_S_soc_S_timers_40010400_ORD_STR_SORTABLE 00280 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010400_SUPPORTS_ORDS \ - 278, /* /soc/timers@40010400/pwm */ + 281, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40010400_EXISTS 1 @@ -37850,8 +38761,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40010400_REG_NUM 1 #define DT_N_S_soc_S_timers_40010400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_VAL_ADDRESS 1073808384 /* 0x40010400 */ -#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_VAL_ADDRESS 1073808384 +#define DT_N_S_soc_S_timers_40010400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40010400_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40010400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40010400_IRQ_NUM 4 @@ -37915,20 +38826,46 @@ #define DT_N_S_soc_S_timers_40010400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010400_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_reg {1073808384, 1024} +#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_0 1073808384 +#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40010400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bits 2 +#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, clocks, 0) +#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, clocks, 0) +#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010400_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40010400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_VAL_id 4865 +#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, resets, 0) +#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, resets, 0) +#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40010400_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40010400_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40010400_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40010400_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_status "disabled" #define DT_N_S_soc_S_timers_40010400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40010400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40010400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40010400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40010400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40010400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40010400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40010400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40010400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, status, 0) #define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, status, 0) #define DT_N_S_soc_S_timers_40010400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, status, 0, __VA_ARGS__) @@ -37936,62 +38873,56 @@ #define DT_N_S_soc_S_timers_40010400_P_status_LEN 1 #define DT_N_S_soc_S_timers_40010400_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40010400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, compatible, 0) #define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, compatible, 0) #define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40010400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40010400_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40010400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_reg {1073808384 /* 0x40010400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_0 1073808384 -#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40010400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts {43 /* 0x2b */, 0 /* 0x0 */, 44 /* 0x2c */, 0 /* 0x0 */, 45 /* 0x2d */, 0 /* 0x0 */, 46 /* 0x2e */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_0 43 +#define DT_N_S_soc_S_timers_40010400_P_interrupts {43, 0, 44, 0, 45, 0, 46, 0} #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_0 43 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_2 44 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_2_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_3 0 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_2 44 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_3_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_4 45 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_3 0 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_4_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_5 0 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_4 45 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_5_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_6 46 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_5 0 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_6_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_7 0 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_6 46 #define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_7_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_interrupts_IDX_7 0 #define DT_N_S_soc_S_timers_40010400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names {"brk", "up", "trgcom", "cc"} +#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0 "brk" #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_STRING_UNQUOTED brk #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_STRING_TOKEN brk #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN BRK -#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1 "up" #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_STRING_UNQUOTED up #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_STRING_TOKEN up #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_STRING_UPPER_TOKEN UP -#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2 "trgcom" #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_STRING_UNQUOTED trgcom #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_STRING_TOKEN trgcom #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_STRING_UPPER_TOKEN TRGCOM -#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_2_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3 "cc" #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_STRING_UNQUOTED cc #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_STRING_TOKEN cc #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_STRING_UPPER_TOKEN CC -#define DT_N_S_soc_S_timers_40010400_P_interrupt_names_IDX_3_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 0) \ fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 1) \ fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 2) \ @@ -38010,34 +38941,12 @@ fn(DT_N_S_soc_S_timers_40010400, interrupt_names, 3, __VA_ARGS__) #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_LEN 4 #define DT_N_S_soc_S_timers_40010400_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bits 2 -#define DT_N_S_soc_S_timers_40010400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, clocks, 0) -#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, clocks, 0) -#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010400_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40010400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40010400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_VAL_id 4865 -#define DT_N_S_soc_S_timers_40010400_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400, resets, 0) -#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400, resets, 0) -#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40010400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40010400_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40010400_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40010400_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40010400_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40010400/pwm @@ -38056,6 +38965,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40010400_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40010400) identifier: */ #define DT_N_S_soc_S_timers_40010400_S_pwm_PARENT DT_N_S_soc_S_timers_40010400 @@ -38081,12 +38993,12 @@ #define DT_N_S_soc_S_timers_40010400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD 278 -#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD_STR_SORTABLE 00278 +#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD 281 +#define DT_N_S_soc_S_timers_40010400_S_pwm_ORD_STR_SORTABLE 00281 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40010400_S_pwm_REQUIRES_ORDS \ - 277, /* /soc/timers@40010400 */ + 280, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40010400_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -38112,20 +39024,16 @@ #define DT_N_S_soc_S_timers_40010400_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, status, 0, __VA_ARGS__) @@ -38133,11 +39041,11 @@ #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40010400_S_pwm, compatible, 0, __VA_ARGS__) @@ -38146,8 +39054,10 @@ #define DT_N_S_soc_S_timers_40010400_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40010400_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40010400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014000 @@ -38166,6 +39076,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014000_FULL_NAME "timers@40014000" +#define DT_N_S_soc_S_timers_40014000_FULL_NAME_UNQUOTED timers@40014000 +#define DT_N_S_soc_S_timers_40014000_FULL_NAME_TOKEN timers_40014000 +#define DT_N_S_soc_S_timers_40014000_FULL_NAME_UPPER_TOKEN TIMERS_40014000 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40014000_PARENT DT_N_S_soc @@ -38191,20 +39104,20 @@ #define DT_N_S_soc_S_timers_40014000_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014000_ORD 279 -#define DT_N_S_soc_S_timers_40014000_ORD_STR_SORTABLE 00279 +#define DT_N_S_soc_S_timers_40014000_ORD 282 +#define DT_N_S_soc_S_timers_40014000_ORD_STR_SORTABLE 00282 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014000_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014000_SUPPORTS_ORDS \ - 280, /* /soc/timers@40014000/counter */ \ - 281, /* /soc/timers@40014000/pwm */ + 283, \ + 284, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40014000_EXISTS 1 @@ -38214,8 +39127,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40014000_REG_NUM 1 #define DT_N_S_soc_S_timers_40014000_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_ADDRESS 1073823744 /* 0x40014000 */ -#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_ADDRESS 1073823744 +#define DT_N_S_soc_S_timers_40014000_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40014000_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40014000_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40014000_IRQ_NUM 1 @@ -38243,20 +39156,46 @@ #define DT_N_S_soc_S_timers_40014000_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014000_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014000_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_reg {1073823744, 1024} +#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0 1073823744 +#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40014000_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits 65536 +#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) +#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) +#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014000_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40014000_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id 4880 +#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, resets, 0) +#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, resets, 0) +#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014000_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40014000_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40014000_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40014000_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_status "disabled" #define DT_N_S_soc_S_timers_40014000_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014000_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014000_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014000_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014000_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014000_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014000_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, status, 0) #define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, status, 0) #define DT_N_S_soc_S_timers_40014000_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, status, 0, __VA_ARGS__) @@ -38264,69 +39203,41 @@ #define DT_N_S_soc_S_timers_40014000_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014000_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40014000_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, compatible, 0) #define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, compatible, 0) #define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014000_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014000_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40014000_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_reg {1073823744 /* 0x40014000 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0 1073823744 -#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40014000_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_interrupts {116 /* 0x74 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0 116 +#define DT_N_S_soc_S_timers_40014000_P_interrupts {116, 0} #define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_0 116 #define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40014000_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40014000_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0) #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40014000_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits 65536 -#define DT_N_S_soc_S_timers_40014000_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) -#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, clocks, 0) -#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014000_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014000_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40014000_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014000_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id 4880 -#define DT_N_S_soc_S_timers_40014000_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000, resets, 0) -#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000, resets, 0) -#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014000_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014000, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014000_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40014000_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40014000_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40014000_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014000_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014000_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014000/counter @@ -38345,6 +39256,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40014000_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40014000) identifier: */ #define DT_N_S_soc_S_timers_40014000_S_counter_PARENT DT_N_S_soc_S_timers_40014000 @@ -38370,12 +39284,12 @@ #define DT_N_S_soc_S_timers_40014000_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014000_S_counter_ORD 280 -#define DT_N_S_soc_S_timers_40014000_S_counter_ORD_STR_SORTABLE 00280 +#define DT_N_S_soc_S_timers_40014000_S_counter_ORD 283 +#define DT_N_S_soc_S_timers_40014000_S_counter_ORD_STR_SORTABLE 00283 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014000_S_counter_REQUIRES_ORDS \ - 279, /* /soc/timers@40014000 */ + 282, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014000_S_counter_SUPPORTS_ORDS /* nothing */ @@ -38401,20 +39315,14 @@ #define DT_N_S_soc_S_timers_40014000_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014000_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0) #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, status, 0, __VA_ARGS__) @@ -38422,11 +39330,11 @@ #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_counter, compatible, 0, __VA_ARGS__) @@ -38435,6 +39343,10 @@ #define DT_N_S_soc_S_timers_40014000_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014000_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014000_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014000/pwm @@ -38453,6 +39365,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40014000_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40014000) identifier: */ #define DT_N_S_soc_S_timers_40014000_S_pwm_PARENT DT_N_S_soc_S_timers_40014000 @@ -38478,12 +39393,12 @@ #define DT_N_S_soc_S_timers_40014000_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD 281 -#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD_STR_SORTABLE 00281 +#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD 284 +#define DT_N_S_soc_S_timers_40014000_S_pwm_ORD_STR_SORTABLE 00284 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014000_S_pwm_REQUIRES_ORDS \ - 279, /* /soc/timers@40014000 */ + 282, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014000_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -38509,20 +39424,16 @@ #define DT_N_S_soc_S_timers_40014000_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, status, 0, __VA_ARGS__) @@ -38530,11 +39441,11 @@ #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014000_S_pwm, compatible, 0, __VA_ARGS__) @@ -38543,8 +39454,10 @@ #define DT_N_S_soc_S_timers_40014000_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40014000_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014000_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014400 @@ -38563,6 +39476,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014400_FULL_NAME "timers@40014400" +#define DT_N_S_soc_S_timers_40014400_FULL_NAME_UNQUOTED timers@40014400 +#define DT_N_S_soc_S_timers_40014400_FULL_NAME_TOKEN timers_40014400 +#define DT_N_S_soc_S_timers_40014400_FULL_NAME_UPPER_TOKEN TIMERS_40014400 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40014400_PARENT DT_N_S_soc @@ -38588,20 +39504,20 @@ #define DT_N_S_soc_S_timers_40014400_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014400_ORD 282 -#define DT_N_S_soc_S_timers_40014400_ORD_STR_SORTABLE 00282 +#define DT_N_S_soc_S_timers_40014400_ORD 285 +#define DT_N_S_soc_S_timers_40014400_ORD_STR_SORTABLE 00285 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014400_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014400_SUPPORTS_ORDS \ - 283, /* /soc/timers@40014400/counter */ \ - 284, /* /soc/timers@40014400/pwm */ + 286, \ + 287, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40014400_EXISTS 1 @@ -38611,8 +39527,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40014400_REG_NUM 1 #define DT_N_S_soc_S_timers_40014400_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_ADDRESS 1073824768 /* 0x40014400 */ -#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_ADDRESS 1073824768 +#define DT_N_S_soc_S_timers_40014400_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40014400_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40014400_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40014400_IRQ_NUM 1 @@ -38640,20 +39556,46 @@ #define DT_N_S_soc_S_timers_40014400_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014400_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014400_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_reg {1073824768, 1024} +#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0 1073824768 +#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40014400_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits 131072 +#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) +#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) +#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014400_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40014400_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id 4881 +#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, resets, 0) +#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, resets, 0) +#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014400_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40014400_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40014400_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40014400_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_status "disabled" #define DT_N_S_soc_S_timers_40014400_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014400_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014400_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014400_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014400_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014400_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014400_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, status, 0) #define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, status, 0) #define DT_N_S_soc_S_timers_40014400_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, status, 0, __VA_ARGS__) @@ -38661,69 +39603,41 @@ #define DT_N_S_soc_S_timers_40014400_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014400_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40014400_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, compatible, 0) #define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, compatible, 0) #define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014400_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014400_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40014400_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_reg {1073824768 /* 0x40014400 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0 1073824768 -#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40014400_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_interrupts {117 /* 0x75 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0 117 +#define DT_N_S_soc_S_timers_40014400_P_interrupts {117, 0} #define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_0 117 #define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40014400_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40014400_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0) #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40014400_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits 131072 -#define DT_N_S_soc_S_timers_40014400_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) -#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, clocks, 0) -#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014400_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014400_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40014400_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014400_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id 4881 -#define DT_N_S_soc_S_timers_40014400_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400, resets, 0) -#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400, resets, 0) -#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014400_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014400, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014400_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40014400_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40014400_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40014400_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014400_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014400_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014400/counter @@ -38742,6 +39656,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40014400_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40014400) identifier: */ #define DT_N_S_soc_S_timers_40014400_S_counter_PARENT DT_N_S_soc_S_timers_40014400 @@ -38767,12 +39684,12 @@ #define DT_N_S_soc_S_timers_40014400_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014400_S_counter_ORD 283 -#define DT_N_S_soc_S_timers_40014400_S_counter_ORD_STR_SORTABLE 00283 +#define DT_N_S_soc_S_timers_40014400_S_counter_ORD 286 +#define DT_N_S_soc_S_timers_40014400_S_counter_ORD_STR_SORTABLE 00286 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014400_S_counter_REQUIRES_ORDS \ - 282, /* /soc/timers@40014400 */ + 285, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014400_S_counter_SUPPORTS_ORDS /* nothing */ @@ -38798,20 +39715,14 @@ #define DT_N_S_soc_S_timers_40014400_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014400_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0) #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0) #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, status, 0, __VA_ARGS__) @@ -38819,11 +39730,11 @@ #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_counter, compatible, 0, __VA_ARGS__) @@ -38832,6 +39743,10 @@ #define DT_N_S_soc_S_timers_40014400_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014400_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014400_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014400/pwm @@ -38850,6 +39765,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40014400_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40014400) identifier: */ #define DT_N_S_soc_S_timers_40014400_S_pwm_PARENT DT_N_S_soc_S_timers_40014400 @@ -38875,12 +39793,12 @@ #define DT_N_S_soc_S_timers_40014400_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD 284 -#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD_STR_SORTABLE 00284 +#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD 287 +#define DT_N_S_soc_S_timers_40014400_S_pwm_ORD_STR_SORTABLE 00287 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014400_S_pwm_REQUIRES_ORDS \ - 282, /* /soc/timers@40014400 */ + 285, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014400_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -38906,20 +39824,16 @@ #define DT_N_S_soc_S_timers_40014400_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, status, 0, __VA_ARGS__) @@ -38927,11 +39841,11 @@ #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014400_S_pwm, compatible, 0, __VA_ARGS__) @@ -38940,8 +39854,10 @@ #define DT_N_S_soc_S_timers_40014400_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40014400_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014400_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014800 @@ -38960,6 +39876,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014800_FULL_NAME "timers@40014800" +#define DT_N_S_soc_S_timers_40014800_FULL_NAME_UNQUOTED timers@40014800 +#define DT_N_S_soc_S_timers_40014800_FULL_NAME_TOKEN timers_40014800 +#define DT_N_S_soc_S_timers_40014800_FULL_NAME_UPPER_TOKEN TIMERS_40014800 /* Node parent (/soc) identifier: */ #define DT_N_S_soc_S_timers_40014800_PARENT DT_N_S_soc @@ -38985,20 +39904,20 @@ #define DT_N_S_soc_S_timers_40014800_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014800_ORD 285 -#define DT_N_S_soc_S_timers_40014800_ORD_STR_SORTABLE 00285 +#define DT_N_S_soc_S_timers_40014800_ORD 288 +#define DT_N_S_soc_S_timers_40014800_ORD_STR_SORTABLE 00288 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014800_REQUIRES_ORDS \ - 4, /* /soc */ \ - 5, /* /soc/interrupt-controller@e000e100 */ \ - 9, /* /soc/rcc@58024400 */ \ - 54, /* /soc/rcc@58024400/reset-controller */ + 4, \ + 5, \ + 9, \ + 54, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014800_SUPPORTS_ORDS \ - 286, /* /soc/timers@40014800/counter */ \ - 287, /* /soc/timers@40014800/pwm */ + 289, \ + 290, /* Existence and alternate IDs: */ #define DT_N_S_soc_S_timers_40014800_EXISTS 1 @@ -39008,8 +39927,8 @@ /* Macros for properties that are special in the specification: */ #define DT_N_S_soc_S_timers_40014800_REG_NUM 1 #define DT_N_S_soc_S_timers_40014800_REG_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_ADDRESS 1073825792 /* 0x40014800 */ -#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_SIZE 1024 /* 0x400 */ +#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_ADDRESS 1073825792 +#define DT_N_S_soc_S_timers_40014800_REG_IDX_0_VAL_SIZE 1024 #define DT_N_S_soc_S_timers_40014800_RANGES_NUM 0 #define DT_N_S_soc_S_timers_40014800_FOREACH_RANGE(fn) #define DT_N_S_soc_S_timers_40014800_IRQ_NUM 1 @@ -39037,20 +39956,46 @@ #define DT_N_S_soc_S_timers_40014800_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014800_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014800_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_reg {1073825792, 1024} +#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0 1073825792 +#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1 1024 +#define DT_N_S_soc_S_timers_40014800_P_reg_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 +#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus 240 +#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits 262144 +#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) +#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) +#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014800_P_clocks_LEN 1 +#define DT_N_S_soc_S_timers_40014800_P_clocks_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller +#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id 4882 +#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, resets, 0) +#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, resets, 0) +#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__) +#define DT_N_S_soc_S_timers_40014800_P_resets_LEN 1 +#define DT_N_S_soc_S_timers_40014800_P_resets_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_st_prescaler 0 +#define DT_N_S_soc_S_timers_40014800_P_st_prescaler_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_st_countermode 0 +#define DT_N_S_soc_S_timers_40014800_P_st_countermode_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_status "disabled" #define DT_N_S_soc_S_timers_40014800_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014800_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014800_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014800_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014800_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014800_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014800_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, status, 0) #define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, status, 0) #define DT_N_S_soc_S_timers_40014800_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, status, 0, __VA_ARGS__) @@ -39058,69 +40003,41 @@ #define DT_N_S_soc_S_timers_40014800_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014800_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_compatible {"st,stm32-timers"} +#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0 "st,stm32-timers" #define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-timers #define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_TOKEN st_stm32_timers #define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_TIMERS -#define DT_N_S_soc_S_timers_40014800_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, compatible, 0) #define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, compatible, 0) #define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014800_P_compatible_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, compatible, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014800_P_compatible_LEN 1 #define DT_N_S_soc_S_timers_40014800_P_compatible_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_reg {1073825792 /* 0x40014800 */, 1024 /* 0x400 */} -#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0 1073825792 -#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1 1024 -#define DT_N_S_soc_S_timers_40014800_P_reg_IDX_1_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_reg_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_interrupts {118 /* 0x76 */, 0 /* 0x0 */} -#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0 118 +#define DT_N_S_soc_S_timers_40014800_P_interrupts {118, 0} #define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1 0 +#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_0 118 #define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_interrupts_IDX_1 0 #define DT_N_S_soc_S_timers_40014800_P_interrupts_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_interrupt_names {"global"} +#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0 "global" #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_UNQUOTED global #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_TOKEN global #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_STRING_UPPER_TOKEN GLOBAL -#define DT_N_S_soc_S_timers_40014800_P_interrupt_names_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0) #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0) #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, interrupt_names, 0, __VA_ARGS__) #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_LEN 1 #define DT_N_S_soc_S_timers_40014800_P_interrupt_names_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_PH DT_N_S_soc_S_rcc_58024400 -#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus 240 -#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bus_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits 262144 -#define DT_N_S_soc_S_timers_40014800_P_clocks_IDX_0_VAL_bits_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) -#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, clocks, 0) -#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014800_P_clocks_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, clocks, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014800_P_clocks_LEN 1 -#define DT_N_S_soc_S_timers_40014800_P_clocks_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014800_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_PH DT_N_S_soc_S_rcc_58024400_S_reset_controller -#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id 4882 -#define DT_N_S_soc_S_timers_40014800_P_resets_IDX_0_VAL_id_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800, resets, 0) -#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800, resets, 0) -#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014800_P_resets_FOREACH_PROP_ELEM_SEP_VARGS(fn, sep, ...) fn(DT_N_S_soc_S_timers_40014800, resets, 0, __VA_ARGS__) -#define DT_N_S_soc_S_timers_40014800_P_resets_LEN 1 -#define DT_N_S_soc_S_timers_40014800_P_resets_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_st_prescaler 0 -#define DT_N_S_soc_S_timers_40014800_P_st_prescaler_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_P_st_countermode 0 -#define DT_N_S_soc_S_timers_40014800_P_st_countermode_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014800_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014800_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014800/counter @@ -39139,6 +40056,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME "counter" +#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_UNQUOTED counter +#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_TOKEN counter +#define DT_N_S_soc_S_timers_40014800_S_counter_FULL_NAME_UPPER_TOKEN COUNTER /* Node parent (/soc/timers@40014800) identifier: */ #define DT_N_S_soc_S_timers_40014800_S_counter_PARENT DT_N_S_soc_S_timers_40014800 @@ -39164,12 +40084,12 @@ #define DT_N_S_soc_S_timers_40014800_S_counter_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014800_S_counter_ORD 286 -#define DT_N_S_soc_S_timers_40014800_S_counter_ORD_STR_SORTABLE 00286 +#define DT_N_S_soc_S_timers_40014800_S_counter_ORD 289 +#define DT_N_S_soc_S_timers_40014800_S_counter_ORD_STR_SORTABLE 00289 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014800_S_counter_REQUIRES_ORDS \ - 285, /* /soc/timers@40014800 */ + 288, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014800_S_counter_SUPPORTS_ORDS /* nothing */ @@ -39195,20 +40115,14 @@ #define DT_N_S_soc_S_timers_40014800_S_counter_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_status "disabled" #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014800_S_counter_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0) #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0) #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, status, 0, __VA_ARGS__) @@ -39216,11 +40130,11 @@ #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible {"st,stm32-counter"} +#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0 "st,stm32-counter" #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-counter #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_TOKEN st_stm32_counter #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_COUNTER -#define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0) #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_counter, compatible, 0, __VA_ARGS__) @@ -39229,6 +40143,10 @@ #define DT_N_S_soc_S_timers_40014800_S_counter_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_deferred_init_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014800_S_counter_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014800_S_counter_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Devicetree node: /soc/timers@40014800/pwm @@ -39247,6 +40165,9 @@ /* Node's name with unit-address: */ #define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME "pwm" +#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_UNQUOTED pwm +#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_TOKEN pwm +#define DT_N_S_soc_S_timers_40014800_S_pwm_FULL_NAME_UPPER_TOKEN PWM /* Node parent (/soc/timers@40014800) identifier: */ #define DT_N_S_soc_S_timers_40014800_S_pwm_PARENT DT_N_S_soc_S_timers_40014800 @@ -39272,12 +40193,12 @@ #define DT_N_S_soc_S_timers_40014800_S_pwm_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(fn, sep, ...) /* Node's dependency ordinal: */ -#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD 287 -#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD_STR_SORTABLE 00287 +#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD 290 +#define DT_N_S_soc_S_timers_40014800_S_pwm_ORD_STR_SORTABLE 00290 /* Ordinals for what this node depends on directly: */ #define DT_N_S_soc_S_timers_40014800_S_pwm_REQUIRES_ORDS \ - 285, /* /soc/timers@40014800 */ + 288, /* Ordinals for what depends directly on this node: */ #define DT_N_S_soc_S_timers_40014800_S_pwm_SUPPORTS_ORDS /* nothing */ @@ -39303,20 +40224,16 @@ #define DT_N_S_soc_S_timers_40014800_S_pwm_PINCTRL_NUM 0 /* Generic property macros: */ -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source 0 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto 0 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support 0 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status "disabled" #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_UNQUOTED disabled #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_TOKEN disabled #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_STRING_UPPER_TOKEN DISABLED #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0 "disabled" #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_ENUM_IDX 2 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_ENUM_VAL_disabled_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_ENUM_TOKEN disabled -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_ENUM_UPPER_TOKEN DISABLED +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_ENUM_IDX 2 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_IDX_0_ENUM_VAL_disabled_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0) #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, status, 0, __VA_ARGS__) @@ -39324,11 +40241,11 @@ #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_LEN 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_status_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible {"st,stm32-pwm"} +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0 "st,stm32-pwm" #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_UNQUOTED st,stm32-pwm #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_TOKEN st_stm32_pwm #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_STRING_UPPER_TOKEN ST_STM32_PWM -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_IDX_0_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM(fn) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_SEP(fn, sep) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0) #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_FOREACH_PROP_ELEM_VARGS(fn, ...) fn(DT_N_S_soc_S_timers_40014800_S_pwm, compatible, 0, __VA_ARGS__) @@ -39337,8 +40254,10 @@ #define DT_N_S_soc_S_timers_40014800_S_pwm_P_compatible_EXISTS 1 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_deferred_init 0 #define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_deferred_init_EXISTS 1 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support 0 -#define DT_N_S_soc_S_timers_40014800_S_pwm_P_four_channel_capture_support_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source 0 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_wakeup_source_EXISTS 1 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto 0 +#define DT_N_S_soc_S_timers_40014800_S_pwm_P_zephyr_pm_device_runtime_auto_EXISTS 1 /* * Chosen nodes @@ -39367,10 +40286,10 @@ #define DT_CHOSEN_zephyr_camera_EXISTS 1 /* Macros for iterating over all nodes and enabled nodes */ -#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_watchdog_58004800) fn(DT_N_S_soc_S_watchdog_50003000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_serial_58000c00) fn(DT_N_S_soc_S_rtc_58004000) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_58001400) fn(DT_N_S_soc_S_i2s_40013000) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_can_4000a000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) fn(DT_N_S_soc_S_timers_40000c00_S_counter) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001000_S_counter) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40001400_S_counter) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40010400_S_pwm) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001800_S_pwm) fn(DT_N_S_soc_S_timers_40001800_S_counter) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) fn(DT_N_S_soc_S_timers_40001c00_S_counter) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_timers_40002000_S_pwm) fn(DT_N_S_soc_S_timers_40002000_S_counter) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter) fn(DT_N_S_soc_S_timers_40002400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) fn(DT_N_S_soc_S_adc_40022100) fn(DT_N_S_soc_S_adc_40022300) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_bdma_58025400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_dmamux_58025800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_sdmmc_52007000) fn(DT_N_S_soc_S_sdmmc_48022400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_memory_38800000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_dcmi_48020000_S_port) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_display_controller_50001000) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_soc_S_dsihost_50000000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_csi) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_clocks_S_pll_1) fn(DT_N_S_clocks_S_pll_2) fn(DT_N_S_clocks_S_perck) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) -#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_dcmi_48020000_S_port) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) -#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_58004800, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_58000c00, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_58001400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022300, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_bdma_58025400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_58025800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_52007000, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_48022400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_memory_38800000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_soc_S_dsihost_50000000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_csi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_1, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_2, __VA_ARGS__) fn(DT_N_S_clocks_S_perck, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) -#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_FOREACH_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_watchdog_58004800) fn(DT_N_S_soc_S_watchdog_50003000) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004800) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40005000) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_serial_40007c00) fn(DT_N_S_soc_S_serial_58000c00) fn(DT_N_S_soc_S_rtc_58004000) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_40005c00) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40003800) fn(DT_N_S_soc_S_spi_40003c00) fn(DT_N_S_soc_S_spi_40013400) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_spi_58001400) fn(DT_N_S_soc_S_i2s_40013000) fn(DT_N_S_soc_S_i2s_40003800) fn(DT_N_S_soc_S_i2s_40003c00) fn(DT_N_S_soc_S_can_4000a000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) fn(DT_N_S_soc_S_timers_40000000) fn(DT_N_S_soc_S_timers_40000000_S_pwm) fn(DT_N_S_soc_S_timers_40000000_S_counter) fn(DT_N_S_soc_S_timers_40000400) fn(DT_N_S_soc_S_timers_40000400_S_pwm) fn(DT_N_S_soc_S_timers_40000400_S_counter) fn(DT_N_S_soc_S_timers_40000800) fn(DT_N_S_soc_S_timers_40000800_S_pwm) fn(DT_N_S_soc_S_timers_40000800_S_counter) fn(DT_N_S_soc_S_timers_40000c00) fn(DT_N_S_soc_S_timers_40000c00_S_pwm) fn(DT_N_S_soc_S_timers_40000c00_S_counter) fn(DT_N_S_soc_S_timers_40001000) fn(DT_N_S_soc_S_timers_40001000_S_counter) fn(DT_N_S_soc_S_timers_40001400) fn(DT_N_S_soc_S_timers_40001400_S_counter) fn(DT_N_S_soc_S_timers_40010400) fn(DT_N_S_soc_S_timers_40010400_S_pwm) fn(DT_N_S_soc_S_timers_40001800) fn(DT_N_S_soc_S_timers_40001800_S_pwm) fn(DT_N_S_soc_S_timers_40001800_S_counter) fn(DT_N_S_soc_S_timers_40001c00) fn(DT_N_S_soc_S_timers_40001c00_S_pwm) fn(DT_N_S_soc_S_timers_40001c00_S_counter) fn(DT_N_S_soc_S_timers_40002000) fn(DT_N_S_soc_S_timers_40002000_S_pwm) fn(DT_N_S_soc_S_timers_40002000_S_counter) fn(DT_N_S_soc_S_timers_40014000) fn(DT_N_S_soc_S_timers_40014000_S_pwm) fn(DT_N_S_soc_S_timers_40014000_S_counter) fn(DT_N_S_soc_S_timers_40014400) fn(DT_N_S_soc_S_timers_40014400_S_pwm) fn(DT_N_S_soc_S_timers_40014400_S_counter) fn(DT_N_S_soc_S_timers_40014800) fn(DT_N_S_soc_S_timers_40014800_S_pwm) fn(DT_N_S_soc_S_timers_40014800_S_counter) fn(DT_N_S_soc_S_timers_40002400) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) fn(DT_N_S_soc_S_adc_40022100) fn(DT_N_S_soc_S_adc_40022300) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dma_40020400) fn(DT_N_S_soc_S_bdma_58025400) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_dmamux_58025800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_sdmmc_52007000) fn(DT_N_S_soc_S_sdmmc_48022400) fn(DT_N_S_soc_S_ethernet_40028000) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_memory_38800000) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_dcmi_48020000_S_port) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_display_controller_50001000) fn(DT_N_S_soc_S_usb_40040000) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_soc_S_dsihost_50000000) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_csi) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_clk_lsi) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_clocks_S_pll_1) fn(DT_N_S_clocks_S_pll_2) fn(DT_N_S_clocks_S_perck) fn(DT_N_S_mcos) fn(DT_N_S_mcos_S_mco1) fn(DT_N_S_mcos_S_mco2) fn(DT_N_S_dietemp) fn(DT_N_S_vbat) fn(DT_N_S_vref) fn(DT_N_S_smbus1) fn(DT_N_S_smbus2) fn(DT_N_S_smbus3) fn(DT_N_S_smbus4) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_FOREACH_OKAY_HELPER(fn) fn(DT_N) fn(DT_N_S_chosen) fn(DT_N_S_aliases) fn(DT_N_S_soc) fn(DT_N_S_soc_S_interrupt_controller_e000e100) fn(DT_N_S_soc_S_timer_e000e010) fn(DT_N_S_soc_S_flash_controller_52002000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000) fn(DT_N_S_soc_S_rcc_58024400) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller) fn(DT_N_S_soc_S_interrupt_controller_58000000) fn(DT_N_S_soc_S_pin_controller_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12) fn(DT_N_S_soc_S_serial_40011000) fn(DT_N_S_soc_S_serial_40004400) fn(DT_N_S_soc_S_serial_40004c00) fn(DT_N_S_soc_S_serial_40011400) fn(DT_N_S_soc_S_serial_40007800) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx) fn(DT_N_S_soc_S_i2c_40005400) fn(DT_N_S_soc_S_i2c_40005800) fn(DT_N_S_soc_S_i2c_58001c00) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint) fn(DT_N_S_soc_S_spi_40013000) fn(DT_N_S_soc_S_spi_40015000) fn(DT_N_S_soc_S_can_4000a400) fn(DT_N_S_soc_S_timers_40010000) fn(DT_N_S_soc_S_timers_40010000_S_pwm) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock) fn(DT_N_S_soc_S_adc_40022000) fn(DT_N_S_soc_S_adc_40022000_S_channel_4) fn(DT_N_S_soc_S_adc_40022000_S_channel_8) fn(DT_N_S_soc_S_adc_40022000_S_channel_9) fn(DT_N_S_soc_S_adc_40022000_S_channel_5) fn(DT_N_S_soc_S_adc_40022000_S_channel_d) fn(DT_N_S_soc_S_adc_40022000_S_channel_c) fn(DT_N_S_soc_S_adc_40022000_S_channel_a) fn(DT_N_S_soc_S_adc_40022000_S_channel_10) fn(DT_N_S_soc_S_adc_40022000_S_channel_12) fn(DT_N_S_soc_S_adc_40022000_S_channel_13) fn(DT_N_S_soc_S_adc_40022000_S_channel_0) fn(DT_N_S_soc_S_adc_40022000_S_channel_1) fn(DT_N_S_soc_S_adc_58026000) fn(DT_N_S_soc_S_adc_58026000_S_channel_0) fn(DT_N_S_soc_S_adc_58026000_S_channel_1) fn(DT_N_S_soc_S_dac_40007400) fn(DT_N_S_soc_S_dma_40020000) fn(DT_N_S_soc_S_dmamux_40020800) fn(DT_N_S_soc_S_rng_48021800) fn(DT_N_S_soc_S_memory_controller_52004000) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0) fn(DT_N_S_soc_S_quadspi_52005000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000) fn(DT_N_S_soc_S_dcmi_48020000) fn(DT_N_S_soc_S_dcmi_48020000_S_port) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint) fn(DT_N_S_soc_S_mailbox_58026400) fn(DT_N_S_soc_S_usb_40080000) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0) fn(DT_N_S_cpus) fn(DT_N_S_cpus_S_cpu_0) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90) fn(DT_N_S_memory_90000000) fn(DT_N_S_clocks) fn(DT_N_S_clocks_S_clk_hse) fn(DT_N_S_clocks_S_clk_hsi48) fn(DT_N_S_clocks_S_clk_lse) fn(DT_N_S_clocks_S_pll_0) fn(DT_N_S_mcos) fn(DT_N_S_memory_24000000) fn(DT_N_S_memory_30000000) fn(DT_N_S_memory_30020000) fn(DT_N_S_memory_30040000) fn(DT_N_S_memory_38000000) fn(DT_N_S_otghs_fs_phy) fn(DT_N_S_connector) fn(DT_N_S_leds) fn(DT_N_S_leds_S_led_0) fn(DT_N_S_leds_S_led_1) fn(DT_N_S_leds_S_led_2) fn(DT_N_S_gpio_keys) fn(DT_N_S_gpio_keys_S_button_0) fn(DT_N_S_sdram_c0000000) fn(DT_N_S_gpio_deadbeef) fn(DT_N_S_zephyr_user) +#define DT_FOREACH_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_58004800, __VA_ARGS__) fn(DT_N_S_soc_S_watchdog_50003000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40005000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_58000c00, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000, __VA_ARGS__) fn(DT_N_S_soc_S_rtc_58004000_S_backup_regs, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013400, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_58001400, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003800, __VA_ARGS__) fn(DT_N_S_soc_S_i2s_40003c00, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40000c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40001c00_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014000_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014400_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40014800_S_counter, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40002400, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022100, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022300, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020400, __VA_ARGS__) fn(DT_N_S_soc_S_bdma_58025400, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_58025800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_52007000, __VA_ARGS__) fn(DT_N_S_soc_S_sdmmc_48022400, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000, __VA_ARGS__) fn(DT_N_S_soc_S_ethernet_40028000_S_mdio, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_memory_38800000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_display_controller_50001000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40040000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_soc_S_dsihost_50000000, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_csi, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lsi, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_1, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_2, __VA_ARGS__) fn(DT_N_S_clocks_S_perck, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_mcos_S_mco1, __VA_ARGS__) fn(DT_N_S_mcos_S_mco2, __VA_ARGS__) fn(DT_N_S_dietemp, __VA_ARGS__) fn(DT_N_S_vbat, __VA_ARGS__) fn(DT_N_S_vref, __VA_ARGS__) fn(DT_N_S_smbus1, __VA_ARGS__) fn(DT_N_S_smbus2, __VA_ARGS__) fn(DT_N_S_smbus3, __VA_ARGS__) fn(DT_N_S_smbus4, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) +#define DT_FOREACH_OKAY_VARGS_HELPER(fn, ...) fn(DT_N, __VA_ARGS__) fn(DT_N_S_chosen, __VA_ARGS__) fn(DT_N_S_aliases, __VA_ARGS__) fn(DT_N_S_soc, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_e000e100, __VA_ARGS__) fn(DT_N_S_soc_S_timer_e000e010, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000, __VA_ARGS__) fn(DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_e0000, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400, __VA_ARGS__) fn(DT_N_S_soc_S_rcc_58024400_S_reset_controller, __VA_ARGS__) fn(DT_N_S_soc_S_interrupt_controller_58000000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58020c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58021c00, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022000, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022400, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_gpio_58022800, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp16_pa0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp0_pa0_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp1_pa1_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp18_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp19_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp9_pb0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp5_pb1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp10_pc0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp12_pc2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp13_pc3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp4_pc4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc1_inp8_pc5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp0_pc2_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_adc3_inp1_pc3_c, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out1_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dac1_out2_pa5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_pixclk_pa6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d3_pg11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_hsync_ph8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d0_ph9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d1_ph10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d2_ph11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d4_ph14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d5_pi4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_vsync_pi5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d6_pi6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_dcmi_d7_pi7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_rx_pb5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fdcan2_tx_pb13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d2_pd0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d3_pd1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d13_pd8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d14_pd9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d15_pd10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d0_pd14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d1_pd15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl0_pe0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_nbl1_pe1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d4_pe7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d5_pe8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d6_pe9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d7_pe10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d8_pe11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d9_pe12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d10_pe13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d11_pe14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_d12_pe15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a0_pf0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a1_pf1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a2_pf2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a3_pf3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a4_pf4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a5_pf5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnras_pf11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a6_pf12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a7_pf13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a8_pf14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a9_pf15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a10_pg0, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a11_pg1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a12_pg2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a14_pg4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_a15_pg5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdclk_pg8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdncas_pg15, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdcke0_ph2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdne0_ph3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_fmc_sdnwe_ph5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_scl_pb8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_scl_ph4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_scl_pb6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c1_sda_pb9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c2_sda_pb11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_i2c4_sda_ph12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io0_pd11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io1_pd12, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io2_pe2, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_io3_pf6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_clk_pf10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_quadspi_bk1_ncs_pg6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_miso_pg9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_miso_pj11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_mosi_pd7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_mosi_pj10, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_nss_pa4, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_nss_pk1, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi1_sck_pb3, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_spi5_sck_ph6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_tim1_ch3_pj9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_cts_pf9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rts_pf8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_rx_pb7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_rx_pd6, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_rx_pi9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_rx_pc7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_rx_pa8, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart1_tx_pa9, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart2_tx_pd5, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart4_tx_ph13, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usart6_tx_pg14, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_uart7_tx_pf7, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dm_pa11, __VA_ARGS__) fn(DT_N_S_soc_S_pin_controller_58020000_S_usb_otg_fs_dp_pa12, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011000, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40004c00, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40011400, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart, __VA_ARGS__) fn(DT_N_S_soc_S_serial_40007800_S_bt_hci_uart_S_murata_1dx, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005400, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_40005800, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_i2c_58001c00_S_ov7670_21_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40013000, __VA_ARGS__) fn(DT_N_S_soc_S_spi_40015000, __VA_ARGS__) fn(DT_N_S_soc_S_can_4000a400, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm, __VA_ARGS__) fn(DT_N_S_soc_S_timers_40010000_S_pwm_S_pwmclock, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_4, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_8, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_9, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_5, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_d, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_c, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_a, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_10, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_12, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_13, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_40022000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_0, __VA_ARGS__) fn(DT_N_S_soc_S_adc_58026000_S_channel_1, __VA_ARGS__) fn(DT_N_S_soc_S_dac_40007400, __VA_ARGS__) fn(DT_N_S_soc_S_dma_40020000, __VA_ARGS__) fn(DT_N_S_soc_S_dmamux_40020800, __VA_ARGS__) fn(DT_N_S_soc_S_rng_48021800, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram, __VA_ARGS__) fn(DT_N_S_soc_S_memory_controller_52004000_S_sdram_S_bank_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_0, __VA_ARGS__) fn(DT_N_S_soc_S_quadspi_52005000_S_qspi_nor_flash_90000000_S_partitions_S_partition_100000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port, __VA_ARGS__) fn(DT_N_S_soc_S_dcmi_48020000_S_port_S_endpoint, __VA_ARGS__) fn(DT_N_S_soc_S_mailbox_58026400, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000, __VA_ARGS__) fn(DT_N_S_soc_S_usb_40080000_S_cdc_acm_uart0, __VA_ARGS__) fn(DT_N_S_cpus, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0, __VA_ARGS__) fn(DT_N_S_cpus_S_cpu_0_S_mpu_e000ed90, __VA_ARGS__) fn(DT_N_S_memory_90000000, __VA_ARGS__) fn(DT_N_S_clocks, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hse, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_hsi48, __VA_ARGS__) fn(DT_N_S_clocks_S_clk_lse, __VA_ARGS__) fn(DT_N_S_clocks_S_pll_0, __VA_ARGS__) fn(DT_N_S_mcos, __VA_ARGS__) fn(DT_N_S_memory_24000000, __VA_ARGS__) fn(DT_N_S_memory_30000000, __VA_ARGS__) fn(DT_N_S_memory_30020000, __VA_ARGS__) fn(DT_N_S_memory_30040000, __VA_ARGS__) fn(DT_N_S_memory_38000000, __VA_ARGS__) fn(DT_N_S_otghs_fs_phy, __VA_ARGS__) fn(DT_N_S_connector, __VA_ARGS__) fn(DT_N_S_leds, __VA_ARGS__) fn(DT_N_S_leds_S_led_0, __VA_ARGS__) fn(DT_N_S_leds_S_led_1, __VA_ARGS__) fn(DT_N_S_leds_S_led_2, __VA_ARGS__) fn(DT_N_S_gpio_keys, __VA_ARGS__) fn(DT_N_S_gpio_keys_S_button_0, __VA_ARGS__) fn(DT_N_S_sdram_c0000000, __VA_ARGS__) fn(DT_N_S_gpio_deadbeef, __VA_ARGS__) fn(DT_N_S_zephyr_user, __VA_ARGS__) #define DT_COMPAT_fixed_partitions_LABEL_bootloader DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_0 #define DT_COMPAT_fixed_partitions_LABEL_bootloader_EXISTS 1 #define DT_COMPAT_fixed_partitions_LABEL_image_0 DT_N_S_soc_S_flash_controller_52002000_S_flash_8000000_S_partitions_S_partition_40000 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h index 136c9d4d..b1f07dc4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/driver-validation.h @@ -8,6 +8,8 @@ #define K_SYSCALL_DRIVER_DMA(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, dma, DMA) +#define K_SYSCALL_DRIVER_ENTROPY(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, entropy, ENTROPY) + #define K_SYSCALL_DRIVER_FLASH(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, flash, FLASH) #define K_SYSCALL_DRIVER_GPIO(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, gpio, GPIO) @@ -20,8 +22,6 @@ #define K_SYSCALL_DRIVER_RESET(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, reset, RESET) -#define K_SYSCALL_DRIVER_UART(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, uart, UART) - #define K_SYSCALL_DRIVER_SPI(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, spi, SPI) #define K_SYSCALL_DRIVER_SHARED_IRQ(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, shared_irq, SHARED_IRQ) @@ -42,6 +42,8 @@ #define K_SYSCALL_DRIVER_CLOCK_CONTROL(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, clock_control, CLOCK_CONTROL) +#define K_SYSCALL_DRIVER_COMPARATOR(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, comparator, COMPARATOR) + #define K_SYSCALL_DRIVER_COREDUMP(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, coredump, COREDUMP) #define K_SYSCALL_DRIVER_COUNTER(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, counter, COUNTER) @@ -62,8 +64,6 @@ #define K_SYSCALL_DRIVER_EMUL_SENSOR(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, emul_sensor, EMUL_SENSOR) -#define K_SYSCALL_DRIVER_ENTROPY(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, entropy, ENTROPY) - #define K_SYSCALL_DRIVER_ESPI(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, espi, ESPI) #define K_SYSCALL_DRIVER_ESPI_SAF(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, espi_saf, ESPI_SAF) @@ -74,6 +74,8 @@ #define K_SYSCALL_DRIVER_GNSS(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, gnss, GNSS) +#define K_SYSCALL_DRIVER_HAPTICS(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, haptics, HAPTICS) + #define K_SYSCALL_DRIVER_HWSPINLOCK(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, hwspinlock, HWSPINLOCK) #define K_SYSCALL_DRIVER_I2S(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, i2s, I2S) @@ -120,6 +122,8 @@ #define K_SYSCALL_DRIVER_SMBUS(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, smbus, SMBUS) +#define K_SYSCALL_DRIVER_STEPPER(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, stepper, STEPPER) + #define K_SYSCALL_DRIVER_SYSCON(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, syscon, SYSCON) #define K_SYSCALL_DRIVER_TEE(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, tee, TEE) @@ -132,6 +136,8 @@ #define K_SYSCALL_DRIVER_CAN_TRANSCEIVER(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, can_transceiver, CAN_TRANSCEIVER) +#define K_SYSCALL_DRIVER_NRF_CLOCK_CONTROL(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, nrf_clock_control, NRF_CLOCK_CONTROL) + #define K_SYSCALL_DRIVER_I3C_TARGET(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, i3c_target, I3C_TARGET) #define K_SYSCALL_DRIVER_ITS(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, its, ITS) @@ -146,6 +152,8 @@ #define K_SYSCALL_DRIVER_SVC(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, svc, SVC) +#define K_SYSCALL_DRIVER_UART(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, uart, UART) + #define K_SYSCALL_DRIVER_BC12_EMUL(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, bc12_emul, BC12_EMUL) #define K_SYSCALL_DRIVER_BC12(ptr, op) K_SYSCALL_DRIVER_GEN(ptr, op, bc12, BC12) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h index bc465b92..13243796 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/kobj-types-enum.h @@ -42,13 +42,13 @@ K_OBJ_SENSOR_DECODER_API, /* Driver subsystems */ K_OBJ_DRIVER_ADC, K_OBJ_DRIVER_DMA, +K_OBJ_DRIVER_ENTROPY, K_OBJ_DRIVER_FLASH, K_OBJ_DRIVER_GPIO, K_OBJ_DRIVER_I2C, K_OBJ_DRIVER_I2C_TARGET, K_OBJ_DRIVER_PWM, K_OBJ_DRIVER_RESET, -K_OBJ_DRIVER_UART, K_OBJ_DRIVER_SPI, K_OBJ_DRIVER_SHARED_IRQ, K_OBJ_DRIVER_CRYPTO, @@ -59,6 +59,7 @@ K_OBJ_DRIVER_CAN, K_OBJ_DRIVER_CELLULAR, K_OBJ_DRIVER_CHARGER, K_OBJ_DRIVER_CLOCK_CONTROL, +K_OBJ_DRIVER_COMPARATOR, K_OBJ_DRIVER_COREDUMP, K_OBJ_DRIVER_COUNTER, K_OBJ_DRIVER_DAC, @@ -69,12 +70,12 @@ K_OBJ_DRIVER_EEPROM, K_OBJ_DRIVER_EMUL_BBRAM, K_OBJ_DRIVER_FUEL_GAUGE_EMUL, K_OBJ_DRIVER_EMUL_SENSOR, -K_OBJ_DRIVER_ENTROPY, K_OBJ_DRIVER_ESPI, K_OBJ_DRIVER_ESPI_SAF, K_OBJ_DRIVER_FPGA, K_OBJ_DRIVER_FUEL_GAUGE, K_OBJ_DRIVER_GNSS, +K_OBJ_DRIVER_HAPTICS, K_OBJ_DRIVER_HWSPINLOCK, K_OBJ_DRIVER_I2S, K_OBJ_DRIVER_I3C, @@ -98,12 +99,14 @@ K_OBJ_DRIVER_RTC, K_OBJ_DRIVER_SDHC, K_OBJ_DRIVER_SENSOR, K_OBJ_DRIVER_SMBUS, +K_OBJ_DRIVER_STEPPER, K_OBJ_DRIVER_SYSCON, K_OBJ_DRIVER_TEE, K_OBJ_DRIVER_VIDEO, K_OBJ_DRIVER_W1, K_OBJ_DRIVER_WDT, K_OBJ_DRIVER_CAN_TRANSCEIVER, +K_OBJ_DRIVER_NRF_CLOCK_CONTROL, K_OBJ_DRIVER_I3C_TARGET, K_OBJ_DRIVER_ITS, K_OBJ_DRIVER_VTD, @@ -111,6 +114,7 @@ K_OBJ_DRIVER_TGPIO, K_OBJ_DRIVER_PCIE_CTRL, K_OBJ_DRIVER_PCIE_EP, K_OBJ_DRIVER_SVC, +K_OBJ_DRIVER_UART, K_OBJ_DRIVER_BC12_EMUL, K_OBJ_DRIVER_BC12, K_OBJ_DRIVER_USBC_PPC, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/offsets.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/offsets.h index 01476ffd..e8fe036a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/offsets.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/offsets.h @@ -24,6 +24,7 @@ #define ___thread_t_stack_info_OFFSET 0x98 #define ___thread_t_tls_OFFSET 0xa8 #define __z_interrupt_stack_SIZEOF 0x800 +#define __z_interrupt_all_stacks_SIZEOF 0x800 #define _PM_DEVICE_STRUCT_FLAGS_OFFSET 0x0 #define ___thread_arch_t_basepri_OFFSET 0x0 #define ___thread_arch_t_swap_return_value_OFFSET 0x4 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h index 7d7fbdfe..8948d60c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/otype-to-str.h @@ -42,13 +42,13 @@ case K_OBJ_SENSOR_DECODER_API: ret = "sensor_decoder_api"; break; /* Driver subsystems */ case K_OBJ_DRIVER_ADC: ret = "adc driver"; break; case K_OBJ_DRIVER_DMA: ret = "dma driver"; break; +case K_OBJ_DRIVER_ENTROPY: ret = "entropy driver"; break; case K_OBJ_DRIVER_FLASH: ret = "flash driver"; break; case K_OBJ_DRIVER_GPIO: ret = "gpio driver"; break; case K_OBJ_DRIVER_I2C: ret = "i2c driver"; break; case K_OBJ_DRIVER_I2C_TARGET: ret = "i2c_target driver"; break; case K_OBJ_DRIVER_PWM: ret = "pwm driver"; break; case K_OBJ_DRIVER_RESET: ret = "reset driver"; break; -case K_OBJ_DRIVER_UART: ret = "uart driver"; break; case K_OBJ_DRIVER_SPI: ret = "spi driver"; break; case K_OBJ_DRIVER_SHARED_IRQ: ret = "shared_irq driver"; break; case K_OBJ_DRIVER_CRYPTO: ret = "crypto driver"; break; @@ -59,6 +59,7 @@ case K_OBJ_DRIVER_CAN: ret = "can driver"; break; case K_OBJ_DRIVER_CELLULAR: ret = "cellular driver"; break; case K_OBJ_DRIVER_CHARGER: ret = "charger driver"; break; case K_OBJ_DRIVER_CLOCK_CONTROL: ret = "clock_control driver"; break; +case K_OBJ_DRIVER_COMPARATOR: ret = "comparator driver"; break; case K_OBJ_DRIVER_COREDUMP: ret = "coredump driver"; break; case K_OBJ_DRIVER_COUNTER: ret = "counter driver"; break; case K_OBJ_DRIVER_DAC: ret = "dac driver"; break; @@ -69,12 +70,12 @@ case K_OBJ_DRIVER_EEPROM: ret = "eeprom driver"; break; case K_OBJ_DRIVER_EMUL_BBRAM: ret = "emul_bbram driver"; break; case K_OBJ_DRIVER_FUEL_GAUGE_EMUL: ret = "fuel_gauge_emul driver"; break; case K_OBJ_DRIVER_EMUL_SENSOR: ret = "emul_sensor driver"; break; -case K_OBJ_DRIVER_ENTROPY: ret = "entropy driver"; break; case K_OBJ_DRIVER_ESPI: ret = "espi driver"; break; case K_OBJ_DRIVER_ESPI_SAF: ret = "espi_saf driver"; break; case K_OBJ_DRIVER_FPGA: ret = "fpga driver"; break; case K_OBJ_DRIVER_FUEL_GAUGE: ret = "fuel_gauge driver"; break; case K_OBJ_DRIVER_GNSS: ret = "gnss driver"; break; +case K_OBJ_DRIVER_HAPTICS: ret = "haptics driver"; break; case K_OBJ_DRIVER_HWSPINLOCK: ret = "hwspinlock driver"; break; case K_OBJ_DRIVER_I2S: ret = "i2s driver"; break; case K_OBJ_DRIVER_I3C: ret = "i3c driver"; break; @@ -98,12 +99,14 @@ case K_OBJ_DRIVER_RTC: ret = "rtc driver"; break; case K_OBJ_DRIVER_SDHC: ret = "sdhc driver"; break; case K_OBJ_DRIVER_SENSOR: ret = "sensor driver"; break; case K_OBJ_DRIVER_SMBUS: ret = "smbus driver"; break; +case K_OBJ_DRIVER_STEPPER: ret = "stepper driver"; break; case K_OBJ_DRIVER_SYSCON: ret = "syscon driver"; break; case K_OBJ_DRIVER_TEE: ret = "tee driver"; break; case K_OBJ_DRIVER_VIDEO: ret = "video driver"; break; case K_OBJ_DRIVER_W1: ret = "w1 driver"; break; case K_OBJ_DRIVER_WDT: ret = "wdt driver"; break; case K_OBJ_DRIVER_CAN_TRANSCEIVER: ret = "can_transceiver driver"; break; +case K_OBJ_DRIVER_NRF_CLOCK_CONTROL: ret = "nrf_clock_control driver"; break; case K_OBJ_DRIVER_I3C_TARGET: ret = "i3c_target driver"; break; case K_OBJ_DRIVER_ITS: ret = "its driver"; break; case K_OBJ_DRIVER_VTD: ret = "vtd driver"; break; @@ -111,6 +114,7 @@ case K_OBJ_DRIVER_TGPIO: ret = "tgpio driver"; break; case K_OBJ_DRIVER_PCIE_CTRL: ret = "pcie_ctrl driver"; break; case K_OBJ_DRIVER_PCIE_EP: ret = "pcie_ep driver"; break; case K_OBJ_DRIVER_SVC: ret = "svc driver"; break; +case K_OBJ_DRIVER_UART: ret = "uart driver"; break; case K_OBJ_DRIVER_BC12_EMUL: ret = "bc12_emul driver"; break; case K_OBJ_DRIVER_BC12: ret = "bc12 driver"; break; case K_OBJ_DRIVER_USBC_PPC: ret = "usbc_ppc driver"; break; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h index 74704a43..bdea1cac 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscall_list.h @@ -17,547 +17,563 @@ #define K_SYSCALL_DMA_START 11 #define K_SYSCALL_DMA_STOP 12 #define K_SYSCALL_DMA_SUSPEND 13 -#define K_SYSCALL_FLASH_ERASE 14 -#define K_SYSCALL_FLASH_EX_OP 15 -#define K_SYSCALL_FLASH_FILL 16 -#define K_SYSCALL_FLASH_FLATTEN 17 -#define K_SYSCALL_FLASH_GET_PAGE_COUNT 18 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 19 -#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 20 -#define K_SYSCALL_FLASH_GET_PARAMETERS 21 -#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 22 -#define K_SYSCALL_FLASH_READ 23 -#define K_SYSCALL_FLASH_READ_JEDEC_ID 24 -#define K_SYSCALL_FLASH_SFDP_READ 25 -#define K_SYSCALL_FLASH_WRITE 26 -#define K_SYSCALL_GPIO_GET_PENDING_INT 27 -#define K_SYSCALL_GPIO_PIN_CONFIGURE 28 -#define K_SYSCALL_GPIO_PIN_GET_CONFIG 29 -#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 30 -#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 31 -#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 32 -#define K_SYSCALL_GPIO_PORT_GET_RAW 33 -#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 34 -#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 35 -#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 36 -#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 37 -#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 38 -#define K_SYSCALL_HWINFO_GET_DEVICE_ID 39 -#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 40 -#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 41 -#define K_SYSCALL_I2C_CONFIGURE 42 -#define K_SYSCALL_I2C_GET_CONFIG 43 -#define K_SYSCALL_I2C_RECOVER_BUS 44 -#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 45 -#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 46 -#define K_SYSCALL_I2C_TRANSFER 47 -#define K_SYSCALL_K_BUSY_WAIT 48 -#define K_SYSCALL_K_CONDVAR_BROADCAST 49 -#define K_SYSCALL_K_CONDVAR_INIT 50 -#define K_SYSCALL_K_CONDVAR_SIGNAL 51 -#define K_SYSCALL_K_CONDVAR_WAIT 52 -#define K_SYSCALL_K_EVENT_CLEAR 53 -#define K_SYSCALL_K_EVENT_INIT 54 -#define K_SYSCALL_K_EVENT_POST 55 -#define K_SYSCALL_K_EVENT_SET 56 -#define K_SYSCALL_K_EVENT_SET_MASKED 57 -#define K_SYSCALL_K_EVENT_WAIT 58 -#define K_SYSCALL_K_EVENT_WAIT_ALL 59 -#define K_SYSCALL_K_FLOAT_DISABLE 60 -#define K_SYSCALL_K_FLOAT_ENABLE 61 -#define K_SYSCALL_K_FUTEX_WAIT 62 -#define K_SYSCALL_K_FUTEX_WAKE 63 -#define K_SYSCALL_K_IS_PREEMPT_THREAD 64 -#define K_SYSCALL_K_MSGQ_ALLOC_INIT 65 -#define K_SYSCALL_K_MSGQ_GET 66 -#define K_SYSCALL_K_MSGQ_GET_ATTRS 67 -#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 68 -#define K_SYSCALL_K_MSGQ_NUM_USED_GET 69 -#define K_SYSCALL_K_MSGQ_PEEK 70 -#define K_SYSCALL_K_MSGQ_PEEK_AT 71 -#define K_SYSCALL_K_MSGQ_PURGE 72 -#define K_SYSCALL_K_MSGQ_PUT 73 -#define K_SYSCALL_K_MUTEX_INIT 74 -#define K_SYSCALL_K_MUTEX_LOCK 75 -#define K_SYSCALL_K_MUTEX_UNLOCK 76 -#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 77 -#define K_SYSCALL_K_OBJECT_ALLOC 78 -#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 79 -#define K_SYSCALL_K_OBJECT_RELEASE 80 -#define K_SYSCALL_K_PIPE_ALLOC_INIT 81 -#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 82 -#define K_SYSCALL_K_PIPE_FLUSH 83 -#define K_SYSCALL_K_PIPE_GET 84 -#define K_SYSCALL_K_PIPE_PUT 85 -#define K_SYSCALL_K_PIPE_READ_AVAIL 86 -#define K_SYSCALL_K_PIPE_WRITE_AVAIL 87 -#define K_SYSCALL_K_POLL 88 -#define K_SYSCALL_K_POLL_SIGNAL_CHECK 89 -#define K_SYSCALL_K_POLL_SIGNAL_INIT 90 -#define K_SYSCALL_K_POLL_SIGNAL_RAISE 91 -#define K_SYSCALL_K_POLL_SIGNAL_RESET 92 -#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 93 -#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 94 -#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 95 -#define K_SYSCALL_K_QUEUE_GET 96 -#define K_SYSCALL_K_QUEUE_INIT 97 -#define K_SYSCALL_K_QUEUE_IS_EMPTY 98 -#define K_SYSCALL_K_QUEUE_PEEK_HEAD 99 -#define K_SYSCALL_K_QUEUE_PEEK_TAIL 100 -#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 101 -#define K_SYSCALL_K_SEM_COUNT_GET 102 -#define K_SYSCALL_K_SEM_GIVE 103 -#define K_SYSCALL_K_SEM_INIT 104 -#define K_SYSCALL_K_SEM_RESET 105 -#define K_SYSCALL_K_SEM_TAKE 106 -#define K_SYSCALL_K_SLEEP 107 -#define K_SYSCALL_K_STACK_ALLOC_INIT 108 -#define K_SYSCALL_K_STACK_POP 109 -#define K_SYSCALL_K_STACK_PUSH 110 -#define K_SYSCALL_K_STR_OUT 111 -#define K_SYSCALL_K_THREAD_ABORT 112 -#define K_SYSCALL_K_THREAD_CREATE 113 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 114 -#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 115 -#define K_SYSCALL_K_THREAD_DEADLINE_SET 116 -#define K_SYSCALL_K_THREAD_JOIN 117 -#define K_SYSCALL_K_THREAD_NAME_COPY 118 -#define K_SYSCALL_K_THREAD_NAME_SET 119 -#define K_SYSCALL_K_THREAD_PRIORITY_GET 120 -#define K_SYSCALL_K_THREAD_PRIORITY_SET 121 -#define K_SYSCALL_K_THREAD_RESUME 122 -#define K_SYSCALL_K_THREAD_STACK_ALLOC 123 -#define K_SYSCALL_K_THREAD_STACK_FREE 124 -#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 125 -#define K_SYSCALL_K_THREAD_START 126 -#define K_SYSCALL_K_THREAD_SUSPEND 127 -#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 128 -#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 129 -#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 130 -#define K_SYSCALL_K_TIMER_REMAINING_TICKS 131 -#define K_SYSCALL_K_TIMER_START 132 -#define K_SYSCALL_K_TIMER_STATUS_GET 133 -#define K_SYSCALL_K_TIMER_STATUS_SYNC 134 -#define K_SYSCALL_K_TIMER_STOP 135 -#define K_SYSCALL_K_TIMER_USER_DATA_GET 136 -#define K_SYSCALL_K_TIMER_USER_DATA_SET 137 -#define K_SYSCALL_K_UPTIME_TICKS 138 -#define K_SYSCALL_K_USLEEP 139 -#define K_SYSCALL_K_WAKEUP 140 -#define K_SYSCALL_K_YIELD 141 -#define K_SYSCALL_LLEXT_GET_FN_TABLE 142 -#define K_SYSCALL_LOG_BUFFERED_CNT 143 -#define K_SYSCALL_LOG_FILTER_SET 144 -#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 145 -#define K_SYSCALL_LOG_PANIC 146 -#define K_SYSCALL_LOG_PROCESS 147 -#define K_SYSCALL_PWM_CAPTURE_CYCLES 148 -#define K_SYSCALL_PWM_DISABLE_CAPTURE 149 -#define K_SYSCALL_PWM_ENABLE_CAPTURE 150 -#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 151 -#define K_SYSCALL_PWM_SET_CYCLES 152 -#define K_SYSCALL_RESET_LINE_ASSERT 153 -#define K_SYSCALL_RESET_LINE_DEASSERT 154 -#define K_SYSCALL_RESET_LINE_TOGGLE 155 -#define K_SYSCALL_RESET_STATUS 156 -#define K_SYSCALL_SPI_RELEASE 157 -#define K_SYSCALL_SPI_TRANSCEIVE 158 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 159 -#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 160 -#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 161 -#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 162 -#define K_SYSCALL_UART_CONFIGURE 163 -#define K_SYSCALL_UART_CONFIG_GET 164 -#define K_SYSCALL_UART_DRV_CMD 165 -#define K_SYSCALL_UART_ERR_CHECK 166 -#define K_SYSCALL_UART_IRQ_ERR_DISABLE 167 -#define K_SYSCALL_UART_IRQ_ERR_ENABLE 168 -#define K_SYSCALL_UART_IRQ_IS_PENDING 169 -#define K_SYSCALL_UART_IRQ_RX_DISABLE 170 -#define K_SYSCALL_UART_IRQ_RX_ENABLE 171 -#define K_SYSCALL_UART_IRQ_TX_DISABLE 172 -#define K_SYSCALL_UART_IRQ_TX_ENABLE 173 -#define K_SYSCALL_UART_IRQ_UPDATE 174 -#define K_SYSCALL_UART_LINE_CTRL_GET 175 -#define K_SYSCALL_UART_LINE_CTRL_SET 176 -#define K_SYSCALL_UART_POLL_IN 177 -#define K_SYSCALL_UART_POLL_IN_U16 178 -#define K_SYSCALL_UART_POLL_OUT 179 -#define K_SYSCALL_UART_POLL_OUT_U16 180 -#define K_SYSCALL_UART_RX_DISABLE 181 -#define K_SYSCALL_UART_RX_ENABLE 182 -#define K_SYSCALL_UART_RX_ENABLE_U16 183 -#define K_SYSCALL_UART_TX 184 -#define K_SYSCALL_UART_TX_ABORT 185 -#define K_SYSCALL_UART_TX_U16 186 -#define K_SYSCALL_ZEPHYR_FPUTC 187 -#define K_SYSCALL_ZEPHYR_FWRITE 188 -#define K_SYSCALL_ZEPHYR_READ_STDIN 189 -#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 190 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 191 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 192 -#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 193 -#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 194 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 195 -#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 196 -#define K_SYSCALL_BAD 197 -#define K_SYSCALL_LIMIT 198 +#define K_SYSCALL_ENTROPY_GET_ENTROPY 14 +#define K_SYSCALL_FLASH_COPY 15 +#define K_SYSCALL_FLASH_ERASE 16 +#define K_SYSCALL_FLASH_EX_OP 17 +#define K_SYSCALL_FLASH_FILL 18 +#define K_SYSCALL_FLASH_FLATTEN 19 +#define K_SYSCALL_FLASH_GET_PAGE_COUNT 20 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_IDX 21 +#define K_SYSCALL_FLASH_GET_PAGE_INFO_BY_OFFS 22 +#define K_SYSCALL_FLASH_GET_PARAMETERS 23 +#define K_SYSCALL_FLASH_GET_SIZE 24 +#define K_SYSCALL_FLASH_GET_WRITE_BLOCK_SIZE 25 +#define K_SYSCALL_FLASH_READ 26 +#define K_SYSCALL_FLASH_READ_JEDEC_ID 27 +#define K_SYSCALL_FLASH_SFDP_READ 28 +#define K_SYSCALL_FLASH_WRITE 29 +#define K_SYSCALL_GPIO_GET_PENDING_INT 30 +#define K_SYSCALL_GPIO_PIN_CONFIGURE 31 +#define K_SYSCALL_GPIO_PIN_GET_CONFIG 32 +#define K_SYSCALL_GPIO_PIN_INTERRUPT_CONFIGURE 33 +#define K_SYSCALL_GPIO_PORT_CLEAR_BITS_RAW 34 +#define K_SYSCALL_GPIO_PORT_GET_DIRECTION 35 +#define K_SYSCALL_GPIO_PORT_GET_RAW 36 +#define K_SYSCALL_GPIO_PORT_SET_BITS_RAW 37 +#define K_SYSCALL_GPIO_PORT_SET_MASKED_RAW 38 +#define K_SYSCALL_GPIO_PORT_TOGGLE_BITS 39 +#define K_SYSCALL_HWINFO_CLEAR_RESET_CAUSE 40 +#define K_SYSCALL_HWINFO_GET_DEVICE_EUI64 41 +#define K_SYSCALL_HWINFO_GET_DEVICE_ID 42 +#define K_SYSCALL_HWINFO_GET_RESET_CAUSE 43 +#define K_SYSCALL_HWINFO_GET_SUPPORTED_RESET_CAUSE 44 +#define K_SYSCALL_I2C_CONFIGURE 45 +#define K_SYSCALL_I2C_GET_CONFIG 46 +#define K_SYSCALL_I2C_RECOVER_BUS 47 +#define K_SYSCALL_I2C_TARGET_DRIVER_REGISTER 48 +#define K_SYSCALL_I2C_TARGET_DRIVER_UNREGISTER 49 +#define K_SYSCALL_I2C_TRANSFER 50 +#define K_SYSCALL_K_BUSY_WAIT 51 +#define K_SYSCALL_K_CONDVAR_BROADCAST 52 +#define K_SYSCALL_K_CONDVAR_INIT 53 +#define K_SYSCALL_K_CONDVAR_SIGNAL 54 +#define K_SYSCALL_K_CONDVAR_WAIT 55 +#define K_SYSCALL_K_EVENT_CLEAR 56 +#define K_SYSCALL_K_EVENT_INIT 57 +#define K_SYSCALL_K_EVENT_POST 58 +#define K_SYSCALL_K_EVENT_SET 59 +#define K_SYSCALL_K_EVENT_SET_MASKED 60 +#define K_SYSCALL_K_EVENT_WAIT 61 +#define K_SYSCALL_K_EVENT_WAIT_ALL 62 +#define K_SYSCALL_K_FLOAT_DISABLE 63 +#define K_SYSCALL_K_FLOAT_ENABLE 64 +#define K_SYSCALL_K_FUTEX_WAIT 65 +#define K_SYSCALL_K_FUTEX_WAKE 66 +#define K_SYSCALL_K_IS_PREEMPT_THREAD 67 +#define K_SYSCALL_K_MSGQ_ALLOC_INIT 68 +#define K_SYSCALL_K_MSGQ_GET 69 +#define K_SYSCALL_K_MSGQ_GET_ATTRS 70 +#define K_SYSCALL_K_MSGQ_NUM_FREE_GET 71 +#define K_SYSCALL_K_MSGQ_NUM_USED_GET 72 +#define K_SYSCALL_K_MSGQ_PEEK 73 +#define K_SYSCALL_K_MSGQ_PEEK_AT 74 +#define K_SYSCALL_K_MSGQ_PURGE 75 +#define K_SYSCALL_K_MSGQ_PUT 76 +#define K_SYSCALL_K_MUTEX_INIT 77 +#define K_SYSCALL_K_MUTEX_LOCK 78 +#define K_SYSCALL_K_MUTEX_UNLOCK 79 +#define K_SYSCALL_K_OBJECT_ACCESS_GRANT 80 +#define K_SYSCALL_K_OBJECT_ALLOC 81 +#define K_SYSCALL_K_OBJECT_ALLOC_SIZE 82 +#define K_SYSCALL_K_OBJECT_RELEASE 83 +#define K_SYSCALL_K_PIPE_ALLOC_INIT 84 +#define K_SYSCALL_K_PIPE_BUFFER_FLUSH 85 +#define K_SYSCALL_K_PIPE_FLUSH 86 +#define K_SYSCALL_K_PIPE_GET 87 +#define K_SYSCALL_K_PIPE_PUT 88 +#define K_SYSCALL_K_PIPE_READ_AVAIL 89 +#define K_SYSCALL_K_PIPE_WRITE_AVAIL 90 +#define K_SYSCALL_K_POLL 91 +#define K_SYSCALL_K_POLL_SIGNAL_CHECK 92 +#define K_SYSCALL_K_POLL_SIGNAL_INIT 93 +#define K_SYSCALL_K_POLL_SIGNAL_RAISE 94 +#define K_SYSCALL_K_POLL_SIGNAL_RESET 95 +#define K_SYSCALL_K_QUEUE_ALLOC_APPEND 96 +#define K_SYSCALL_K_QUEUE_ALLOC_PREPEND 97 +#define K_SYSCALL_K_QUEUE_CANCEL_WAIT 98 +#define K_SYSCALL_K_QUEUE_GET 99 +#define K_SYSCALL_K_QUEUE_INIT 100 +#define K_SYSCALL_K_QUEUE_IS_EMPTY 101 +#define K_SYSCALL_K_QUEUE_PEEK_HEAD 102 +#define K_SYSCALL_K_QUEUE_PEEK_TAIL 103 +#define K_SYSCALL_K_SCHED_CURRENT_THREAD_QUERY 104 +#define K_SYSCALL_K_SEM_COUNT_GET 105 +#define K_SYSCALL_K_SEM_GIVE 106 +#define K_SYSCALL_K_SEM_INIT 107 +#define K_SYSCALL_K_SEM_RESET 108 +#define K_SYSCALL_K_SEM_TAKE 109 +#define K_SYSCALL_K_SLEEP 110 +#define K_SYSCALL_K_STACK_ALLOC_INIT 111 +#define K_SYSCALL_K_STACK_POP 112 +#define K_SYSCALL_K_STACK_PUSH 113 +#define K_SYSCALL_K_STR_OUT 114 +#define K_SYSCALL_K_THREAD_ABORT 115 +#define K_SYSCALL_K_THREAD_CREATE 116 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_GET 117 +#define K_SYSCALL_K_THREAD_CUSTOM_DATA_SET 118 +#define K_SYSCALL_K_THREAD_DEADLINE_SET 119 +#define K_SYSCALL_K_THREAD_JOIN 120 +#define K_SYSCALL_K_THREAD_NAME_COPY 121 +#define K_SYSCALL_K_THREAD_NAME_SET 122 +#define K_SYSCALL_K_THREAD_PRIORITY_GET 123 +#define K_SYSCALL_K_THREAD_PRIORITY_SET 124 +#define K_SYSCALL_K_THREAD_RESUME 125 +#define K_SYSCALL_K_THREAD_STACK_ALLOC 126 +#define K_SYSCALL_K_THREAD_STACK_FREE 127 +#define K_SYSCALL_K_THREAD_STACK_SPACE_GET 128 +#define K_SYSCALL_K_THREAD_SUSPEND 129 +#define K_SYSCALL_K_THREAD_TIMEOUT_EXPIRES_TICKS 130 +#define K_SYSCALL_K_THREAD_TIMEOUT_REMAINING_TICKS 131 +#define K_SYSCALL_K_TIMER_EXPIRES_TICKS 132 +#define K_SYSCALL_K_TIMER_REMAINING_TICKS 133 +#define K_SYSCALL_K_TIMER_START 134 +#define K_SYSCALL_K_TIMER_STATUS_GET 135 +#define K_SYSCALL_K_TIMER_STATUS_SYNC 136 +#define K_SYSCALL_K_TIMER_STOP 137 +#define K_SYSCALL_K_TIMER_USER_DATA_GET 138 +#define K_SYSCALL_K_TIMER_USER_DATA_SET 139 +#define K_SYSCALL_K_UPTIME_TICKS 140 +#define K_SYSCALL_K_USLEEP 141 +#define K_SYSCALL_K_WAKEUP 142 +#define K_SYSCALL_K_YIELD 143 +#define K_SYSCALL_LLEXT_GET_FN_TABLE 144 +#define K_SYSCALL_LOG_BUFFERED_CNT 145 +#define K_SYSCALL_LOG_FILTER_SET 146 +#define K_SYSCALL_LOG_FRONTEND_FILTER_SET 147 +#define K_SYSCALL_LOG_PANIC 148 +#define K_SYSCALL_LOG_PROCESS 149 +#define K_SYSCALL_PWM_CAPTURE_CYCLES 150 +#define K_SYSCALL_PWM_DISABLE_CAPTURE 151 +#define K_SYSCALL_PWM_ENABLE_CAPTURE 152 +#define K_SYSCALL_PWM_GET_CYCLES_PER_SEC 153 +#define K_SYSCALL_PWM_SET_CYCLES 154 +#define K_SYSCALL_RESET_LINE_ASSERT 155 +#define K_SYSCALL_RESET_LINE_DEASSERT 156 +#define K_SYSCALL_RESET_LINE_TOGGLE 157 +#define K_SYSCALL_RESET_STATUS 158 +#define K_SYSCALL_SPI_RELEASE 159 +#define K_SYSCALL_SPI_TRANSCEIVE 160 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_AND_INVD_RANGE 161 +#define K_SYSCALL_SYS_CACHE_DATA_FLUSH_RANGE 162 +#define K_SYSCALL_SYS_CACHE_DATA_INVD_RANGE 163 +#define K_SYSCALL_SYS_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_GET 164 +#define K_SYSCALL_SYS_CSRAND_GET 165 +#define K_SYSCALL_SYS_RAND_GET 166 +#define K_SYSCALL_UART_CONFIGURE 167 +#define K_SYSCALL_UART_CONFIG_GET 168 +#define K_SYSCALL_UART_DRV_CMD 169 +#define K_SYSCALL_UART_ERR_CHECK 170 +#define K_SYSCALL_UART_IRQ_ERR_DISABLE 171 +#define K_SYSCALL_UART_IRQ_ERR_ENABLE 172 +#define K_SYSCALL_UART_IRQ_IS_PENDING 173 +#define K_SYSCALL_UART_IRQ_RX_DISABLE 174 +#define K_SYSCALL_UART_IRQ_RX_ENABLE 175 +#define K_SYSCALL_UART_IRQ_TX_DISABLE 176 +#define K_SYSCALL_UART_IRQ_TX_ENABLE 177 +#define K_SYSCALL_UART_IRQ_UPDATE 178 +#define K_SYSCALL_UART_LINE_CTRL_GET 179 +#define K_SYSCALL_UART_LINE_CTRL_SET 180 +#define K_SYSCALL_UART_POLL_IN 181 +#define K_SYSCALL_UART_POLL_IN_U16 182 +#define K_SYSCALL_UART_POLL_OUT 183 +#define K_SYSCALL_UART_POLL_OUT_U16 184 +#define K_SYSCALL_UART_RX_DISABLE 185 +#define K_SYSCALL_UART_RX_ENABLE 186 +#define K_SYSCALL_UART_RX_ENABLE_U16 187 +#define K_SYSCALL_UART_TX 188 +#define K_SYSCALL_UART_TX_ABORT 189 +#define K_SYSCALL_UART_TX_U16 190 +#define K_SYSCALL_ZEPHYR_FPUTC 191 +#define K_SYSCALL_ZEPHYR_FWRITE 192 +#define K_SYSCALL_ZEPHYR_READ_STDIN 193 +#define K_SYSCALL_ZEPHYR_WRITE_STDOUT 194 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_0 195 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_1 196 +#define K_SYSCALL_Z_LOG_MSG_SIMPLE_CREATE_2 197 +#define K_SYSCALL_Z_LOG_MSG_STATIC_CREATE 198 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_LOCK 199 +#define K_SYSCALL_Z_SYS_MUTEX_KERNEL_UNLOCK 200 +#define K_SYSCALL_BAD 201 +#define K_SYSCALL_LIMIT 202 /* Following syscalls are not used in image */ -#define K_SYSCALL_ATOMIC_ADD 199 -#define K_SYSCALL_ATOMIC_AND 200 -#define K_SYSCALL_ATOMIC_CAS 201 -#define K_SYSCALL_ATOMIC_NAND 202 -#define K_SYSCALL_ATOMIC_OR 203 -#define K_SYSCALL_ATOMIC_PTR_CAS 204 -#define K_SYSCALL_ATOMIC_PTR_SET 205 -#define K_SYSCALL_ATOMIC_SET 206 -#define K_SYSCALL_ATOMIC_SUB 207 -#define K_SYSCALL_ATOMIC_XOR 208 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 209 -#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 210 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 211 -#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 212 -#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 213 -#define K_SYSCALL_AUXDISPLAY_CLEAR 214 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 215 -#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 216 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 217 -#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 218 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 219 -#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 220 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 221 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 222 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 223 -#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 224 -#define K_SYSCALL_AUXDISPLAY_IS_BUSY 225 -#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 226 -#define K_SYSCALL_AUXDISPLAY_WRITE 227 -#define K_SYSCALL_BBRAM_CHECK_INVALID 228 -#define K_SYSCALL_BBRAM_CHECK_POWER 229 -#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 230 -#define K_SYSCALL_BBRAM_GET_SIZE 231 -#define K_SYSCALL_BBRAM_READ 232 -#define K_SYSCALL_BBRAM_WRITE 233 -#define K_SYSCALL_BC12_SET_RESULT_CB 234 -#define K_SYSCALL_BC12_SET_ROLE 235 -#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 236 -#define K_SYSCALL_CAN_CALC_TIMING 237 -#define K_SYSCALL_CAN_CALC_TIMING_DATA 238 -#define K_SYSCALL_CAN_GET_BITRATE_MAX 239 -#define K_SYSCALL_CAN_GET_BITRATE_MIN 240 -#define K_SYSCALL_CAN_GET_CAPABILITIES 241 -#define K_SYSCALL_CAN_GET_CORE_CLOCK 242 -#define K_SYSCALL_CAN_GET_MAX_FILTERS 243 -#define K_SYSCALL_CAN_GET_MODE 244 -#define K_SYSCALL_CAN_GET_STATE 245 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 246 -#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 247 -#define K_SYSCALL_CAN_GET_TIMING_MAX 248 -#define K_SYSCALL_CAN_GET_TIMING_MIN 249 -#define K_SYSCALL_CAN_GET_TRANSCEIVER 250 -#define K_SYSCALL_CAN_RECOVER 251 -#define K_SYSCALL_CAN_REMOVE_RX_FILTER 252 -#define K_SYSCALL_CAN_SEND 253 -#define K_SYSCALL_CAN_SET_BITRATE 254 -#define K_SYSCALL_CAN_SET_BITRATE_DATA 255 -#define K_SYSCALL_CAN_SET_MODE 256 -#define K_SYSCALL_CAN_SET_TIMING 257 -#define K_SYSCALL_CAN_SET_TIMING_DATA 258 -#define K_SYSCALL_CAN_START 259 -#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 260 -#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 261 -#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 262 -#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 263 -#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 264 -#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 265 -#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 266 -#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 267 -#define K_SYSCALL_CAN_STOP 268 -#define K_SYSCALL_CHARGER_CHARGE_ENABLE 269 -#define K_SYSCALL_CHARGER_GET_PROP 270 -#define K_SYSCALL_CHARGER_SET_PROP 271 -#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 272 -#define K_SYSCALL_COUNTER_GET_FREQUENCY 273 -#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 274 -#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 275 -#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 276 -#define K_SYSCALL_COUNTER_GET_PENDING_INT 277 -#define K_SYSCALL_COUNTER_GET_TOP_VALUE 278 -#define K_SYSCALL_COUNTER_GET_VALUE 279 -#define K_SYSCALL_COUNTER_GET_VALUE_64 280 -#define K_SYSCALL_COUNTER_IS_COUNTING_UP 281 -#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 282 -#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 283 -#define K_SYSCALL_COUNTER_SET_TOP_VALUE 284 -#define K_SYSCALL_COUNTER_START 285 -#define K_SYSCALL_COUNTER_STOP 286 -#define K_SYSCALL_COUNTER_TICKS_TO_US 287 -#define K_SYSCALL_COUNTER_US_TO_TICKS 288 -#define K_SYSCALL_DAC_CHANNEL_SETUP 289 -#define K_SYSCALL_DAC_WRITE_VALUE 290 -#define K_SYSCALL_DEVMUX_SELECT_GET 291 -#define K_SYSCALL_DEVMUX_SELECT_SET 292 -#define K_SYSCALL_EEPROM_GET_SIZE 293 -#define K_SYSCALL_EEPROM_READ 294 -#define K_SYSCALL_EEPROM_WRITE 295 -#define K_SYSCALL_EMUL_FUEL_GAUGE_IS_BATTERY_CUTOFF 296 -#define K_SYSCALL_EMUL_FUEL_GAUGE_SET_BATTERY_CHARGING 297 -#define K_SYSCALL_ENTROPY_GET_ENTROPY 298 -#define K_SYSCALL_ESPI_CONFIG 299 -#define K_SYSCALL_ESPI_FLASH_ERASE 300 -#define K_SYSCALL_ESPI_GET_CHANNEL_STATUS 301 -#define K_SYSCALL_ESPI_READ_FLASH 302 -#define K_SYSCALL_ESPI_READ_LPC_REQUEST 303 -#define K_SYSCALL_ESPI_READ_REQUEST 304 -#define K_SYSCALL_ESPI_RECEIVE_OOB 305 -#define K_SYSCALL_ESPI_RECEIVE_VWIRE 306 -#define K_SYSCALL_ESPI_SAF_ACTIVATE 307 -#define K_SYSCALL_ESPI_SAF_CONFIG 308 -#define K_SYSCALL_ESPI_SAF_FLASH_ERASE 309 -#define K_SYSCALL_ESPI_SAF_FLASH_READ 310 -#define K_SYSCALL_ESPI_SAF_FLASH_UNSUCCESS 311 -#define K_SYSCALL_ESPI_SAF_FLASH_WRITE 312 -#define K_SYSCALL_ESPI_SAF_GET_CHANNEL_STATUS 313 -#define K_SYSCALL_ESPI_SAF_SET_PROTECTION_REGIONS 314 -#define K_SYSCALL_ESPI_SEND_OOB 315 -#define K_SYSCALL_ESPI_SEND_VWIRE 316 -#define K_SYSCALL_ESPI_WRITE_FLASH 317 -#define K_SYSCALL_ESPI_WRITE_LPC_REQUEST 318 -#define K_SYSCALL_ESPI_WRITE_REQUEST 319 -#define K_SYSCALL_FLASH_SIMULATOR_GET_MEMORY 320 -#define K_SYSCALL_FUEL_GAUGE_BATTERY_CUTOFF 321 -#define K_SYSCALL_FUEL_GAUGE_GET_BUFFER_PROP 322 -#define K_SYSCALL_FUEL_GAUGE_GET_PROP 323 -#define K_SYSCALL_FUEL_GAUGE_GET_PROPS 324 -#define K_SYSCALL_FUEL_GAUGE_SET_PROP 325 -#define K_SYSCALL_FUEL_GAUGE_SET_PROPS 326 -#define K_SYSCALL_GNSS_GET_ENABLED_SYSTEMS 327 -#define K_SYSCALL_GNSS_GET_FIX_RATE 328 -#define K_SYSCALL_GNSS_GET_NAVIGATION_MODE 329 -#define K_SYSCALL_GNSS_GET_PERIODIC_CONFIG 330 -#define K_SYSCALL_GNSS_GET_SUPPORTED_SYSTEMS 331 -#define K_SYSCALL_GNSS_SET_ENABLED_SYSTEMS 332 -#define K_SYSCALL_GNSS_SET_FIX_RATE 333 -#define K_SYSCALL_GNSS_SET_NAVIGATION_MODE 334 -#define K_SYSCALL_GNSS_SET_PERIODIC_CONFIG 335 -#define K_SYSCALL_HWSPINLOCK_GET_MAX_ID 336 -#define K_SYSCALL_HWSPINLOCK_LOCK 337 -#define K_SYSCALL_HWSPINLOCK_TRYLOCK 338 -#define K_SYSCALL_HWSPINLOCK_UNLOCK 339 -#define K_SYSCALL_I2S_BUF_READ 340 -#define K_SYSCALL_I2S_BUF_WRITE 341 -#define K_SYSCALL_I2S_CONFIGURE 342 -#define K_SYSCALL_I2S_TRIGGER 343 -#define K_SYSCALL_I3C_DO_CCC 344 -#define K_SYSCALL_I3C_TRANSFER 345 -#define K_SYSCALL_IPM_COMPLETE 346 -#define K_SYSCALL_IPM_MAX_DATA_SIZE_GET 347 -#define K_SYSCALL_IPM_MAX_ID_VAL_GET 348 -#define K_SYSCALL_IPM_SEND 349 -#define K_SYSCALL_IPM_SET_ENABLED 350 -#define K_SYSCALL_IVSHMEM_ENABLE_INTERRUPTS 351 -#define K_SYSCALL_IVSHMEM_GET_ID 352 -#define K_SYSCALL_IVSHMEM_GET_MAX_PEERS 353 -#define K_SYSCALL_IVSHMEM_GET_MEM 354 -#define K_SYSCALL_IVSHMEM_GET_OUTPUT_MEM_SECTION 355 -#define K_SYSCALL_IVSHMEM_GET_PROTOCOL 356 -#define K_SYSCALL_IVSHMEM_GET_RW_MEM_SECTION 357 -#define K_SYSCALL_IVSHMEM_GET_STATE 358 -#define K_SYSCALL_IVSHMEM_GET_VECTORS 359 -#define K_SYSCALL_IVSHMEM_INT_PEER 360 -#define K_SYSCALL_IVSHMEM_REGISTER_HANDLER 361 -#define K_SYSCALL_IVSHMEM_SET_STATE 362 -#define K_SYSCALL_KSCAN_CONFIG 363 -#define K_SYSCALL_KSCAN_DISABLE_CALLBACK 364 -#define K_SYSCALL_KSCAN_ENABLE_CALLBACK 365 -#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_IN_GET 366 -#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_OUT_GET 367 -#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_EVICTION_GET 368 -#define K_SYSCALL_K_MEM_PAGING_STATS_GET 369 -#define K_SYSCALL_K_MEM_PAGING_THREAD_STATS_GET 370 -#define K_SYSCALL_LED_BLINK 371 -#define K_SYSCALL_LED_GET_INFO 372 -#define K_SYSCALL_LED_OFF 373 -#define K_SYSCALL_LED_ON 374 -#define K_SYSCALL_LED_SET_BRIGHTNESS 375 -#define K_SYSCALL_LED_SET_CHANNEL 376 -#define K_SYSCALL_LED_SET_COLOR 377 -#define K_SYSCALL_LED_WRITE_CHANNELS 378 -#define K_SYSCALL_MAXIM_DS3231_GET_SYNCPOINT 379 -#define K_SYSCALL_MAXIM_DS3231_REQ_SYNCPOINT 380 -#define K_SYSCALL_MBOX_MAX_CHANNELS_GET 381 -#define K_SYSCALL_MBOX_MTU_GET 382 -#define K_SYSCALL_MBOX_SEND 383 -#define K_SYSCALL_MBOX_SET_ENABLED 384 -#define K_SYSCALL_MDIO_BUS_DISABLE 385 -#define K_SYSCALL_MDIO_BUS_ENABLE 386 -#define K_SYSCALL_MDIO_READ 387 -#define K_SYSCALL_MDIO_READ_C45 388 -#define K_SYSCALL_MDIO_WRITE 389 -#define K_SYSCALL_MDIO_WRITE_C45 390 -#define K_SYSCALL_MSPI_CONFIG 391 -#define K_SYSCALL_MSPI_DEV_CONFIG 392 -#define K_SYSCALL_MSPI_GET_CHANNEL_STATUS 393 -#define K_SYSCALL_MSPI_SCRAMBLE_CONFIG 394 -#define K_SYSCALL_MSPI_TIMING_CONFIG 395 -#define K_SYSCALL_MSPI_TRANSCEIVE 396 -#define K_SYSCALL_MSPI_XIP_CONFIG 397 -#define K_SYSCALL_NET_ADDR_NTOP 398 -#define K_SYSCALL_NET_ADDR_PTON 399 -#define K_SYSCALL_NET_ETH_GET_PTP_CLOCK_BY_INDEX 400 -#define K_SYSCALL_NET_IF_GET_BY_INDEX 401 -#define K_SYSCALL_NET_IF_IPV4_ADDR_ADD_BY_INDEX 402 -#define K_SYSCALL_NET_IF_IPV4_ADDR_LOOKUP_BY_INDEX 403 -#define K_SYSCALL_NET_IF_IPV4_ADDR_RM_BY_INDEX 404 -#define K_SYSCALL_NET_IF_IPV4_SET_GW_BY_INDEX 405 -#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_ADDR_BY_INDEX 406 -#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_INDEX 407 -#define K_SYSCALL_NET_IF_IPV6_ADDR_ADD_BY_INDEX 408 -#define K_SYSCALL_NET_IF_IPV6_ADDR_LOOKUP_BY_INDEX 409 -#define K_SYSCALL_NET_IF_IPV6_ADDR_RM_BY_INDEX 410 -#define K_SYSCALL_NET_SOCKET_SERVICE_REGISTER 411 -#define K_SYSCALL_NRF_QSPI_NOR_XIP_ENABLE 412 -#define K_SYSCALL_PECI_CONFIG 413 -#define K_SYSCALL_PECI_DISABLE 414 -#define K_SYSCALL_PECI_ENABLE 415 -#define K_SYSCALL_PECI_TRANSFER 416 -#define K_SYSCALL_PS2_CONFIG 417 -#define K_SYSCALL_PS2_DISABLE_CALLBACK 418 -#define K_SYSCALL_PS2_ENABLE_CALLBACK 419 -#define K_SYSCALL_PS2_READ 420 -#define K_SYSCALL_PS2_WRITE 421 -#define K_SYSCALL_PTP_CLOCK_GET 422 -#define K_SYSCALL_RETAINED_MEM_CLEAR 423 -#define K_SYSCALL_RETAINED_MEM_READ 424 -#define K_SYSCALL_RETAINED_MEM_SIZE 425 -#define K_SYSCALL_RETAINED_MEM_WRITE 426 -#define K_SYSCALL_RTC_ALARM_GET_SUPPORTED_FIELDS 427 -#define K_SYSCALL_RTC_ALARM_GET_TIME 428 -#define K_SYSCALL_RTC_ALARM_IS_PENDING 429 -#define K_SYSCALL_RTC_ALARM_SET_CALLBACK 430 -#define K_SYSCALL_RTC_ALARM_SET_TIME 431 -#define K_SYSCALL_RTC_GET_CALIBRATION 432 -#define K_SYSCALL_RTC_GET_TIME 433 -#define K_SYSCALL_RTC_SET_CALIBRATION 434 -#define K_SYSCALL_RTC_SET_TIME 435 -#define K_SYSCALL_RTC_UPDATE_SET_CALLBACK 436 -#define K_SYSCALL_RTIO_CQE_COPY_OUT 437 -#define K_SYSCALL_RTIO_CQE_GET_MEMPOOL_BUFFER 438 -#define K_SYSCALL_RTIO_RELEASE_BUFFER 439 -#define K_SYSCALL_RTIO_SQE_CANCEL 440 -#define K_SYSCALL_RTIO_SQE_COPY_IN_GET_HANDLES 441 -#define K_SYSCALL_RTIO_SUBMIT 442 -#define K_SYSCALL_SDHC_CARD_BUSY 443 -#define K_SYSCALL_SDHC_CARD_PRESENT 444 -#define K_SYSCALL_SDHC_DISABLE_INTERRUPT 445 -#define K_SYSCALL_SDHC_ENABLE_INTERRUPT 446 -#define K_SYSCALL_SDHC_EXECUTE_TUNING 447 -#define K_SYSCALL_SDHC_GET_HOST_PROPS 448 -#define K_SYSCALL_SDHC_HW_RESET 449 -#define K_SYSCALL_SDHC_REQUEST 450 -#define K_SYSCALL_SDHC_SET_IO 451 -#define K_SYSCALL_SENSOR_ATTR_GET 452 -#define K_SYSCALL_SENSOR_ATTR_SET 453 -#define K_SYSCALL_SENSOR_CHANNEL_GET 454 -#define K_SYSCALL_SENSOR_GET_DECODER 455 -#define K_SYSCALL_SENSOR_RECONFIGURE_READ_IODEV 456 -#define K_SYSCALL_SENSOR_SAMPLE_FETCH 457 -#define K_SYSCALL_SENSOR_SAMPLE_FETCH_CHAN 458 -#define K_SYSCALL_SIP_SUPERVISORY_CALL 459 -#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_REQ 460 -#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_RES 461 -#define K_SYSCALL_SIP_SVC_PLAT_FORMAT_TRANS_ID 462 -#define K_SYSCALL_SIP_SVC_PLAT_FREE_ASYNC_MEMORY 463 -#define K_SYSCALL_SIP_SVC_PLAT_FUNC_ID_VALID 464 -#define K_SYSCALL_SIP_SVC_PLAT_GET_ERROR_CODE 465 -#define K_SYSCALL_SIP_SVC_PLAT_GET_TRANS_IDX 466 -#define K_SYSCALL_SIP_SVC_PLAT_UPDATE_TRANS_ID 467 -#define K_SYSCALL_SMBUS_BLOCK_PCALL 468 -#define K_SYSCALL_SMBUS_BLOCK_READ 469 -#define K_SYSCALL_SMBUS_BLOCK_WRITE 470 -#define K_SYSCALL_SMBUS_BYTE_DATA_READ 471 -#define K_SYSCALL_SMBUS_BYTE_DATA_WRITE 472 -#define K_SYSCALL_SMBUS_BYTE_READ 473 -#define K_SYSCALL_SMBUS_BYTE_WRITE 474 -#define K_SYSCALL_SMBUS_CONFIGURE 475 -#define K_SYSCALL_SMBUS_GET_CONFIG 476 -#define K_SYSCALL_SMBUS_HOST_NOTIFY_REMOVE_CB 477 -#define K_SYSCALL_SMBUS_PCALL 478 -#define K_SYSCALL_SMBUS_QUICK 479 -#define K_SYSCALL_SMBUS_SMBALERT_REMOVE_CB 480 -#define K_SYSCALL_SMBUS_WORD_DATA_READ 481 -#define K_SYSCALL_SMBUS_WORD_DATA_WRITE 482 -#define K_SYSCALL_SYSCON_GET_BASE 483 -#define K_SYSCALL_SYSCON_GET_SIZE 484 -#define K_SYSCALL_SYSCON_READ_REG 485 -#define K_SYSCALL_SYSCON_WRITE_REG 486 -#define K_SYSCALL_SYS_CSRAND_GET 487 -#define K_SYSCALL_SYS_RAND_GET 488 -#define K_SYSCALL_TEE_CANCEL 489 -#define K_SYSCALL_TEE_CLOSE_SESSION 490 -#define K_SYSCALL_TEE_GET_VERSION 491 -#define K_SYSCALL_TEE_INVOKE_FUNC 492 -#define K_SYSCALL_TEE_OPEN_SESSION 493 -#define K_SYSCALL_TEE_SHM_ALLOC 494 -#define K_SYSCALL_TEE_SHM_FREE 495 -#define K_SYSCALL_TEE_SHM_REGISTER 496 -#define K_SYSCALL_TEE_SHM_UNREGISTER 497 -#define K_SYSCALL_TEE_SUPPL_RECV 498 -#define K_SYSCALL_TEE_SUPPL_SEND 499 -#define K_SYSCALL_TGPIO_PIN_CONFIG_EXT_TIMESTAMP 500 -#define K_SYSCALL_TGPIO_PIN_DISABLE 501 -#define K_SYSCALL_TGPIO_PIN_PERIODIC_OUTPUT 502 -#define K_SYSCALL_TGPIO_PIN_READ_TS_EC 503 -#define K_SYSCALL_TGPIO_PORT_GET_CYCLES_PER_SECOND 504 -#define K_SYSCALL_TGPIO_PORT_GET_TIME 505 -#define K_SYSCALL_UPDATEHUB_AUTOHANDLER 506 -#define K_SYSCALL_UPDATEHUB_CONFIRM 507 -#define K_SYSCALL_UPDATEHUB_PROBE 508 -#define K_SYSCALL_UPDATEHUB_REBOOT 509 -#define K_SYSCALL_UPDATEHUB_UPDATE 510 -#define K_SYSCALL_USER_FAULT 511 -#define K_SYSCALL_W1_CHANGE_BUS_LOCK 512 -#define K_SYSCALL_W1_CONFIGURE 513 -#define K_SYSCALL_W1_GET_SLAVE_COUNT 514 -#define K_SYSCALL_W1_READ_BIT 515 -#define K_SYSCALL_W1_READ_BLOCK 516 -#define K_SYSCALL_W1_READ_BYTE 517 -#define K_SYSCALL_W1_RESET_BUS 518 -#define K_SYSCALL_W1_SEARCH_BUS 519 -#define K_SYSCALL_W1_WRITE_BIT 520 -#define K_SYSCALL_W1_WRITE_BLOCK 521 -#define K_SYSCALL_W1_WRITE_BYTE 522 -#define K_SYSCALL_WDT_DISABLE 523 -#define K_SYSCALL_WDT_FEED 524 -#define K_SYSCALL_WDT_SETUP 525 -#define K_SYSCALL_XTENSA_USER_FAULT 526 -#define K_SYSCALL_ZSOCK_ACCEPT 527 -#define K_SYSCALL_ZSOCK_BIND 528 -#define K_SYSCALL_ZSOCK_CLOSE 529 -#define K_SYSCALL_ZSOCK_CONNECT 530 -#define K_SYSCALL_ZSOCK_FCNTL_IMPL 531 -#define K_SYSCALL_ZSOCK_GETHOSTNAME 532 -#define K_SYSCALL_ZSOCK_GETPEERNAME 533 -#define K_SYSCALL_ZSOCK_GETSOCKNAME 534 -#define K_SYSCALL_ZSOCK_GETSOCKOPT 535 -#define K_SYSCALL_ZSOCK_GET_CONTEXT_OBJECT 536 -#define K_SYSCALL_ZSOCK_INET_PTON 537 -#define K_SYSCALL_ZSOCK_IOCTL_IMPL 538 -#define K_SYSCALL_ZSOCK_LISTEN 539 -#define K_SYSCALL_ZSOCK_POLL 540 -#define K_SYSCALL_ZSOCK_RECVFROM 541 -#define K_SYSCALL_ZSOCK_RECVMSG 542 -#define K_SYSCALL_ZSOCK_SELECT 543 -#define K_SYSCALL_ZSOCK_SENDMSG 544 -#define K_SYSCALL_ZSOCK_SENDTO 545 -#define K_SYSCALL_ZSOCK_SETSOCKOPT 546 -#define K_SYSCALL_ZSOCK_SHUTDOWN 547 -#define K_SYSCALL_ZSOCK_SOCKET 548 -#define K_SYSCALL_ZSOCK_SOCKETPAIR 549 -#define K_SYSCALL_Z_ERRNO 550 -#define K_SYSCALL_Z_ZSOCK_GETADDRINFO_INTERNAL 551 +#define K_SYSCALL_ATOMIC_ADD 203 +#define K_SYSCALL_ATOMIC_AND 204 +#define K_SYSCALL_ATOMIC_CAS 205 +#define K_SYSCALL_ATOMIC_NAND 206 +#define K_SYSCALL_ATOMIC_OR 207 +#define K_SYSCALL_ATOMIC_PTR_CAS 208 +#define K_SYSCALL_ATOMIC_PTR_SET 209 +#define K_SYSCALL_ATOMIC_SET 210 +#define K_SYSCALL_ATOMIC_SUB 211 +#define K_SYSCALL_ATOMIC_XOR 212 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_GET 213 +#define K_SYSCALL_AUXDISPLAY_BACKLIGHT_SET 214 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_GET 215 +#define K_SYSCALL_AUXDISPLAY_BRIGHTNESS_SET 216 +#define K_SYSCALL_AUXDISPLAY_CAPABILITIES_GET 217 +#define K_SYSCALL_AUXDISPLAY_CLEAR 218 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_GET 219 +#define K_SYSCALL_AUXDISPLAY_CURSOR_POSITION_SET 220 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SET_ENABLED 221 +#define K_SYSCALL_AUXDISPLAY_CURSOR_SHIFT_SET 222 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_CHARACTER_SET 223 +#define K_SYSCALL_AUXDISPLAY_CUSTOM_COMMAND 224 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_OFF 225 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_ON 226 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_GET 227 +#define K_SYSCALL_AUXDISPLAY_DISPLAY_POSITION_SET 228 +#define K_SYSCALL_AUXDISPLAY_IS_BUSY 229 +#define K_SYSCALL_AUXDISPLAY_POSITION_BLINKING_SET_ENABLED 230 +#define K_SYSCALL_AUXDISPLAY_WRITE 231 +#define K_SYSCALL_BBRAM_CHECK_INVALID 232 +#define K_SYSCALL_BBRAM_CHECK_POWER 233 +#define K_SYSCALL_BBRAM_CHECK_STANDBY_POWER 234 +#define K_SYSCALL_BBRAM_GET_SIZE 235 +#define K_SYSCALL_BBRAM_READ 236 +#define K_SYSCALL_BBRAM_WRITE 237 +#define K_SYSCALL_BC12_SET_RESULT_CB 238 +#define K_SYSCALL_BC12_SET_ROLE 239 +#define K_SYSCALL_CAN_ADD_RX_FILTER_MSGQ 240 +#define K_SYSCALL_CAN_CALC_TIMING 241 +#define K_SYSCALL_CAN_CALC_TIMING_DATA 242 +#define K_SYSCALL_CAN_GET_BITRATE_MAX 243 +#define K_SYSCALL_CAN_GET_BITRATE_MIN 244 +#define K_SYSCALL_CAN_GET_CAPABILITIES 245 +#define K_SYSCALL_CAN_GET_CORE_CLOCK 246 +#define K_SYSCALL_CAN_GET_MAX_FILTERS 247 +#define K_SYSCALL_CAN_GET_MODE 248 +#define K_SYSCALL_CAN_GET_STATE 249 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MAX 250 +#define K_SYSCALL_CAN_GET_TIMING_DATA_MIN 251 +#define K_SYSCALL_CAN_GET_TIMING_MAX 252 +#define K_SYSCALL_CAN_GET_TIMING_MIN 253 +#define K_SYSCALL_CAN_GET_TRANSCEIVER 254 +#define K_SYSCALL_CAN_RECOVER 255 +#define K_SYSCALL_CAN_REMOVE_RX_FILTER 256 +#define K_SYSCALL_CAN_SEND 257 +#define K_SYSCALL_CAN_SET_BITRATE 258 +#define K_SYSCALL_CAN_SET_BITRATE_DATA 259 +#define K_SYSCALL_CAN_SET_MODE 260 +#define K_SYSCALL_CAN_SET_TIMING 261 +#define K_SYSCALL_CAN_SET_TIMING_DATA 262 +#define K_SYSCALL_CAN_START 263 +#define K_SYSCALL_CAN_STATS_GET_ACK_ERRORS 264 +#define K_SYSCALL_CAN_STATS_GET_BIT0_ERRORS 265 +#define K_SYSCALL_CAN_STATS_GET_BIT1_ERRORS 266 +#define K_SYSCALL_CAN_STATS_GET_BIT_ERRORS 267 +#define K_SYSCALL_CAN_STATS_GET_CRC_ERRORS 268 +#define K_SYSCALL_CAN_STATS_GET_FORM_ERRORS 269 +#define K_SYSCALL_CAN_STATS_GET_RX_OVERRUNS 270 +#define K_SYSCALL_CAN_STATS_GET_STUFF_ERRORS 271 +#define K_SYSCALL_CAN_STOP 272 +#define K_SYSCALL_CHARGER_CHARGE_ENABLE 273 +#define K_SYSCALL_CHARGER_GET_PROP 274 +#define K_SYSCALL_CHARGER_SET_PROP 275 +#define K_SYSCALL_COMPARATOR_GET_OUTPUT 276 +#define K_SYSCALL_COMPARATOR_SET_TRIGGER 277 +#define K_SYSCALL_COMPARATOR_TRIGGER_IS_PENDING 278 +#define K_SYSCALL_COUNTER_CANCEL_CHANNEL_ALARM 279 +#define K_SYSCALL_COUNTER_GET_FREQUENCY 280 +#define K_SYSCALL_COUNTER_GET_GUARD_PERIOD 281 +#define K_SYSCALL_COUNTER_GET_MAX_TOP_VALUE 282 +#define K_SYSCALL_COUNTER_GET_NUM_OF_CHANNELS 283 +#define K_SYSCALL_COUNTER_GET_PENDING_INT 284 +#define K_SYSCALL_COUNTER_GET_TOP_VALUE 285 +#define K_SYSCALL_COUNTER_GET_VALUE 286 +#define K_SYSCALL_COUNTER_GET_VALUE_64 287 +#define K_SYSCALL_COUNTER_IS_COUNTING_UP 288 +#define K_SYSCALL_COUNTER_SET_CHANNEL_ALARM 289 +#define K_SYSCALL_COUNTER_SET_GUARD_PERIOD 290 +#define K_SYSCALL_COUNTER_SET_TOP_VALUE 291 +#define K_SYSCALL_COUNTER_START 292 +#define K_SYSCALL_COUNTER_STOP 293 +#define K_SYSCALL_COUNTER_TICKS_TO_US 294 +#define K_SYSCALL_COUNTER_US_TO_TICKS 295 +#define K_SYSCALL_DAC_CHANNEL_SETUP 296 +#define K_SYSCALL_DAC_WRITE_VALUE 297 +#define K_SYSCALL_DEVMUX_SELECT_GET 298 +#define K_SYSCALL_DEVMUX_SELECT_SET 299 +#define K_SYSCALL_EEPROM_GET_SIZE 300 +#define K_SYSCALL_EEPROM_READ 301 +#define K_SYSCALL_EEPROM_WRITE 302 +#define K_SYSCALL_EMUL_FUEL_GAUGE_IS_BATTERY_CUTOFF 303 +#define K_SYSCALL_EMUL_FUEL_GAUGE_SET_BATTERY_CHARGING 304 +#define K_SYSCALL_ESPI_CONFIG 305 +#define K_SYSCALL_ESPI_FLASH_ERASE 306 +#define K_SYSCALL_ESPI_GET_CHANNEL_STATUS 307 +#define K_SYSCALL_ESPI_READ_FLASH 308 +#define K_SYSCALL_ESPI_READ_LPC_REQUEST 309 +#define K_SYSCALL_ESPI_READ_REQUEST 310 +#define K_SYSCALL_ESPI_RECEIVE_OOB 311 +#define K_SYSCALL_ESPI_RECEIVE_VWIRE 312 +#define K_SYSCALL_ESPI_SAF_ACTIVATE 313 +#define K_SYSCALL_ESPI_SAF_CONFIG 314 +#define K_SYSCALL_ESPI_SAF_FLASH_ERASE 315 +#define K_SYSCALL_ESPI_SAF_FLASH_READ 316 +#define K_SYSCALL_ESPI_SAF_FLASH_UNSUCCESS 317 +#define K_SYSCALL_ESPI_SAF_FLASH_WRITE 318 +#define K_SYSCALL_ESPI_SAF_GET_CHANNEL_STATUS 319 +#define K_SYSCALL_ESPI_SAF_SET_PROTECTION_REGIONS 320 +#define K_SYSCALL_ESPI_SEND_OOB 321 +#define K_SYSCALL_ESPI_SEND_VWIRE 322 +#define K_SYSCALL_ESPI_WRITE_FLASH 323 +#define K_SYSCALL_ESPI_WRITE_LPC_REQUEST 324 +#define K_SYSCALL_ESPI_WRITE_REQUEST 325 +#define K_SYSCALL_FLASH_SIMULATOR_GET_MEMORY 326 +#define K_SYSCALL_FUEL_GAUGE_BATTERY_CUTOFF 327 +#define K_SYSCALL_FUEL_GAUGE_GET_BUFFER_PROP 328 +#define K_SYSCALL_FUEL_GAUGE_GET_PROP 329 +#define K_SYSCALL_FUEL_GAUGE_GET_PROPS 330 +#define K_SYSCALL_FUEL_GAUGE_SET_PROP 331 +#define K_SYSCALL_FUEL_GAUGE_SET_PROPS 332 +#define K_SYSCALL_GNSS_GET_ENABLED_SYSTEMS 333 +#define K_SYSCALL_GNSS_GET_FIX_RATE 334 +#define K_SYSCALL_GNSS_GET_LATEST_TIMEPULSE 335 +#define K_SYSCALL_GNSS_GET_NAVIGATION_MODE 336 +#define K_SYSCALL_GNSS_GET_SUPPORTED_SYSTEMS 337 +#define K_SYSCALL_GNSS_SET_ENABLED_SYSTEMS 338 +#define K_SYSCALL_GNSS_SET_FIX_RATE 339 +#define K_SYSCALL_GNSS_SET_NAVIGATION_MODE 340 +#define K_SYSCALL_HAPTICS_START_OUTPUT 341 +#define K_SYSCALL_HAPTICS_STOP_OUTPUT 342 +#define K_SYSCALL_HWSPINLOCK_GET_MAX_ID 343 +#define K_SYSCALL_HWSPINLOCK_LOCK 344 +#define K_SYSCALL_HWSPINLOCK_TRYLOCK 345 +#define K_SYSCALL_HWSPINLOCK_UNLOCK 346 +#define K_SYSCALL_I2S_BUF_READ 347 +#define K_SYSCALL_I2S_BUF_WRITE 348 +#define K_SYSCALL_I2S_CONFIGURE 349 +#define K_SYSCALL_I2S_TRIGGER 350 +#define K_SYSCALL_I3C_DO_CCC 351 +#define K_SYSCALL_I3C_TRANSFER 352 +#define K_SYSCALL_IPM_COMPLETE 353 +#define K_SYSCALL_IPM_MAX_DATA_SIZE_GET 354 +#define K_SYSCALL_IPM_MAX_ID_VAL_GET 355 +#define K_SYSCALL_IPM_SEND 356 +#define K_SYSCALL_IPM_SET_ENABLED 357 +#define K_SYSCALL_IVSHMEM_ENABLE_INTERRUPTS 358 +#define K_SYSCALL_IVSHMEM_GET_ID 359 +#define K_SYSCALL_IVSHMEM_GET_MAX_PEERS 360 +#define K_SYSCALL_IVSHMEM_GET_MEM 361 +#define K_SYSCALL_IVSHMEM_GET_OUTPUT_MEM_SECTION 362 +#define K_SYSCALL_IVSHMEM_GET_PROTOCOL 363 +#define K_SYSCALL_IVSHMEM_GET_RW_MEM_SECTION 364 +#define K_SYSCALL_IVSHMEM_GET_STATE 365 +#define K_SYSCALL_IVSHMEM_GET_VECTORS 366 +#define K_SYSCALL_IVSHMEM_INT_PEER 367 +#define K_SYSCALL_IVSHMEM_REGISTER_HANDLER 368 +#define K_SYSCALL_IVSHMEM_SET_STATE 369 +#define K_SYSCALL_KSCAN_CONFIG 370 +#define K_SYSCALL_KSCAN_DISABLE_CALLBACK 371 +#define K_SYSCALL_KSCAN_ENABLE_CALLBACK 372 +#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_IN_GET 373 +#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_BACKING_STORE_PAGE_OUT_GET 374 +#define K_SYSCALL_K_MEM_PAGING_HISTOGRAM_EVICTION_GET 375 +#define K_SYSCALL_K_MEM_PAGING_STATS_GET 376 +#define K_SYSCALL_K_MEM_PAGING_THREAD_STATS_GET 377 +#define K_SYSCALL_LED_BLINK 378 +#define K_SYSCALL_LED_GET_INFO 379 +#define K_SYSCALL_LED_OFF 380 +#define K_SYSCALL_LED_ON 381 +#define K_SYSCALL_LED_SET_BRIGHTNESS 382 +#define K_SYSCALL_LED_SET_CHANNEL 383 +#define K_SYSCALL_LED_SET_COLOR 384 +#define K_SYSCALL_LED_WRITE_CHANNELS 385 +#define K_SYSCALL_MAXIM_DS3231_GET_SYNCPOINT 386 +#define K_SYSCALL_MAXIM_DS3231_REQ_SYNCPOINT 387 +#define K_SYSCALL_MBOX_MAX_CHANNELS_GET 388 +#define K_SYSCALL_MBOX_MTU_GET 389 +#define K_SYSCALL_MBOX_SEND 390 +#define K_SYSCALL_MBOX_SET_ENABLED 391 +#define K_SYSCALL_MDIO_BUS_DISABLE 392 +#define K_SYSCALL_MDIO_BUS_ENABLE 393 +#define K_SYSCALL_MDIO_READ 394 +#define K_SYSCALL_MDIO_READ_C45 395 +#define K_SYSCALL_MDIO_WRITE 396 +#define K_SYSCALL_MDIO_WRITE_C45 397 +#define K_SYSCALL_MSPI_CONFIG 398 +#define K_SYSCALL_MSPI_DEV_CONFIG 399 +#define K_SYSCALL_MSPI_GET_CHANNEL_STATUS 400 +#define K_SYSCALL_MSPI_SCRAMBLE_CONFIG 401 +#define K_SYSCALL_MSPI_TIMING_CONFIG 402 +#define K_SYSCALL_MSPI_TRANSCEIVE 403 +#define K_SYSCALL_MSPI_XIP_CONFIG 404 +#define K_SYSCALL_NET_ADDR_NTOP 405 +#define K_SYSCALL_NET_ADDR_PTON 406 +#define K_SYSCALL_NET_ETH_GET_PTP_CLOCK_BY_INDEX 407 +#define K_SYSCALL_NET_IF_GET_BY_INDEX 408 +#define K_SYSCALL_NET_IF_IPV4_ADDR_ADD_BY_INDEX 409 +#define K_SYSCALL_NET_IF_IPV4_ADDR_LOOKUP_BY_INDEX 410 +#define K_SYSCALL_NET_IF_IPV4_ADDR_RM_BY_INDEX 411 +#define K_SYSCALL_NET_IF_IPV4_SET_GW_BY_INDEX 412 +#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_ADDR_BY_INDEX 413 +#define K_SYSCALL_NET_IF_IPV4_SET_NETMASK_BY_INDEX 414 +#define K_SYSCALL_NET_IF_IPV6_ADDR_ADD_BY_INDEX 415 +#define K_SYSCALL_NET_IF_IPV6_ADDR_LOOKUP_BY_INDEX 416 +#define K_SYSCALL_NET_IF_IPV6_ADDR_RM_BY_INDEX 417 +#define K_SYSCALL_NET_SOCKET_SERVICE_REGISTER 418 +#define K_SYSCALL_NRF_QSPI_NOR_XIP_ENABLE 419 +#define K_SYSCALL_PECI_CONFIG 420 +#define K_SYSCALL_PECI_DISABLE 421 +#define K_SYSCALL_PECI_ENABLE 422 +#define K_SYSCALL_PECI_TRANSFER 423 +#define K_SYSCALL_PS2_CONFIG 424 +#define K_SYSCALL_PS2_DISABLE_CALLBACK 425 +#define K_SYSCALL_PS2_ENABLE_CALLBACK 426 +#define K_SYSCALL_PS2_READ 427 +#define K_SYSCALL_PS2_WRITE 428 +#define K_SYSCALL_PTP_CLOCK_GET 429 +#define K_SYSCALL_RETAINED_MEM_CLEAR 430 +#define K_SYSCALL_RETAINED_MEM_READ 431 +#define K_SYSCALL_RETAINED_MEM_SIZE 432 +#define K_SYSCALL_RETAINED_MEM_WRITE 433 +#define K_SYSCALL_RTC_ALARM_GET_SUPPORTED_FIELDS 434 +#define K_SYSCALL_RTC_ALARM_GET_TIME 435 +#define K_SYSCALL_RTC_ALARM_IS_PENDING 436 +#define K_SYSCALL_RTC_ALARM_SET_CALLBACK 437 +#define K_SYSCALL_RTC_ALARM_SET_TIME 438 +#define K_SYSCALL_RTC_GET_CALIBRATION 439 +#define K_SYSCALL_RTC_GET_TIME 440 +#define K_SYSCALL_RTC_SET_CALIBRATION 441 +#define K_SYSCALL_RTC_SET_TIME 442 +#define K_SYSCALL_RTC_UPDATE_SET_CALLBACK 443 +#define K_SYSCALL_RTIO_CQE_COPY_OUT 444 +#define K_SYSCALL_RTIO_CQE_GET_MEMPOOL_BUFFER 445 +#define K_SYSCALL_RTIO_RELEASE_BUFFER 446 +#define K_SYSCALL_RTIO_SQE_CANCEL 447 +#define K_SYSCALL_RTIO_SQE_COPY_IN_GET_HANDLES 448 +#define K_SYSCALL_RTIO_SUBMIT 449 +#define K_SYSCALL_SDHC_CARD_BUSY 450 +#define K_SYSCALL_SDHC_CARD_PRESENT 451 +#define K_SYSCALL_SDHC_DISABLE_INTERRUPT 452 +#define K_SYSCALL_SDHC_ENABLE_INTERRUPT 453 +#define K_SYSCALL_SDHC_EXECUTE_TUNING 454 +#define K_SYSCALL_SDHC_GET_HOST_PROPS 455 +#define K_SYSCALL_SDHC_HW_RESET 456 +#define K_SYSCALL_SDHC_REQUEST 457 +#define K_SYSCALL_SDHC_SET_IO 458 +#define K_SYSCALL_SENSOR_ATTR_GET 459 +#define K_SYSCALL_SENSOR_ATTR_SET 460 +#define K_SYSCALL_SENSOR_CHANNEL_GET 461 +#define K_SYSCALL_SENSOR_GET_DECODER 462 +#define K_SYSCALL_SENSOR_RECONFIGURE_READ_IODEV 463 +#define K_SYSCALL_SENSOR_SAMPLE_FETCH 464 +#define K_SYSCALL_SENSOR_SAMPLE_FETCH_CHAN 465 +#define K_SYSCALL_SIP_SUPERVISORY_CALL 466 +#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_REQ 467 +#define K_SYSCALL_SIP_SVC_PLAT_ASYNC_RES_RES 468 +#define K_SYSCALL_SIP_SVC_PLAT_FORMAT_TRANS_ID 469 +#define K_SYSCALL_SIP_SVC_PLAT_FREE_ASYNC_MEMORY 470 +#define K_SYSCALL_SIP_SVC_PLAT_FUNC_ID_VALID 471 +#define K_SYSCALL_SIP_SVC_PLAT_GET_ERROR_CODE 472 +#define K_SYSCALL_SIP_SVC_PLAT_GET_TRANS_IDX 473 +#define K_SYSCALL_SIP_SVC_PLAT_UPDATE_TRANS_ID 474 +#define K_SYSCALL_SMBUS_BLOCK_PCALL 475 +#define K_SYSCALL_SMBUS_BLOCK_READ 476 +#define K_SYSCALL_SMBUS_BLOCK_WRITE 477 +#define K_SYSCALL_SMBUS_BYTE_DATA_READ 478 +#define K_SYSCALL_SMBUS_BYTE_DATA_WRITE 479 +#define K_SYSCALL_SMBUS_BYTE_READ 480 +#define K_SYSCALL_SMBUS_BYTE_WRITE 481 +#define K_SYSCALL_SMBUS_CONFIGURE 482 +#define K_SYSCALL_SMBUS_GET_CONFIG 483 +#define K_SYSCALL_SMBUS_HOST_NOTIFY_REMOVE_CB 484 +#define K_SYSCALL_SMBUS_PCALL 485 +#define K_SYSCALL_SMBUS_QUICK 486 +#define K_SYSCALL_SMBUS_SMBALERT_REMOVE_CB 487 +#define K_SYSCALL_SMBUS_WORD_DATA_READ 488 +#define K_SYSCALL_SMBUS_WORD_DATA_WRITE 489 +#define K_SYSCALL_STEPPER_ENABLE 490 +#define K_SYSCALL_STEPPER_GET_ACTUAL_POSITION 491 +#define K_SYSCALL_STEPPER_GET_MICRO_STEP_RES 492 +#define K_SYSCALL_STEPPER_IS_MOVING 493 +#define K_SYSCALL_STEPPER_MOVE_BY 494 +#define K_SYSCALL_STEPPER_MOVE_TO 495 +#define K_SYSCALL_STEPPER_RUN 496 +#define K_SYSCALL_STEPPER_SET_EVENT_CALLBACK 497 +#define K_SYSCALL_STEPPER_SET_MAX_VELOCITY 498 +#define K_SYSCALL_STEPPER_SET_MICRO_STEP_RES 499 +#define K_SYSCALL_STEPPER_SET_REFERENCE_POSITION 500 +#define K_SYSCALL_SYSCON_GET_BASE 501 +#define K_SYSCALL_SYSCON_GET_SIZE 502 +#define K_SYSCALL_SYSCON_READ_REG 503 +#define K_SYSCALL_SYSCON_WRITE_REG 504 +#define K_SYSCALL_TEE_CANCEL 505 +#define K_SYSCALL_TEE_CLOSE_SESSION 506 +#define K_SYSCALL_TEE_GET_VERSION 507 +#define K_SYSCALL_TEE_INVOKE_FUNC 508 +#define K_SYSCALL_TEE_OPEN_SESSION 509 +#define K_SYSCALL_TEE_SHM_ALLOC 510 +#define K_SYSCALL_TEE_SHM_FREE 511 +#define K_SYSCALL_TEE_SHM_REGISTER 512 +#define K_SYSCALL_TEE_SHM_UNREGISTER 513 +#define K_SYSCALL_TEE_SUPPL_RECV 514 +#define K_SYSCALL_TEE_SUPPL_SEND 515 +#define K_SYSCALL_TGPIO_PIN_CONFIG_EXT_TIMESTAMP 516 +#define K_SYSCALL_TGPIO_PIN_DISABLE 517 +#define K_SYSCALL_TGPIO_PIN_PERIODIC_OUTPUT 518 +#define K_SYSCALL_TGPIO_PIN_READ_TS_EC 519 +#define K_SYSCALL_TGPIO_PORT_GET_CYCLES_PER_SECOND 520 +#define K_SYSCALL_TGPIO_PORT_GET_TIME 521 +#define K_SYSCALL_UPDATEHUB_AUTOHANDLER 522 +#define K_SYSCALL_UPDATEHUB_CONFIRM 523 +#define K_SYSCALL_UPDATEHUB_PROBE 524 +#define K_SYSCALL_UPDATEHUB_REBOOT 525 +#define K_SYSCALL_UPDATEHUB_UPDATE 526 +#define K_SYSCALL_USER_FAULT 527 +#define K_SYSCALL_W1_CHANGE_BUS_LOCK 528 +#define K_SYSCALL_W1_CONFIGURE 529 +#define K_SYSCALL_W1_GET_SLAVE_COUNT 530 +#define K_SYSCALL_W1_READ_BIT 531 +#define K_SYSCALL_W1_READ_BLOCK 532 +#define K_SYSCALL_W1_READ_BYTE 533 +#define K_SYSCALL_W1_RESET_BUS 534 +#define K_SYSCALL_W1_SEARCH_BUS 535 +#define K_SYSCALL_W1_WRITE_BIT 536 +#define K_SYSCALL_W1_WRITE_BLOCK 537 +#define K_SYSCALL_W1_WRITE_BYTE 538 +#define K_SYSCALL_WDT_DISABLE 539 +#define K_SYSCALL_WDT_FEED 540 +#define K_SYSCALL_WDT_SETUP 541 +#define K_SYSCALL_XTENSA_USER_FAULT 542 +#define K_SYSCALL_ZSOCK_ACCEPT 543 +#define K_SYSCALL_ZSOCK_BIND 544 +#define K_SYSCALL_ZSOCK_CLOSE 545 +#define K_SYSCALL_ZSOCK_CONNECT 546 +#define K_SYSCALL_ZSOCK_FCNTL_IMPL 547 +#define K_SYSCALL_ZSOCK_GETHOSTNAME 548 +#define K_SYSCALL_ZSOCK_GETPEERNAME 549 +#define K_SYSCALL_ZSOCK_GETSOCKNAME 550 +#define K_SYSCALL_ZSOCK_GETSOCKOPT 551 +#define K_SYSCALL_ZSOCK_GET_CONTEXT_OBJECT 552 +#define K_SYSCALL_ZSOCK_INET_PTON 553 +#define K_SYSCALL_ZSOCK_IOCTL_IMPL 554 +#define K_SYSCALL_ZSOCK_LISTEN 555 +#define K_SYSCALL_ZSOCK_RECVFROM 556 +#define K_SYSCALL_ZSOCK_RECVMSG 557 +#define K_SYSCALL_ZSOCK_SENDMSG 558 +#define K_SYSCALL_ZSOCK_SENDTO 559 +#define K_SYSCALL_ZSOCK_SETSOCKOPT 560 +#define K_SYSCALL_ZSOCK_SHUTDOWN 561 +#define K_SYSCALL_ZSOCK_SOCKET 562 +#define K_SYSCALL_ZSOCK_SOCKETPAIR 563 +#define K_SYSCALL_ZVFS_POLL 564 +#define K_SYSCALL_ZVFS_SELECT 565 +#define K_SYSCALL_Z_ERRNO 566 +#define K_SYSCALL_Z_ZSOCK_GETADDRINFO_INTERNAL 567 #ifndef _ASMLANGUAGE diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/comparator.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/comparator.h new file mode 100644 index 00000000..dfae6e51 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/comparator.h @@ -0,0 +1,98 @@ +/* auto-generated by gen_syscalls.py, don't edit */ + +#ifndef Z_INCLUDE_SYSCALLS_COMPARATOR_H +#define Z_INCLUDE_SYSCALLS_COMPARATOR_H + + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include +#include + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +extern int z_impl_comparator_get_output(const struct device * dev); + +__pinned_func +static inline int comparator_get_output(const struct device * dev) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_COMPARATOR_GET_OUTPUT); + } +#endif + compiler_barrier(); + return z_impl_comparator_get_output(dev); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define comparator_get_output(dev) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_COMPARATOR_GET_OUTPUT, comparator_get_output, dev); syscall__retval = comparator_get_output(dev); sys_port_trace_syscall_exit(K_SYSCALL_COMPARATOR_GET_OUTPUT, comparator_get_output, dev, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_comparator_set_trigger(const struct device * dev, enum comparator_trigger trigger); + +__pinned_func +static inline int comparator_set_trigger(const struct device * dev, enum comparator_trigger trigger) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; enum comparator_trigger val; } parm1 = { .val = trigger }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_COMPARATOR_SET_TRIGGER); + } +#endif + compiler_barrier(); + return z_impl_comparator_set_trigger(dev, trigger); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define comparator_set_trigger(dev, trigger) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_COMPARATOR_SET_TRIGGER, comparator_set_trigger, dev, trigger); syscall__retval = comparator_set_trigger(dev, trigger); sys_port_trace_syscall_exit(K_SYSCALL_COMPARATOR_SET_TRIGGER, comparator_set_trigger, dev, trigger, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_comparator_trigger_is_pending(const struct device * dev); + +__pinned_func +static inline int comparator_trigger_is_pending(const struct device * dev) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_COMPARATOR_TRIGGER_IS_PENDING); + } +#endif + compiler_barrier(); + return z_impl_comparator_trigger_is_pending(dev); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define comparator_trigger_is_pending(dev) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_COMPARATOR_TRIGGER_IS_PENDING, comparator_trigger_is_pending, dev); syscall__retval = comparator_trigger_is_pending(dev); sys_port_trace_syscall_exit(K_SYSCALL_COMPARATOR_TRIGGER_IS_PENDING, comparator_trigger_is_pending, dev, syscall__retval); syscall__retval; }) +#endif +#endif + + +#ifdef __cplusplus +} +#endif + +#endif +#endif /* include guard */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/devmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/devmux.h index d9a48740..dc5b4a91 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/devmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/devmux.h @@ -20,15 +20,15 @@ extern "C" { #endif -extern ssize_t z_impl_devmux_select_get(const struct device * dev); +extern int z_impl_devmux_select_get(const struct device * dev); __pinned_func -static inline ssize_t devmux_select_get(const struct device * dev) +static inline int devmux_select_get(const struct device * dev) { #ifdef CONFIG_USERSPACE if (z_syscall_trap()) { union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; - return (ssize_t) arch_syscall_invoke1(parm0.x, K_SYSCALL_DEVMUX_SELECT_GET); + return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_DEVMUX_SELECT_GET); } #endif compiler_barrier(); @@ -38,7 +38,7 @@ static inline ssize_t devmux_select_get(const struct device * dev) #if defined(CONFIG_TRACING_SYSCALL) #ifndef DISABLE_SYSCALL_TRACING -#define devmux_select_get(dev) ({ ssize_t syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_DEVMUX_SELECT_GET, devmux_select_get, dev); syscall__retval = devmux_select_get(dev); sys_port_trace_syscall_exit(K_SYSCALL_DEVMUX_SELECT_GET, devmux_select_get, dev, syscall__retval); syscall__retval; }) +#define devmux_select_get(dev) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_DEVMUX_SELECT_GET, devmux_select_get, dev); syscall__retval = devmux_select_get(dev); sys_port_trace_syscall_exit(K_SYSCALL_DEVMUX_SELECT_GET, devmux_select_get, dev, syscall__retval); syscall__retval; }) #endif #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/fdtable.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/fdtable.h new file mode 100644 index 00000000..7ef41145 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/fdtable.h @@ -0,0 +1,81 @@ +/* auto-generated by gen_syscalls.py, don't edit */ + +#ifndef Z_INCLUDE_SYSCALLS_FDTABLE_H +#define Z_INCLUDE_SYSCALLS_FDTABLE_H + + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include +#include + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +extern int z_impl_zvfs_poll(struct zvfs_pollfd * fds, int nfds, int poll_timeout); + +__pinned_func +static inline int zvfs_poll(struct zvfs_pollfd * fds, int nfds, int poll_timeout) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; struct zvfs_pollfd * val; } parm0 = { .val = fds }; + union { uintptr_t x; int val; } parm1 = { .val = nfds }; + union { uintptr_t x; int val; } parm2 = { .val = poll_timeout }; + return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_ZVFS_POLL); + } +#endif + compiler_barrier(); + return z_impl_zvfs_poll(fds, nfds, poll_timeout); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define zvfs_poll(fds, nfds, poll_timeout) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_ZVFS_POLL, zvfs_poll, fds, nfds, poll_timeout); syscall__retval = zvfs_poll(fds, nfds, poll_timeout); sys_port_trace_syscall_exit(K_SYSCALL_ZVFS_POLL, zvfs_poll, fds, nfds, poll_timeout, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_zvfs_select(int nfds, struct zvfs_fd_set *ZRESTRICT readfds, struct zvfs_fd_set *ZRESTRICT writefds, struct zvfs_fd_set *ZRESTRICT errorfds, const struct timespec *ZRESTRICT timeout, const void *ZRESTRICT sigmask); + +__pinned_func +static inline int zvfs_select(int nfds, struct zvfs_fd_set *ZRESTRICT readfds, struct zvfs_fd_set *ZRESTRICT writefds, struct zvfs_fd_set *ZRESTRICT errorfds, const struct timespec *ZRESTRICT timeout, const void *ZRESTRICT sigmask) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; int val; } parm0 = { .val = nfds }; + union { uintptr_t x; struct zvfs_fd_set *ZRESTRICT val; } parm1 = { .val = readfds }; + union { uintptr_t x; struct zvfs_fd_set *ZRESTRICT val; } parm2 = { .val = writefds }; + union { uintptr_t x; struct zvfs_fd_set *ZRESTRICT val; } parm3 = { .val = errorfds }; + union { uintptr_t x; const struct timespec *ZRESTRICT val; } parm4 = { .val = timeout }; + union { uintptr_t x; const void *ZRESTRICT val; } parm5 = { .val = sigmask }; + return (int) arch_syscall_invoke6(parm0.x, parm1.x, parm2.x, parm3.x, parm4.x, parm5.x, K_SYSCALL_ZVFS_SELECT); + } +#endif + compiler_barrier(); + return z_impl_zvfs_select(nfds, readfds, writefds, errorfds, timeout, sigmask); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define zvfs_select(nfds, readfds, writefds, errorfds, timeout, sigmask) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_ZVFS_SELECT, zvfs_select, nfds, readfds, writefds, errorfds, timeout, sigmask); syscall__retval = zvfs_select(nfds, readfds, writefds, errorfds, timeout, sigmask); sys_port_trace_syscall_exit(K_SYSCALL_ZVFS_SELECT, zvfs_select, nfds, readfds, writefds, errorfds, timeout, sigmask, syscall__retval); syscall__retval; }) +#endif +#endif + + +#ifdef __cplusplus +} +#endif + +#endif +#endif /* include guard */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/flash.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/flash.h index 670314e6..b9d580dd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/flash.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/flash.h @@ -97,6 +97,30 @@ static inline int flash_erase(const struct device * dev, off_t offset, size_t si #endif +extern int z_impl_flash_get_size(const struct device * dev, uint64_t * size); + +__pinned_func +static inline int flash_get_size(const struct device * dev, uint64_t * size) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; uint64_t * val; } parm1 = { .val = size }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_FLASH_GET_SIZE); + } +#endif + compiler_barrier(); + return z_impl_flash_get_size(dev, size); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define flash_get_size(dev, size) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_FLASH_GET_SIZE, flash_get_size, dev, size); syscall__retval = flash_get_size(dev, size); sys_port_trace_syscall_exit(K_SYSCALL_FLASH_GET_SIZE, flash_get_size, dev, size, syscall__retval); syscall__retval; }) +#endif +#endif + + extern int z_impl_flash_fill(const struct device * dev, uint8_t val, off_t offset, size_t size); __pinned_func @@ -343,6 +367,39 @@ static inline int flash_ex_op(const struct device * dev, uint16_t code, const ui #endif +extern int z_impl_flash_copy(const struct device * src_dev, off_t src_offset, const struct device * dst_dev, off_t dst_offset, off_t size, uint8_t * buf, size_t buf_size); + +__pinned_func +static inline int flash_copy(const struct device * src_dev, off_t src_offset, const struct device * dst_dev, off_t dst_offset, off_t size, uint8_t * buf, size_t buf_size) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = src_dev }; + union { uintptr_t x; off_t val; } parm1 = { .val = src_offset }; + union { uintptr_t x; const struct device * val; } parm2 = { .val = dst_dev }; + union { uintptr_t x; off_t val; } parm3 = { .val = dst_offset }; + union { uintptr_t x; off_t val; } parm4 = { .val = size }; + union { uintptr_t x; uint8_t * val; } parm5 = { .val = buf }; + union { uintptr_t x; size_t val; } parm6 = { .val = buf_size }; + uintptr_t more[] = { + parm5.x, + parm6.x + }; + return (int) arch_syscall_invoke6(parm0.x, parm1.x, parm2.x, parm3.x, parm4.x, (uintptr_t) &more, K_SYSCALL_FLASH_COPY); + } +#endif + compiler_barrier(); + return z_impl_flash_copy(src_dev, src_offset, dst_dev, dst_offset, size, buf, buf_size); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define flash_copy(src_dev, src_offset, dst_dev, dst_offset, size, buf, buf_size) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_FLASH_COPY, flash_copy, src_dev, src_offset, dst_dev, dst_offset, size, buf, buf_size); syscall__retval = flash_copy(src_dev, src_offset, dst_dev, dst_offset, size, buf, buf_size); sys_port_trace_syscall_exit(K_SYSCALL_FLASH_COPY, flash_copy, src_dev, src_offset, dst_dev, dst_offset, size, buf, buf_size, syscall__retval); syscall__retval; }) +#endif +#endif + + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/gnss.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/gnss.h index f8c2fc7a..0c645979 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/gnss.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/gnss.h @@ -68,54 +68,6 @@ static inline int gnss_get_fix_rate(const struct device * dev, uint32_t * fix_in #endif -extern int z_impl_gnss_set_periodic_config(const struct device * dev, const struct gnss_periodic_config * config); - -__pinned_func -static inline int gnss_set_periodic_config(const struct device * dev, const struct gnss_periodic_config * config) -{ -#ifdef CONFIG_USERSPACE - if (z_syscall_trap()) { - union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; - union { uintptr_t x; const struct gnss_periodic_config * val; } parm1 = { .val = config }; - return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_GNSS_SET_PERIODIC_CONFIG); - } -#endif - compiler_barrier(); - return z_impl_gnss_set_periodic_config(dev, config); -} - -#if defined(CONFIG_TRACING_SYSCALL) -#ifndef DISABLE_SYSCALL_TRACING - -#define gnss_set_periodic_config(dev, config) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_GNSS_SET_PERIODIC_CONFIG, gnss_set_periodic_config, dev, config); syscall__retval = gnss_set_periodic_config(dev, config); sys_port_trace_syscall_exit(K_SYSCALL_GNSS_SET_PERIODIC_CONFIG, gnss_set_periodic_config, dev, config, syscall__retval); syscall__retval; }) -#endif -#endif - - -extern int z_impl_gnss_get_periodic_config(const struct device * dev, struct gnss_periodic_config * config); - -__pinned_func -static inline int gnss_get_periodic_config(const struct device * dev, struct gnss_periodic_config * config) -{ -#ifdef CONFIG_USERSPACE - if (z_syscall_trap()) { - union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; - union { uintptr_t x; struct gnss_periodic_config * val; } parm1 = { .val = config }; - return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_GNSS_GET_PERIODIC_CONFIG); - } -#endif - compiler_barrier(); - return z_impl_gnss_get_periodic_config(dev, config); -} - -#if defined(CONFIG_TRACING_SYSCALL) -#ifndef DISABLE_SYSCALL_TRACING - -#define gnss_get_periodic_config(dev, config) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_GNSS_GET_PERIODIC_CONFIG, gnss_get_periodic_config, dev, config); syscall__retval = gnss_get_periodic_config(dev, config); sys_port_trace_syscall_exit(K_SYSCALL_GNSS_GET_PERIODIC_CONFIG, gnss_get_periodic_config, dev, config, syscall__retval); syscall__retval; }) -#endif -#endif - - extern int z_impl_gnss_set_navigation_mode(const struct device * dev, enum gnss_navigation_mode mode); __pinned_func @@ -236,6 +188,30 @@ static inline int gnss_get_supported_systems(const struct device * dev, gnss_sys #endif +extern int z_impl_gnss_get_latest_timepulse(const struct device * dev, k_ticks_t * timestamp); + +__pinned_func +static inline int gnss_get_latest_timepulse(const struct device * dev, k_ticks_t * timestamp) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; k_ticks_t * val; } parm1 = { .val = timestamp }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_GNSS_GET_LATEST_TIMEPULSE); + } +#endif + compiler_barrier(); + return z_impl_gnss_get_latest_timepulse(dev, timestamp); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define gnss_get_latest_timepulse(dev, timestamp) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_GNSS_GET_LATEST_TIMEPULSE, gnss_get_latest_timepulse, dev, timestamp); syscall__retval = gnss_get_latest_timepulse(dev, timestamp); sys_port_trace_syscall_exit(K_SYSCALL_GNSS_GET_LATEST_TIMEPULSE, gnss_get_latest_timepulse, dev, timestamp, syscall__retval); syscall__retval; }) +#endif +#endif + + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/haptics.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/haptics.h new file mode 100644 index 00000000..b6e30be9 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/haptics.h @@ -0,0 +1,74 @@ +/* auto-generated by gen_syscalls.py, don't edit */ + +#ifndef Z_INCLUDE_SYSCALLS_HAPTICS_H +#define Z_INCLUDE_SYSCALLS_HAPTICS_H + + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include +#include + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +extern int z_impl_haptics_start_output(const struct device * dev); + +__pinned_func +static inline int haptics_start_output(const struct device * dev) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_HAPTICS_START_OUTPUT); + } +#endif + compiler_barrier(); + return z_impl_haptics_start_output(dev); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define haptics_start_output(dev) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_HAPTICS_START_OUTPUT, haptics_start_output, dev); syscall__retval = haptics_start_output(dev); sys_port_trace_syscall_exit(K_SYSCALL_HAPTICS_START_OUTPUT, haptics_start_output, dev, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_haptics_stop_output(const struct device * dev); + +__pinned_func +static inline int haptics_stop_output(const struct device * dev) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + return (int) arch_syscall_invoke1(parm0.x, K_SYSCALL_HAPTICS_STOP_OUTPUT); + } +#endif + compiler_barrier(); + return z_impl_haptics_stop_output(dev); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define haptics_stop_output(dev) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_HAPTICS_STOP_OUTPUT, haptics_stop_output, dev); syscall__retval = haptics_stop_output(dev); sys_port_trace_syscall_exit(K_SYSCALL_HAPTICS_STOP_OUTPUT, haptics_stop_output, dev, syscall__retval); syscall__retval; }) +#endif +#endif + + +#ifdef __cplusplus +} +#endif + +#endif +#endif /* include guard */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/kernel.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/kernel.h index 152fbfee..83a2d765 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/kernel.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/kernel.h @@ -234,23 +234,6 @@ static inline void k_thread_abort(k_tid_t thread) } -extern void z_impl_k_thread_start(k_tid_t thread); - -__pinned_func -static inline void k_thread_start(k_tid_t thread) -{ -#ifdef CONFIG_USERSPACE - if (z_syscall_trap()) { - union { uintptr_t x; k_tid_t val; } parm0 = { .val = thread }; - (void) arch_syscall_invoke1(parm0.x, K_SYSCALL_K_THREAD_START); - return; - } -#endif - compiler_barrier(); - z_impl_k_thread_start(thread); -} - - extern k_ticks_t z_impl_k_thread_timeout_expires_ticks(const struct k_thread * thread); __pinned_func diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/socket.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/socket.h index b46faf72..548884c2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/socket.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/socket.h @@ -399,31 +399,6 @@ static inline int zsock_ioctl_impl(int sock, unsigned long request, va_list ap) #endif -extern int z_impl_zsock_poll(struct zsock_pollfd * fds, int nfds, int timeout); - -__pinned_func -static inline int zsock_poll(struct zsock_pollfd * fds, int nfds, int timeout) -{ -#ifdef CONFIG_USERSPACE - if (z_syscall_trap()) { - union { uintptr_t x; struct zsock_pollfd * val; } parm0 = { .val = fds }; - union { uintptr_t x; int val; } parm1 = { .val = nfds }; - union { uintptr_t x; int val; } parm2 = { .val = timeout }; - return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_ZSOCK_POLL); - } -#endif - compiler_barrier(); - return z_impl_zsock_poll(fds, nfds, timeout); -} - -#if defined(CONFIG_TRACING_SYSCALL) -#ifndef DISABLE_SYSCALL_TRACING - -#define zsock_poll(fds, nfds, timeout) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_ZSOCK_POLL, zsock_poll, fds, nfds, timeout); syscall__retval = zsock_poll(fds, nfds, timeout); sys_port_trace_syscall_exit(K_SYSCALL_ZSOCK_POLL, zsock_poll, fds, nfds, timeout, syscall__retval); syscall__retval; }) -#endif -#endif - - extern int z_impl_zsock_getsockopt(int sock, int level, int optname, void * optval, socklen_t * optlen); __pinned_func diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/stepper.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/stepper.h new file mode 100644 index 00000000..598cd51c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/syscalls/stepper.h @@ -0,0 +1,294 @@ +/* auto-generated by gen_syscalls.py, don't edit */ + +#ifndef Z_INCLUDE_SYSCALLS_STEPPER_H +#define Z_INCLUDE_SYSCALLS_STEPPER_H + + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include +#include + +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +extern int z_impl_stepper_enable(const struct device * dev, const bool enable); + +__pinned_func +static inline int stepper_enable(const struct device * dev, const bool enable) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; const bool val; } parm1 = { .val = enable }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_ENABLE); + } +#endif + compiler_barrier(); + return z_impl_stepper_enable(dev, enable); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_enable(dev, enable) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_ENABLE, stepper_enable, dev, enable); syscall__retval = stepper_enable(dev, enable); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_ENABLE, stepper_enable, dev, enable, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_move_by(const struct device * dev, int32_t micro_steps); + +__pinned_func +static inline int stepper_move_by(const struct device * dev, int32_t micro_steps) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; int32_t val; } parm1 = { .val = micro_steps }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_MOVE_BY); + } +#endif + compiler_barrier(); + return z_impl_stepper_move_by(dev, micro_steps); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_move_by(dev, micro_steps) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_MOVE_BY, stepper_move_by, dev, micro_steps); syscall__retval = stepper_move_by(dev, micro_steps); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_MOVE_BY, stepper_move_by, dev, micro_steps, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_set_max_velocity(const struct device * dev, uint32_t micro_steps_per_second); + +__pinned_func +static inline int stepper_set_max_velocity(const struct device * dev, uint32_t micro_steps_per_second) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; uint32_t val; } parm1 = { .val = micro_steps_per_second }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_SET_MAX_VELOCITY); + } +#endif + compiler_barrier(); + return z_impl_stepper_set_max_velocity(dev, micro_steps_per_second); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_set_max_velocity(dev, micro_steps_per_second) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_SET_MAX_VELOCITY, stepper_set_max_velocity, dev, micro_steps_per_second); syscall__retval = stepper_set_max_velocity(dev, micro_steps_per_second); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_SET_MAX_VELOCITY, stepper_set_max_velocity, dev, micro_steps_per_second, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_set_micro_step_res(const struct device * dev, enum stepper_micro_step_resolution resolution); + +__pinned_func +static inline int stepper_set_micro_step_res(const struct device * dev, enum stepper_micro_step_resolution resolution) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; enum stepper_micro_step_resolution val; } parm1 = { .val = resolution }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_SET_MICRO_STEP_RES); + } +#endif + compiler_barrier(); + return z_impl_stepper_set_micro_step_res(dev, resolution); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_set_micro_step_res(dev, resolution) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_SET_MICRO_STEP_RES, stepper_set_micro_step_res, dev, resolution); syscall__retval = stepper_set_micro_step_res(dev, resolution); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_SET_MICRO_STEP_RES, stepper_set_micro_step_res, dev, resolution, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_get_micro_step_res(const struct device * dev, enum stepper_micro_step_resolution * resolution); + +__pinned_func +static inline int stepper_get_micro_step_res(const struct device * dev, enum stepper_micro_step_resolution * resolution) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; enum stepper_micro_step_resolution * val; } parm1 = { .val = resolution }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_GET_MICRO_STEP_RES); + } +#endif + compiler_barrier(); + return z_impl_stepper_get_micro_step_res(dev, resolution); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_get_micro_step_res(dev, resolution) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_GET_MICRO_STEP_RES, stepper_get_micro_step_res, dev, resolution); syscall__retval = stepper_get_micro_step_res(dev, resolution); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_GET_MICRO_STEP_RES, stepper_get_micro_step_res, dev, resolution, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_set_reference_position(const struct device * dev, int32_t value); + +__pinned_func +static inline int stepper_set_reference_position(const struct device * dev, int32_t value) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; int32_t val; } parm1 = { .val = value }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_SET_REFERENCE_POSITION); + } +#endif + compiler_barrier(); + return z_impl_stepper_set_reference_position(dev, value); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_set_reference_position(dev, value) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_SET_REFERENCE_POSITION, stepper_set_reference_position, dev, value); syscall__retval = stepper_set_reference_position(dev, value); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_SET_REFERENCE_POSITION, stepper_set_reference_position, dev, value, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_get_actual_position(const struct device * dev, int32_t * value); + +__pinned_func +static inline int stepper_get_actual_position(const struct device * dev, int32_t * value) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; int32_t * val; } parm1 = { .val = value }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_GET_ACTUAL_POSITION); + } +#endif + compiler_barrier(); + return z_impl_stepper_get_actual_position(dev, value); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_get_actual_position(dev, value) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_GET_ACTUAL_POSITION, stepper_get_actual_position, dev, value); syscall__retval = stepper_get_actual_position(dev, value); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_GET_ACTUAL_POSITION, stepper_get_actual_position, dev, value, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_move_to(const struct device * dev, int32_t micro_steps); + +__pinned_func +static inline int stepper_move_to(const struct device * dev, int32_t micro_steps) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; int32_t val; } parm1 = { .val = micro_steps }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_MOVE_TO); + } +#endif + compiler_barrier(); + return z_impl_stepper_move_to(dev, micro_steps); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_move_to(dev, micro_steps) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_MOVE_TO, stepper_move_to, dev, micro_steps); syscall__retval = stepper_move_to(dev, micro_steps); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_MOVE_TO, stepper_move_to, dev, micro_steps, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_is_moving(const struct device * dev, bool * is_moving); + +__pinned_func +static inline int stepper_is_moving(const struct device * dev, bool * is_moving) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; bool * val; } parm1 = { .val = is_moving }; + return (int) arch_syscall_invoke2(parm0.x, parm1.x, K_SYSCALL_STEPPER_IS_MOVING); + } +#endif + compiler_barrier(); + return z_impl_stepper_is_moving(dev, is_moving); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_is_moving(dev, is_moving) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_IS_MOVING, stepper_is_moving, dev, is_moving); syscall__retval = stepper_is_moving(dev, is_moving); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_IS_MOVING, stepper_is_moving, dev, is_moving, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_run(const struct device * dev, enum stepper_direction direction, uint32_t velocity); + +__pinned_func +static inline int stepper_run(const struct device * dev, enum stepper_direction direction, uint32_t velocity) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; enum stepper_direction val; } parm1 = { .val = direction }; + union { uintptr_t x; uint32_t val; } parm2 = { .val = velocity }; + return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_STEPPER_RUN); + } +#endif + compiler_barrier(); + return z_impl_stepper_run(dev, direction, velocity); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_run(dev, direction, velocity) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_RUN, stepper_run, dev, direction, velocity); syscall__retval = stepper_run(dev, direction, velocity); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_RUN, stepper_run, dev, direction, velocity, syscall__retval); syscall__retval; }) +#endif +#endif + + +extern int z_impl_stepper_set_event_callback(const struct device * dev, stepper_event_callback_t callback, void * user_data); + +__pinned_func +static inline int stepper_set_event_callback(const struct device * dev, stepper_event_callback_t callback, void * user_data) +{ +#ifdef CONFIG_USERSPACE + if (z_syscall_trap()) { + union { uintptr_t x; const struct device * val; } parm0 = { .val = dev }; + union { uintptr_t x; stepper_event_callback_t val; } parm1 = { .val = callback }; + union { uintptr_t x; void * val; } parm2 = { .val = user_data }; + return (int) arch_syscall_invoke3(parm0.x, parm1.x, parm2.x, K_SYSCALL_STEPPER_SET_EVENT_CALLBACK); + } +#endif + compiler_barrier(); + return z_impl_stepper_set_event_callback(dev, callback, user_data); +} + +#if defined(CONFIG_TRACING_SYSCALL) +#ifndef DISABLE_SYSCALL_TRACING + +#define stepper_set_event_callback(dev, callback, user_data) ({ int syscall__retval; sys_port_trace_syscall_enter(K_SYSCALL_STEPPER_SET_EVENT_CALLBACK, stepper_set_event_callback, dev, callback, user_data); syscall__retval = stepper_set_event_callback(dev, callback, user_data); sys_port_trace_syscall_exit(K_SYSCALL_STEPPER_SET_EVENT_CALLBACK, stepper_set_event_callback, dev, callback, user_data, syscall__retval); syscall__retval; }) +#endif +#endif + + +#ifdef __cplusplus +} +#endif + +#endif +#endif /* include guard */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/version.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/version.h index 8733cd47..4cdd915b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/version.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/generated/zephyr/version.h @@ -6,20 +6,20 @@ * alternatively user defined BUILD_VERSION. */ -#define ZEPHYR_VERSION_CODE 198400 +#define ZEPHYR_VERSION_CODE 262243 #define ZEPHYR_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) -#define KERNELVERSION 0x3070000 -#define KERNEL_VERSION_NUMBER 0x30700 -#define KERNEL_VERSION_MAJOR 3 -#define KERNEL_VERSION_MINOR 7 -#define KERNEL_PATCHLEVEL 0 +#define KERNELVERSION 0x4006300 +#define KERNEL_VERSION_NUMBER 0x40063 +#define KERNEL_VERSION_MAJOR 4 +#define KERNEL_VERSION_MINOR 0 +#define KERNEL_PATCHLEVEL 99 #define KERNEL_TWEAK 0 -#define KERNEL_VERSION_STRING "3.7.0" -#define KERNEL_VERSION_EXTENDED_STRING "3.7.0+0" -#define KERNEL_VERSION_TWEAK_STRING "3.7.0+0" +#define KERNEL_VERSION_STRING "4.0.99" +#define KERNEL_VERSION_EXTENDED_STRING "4.0.99+0" +#define KERNEL_VERSION_TWEAK_STRING "4.0.99+0" -#define BUILD_VERSION v3.7.0-35-gfbc79e8814e1 +#define BUILD_VERSION v3.7.0-8117-gd5cc72a5209a #endif /* _KERNEL_VERSION_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/app_memory/mem_domain.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/app_memory/mem_domain.h index 8fe75eb3..b950235f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/app_memory/mem_domain.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/app_memory/mem_domain.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef INCLUDE_APP_MEMORY_MEM_DOMAIN_H -#define INCLUDE_APP_MEMORY_MEM_DOMAIN_H +#ifndef ZEPHYR_INCLUDE_APP_MEMORY_MEM_DOMAIN_H_ +#define ZEPHYR_INCLUDE_APP_MEMORY_MEM_DOMAIN_H_ #include #include @@ -193,4 +193,4 @@ int k_mem_domain_add_thread(struct k_mem_domain *domain, #endif /** @} */ -#endif /* INCLUDE_APP_MEMORY_MEM_DOMAIN_H */ +#endif /* ZEPHYR_INCLUDE_APP_MEMORY_MEM_DOMAIN_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/arch_inlines.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/arch_inlines.h index 1d1e0b92..b15888fb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/arch_inlines.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/arch_inlines.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ -#define ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_ARC_ARCH_INLINES_H_ +#define ZEPHYR_INCLUDE_ARCH_ARC_ARCH_INLINES_H_ #ifndef _ASMLANGUAGE @@ -42,4 +42,4 @@ static ALWAYS_INLINE unsigned int arch_num_cpus(void) } #endif /* !_ASMLANGUAGE */ -#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ */ +#endif /* ZEPHYR_INCLUDE_ARCH_ARC_ARCH_INLINES_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/arcv2_irq_unit.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/arcv2_irq_unit.h index 18cb0fa2..a8f3760a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/arcv2_irq_unit.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/arcv2_irq_unit.h @@ -199,9 +199,11 @@ bool z_arc_v2_irq_unit_is_in_isr(void) /** * @brief Sets an IRQ line to level/pulse trigger * - * Sets the IRQ line to trigger an interrupt based on the level or the - * edge of the signal. Valid values for are _ARC_V2_INT_LEVEL and + * Sets the IRQ line @p irq to trigger an interrupt based on the level or the + * edge of the signal. Valid values for @p trigger are _ARC_V2_INT_LEVEL and * _ARC_V2_INT_PULSE. + * @param irq IRQ line + * @param trigger Trigger state */ static ALWAYS_INLINE void z_arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger) @@ -217,8 +219,10 @@ void z_arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger) /** * @brief Returns an IRQ line trigger type * - * Gets the IRQ line trigger type. - * Valid values for are _ARC_V2_INT_LEVEL and _ARC_V2_INT_PULSE. + * Gets the IRQ line @p irq trigger type. + * Valid values for @retval trigger are _ARC_V2_INT_LEVEL and _ARC_V2_INT_PULSE. + * + * @param irq IRQ line * * @return trigger state */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/vpx/arc_vpx.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/vpx/arc_vpx.h new file mode 100644 index 00000000..904c44cd --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arc/v2/vpx/arc_vpx.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2024 Synopsys. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_VPX_ARC_VPX_H_ +#define ZEPHYR_INCLUDE_ARCH_ARC_V2_VPX_ARC_VPX_H_ + +#include + +/** + * @brief Obtain a cooperative lock on the VPX vector registers + * + * This function is used to obtain a cooperative lock on the current CPU's + * VPX vector registers before the calling thread uses them. Callers + * attempting to obtain the cooperative lock must be already restricted to + * executing on a single CPU, and continue to execute on that same CPU while + * both waiting and holding the lock. + * + * This routine is not callable from an ISR. + * + * @param timeout Waiting period to obtain the lock, or one of the special + * values K_NO_WAIT and K_FOREVER. + * + * @return Zero on success, otherwise error code + */ +int arc_vpx_lock(k_timeout_t timeout); + +/** + * @brief Release cooperative lock on the VPX vector registers + * + * This function is used to release the cooperative lock on the current CPU's + * VPX vector registers. It is called after the current thread no longer needs + * to use the VPX vector registers, thereby allowing another thread to use them. + * + * This routine is not callable from an ISR. + */ +void arc_vpx_unlock(void); + +/** + * @brief Release cooperative lock on a CPU's VPX vector registers + * + * This function is used to release the cooperative lock on the specified CPU's + * VPX vector registers. This routine should not be used except by a system + * monitor to release the cooperative lock in case the locking thread where it + * is known that the locking thread is unable to release it (e.g. it was + * aborted while holding the lock). + * + * @param cpu_id CPU ID of the VPX vector register set to be unlocked + */ +void arc_vpx_unlock_force(unsigned int cpu_id); + +#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_VPX_ARC_VPX_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_inlines.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_inlines.h index 0f32159e..04c4a649 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_inlines.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_inlines.h @@ -34,4 +34,6 @@ #include #endif +#include + #endif /* ZEPHYR_INCLUDE_ARCH_INLINES_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_interface.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_interface.h index ae51b4a3..0f081d06 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_interface.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arch_interface.h @@ -455,6 +455,13 @@ bool arch_irq_is_used(unsigned int irq); * @param parameter Value to pass to the function when invoked */ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter); + + +/** + * Initialize the architecture-specific portion of the irq_offload subsystem + */ +void arch_irq_offload_init(void); + #endif /* CONFIG_IRQ_OFFLOAD */ /** @} */ @@ -1251,6 +1258,17 @@ bool arch_pcie_msi_vector_connect(msi_vector_t *vector, */ void arch_spin_relax(void); +/** + * @defgroup arch-stackwalk Architecture-specific Stack Walk APIs + * @ingroup arch-interface + * + * To add API support to an architecture, `arch_stack_walk()` should be implemented and a non-user + * configurable Kconfig `ARCH_HAS_STACKWALK` that is default to `y` should be created in the + * architecture's top level Kconfig, with all the relevant dependencies. + * + * @{ + */ + /** * stack_trace_callback_fn - Callback for @ref arch_stack_walk * @param cookie Caller supplied pointer handed back by @ref arch_stack_walk @@ -1271,13 +1289,18 @@ typedef bool (*stack_trace_callback_fn)(void *cookie, unsigned long addr); * ============ ======= ============================================ * thread esf * ============ ======= ============================================ - * thread NULL Stack trace from thread (can be _current) + * thread NULL Stack trace from thread (can be arch_current_thread()) * thread esf Stack trace starting on esf * ============ ======= ============================================ */ void arch_stack_walk(stack_trace_callback_fn callback_fn, void *cookie, const struct k_thread *thread, const struct arch_esf *esf); +/** + * arch-stackwalk + * @} + */ + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/arch.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/arch.h index 804e1d23..9bbcc237 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/arch.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/arch.h @@ -19,9 +19,6 @@ /* Add include for DTS generated information */ #include -/* ARM GPRs are often designated by two different names */ -#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; } - #include #include #include @@ -270,9 +267,9 @@ enum k_fatal_error_reason_arch { #ifdef CONFIG_CPU_HAS_ARM_MPU #include #endif /* CONFIG_CPU_HAS_ARM_MPU */ -#ifdef CONFIG_CPU_HAS_NXP_MPU +#ifdef CONFIG_CPU_HAS_NXP_SYSMPU #include -#endif /* CONFIG_CPU_HAS_NXP_MPU */ +#endif /* CONFIG_CPU_HAS_NXP_SYSMPU */ #endif /* CONFIG_ARM_MPU */ #ifdef CONFIG_ARM_AARCH32_MMU #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/cpu.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/cpu.h index 13455fe6..74021eba 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/cpu.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/cpu.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 Lexmark International, Inc. + * Copyright 2024 Arm Limited and/or its affiliates * * SPDX-License-Identifier: Apache-2.0 */ @@ -55,6 +56,12 @@ #define SCTLR_C_BIT BIT(2) #define SCTLR_I_BIT BIT(12) +/* Armv8-R Cortex-R52 Cache Segregation Control Register */ +#define IMP_CSCTLR_DFLW_SHIFT (0) +#define IMP_CSCTLR_IFLW_SHIFT (8) +#define IMP_CSCTLR(iway, dway) ((iway << IMP_CSCTLR_IFLW_SHIFT) | \ + ((dway << IMP_CSCTLR_DFLW_SHIFT))) + /* Hyp System Control Register */ #define HSCTLR_RES1 (BIT(29) | BIT(28) | BIT(23) | \ BIT(22) | BIT(18) | BIT(16) | \ @@ -84,8 +91,8 @@ #define ICC_SRE_ELx_DIB_BIT BIT(2) #define ICC_SRE_EL3_EN_BIT BIT(3) -/* MPIDR */ -#define MPIDR_AFFLVL_MASK (0xff) +/* MPIDR mask to extract Aff0, Aff1, and Aff2 */ +#define MPIDR_AFFLVL_MASK (0xffffff) #define MPIDR_AFF0_SHIFT (0) #define MPIDR_AFF1_SHIFT (8) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/exception.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/exception.h index cd8377bc..8fcc6d0e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/exception.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/exception.h @@ -54,6 +54,9 @@ struct __extra_esf_info { }; #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ +/* ARM GPRs are often designated by two different names */ +#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; } + struct arch_esf { #if defined(CONFIG_EXTRA_EXCEPTION_INFO) struct __extra_esf_info extra_info; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/mpu.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/mpu.h index e660247e..896b73e2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/mpu.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_a_r/mpu.h @@ -32,7 +32,7 @@ #define MPU_RASR_B_Pos 0 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) -#if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5) +#if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5) || defined(CONFIG_CPU_CORTEX_R8) #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h index 7f0d3e3e..3f74451c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h @@ -37,6 +37,12 @@ #define REGION_FLASH_SIZE REGION_256M #elif CONFIG_FLASH_SIZE <= 524288 #define REGION_FLASH_SIZE REGION_512M +#elif CONFIG_FLASH_SIZE <= 1048576 +#define REGION_FLASH_SIZE REGION_1G +#elif CONFIG_FLASH_SIZE <= 2097152 +#define REGION_FLASH_SIZE REGION_2G +#elif CONFIG_FLASH_SIZE <= 4194304 +#define REGION_FLASH_SIZE REGION_4G #else #error "Unsupported flash size configuration" #endif @@ -64,10 +70,22 @@ #define REGION_SRAM_SIZE REGION_8M #elif CONFIG_SRAM_SIZE <= 16384 #define REGION_SRAM_SIZE REGION_16M -#elif CONFIG_SRAM_SIZE == 32768 +#elif CONFIG_SRAM_SIZE <= 32768 #define REGION_SRAM_SIZE REGION_32M -#elif CONFIG_SRAM_SIZE == 65536 +#elif CONFIG_SRAM_SIZE <= 65536 #define REGION_SRAM_SIZE REGION_64M +#elif CONFIG_SRAM_SIZE <= 131072 +#define REGION_SRAM_SIZE REGION_128M +#elif CONFIG_SRAM_SIZE <= 262144 +#define REGION_SRAM_SIZE REGION_256M +#elif CONFIG_SRAM_SIZE <= 524288 +#define REGION_SRAM_SIZE REGION_512M +#elif CONFIG_SRAM_SIZE <= 1048576 +#define REGION_SRAM_SIZE REGION_1G +#elif CONFIG_SRAM_SIZE <= 2097152 +#define REGION_SRAM_SIZE REGION_2G +#elif CONFIG_SRAM_SIZE <= 4194304 +#define REGION_SRAM_SIZE REGION_4G #else #error "Unsupported sram size configuration" #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/cpu.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/cpu.h index c8318bd9..064d8f92 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/cpu.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/cpu.h @@ -54,16 +54,21 @@ extern "C" { struct __cpu_context { /* GPRs are saved onto the stack */ uint32_t msp; - uint32_t msplim; uint32_t psp; - uint32_t psplim; - uint32_t apsr; - uint32_t ipsr; - uint32_t epsr; uint32_t primask; + uint32_t control; + +#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) + /* Registers present only on ARMv7-M and ARMv8-M Mainline */ uint32_t faultmask; uint32_t basepri; - uint32_t control; +#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ + +#if defined(CONFIG_CPU_CORTEX_M_HAS_SPLIM) + /* Registers present only on certain ARMv8-M implementations */ + uint32_t msplim; + uint32_t psplim; +#endif /* CONFIG_CPU_CORTEX_M_HAS_SPLIM */ }; typedef struct __cpu_context _cpu_context_t; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/exception.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/exception.h index 2deed9bd..6f603178 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/exception.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/cortex_m/exception.h @@ -98,6 +98,9 @@ struct __extra_esf_info { }; #endif /* CONFIG_EXTRA_EXCEPTION_INFO */ +/* ARM GPRs are often designated by two different names */ +#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; } + struct arch_esf { struct __basic_sf { sys_define_gpr_with_alias(a1, r0); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/gdbstub.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/gdbstub.h index 55fceff1..5eb4ea15 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/gdbstub.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/gdbstub.h @@ -7,7 +7,7 @@ #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_GDBSTUB_H_ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_GDBSTUB_H_ -#include +#include #ifndef _ASMLANGUAGE diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/mpu/arm_mpu_v8.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/mpu/arm_mpu_v8.h index 11d4a2e7..77deb64b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/mpu/arm_mpu_v8.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm/mpu/arm_mpu_v8.h @@ -82,7 +82,7 @@ (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk) /* Attribute flags for cache-ability */ -#if defined(CONFIG_AARCH32_ARMV8_R) + /* Memory Attributes for Device Memory * 1.Gathering (G/nG) * Determines whether multiple accesses can be merged into a single @@ -105,7 +105,6 @@ #define DEVICE_nGnRE 0x4U #define DEVICE_nGRE 0x8U #define DEVICE_GRE 0xCU -#endif /* Read/Write Allocation Configurations for Cacheable Memory */ #define R_NON_W_NON 0x0 /* Do not allocate Read/Write */ @@ -152,8 +151,6 @@ #define MPU_MAIR_INDEX_SRAM 1 #define MPU_MAIR_ATTR_SRAM_NOCACHE MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE #define MPU_MAIR_INDEX_SRAM_NOCACHE 2 - -#if defined(CONFIG_AARCH32_ARMV8_R) #define MPU_MAIR_ATTR_DEVICE DEVICE_nGnRnE #define MPU_MAIR_INDEX_DEVICE 3 /* Flash region(s): Attribute-0 @@ -166,17 +163,6 @@ (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) | \ (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)) | \ (MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8))) -#else -/* Flash region(s): Attribute-0 - * SRAM region(s): Attribute-1 - * SRAM no cache-able regions(s): Attribute-2 - */ -#define MPU_MAIR_ATTRS \ - (((MPU_MAIR_ATTR_FLASH << MPU_MAIR0_Attr0_Pos) & MPU_MAIR0_Attr0_Msk) | \ - ((MPU_MAIR_ATTR_SRAM << MPU_MAIR0_Attr1_Pos) & MPU_MAIR0_Attr1_Msk) | \ - ((MPU_MAIR_ATTR_SRAM_NOCACHE << MPU_MAIR0_Attr2_Pos) & \ - MPU_MAIR0_Attr2_Msk)) -#endif /* Some helper defines for common regions. * @@ -309,6 +295,13 @@ } #endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */ +#define REGION_DEVICE_ATTR(base, size) \ + { \ + /* AP, XN, SH */ \ + .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* Cache-ability */ \ + .mair_idx = MPU_MAIR_INDEX_DEVICE, \ + .r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */ \ + } #endif struct arm_mpu_region_attr { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/arm_mmu.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/arm_mmu.h index 65aab01f..450a8238 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/arm_mmu.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/arm_mmu.h @@ -45,6 +45,7 @@ * attrs[7] : Mirror RO/RW permissions to EL0 * attrs[8] : Overwrite existing mapping if any * attrs[9] : non-Global mapping (nG) + * attrs[10]: Paged-out mapping * */ #define MT_PERM_SHIFT 3U @@ -54,6 +55,7 @@ #define MT_RW_AP_SHIFT 7U #define MT_NO_OVERWRITE_SHIFT 8U #define MT_NON_GLOBAL_SHIFT 9U +#define MT_PAGED_OUT_SHIFT 10U #define MT_RO (0U << MT_PERM_SHIFT) #define MT_RW (1U << MT_PERM_SHIFT) @@ -75,6 +77,8 @@ #define MT_G (0U << MT_NON_GLOBAL_SHIFT) #define MT_NG (1U << MT_NON_GLOBAL_SHIFT) +#define MT_PAGED_OUT (1U << MT_PAGED_OUT_SHIFT) + #define MT_P_RW_U_RW (MT_RW | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) #define MT_P_RW_U_NA (MT_RW | MT_RW_AP_EL_HIGHER | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) #define MT_P_RO_U_RO (MT_RO | MT_RW_AP_ELx | MT_P_EXECUTE_NEVER | MT_U_EXECUTE_NEVER) @@ -89,6 +93,19 @@ #define MT_DEFAULT_SECURE_STATE MT_SECURE #endif +/* Definitions used by arch_page_info_get() */ +#define ARCH_DATA_PAGE_LOADED BIT(0) +#define ARCH_DATA_PAGE_ACCESSED BIT(1) +#define ARCH_DATA_PAGE_DIRTY BIT(2) +#define ARCH_DATA_PAGE_NOT_MAPPED BIT(3) + +/* + * Special unpaged "location" tags (highest possible descriptor physical + * address values unlikely to conflict with backing store locations) + */ +#define ARCH_UNPAGED_ANON_ZERO 0x0000fffffffff000 +#define ARCH_UNPAGED_ANON_UNINIT 0x0000ffffffffe000 + #ifndef _ASMLANGUAGE /* Region definition data structure */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/cache.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/cache.h index cddd901b..e0a7a603 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/cache.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/arm64/cache.h @@ -236,6 +236,10 @@ static ALWAYS_INLINE void arch_icache_disable(void) #endif /* CONFIG_ICACHE */ +static ALWAYS_INLINE void arch_cache_init(void) +{ +} + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/cache.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/cache.h index 1516f03e..088de27c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/cache.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/cache.h @@ -349,6 +349,9 @@ void *arch_cache_uncached_ptr_get(void __sparse_cache *ptr); #define cache_uncached_ptr(ptr) arch_cache_uncached_ptr_get(ptr) #endif /* CONFIG_CACHE_DOUBLEMAP */ + +void arch_cache_init(void); + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/arch_inlines.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/arch_inlines.h new file mode 100644 index 00000000..8c0ba334 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/arch_inlines.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Meta Platforms. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ZEPHYR_ARCH_COMMON_ARCH_INLINES_H_ +#define ZEPHYR_INCLUDE_ZEPHYR_ARCH_COMMON_ARCH_INLINES_H_ + +#ifndef ZEPHYR_INCLUDE_ARCH_INLINES_H_ +#error "This header shouldn't be included directly" +#endif /* ZEPHYR_INCLUDE_ARCH_INLINES_H_ */ + +#ifndef _ASMLANGUAGE + +#include + +#ifndef CONFIG_ARCH_HAS_CUSTOM_CURRENT_IMPL +static ALWAYS_INLINE struct k_thread *arch_current_thread(void) +{ +#ifdef CONFIG_SMP + /* In SMP, arch_current_thread() is a field read from _current_cpu, which + * can race with preemption before it is read. We must lock + * local interrupts when reading it. + */ + unsigned int k = arch_irq_lock(); + + struct k_thread *ret = _current_cpu->current; + + arch_irq_unlock(k); +#else + struct k_thread *ret = _kernel.cpus[0].current; +#endif /* CONFIG_SMP */ + return ret; +} + +static ALWAYS_INLINE void arch_current_thread_set(struct k_thread *thread) +{ + _current_cpu->current = thread; +} +#endif /* CONFIG_ARCH_HAS_CUSTOM_CURRENT_IMPL */ + +#endif /* _ASMLANGUAGE */ + +#endif /* ZEPHYR_INCLUDE_ZEPHYR_ARCH_COMMON_ARCH_INLINES_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/ffs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/ffs.h index 11f85659..2660faa2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/ffs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/ffs.h @@ -57,26 +57,13 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op) #else /* - * Toolchain does not have __builtin_ffs(). - * Need to do this manually. + * Toolchain does not have __builtin_ffs(). Leverage find_lsb_set() + * by first clearing all but the lowest set bit. */ - int bit; - if (op == 0) { - return 0; - } + op = op ^ (op & (op - 1)); - for (bit = 0; bit < 32; bit++) { - if ((op & (1 << bit)) != 0) { - return (bit + 1); - } - } - - /* - * This should never happen but we need to keep - * compiler happy. - */ - return 0; + return find_msb_set(op); #endif /* CONFIG_TOOLCHAIN_HAS_BUILTIN_FFS */ } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/pm_s2ram.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/pm_s2ram.h index 451794a5..ad9ab8ad 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/pm_s2ram.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/common/pm_s2ram.h @@ -7,6 +7,7 @@ * * @brief public S2RAM APIs. * @defgroup pm_s2ram S2RAM APIs + * @ingroup subsys_pm * @{ */ @@ -64,6 +65,11 @@ int arch_pm_s2ram_suspend(pm_s2ram_system_off_fn_t system_off); * * Default implementation is setting a magic word in RAM. CONFIG_PM_S2RAM_CUSTOM_MARKING * allows custom implementation. + * The following requirements must be fulfilled: + * - the function cannot use stack (asm function or function with 'naked' attribute) + * - the content of the R1 and R4 registers must remain unchanged + * - returning from the function should be performed with the `bx lr` instruction + * */ void pm_s2ram_mark_set(void); @@ -75,6 +81,11 @@ void pm_s2ram_mark_set(void); * * Default implementation is checking a magic word in RAM. CONFIG_PM_S2RAM_CUSTOM_MARKING * allows custom implementation. + * The following requirements must be fulfilled: + * - the function cannot use stack (most likely asm function) + * - the content of the R1 and R4 registers must remain unchanged + * - the function's return value is passed by R0 register + * - returning from the function should be performed with the `bx lr` instruction * * @retval true if marking is found which indicates resuming after suspend-to-RAM. * @retval false if marking is not found which indicates standard boot. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/arch_inlines.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/arch_inlines.h index 36dc2e64..c97413a5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/arch_inlines.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/arch_inlines.h @@ -11,6 +11,7 @@ #include #include "csr.h" +#include "reg.h" static ALWAYS_INLINE uint32_t arch_proc_id(void) { @@ -26,6 +27,16 @@ static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void) #endif } +#ifdef CONFIG_RISCV_CURRENT_VIA_GP +register struct k_thread *__arch_current_thread __asm__("gp"); + +#define arch_current_thread() __arch_current_thread +#define arch_current_thread_set(thread) \ + do { \ + __arch_current_thread = _current_cpu->current = (thread); \ + } while (0) +#endif /* CONFIG_RISCV_CURRENT_VIA_GP */ + static ALWAYS_INLINE unsigned int arch_num_cpus(void) { return CONFIG_MP_MAX_NUM_CPUS; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/elf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/elf.h new file mode 100644 index 00000000..fe40dc88 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/elf.h @@ -0,0 +1,298 @@ +/** + * @file + * @brief RISCV-Specific constants for ELF binaries. + * + * References can be found here: + * https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc + */ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_ARCH_RISCV_ELF_H +#define ZEPHYR_ARCH_RISCV_ELF_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Relocation names for RISCV-specific relocations + * @cond ignore + */ + +#define R_RISCV_NONE 0 +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 +#define R_RISCV_COPY 4 +#define R_RISCV_JUMP_SLOT 5 +#define R_RISCV_TLS_DTPMOD32 6 +#define R_RISCV_TLS_DTPMOD64 7 +#define R_RISCV_TLS_DTPREL32 8 +#define R_RISCV_TLS_DTPREL64 9 +#define R_RISCV_TLS_TPREL32 10 +#define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_TLSDESC 12 +/* 13-15 reserved */ +#define R_RISCV_BRANCH 16 +#define R_RISCV_JAL 17 +#define R_RISCV_CALL 18 +#define R_RISCV_CALL_PLT 19 +#define R_RISCV_GOT_HI20 20 +#define R_RISCV_TLS_GOT_HI20 21 +#define R_RISCV_TLS_GD_HI20 22 +#define R_RISCV_PCREL_HI20 23 +#define R_RISCV_PCREL_LO12_I 24 +#define R_RISCV_PCREL_LO12_S 25 +#define R_RISCV_HI20 26 +#define R_RISCV_LO12_I 27 +#define R_RISCV_LO12_S 28 +#define R_RISCV_TPREL_HI20 29 +#define R_RISCV_TPREL_LO12_I 30 +#define R_RISCV_TPREL_LO12_S 31 +#define R_RISCV_TPREL_ADD 32 +#define R_RISCV_ADD8 33 +#define R_RISCV_ADD16 34 +#define R_RISCV_ADD32 35 +#define R_RISCV_ADD64 36 +#define R_RISCV_SUB8 37 +#define R_RISCV_SUB16 38 +#define R_RISCV_SUB32 39 +#define R_RISCV_SUB64 40 +#define R_RISCV_GOT32_PCREL 41 +/* 42 reserved */ +#define R_RISCV_ALIGN 43 +/* next two refer to compressed instructions */ +#define R_RISCV_RVC_BRANCH 44 +#define R_RISCV_RVC_JUMP 45 +/* 46-50 reserved */ +#define R_RISCV_RELAX 51 +#define R_RISCV_SUB6 52 +#define R_RISCV_SET6 53 +#define R_RISCV_SET8 54 +#define R_RISCV_SET16 55 +#define R_RISCV_SET32 56 +#define R_RISCV_32_PCREL 57 +#define R_RISCV_IRELATIVE 58 +#define R_RISCV_PLT32 59 +#define R_RISCV_SET_ULEB128 60 +#define R_RISCV_SUB_ULEB128 61 +#define R_RISCV_TLSDESC_HI20 62 +#define R_RISCV_TLSDESC_LOAD_LO12 63 +#define R_RISCV_TLSDESC_ADD_LO12 64 +#define R_RISCV_TLSDESC_CALL 65 +/* 66-190 reserved */ +#define R_RISCV_VENDOR 191 +/* 192-255 reserved */ +/** @endcond */ + +/** + * "wordclass" from RISC-V specification + * @cond ignore + */ +#if defined(CONFIG_64BIT) +typedef uint64_t r_riscv_wordclass_t; +#else +typedef uint32_t r_riscv_wordclass_t; +#endif +/** @endcond */ + +/** @brief Extract bit from immediate + * + * @param imm8 immediate value (usually upper 20 or lower 12 bit) + * @param bit which bit to extract + */ +#define R_RISCV_IMM8_GET_BIT(imm8, bit) (((imm8) & BIT(bit)) >> (bit)) + +/** @brief Generate mask for immediate in B-type RISC-V instruction + * + * @param imm8 immediate value, lower 12 bits used; + * due to alignment requirements, imm8[0] is implicitly 0 + * + */ +#define R_RISCV_BTYPE_IMM8_MASK(imm8) \ + ((R_RISCV_IMM8_GET_BIT(imm8, 12) << 31) | (R_RISCV_IMM8_GET_BIT(imm8, 10) << 30) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 9) << 29) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 28) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 7) << 27) | (R_RISCV_IMM8_GET_BIT(imm8, 6) << 26) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 5) << 25) | (R_RISCV_IMM8_GET_BIT(imm8, 4) << 11) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 3) << 10) | (R_RISCV_IMM8_GET_BIT(imm8, 2) << 9) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 1) << 8) | (R_RISCV_IMM8_GET_BIT(imm8, 11) << 7)) + +/** @brief Generate mask for immediate in J-type RISC-V instruction + * + * @param imm8 immediate value, lower 21 bits used; + * due to alignment requirements, imm8[0] is implicitly 0 + * + */ +#define R_RISCV_JTYPE_IMM8_MASK(imm8) \ + ((R_RISCV_IMM8_GET_BIT(imm8, 20) << 31) | (R_RISCV_IMM8_GET_BIT(imm8, 10) << 30) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 9) << 29) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 28) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 7) << 27) | (R_RISCV_IMM8_GET_BIT(imm8, 6) << 26) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 5) << 25) | (R_RISCV_IMM8_GET_BIT(imm8, 4) << 24) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 3) << 23) | (R_RISCV_IMM8_GET_BIT(imm8, 2) << 22) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 1) << 21) | (R_RISCV_IMM8_GET_BIT(imm8, 11) << 20) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 19) << 19) | (R_RISCV_IMM8_GET_BIT(imm8, 18) << 18) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 17) << 17) | (R_RISCV_IMM8_GET_BIT(imm8, 16) << 16) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 15) << 15) | (R_RISCV_IMM8_GET_BIT(imm8, 14) << 14) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 13) << 13) | (R_RISCV_IMM8_GET_BIT(imm8, 12) << 12)) + +/** @brief Generate mask for immediate in S-type RISC-V instruction + * + * @param imm8 immediate value, lower 12 bits used + * + */ +#define R_RISCV_STYPE_IMM8_MASK(imm8) \ + ((R_RISCV_IMM8_GET_BIT(imm8, 11) << 31) | (R_RISCV_IMM8_GET_BIT(imm8, 10) << 30) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 9) << 29) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 28) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 7) << 27) | (R_RISCV_IMM8_GET_BIT(imm8, 6) << 26) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 5) << 25) | (R_RISCV_IMM8_GET_BIT(imm8, 4) << 11) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 3) << 10) | (R_RISCV_IMM8_GET_BIT(imm8, 2) << 9) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 1) << 8) | (R_RISCV_IMM8_GET_BIT(imm8, 0) << 7)) + +/** @brief Generate mask for immediate in compressed J-type RISC-V instruction + * + * @param imm8 immediate value, lower 12 bits used; + * due to alignment requirements, imm8[0] is implicitly 0 + * + */ +#define R_RISCV_CJTYPE_IMM8_MASK(imm8) \ + ((R_RISCV_IMM8_GET_BIT(imm8, 11) << 12) | (R_RISCV_IMM8_GET_BIT(imm8, 4) << 11) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 9) << 10) | (R_RISCV_IMM8_GET_BIT(imm8, 8) << 9) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 10) << 8) | (R_RISCV_IMM8_GET_BIT(imm8, 6) << 7) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 7) << 6) | (R_RISCV_IMM8_GET_BIT(imm8, 3) << 5) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 2) << 4) | (R_RISCV_IMM8_GET_BIT(imm8, 1) << 3) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 5) << 2)) + +/** @brief Generate mask for immediate in compressed B-type RISC-V instruction + * + * @param imm8 immediate value, lower 9 bits used; + * due to alignment requirements, imm8[0] is implicitly 0 + * + */ +#define R_RISCV_CBTYPE_IMM8_MASK(imm8) \ + ((R_RISCV_IMM8_GET_BIT(imm8, 8) << 12) | (R_RISCV_IMM8_GET_BIT(imm8, 4) << 11) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 3) << 10) | (R_RISCV_IMM8_GET_BIT(imm8, 7) << 6) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 6) << 5) | (R_RISCV_IMM8_GET_BIT(imm8, 2) << 4) | \ + (R_RISCV_IMM8_GET_BIT(imm8, 1) << 3) | (R_RISCV_IMM8_GET_BIT(imm8, 5) << 2)) + +/** @brief Clear immediate bits in B-type instruction. + * + * @param operand Address of RISC-V instruction, B-type + * + */ +#define R_RISCV_CLEAR_BTYPE_IMM8(operand) ((operand) & ~R_RISCV_BTYPE_IMM8_MASK((uint32_t) -1)) + +/** @brief Overwrite immediate in B-type instruction + * + * @param operand Address of RISC-V instruction, B-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_BTYPE_IMM8(operand, imm8) \ + ((R_RISCV_CLEAR_BTYPE_IMM8(operand)) | R_RISCV_BTYPE_IMM8_MASK(imm8)) + +/** @brief Clear immediate bits in J-type instruction. + * + * @param operand Address of RISC-V instruction, J-type + * + */ +#define R_RISCV_CLEAR_JTYPE_IMM8(operand) ((operand) & ~R_RISCV_JTYPE_IMM8_MASK((uint32_t) -1)) + +/** @brief Overwrite immediate in J-type instruction + * + * @param operand Address of RISC-V instruction, J-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_JTYPE_IMM8(operand, imm8) \ + ((R_RISCV_CLEAR_JTYPE_IMM8(operand)) | R_RISCV_JTYPE_IMM8_MASK(imm8)) + +/** @brief Clear immediate bits in S-type instruction. + * + * @param operand Address of RISC-V instruction, S-type + * + */ +#define R_RISCV_CLEAR_STYPE_IMM8(operand) ((operand) & ~R_RISCV_STYPE_IMM8_MASK((uint32_t) -1)) + +/** @brief Overwrite immediate in S-type instruction + * + * @param operand Address of RISC-V instruction, S-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_STYPE_IMM8(operand, imm8) \ + ((R_RISCV_CLEAR_STYPE_IMM8(operand)) | R_RISCV_STYPE_IMM8_MASK(imm8)) + +/** @brief Clear immediate bits in compressed J-type instruction. + * + * @param operand Address of RISC-V instruction, compressed-J-type + * + */ +#define R_RISCV_CLEAR_CJTYPE_IMM8(operand) ((operand) & ~R_RISCV_CJTYPE_IMM8_MASK((uint32_t) -1)) + +/** @brief Overwrite immediate in compressed J-type instruction + * + * @param operand Address of RISC-V instruction, compressed-J-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_CJTYPE_IMM8(operand, imm8) \ + ((R_RISCV_CLEAR_CJTYPE_IMM8(operand)) | R_RISCV_CJTYPE_IMM8_MASK(imm8)) + +/** @brief Clear immediate bits in compressed B-type instruction. + * + * @param operand Address of RISC-V instruction, compressed-B-type + * + */ +#define R_RISCV_CLEAR_CBTYPE_IMM8(operand) ((operand) & ~R_RISCV_CBTYPE_IMM8_MASK((uint32_t) -1)) + +/** @brief Overwrite immediate in compressed B-type instruction + * + * @param operand Address of RISC-V instruction, compressed-B-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_CBTYPE_IMM8(operand, imm8) \ + ((R_RISCV_CLEAR_CBTYPE_IMM8(operand)) | R_RISCV_CBTYPE_IMM8_MASK(imm8)) + +/** @brief Clear immediate bits in U-type instruction. + * + * @param operand Address of RISC-V instruction, U-type + * + */ +#define R_RISCV_CLEAR_UTYPE_IMM8(operand) ((operand) & ~(0xFFFFF000)) + +/** @brief Overwrite immediate in U-type instruction + * + * @param operand Address of RISC-V instruction, U-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_UTYPE_IMM8(operand, imm8) \ + ((R_RISCV_CLEAR_UTYPE_IMM8(operand)) | ((imm8) & 0xFFFFF000)) + +/** @brief Clear immediate bits in I-type instruction. + * + * @param operand Address of RISC-V instruction, I-type + * + */ +#define R_RISCV_CLEAR_ITYPE_IMM8(operand) ((operand) & ~(0xFFF00000)) + +/** @brief Overwrite immediate in I-type instruction + * + * @param operand Address of RISC-V instruction, I-type + * @param imm8 New immediate + * + */ +#define R_RISCV_SET_ITYPE_IMM8(operand, imm8) ((R_RISCV_CLEAR_ITYPE_IMM8(operand)) | ((imm8) << 20)) + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_ARCH_RISCV_ELF_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/exception.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/exception.h index 09777622..4e464170 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/exception.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/exception.h @@ -45,6 +45,12 @@ struct soc_esf { }; #endif +#ifdef CONFIG_EXTRA_EXCEPTION_INFO +/* Forward declaration */ +struct _callee_saved; +typedef struct _callee_saved _callee_saved_t; +#endif /* CONFIG_EXTRA_EXCEPTION_INFO */ + #if defined(CONFIG_RISCV_SOC_HAS_ISR_STACKING) SOC_ISR_STACKING_ESF_DECLARE; #else @@ -81,6 +87,10 @@ struct arch_esf { unsigned long sp; /* preserved (user or kernel) stack pointer */ #endif +#ifdef CONFIG_EXTRA_EXCEPTION_INFO + _callee_saved_t *csf; /* pointer to callee-saved-registers */ +#endif /* CONFIG_EXTRA_EXCEPTION_INFO */ + #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE struct soc_esf soc_context; #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/irq.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/irq.h index 1cebd2ae..84089127 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/irq.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/irq.h @@ -62,6 +62,12 @@ extern void z_riscv_irq_priority_set(unsigned int irq, #define z_riscv_irq_priority_set(i, p, f) /* Nothing */ #endif /* CONFIG_RISCV_HAS_PLIC || CONFIG_RISCV_HAS_CLIC */ +#ifdef CONFIG_RISCV_HAS_CLIC +extern void z_riscv_irq_vector_set(unsigned int irq); +#else +#define z_riscv_irq_vector_set(i) /* Nothing */ +#endif /* CONFIG_RISCV_HAS_CLIC */ + #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \ { \ Z_ISR_DECLARE(irq_p + CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET, \ @@ -74,6 +80,7 @@ extern void z_riscv_irq_priority_set(unsigned int irq, Z_ISR_DECLARE_DIRECT(irq_p + CONFIG_RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET, \ ISR_FLAG_DIRECT, isr_p); \ z_riscv_irq_priority_set(irq_p, priority_p, flags_p); \ + z_riscv_irq_vector_set(irq_p); \ } #define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header() diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/reg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/reg.h new file mode 100644 index 00000000..2c0650f0 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/reg.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ +#define ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ + +#include + +#define reg_read(reg) \ + ({ \ + register unsigned long __rv; \ + __asm__ volatile("mv %0, " STRINGIFY(reg) : "=r"(__rv)); \ + __rv; \ + }) + +#define reg_write(reg, val) ({ __asm__("mv " STRINGIFY(reg) ", %0" : : "r"(val)); }) + +#endif /* ZEPHYR_INCLUDE_ZEPHYR_ARCH_RISCV_REG_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/sys_io.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/sys_io.h index 0437053d..2bda1f7b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/sys_io.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/sys_io.h @@ -41,7 +41,7 @@ static ALWAYS_INLINE uint8_t sys_read8(mem_addr_t addr) static ALWAYS_INLINE void sys_write8(uint8_t data, mem_addr_t addr) { - return z_soc_sys_write8(data, addr); + z_soc_sys_write8(data, addr); } static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr) @@ -51,7 +51,7 @@ static ALWAYS_INLINE uint16_t sys_read16(mem_addr_t addr) static ALWAYS_INLINE void sys_write16(uint16_t data, mem_addr_t addr) { - return z_soc_sys_write16(data, addr); + z_soc_sys_write16(data, addr); } static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) @@ -61,7 +61,7 @@ static ALWAYS_INLINE uint32_t sys_read32(mem_addr_t addr) static ALWAYS_INLINE void sys_write32(uint32_t data, mem_addr_t addr) { - return z_soc_sys_write32(data, addr); + z_soc_sys_write32(data, addr); } static ALWAYS_INLINE uint64_t sys_read64(mem_addr_t addr) @@ -71,7 +71,7 @@ static ALWAYS_INLINE uint64_t sys_read64(mem_addr_t addr) static ALWAYS_INLINE void sys_write64(uint64_t data, mem_addr_t addr) { - return z_soc_sys_write64(data, addr); + z_soc_sys_write64(data, addr); } #endif /* CONFIG_RISCV_SOC_HAS_CUSTOM_SYS_IO */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/syscall.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/syscall.h index 8865bd67..e88cd4e8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/syscall.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/riscv/syscall.h @@ -158,7 +158,7 @@ static inline bool arch_is_user_context(void) } /* Defined in arch/riscv/core/thread.c */ - extern __thread uint8_t is_user_mode; + extern Z_THREAD_LOCAL uint8_t is_user_mode; return is_user_mode != 0; } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/ia32/arch.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/ia32/arch.h index b82e0db0..e2f961c8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/ia32/arch.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/ia32/arch.h @@ -305,7 +305,7 @@ static inline void arch_isr_direct_footer(int swap) * 3) Next thread to run in the ready queue is not this thread */ if (swap != 0 && _kernel.cpus[0].nested == 0 && - _kernel.ready_q.cache != _current) { + _kernel.ready_q.cache != arch_current_thread()) { unsigned int flags; /* Fetch EFLAGS argument to z_swap() */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/mmustructs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/mmustructs.h index d02d517f..8e079714 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/mmustructs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/mmustructs.h @@ -32,6 +32,20 @@ /* Use an PAT bit for this one since it's never set in a mapped PTE */ #define ARCH_DATA_PAGE_NOT_MAPPED ((uintptr_t)BIT(7)) +/* + * Special unpaged "location" tags. These are defined as the highest possible + * PTE address values unlikely to conflict with backing store locations. + * As noted in arch_page_info_get(), those values on PAE systems, whose + * pentry_t is larger than uintptr_t get truncated. + */ +#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) +#define ARCH_UNPAGED_ANON_ZERO ((uintptr_t)0x07FFFFFFFFFFF000ULL) +#define ARCH_UNPAGED_ANON_UNINIT ((uintptr_t)0x07FFFFFFFFFFE000ULL) +#else +#define ARCH_UNPAGED_ANON_ZERO ((uintptr_t)0xFFFFF000U) +#define ARCH_UNPAGED_ANON_UNINIT ((uintptr_t)0xFFFFE000U) +#endif + /* Always true with 32-bit page tables, don't enable * CONFIG_EXECUTE_XOR_WRITE and expect it to work for you */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot.h index 66c312e4..379f03dd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot.h @@ -9,32 +9,7 @@ #ifndef _ASMLANGUAGE -#include - -/* - * Multiboot (version 1) boot information structure. - * - * Only fields/values of interest to Zephyr are enumerated: at - * present, that means only those pertaining to the framebuffer. - */ - -struct multiboot_info { - uint32_t flags; - uint32_t mem_lower; - uint32_t mem_upper; - uint32_t unused0[8]; - uint32_t mmap_length; - uint32_t mmap_addr; - uint32_t unused1[9]; - uint32_t fb_addr_lo; - uint32_t fb_addr_hi; - uint32_t fb_pitch; - uint32_t fb_width; - uint32_t fb_height; - uint8_t fb_bpp; - uint8_t fb_type; - uint8_t fb_color_info[6]; -}; +#include "multiboot_info.h" extern struct multiboot_info multiboot_info; @@ -105,9 +80,10 @@ struct multiboot_mmap { /* The flags in the boot info structure tell us which fields are valid. */ -#define MULTIBOOT_INFO_FLAGS_MEM (1 << 0) /* mem_* valid */ -#define MULTIBOOT_INFO_FLAGS_MMAP (1 << 6) /* mmap_* valid */ -#define MULTIBOOT_INFO_FLAGS_FB (1 << 12) /* fb_* valid */ +#define MULTIBOOT_INFO_FLAGS_MEM BIT(0) /* mem_* valid */ +#define MULTIBOOT_INFO_FLAGS_CMDLINE BIT(2) /* cmdline* valid */ +#define MULTIBOOT_INFO_FLAGS_MMAP BIT(6) /* mmap_* valid */ +#define MULTIBOOT_INFO_FLAGS_FB BIT(12) /* fb_* valid */ /* The only fb_type we support is RGB. No text modes and no color palettes. */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot_info.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot_info.h new file mode 100644 index 00000000..5ff7ca2c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/x86/multiboot_info.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ARCH_X86_MULTIBOOT_INFO_H_ +#define ZEPHYR_INCLUDE_ARCH_X86_MULTIBOOT_INFO_H_ + +#include + +/* + * Multiboot (version 1) boot information structure. + * + * Only fields/values of interest to Zephyr are enumerated + */ + +struct multiboot_info { + uint32_t flags; + uint32_t mem_lower; + uint32_t mem_upper; + uint32_t unused0; + uint32_t cmdline; + uint32_t unused1[6]; + uint32_t mmap_length; + uint32_t mmap_addr; + uint32_t unused2[9]; + uint32_t fb_addr_lo; + uint32_t fb_addr_hi; + uint32_t fb_pitch; + uint32_t fb_width; + uint32_t fb_height; + uint8_t fb_bpp; + uint8_t fb_type; + uint8_t fb_color_info[6]; +}; + +typedef struct multiboot_info multiboot_info_t; + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/arch.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/arch.h index c69f0835..794bd1b5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/arch.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/arch.h @@ -45,6 +45,7 @@ /** * @defgroup xtensa_apis Xtensa APIs + * @ingroup arch-interface * @{ * @} * @@ -62,7 +63,7 @@ extern "C" { struct arch_mem_domain { #ifdef CONFIG_XTENSA_MMU - uint32_t *ptables __aligned(CONFIG_MMU_PAGE_SIZE); + uint32_t *ptables; uint8_t asid; bool dirty; #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/cache.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/cache.h index c5964c16..f090bbd1 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/cache.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/cache.h @@ -331,6 +331,10 @@ static inline void *arch_cache_uncached_ptr_get(void *ptr) } #endif +static ALWAYS_INLINE void arch_cache_init(void) +{ +} + #ifdef __cplusplus } /* extern "C" */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/syscall.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/syscall.h index cc19f23d..9fdbe2b0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/syscall.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/arch/xtensa/syscall.h @@ -31,10 +31,18 @@ extern "C" { #endif #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER -uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, - uintptr_t arg3, uintptr_t arg4, - uintptr_t arg5, uintptr_t arg6, - uintptr_t call_id); +uintptr_t xtensa_syscall_helper_args_6(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t arg4, + uintptr_t arg5, uintptr_t arg6, + uintptr_t call_id); + +uintptr_t xtensa_syscall_helper_args_5(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t arg4, + uintptr_t arg5, uintptr_t call_id); + +uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t arg4, + uintptr_t call_id); #define SYSINL ALWAYS_INLINE #else @@ -50,13 +58,14 @@ uintptr_t xtensa_syscall_helper(uintptr_t arg1, uintptr_t arg2, * **/ + static SYSINL uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2, uintptr_t arg3, uintptr_t arg4, uintptr_t arg5, uintptr_t arg6, uintptr_t call_id) { #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(arg1, arg2, arg3, arg4, arg5, arg6, call_id); + return xtensa_syscall_helper_args_6(arg1, arg2, arg3, arg4, arg5, arg6, call_id); #else register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; @@ -77,11 +86,11 @@ static SYSINL uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2, } static SYSINL uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2, - uintptr_t arg3, uintptr_t arg4, - uintptr_t arg5, uintptr_t call_id) + uintptr_t arg3, uintptr_t arg4, + uintptr_t arg5, uintptr_t call_id) { #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(arg1, arg2, arg3, arg4, arg5, 0, call_id); + return xtensa_syscall_helper_args_5(arg1, arg2, arg3, arg4, arg5, call_id); #else register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; @@ -101,11 +110,11 @@ static SYSINL uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2, } static SYSINL uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2, - uintptr_t arg3, uintptr_t arg4, - uintptr_t call_id) + uintptr_t arg3, uintptr_t arg4, + uintptr_t call_id) { #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(arg1, arg2, arg3, arg4, 0, 0, call_id); + return xtensa_syscall_helper_args_4(arg1, arg2, arg3, arg4, call_id); #else register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; @@ -123,12 +132,9 @@ static SYSINL uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2, #endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ } -static SYSINL uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2, - uintptr_t arg3, uintptr_t call_id) +static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2, + uintptr_t arg3, uintptr_t call_id) { -#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(arg1, arg2, arg3, 0, 0, 0, call_id); -#else register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; register uintptr_t a3 __asm__("%a3") = arg2; @@ -140,15 +146,11 @@ static SYSINL uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2, : "memory"); return a2; -#endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */ } -static SYSINL uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2, - uintptr_t call_id) +static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2, + uintptr_t call_id) { -#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(arg1, arg2, 0, 0, 0, 0, call_id); -#else register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; register uintptr_t a3 __asm__("%a3") = arg2; @@ -159,15 +161,10 @@ static SYSINL uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2, : "memory"); return a2; -#endif } -static SYSINL uintptr_t arch_syscall_invoke1(uintptr_t arg1, - uintptr_t call_id) +static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id) { -#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(arg1, 0, 0, 0, 0, 0, call_id); -#else register uintptr_t a2 __asm__("%a2") = call_id; register uintptr_t a6 __asm__("%a6") = arg1; @@ -177,14 +174,10 @@ static SYSINL uintptr_t arch_syscall_invoke1(uintptr_t arg1, : "memory"); return a2; -#endif } -static SYSINL uintptr_t arch_syscall_invoke0(uintptr_t call_id) +static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id) { -#ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER - return xtensa_syscall_helper(0, 0, 0, 0, 0, 0, call_id); -#else register uintptr_t a2 __asm__("%a2") = call_id; __asm__ volatile("syscall\n\t" @@ -193,7 +186,6 @@ static SYSINL uintptr_t arch_syscall_invoke0(uintptr_t call_id) : "memory"); return a2; -#endif } /* @@ -211,7 +203,7 @@ static inline bool arch_is_user_context(void) : "=a" (thread) ); #ifdef CONFIG_THREAD_LOCAL_STORAGE - extern __thread uint32_t is_user_mode; + extern Z_THREAD_LOCAL uint32_t is_user_mode; if (!thread) { return false; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/audio/codec.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/audio/codec.h index 1f56f006..7b2c15db 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/audio/codec.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/audio/codec.h @@ -35,7 +35,9 @@ extern "C" { */ typedef enum { AUDIO_PCM_RATE_8K = 8000, /**< 8 kHz sample rate */ + AUDIO_PCM_RATE_11P025K = 11025, /**< 11.025 kHz sample rate */ AUDIO_PCM_RATE_16K = 16000, /**< 16 kHz sample rate */ + AUDIO_PCM_RATE_22P05K = 22050, /**< 22.05 kHz sample rate */ AUDIO_PCM_RATE_24K = 24000, /**< 24 kHz sample rate */ AUDIO_PCM_RATE_32K = 32000, /**< 32 kHz sample rate */ AUDIO_PCM_RATE_44P1K = 44100, /**< 44.1 kHz sample rate */ @@ -59,6 +61,10 @@ typedef enum { */ typedef enum { AUDIO_DAI_TYPE_I2S, /**< I2S Interface */ + AUDIO_DAI_TYPE_LEFT_JUSTIFIED, /**< I2S Interface, left justified */ + AUDIO_DAI_TYPE_RIGHT_JUSTIFIED, /**< I2S Interface, right justified */ + AUDIO_DAI_TYPE_PCMA, /**< PCM Interface, variant A */ + AUDIO_DAI_TYPE_PCMB, /**< PCM Interface, variant B */ AUDIO_DAI_TYPE_INVALID, /**< Other interfaces can be added here */ } audio_dai_type_t; @@ -68,6 +74,8 @@ typedef enum { typedef enum { AUDIO_PROPERTY_OUTPUT_VOLUME, /**< Output volume */ AUDIO_PROPERTY_OUTPUT_MUTE, /**< Output mute/unmute */ + AUDIO_PROPERTY_INPUT_VOLUME, /**< Input volume */ + AUDIO_PROPERTY_INPUT_MUTE /**< Input mute/unmute */ } audio_property_t; /** @@ -83,6 +91,8 @@ typedef enum { AUDIO_CHANNEL_REAR_CENTER, /**< Rear center channel */ AUDIO_CHANNEL_SIDE_LEFT, /**< Side left channel */ AUDIO_CHANNEL_SIDE_RIGHT, /**< Side right channel */ + AUDIO_CHANNEL_HEADPHONE_LEFT, /**< Headphone left */ + AUDIO_CHANNEL_HEADPHONE_RIGHT, /**< Headphone right */ AUDIO_CHANNEL_ALL, /**< All channels */ } audio_channel_t; @@ -96,6 +106,16 @@ typedef union { /* Other DAI types go here */ } audio_dai_cfg_t; +/* + * DAI Route types + */ +typedef enum { + AUDIO_ROUTE_BYPASS, + AUDIO_ROUTE_PLAYBACK, + AUDIO_ROUTE_PLAYBACK_CAPTURE, + AUDIO_ROUTE_CAPTURE, +} audio_route_t; + /** * Codec configuration parameters */ @@ -103,13 +123,14 @@ struct audio_codec_cfg { uint32_t mclk_freq; /**< MCLK input frequency in Hz */ audio_dai_type_t dai_type; /**< Digital interface type */ audio_dai_cfg_t dai_cfg; /**< DAI configuration info */ + audio_route_t dai_route; /**< Codec route type */ }; /** * Codec property values */ typedef union { - int vol; /**< Volume level in 0.5dB resolution */ + int vol; /**< Volume level (codec-specific) */ bool mute; /**< Mute if @a true, unmute if @a false */ } audio_property_value_t; @@ -160,6 +181,8 @@ struct audio_codec_api { int (*clear_errors)(const struct device *dev); int (*register_error_callback)(const struct device *dev, audio_codec_error_callback_t cb); + int (*route_input)(const struct device *dev, audio_channel_t channel, uint32_t input); + int (*route_output)(const struct device *dev, audio_channel_t channel, uint32_t output); }; /** * @endcond @@ -306,6 +329,56 @@ static inline int audio_codec_register_error_callback(const struct device *dev, return api->register_error_callback(dev, cb); } +/** + * @brief Sets up signal routing for a given input channel. + * + * Some codecs can do input routing (multiplexing) from a chosen set of + * physical inputs. This function maps a given audio (stream) channel to + * a given physical input terminal. + * + * @param dev Pointer to the audio codec device + * @param channel The channel to map + * @param input The input terminal index, codec-specific + * + * @return 0 if successful, negative errno code if failure. + */ +static inline int audio_codec_route_input(const struct device *dev, audio_channel_t channel, + uint32_t input) +{ + const struct audio_codec_api *api = (const struct audio_codec_api *)dev->api; + + if (api->route_input == NULL) { + return -ENOSYS; + } + + return api->route_input(dev, channel, input); +} + +/** + * @brief Sets up signal routing for a given output channel. + * + * Some codecs can do output routing (multiplexing) from a chosen set of + * physical output. This function maps a given audio (stream) channel to + * a given physical output terminal. + * + * @param dev Pointer to the audio codec device + * @param channel The channel to map + * @param output The output terminal index, codec-specific + * + * @return 0 if successful, negative errno code if failure. + */ +static inline int audio_codec_route_output(const struct device *dev, audio_channel_t channel, + uint32_t output) +{ + const struct audio_codec_api *api = (const struct audio_codec_api *)dev->api; + + if (api->route_output == NULL) { + return -ENOSYS; + } + + return api->route_output(dev, channel, output); +} + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bindesc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bindesc.h index a4daaf66..88e51dbf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bindesc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bindesc.h @@ -23,6 +23,8 @@ extern "C" { #define BINDESC_TYPE_STR 0x1 #define BINDESC_TYPE_BYTES 0x2 #define BINDESC_TYPE_DESCRIPTORS_END 0xf +/* sizeof ignores the data as it's a flexible array */ +#define BINDESC_ENTRY_HEADER_SIZE (sizeof(struct bindesc_entry)) /** * @brief Binary Descriptor Definition @@ -51,6 +53,9 @@ extern "C" { /** The app version number such as 0x10203 */ #define BINDESC_ID_APP_VERSION_NUMBER 0x804 +/** The app git reference such as "v3.3.0-18-g2c85d9224fca" */ +#define BINDESC_ID_APP_BUILD_VERSION 0x805 + /** The kernel version string such as "3.4.0" */ #define BINDESC_ID_KERNEL_VERSION_STRING 0x900 @@ -66,6 +71,9 @@ extern "C" { /** The kernel version number such as 0x30400 */ #define BINDESC_ID_KERNEL_VERSION_NUMBER 0x904 +/** The kernel git reference such as "v3.3.0-18-g2c85d9224fca" */ +#define BINDESC_ID_KERNEL_BUILD_VERSION 0x905 + /** The year the image was compiled in */ #define BINDESC_ID_BUILD_TIME_YEAR 0xa00 @@ -125,13 +133,21 @@ extern "C" { */ #define BINDESC_TAG(type, id) ((BINDESC_TYPE_##type & 0xf) << 12 | (id & 0x0fff)) +/** + * @brief Utility macro to get the type of a bindesc tag + * + * @param tag Tag to get the type of + */ +#define BINDESC_GET_TAG_TYPE(tag) ((tag >> 12) & 0xf) + /** * @endcond */ -#if !defined(_LINKER) +#if !defined(_LINKER) || defined(__DOXYGEN__) #include +#include /** * @cond INTERNAL_HIDDEN @@ -165,12 +181,15 @@ extern "C" { * @param id Unique ID of the descriptor * @param value A string value for the descriptor */ -#define BINDESC_STR_DEFINE(name, id, value) \ - __BINDESC_ENTRY_DEFINE(name) = { \ - .tag = BINDESC_TAG(STR, id), \ - .len = (uint16_t)sizeof(value), \ - .data = value, \ - } +#define BINDESC_STR_DEFINE(name, id, value) \ + __BINDESC_ENTRY_DEFINE(name) = { \ + .tag = BINDESC_TAG(STR, id), \ + .len = (uint16_t)sizeof(value), \ + .data = value, \ + }; \ + BUILD_ASSERT(sizeof(value) <= CONFIG_BINDESC_DEFINE_MAX_DATA_SIZE, \ + "Bindesc " STRINGIFY(name) " exceeded maximum size, consider reducing the" \ + " size or changing CONFIG_BINDESC_DEFINE_MAX_DATA_SIZE. ") /** * @brief Define a binary descriptor of type uint. @@ -211,12 +230,16 @@ extern "C" { * @param id Unique ID of the descriptor * @param value A uint8_t array as data for the descriptor */ -#define BINDESC_BYTES_DEFINE(name, id, value) \ - __BINDESC_ENTRY_DEFINE(name) = { \ - .tag = BINDESC_TAG(BYTES, id), \ - .len = (uint16_t)sizeof((uint8_t [])__DEBRACKET value), \ - .data = __DEBRACKET value, \ - } +#define BINDESC_BYTES_DEFINE(name, id, value) \ + __BINDESC_ENTRY_DEFINE(name) = { \ + .tag = BINDESC_TAG(BYTES, id), \ + .len = (uint16_t)sizeof((uint8_t [])__DEBRACKET value), \ + .data = __DEBRACKET value, \ + }; \ + BUILD_ASSERT(sizeof((uint8_t [])__DEBRACKET value) <= \ + CONFIG_BINDESC_DEFINE_MAX_DATA_SIZE, \ + "Bindesc " STRINGIFY(name) " exceeded maximum size, consider reducing the" \ + " size or changing CONFIG_BINDESC_DEFINE_MAX_DATA_SIZE. ") /** * @brief Get the value of a string binary descriptor @@ -265,6 +288,10 @@ extern "C" { */ #define BINDESC_GET_SIZE(name) BINDESC_NAME(name).len +/** + * @} + */ + /* * An entry of the binary descriptor header. Each descriptor is * described by one of these entries. @@ -288,6 +315,176 @@ BUILD_ASSERT(offsetof(struct bindesc_entry, tag) == 0, "Incorrect memory layout" BUILD_ASSERT(offsetof(struct bindesc_entry, len) == 2, "Incorrect memory layout"); BUILD_ASSERT(offsetof(struct bindesc_entry, data) == 4, "Incorrect memory layout"); +struct bindesc_handle { + const uint8_t *address; + enum { + BINDESC_HANDLE_TYPE_RAM, + BINDESC_HANDLE_TYPE_MEMORY_MAPPED_FLASH, + BINDESC_HANDLE_TYPE_FLASH, + } type; + size_t size_limit; +#if IS_ENABLED(CONFIG_BINDESC_READ_FLASH) + const struct device *flash_device; + uint8_t buffer[sizeof(struct bindesc_entry) + + CONFIG_BINDESC_READ_FLASH_MAX_DATA_SIZE] __aligned(BINDESC_ALIGNMENT); +#endif /* IS_ENABLED(CONFIG_BINDESC_READ_FLASH) */ +}; + +/** + * @brief Reading Binary Descriptors of other images. + * @defgroup bindesc_read Bindesc Read + * @ingroup os_services + * @{ + */ + +/** + * @brief Callback type to be called on descriptors found during a walk + * + * @param entry Current descriptor + * @param user_data The user_data given to @ref bindesc_foreach + * + * @return Any non zero value will halt the walk + */ +typedef int (*bindesc_callback_t)(const struct bindesc_entry *entry, void *user_data); + +/** + * @brief Open an image's binary descriptors for reading, from a memory mapped flash + * + * @details + * Initializes a bindesc handle for subsequent calls to bindesc API. + * Memory mapped flash is any flash that can be directly accessed by the CPU, + * without needing to use the flash API for copying the data to RAM. + * + * @param handle Bindesc handle to be given to subsequent calls + * @param offset The offset from the beginning of the flash that the bindesc magic can be found at + * + * @retval 0 On success + * @retval -ENOENT If no bindesc magic was found at the given offset + */ +int bindesc_open_memory_mapped_flash(struct bindesc_handle *handle, size_t offset); + +/** + * @brief Open an image's binary descriptors for reading, from RAM + * + * @details + * Initializes a bindesc handle for subsequent calls to bindesc API. + * It's assumed that the whole bindesc context was copied to RAM prior to calling + * this function, either by the user or by a bootloader. + * + * @note The given address must be aligned to BINDESC_ALIGNMENT + * + * @param handle Bindesc handle to be given to subsequent calls + * @param address The address that the bindesc magic can be found at + * @param max_size Maximum size of the given buffer + * + * @retval 0 On success + * @retval -ENOENT If no bindesc magic was found at the given address + * @retval -EINVAL If the given address is not aligned + */ +int bindesc_open_ram(struct bindesc_handle *handle, const uint8_t *address, size_t max_size); + +/** + * @brief Open an image's binary descriptors for reading, from flash + * + * @details + * Initializes a bindesc handle for subsequent calls to bindesc API. + * As opposed to reading bindesc from RAM or memory mapped flash, this + * backend requires reading the data from flash to an internal buffer + * using the flash API + * + * @param handle Bindesc handle to be given to subsequent calls + * @param offset The offset from the beginning of the flash that the bindesc magic can be found at + * @param flash_device Flash device to read descriptors from + * + * @retval 0 On success + * @retval -ENOENT If no bindesc magic was found at the given offset + */ +int bindesc_open_flash(struct bindesc_handle *handle, size_t offset, + const struct device *flash_device); + +/** + * @brief Walk the binary descriptors and run a user defined callback on each of them + * + * @note + * If the callback returns a non zero value, the walk stops. + * + * @param handle An initialized bindesc handle + * @param callback A user defined callback to be called on each descriptor + * @param user_data User defined data to be given to the callback + * + * @return If the walk was finished prematurely by the callback, + * return the callback's retval, zero otherwise + */ +int bindesc_foreach(struct bindesc_handle *handle, bindesc_callback_t callback, void *user_data); + +/** + * @brief Find a specific descriptor of type string + * + * @warning + * When using the flash backend, result will be invalidated by the next call to any bindesc API. + * Use the value immediately or copy it elsewhere. + * + * @param handle An initialized bindesc handle + * @param id ID to search for + * @param result Pointer to the found string + * + * @retval 0 If the descriptor was found + * @retval -ENOENT If the descriptor was not found + */ +int bindesc_find_str(struct bindesc_handle *handle, uint16_t id, const char **result); + +/** + * @brief Find a specific descriptor of type uint + * + * @warning + * When using the flash backend, result will be invalidated by the next call to any bindesc API. + * Use the value immediately or copy it elsewhere. + * + * @param handle An initialized bindesc handle + * @param id ID to search for + * @param result Pointer to the found uint + * + * @retval 0 If the descriptor was found + * @retval -ENOENT If the descriptor was not found + */ +int bindesc_find_uint(struct bindesc_handle *handle, uint16_t id, const uint32_t **result); + +/** + * @brief Find a specific descriptor of type bytes + * + * @warning + * When using the flash backend, result will be invalidated by the next call to any bindesc API. + * Use the value immediately or copy it elsewhere. + * + * @param handle An initialized bindesc handle + * @param id ID to search for + * @param result Pointer to the found bytes + * @param result_size Size of the found bytes + * + * @retval 0 If the descriptor was found + * @retval -ENOENT If the descriptor was not found + */ +int bindesc_find_bytes(struct bindesc_handle *handle, uint16_t id, const uint8_t **result, + size_t *result_size); + +/** + * @brief Get the size of an image's binary descriptors + * + * @details + * Walks the binary descriptor structure to caluculate the total size of the structure + * in bytes. This is useful, for instance, if the whole structure is to be copied to RAM. + * + * @param handle An initialized bindesc handle + * @param result Pointer to write result to + * + * @return 0 On success, negative errno otherwise + */ +int bindesc_get_size(struct bindesc_handle *handle, size_t *result); + +/** + * @} + */ + #if defined(CONFIG_BINDESC_KERNEL_VERSION_STRING) extern const struct bindesc_entry BINDESC_NAME(kernel_version_string); #endif /* defined(CONFIG_BINDESC_KERNEL_VERSION_STRING) */ @@ -308,6 +505,10 @@ extern const struct bindesc_entry BINDESC_NAME(kernel_version_patchlevel); extern const struct bindesc_entry BINDESC_NAME(kernel_version_number); #endif /* defined(CONFIG_BINDESC_KERNEL_VERSION_NUMBER) */ +#if defined(CONFIG_BINDESC_KERNEL_BUILD_VERSION) +extern const struct bindesc_entry BINDESC_NAME(kernel_build_version); +#endif /* defined(CONFIG_BINDESC_KERNEL_BUILD_VERSION) */ + #if defined(CONFIG_BINDESC_APP_VERSION_STRING) extern const struct bindesc_entry BINDESC_NAME(app_version_string); #endif /* defined(CONFIG_BINDESC_APP_VERSION_STRING) */ @@ -328,6 +529,10 @@ extern const struct bindesc_entry BINDESC_NAME(app_version_patchlevel); extern const struct bindesc_entry BINDESC_NAME(app_version_number); #endif /* defined(CONFIG_BINDESC_APP_VERSION_NUMBER) */ +#if defined(CONFIG_BINDESC_APP_BUILD_VERSION) +extern const struct bindesc_entry BINDESC_NAME(app_build_version); +#endif /* defined(CONFIG_BINDESC_APP_BUILD_VERSION) */ + #if defined(CONFIG_BINDESC_BUILD_TIME_YEAR) extern const struct bindesc_entry BINDESC_NAME(build_time_year); #endif /* defined(CONFIG_BINDESC_BUILD_TIME_YEAR) */ @@ -390,10 +595,6 @@ extern const struct bindesc_entry BINDESC_NAME(cxx_compiler_version); #endif /* !defined(_LINKER) */ -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/aics.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/aics.h index 17f4fea4..9c57d90b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/aics.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/aics.h @@ -15,7 +15,7 @@ /** * @brief Audio Input Control Service (AICS) * - * @defgroup bt_gatt_aics Audio Input Control Service (AICS) + * @defgroup bt_aics Audio Input Control Service (AICS) * * @since 2.6 * @version 0.8.0 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/audio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/audio.h index 3a826179..86b59fd7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/audio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/audio.h @@ -47,9 +47,8 @@ extern "C" { #define BT_AUDIO_PD_PREF_NONE 0x000000U /** Maximum presentation delay in microseconds */ #define BT_AUDIO_PD_MAX 0xFFFFFFU -/** Maximum size of the broadcast code in octets */ -#define BT_AUDIO_BROADCAST_CODE_SIZE 16 - +/** Indicates that the unicast server does not have a preference for any retransmission number */ +#define BT_AUDIO_RTN_PREF_NONE 0xFFU /** The minimum size of a Broadcast Name as defined by Bluetooth Assigned Numbers */ #define BT_AUDIO_BROADCAST_NAME_LEN_MIN 4 /** The maximum size of a Broadcast Name as defined by Bluetooth Assigned Numbers */ @@ -419,6 +418,12 @@ enum bt_audio_active_state { BT_AUDIO_ACTIVE_STATE_ENABLED = 0x01, }; +/** Assisted Listening Stream defined by the Generic Audio assigned numbers (bluetooth.com). */ +enum bt_audio_assisted_listening_stream { + /** Unspecified audio enhancement */ + BT_AUDIO_ASSISTED_LISTENING_STREAM_UNSPECIFIED = 0x00, +}; + /** * @brief Codec metadata type IDs * @@ -435,7 +440,7 @@ enum bt_audio_metadata_type { * * See the BT_AUDIO_CONTEXT_* for valid values. */ - BT_AUDIO_METADATA_TYPE_PREF_CONTEXT = 0x01, + BT_AUDIO_METADATA_TYPE_PREF_CONTEXT = 0x01, /** * @brief Streaming audio context. @@ -447,10 +452,10 @@ enum bt_audio_metadata_type { * * See the BT_AUDIO_CONTEXT_* for valid values. */ - BT_AUDIO_METADATA_TYPE_STREAM_CONTEXT = 0x02, + BT_AUDIO_METADATA_TYPE_STREAM_CONTEXT = 0x02, /** UTF-8 encoded title or summary of stream content */ - BT_AUDIO_METADATA_TYPE_PROGRAM_INFO = 0x03, + BT_AUDIO_METADATA_TYPE_PROGRAM_INFO = 0x03, /** * @brief Language @@ -458,36 +463,46 @@ enum bt_audio_metadata_type { * 3 octet lower case language code defined by ISO 639-3 * Possible values can be found at https://iso639-3.sil.org/code_tables/639/data */ - BT_AUDIO_METADATA_TYPE_LANG = 0x04, + BT_AUDIO_METADATA_TYPE_LANG = 0x04, /** Array of 8-bit CCID values */ - BT_AUDIO_METADATA_TYPE_CCID_LIST = 0x05, + BT_AUDIO_METADATA_TYPE_CCID_LIST = 0x05, /** * @brief Parental rating * * See @ref bt_audio_parental_rating for valid values. */ - BT_AUDIO_METADATA_TYPE_PARENTAL_RATING = 0x06, + BT_AUDIO_METADATA_TYPE_PARENTAL_RATING = 0x06, /** UTF-8 encoded URI for additional Program information */ - BT_AUDIO_METADATA_TYPE_PROGRAM_INFO_URI = 0x07, + BT_AUDIO_METADATA_TYPE_PROGRAM_INFO_URI = 0x07, /** * @brief Audio active state * * See @ref bt_audio_active_state for valid values. */ - BT_AUDIO_METADATA_TYPE_AUDIO_STATE = 0x08, + BT_AUDIO_METADATA_TYPE_AUDIO_STATE = 0x08, /** Broadcast Audio Immediate Rendering flag */ BT_AUDIO_METADATA_TYPE_BROADCAST_IMMEDIATE = 0x09, + /** + * @brief Assisted listening stream + * + * See @ref bt_audio_assisted_listening_stream for valid values. + */ + BT_AUDIO_METADATA_TYPE_ASSISTED_LISTENING_STREAM = 0x0A, + + /** UTF-8 encoded Broadcast name */ + BT_AUDIO_METADATA_TYPE_BROADCAST_NAME = 0x0B, + /** Extended metadata */ - BT_AUDIO_METADATA_TYPE_EXTENDED = 0xFE, + BT_AUDIO_METADATA_TYPE_EXTENDED = 0xFE, /** Vendor specific metadata */ - BT_AUDIO_METADATA_TYPE_VENDOR = 0xFF, + BT_AUDIO_METADATA_TYPE_VENDOR = 0xFF, }; /** @@ -743,13 +758,31 @@ struct bt_audio_codec_cfg { * true to continue parsing, or false to stop parsing. * @param user_data User data to be passed to the callback. * - * @retval 0 if all entries were parsed. - * @retval -EINVAL if the data is incorrectly encoded - * @retval -ECANCELED if parsing was prematurely cancelled by the callback + * @retval 0 All entries were parsed. + * @retval -EINVAL The data is incorrectly encoded + * @retval -ECANCELED Parsing was prematurely cancelled by the callback */ int bt_audio_data_parse(const uint8_t ltv[], size_t size, bool (*func)(struct bt_data *data, void *user_data), void *user_data); +/** + * @brief Get the value of a specific data type in an length-type-value data array + * + * @param[in] ltv_data The array containing the length-type-value tuples + * @param[in] size The size of @p ltv_data + * @param[in] type The type to get the value for. May be any type, but typically either + * @ref bt_audio_codec_cap_type, @ref bt_audio_codec_cfg_type or + * @ref bt_audio_metadata_type. + * @param[out] data Pointer to the data-pointer to update when item is found. + * Any found data will be little endian. + * + * @retval length The length of found @p data (may be 0). + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + */ +int bt_audio_data_get_val(const uint8_t ltv_data[], size_t size, uint8_t type, + const uint8_t **data); + /** * @brief Function to get the number of channels from the channel allocation * @@ -777,251 +810,6 @@ enum bt_audio_dir { BT_AUDIO_DIR_SOURCE = 0x02, }; -/** - * @brief Helper to declare elements of bt_audio_codec_qos - * - * @param _interval SDU interval (usec) - * @param _framing Framing - * @param _phy Target PHY - * @param _sdu Maximum SDU Size - * @param _rtn Retransmission number - * @param _latency Maximum Transport Latency (msec) - * @param _pd Presentation Delay (usec) - */ -#define BT_AUDIO_CODEC_QOS(_interval, _framing, _phy, _sdu, _rtn, _latency, _pd) \ - ((struct bt_audio_codec_qos){ \ - .interval = _interval, \ - .framing = _framing, \ - .phy = _phy, \ - .sdu = _sdu, \ - .rtn = _rtn, \ - IF_ENABLED(UTIL_OR(IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SOURCE), \ - IS_ENABLED(CONFIG_BT_BAP_UNICAST)), \ - (.latency = _latency,)) \ - .pd = _pd, \ - }) - -/** @brief Codec QoS Framing */ -enum bt_audio_codec_qos_framing { - /** Packets may be framed or unframed */ - BT_AUDIO_CODEC_QOS_FRAMING_UNFRAMED = 0x00, - /** Packets are always framed */ - BT_AUDIO_CODEC_QOS_FRAMING_FRAMED = 0x01, -}; - -/** @brief Codec QoS Preferred PHY */ -enum { - /** LE 1M PHY */ - BT_AUDIO_CODEC_QOS_1M = BIT(0), - /** LE 2M PHY */ - BT_AUDIO_CODEC_QOS_2M = BIT(1), - /** LE Coded PHY */ - BT_AUDIO_CODEC_QOS_CODED = BIT(2), -}; - -/** - * @brief Helper to declare Input Unframed bt_audio_codec_qos - * - * @param _interval SDU interval (usec) - * @param _sdu Maximum SDU Size - * @param _rtn Retransmission number - * @param _latency Maximum Transport Latency (msec) - * @param _pd Presentation Delay (usec) - */ -#define BT_AUDIO_CODEC_QOS_UNFRAMED(_interval, _sdu, _rtn, _latency, _pd) \ - BT_AUDIO_CODEC_QOS(_interval, BT_AUDIO_CODEC_QOS_FRAMING_UNFRAMED, BT_AUDIO_CODEC_QOS_2M, \ - _sdu, _rtn, _latency, _pd) - -/** - * @brief Helper to declare Input Framed bt_audio_codec_qos - * - * @param _interval SDU interval (usec) - * @param _sdu Maximum SDU Size - * @param _rtn Retransmission number - * @param _latency Maximum Transport Latency (msec) - * @param _pd Presentation Delay (usec) - */ -#define BT_AUDIO_CODEC_QOS_FRAMED(_interval, _sdu, _rtn, _latency, _pd) \ - BT_AUDIO_CODEC_QOS(_interval, BT_AUDIO_CODEC_QOS_FRAMING_FRAMED, BT_AUDIO_CODEC_QOS_2M, \ - _sdu, _rtn, _latency, _pd) - -/** @brief Codec QoS structure. */ -struct bt_audio_codec_qos { - /** - * @brief Presentation Delay in microseconds - * - * This value can be changed up and until bt_bap_stream_qos() has been called. - * Once a stream has been QoS configured, modifying this field does not modify the value. - * It is however possible to modify this field and call bt_bap_stream_qos() again to update - * the value, assuming that the stream is in the correct state. - * - * Value range 0 to @ref BT_AUDIO_PD_MAX. - */ - uint32_t pd; - - /** - * @brief Connected Isochronous Group (CIG) parameters - * - * The fields in this struct affect the value sent to the controller via HCI - * when creating the CIG. Once the group has been created with - * bt_bap_unicast_group_create(), modifying these fields will not affect the group. - */ - struct { - /** QoS Framing */ - enum bt_audio_codec_qos_framing framing; - - /** - * @brief PHY - * - * Allowed values are @ref BT_AUDIO_CODEC_QOS_1M, @ref BT_AUDIO_CODEC_QOS_2M and - * @ref BT_AUDIO_CODEC_QOS_CODED. - */ - uint8_t phy; - - /** - * @brief Retransmission Number - * - * This a recommendation to the controller, and the actual retransmission number - * may be different than this. - */ - uint8_t rtn; - - /** - * @brief Maximum SDU size - * - * Value range @ref BT_ISO_MIN_SDU to @ref BT_ISO_MAX_SDU. - */ - uint16_t sdu; - -#if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) || defined(CONFIG_BT_BAP_UNICAST) || \ - defined(__DOXYGEN__) - /** - * @brief Maximum Transport Latency - * - * Not used for the @kconfig{CONFIG_BT_BAP_BROADCAST_SINK} role. - */ - uint16_t latency; -#endif /* CONFIG_BT_BAP_BROADCAST_SOURCE || CONFIG_BT_BAP_UNICAST */ - - /** - * @brief SDU Interval - * - * Value range @ref BT_ISO_SDU_INTERVAL_MIN to @ref BT_ISO_SDU_INTERVAL_MAX - */ - uint32_t interval; - -#if defined(CONFIG_BT_ISO_TEST_PARAMS) || defined(__DOXYGEN__) - /** - * @brief Maximum PDU size - * - * Maximum size, in octets, of the payload from link layer to link layer. - * - * Value range @ref BT_ISO_CONNECTED_PDU_MIN to @ref BT_ISO_PDU_MAX for - * connected ISO. - * - * Value range @ref BT_ISO_BROADCAST_PDU_MIN to @ref BT_ISO_PDU_MAX for - * broadcast ISO. - */ - uint16_t max_pdu; - - /** - * @brief Burst number - * - * Value range @ref BT_ISO_BN_MIN to @ref BT_ISO_BN_MAX. - */ - uint8_t burst_number; - - /** - * @brief Number of subevents - * - * Maximum number of subevents in each CIS or BIS event. - * - * Value range @ref BT_ISO_NSE_MIN to @ref BT_ISO_NSE_MAX. - */ - uint8_t num_subevents; -#endif /* CONFIG_BT_ISO_TEST_PARAMS */ - }; -}; - -/** - * @brief Helper to declare elements of @ref bt_audio_codec_qos_pref - * - * @param _unframed_supported Unframed PDUs supported - * @param _phy Preferred Target PHY - * @param _rtn Preferred Retransmission number - * @param _latency Preferred Maximum Transport Latency (msec) - * @param _pd_min Minimum Presentation Delay (usec) - * @param _pd_max Maximum Presentation Delay (usec) - * @param _pref_pd_min Preferred Minimum Presentation Delay (usec) - * @param _pref_pd_max Preferred Maximum Presentation Delay (usec) - */ -#define BT_AUDIO_CODEC_QOS_PREF(_unframed_supported, _phy, _rtn, _latency, _pd_min, _pd_max, \ - _pref_pd_min, _pref_pd_max) \ - { \ - .unframed_supported = _unframed_supported, \ - .phy = _phy, \ - .rtn = _rtn, \ - .latency = _latency, \ - .pd_min = _pd_min, \ - .pd_max = _pd_max, \ - .pref_pd_min = _pref_pd_min, \ - .pref_pd_max = _pref_pd_max, \ - } - -/** @brief Audio Stream Quality of Service Preference structure. */ -struct bt_audio_codec_qos_pref { - /** - * @brief Unframed PDUs supported - * - * Unlike the other fields, this is not a preference but whether - * the codec supports unframed ISOAL PDUs. - */ - bool unframed_supported; - - /** Preferred PHY */ - uint8_t phy; - - /** Preferred Retransmission Number */ - uint8_t rtn; - - /** Preferred Transport Latency */ - uint16_t latency; - - /** - * @brief Minimum Presentation Delay in microseconds - * - * Unlike the other fields, this is not a preference but a minimum requirement. - * - * Value range 0 to @ref BT_AUDIO_PD_MAX, or @ref BT_AUDIO_PD_PREF_NONE - * to indicate no preference. - */ - uint32_t pd_min; - - /** - * @brief Maximum Presentation Delay - * - * Unlike the other fields, this is not a preference but a maximum requirement. - * - * Value range 0 to @ref BT_AUDIO_PD_MAX, or @ref BT_AUDIO_PD_PREF_NONE - * to indicate no preference. - */ - uint32_t pd_max; - - /** - * @brief Preferred minimum Presentation Delay - * - * Value range 0 to @ref BT_AUDIO_PD_MAX. - */ - uint32_t pref_pd_min; - - /** - * @brief Preferred maximum Presentation Delay - * - * Value range 0 to @ref BT_AUDIO_PD_MAX. - */ - uint32_t pref_pd_max; -}; - /** * @brief Audio codec Config APIs * @defgroup bt_audio_codec_cfg Codec config parsing APIs @@ -1036,8 +824,8 @@ struct bt_audio_codec_qos_pref { * * @param freq The assigned numbers frequency to convert. * - * @retval -EINVAL if arguments are invalid. - * @retval The converted frequency value in Hz. + * @retval frequency The converted frequency value in Hz. + * @retval -EINVAL Arguments are invalid. */ int bt_audio_codec_cfg_freq_to_freq_hz(enum bt_audio_codec_cfg_freq freq); @@ -1046,8 +834,8 @@ int bt_audio_codec_cfg_freq_to_freq_hz(enum bt_audio_codec_cfg_freq freq); * * @param freq_hz The frequency value to convert. * - * @retval -EINVAL if arguments are invalid. - * @retval The assigned numbers frequency (@ref bt_audio_codec_cfg_freq). + * @retval frequency The assigned numbers frequency (@ref bt_audio_codec_cfg_freq). + * @retval -EINVAL Arguments are invalid. */ int bt_audio_codec_cfg_freq_hz_to_freq(uint32_t freq_hz); @@ -1056,10 +844,10 @@ int bt_audio_codec_cfg_freq_hz_to_freq(uint32_t freq_hz); * * @param codec_cfg The codec configuration to extract data from. * - * @retval A @ref bt_audio_codec_cfg_freq value - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval frequency A @ref bt_audio_codec_cfg_freq value + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cfg_get_freq(const struct bt_audio_codec_cfg *codec_cfg); @@ -1069,9 +857,9 @@ int bt_audio_codec_cfg_get_freq(const struct bt_audio_codec_cfg *codec_cfg); * @param codec_cfg The codec configuration to set data for. * @param freq The assigned numbers frequency to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_set_freq(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_codec_cfg_freq freq); @@ -1081,8 +869,8 @@ int bt_audio_codec_cfg_set_freq(struct bt_audio_codec_cfg *codec_cfg, * * @param frame_dur The assigned numbers frame duration to convert. * - * @retval -EINVAL if arguments are invalid. - * @retval The converted frame duration value in microseconds. + * @retval duration The converted frame duration value in microseconds. + * @retval -EINVAL Arguments are invalid. */ int bt_audio_codec_cfg_frame_dur_to_frame_dur_us(enum bt_audio_codec_cfg_frame_dur frame_dur); @@ -1091,8 +879,8 @@ int bt_audio_codec_cfg_frame_dur_to_frame_dur_us(enum bt_audio_codec_cfg_frame_d * * @param frame_dur_us The frame duration in microseconds to convert. * - * @retval -EINVAL if arguments are invalid. - * @retval The assigned numbers frame duration (@ref bt_audio_codec_cfg_frame_dur). + * @retval duration The assigned numbers frame duration (@ref bt_audio_codec_cfg_frame_dur). + * @retval -EINVAL Arguments are invalid. */ int bt_audio_codec_cfg_frame_dur_us_to_frame_dur(uint32_t frame_dur_us); @@ -1101,10 +889,10 @@ int bt_audio_codec_cfg_frame_dur_us_to_frame_dur(uint32_t frame_dur_us); * * @param codec_cfg The codec configuration to extract data from. * - * @retval A @ref bt_audio_codec_cfg_frame_dur value - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval frequency A @ref bt_audio_codec_cfg_frame_dur value + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cfg_get_frame_dur(const struct bt_audio_codec_cfg *codec_cfg); @@ -1114,9 +902,9 @@ int bt_audio_codec_cfg_get_frame_dur(const struct bt_audio_codec_cfg *codec_cfg) * @param codec_cfg The codec configuration to set data for. * @param frame_dur The assigned numbers frame duration to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_set_frame_dur(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_codec_cfg_frame_dur frame_dur); @@ -1136,10 +924,10 @@ int bt_audio_codec_cfg_set_frame_dur(struct bt_audio_codec_cfg *codec_cfg, * @ref BT_AUDIO_LOCATION_MONO_AUDIO if the type is not found when @p codec_cfg.id is @ref * BT_HCI_CODING_FORMAT_LC3. * - * @retval 0 if value is found and stored in the pointer provided - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval 0 Value is found and stored in the pointer provided + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cfg_get_chan_allocation(const struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_location *chan_allocation, @@ -1151,9 +939,9 @@ int bt_audio_codec_cfg_get_chan_allocation(const struct bt_audio_codec_cfg *code * @param codec_cfg The codec configuration to set data for. * @param chan_allocation The channel allocation to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_set_chan_allocation(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_location chan_allocation); @@ -1172,10 +960,10 @@ int bt_audio_codec_cfg_set_chan_allocation(struct bt_audio_codec_cfg *codec_cfg, * * @param codec_cfg The codec configuration to extract data from. * - * @retval Frame length in octets - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval frame_length Frame length in octets + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cfg_get_octets_per_frame(const struct bt_audio_codec_cfg *codec_cfg); @@ -1185,9 +973,9 @@ int bt_audio_codec_cfg_get_octets_per_frame(const struct bt_audio_codec_cfg *cod * @param codec_cfg The codec configuration to set data for. * @param octets_per_frame The octets per codec frame to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_set_octets_per_frame(struct bt_audio_codec_cfg *codec_cfg, uint16_t octets_per_frame); @@ -1207,10 +995,10 @@ int bt_audio_codec_cfg_set_octets_per_frame(struct bt_audio_codec_cfg *codec_cfg * @param fallback_to_default If true this function will return the default value of 1 * if the type is not found when @p codec_cfg.id is @ref BT_HCI_CODING_FORMAT_LC3. * - * @retval The count of codec frame blocks in each SDU. - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval frame_blocks_per_sdu The count of codec frame blocks in each SDU. + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cfg_get_frame_blocks_per_sdu(const struct bt_audio_codec_cfg *codec_cfg, bool fallback_to_default); @@ -1221,9 +1009,9 @@ int bt_audio_codec_cfg_get_frame_blocks_per_sdu(const struct bt_audio_codec_cfg * @param codec_cfg The codec configuration to set data for. * @param frame_blocks The frame blocks per SDU to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_set_frame_blocks_per_sdu(struct bt_audio_codec_cfg *codec_cfg, uint8_t frame_blocks); @@ -1235,9 +1023,9 @@ int bt_audio_codec_cfg_set_frame_blocks_per_sdu(struct bt_audio_codec_cfg *codec * @param[in] type The type id to look for * @param[out] data Pointer to the data-pointer to update when item is found * - * @retval Length of found @p data (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len Length of found @p data (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_get_val(const struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_codec_cfg_type type, const uint8_t **data); @@ -1250,9 +1038,9 @@ int bt_audio_codec_cfg_get_val(const struct bt_audio_codec_cfg *codec_cfg, * @param data Pointer to the data-pointer to set * @param data_len Length of @p data * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_set_val(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_codec_cfg_type type, const uint8_t *data, @@ -1266,8 +1054,8 @@ int bt_audio_codec_cfg_set_val(struct bt_audio_codec_cfg *codec_cfg, * @param codec_cfg The codec data to set the value in. * @param type The type id to unset. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid */ int bt_audio_codec_cfg_unset_val(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_codec_cfg_type type); @@ -1280,9 +1068,9 @@ int bt_audio_codec_cfg_unset_val(struct bt_audio_codec_cfg *codec_cfg, * @param[in] type The type id to look for * @param[out] data Pointer to the data-pointer to update when item is found * - * @retval Length of found @p data (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len Length of found @p data (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_meta_get_val(const struct bt_audio_codec_cfg *codec_cfg, uint8_t type, const uint8_t **data); @@ -1295,9 +1083,9 @@ int bt_audio_codec_cfg_meta_get_val(const struct bt_audio_codec_cfg *codec_cfg, * @param data Pointer to the data-pointer to set. * @param data_len Length of @p data. * - * @retval The meta_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval meta_len The @p codec_cfg.meta_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_val(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_metadata_type type, const uint8_t *data, @@ -1311,8 +1099,8 @@ int bt_audio_codec_cfg_meta_set_val(struct bt_audio_codec_cfg *codec_cfg, * @param codec_cfg The codec data to set the value in. * @param type The type id to unset. * - * @retval The meta_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid + * @retval meta_len The of @p codec_cfg.meta_len success + * @retval -EINVAL Arguments are invalid */ int bt_audio_codec_cfg_meta_unset_val(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_metadata_type type); @@ -1326,10 +1114,10 @@ int bt_audio_codec_cfg_meta_unset_val(struct bt_audio_codec_cfg *codec_cfg, * @ref BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED if the type is not found when @p codec_cfg.id is * @ref BT_HCI_CODING_FORMAT_LC3. * - * @retval The preferred context type if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval context The preferred context type if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cfg_meta_get_pref_context(const struct bt_audio_codec_cfg *codec_cfg, bool fallback_to_default); @@ -1340,9 +1128,9 @@ int bt_audio_codec_cfg_meta_get_pref_context(const struct bt_audio_codec_cfg *co * @param codec_cfg The codec configuration to set data for. * @param ctx The preferred context to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_pref_context(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_context ctx); @@ -1354,10 +1142,10 @@ int bt_audio_codec_cfg_meta_set_pref_context(struct bt_audio_codec_cfg *codec_cf * * @param codec_cfg The codec data to search in. * - * @retval The stream context type if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval context The stream context type if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cfg_meta_get_stream_context(const struct bt_audio_codec_cfg *codec_cfg); @@ -1367,9 +1155,9 @@ int bt_audio_codec_cfg_meta_get_stream_context(const struct bt_audio_codec_cfg * * @param codec_cfg The codec configuration to set data for. * @param ctx The stream context to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_stream_context(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_context ctx); @@ -1382,9 +1170,9 @@ int bt_audio_codec_cfg_meta_set_stream_context(struct bt_audio_codec_cfg *codec_ * @param[in] codec_cfg The codec data to search in. * @param[out] program_info Pointer to the UTF-8 formatted program info. * - * @retval The length of the @p program_info (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p program_info (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_meta_get_program_info(const struct bt_audio_codec_cfg *codec_cfg, const uint8_t **program_info); @@ -1396,9 +1184,9 @@ int bt_audio_codec_cfg_meta_get_program_info(const struct bt_audio_codec_cfg *co * @param program_info The program info to set. * @param program_info_len The length of @p program_info. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_program_info(struct bt_audio_codec_cfg *codec_cfg, const uint8_t *program_info, size_t program_info_len); @@ -1411,10 +1199,10 @@ int bt_audio_codec_cfg_meta_set_program_info(struct bt_audio_codec_cfg *codec_cf * @param[in] codec_cfg The codec data to search in. * @param[out] lang Pointer to the language bytes (of length BT_AUDIO_LANG_SIZE) * - * @retval The language if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval 0 Success + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cfg_meta_get_lang(const struct bt_audio_codec_cfg *codec_cfg, const uint8_t **lang); @@ -1425,9 +1213,9 @@ int bt_audio_codec_cfg_meta_get_lang(const struct bt_audio_codec_cfg *codec_cfg, * @param codec_cfg The codec configuration to set data for. * @param lang The 24-bit language to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_lang(struct bt_audio_codec_cfg *codec_cfg, const uint8_t lang[BT_AUDIO_LANG_SIZE]); @@ -1440,9 +1228,9 @@ int bt_audio_codec_cfg_meta_set_lang(struct bt_audio_codec_cfg *codec_cfg, * @param[in] codec_cfg The codec data to search in. * @param[out] ccid_list Pointer to the array containing 8-bit CCIDs. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p ccid_list (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_meta_get_ccid_list(const struct bt_audio_codec_cfg *codec_cfg, const uint8_t **ccid_list); @@ -1454,9 +1242,9 @@ int bt_audio_codec_cfg_meta_get_ccid_list(const struct bt_audio_codec_cfg *codec * @param ccid_list The program info to set. * @param ccid_list_len The length of @p ccid_list. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_ccid_list(struct bt_audio_codec_cfg *codec_cfg, const uint8_t *ccid_list, size_t ccid_list_len); @@ -1468,10 +1256,10 @@ int bt_audio_codec_cfg_meta_set_ccid_list(struct bt_audio_codec_cfg *codec_cfg, * * @param codec_cfg The codec data to search in. * - * @retval The parental rating if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval parental_rating The parental rating if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cfg_meta_get_parental_rating(const struct bt_audio_codec_cfg *codec_cfg); @@ -1481,9 +1269,9 @@ int bt_audio_codec_cfg_meta_get_parental_rating(const struct bt_audio_codec_cfg * @param codec_cfg The codec configuration to set data for. * @param parental_rating The parental rating to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_parental_rating(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_parental_rating parental_rating); @@ -1496,9 +1284,9 @@ int bt_audio_codec_cfg_meta_set_parental_rating(struct bt_audio_codec_cfg *codec * @param[in] codec_cfg The codec data to search in. * @param[out] program_info_uri Pointer to the UTF-8 formatted program info URI. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p program_info_uri (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_meta_get_program_info_uri(const struct bt_audio_codec_cfg *codec_cfg, const uint8_t **program_info_uri); @@ -1510,9 +1298,9 @@ int bt_audio_codec_cfg_meta_get_program_info_uri(const struct bt_audio_codec_cfg * @param program_info_uri The program info URI to set. * @param program_info_uri_len The length of @p program_info_uri. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_program_info_uri(struct bt_audio_codec_cfg *codec_cfg, const uint8_t *program_info_uri, @@ -1525,10 +1313,10 @@ int bt_audio_codec_cfg_meta_set_program_info_uri(struct bt_audio_codec_cfg *code * * @param codec_cfg The codec data to search in. * - * @retval The preferred context type if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval context The preferred context type if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cfg_meta_get_audio_active_state(const struct bt_audio_codec_cfg *codec_cfg); @@ -1538,9 +1326,9 @@ int bt_audio_codec_cfg_meta_get_audio_active_state(const struct bt_audio_codec_c * @param codec_cfg The codec configuration to set data for. * @param state The audio active state to set. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_audio_active_state(struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_active_state state); @@ -1552,9 +1340,9 @@ int bt_audio_codec_cfg_meta_set_audio_active_state(struct bt_audio_codec_cfg *co * * @param codec_cfg The codec data to search in. * - * @retval 0 if the flag was found - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not the flag was not found + * @retval 0 The flag was found + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA The flag was not found */ int bt_audio_codec_cfg_meta_get_bcast_audio_immediate_rend_flag( const struct bt_audio_codec_cfg *codec_cfg); @@ -1564,13 +1352,71 @@ int bt_audio_codec_cfg_meta_get_bcast_audio_immediate_rend_flag( * * @param codec_cfg The codec configuration to set data for. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_bcast_audio_immediate_rend_flag( struct bt_audio_codec_cfg *codec_cfg); +/** + * @brief Extract assisted listening stream + * + * See @ref BT_AUDIO_METADATA_TYPE_ASSISTED_LISTENING_STREAM for more information about this value. + * + * @param codec_cfg The codec data to search in. + * + * @retval value The assisted listening stream value if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size + */ +int bt_audio_codec_cfg_meta_get_assisted_listening_stream( + const struct bt_audio_codec_cfg *codec_cfg); + +/** + * @brief Set the assisted listening stream value of a codec configuration metadata. + * + * @param codec_cfg The codec configuration to set data for. + * @param val The assisted listening stream value to set. + * + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory + */ +int bt_audio_codec_cfg_meta_set_assisted_listening_stream( + struct bt_audio_codec_cfg *codec_cfg, enum bt_audio_assisted_listening_stream val); + +/** + * @brief Extract broadcast name + * + * See @ref BT_AUDIO_METADATA_TYPE_BROADCAST_NAME for more information about this value. + * + * @param[in] codec_cfg The codec data to search in. + * @param[out] broadcast_name Pointer to the UTF-8 formatted broadcast name. + * + * @retval length The length of the @p broadcast_name (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + */ +int bt_audio_codec_cfg_meta_get_broadcast_name(const struct bt_audio_codec_cfg *codec_cfg, + const uint8_t **broadcast_name); + +/** + * @brief Set the broadcast name of a codec configuration metadata. + * + * @param codec_cfg The codec configuration to set data for. + * @param broadcast_name The broadcast name to set. + * @param broadcast_name_len The length of @p broadcast_name. + * + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory + */ +int bt_audio_codec_cfg_meta_set_broadcast_name(struct bt_audio_codec_cfg *codec_cfg, + const uint8_t *broadcast_name, + size_t broadcast_name_len); + /** * @brief Extract extended metadata * @@ -1579,9 +1425,9 @@ int bt_audio_codec_cfg_meta_set_bcast_audio_immediate_rend_flag( * @param[in] codec_cfg The codec data to search in. * @param[out] extended_meta Pointer to the extended metadata. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p extended_meta (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_meta_get_extended(const struct bt_audio_codec_cfg *codec_cfg, const uint8_t **extended_meta); @@ -1593,9 +1439,9 @@ int bt_audio_codec_cfg_meta_get_extended(const struct bt_audio_codec_cfg *codec_ * @param extended_meta The extended metadata to set. * @param extended_meta_len The length of @p extended_meta. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_extended(struct bt_audio_codec_cfg *codec_cfg, const uint8_t *extended_meta, size_t extended_meta_len); @@ -1608,9 +1454,9 @@ int bt_audio_codec_cfg_meta_set_extended(struct bt_audio_codec_cfg *codec_cfg, * @param[in] codec_cfg The codec data to search in. * @param[out] vendor_meta Pointer to the vendor specific metadata. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p vendor_meta (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cfg_meta_get_vendor(const struct bt_audio_codec_cfg *codec_cfg, const uint8_t **vendor_meta); @@ -1622,9 +1468,9 @@ int bt_audio_codec_cfg_meta_get_vendor(const struct bt_audio_codec_cfg *codec_cf * @param vendor_meta The vendor specific metadata to set. * @param vendor_meta_len The length of @p vendor_meta. * - * @retval The data_len of @p codec_cfg on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cfg.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cfg_meta_set_vendor(struct bt_audio_codec_cfg *codec_cfg, const uint8_t *vendor_meta, size_t vendor_meta_len); @@ -1647,9 +1493,9 @@ int bt_audio_codec_cfg_meta_set_vendor(struct bt_audio_codec_cfg *codec_cfg, * @param[in] type The type id to look for * @param[out] data Pointer to the data-pointer to update when item is found * - * @retval Length of found @p data (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len Length of found @p data (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_get_val(const struct bt_audio_codec_cap *codec_cap, enum bt_audio_codec_cap_type type, const uint8_t **data); @@ -1662,9 +1508,9 @@ int bt_audio_codec_cap_get_val(const struct bt_audio_codec_cap *codec_cap, * @param data Pointer to the data-pointer to set * @param data_len Length of @p data * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_set_val(struct bt_audio_codec_cap *codec_cap, enum bt_audio_codec_cap_type type, const uint8_t *data, @@ -1678,8 +1524,8 @@ int bt_audio_codec_cap_set_val(struct bt_audio_codec_cap *codec_cap, * @param codec_cap The codec data to set the value in. * @param type The type id to unset. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid */ int bt_audio_codec_cap_unset_val(struct bt_audio_codec_cap *codec_cap, enum bt_audio_codec_cap_type type); @@ -1689,10 +1535,11 @@ int bt_audio_codec_cap_unset_val(struct bt_audio_codec_cap *codec_cap, * * @param codec_cap The codec capabilities to extract data from. * - * @retval Bitfield of supported frequencies (@ref bt_audio_codec_cap_freq) if 0 or positive - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval frequencies Bitfield of supported frequencies (@ref bt_audio_codec_cap_freq) if 0 or + * positive + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cap_get_freq(const struct bt_audio_codec_cap *codec_cap); @@ -1702,9 +1549,9 @@ int bt_audio_codec_cap_get_freq(const struct bt_audio_codec_cap *codec_cap); * @param codec_cap The codec capabilities to set data for. * @param freq The supported frequencies to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_set_freq(struct bt_audio_codec_cap *codec_cap, enum bt_audio_codec_cap_freq freq); @@ -1714,10 +1561,10 @@ int bt_audio_codec_cap_set_freq(struct bt_audio_codec_cap *codec_cap, * * @param codec_cap The codec capabilities to extract data from. * - * @retval Bitfield of supported frame durations if 0 or positive - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval durations Bitfield of supported frame durations if 0 or positive + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cap_get_frame_dur(const struct bt_audio_codec_cap *codec_cap); @@ -1727,9 +1574,9 @@ int bt_audio_codec_cap_get_frame_dur(const struct bt_audio_codec_cap *codec_cap) * @param codec_cap The codec capabilities to set data for. * @param frame_dur The frame duration to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_set_frame_dur(struct bt_audio_codec_cap *codec_cap, enum bt_audio_codec_cap_frame_dur frame_dur); @@ -1741,10 +1588,10 @@ int bt_audio_codec_cap_set_frame_dur(struct bt_audio_codec_cap *codec_cap, * @param fallback_to_default If true this function will provide the default value of 1 * if the type is not found when @p codec_cap.id is @ref BT_HCI_CODING_FORMAT_LC3. * - * @retval Number of supported channel counts if 0 or positive - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval channel_counts Number of supported channel counts if 0 or positive + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cap_get_supported_audio_chan_counts(const struct bt_audio_codec_cap *codec_cap, bool fallback_to_default); @@ -1755,9 +1602,9 @@ int bt_audio_codec_cap_get_supported_audio_chan_counts(const struct bt_audio_cod * @param codec_cap The codec capabilities to set data for. * @param chan_count The channel count frequency to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_set_supported_audio_chan_counts( struct bt_audio_codec_cap *codec_cap, enum bt_audio_codec_cap_chan_count chan_count); @@ -1768,10 +1615,10 @@ int bt_audio_codec_cap_set_supported_audio_chan_counts( * @param[in] codec_cap The codec capabilities to extract data from. * @param[out] codec_frame Struct to place the resulting values in * - * @retval 0 on success - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval 0 Success + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cap_get_octets_per_frame( const struct bt_audio_codec_cap *codec_cap, @@ -1783,9 +1630,9 @@ int bt_audio_codec_cap_get_octets_per_frame( * @param codec_cap The codec capabilities to set data for. * @param codec_frame The octets per codec frame to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_set_octets_per_frame( struct bt_audio_codec_cap *codec_cap, @@ -1798,10 +1645,10 @@ int bt_audio_codec_cap_set_octets_per_frame( * @param fallback_to_default If true this function will provide the default value of 1 * if the type is not found when @p codec_cap.id is @ref BT_HCI_CODING_FORMAT_LC3. * - * @retval Maximum number of codec frames per SDU supported - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size or value + * @retval codec_frames_per_sdu Maximum number of codec frames per SDU supported + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size or value */ int bt_audio_codec_cap_get_max_codec_frames_per_sdu(const struct bt_audio_codec_cap *codec_cap, bool fallback_to_default); @@ -1812,9 +1659,9 @@ int bt_audio_codec_cap_get_max_codec_frames_per_sdu(const struct bt_audio_codec_ * @param codec_cap The codec capabilities to set data for. * @param codec_frames_per_sdu The maximum codec frames per SDU to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_set_max_codec_frames_per_sdu(struct bt_audio_codec_cap *codec_cap, uint8_t codec_frames_per_sdu); @@ -1826,9 +1673,9 @@ int bt_audio_codec_cap_set_max_codec_frames_per_sdu(struct bt_audio_codec_cap *c * @param[in] type The type id to look for * @param[out] data Pointer to the data-pointer to update when item is found * - * @retval Length of found @p data (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len Length of found @p data (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_meta_get_val(const struct bt_audio_codec_cap *codec_cap, uint8_t type, const uint8_t **data); @@ -1841,9 +1688,9 @@ int bt_audio_codec_cap_meta_get_val(const struct bt_audio_codec_cap *codec_cap, * @param data Pointer to the data-pointer to set. * @param data_len Length of @p data. * - * @retval The meta_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval meta_len The @p codec_cap.meta_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_val(struct bt_audio_codec_cap *codec_cap, enum bt_audio_metadata_type type, const uint8_t *data, @@ -1857,8 +1704,8 @@ int bt_audio_codec_cap_meta_set_val(struct bt_audio_codec_cap *codec_cap, * @param codec_cap The codec data to set the value in. * @param type The type id to unset. * - * @retval The meta_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid + * @retval meta_len The of @p codec_cap.meta_len on success + * @retval -EINVAL Arguments are invalid */ int bt_audio_codec_cap_meta_unset_val(struct bt_audio_codec_cap *codec_cap, enum bt_audio_metadata_type type); @@ -1871,9 +1718,9 @@ int bt_audio_codec_cap_meta_unset_val(struct bt_audio_codec_cap *codec_cap, * @param codec_cap The codec data to search in. * * @retval The preferred context type if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cap_meta_get_pref_context(const struct bt_audio_codec_cap *codec_cap); @@ -1883,9 +1730,9 @@ int bt_audio_codec_cap_meta_get_pref_context(const struct bt_audio_codec_cap *co * @param codec_cap The codec capability to set data for. * @param ctx The preferred context to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_pref_context(struct bt_audio_codec_cap *codec_cap, enum bt_audio_context ctx); @@ -1897,10 +1744,10 @@ int bt_audio_codec_cap_meta_set_pref_context(struct bt_audio_codec_cap *codec_ca * * @param codec_cap The codec data to search in. * - * @retval The stream context type if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval context The stream context type if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cap_meta_get_stream_context(const struct bt_audio_codec_cap *codec_cap); @@ -1910,9 +1757,9 @@ int bt_audio_codec_cap_meta_get_stream_context(const struct bt_audio_codec_cap * * @param codec_cap The codec capability to set data for. * @param ctx The stream context to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_stream_context(struct bt_audio_codec_cap *codec_cap, enum bt_audio_context ctx); @@ -1925,9 +1772,9 @@ int bt_audio_codec_cap_meta_set_stream_context(struct bt_audio_codec_cap *codec_ * @param[in] codec_cap The codec data to search in. * @param[out] program_info Pointer to the UTF-8 formatted program info. * - * @retval The length of the @p program_info (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p program_info (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_meta_get_program_info(const struct bt_audio_codec_cap *codec_cap, const uint8_t **program_info); @@ -1939,9 +1786,9 @@ int bt_audio_codec_cap_meta_get_program_info(const struct bt_audio_codec_cap *co * @param program_info The program info to set. * @param program_info_len The length of @p program_info. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_program_info(struct bt_audio_codec_cap *codec_cap, const uint8_t *program_info, size_t program_info_len); @@ -1954,10 +1801,10 @@ int bt_audio_codec_cap_meta_set_program_info(struct bt_audio_codec_cap *codec_ca * @param[in] codec_cap The codec data to search in. * @param[out] lang Pointer to the language bytes (of length BT_AUDIO_LANG_SIZE) * - * @retval 0 On success - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval 0 Success + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cap_meta_get_lang(const struct bt_audio_codec_cap *codec_cap, const uint8_t **lang); @@ -1968,9 +1815,9 @@ int bt_audio_codec_cap_meta_get_lang(const struct bt_audio_codec_cap *codec_cap, * @param codec_cap The codec capability to set data for. * @param lang The 24-bit language to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_lang(struct bt_audio_codec_cap *codec_cap, const uint8_t lang[BT_AUDIO_LANG_SIZE]); @@ -1983,9 +1830,9 @@ int bt_audio_codec_cap_meta_set_lang(struct bt_audio_codec_cap *codec_cap, * @param[in] codec_cap The codec data to search in. * @param[out] ccid_list Pointer to the array containing 8-bit CCIDs. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p ccid_list (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_meta_get_ccid_list(const struct bt_audio_codec_cap *codec_cap, const uint8_t **ccid_list); @@ -1997,9 +1844,9 @@ int bt_audio_codec_cap_meta_get_ccid_list(const struct bt_audio_codec_cap *codec * @param ccid_list The program info to set. * @param ccid_list_len The length of @p ccid_list. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_ccid_list(struct bt_audio_codec_cap *codec_cap, const uint8_t *ccid_list, size_t ccid_list_len); @@ -2012,9 +1859,9 @@ int bt_audio_codec_cap_meta_set_ccid_list(struct bt_audio_codec_cap *codec_cap, * @param codec_cap The codec data to search in. * * @retval The parental rating if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cap_meta_get_parental_rating(const struct bt_audio_codec_cap *codec_cap); @@ -2024,9 +1871,9 @@ int bt_audio_codec_cap_meta_get_parental_rating(const struct bt_audio_codec_cap * @param codec_cap The codec capability to set data for. * @param parental_rating The parental rating to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_parental_rating(struct bt_audio_codec_cap *codec_cap, enum bt_audio_parental_rating parental_rating); @@ -2039,9 +1886,9 @@ int bt_audio_codec_cap_meta_set_parental_rating(struct bt_audio_codec_cap *codec * @param[in] codec_cap The codec data to search in. * @param[out] program_info_uri Pointer to the UTF-8 formatted program info URI. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p program_info_uri (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_meta_get_program_info_uri(const struct bt_audio_codec_cap *codec_cap, const uint8_t **program_info_uri); @@ -2053,9 +1900,9 @@ int bt_audio_codec_cap_meta_get_program_info_uri(const struct bt_audio_codec_cap * @param program_info_uri The program info URI to set. * @param program_info_uri_len The length of @p program_info_uri. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_program_info_uri(struct bt_audio_codec_cap *codec_cap, const uint8_t *program_info_uri, @@ -2068,10 +1915,10 @@ int bt_audio_codec_cap_meta_set_program_info_uri(struct bt_audio_codec_cap *code * * @param codec_cap The codec data to search in. * - * @retval The preferred context type if positive or 0 - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found - * @retval -EBADMSG if found value has invalid size + * @retval context The preferred context type if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size */ int bt_audio_codec_cap_meta_get_audio_active_state(const struct bt_audio_codec_cap *codec_cap); @@ -2081,9 +1928,9 @@ int bt_audio_codec_cap_meta_get_audio_active_state(const struct bt_audio_codec_c * @param codec_cap The codec capability to set data for. * @param state The audio active state to set. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_audio_active_state(struct bt_audio_codec_cap *codec_cap, enum bt_audio_active_state state); @@ -2095,9 +1942,9 @@ int bt_audio_codec_cap_meta_set_audio_active_state(struct bt_audio_codec_cap *co * * @param codec_cap The codec data to search in. * - * @retval 0 if the flag was found - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not the flag was not found + * @retval 0 The flag was found + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA The flag was not found */ int bt_audio_codec_cap_meta_get_bcast_audio_immediate_rend_flag( const struct bt_audio_codec_cap *codec_cap); @@ -2107,13 +1954,70 @@ int bt_audio_codec_cap_meta_get_bcast_audio_immediate_rend_flag( * * @param codec_cap The codec capability to set data for. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_bcast_audio_immediate_rend_flag( struct bt_audio_codec_cap *codec_cap); +/** + * @brief Extract assisted listening stream + * + * See @ref BT_AUDIO_METADATA_TYPE_ASSISTED_LISTENING_STREAM for more information about this value. + * + * @param codec_cap The codec data to search in. + * + * @retval value The assisted listening stream value if positive or 0 + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + * @retval -EBADMSG The found value has invalid size + */ +int bt_audio_codec_cap_meta_get_assisted_listening_stream( + const struct bt_audio_codec_cap *codec_cap); + +/** + * @brief Set the assisted listening stream value of a codec capability metadata. + * + * @param codec_cap The codec capability to set data for. + * @param val The assisted listening stream value to set. + * + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory + */ +int bt_audio_codec_cap_meta_set_assisted_listening_stream( + struct bt_audio_codec_cap *codec_cap, enum bt_audio_assisted_listening_stream val); + +/** + * @brief Extract broadcast name + * + * See @ref BT_AUDIO_METADATA_TYPE_BROADCAST_NAME for more information about this value. + * + * @param[in] codec_cap The codec data to search in. + * @param[out] broadcast_name Pointer to the UTF-8 formatted broadcast name. + * + * @retval length The length of the @p broadcast_name (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found + */ +int bt_audio_codec_cap_meta_get_broadcast_name(const struct bt_audio_codec_cap *codec_cap, + const uint8_t **broadcast_name); + +/** + * @brief Set the broadcast name of a codec capability metadata. + * + * @param codec_cap The codec capability to set data for. + * @param broadcast_name The broadcast name to set. + * @param broadcast_name_len The length of @p broadcast_name. + * + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory + */ +int bt_audio_codec_cap_meta_set_broadcast_name(struct bt_audio_codec_cap *codec_cap, + const uint8_t *broadcast_name, + size_t broadcast_name_len); /** * @brief Extract extended metadata * @@ -2122,9 +2026,9 @@ int bt_audio_codec_cap_meta_set_bcast_audio_immediate_rend_flag( * @param[in] codec_cap The codec data to search in. * @param[out] extended_meta Pointer to the extended metadata. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p extended_meta (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_meta_get_extended(const struct bt_audio_codec_cap *codec_cap, const uint8_t **extended_meta); @@ -2136,9 +2040,9 @@ int bt_audio_codec_cap_meta_get_extended(const struct bt_audio_codec_cap *codec_ * @param extended_meta The extended metadata to set. * @param extended_meta_len The length of @p extended_meta. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_extended(struct bt_audio_codec_cap *codec_cap, const uint8_t *extended_meta, size_t extended_meta_len); @@ -2151,9 +2055,9 @@ int bt_audio_codec_cap_meta_set_extended(struct bt_audio_codec_cap *codec_cap, * @param[in] codec_cap The codec data to search in. * @param[out] vendor_meta Pointer to the vendor specific metadata. * - * @retval The length of the @p ccid_list (may be 0) - * @retval -EINVAL if arguments are invalid - * @retval -ENODATA if not found + * @retval len The length of the @p vendor_meta (may be 0) + * @retval -EINVAL Arguments are invalid + * @retval -ENODATA Data not found */ int bt_audio_codec_cap_meta_get_vendor(const struct bt_audio_codec_cap *codec_cap, const uint8_t **vendor_meta); @@ -2165,15 +2069,312 @@ int bt_audio_codec_cap_meta_get_vendor(const struct bt_audio_codec_cap *codec_ca * @param vendor_meta The vendor specific metadata to set. * @param vendor_meta_len The length of @p vendor_meta. * - * @retval The data_len of @p codec_cap on success - * @retval -EINVAL if arguments are invalid - * @retval -ENOMEM if the new value could not set or added due to memory + * @retval data_len The @p codec_cap.data_len on success + * @retval -EINVAL Arguments are invalid + * @retval -ENOMEM The new value could not be set or added due to lack of memory */ int bt_audio_codec_cap_meta_set_vendor(struct bt_audio_codec_cap *codec_cap, const uint8_t *vendor_meta, size_t vendor_meta_len); /** @} */ /* End of bt_audio_codec_cap */ +/** + * @brief Assigned numbers to string API + * @defgroup bt_audio_to_str Assigned numbers to string API + * + * Functions to return string representation of Bluetooth Audio assigned number values. + * + * @{ + */ + +/** + * @brief Returns a string representation of a specific @ref bt_audio_context bit + * + * If @p context contains multiple bits, it will return "Unknown context" + * + * @param context A single context bit + * + * @return String representation of the supplied bit + */ +static inline char *bt_audio_context_bit_to_str(enum bt_audio_context context) +{ + switch (context) { + case BT_AUDIO_CONTEXT_TYPE_PROHIBITED: + return "Prohibited"; + case BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED: + return "Unspecified"; + case BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL: + return "Conversational"; + case BT_AUDIO_CONTEXT_TYPE_MEDIA: + return "Media"; + case BT_AUDIO_CONTEXT_TYPE_GAME: + return "Game"; + case BT_AUDIO_CONTEXT_TYPE_INSTRUCTIONAL: + return "Instructional"; + case BT_AUDIO_CONTEXT_TYPE_VOICE_ASSISTANTS: + return "Voice assistant"; + case BT_AUDIO_CONTEXT_TYPE_LIVE: + return "Live"; + case BT_AUDIO_CONTEXT_TYPE_SOUND_EFFECTS: + return "Sound effects"; + case BT_AUDIO_CONTEXT_TYPE_NOTIFICATIONS: + return "Notifications"; + case BT_AUDIO_CONTEXT_TYPE_RINGTONE: + return "Ringtone"; + case BT_AUDIO_CONTEXT_TYPE_ALERTS: + return "Alerts"; + case BT_AUDIO_CONTEXT_TYPE_EMERGENCY_ALARM: + return "Emergency alarm"; + default: + return "Unknown context"; + } +} + +/** + * @brief Returns a string representation of a @ref bt_audio_parental_rating value + * + * @param parental_rating The parental rating value + * + * @return String representation of the supplied parental rating value + */ +static inline char *bt_audio_parental_rating_to_str(enum bt_audio_parental_rating parental_rating) +{ + switch (parental_rating) { + case BT_AUDIO_PARENTAL_RATING_NO_RATING: + return "No rating"; + case BT_AUDIO_PARENTAL_RATING_AGE_ANY: + return "Any"; + case BT_AUDIO_PARENTAL_RATING_AGE_5_OR_ABOVE: + return "Age 5 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_6_OR_ABOVE: + return "Age 6 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_7_OR_ABOVE: + return "Age 7 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_8_OR_ABOVE: + return "Age 8 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_9_OR_ABOVE: + return "Age 9 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_10_OR_ABOVE: + return "Age 10 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_11_OR_ABOVE: + return "Age 11 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_12_OR_ABOVE: + return "Age 12 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_13_OR_ABOVE: + return "Age 13 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_14_OR_ABOVE: + return "Age 14 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_15_OR_ABOVE: + return "Age 15 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_16_OR_ABOVE: + return "Age 16 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_17_OR_ABOVE: + return "Age 17 or above"; + case BT_AUDIO_PARENTAL_RATING_AGE_18_OR_ABOVE: + return "Age 18 or above"; + default: + return "Unknown rating"; + } +} + +/** + * @brief Returns a string representation of a @ref bt_audio_active_state value + * + * @param state The active state value + * + * @return String representation of the supplied active state value + */ +static inline char *bt_audio_active_state_to_str(enum bt_audio_active_state state) +{ + switch (state) { + case BT_AUDIO_ACTIVE_STATE_DISABLED: + return "Disabled"; + case BT_AUDIO_ACTIVE_STATE_ENABLED: + return "Enabled"; + default: + return "Unknown active state"; + } +} + +/** + * @brief Returns a string representation of a specific @ref bt_audio_codec_cap_freq bit + * + * If @p freq contains multiple bits, it will return "Unknown supported frequency" + * + * @param freq A single frequency bit + * + * @return String representation of the supplied bit + */ +static inline char *bt_audio_codec_cap_freq_bit_to_str(enum bt_audio_codec_cap_freq freq) +{ + switch (freq) { + case BT_AUDIO_CODEC_CAP_FREQ_8KHZ: + return "8000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_11KHZ: + return "11025 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_16KHZ: + return "16000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_22KHZ: + return "22050 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_24KHZ: + return "24000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_32KHZ: + return "32000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_44KHZ: + return "44100 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_48KHZ: + return "48000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_88KHZ: + return "88200 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_96KHZ: + return "96000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_176KHZ: + return "176400 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_192KHZ: + return "192000 Hz"; + case BT_AUDIO_CODEC_CAP_FREQ_384KHZ: + return "384000 Hz"; + default: + return "Unknown supported frequency"; + } +} + +/** + * @brief Returns a string representation of a specific @ref bt_audio_codec_cap_frame_dur bit + * + * If @p frame_dur contains multiple bits, it will return "Unknown frame duration" + * + * @param frame_dur A single frame duration bit + * + * @return String representation of the supplied bit + */ +static inline char * +bt_audio_codec_cap_frame_dur_bit_to_str(enum bt_audio_codec_cap_frame_dur frame_dur) +{ + switch (frame_dur) { + case BT_AUDIO_CODEC_CAP_DURATION_7_5: + return "7.5 ms"; + case BT_AUDIO_CODEC_CAP_DURATION_10: + return "10 ms"; + case BT_AUDIO_CODEC_CAP_DURATION_PREFER_7_5: + return "7.5 ms preferred"; + case BT_AUDIO_CODEC_CAP_DURATION_PREFER_10: + return "10 ms preferred"; + default: + return "Unknown frame duration"; + } +} + +/** + * @brief Returns a string representation of a specific @ref bt_audio_codec_cap_chan_count bit + * + * If @p chan_count contains multiple bits, it will return "Unknown channel count" + * + * @param chan_count A single frame channel count bit + * + * @return String representation of the supplied bit + */ +static inline char * +bt_audio_codec_cap_chan_count_bit_to_str(enum bt_audio_codec_cap_chan_count chan_count) +{ + switch (chan_count) { + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_1: + return "1 channel"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_2: + return "2 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_3: + return "3 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_4: + return "4 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_5: + return "5 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_6: + return "6 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_7: + return "7 channels"; + case BT_AUDIO_CODEC_CAP_CHAN_COUNT_8: + return "8 channels"; + default: + return "Unknown channel count"; + } +} + +/** + * @brief Returns a string representation of a specific @ref bt_audio_location bit + * + * If @p location contains multiple bits, it will return "Unknown location" + * + * @param location A single location bit + * + * @return String representation of the supplied bit + */ +static inline char *bt_audio_location_bit_to_str(enum bt_audio_location location) +{ + switch (location) { + case BT_AUDIO_LOCATION_MONO_AUDIO: + return "Mono"; + case BT_AUDIO_LOCATION_FRONT_LEFT: + return "Front left"; + case BT_AUDIO_LOCATION_FRONT_RIGHT: + return "Front right"; + case BT_AUDIO_LOCATION_FRONT_CENTER: + return "Front center"; + case BT_AUDIO_LOCATION_LOW_FREQ_EFFECTS_1: + return "Low frequency effects 1"; + case BT_AUDIO_LOCATION_BACK_LEFT: + return "Back left"; + case BT_AUDIO_LOCATION_BACK_RIGHT: + return "Back right"; + case BT_AUDIO_LOCATION_FRONT_LEFT_OF_CENTER: + return "Front left of center"; + case BT_AUDIO_LOCATION_FRONT_RIGHT_OF_CENTER: + return "Front right of center"; + case BT_AUDIO_LOCATION_BACK_CENTER: + return "Back center"; + case BT_AUDIO_LOCATION_LOW_FREQ_EFFECTS_2: + return "Low frequency effects 2"; + case BT_AUDIO_LOCATION_SIDE_LEFT: + return "Side left"; + case BT_AUDIO_LOCATION_SIDE_RIGHT: + return "Side right"; + case BT_AUDIO_LOCATION_TOP_FRONT_LEFT: + return "Top front left"; + case BT_AUDIO_LOCATION_TOP_FRONT_RIGHT: + return "Top front right"; + case BT_AUDIO_LOCATION_TOP_FRONT_CENTER: + return "Top front center"; + case BT_AUDIO_LOCATION_TOP_CENTER: + return "Top center"; + case BT_AUDIO_LOCATION_TOP_BACK_LEFT: + return "Top back left"; + case BT_AUDIO_LOCATION_TOP_BACK_RIGHT: + return "Top back right"; + case BT_AUDIO_LOCATION_TOP_SIDE_LEFT: + return "Top side left"; + case BT_AUDIO_LOCATION_TOP_SIDE_RIGHT: + return "Top side right"; + case BT_AUDIO_LOCATION_TOP_BACK_CENTER: + return "Top back center"; + case BT_AUDIO_LOCATION_BOTTOM_FRONT_CENTER: + return "Bottom front center"; + case BT_AUDIO_LOCATION_BOTTOM_FRONT_LEFT: + return "Bottom front left"; + case BT_AUDIO_LOCATION_BOTTOM_FRONT_RIGHT: + return "Bottom front right"; + case BT_AUDIO_LOCATION_FRONT_LEFT_WIDE: + return "Front left wide"; + case BT_AUDIO_LOCATION_FRONT_RIGHT_WIDE: + return "Front right wde"; + case BT_AUDIO_LOCATION_LEFT_SURROUND: + return "Left surround"; + case BT_AUDIO_LOCATION_RIGHT_SURROUND: + return "Right surround"; + default: + return "Unknown location"; + } +} + +/** @} */ /* End of bt_audio_to_str */ #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap.h index 1d61c07a..17e53ca6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap.h @@ -33,13 +33,289 @@ #include #include #include -#include +#include #include +#include #ifdef __cplusplus extern "C" { #endif +#if defined(CONFIG_BT_BAP_BASS_MAX_SUBGROUPS) +#define BT_BAP_BASS_MAX_SUBGROUPS CONFIG_BT_BAP_BASS_MAX_SUBGROUPS +#else +#define BT_BAP_BASS_MAX_SUBGROUPS 0 +#endif /* CONFIG_BT_BAP_BASS_MAX_SUBGROUPS*/ + +/** An invalid Broadcast ID */ +#define BT_BAP_INVALID_BROADCAST_ID 0xFFFFFFFFU + +/** + * @brief Check if a BAP BASS BIS_Sync bitfield is valid + * + * Valid options are eiter a bitmask of valid BIS indices, including none (0x00000000) + * or @ref BT_BAP_BIS_SYNC_NO_PREF (0xFFFFFFFF). + * + * @param _bis_bitfield BIS_Sync bitfield (uint32) + */ +#define BT_BAP_BASS_VALID_BIT_BITFIELD(_bis_bitfield) \ + ((_bis_bitfield) == 0U || (_bis_bitfield) == BT_BAP_BIS_SYNC_NO_PREF || \ + BT_ISO_VALID_BIS_BITFIELD(_bis_bitfield)) + +/** + * @brief Helper to declare elements of bt_bap_qos_cfg + * + * @param _interval SDU interval (usec) + * @param _framing Framing + * @param _phy Target PHY + * @param _sdu Maximum SDU Size + * @param _rtn Retransmission number + * @param _latency Maximum Transport Latency (msec) + * @param _pd Presentation Delay (usec) + */ +#define BT_BAP_QOS_CFG(_interval, _framing, _phy, _sdu, _rtn, _latency, _pd) \ + ((struct bt_bap_qos_cfg){ \ + .interval = _interval, \ + .framing = _framing, \ + .phy = _phy, \ + .sdu = _sdu, \ + .rtn = _rtn, \ + IF_ENABLED(UTIL_OR(IS_ENABLED(CONFIG_BT_BAP_BROADCAST_SOURCE), \ + IS_ENABLED(CONFIG_BT_BAP_UNICAST)), \ + (.latency = _latency,)) \ + .pd = _pd, \ + }) + +/** @brief QoS Framing */ +enum bt_bap_qos_cfg_framing { + /** Packets may be framed or unframed */ + BT_BAP_QOS_CFG_FRAMING_UNFRAMED = 0x00, + /** Packets are always framed */ + BT_BAP_QOS_CFG_FRAMING_FRAMED = 0x01, +}; + +/** @brief QoS Preferred PHY */ +enum { + /** LE 1M PHY */ + BT_BAP_QOS_CFG_1M = BIT(0), + /** LE 2M PHY */ + BT_BAP_QOS_CFG_2M = BIT(1), + /** LE Coded PHY */ + BT_BAP_QOS_CFG_CODED = BIT(2), +}; + +/** + * @brief Helper to declare Input Unframed bt_bap_qos_cfg + * + * @param _interval SDU interval (usec) + * @param _sdu Maximum SDU Size + * @param _rtn Retransmission number + * @param _latency Maximum Transport Latency (msec) + * @param _pd Presentation Delay (usec) + */ +#define BT_BAP_QOS_CFG_UNFRAMED(_interval, _sdu, _rtn, _latency, _pd) \ + BT_BAP_QOS_CFG(_interval, BT_BAP_QOS_CFG_FRAMING_UNFRAMED, BT_BAP_QOS_CFG_2M, _sdu, _rtn, \ + _latency, _pd) + +/** + * @brief Helper to declare Input Framed bt_bap_qos_cfg + * + * @param _interval SDU interval (usec) + * @param _sdu Maximum SDU Size + * @param _rtn Retransmission number + * @param _latency Maximum Transport Latency (msec) + * @param _pd Presentation Delay (usec) + */ +#define BT_BAP_QOS_CFG_FRAMED(_interval, _sdu, _rtn, _latency, _pd) \ + BT_BAP_QOS_CFG(_interval, BT_BAP_QOS_CFG_FRAMING_FRAMED, BT_BAP_QOS_CFG_2M, _sdu, _rtn, \ + _latency, _pd) + +/** @brief QoS configuration structure. */ +struct bt_bap_qos_cfg { + /** + * @brief Presentation Delay in microseconds + * + * This value can be changed up and until bt_bap_stream_qos() has been called. + * Once a stream has been QoS configured, modifying this field does not modify the value. + * It is however possible to modify this field and call bt_bap_stream_qos() again to update + * the value, assuming that the stream is in the correct state. + * + * Value range 0 to @ref BT_AUDIO_PD_MAX. + */ + uint32_t pd; + + /** + * @brief Connected Isochronous Group (CIG) parameters + * + * The fields in this struct affect the value sent to the controller via HCI + * when creating the CIG. Once the group has been created with + * bt_bap_unicast_group_create(), modifying these fields will not affect the group. + */ + struct { + /** QoS Framing */ + enum bt_bap_qos_cfg_framing framing; + + /** + * @brief PHY + * + * Allowed values are @ref BT_BAP_QOS_CFG_1M, @ref BT_BAP_QOS_CFG_2M and + * @ref BT_BAP_QOS_CFG_CODED. + */ + uint8_t phy; + + /** + * @brief Retransmission Number + * + * This a recommendation to the controller, and the actual retransmission number + * may be different than this. + */ + uint8_t rtn; + + /** + * @brief Maximum SDU size + * + * Value range @ref BT_ISO_MIN_SDU to @ref BT_ISO_MAX_SDU. + */ + uint16_t sdu; + +#if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) || defined(CONFIG_BT_BAP_UNICAST) || \ + defined(__DOXYGEN__) + /** + * @brief Maximum Transport Latency + * + * Not used for the @kconfig{CONFIG_BT_BAP_BROADCAST_SINK} role. + */ + uint16_t latency; +#endif /* CONFIG_BT_BAP_BROADCAST_SOURCE || CONFIG_BT_BAP_UNICAST */ + + /** + * @brief SDU Interval + * + * Value range @ref BT_ISO_SDU_INTERVAL_MIN to @ref BT_ISO_SDU_INTERVAL_MAX + */ + uint32_t interval; + +#if defined(CONFIG_BT_ISO_TEST_PARAMS) || defined(__DOXYGEN__) + /** + * @brief Maximum PDU size + * + * Maximum size, in octets, of the payload from link layer to link layer. + * + * Value range @ref BT_ISO_CONNECTED_PDU_MIN to @ref BT_ISO_PDU_MAX for + * connected ISO. + * + * Value range @ref BT_ISO_BROADCAST_PDU_MIN to @ref BT_ISO_PDU_MAX for + * broadcast ISO. + */ + uint16_t max_pdu; + + /** + * @brief Burst number + * + * Value range @ref BT_ISO_BN_MIN to @ref BT_ISO_BN_MAX. + */ + uint8_t burst_number; + + /** + * @brief Number of subevents + * + * Maximum number of subevents in each CIS or BIS event. + * + * Value range @ref BT_ISO_NSE_MIN to @ref BT_ISO_NSE_MAX. + */ + uint8_t num_subevents; +#endif /* CONFIG_BT_ISO_TEST_PARAMS */ + }; +}; + +/** + * @brief Helper to declare elements of @ref bt_bap_qos_cfg_pref + * + * @param _unframed_supported Unframed PDUs supported + * @param _phy Preferred Target PHY + * @param _rtn Preferred Retransmission number + * @param _latency Preferred Maximum Transport Latency (msec) + * @param _pd_min Minimum Presentation Delay (usec) + * @param _pd_max Maximum Presentation Delay (usec) + * @param _pref_pd_min Preferred Minimum Presentation Delay (usec) + * @param _pref_pd_max Preferred Maximum Presentation Delay (usec) + */ +#define BT_BAP_QOS_CFG_PREF(_unframed_supported, _phy, _rtn, _latency, _pd_min, _pd_max, \ + _pref_pd_min, _pref_pd_max) \ + { \ + .unframed_supported = _unframed_supported, .phy = _phy, .rtn = _rtn, \ + .latency = _latency, .pd_min = _pd_min, .pd_max = _pd_max, \ + .pref_pd_min = _pref_pd_min, .pref_pd_max = _pref_pd_max, \ + } + +/** @brief Audio Stream Quality of Service Preference structure. */ +struct bt_bap_qos_cfg_pref { + /** + * @brief Unframed PDUs supported + * + * Unlike the other fields, this is not a preference but whether + * the codec supports unframed ISOAL PDUs. + */ + bool unframed_supported; + + /** + * @brief Preferred PHY bitfield + * + * Bitfield consisting of one or more of @ref BT_GAP_LE_PHY_1M, @ref BT_GAP_LE_PHY_2M and + * @ref BT_GAP_LE_PHY_CODED. + */ + uint8_t phy; + + /** + * @brief Preferred Retransmission Number + * + * @ref BT_AUDIO_RTN_PREF_NONE indicates no preference. + */ + uint8_t rtn; + + /** + * Preferred Transport Latency + * + * Value range @ref BT_ISO_LATENCY_MIN to @ref BT_ISO_LATENCY_MAX + */ + uint16_t latency; + + /** + * @brief Minimum Presentation Delay in microseconds + * + * Unlike the other fields, this is not a preference but a minimum requirement. + * + * Value range 0 to @ref BT_AUDIO_PD_MAX + */ + uint32_t pd_min; + + /** + * @brief Maximum Presentation Delay in microseconds + * + * Unlike the other fields, this is not a preference but a maximum requirement. + * + * Value range @ref bt_bap_qos_cfg_pref.pd_min to @ref BT_AUDIO_PD_MAX + */ + uint32_t pd_max; + + /** + * @brief Preferred minimum Presentation Delay in microseconds + * + * Value range @ref bt_bap_qos_cfg_pref.pd_min to @ref bt_bap_qos_cfg_pref.pd_max, or + * @ref BT_AUDIO_PD_PREF_NONE to indicate no preference. + */ + uint32_t pref_pd_min; + + /** + * @brief Preferred maximum Presentation Delay in microseconds + * + * Value range @ref bt_bap_qos_cfg_pref.pd_min to @ref bt_bap_qos_cfg_pref.pd_max, + * and higher than or equal to @ref bt_bap_qos_cfg_pref.pref_pd_min, or + * @ref BT_AUDIO_PD_PREF_NONE to indicate no preference. + */ + uint32_t pref_pd_max; +}; + /** Periodic advertising state reported by the Scan Delegator */ enum bt_bap_pa_state { /** The periodic advertising has not been synchronized */ @@ -91,7 +367,9 @@ enum bt_bap_bass_att_err { * Value indicating that the Broadcast Assistant has no preference to which BIS * the Scan Delegator syncs to */ -#define BT_BAP_BIS_SYNC_NO_PREF 0xFFFFFFFF +#define BT_BAP_BIS_SYNC_NO_PREF 0xFFFFFFFF +/** BIS sync value indicating that the BIG sync has failed for any reason */ +#define BT_BAP_BIS_SYNC_FAILED 0xFFFFFFFF /** Endpoint states */ enum bt_bap_ep_state { @@ -300,19 +578,23 @@ struct bt_bap_scan_delegator_recv_state { * * Only valid if encrypt_state is @ref BT_BAP_BIG_ENC_STATE_BCODE_REQ */ - uint8_t bad_code[BT_AUDIO_BROADCAST_CODE_SIZE]; + uint8_t bad_code[BT_ISO_BROADCAST_CODE_SIZE]; /** Number of subgroups */ uint8_t num_subgroups; - /** Subgroup specific information */ - struct bt_bap_bass_subgroup subgroups[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]; + /** Subgroup specific information + * + * If the @ref bt_bap_bass_subgroup.bis_sync value is @ref BT_BAP_BIS_SYNC_FAILED then it + * indicates that the BIG sync failed. + */ + struct bt_bap_bass_subgroup subgroups[BT_BAP_BASS_MAX_SUBGROUPS]; }; /** * @brief Struct to hold the Basic Audio Profile Scan Delegator callbacks * - * These can be registered for usage with bt_bap_scan_delegator_register_cb(). + * These can be registered for usage with bt_bap_scan_delegator_register(). */ struct bt_bap_scan_delegator_cb { /** @@ -376,7 +658,7 @@ struct bt_bap_scan_delegator_cb { */ void (*broadcast_code)(struct bt_conn *conn, const struct bt_bap_scan_delegator_recv_state *recv_state, - const uint8_t broadcast_code[BT_AUDIO_BROADCAST_CODE_SIZE]); + const uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]); /** * @brief Broadcast Isochronous Stream synchronize request * @@ -400,7 +682,17 @@ struct bt_bap_scan_delegator_cb { */ int (*bis_sync_req)(struct bt_conn *conn, const struct bt_bap_scan_delegator_recv_state *recv_state, - const uint32_t bis_sync_req[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]); + const uint32_t bis_sync_req[BT_BAP_BASS_MAX_SUBGROUPS]); + /** + * @brief Broadcast Assistant scanning state callback + * + * Callback triggered when a Broadcast Assistant notifies the Scan Delegator about the + * assistants scanning state. + * + * @param conn Pointer to the connection that initiated the scan. + * @param is_scanning true if scanning started, false if scanning stopped. + */ + void (*scanning_state)(struct bt_conn *conn, bool is_scanning); }; /** Structure holding information of audio stream endpoint */ @@ -429,7 +721,7 @@ struct bt_bap_ep_info { struct bt_bap_ep *paired_ep; /** Pointer to the preferred QoS settings associated with the endpoint */ - const struct bt_audio_codec_qos_pref *qos_pref; + const struct bt_bap_qos_cfg_pref *qos_pref; }; /** @@ -462,7 +754,7 @@ struct bt_bap_stream { struct bt_audio_codec_cfg *codec_cfg; /** QoS Configuration */ - struct bt_audio_codec_qos *qos; + struct bt_bap_qos_cfg *qos; /** Audio stream operations */ struct bt_bap_stream_ops *ops; @@ -502,8 +794,7 @@ struct bt_bap_stream_ops { * @param stream Stream object that has been configured. * @param pref Remote QoS preferences. */ - void (*configured)(struct bt_bap_stream *stream, - const struct bt_audio_codec_qos_pref *pref); + void (*configured)(struct bt_bap_stream *stream, const struct bt_bap_qos_cfg_pref *pref); /** * @brief Stream QoS set callback @@ -635,6 +926,22 @@ struct bt_bap_stream_ops { void (*disconnected)(struct bt_bap_stream *stream, uint8_t reason); }; +/** Structure for registering Unicast Server */ +struct bt_bap_unicast_server_register_param { + /** + * @brief Sink Count to register. + * + * Should be in range 0 to @kconfig{CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT} + */ + uint8_t snk_cnt; + + /** @brief Source Count to register. + * + * Should be in range 0 to @kconfig{CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT} + */ + uint8_t src_cnt; +}; + /** * @brief Register Audio callbacks for a stream. * @@ -793,6 +1100,16 @@ int bt_bap_stream_start(struct bt_bap_stream *stream); * * @param stream Stream object * + * @retval 0 Success + * @retval -EINVAL The @p stream does not have an endpoint or a connection, of the stream's + * connection's role is not @p BT_HCI_ROLE_CENTRAL + * @retval -EBADMSG The state of the @p stream endpoint is not @ref BT_BAP_EP_STATE_DISABLING + * @retval -EALREADY The CIS state of the @p is not in a connected state, and thus is already + * stopping + * @retval -EBUSY The @p stream is busy with another operation + * @retval -ENOTCONN The @p stream ACL connection is not connected + * @retval -ENOMEM No memory to send request + * @retval -ENOEXEC The request was rejected by GATT * @return 0 in case of success or negative value in case of error. */ int bt_bap_stream_stop(struct bt_bap_stream *stream); @@ -895,7 +1212,7 @@ struct bt_bap_unicast_server_cb { */ int (*config)(struct bt_conn *conn, const struct bt_bap_ep *ep, enum bt_audio_dir dir, const struct bt_audio_codec_cfg *codec_cfg, struct bt_bap_stream **stream, - struct bt_audio_codec_qos_pref *const pref, struct bt_bap_ascs_rsp *rsp); + struct bt_bap_qos_cfg_pref *const pref, struct bt_bap_ascs_rsp *rsp); /** * @brief Stream reconfig request callback @@ -915,7 +1232,7 @@ struct bt_bap_unicast_server_cb { */ int (*reconfig)(struct bt_bap_stream *stream, enum bt_audio_dir dir, const struct bt_audio_codec_cfg *codec_cfg, - struct bt_audio_codec_qos_pref *const pref, struct bt_bap_ascs_rsp *rsp); + struct bt_bap_qos_cfg_pref *const pref, struct bt_bap_ascs_rsp *rsp); /** * @brief Stream QoS request callback @@ -930,7 +1247,7 @@ struct bt_bap_unicast_server_cb { * * @return 0 in case of success or negative value in case of error. */ - int (*qos)(struct bt_bap_stream *stream, const struct bt_audio_codec_qos *qos, + int (*qos)(struct bt_bap_stream *stream, const struct bt_bap_qos_cfg *qos, struct bt_bap_ascs_rsp *rsp); /** @@ -1019,11 +1336,41 @@ struct bt_bap_unicast_server_cb { int (*release)(struct bt_bap_stream *stream, struct bt_bap_ascs_rsp *rsp); }; +/** + * @brief Register the Unicast Server. + * + * Register the Unicast Server. Only a single Unicast Server can be registered at any one time. + * This will register ASCS in the GATT database. + * + * @param param Registration parameters for ascs. + * + * @return 0 in case of success, negative error code otherwise. + */ +int bt_bap_unicast_server_register(const struct bt_bap_unicast_server_register_param *param); + +/** + * @brief Unregister the Unicast Server. + * + * Unregister the Unicast Server. + * This will unregister ASCS in the GATT database. + * Before calling this function, any callbacks registered through + * bt_bap_unicast_server_register_cb() needs to be unregistered with + * bt_bap_unicast_server_unregister_cb(). + * + * Calling this function will issue an release operation on any ASE + * in a non-idle state. + * + * @return 0 in case of success, negative error code otherwise. + */ +int bt_bap_unicast_server_unregister(void); + /** * @brief Register unicast server callbacks. * * Only one callback structure can be registered, and attempting to * registering more than one will result in an error. + * Prior to calling this function the Unicast Server needs to be + * registered with bt_bap_unicast_server_register(). * * @param cb Unicast server callback structure. * @@ -1037,6 +1384,9 @@ int bt_bap_unicast_server_register_cb(const struct bt_bap_unicast_server_cb *cb) * May only unregister a callback structure that has previously been * registered by bt_bap_unicast_server_register_cb(). * + * Calling this function will issue an release operation on any ASE + * in a non-idle state. + * * @param cb Unicast server callback structure. * * @return 0 in case of success or negative value in case of error. @@ -1073,7 +1423,7 @@ void bt_bap_unicast_server_foreach_ep(struct bt_conn *conn, bt_bap_ep_func_t fun */ int bt_bap_unicast_server_config_ase(struct bt_conn *conn, struct bt_bap_stream *stream, struct bt_audio_codec_cfg *codec_cfg, - const struct bt_audio_codec_qos_pref *qos_pref); + const struct bt_bap_qos_cfg_pref *qos_pref); /** @} */ /* End of group bt_bap_unicast_server */ @@ -1089,7 +1439,7 @@ struct bt_bap_unicast_group_stream_param { struct bt_bap_stream *stream; /** The QoS settings for the stream object. */ - struct bt_audio_codec_qos *qos; + struct bt_bap_qos_cfg *qos; }; /** @@ -1156,10 +1506,12 @@ struct bt_bap_unicast_group_param { }; /** - * @brief Create audio unicast group. + * @brief Create unicast group. * - * Create a new audio unicast group with one or more audio streams as a unicast client. Streams in - * a unicast group shall share the same interval, framing and latency (see @ref bt_audio_codec_qos). + * Create a new audio unicast group with one or more audio streams as a unicast client. + * All streams shall share the same framing. + * All streams in the same direction shall share the same interval and latency (see + * @ref bt_bap_qos_cfg). * * @param[in] param The unicast group create parameters. * @param[out] unicast_group Pointer to the unicast group created. @@ -1169,6 +1521,24 @@ struct bt_bap_unicast_group_param { int bt_bap_unicast_group_create(struct bt_bap_unicast_group_param *param, struct bt_bap_unicast_group **unicast_group); +/** + * @brief Reconfigure unicast group. + * + * Reconfigure a unicast group with one or more audio streams as a unicast client. + * All streams shall share the same framing. + * All streams in the same direction shall share the same interval and latency (see + * @ref bt_bap_qos_cfg). + * All streams in @p param shall already belong to @p unicast_group. + * Use bt_bap_unicast_group_add_streams() to add additional streams. + * + * @param unicast_group Pointer to the unicast group created. + * @param param The unicast group reconfigure parameters. + * + * @return Zero on success or (negative) error code otherwise. + */ +int bt_bap_unicast_group_reconfig(struct bt_bap_unicast_group *unicast_group, + const struct bt_bap_unicast_group_param *param); + /** * @brief Add streams to a unicast group as a unicast client * @@ -1387,6 +1757,11 @@ struct bt_bap_unicast_client_cb { * If discovery procedure has complete both @p codec and @p ep are set to NULL. */ void (*discover)(struct bt_conn *conn, int err, enum bt_audio_dir dir); + + /** @cond INTERNAL_HIDDEN */ + /** Internally used field for list handling */ + sys_snode_t _node; + /** @endcond */ }; /** @@ -1397,9 +1772,11 @@ struct bt_bap_unicast_client_cb { * * @param cb Unicast client callback structure. * - * @return 0 in case of success or negative value in case of error. + * @retval 0 Success + * @retval -EINVAL @p cb is NULL. + * @retval -EEXIST @p cb is already registered. */ -int bt_bap_unicast_client_register_cb(const struct bt_bap_unicast_client_cb *cb); +int bt_bap_unicast_client_register_cb(struct bt_bap_unicast_client_cb *cb); /** * @brief Discover remote capabilities and endpoints @@ -1624,6 +2001,53 @@ int bt_bap_base_subgroup_bis_codec_to_codec_cfg(const struct bt_bap_base_subgrou * @{ */ +/** + * @brief Struct to hold the Broadcast Source callbacks + * + * These can be registered for usage with bt_bap_broadcast_source_register_cb(). + */ +struct bt_bap_broadcast_source_cb { + /** + * @brief The Broadcast Source has started and all of the streams are ready for audio data + * + * @param source The started Broadcast Source + */ + void (*started)(struct bt_bap_broadcast_source *source); + + /** + * @brief The Broadcast Source has stopped and none of the streams are ready for audio data + * + * @param source The stopped Broadcast Source + * @param reason The reason why the Broadcast Source stopped (see the BT_HCI_ERR_* values) + */ + void (*stopped)(struct bt_bap_broadcast_source *source, uint8_t reason); + + /** @internal Internally used field for list handling */ + sys_snode_t _node; +}; + +/** + * @brief Registers callbacks for Broadcast Sources + * + * @param cb Pointer to the callback structure. + * + * @retval 0 on success + * @retval -EINVAL if @p cb is NULL + * @retval -EEXIST if @p cb is already registered + */ +int bt_bap_broadcast_source_register_cb(struct bt_bap_broadcast_source_cb *cb); + +/** + * @brief Unregisters callbacks for Broadcast Sources + * + * @param cb Pointer to the callback structure. + * + * @retval 0 on success + * @retval -EINVAL if @p cb is NULL + * @retval -ENOENT if @p cb is not registered + */ +int bt_bap_broadcast_source_unregister_cb(struct bt_bap_broadcast_source_cb *cb); + /** Broadcast Source stream parameters */ struct bt_bap_broadcast_source_stream_param { /** Audio stream */ @@ -1663,7 +2087,7 @@ struct bt_bap_broadcast_source_param { struct bt_bap_broadcast_source_subgroup_param *params; /** Quality of Service configuration. */ - struct bt_audio_codec_qos *qos; + struct bt_bap_qos_cfg *qos; /** * @brief Broadcast Source packing mode. @@ -1687,7 +2111,7 @@ struct bt_bap_broadcast_source_param { * The string "Broadcast Code" shall be * [42 72 6F 61 64 63 61 73 74 20 43 6F 64 65 00 00] */ - uint8_t broadcast_code[BT_AUDIO_BROADCAST_CODE_SIZE]; + uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]; #if defined(CONFIG_BT_ISO_TEST_PARAMS) || defined(__DOXYGEN__) /** @@ -1813,22 +2237,6 @@ int bt_bap_broadcast_source_stop(struct bt_bap_broadcast_source *source); */ int bt_bap_broadcast_source_delete(struct bt_bap_broadcast_source *source); -/** - * @brief Get the broadcast ID of a broadcast source - * - * This will return the 3-octet broadcast ID that should be advertised in the - * extended advertising data with @ref BT_UUID_BROADCAST_AUDIO_VAL as @ref BT_DATA_SVC_DATA16. - * - * See table 3.14 in the Basic Audio Profile v1.0.1 for the structure. - * - * @param[in] source Pointer to the broadcast source. - * @param[out] broadcast_id Pointer to the 3-octet broadcast ID. - * - * @return Zero on success or (negative) error code otherwise. - */ -int bt_bap_broadcast_source_get_id(struct bt_bap_broadcast_source *source, - uint32_t *const broadcast_id); - /** * @brief Get the Broadcast Audio Stream Endpoint of a broadcast source * @@ -1884,6 +2292,22 @@ struct bt_bap_broadcast_sink_cb { */ void (*syncable)(struct bt_bap_broadcast_sink *sink, const struct bt_iso_biginfo *biginfo); + /** + * @brief The Broadcast Sink has started and audio data may be received from all of the + * streams + * + * @param sink The started Broadcast Sink + */ + void (*started)(struct bt_bap_broadcast_sink *sink); + + /** + * @brief The Broadcast Sink has stopped and none of the streams will receive audio data + * + * @param sink The stopped Broadcast Sink + * @param reason The reason why the Broadcast Sink stopped (see the BT_HCI_ERR_* values) + */ + void (*stopped)(struct bt_bap_broadcast_sink *sink, uint8_t reason); + /** @internal Internally used list node */ sys_snode_t _node; }; @@ -1894,11 +2318,12 @@ struct bt_bap_broadcast_sink_cb { * It is possible to register multiple struct of callbacks, but a single struct can only be * registered once. * Registering the same callback multiple times is undefined behavior and may break the stack. - * + * @param cb Broadcast sink callback structure. * - * @retval 0 in case of success + * @retval 0 on success * @retval -EINVAL if @p cb is NULL + * @retval -EALREADY if @p cb was already registered */ int bt_bap_broadcast_sink_register_cb(struct bt_bap_broadcast_sink_cb *cb); @@ -1943,7 +2368,8 @@ int bt_bap_broadcast_sink_create(struct bt_le_per_adv_sync *pa_sync, uint32_t br * @return 0 in case of success or negative value in case of error. */ int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t indexes_bitfield, - struct bt_bap_stream *streams[], const uint8_t broadcast_code[16]); + struct bt_bap_stream *streams[], + const uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]); /** * @brief Stop audio broadcast sink. @@ -1973,14 +2399,29 @@ int bt_bap_broadcast_sink_delete(struct bt_bap_broadcast_sink *sink); /** @} */ /* End of group bt_bap_broadcast_sink */ /** - * @brief Register the callbacks for the Basic Audio Profile Scan Delegator + * @brief Register the Basic Audio Profile Scan Delegator and BASS. + * + * Register the scan deligator and Broadcast Audio Scan Service (BASS) + * dynamically at runtime. * * Only one set of callbacks can be registered at any one time, and calling this function multiple * times will override any previously registered callbacks. * * @param cb Pointer to the callback struct + * + * @return 0 in case of success or negative value in case of error. */ -void bt_bap_scan_delegator_register_cb(struct bt_bap_scan_delegator_cb *cb); +int bt_bap_scan_delegator_register(struct bt_bap_scan_delegator_cb *cb); + +/** + * @brief unregister the Basic Audio Profile Scan Delegator and BASS. + * + * Unregister the scan deligator and Broadcast Audio Scan Service (BASS) + * dynamically at runtime. + * + * @return 0 in case of success or negative value in case of error. + */ +int bt_bap_scan_delegator_unregister(void); /** * @brief Set the periodic advertising sync state to syncing @@ -2006,14 +2447,16 @@ int bt_bap_scan_delegator_set_pa_state(uint8_t src_id, * subgroup. * @return int Error value. 0 on success, ERRNO on fail. */ -int bt_bap_scan_delegator_set_bis_sync_state( - uint8_t src_id, - uint32_t bis_synced[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]); +int bt_bap_scan_delegator_set_bis_sync_state(uint8_t src_id, + uint32_t bis_synced[BT_BAP_BASS_MAX_SUBGROUPS]); /** Parameters for bt_bap_scan_delegator_add_src() */ struct bt_bap_scan_delegator_add_src_param { - /** The periodic adverting sync */ - struct bt_le_per_adv_sync *pa_sync; + /** Periodic Advertiser Address */ + bt_addr_le_t addr; + + /** Advertiser SID */ + uint8_t sid; /** The broadcast isochronous group encryption state */ enum bt_bap_big_enc_state encrypt_state; @@ -2025,7 +2468,7 @@ struct bt_bap_scan_delegator_add_src_param { uint8_t num_subgroups; /** Subgroup specific information */ - struct bt_bap_bass_subgroup subgroups[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]; + struct bt_bap_bass_subgroup subgroups[BT_BAP_BASS_MAX_SUBGROUPS]; }; /** @@ -2063,7 +2506,7 @@ struct bt_bap_scan_delegator_mod_src_param { * If a subgroup's metadata_len is set to 0, the existing metadata * for the subgroup will remain unchanged */ - struct bt_bap_bass_subgroup subgroups[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]; + struct bt_bap_bass_subgroup subgroups[BT_BAP_BASS_MAX_SUBGROUPS]; }; /** @@ -2223,7 +2666,7 @@ struct bt_bap_broadcast_assistant_cb { void (*mod_src)(struct bt_conn *conn, int err); /** - * @brief Callback function for bt_bap_broadcast_assistant_broadcast_code(). + * @brief Callback function for bt_bap_broadcast_assistant_set_broadcast_code(). * * @param conn The connection to the peer device. * @param err Error value. 0 on success, GATT error on fail. @@ -2249,7 +2692,13 @@ struct bt_bap_broadcast_assistant_cb { * new connection, will delete all previous data. * * @param conn The connection - * @return int Error value. 0 on success, GATT error or ERRNO on fail. + * + * @retval 0 Success + * @retval -EINVAL @p conn is NULL + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected GATT error */ int bt_bap_broadcast_assistant_discover(struct bt_conn *conn); @@ -2268,7 +2717,14 @@ int bt_bap_broadcast_assistant_discover(struct bt_conn *conn); * Used to let the server know that we are scanning. * @param start_scan Start scanning if true. If false, the application should * enable scan itself. - * @return int Error value. 0 on success, GATT error or ERRNO on fail. + + * @retval 0 Success + * @retval -EINVAL @p conn is NULL of if @p conn has not done discovery + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -EAGAIN Bluetooth has not been enabled. + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_scan_start(struct bt_conn *conn, bool start_scan); @@ -2277,7 +2733,14 @@ int bt_bap_broadcast_assistant_scan_start(struct bt_conn *conn, * @brief Stop remote scanning for BISes for a server. * * @param conn Connection to the server. - * @return int Error value. 0 on success, GATT error or ERRNO on fail. + + * @retval 0 Success + * @retval -EINVAL @p conn is NULL of if @p conn has not done discovery + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -EAGAIN Bluetooth has not been enabled. + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_scan_stop(struct bt_conn *conn); @@ -2328,7 +2791,11 @@ struct bt_bap_broadcast_assistant_add_src_param { /** Number of subgroups */ uint8_t num_subgroups; - /** Pointer to array of subgroups */ + /** Pointer to array of subgroups + * + * The @ref bt_bap_bass_subgroup.bis_sync value can be set to BT_BAP_BIS_SYNC_NO_PREF to + * let the broadcast sink decide which BIS to synchronize to. + */ struct bt_bap_bass_subgroup *subgroups; }; @@ -2338,7 +2805,12 @@ struct bt_bap_broadcast_assistant_add_src_param { * @param conn Connection to the server. * @param param Parameter struct. * - * @return Error value. 0 on success, GATT error or ERRNO on fail. + * @retval 0 Success + * @retval -EINVAL @p conn is NULL or %p conn has not done discovery or if @p param is invalid + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_add_src( struct bt_conn *conn, const struct bt_bap_broadcast_assistant_add_src_param *param); @@ -2371,7 +2843,12 @@ struct bt_bap_broadcast_assistant_mod_src_param { * @param conn Connection to the server. * @param param Parameter struct. * - * @return Error value. 0 on success, GATT error or ERRNO on fail. + * @retval 0 Success + * @retval -EINVAL @p conn is NULL or %p conn has not done discovery or if @p param is invalid + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_mod_src( struct bt_conn *conn, const struct bt_bap_broadcast_assistant_mod_src_param *param); @@ -2383,11 +2860,16 @@ int bt_bap_broadcast_assistant_mod_src( * @param src_id Source ID of the receive state. * @param broadcast_code The broadcast code. * - * @return Error value. 0 on success, GATT error or ERRNO on fail. + * @retval 0 Success + * @retval -EINVAL @p conn is NULL or %p conn has not done discovery or @p src_id is invalid + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_set_broadcast_code( struct bt_conn *conn, uint8_t src_id, - const uint8_t broadcast_code[BT_AUDIO_BROADCAST_CODE_SIZE]); + const uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]); /** * @brief Remove a source from the server. @@ -2395,7 +2877,12 @@ int bt_bap_broadcast_assistant_set_broadcast_code( * @param conn Connection to the server. * @param src_id Source ID of the receive state. * - * @return Error value. 0 on success, GATT error or ERRNO on fail. + * @retval 0 Success + * @retval -EINVAL @p conn is NULL or %p conn has not done discovery or @p src_id is invalid + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_rem_src(struct bt_conn *conn, uint8_t src_id); @@ -2406,7 +2893,12 @@ int bt_bap_broadcast_assistant_rem_src(struct bt_conn *conn, uint8_t src_id); * @param idx The index of the receive start (0 up to the value from * bt_bap_broadcast_assistant_discover_cb) * - * @return Error value. 0 on success, GATT error or ERRNO on fail. + * @retval 0 Success + * @retval -EINVAL @p conn is NULL or %p conn has not done discovery or @p src_id is invalid + * @retval -EBUSY Another operation is already in progress for this @p conn + * @retval -ENOTCONN @p conn is not connected + * @retval -ENOMEM Could not allocated memory for the request + * @retval -ENOEXEC Unexpected scan or GATT error */ int bt_bap_broadcast_assistant_read_recv_state(struct bt_conn *conn, uint8_t idx); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap_lc3_preset.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap_lc3_preset.h index ac9b9533..2a4005dd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap_lc3_preset.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/bap_lc3_preset.h @@ -21,12 +21,13 @@ * @ingroup bluetooth * @{ * - * These APIs provide preset for codec configuration and codec QoS based on values supplied by the + * These APIs provide preset for codec configuration and QoS based on values supplied by the * codec configuration tables in the BAP specification. * */ #include +#include #include #ifdef __cplusplus @@ -38,7 +39,7 @@ struct bt_bap_lc3_preset { /** The LC3 Codec */ struct bt_audio_codec_cfg codec_cfg; /** The BAP spec defined QoS values */ - struct bt_audio_codec_qos qos; + struct bt_bap_qos_cfg qos; }; /** Helper to declare an LC3 preset structure */ @@ -59,7 +60,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 26u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 26u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 26u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Unicast 8_2_1 codec configuration @@ -71,7 +72,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 30u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 30u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Unicast 16_1_1 codec configuration @@ -83,7 +84,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 30u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 30u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Unicast 16_2_1 codec configuration @@ -97,7 +98,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 40U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 40u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 40u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Unicast 24_1_1 codec configuration @@ -109,7 +110,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 45U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 45u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 45u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Unicast 24_2_1 codec configuration @@ -123,7 +124,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 60u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 60u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Unicast 32_1_1 codec configuration @@ -135,7 +136,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 60u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 60u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Unicast 32_2_1 codec configuration @@ -147,7 +148,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 80u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 80u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Unicast 441_1_1 codec configuration @@ -159,7 +160,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 97U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(8163u, 97u, 5u, 24u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(8163u, 97u, 5u, 24u, 40000u)) /** * @brief Helper to declare LC3 Unicast 441_2_1 codec configuration @@ -171,7 +172,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 130U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(10884u, 130u, 5u, 31u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(10884u, 130u, 5u, 31u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_1_1 codec configuration @@ -183,7 +184,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75u, 5u, 15u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75u, 5u, 15u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_2_1 codec configuration @@ -195,7 +196,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100u, 5u, 20u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100u, 5u, 20u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_3_1 codec configuration @@ -207,7 +208,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 90u, 5u, 15u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 90u, 5u, 15u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_4_1 codec configuration @@ -219,7 +220,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 120u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 120u, 5u, 20u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 120u, 5u, 20u, 40000u)) /** * @brief Helper to declare LC3 Unicast 8_5_1 codec configuration @@ -231,7 +232,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 117u, \ 1, _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 117u, 5u, 15u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 117u, 5u, 15u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_6_1 codec configuration @@ -243,7 +244,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 155u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 155u, 5u, 20u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 155u, 5u, 20u, 40000u)) /** * @brief Helper to declare LC3 Unicast 8_1_2 codec configuration @@ -256,7 +257,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 26u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 26u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 26u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 8_2_2 codec configuration @@ -268,7 +269,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 30u, 13u, 95u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 30u, 13u, 95u, 40000u)) /** * @brief Helper to declare LC3 Unicast 16_1_2 codec configuration @@ -280,7 +281,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 30u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 30u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 16_2_2 codec configuration @@ -292,7 +293,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 40U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 40u, 13u, 95u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 40u, 13u, 95u, 40000u)) /** * @brief Helper to declare LC3 Unicast 24_1_2 codec configuration @@ -304,7 +305,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 45U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 45u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 45u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 24_2_2 codec configuration @@ -316,7 +317,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 60u, 13u, 95u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 60u, 13u, 95u, 40000u)) /** * @brief Helper to declare LC3 Unicast 32_1_2 codec configuration @@ -328,7 +329,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 60u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 60u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 32_2_2 codec configuration @@ -340,7 +341,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 80u, 13u, 95u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 80u, 13u, 95u, 40000u)) /** * @brief Helper to declare LC3 Unicast 441_1_2 codec configuration @@ -352,7 +353,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 97U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(8163u, 97u, 13u, 80u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(8163u, 97u, 13u, 80u, 40000u)) /** * @brief Helper to declare LC3 Unicast 441_2_2 codec configuration @@ -364,7 +365,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 130U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(10884u, 130u, 13u, 85u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(10884u, 130u, 13u, 85u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_1_2 codec configuration @@ -376,7 +377,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_2_2 codec configuration @@ -388,7 +389,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100u, 13u, 95u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100u, 13u, 95u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_3_2 codec configuration @@ -400,7 +401,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 90u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 90u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_4_2 codec configuration @@ -412,7 +413,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 120u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 120u, 13u, 100u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 120u, 13u, 100u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_5_2 codec configuration @@ -424,7 +425,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 117u, \ 1, _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 117u, 13u, 75u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 117u, 13u, 75u, 40000u)) /** * @brief Helper to declare LC3 Unicast 48_6_2 codec configuration @@ -436,7 +437,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 155u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 155u, 13u, 100u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 155u, 13u, 100u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 8_1_1 codec configuration @@ -449,7 +450,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 26u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 26u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 26u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 8_2_1 codec configuration @@ -461,7 +462,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 30u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 30u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 16_1_1 codec configuration @@ -473,7 +474,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 30u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 30u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 16_2_1 codec configuration @@ -487,7 +488,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 40U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 40u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 40u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 24_1_1 codec configuration @@ -499,7 +500,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 45U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 45u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 45u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 24_2_1 codec configuration @@ -513,7 +514,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 60u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 60u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 32_1_1 codec configuration @@ -525,7 +526,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 60u, 2u, 8u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 60u, 2u, 8u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 32_2_1 codec configuration @@ -537,7 +538,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 80u, 2u, 10u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 80u, 2u, 10u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 441_1_1 codec configuration @@ -549,7 +550,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 97U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(8163u, 97u, 4u, 24u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(8163u, 97u, 4u, 24u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 441_2_1 codec configuration @@ -561,7 +562,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 130U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(10884u, 130u, 4u, 31u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(10884u, 130u, 4u, 31u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_1_1 codec configuration @@ -573,7 +574,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75u, 4u, 15u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75u, 4u, 15u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_2_1 codec configuration @@ -585,7 +586,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100u, 4u, 20u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100u, 4u, 20u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_3_1 codec configuration @@ -597,7 +598,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 90u, 4u, 15u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 90u, 4u, 15u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_4_1 codec configuration @@ -609,7 +610,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 120u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 120u, 4u, 20u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 120u, 4u, 20u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_5_1 codec configuration @@ -621,7 +622,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 117u, \ 1, _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 117u, 4u, 15u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 117u, 4u, 15u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_6_1 codec configuration @@ -633,7 +634,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 155u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 155u, 4u, 20u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 155u, 4u, 20u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 8_1_2 codec configuration @@ -646,7 +647,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 26u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 26u, 4u, 45u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 26u, 4u, 45u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 8_2_2 codec configuration @@ -658,7 +659,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_8KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 30u, 4u, 60u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 30u, 4u, 60u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 16_1_2 codec configuration @@ -670,7 +671,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 30u, 4u, 45u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 30u, 4u, 45u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 16_2_2 codec configuration @@ -684,7 +685,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 40U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 40u, 4u, 60u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 40u, 4u, 60u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 24_1_2 codec configuration @@ -696,7 +697,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 45U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 45u, 4u, 45u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 45u, 4u, 45u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 24_2_2 codec configuration @@ -710,7 +711,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_24KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 60u, 4u, 60u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 60u, 4u, 60u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 32_1_2 codec configuration @@ -722,7 +723,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 60u, 4u, 45u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 60u, 4u, 45u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 32_2_2 codec configuration @@ -734,7 +735,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 80u, 4u, 60u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 80u, 4u, 60u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 441_1_2 codec configuration @@ -746,7 +747,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 97U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(8163u, 97u, 4u, 54u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(8163u, 97u, 4u, 54u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 441_2_2 codec configuration @@ -758,7 +759,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_44KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 130U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_FRAMED(10884u, 130u, 4u, 60u, 40000u)) + BT_BAP_QOS_CFG_FRAMED(10884u, 130u, 4u, 60u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_1_2 codec configuration @@ -770,7 +771,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75u, 4u, 50u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75u, 4u, 50u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_2_2 codec configuration @@ -782,7 +783,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100u, 4u, 65u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100u, 4u, 65u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_3_2 codec configuration @@ -794,7 +795,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 90u, 4u, 50u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 90u, 4u, 50u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_4_2 codec configuration @@ -806,7 +807,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 120u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 120u, 4u, 65u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 120u, 4u, 65u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_5_2 codec configuration @@ -818,7 +819,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 117u, \ 1, _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 117u, 4u, 50u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 117u, 4u, 50u, 40000u)) /** * @brief Helper to declare LC3 Broadcast 48_6_2 codec configuration @@ -830,7 +831,7 @@ struct bt_bap_lc3_preset { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 155u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 155u, 4u, 65u, 40000u)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 155u, 4u, 65u, 40000u)) #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/cap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/cap.h index f04c5c82..b539a463 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/cap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/cap.h @@ -41,7 +41,7 @@ #include #include #include -#include +#include #ifdef __cplusplus extern "C" { @@ -128,6 +128,22 @@ struct bt_cap_initiator_cb { */ void (*unicast_stop_complete)(int err, struct bt_conn *conn); #endif /* CONFIG_BT_BAP_UNICAST_CLIENT */ +#if defined(CONFIG_BT_BAP_BROADCAST_SOURCE) + /** + * @brief The Broadcast Source has started and all of the streams are ready for audio data + * + * @param source The started Broadcast Source + */ + void (*broadcast_started)(struct bt_cap_broadcast_source *source); + + /** + * @brief The Broadcast Source has stopped and none of the streams are ready for audio data + * + * @param source The stopped Broadcast Source + * @param reason The reason why the Broadcast Source stopped (see the BT_HCI_ERR_* values) + */ + void (*broadcast_stopped)(struct bt_cap_broadcast_source *source, uint8_t reason); +#endif /* CONFIG_BT_BAP_BROADCAST_SOURCE */ }; /** @@ -312,6 +328,9 @@ struct bt_cap_unicast_audio_stop_param { /** Array of streams to stop */ struct bt_cap_stream **streams; + + /** Whether to release the streams after they have stopped */ + bool release; }; /** @@ -346,7 +365,10 @@ int bt_cap_initiator_unregister_cb(const struct bt_cap_initiator_cb *cb); * * @param param Parameters to start the audio streams. * - * @return 0 on success or negative error value on failure. + * @retval 0 on success + * @retval -EBUSY if a CAP procedure is already in progress + * @retval -EINVAL if any parameter is invalid + * @retval -EALREADY All streams are already in the streaming state */ int bt_cap_initiator_unicast_audio_start(const struct bt_cap_unicast_audio_start_param *param); @@ -376,7 +398,10 @@ int bt_cap_initiator_unicast_audio_update(const struct bt_cap_unicast_audio_upda * * @param param Stop parameters. * - * @return 0 on success or negative error value on failure. + * @return 0 on success + * @retval -EBUSY if a CAP procedure is already in progress + * @retval -EINVAL if any parameter is invalid + * @retval -EALREADY if no state changes will occur */ int bt_cap_initiator_unicast_audio_stop(const struct bt_cap_unicast_audio_stop_param *param); @@ -447,7 +472,7 @@ struct bt_cap_initiator_broadcast_create_param { struct bt_cap_initiator_broadcast_subgroup_param *subgroup_params; /** Quality of Service configuration. */ - struct bt_audio_codec_qos *qos; + struct bt_bap_qos_cfg *qos; /** * @brief Broadcast Source packing mode. @@ -473,7 +498,7 @@ struct bt_cap_initiator_broadcast_create_param { * The string "Broadcast Code" shall be * [42 72 6F 61 64 63 61 73 74 20 43 6F 64 65 00 00] */ - uint8_t broadcast_code[BT_AUDIO_BROADCAST_CODE_SIZE]; + uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]; #if defined(CONFIG_BT_ISO_TEST_PARAMS) || defined(__DOXYGEN__) /** @@ -594,23 +619,6 @@ int bt_cap_initiator_broadcast_audio_stop(struct bt_cap_broadcast_source *broadc */ int bt_cap_initiator_broadcast_audio_delete(struct bt_cap_broadcast_source *broadcast_source); -/** - * @brief Get the broadcast ID of a Common Audio Profile broadcast source - * - * This will return the 3-octet broadcast ID that should be advertised in the - * extended advertising data with @ref BT_UUID_BROADCAST_AUDIO_VAL as - * @ref BT_DATA_SVC_DATA16. - * - * See table 3.14 in the Basic Audio Profile v1.0.1 for the structure. - * - * @param[in] broadcast_source Pointer to the broadcast source. - * @param[out] broadcast_id Pointer to the 3-octet broadcast ID. - * - * @return int 0 if on success, errno on error. - */ -int bt_cap_initiator_broadcast_get_id(const struct bt_cap_broadcast_source *broadcast_source, - uint32_t *const broadcast_id); - /** * @brief Get the Broadcast Audio Stream Endpoint of a Common Audio Profile broadcast source * @@ -817,6 +825,28 @@ struct bt_cap_commander_cb { * by bt_cap_commander_cancel(). */ void (*broadcast_reception_start)(struct bt_conn *conn, int err); + /** + * @brief Callback for bt_cap_commander_broadcast_reception_stop(). + * + * @param conn Pointer to the connection where the error + * occurred. NULL if @p err is 0 or if cancelled by + * bt_cap_commander_cancel() + * @param err 0 on success, BT_GATT_ERR() with a + * specific ATT (BT_ATT_ERR_*) error code or -ECANCELED if cancelled + * by bt_cap_commander_cancel(). + */ + void (*broadcast_reception_stop)(struct bt_conn *conn, int err); + /** + * @brief Callback for bt_cap_commander_distribute_broadcast_code(). + * + * @param conn Pointer to the connection where the error + * occurred. NULL if @p err is 0 or if cancelled by + * bt_cap_commander_cancel() + * @param err 0 on success, BT_GATT_ERR() with a + * specific ATT (BT_ATT_ERR_*) error code or -ECANCELED if cancelled + * by bt_cap_commander_cancel(). + */ + void (*distribute_broadcast_code)(struct bt_conn *conn, int err); #endif /* CONFIG_BT_BAP_BROADCAST_ASSISTANT */ }; @@ -915,7 +945,7 @@ struct bt_cap_commander_broadcast_reception_start_member_param { * * At least one bit in one of the subgroups bis_sync parameters shall be set. */ - struct bt_bap_bass_subgroup subgroups[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS]; + struct bt_bap_bass_subgroup subgroups[BT_BAP_BASS_MAX_SUBGROUPS]; /** Number of subgroups */ size_t num_subgroups; @@ -945,14 +975,25 @@ int bt_cap_commander_broadcast_reception_start( const struct bt_cap_commander_broadcast_reception_start_param *param); /** Parameters for stopping broadcast reception */ +struct bt_cap_commander_broadcast_reception_stop_member_param { + /** Coordinated or ad-hoc set member. */ + union bt_cap_set_member member; + + /** Source ID of the receive state. */ + uint8_t src_id; + + /** Number of subgroups */ + size_t num_subgroups; +}; + struct bt_cap_commander_broadcast_reception_stop_param { /** The type of the set. */ enum bt_cap_set_type type; - /** Coordinated or ad-hoc set member. */ - union bt_cap_set_member *members; + /** The set of devices for this procedure */ + struct bt_cap_commander_broadcast_reception_stop_member_param *param; - /** The number of members in @p members */ + /** The number of parameters in @p param */ size_t count; }; @@ -967,6 +1008,49 @@ struct bt_cap_commander_broadcast_reception_stop_param { int bt_cap_commander_broadcast_reception_stop( const struct bt_cap_commander_broadcast_reception_stop_param *param); +/** Parameters for distributing broadcast code */ +struct bt_cap_commander_distribute_broadcast_code_member_param { + /** Coordinated or ad-hoc set member. */ + union bt_cap_set_member member; + + /** Source ID of the receive state. */ + uint8_t src_id; +}; + +struct bt_cap_commander_distribute_broadcast_code_param { + /** The type of the set. */ + enum bt_cap_set_type type; + + /** The set of devices for this procedure */ + struct bt_cap_commander_distribute_broadcast_code_member_param *param; + + /** The number of parameters in @p param */ + size_t count; + + /** + * @brief 16-octet broadcast code. + * + * If the value is a string or a the value is less than 16 octets, + * the remaining octets shall be 0. + * + * Example: + * The string "Broadcast Code" shall be + * [42 72 6F 61 64 63 61 73 74 20 43 6F 64 65 00 00] + */ + uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE]; +}; + +/** + * @brief Distributes the broadcast code on one or more remote Common Audio Profile + * Acceptors + * + * @param param The parameters for distributing the broadcast code + * + * @return 0 on success or negative error value on failure. + */ +int bt_cap_commander_distribute_broadcast_code( + const struct bt_cap_commander_distribute_broadcast_code_param *param); + /** Parameters for changing absolute volume */ struct bt_cap_commander_change_volume_param { /** The type of the set. */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/ccid.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/ccid.h new file mode 100644 index 00000000..9340ab87 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/ccid.h @@ -0,0 +1,74 @@ +/** + * @file + * @brief Header for Bluetooth Audio Content Control Identifier. + * + * Copyright (c) 2020 Bose Corporation + * Copyright (c) 2021-2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_CCID_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_CCID_H_ + +/** + * @brief Bluetooth Content Control Identifier (CCID) + * @defgroup bt_ccid Bluetooth Content Control Identifier + * + * @since 3.7 + * @version 0.8.0 + * + * @ingroup bluetooth + * @{ + * + * The Content Control Identifier (CCID) API manages CCIDs for @ref BT_UUID_CCID characteristics. + */ + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Minimum CCID value */ +#define BT_CCID_MIN 0 +/** Maximum CCID value */ +#define BT_CCID_MAX 255 + +/** + * @brief Allocates a CCID value. + * + * This should always be called right before registering a GATT service that contains a + * @ref BT_UUID_CCID characteristic. Allocating a CCID without registering the characteristic + * may (in very rare cases) result in duplicated CCIDs on the device. + * + * Requires that @kconfig{CONFIG_BT_CONN} is enabled. + * + * @retval ccid 8-bit unsigned CCID value on success + * @retval -ENOMEM No more CCIDs can be allocated + */ +int bt_ccid_alloc_value(void); + +/** + * @brief Get the GATT attribute of a CCID value + * + * Searches the current GATT database for a CCID characteristic that has the supplied CCID value. + * + * Requires that @kconfig{CONFIG_BT_CONN} is enabled. + * + * @param ccid The CCID to search for + * + * @retval NULL None was found + * @retval attr Pointer to a GATT attribute + */ +const struct bt_gatt_attr *bt_ccid_find_attr(uint8_t ccid); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_CCID_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/csip.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/csip.h index c813c81a..e5e059d3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/csip.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/csip.h @@ -15,7 +15,7 @@ /** * @brief Coordinated Set Identification Profile (CSIP) * - * @defgroup bt_gatt_csip Coordinated Set Identification Profile (CSIP) + * @defgroup bt_csip Coordinated Set Identification Profile (CSIP) * * @since 3.0 * @version 0.8.0 @@ -494,6 +494,8 @@ int bt_csip_set_coordinator_ordered_access( * * The members will be locked starting from lowest rank going up. * + * @kconfig_dep{CONFIG_BT_CSIP_SET_COORDINATOR,CONFIG_BT_BONDABLE} + * * TODO: If locking fails, the already locked members will not be unlocked. * * @param members Array of set members to lock. @@ -512,6 +514,8 @@ int bt_csip_set_coordinator_lock(const struct bt_csip_set_coordinator_set_member * * The members will be released starting from highest rank going down. * + * @kconfig_dep{CONFIG_BT_CSIP_SET_COORDINATOR,CONFIG_BT_BONDABLE} + * * @param members Array of set members to lock. * @param count Number of set members in @p members. * @param set_info Pointer to the a specific set_info struct, as a member may diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap.h index 0fb5c3b0..edb38d04 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap.h @@ -89,7 +89,7 @@ enum bt_gmap_ugt_feat { /** * @brief Source support * - * Requires @kconfig{CONFIG_BT_ASCS_ASE_SRC_COUNT} > 0 + * Requires @kconfig{CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT} > 0 */ BT_GMAP_UGT_FEAT_SOURCE = BIT(0), /** @@ -101,7 +101,7 @@ enum bt_gmap_ugt_feat { /** * @brief Sink support * - * Requires @kconfig{CONFIG_BT_ASCS_ASE_SNK_COUNT} > 0 + * Requires @kconfig{CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT} > 0 */ BT_GMAP_UGT_FEAT_SINK = BIT(2), /** @@ -119,14 +119,14 @@ enum bt_gmap_ugt_feat { /** * @brief Support for receiving at least two audio channels, each in a separate CIS * - * Requires @kconfig{CONFIG_BT_ASCS_ASE_SNK_COUNT} > 1 and + * Requires @kconfig{CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT} > 1 and * @kconfig{CONFIG_BT_ASCS_MAX_ACTIVE_ASES} > 1, and BT_GMAP_UGT_FEAT_SINK to be set as well */ BT_GMAP_UGT_FEAT_MULTISINK = BIT(5), /** * @brief Support for sending at least two audio channels, each in a separate CIS * - * Requires @kconfig{CONFIG_BT_ASCS_ASE_SRC_COUNT} > 1 and + * Requires @kconfig{CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT} > 1 and * @kconfig{CONFIG_BT_ASCS_MAX_ACTIVE_ASES} > 1, and BT_GMAP_UGT_FEAT_SOURCE to be set * as well */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap_lc3_preset.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap_lc3_preset.h index 35bce011..73217d9d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap_lc3_preset.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/gmap_lc3_preset.h @@ -21,7 +21,7 @@ * @ingroup bluetooth * @{ * - * These APIs provide presets for codec configuration and codec QoS based on values supplied by the + * These APIs provide presets for codec configuration and QoS based on values supplied by the * codec configurations from table 3.16 in the GMAP v1.0 specification */ @@ -43,7 +43,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 60U, 1U, 15U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 60U, 1U, 15U, 10000U)) /** * @brief Helper to declare LC3 32_2_gr codec configuration @@ -55,7 +55,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 80U, 1U, 20U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 80U, 1U, 20U, 10000U)) /** * @brief Helper to declare LC3 48_1_gr codec configuration @@ -67,7 +67,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75U, 1U, 15U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75U, 1U, 15U, 10000U)) /** * @brief Helper to declare LC3 48_2_gr codec configuration @@ -81,7 +81,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100U, 1U, 20U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100U, 1U, 20U, 10000U)) /** * @brief Helper to declare LC3 48_3_gr codec configuration @@ -93,7 +93,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 90U, 1U, 15U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 90U, 1U, 15U, 10000U)) /** * @brief Helper to declare LC3 48_4_gr codec configuration @@ -107,7 +107,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 120u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 120U, 1U, 20U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 120U, 1U, 20U, 10000U)) /** * @brief Helper to declare LC3 16_1_gs codec configuration @@ -119,7 +119,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 30U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 30U, 1U, 15U, 60000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 30U, 1U, 15U, 60000U)) /** * @brief Helper to declare LC3 16_2_gs codec configuration @@ -131,7 +131,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_16KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 40U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 40U, 1U, 20U, 60000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 40U, 1U, 20U, 60000U)) /** * @brief Helper to declare LC3 32_1_gs codec configuration @@ -143,7 +143,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 60U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 60U, 1U, 15U, 60000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 60U, 1U, 15U, 60000U)) /** * @brief Helper to declare LC3 32_2_gs codec configuration @@ -155,7 +155,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_32KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 80U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 80U, 1U, 20U, 60000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 80U, 1U, 20U, 60000U)) /** * @brief Helper to declare LC3 48_1_gs codec configuration @@ -167,7 +167,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75U, 1U, 15U, 60000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75U, 1U, 15U, 60000U)) /** * @brief Helper to declare LC3 48_2_gs codec configuration @@ -179,7 +179,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100U, 1U, 20U, 60000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100U, 1U, 20U, 60000U)) /* GMAP LC3 broadcast presets defined by table 3.22 in the GMAP v1.0 specification */ @@ -193,7 +193,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 75U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 75U, 1U, 8U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 75U, 1U, 8U, 10000U)) /** * @brief Helper to declare LC3 48_2_g codec configuration @@ -205,7 +205,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 100U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 100U, 1U, 10U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 100U, 1U, 10U, 10000U)) /** * @brief Helper to declare LC3 48_3_g codec configuration @@ -217,7 +217,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_7_5, _loc, 90U, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(7500u, 90U, 1U, 8U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(7500u, 90U, 1U, 8U, 10000U)) /** * @brief Helper to declare LC3 48_4_g codec configuration @@ -229,7 +229,7 @@ extern "C" { BT_BAP_LC3_PRESET(BT_AUDIO_CODEC_LC3_CONFIG(BT_AUDIO_CODEC_CFG_FREQ_48KHZ, \ BT_AUDIO_CODEC_CFG_DURATION_10, _loc, 120u, 1, \ _stream_context), \ - BT_AUDIO_CODEC_QOS_UNFRAMED(10000u, 120U, 1U, 10U, 10000U)) + BT_BAP_QOS_CFG_UNFRAMED(10000u, 120U, 1U, 10U, 10000U)) #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/lc3.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/lc3.h index b206a241..3b8d4e6a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/lc3.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/lc3.h @@ -14,7 +14,11 @@ /** * @brief LC3 - * @defgroup BT_AUDIO_CODEC_LC3 AUDIO + * @defgroup bt_lc3 Bluetooth LC3 codec + + * @since 3.0 + * @version 0.8.0 + * @ingroup bluetooth * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/mcc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/mcc.h index 6b6d0dcf..2b617554 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/mcc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/mcc.h @@ -17,7 +17,7 @@ * * Updated to the Media Control Profile specification revision 1.0 * - * @defgroup bt_gatt_mcc Media Control Client (MCC) + * @defgroup bt_mcc Media Control Client (MCC) * * @since 3.0 * @version 0.8.0 @@ -30,7 +30,7 @@ #include #include -#include +#include #include #ifdef __cplusplus diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/micp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/micp.h index ea79de94..45d75c51 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/micp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/micp.h @@ -15,7 +15,7 @@ /** * @brief Microphone Control Profile (MICP) * - * @defgroup bt_gatt_micp Microphone Control Profile (MICP) + * @defgroup bt_micp Microphone Control Profile (MICP) * * @since 2.7 * @version 0.8.0 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pacs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pacs.h index 12023280..e956e0da 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pacs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pacs.h @@ -15,7 +15,7 @@ /** * @brief Published Audio Capabilities Service (PACS) * - * @defgroup bt_gatt_csip Coordinated Set Identification Profile (CSIP) + * @defgroup bt_pacs Published Audio Capabilities Service (PACS) * * @since 3.0 * @version 0.8.0 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pbp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pbp.h index d577bfe7..db649e52 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pbp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/pbp.h @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tbs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tbs.h index 6c0451fb..6f408ff8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tbs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tbs.h @@ -30,6 +30,7 @@ #include #include +#include #include #ifdef __cplusplus @@ -125,6 +126,8 @@ extern "C" { #define BT_TBS_FEATURE_HOLD BIT(0) /** Join Call Control Point Opcode supported */ #define BT_TBS_FEATURE_JOIN BIT(1) +/** All Control Point Opcodes supported */ +#define BT_TBS_FEATURE_ALL (BT_TBS_FEATURE_HOLD | BT_TBS_FEATURE_JOIN) /** @} */ /** @@ -246,8 +249,6 @@ typedef void (*bt_tbs_call_change_cb)(struct bt_conn *conn, /** * @brief Callback function for authorizing a client. * - * Only used if BT_TBS_AUTHORIZATION is enabled. - * * @param conn The connection used. * * @return true if authorized, false otherwise @@ -461,6 +462,98 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, */ void bt_tbs_register_cb(struct bt_tbs_cb *cbs); +struct bt_tbs_register_param { + /** The name of the provider, for example a cellular service provider */ + char *provider_name; + + /** + * @brief The Uniform Caller Identifier of the bearer + * + * See the Uniform Caller Identifiers table in Bluetooth Assigned Numbers + */ + char *uci; + + /** + * The Uniform Resource Identifiers schemes supported by this bearer as an UTF-8 string + * + * See https://www.iana.org/assignments/uri-schemes/uri-schemes.xhtml for possible values. + * If multiple values are used, these shall be comma separated, e.g. "tel,skype". + */ + char *uri_schemes_supported; + + /** + * @brief Whether this bearer shall be registered as a Generic Telephone Bearer server + * + * A GTBS shall be registered before any non-GTBS services. There can only be a single GTBS + * registered. + */ + bool gtbs; + + /** + * @brief Whether the application will need to authorize changes to calls + * + * If set to false then the service will automatically accept write requests from clients. + */ + bool authorization_required; + + /** + * @brief The technology of the bearer + * + * See the BT_TBS_TECHNOLOGY_* values. + */ + uint8_t technology; + + /** + * @brief The optional supported features of the bearer + * + * See the BT_TBS_FEATURE_* values. + */ + uint8_t supported_features; +}; + +/** + * @brief Register a Telephone Bearer + * + * This will register a Telephone Bearer Service (TBS) (or a Generic Telephone Bearer service + * (GTBS)) with the provided parameters. + * + * As per the TBS specification, the GTBS shall be instantiated for the feature, and as such a GTBS + * shall always be registered before any TBS can be registered. + * Similarly, all TBS shall be unregistered before the GTBS can be unregistered with + * bt_tbs_unregister_bearer(). + * + * @param param The parameters to initialize the bearer. + + * @retval index The bearer index if return value is >= 0 + * @retval -EINVAL @p param contains invalid data + * @retval -EALREADY @p param.gtbs is true and GTBS has already been registered + * @retval -EAGAIN @p param.gtbs is false and GTBS has not been registered + * @retval -ENOMEM @p param.gtbs is false and no more TBS can be registered (see + * @kconfig{CONFIG_BT_TBS_BEARER_COUNT}) + * @retval -ENOEXEC The service failed to be registered + */ +int bt_tbs_register_bearer(const struct bt_tbs_register_param *param); + +/** + * @brief Unregister a Telephone Bearer + * + * This will unregister a Telephone Bearer Service (TBS) (or a Generic Telephone Bearer service + * (GTBS)) with the provided parameters. The bearer shall be registered first by + * bt_tbs_register_bearer() before it can be unregistered. + * + * Similarly, all TBS shall be unregistered before the GTBS can be unregistered with. + * + * @param bearer_index The index of the bearer to unregister. + * + * @retval 0 Success + * @retval -EINVAL @p bearer_index is invalid + * @retval -EALREADY The bearer identified by @p bearer_index is not registered + * @retval -EAGAIN The bearer identified by @p bearer_index is GTBS and there are TBS instances + * registered. + * @retval -ENOEXEC The service failed to be unregistered + */ +int bt_tbs_unregister_bearer(uint8_t bearer_index); + /** @brief Prints all calls of all services to the debug log */ void bt_tbs_dbg_print_calls(void); @@ -680,6 +773,9 @@ struct bt_tbs_client_cb { /** Bearer friendly name has been read */ bt_tbs_client_read_string_cb friendly_name; #endif /* defined(CONFIG_BT_TBS_CLIENT_CALL_FRIENDLY_NAME) */ + + /** @internal Internally used field for list handling */ + sys_snode_t _node; }; /** @@ -998,8 +1094,12 @@ int bt_tbs_client_read_optional_opcodes(struct bt_conn *conn, * @brief Register the callbacks for CCP. * * @param cbs Pointer to the callback structure. + * + * @retval 0 Success + * @retval -EINVAL @p cbs is NULL + * @retval -EEXIST @p cbs is already registered */ -void bt_tbs_client_register_cb(const struct bt_tbs_client_cb *cbs); +int bt_tbs_client_register_cb(struct bt_tbs_client_cb *cbs); /** * @brief Look up Telephone Bearer Service instance by CCID diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tmap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tmap.h index 94682cee..ad16aead 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tmap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/tmap.h @@ -11,6 +11,21 @@ #ifndef ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_TMAP_ #define ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_TMAP_ +/** + * @brief Telephone and Media Audio Profile (TMAP) + * + * @defgroup bt_tmap Telephone and Media Audio Profile (TMAP) + * + * @since 3.4 + * @version 0.8.0 + * + * @ingroup bluetooth + * @{ + * + * The Telephone and Media Audio Profile (TMAP) uses a collection of Bluetooth features and profiles + * to enable interoperability between devices for telephony and media audio. + */ + #include #include #include @@ -138,4 +153,8 @@ int bt_tmap_discover(struct bt_conn *conn, const struct bt_tmap_cb *tmap_cb); */ void bt_tmap_set_role(enum bt_tmap_role role); +/** + * @} + */ + #endif /* ZEPHYR_INCLUDE_BLUETOOTH_AUDIO_TMAP_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vcp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vcp.h index ae26112c..29662ffe 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vcp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vcp.h @@ -15,7 +15,7 @@ /** * @brief Volume Control Profile (VCP) * - * @defgroup bt_gatt_vcp Volume Control Profile (VCP) + * @defgroup bt_vcp Volume Control Profile (VCP) * * @since 2.7 * @version 0.8.0 @@ -163,12 +163,14 @@ struct bt_vcp_vol_rend_cb { * bt_vcp_vol_rend_get_state(), or if the state is changed by either * the Volume Renderer or a remote Volume Controller. * + * @param conn Pointer to the connection to a remote device if + * the change was caused by it, otherwise NULL. * @param err Error value. 0 on success, GATT error on positive value * or errno on negative value. * @param volume The volume of the Volume Control Service server. * @param mute The mute setting of the Volume Control Service server. */ - void (*state)(int err, uint8_t volume, uint8_t mute); + void (*state)(struct bt_conn *conn, int err, uint8_t volume, uint8_t mute); /** * @brief Callback function for Volume Control Service flags. @@ -177,11 +179,13 @@ struct bt_vcp_vol_rend_cb { * Called when the value is remotely read as the client. * Called if the value is changed by either the server or client. * + * @param conn Pointer to the connection to a remote device if + * the change was caused by it, otherwise NULL. * @param err Error value. 0 on success, GATT error on positive value * or errno on negative value. * @param flags The flags of the Volume Control Service server. */ - void (*flags)(int err, uint8_t flags); + void (*flags)(struct bt_conn *conn, int err, uint8_t flags); }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vocs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vocs.h index 7de2d686..7a17c095 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vocs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/audio/vocs.h @@ -15,7 +15,7 @@ /** * @brief Volume Offset Control Service (VOCS) * - * @defgroup bt_gatt_vocs Volume Offset Control Service (VOCS) + * @defgroup bt_vocs Volume Offset Control Service (VOCS) * * @since 2.6 * @version 0.8.0 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/bluetooth.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/bluetooth.h index f26d72c5..b488e8d0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/bluetooth.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/bluetooth.h @@ -22,10 +22,12 @@ #include #include -#include +#include #include #include #include +#include +#include #ifdef __cplusplus extern "C" { @@ -220,7 +222,7 @@ typedef void (*bt_ready_cb_t)(int err); * earlier. * * @param cb Callback to notify completion or NULL to perform the - * enabling synchronously. + * enabling synchronously. The callback is called from the system workqueue. * * @return Zero on success or (negative) error code otherwise. */ @@ -236,7 +238,8 @@ int bt_enable(bt_ready_cb_t cb); * with settings_load() before reenabling the stack. * * This API does _not_ clear previously registered callbacks - * like @ref bt_le_scan_cb_register and @ref bt_conn_cb_register. + * like @ref bt_le_scan_cb_register, @ref bt_conn_cb_register + * AND @ref bt_br_discovery_cb_register. * That is, the application shall not re-register them when * the Bluetooth subsystem is re-enabled later. * @@ -523,16 +526,42 @@ enum { /** * @brief Advertise as connectable. * + * @deprecated Use @ref BT_LE_ADV_OPT_CONN instead. + * * Advertise as connectable. If not connectable then the type of * advertising is determined by providing scan response data. * The advertiser address is determined by the type of advertising * and/or enabling privacy @kconfig{CONFIG_BT_PRIVACY}. + * + * Starting connectable advertising preallocates a connection + * object. If this fails, the API returns @c -ENOMEM. + * + * When an advertiser set results in a connection creation, the + * controller automatically disables that advertising set. + * + * If the advertising set was started with @ref bt_le_adv_start + * without @ref BT_LE_ADV_OPT_ONE_TIME, the host will attempt to + * resume the advertiser under some conditions. + */ + BT_LE_ADV_OPT_CONNECTABLE __deprecated = BIT(0), + + /** + * @internal + * + * Internal access to the deprecated value to maintain the + * implementation of the deprecated feature. + * + * At the end of the deprecation period, ABI will change so + * `BT_LE_ADV_OPT_CONN` is just `BIT(0)`, removing the need for this + * symbol. */ - BT_LE_ADV_OPT_CONNECTABLE = BIT(0), + _BT_LE_ADV_OPT_CONNECTABLE = BIT(0), /** * @brief Advertise one time. * + * @deprecated Use @ref BT_LE_ADV_OPT_CONN instead. + * * Don't try to resume connectable advertising after a connection. * This option is only meaningful when used together with * BT_LE_ADV_OPT_CONNECTABLE. If set the advertising will be stopped @@ -544,7 +573,35 @@ enum { * @ref bt_le_ext_adv_start then this behavior is the default behavior * and this flag has no effect. */ - BT_LE_ADV_OPT_ONE_TIME = BIT(1), + BT_LE_ADV_OPT_ONE_TIME __deprecated = BIT(1), + + /** + * @internal + * + * Internal access to the deprecated value to maintain + * the implementation of the deprecated feature. + */ + _BT_LE_ADV_OPT_ONE_TIME = BIT(1), + + /** + * @brief Connectable advertising + * + * Starting connectable advertising preallocates a connection + * object. If this fails, the API returns @c -ENOMEM. + * + * The advertising set stops immediately after it creates a + * connection. This happens automatically in the controller. + * + * @note To continue advertising after a connection is created, + * the application should listen for the @ref bt_conn_cb.connected + * event and start the advertising set again. Note that the + * advertiser cannot be started when all connection objects are + * in use. In that case, defer starting the advertiser until + * @ref bt_conn_cb.recycled. To continue after a disconnection, + * listen for @ref bt_conn_cb.recycled. + + */ + BT_LE_ADV_OPT_CONN = BIT(0) | BIT(1), /** * @brief Advertise using identity address. @@ -623,8 +680,7 @@ enum { * @brief Support scan response data. * * When used together with @ref BT_LE_ADV_OPT_EXT_ADV then this option - * cannot be used together with the @ref BT_LE_ADV_OPT_CONNECTABLE - * option. + * cannot be used together with the @ref BT_LE_ADV_OPT_CONN option. * When used together with @ref BT_LE_ADV_OPT_EXT_ADV then scan * response data must be set. */ @@ -912,20 +968,61 @@ struct bt_le_per_adv_param { BT_LE_ADV_PARAM_INIT(_options, _int_min, _int_max, _peer) \ }) -#define BT_LE_ADV_CONN_DIR(_peer) BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE | \ - BT_LE_ADV_OPT_ONE_TIME, 0, 0,\ - _peer) +#define BT_LE_ADV_CONN_DIR(_peer) BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONN, 0, 0, _peer) +/** + * @deprecated This is a convenience macro for @ref + * BT_LE_ADV_OPT_CONNECTABLE, which is deprecated. Please use + * @ref BT_LE_ADV_CONN_FAST_1 or @ref BT_LE_ADV_CONN_FAST_2 + * instead. + */ +#define BT_LE_ADV_CONN \ + BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE, BT_GAP_ADV_FAST_INT_MIN_2, \ + BT_GAP_ADV_FAST_INT_MAX_2, NULL) \ + __DEPRECATED_MACRO -#define BT_LE_ADV_CONN BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE, \ - BT_GAP_ADV_FAST_INT_MIN_2, \ - BT_GAP_ADV_FAST_INT_MAX_2, NULL) +/** @brief GAP recommended connectable advertising + * + * This is the recommended default for when a person is likely + * to be waiting the device to connect or be discovered. + * + * Use a longer interval to conserve battery at the cost of + * responsiveness. Consider entering a lower power state with + * longer intervals after a timeout. + * + * GAP recommends advertisers use this "when user-initiated". + * The application developer decides what this means. It can by + * any time the user interacts with the device, a press on a + * dedicated Bluetooth wakeup button, or anything in-between. + * + * This is the recommended setting for limited discoverable + * mode. + * + * See Bluetooth Core Specification: + * - 3.C.A "Timers and Constants", T_GAP(adv_fast_interval1) + * - 3.C.9.3.11 "Connection Establishment Timing parameters" + */ +#define BT_LE_ADV_CONN_FAST_1 \ + BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONN, BT_GAP_ADV_FAST_INT_MIN_1, BT_GAP_ADV_FAST_INT_MAX_1, \ + NULL) -/** This is the recommended default for connectable advertisers. +/** @brief Connectable advertising with + * T_GAP(adv_fast_interval2) + * + * The advertising interval corresponds to what was offered as + * `BT_LE_ADV_CONN` in Zephyr 3.6 and earlier, but unlike + * `BT_LE_ADV_CONN`, the host does not automatically resume the + * advertiser after it results in a connection. + * + * See Bluetooth Core Specification: + * - 3.C.A "Timers and Constants", T_GAP(adv_fast_interval1) + * - 3.C.9.3.11 "Connection Establishment Timing parameters" */ -#define BT_LE_ADV_CONN_ONE_TIME \ - BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE | BT_LE_ADV_OPT_ONE_TIME, \ - BT_GAP_ADV_FAST_INT_MIN_2, BT_GAP_ADV_FAST_INT_MAX_2, NULL) +#define BT_LE_ADV_CONN_FAST_2 \ + BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONN, BT_GAP_ADV_FAST_INT_MIN_2, BT_GAP_ADV_FAST_INT_MAX_2, \ + NULL) + +#define BT_LE_ADV_CONN_ONE_TIME BT_LE_ADV_CONN_FAST_2 __DEPRECATED_MACRO /** * @deprecated This macro will be removed in the near future, see @@ -948,11 +1045,9 @@ struct bt_le_per_adv_param { BT_GAP_ADV_FAST_INT_MAX_2, NULL) \ __DEPRECATED_MACRO -#define BT_LE_ADV_CONN_DIR_LOW_DUTY(_peer) \ - BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONNECTABLE | BT_LE_ADV_OPT_ONE_TIME | \ - BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY, \ - BT_GAP_ADV_FAST_INT_MIN_2, BT_GAP_ADV_FAST_INT_MAX_2, \ - _peer) +#define BT_LE_ADV_CONN_DIR_LOW_DUTY(_peer) \ + BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONN | BT_LE_ADV_OPT_DIR_MODE_LOW_DUTY, \ + BT_GAP_ADV_FAST_INT_MIN_2, BT_GAP_ADV_FAST_INT_MAX_2, _peer) /** Non-connectable advertising with private address */ #define BT_LE_ADV_NCONN BT_LE_ADV_PARAM(0, BT_GAP_ADV_FAST_INT_MIN_2, \ @@ -976,11 +1071,9 @@ struct bt_le_per_adv_param { NULL) /** Connectable extended advertising */ -#define BT_LE_EXT_ADV_CONN BT_LE_ADV_PARAM(BT_LE_ADV_OPT_EXT_ADV | \ - BT_LE_ADV_OPT_CONNECTABLE, \ - BT_GAP_ADV_FAST_INT_MIN_2, \ - BT_GAP_ADV_FAST_INT_MAX_2, \ - NULL) +#define BT_LE_EXT_ADV_CONN \ + BT_LE_ADV_PARAM(BT_LE_ADV_OPT_EXT_ADV | BT_LE_ADV_OPT_CONN, BT_GAP_ADV_FAST_INT_MIN_2, \ + BT_GAP_ADV_FAST_INT_MAX_2, NULL) /** * @deprecated This macro will be removed in the near future, see @@ -2065,12 +2158,26 @@ struct bt_le_scan_param { uint8_t type; /** Bit-field of scanning options. */ - uint32_t options; + uint8_t options; - /** Scan interval (N * 0.625 ms) */ + /** Scan interval (N * 0.625 ms). + * + * @note When @kconfig{CONFIG_BT_SCAN_AND_INITIATE_IN_PARALLEL} is enabled + * and the application wants to scan and connect in parallel, + * the Bluetooth Controller may require the scan interval used + * for scanning and connection establishment to be equal to + * obtain the best performance. + */ uint16_t interval; - /** Scan window (N * 0.625 ms) */ + /** Scan window (N * 0.625 ms) + * + * @note When @kconfig{CONFIG_BT_SCAN_AND_INITIATE_IN_PARALLEL} is enabled + * and the application wants to scan and connect in parallel, + * the Bluetooth Controller may require the scan window used + * for scanning and connection establishment to be equal to + * obtain the best performance. + */ uint16_t window; /** @@ -2294,6 +2401,7 @@ BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN, * * @return Zero on success or error code otherwise, positive in case of * protocol error or negative (POSIX) in case of stack internal error. + * @retval -EBUSY if the scanner is already being started in a different thread. */ int bt_le_scan_start(const struct bt_le_scan_param *param, bt_le_scan_cb_t cb); @@ -2506,126 +2614,6 @@ int bt_le_oob_get_local(uint8_t id, struct bt_le_oob *oob); int bt_le_ext_adv_oob_get_local(struct bt_le_ext_adv *adv, struct bt_le_oob *oob); -/** @brief BR/EDR discovery result structure */ -struct bt_br_discovery_result { - /** private */ - uint8_t _priv[4]; - - /** Remote device address */ - bt_addr_t addr; - - /** RSSI from inquiry */ - int8_t rssi; - - /** Class of Device */ - uint8_t cod[3]; - - /** Extended Inquiry Response */ - uint8_t eir[240]; -}; - -/** - * @typedef bt_br_discovery_cb_t - * @brief Callback type for reporting BR/EDR discovery (inquiry) - * results. - * - * A callback of this type is given to the bt_br_discovery_start() - * function and will be called at the end of the discovery with - * information about found devices populated in the results array. - * - * @param results Storage used for discovery results - * @param count Number of valid discovery results. - */ -typedef void bt_br_discovery_cb_t(struct bt_br_discovery_result *results, - size_t count); - -/** BR/EDR discovery parameters */ -struct bt_br_discovery_param { - /** Maximum length of the discovery in units of 1.28 seconds. - * Valid range is 0x01 - 0x30. - */ - uint8_t length; - - /** True if limited discovery procedure is to be used. */ - bool limited; -}; - -/** - * @brief Start BR/EDR discovery - * - * Start BR/EDR discovery (inquiry) and provide results through the specified - * callback. When bt_br_discovery_cb_t is called it indicates that discovery - * has completed. If more inquiry results were received during session than - * fits in provided result storage, only ones with highest RSSI will be - * reported. - * - * @param param Discovery parameters. - * @param results Storage for discovery results. - * @param count Number of results in storage. Valid range: 1-255. - * @param cb Callback to notify discovery results. - * - * @return Zero on success or error code otherwise, positive in case - * of protocol error or negative (POSIX) in case of stack internal error - */ -int bt_br_discovery_start(const struct bt_br_discovery_param *param, - struct bt_br_discovery_result *results, size_t count, - bt_br_discovery_cb_t cb); - -/** - * @brief Stop BR/EDR discovery. - * - * Stops ongoing BR/EDR discovery. If discovery was stopped by this call - * results won't be reported - * - * @return Zero on success or error code otherwise, positive in case of - * protocol error or negative (POSIX) in case of stack internal error. - */ -int bt_br_discovery_stop(void); - -struct bt_br_oob { - /** BR/EDR address. */ - bt_addr_t addr; -}; - -/** - * @brief Get BR/EDR local Out Of Band information - * - * This function allows to get local controller information that are useful - * for Out Of Band pairing or connection creation process. - * - * @param oob Out Of Band information - */ -int bt_br_oob_get_local(struct bt_br_oob *oob); - - -/** - * @brief Enable/disable set controller in discoverable state. - * - * Allows make local controller to listen on INQUIRY SCAN channel and responds - * to devices making general inquiry. To enable this state it's mandatory - * to first be in connectable state. - * - * @param enable Value allowing/disallowing controller to become discoverable. - * - * @return Negative if fail set to requested state or requested state has been - * already set. Zero if done successfully. - */ -int bt_br_set_discoverable(bool enable); - -/** - * @brief Enable/disable set controller in connectable state. - * - * Allows make local controller to be connectable. It means the controller - * start listen to devices requests on PAGE SCAN channel. If disabled also - * resets discoverability if was set. - * - * @param enable Value allowing/disallowing controller to be connectable. - * - * @return Negative if fail set to requested state or requested state has been - * already set. Zero if done successfully. - */ -int bt_br_set_connectable(bool enable); - /** * @brief Clear pairing information. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/buf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/buf.h index b373ab5b..dd452342 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/buf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/buf.h @@ -20,7 +20,7 @@ #include -#include +#include #include #include @@ -28,22 +28,22 @@ extern "C" { #endif -/** Possible types of buffers passed around the Bluetooth stack */ +/** Possible types of buffers passed around the Bluetooth stack in a form of bitmask. */ enum bt_buf_type { /** HCI command */ - BT_BUF_CMD, + BT_BUF_CMD = BIT(0), /** HCI event */ - BT_BUF_EVT, + BT_BUF_EVT = BIT(1), /** Outgoing ACL data */ - BT_BUF_ACL_OUT, + BT_BUF_ACL_OUT = BIT(2), /** Incoming ACL data */ - BT_BUF_ACL_IN, + BT_BUF_ACL_IN = BIT(3), /** Outgoing ISO data */ - BT_BUF_ISO_OUT, + BT_BUF_ISO_OUT = BIT(4), /** Incoming ISO data */ - BT_BUF_ISO_IN, + BT_BUF_ISO_IN = BIT(5), /** H:4 data */ - BT_BUF_H4, + BT_BUF_H4 = BIT(6), }; /** @brief This is a base type for bt_buf user data. */ @@ -85,13 +85,41 @@ struct bt_buf_data { #define BT_BUF_ISO_RX_COUNT 0 #endif /* CONFIG_BT_ISO */ +/* see Core Spec v6.0 vol.4 part E 7.4.5 */ +#define BT_BUF_ACL_RX_COUNT_MAX 65535 + +#if defined(CONFIG_BT_CONN) && defined(CONFIG_BT_HCI_HOST) + /* The host needs more ACL buffers than maximum ACL links. This is because of + * the way we re-assemble ACL packets into L2CAP PDUs. + * + * We keep around the first buffer (that comes from the driver) to do + * re-assembly into, and if all links are re-assembling, there will be no buffer + * available for the HCI driver to allocate from. + * + * TODO: When CONFIG_BT_BUF_ACL_RX_COUNT is removed, + * remove the MAX and only keep (CONFIG_BT_MAX_CONN + 1) + */ +#define BT_BUF_ACL_RX_COUNT \ + (MAX(CONFIG_BT_BUF_ACL_RX_COUNT, (CONFIG_BT_MAX_CONN + 1)) + \ + CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA) +#else +#define BT_BUF_ACL_RX_COUNT 0 +#endif /* CONFIG_BT_CONN && CONFIG_BT_HCI_HOST */ + +#if defined(CONFIG_BT_BUF_ACL_RX_COUNT) && CONFIG_BT_BUF_ACL_RX_COUNT > 0 +#warning "CONFIG_BT_BUF_ACL_RX_COUNT is deprecated, see Zephyr 4.1 migration guide" +#endif /* CONFIG_BT_BUF_ACL_RX_COUNT && CONFIG_BT_BUF_ACL_RX_COUNT > 0 */ + +BUILD_ASSERT(BT_BUF_ACL_RX_COUNT <= BT_BUF_ACL_RX_COUNT_MAX, + "Maximum number of ACL RX buffer is 65535, reduce CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA"); + /** Data size needed for HCI ACL, HCI ISO or Event RX buffers */ #define BT_BUF_RX_SIZE (MAX(MAX(BT_BUF_ACL_RX_SIZE, BT_BUF_EVT_RX_SIZE), \ BT_BUF_ISO_RX_SIZE)) /** Buffer count needed for HCI ACL, HCI ISO or Event RX buffers */ #define BT_BUF_RX_COUNT (MAX(MAX(CONFIG_BT_BUF_EVT_RX_COUNT, \ - CONFIG_BT_BUF_ACL_RX_COUNT), \ + BT_BUF_ACL_RX_COUNT), \ BT_BUF_ISO_RX_COUNT)) /** Data size needed for HCI Command buffers. */ @@ -110,6 +138,27 @@ struct bt_buf_data { */ struct net_buf *bt_buf_get_rx(enum bt_buf_type type, k_timeout_t timeout); +/** A callback to notify about freed buffer in the incoming data pool. + * + * This callback is called when a buffer of a given type is freed and can be requested through the + * @ref bt_buf_get_rx function. However, this callback is called from the context of the buffer + * freeing operation and must not attempt to allocate a new buffer from the same pool. + * + * @warning When this callback is called, the scheduler is locked and the callee must not perform + * any action that makes the current thread unready. This callback must only be used for very + * short non-blocking operation (e.g. submitting a work item). + * + * @param type_mask A bit mask of buffer types that have been freed. + */ +typedef void (*bt_buf_rx_freed_cb_t)(enum bt_buf_type type_mask); + +/** Set the callback to notify about freed buffer in the incoming data pool. + * + * @param cb Callback to notify about freed buffer in the incoming data pool. If NULL, the callback + * is disabled. + */ +void bt_buf_rx_freed_cb_set(bt_buf_rx_freed_cb_t cb); + /** Allocate a buffer for outgoing data * * This will set the buffer type so bt_buf_set_type() does not need to diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/byteorder.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/byteorder.h index 8ac17da4..d8432c5d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/byteorder.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/byteorder.h @@ -107,6 +107,78 @@ extern "C" { BT_BYTES_LIST_LE32(_v), \ BT_BYTES_LIST_LE32((_v) >> 32) \ +/** @brief Encode 16-bit value into array values in big-endian format. + * + * Helper macro to encode 16-bit values into comma separated values. + * + * @note @p _v is evaluated 2 times. + * + * @param _v 16-bit integer in host endianness. + * + * @return The comma separated values for the 16-bit value. + */ +#define BT_BYTES_LIST_BE16(_v) (((_v) >> 8) & 0xFFU), (((_v) >> 0) & 0xFFU) + +/** @brief Encode 24-bit value into array values in big-endian format. + * + * Helper macro to encode 24-bit values into comma separated values. + * + * @note @p _v is evaluated 3 times. + * + * @param _v 24-bit integer in host endianness. + * + * @return The comma separated values for the 24-bit value. + */ +#define BT_BYTES_LIST_BE24(_v) (((_v) >> 16) & 0xFFU), BT_BYTES_LIST_BE16(_v) + +/** @brief Encode 32-bit value into array values in big-endian format. + * + * Helper macro to encode 32-bit values into comma separated values. + * + * @note @p _v is evaluated 4 times. + * + * @param _v 32-bit integer in host endianness. + * + * @return The comma separated values for the 32-bit value. + */ +#define BT_BYTES_LIST_BE32(_v) (((_v) >> 24) & 0xFFU), BT_BYTES_LIST_BE24(_v) + +/** @brief Encode 40-bit value into array values in big-endian format. + * + * Helper macro to encode 40-bit values into comma separated values. + * + * @note @p _v is evaluated 5 times. + * + * @param _v 40-bit integer in host endianness. + * + * @return The comma separated values for the 40-bit value. + */ +#define BT_BYTES_LIST_BE40(_v) BT_BYTES_LIST_BE16((_v) >> 24), BT_BYTES_LIST_BE24(_v) + +/** @brief Encode 48-bit value into array values in big-endian format. + * + * Helper macro to encode 48-bit values into comma separated values. + * + * @note @p _v is evaluated 6 times. + * + * @param _v 48-bit integer in host endianness. + * + * @return The comma separated values for the 48-bit value. + */ +#define BT_BYTES_LIST_BE48(_v) BT_BYTES_LIST_BE16((_v) >> 32), BT_BYTES_LIST_BE32(_v) + +/** @brief Encode 64-bit value into array values in big-endian format. + * + * Helper macro to encode 64-bit values into comma separated values. + * + * @note @p _v is evaluated 8 times. + * + * @param _v 64-bit integer in host endianness. + * + * @return The comma separated values for the 64-bit value. + */ +#define BT_BYTES_LIST_BE64(_v) BT_BYTES_LIST_BE32((_v) >> 32), BT_BYTES_LIST_BE32(_v) + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/avrcp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/avrcp.h new file mode 100644 index 00000000..4c422570 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/avrcp.h @@ -0,0 +1,127 @@ +/** @file + * @brief Audio Video Remote Control Profile header. + */ + +/* + * Copyright (c) 2015-2016 Intel Corporation + * Copyright (C) 2024 Xiaomi Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_AVRCP_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_AVRCP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief AVRCP structure */ +struct bt_avrcp; + +struct bt_avrcp_unit_info_rsp { + uint8_t unit_type; + uint32_t company_id; +}; + +struct bt_avrcp_subunit_info_rsp { + uint8_t subunit_type; + uint8_t max_subunit_id; + const uint8_t *extended_subunit_type; /**< contains max_subunit_id items */ + const uint8_t *extended_subunit_id; /**< contains max_subunit_id items */ +}; + +struct bt_avrcp_cb { + /** @brief An AVRCP connection has been established. + * + * This callback notifies the application of an avrcp connection, + * i.e., an AVCTP L2CAP connection. + * + * @param avrcp AVRCP connection object. + */ + void (*connected)(struct bt_avrcp *avrcp); + /** @brief An AVRCP connection has been disconnected. + * + * This callback notifies the application that an avrcp connection + * has been disconnected. + * + * @param avrcp AVRCP connection object. + */ + void (*disconnected)(struct bt_avrcp *avrcp); + /** @brief Callback function for bt_avrcp_get_unit_info(). + * + * Called when the get unit info process is completed. + * + * @param avrcp AVRCP connection object. + * @param rsp The response for UNIT INFO command. + */ + void (*unit_info_rsp)(struct bt_avrcp *avrcp, struct bt_avrcp_unit_info_rsp *rsp); + /** @brief Callback function for bt_avrcp_get_subunit_info(). + * + * Called when the get subunit info process is completed. + * + * @param avrcp AVRCP connection object. + * @param rsp The response for SUBUNIT INFO command. + */ + void (*subunit_info_rsp)(struct bt_avrcp *avrcp, struct bt_avrcp_subunit_info_rsp *rsp); +}; + +/** @brief Connect AVRCP. + * + * This function is to be called after the conn parameter is obtained by + * performing a GAP procedure. The API is to be used to establish AVRCP + * connection between devices. + * + * @param conn Pointer to bt_conn structure. + * + * @return pointer to struct bt_avrcp in case of success or NULL in case + * of error. + */ +struct bt_avrcp *bt_avrcp_connect(struct bt_conn *conn); + +/** @brief Disconnect AVRCP. + * + * This function close AVCTP L2CAP connection. + * + * @param avrcp The AVRCP instance. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_disconnect(struct bt_avrcp *avrcp); + +/** @brief Register callback. + * + * Register AVRCP callbacks to monitor the state and interact with the remote device. + * + * @param cb The callback function. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_register_cb(const struct bt_avrcp_cb *cb); + +/** @brief Get AVRCP Unit Info. + * + * This function obtains information that pertains to the AV/C unit as a whole. + * + * @param avrcp The AVRCP instance. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp); + +/** @brief Get AVRCP Subunit Info. + * + * This function obtains information about the subunit(s) of an AV/C unit. A device with AVRCP + * may support other subunits than the panel subunit if other profiles co-exist in the device. + * + * @param avrcp The AVRCP instance. + * + * @return 0 in case of success or error code in case of error. + */ +int bt_avrcp_get_subunit_info(struct bt_avrcp *avrcp); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_AVRCP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/classic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/classic.h new file mode 100644 index 00000000..be7cf8dc --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/classic.h @@ -0,0 +1,210 @@ +/** @file + * @brief Bluetooth subsystem classic core APIs. + */ + +/* + * Copyright (c) 2015-2016 Intel Corporation + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_CLASSIC_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_CLASSIC_H_ + +/** + * @brief Bluetooth APIs + * @defgroup bluetooth Bluetooth APIs + * @ingroup connectivity + * @{ + */ + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Generic Access Profile (GAP) + * @defgroup bt_gap Generic Access Profile (GAP) + * @since 1.0 + * @version 1.0.0 + * @ingroup bluetooth + * @{ + */ + +/** + * @private + * @brief BR/EDR discovery private structure + */ +struct bt_br_discovery_priv { + /** Clock offset */ + uint16_t clock_offset; + /** Page scan repetition mode */ + uint8_t pscan_rep_mode; + /** Resolving remote name*/ + bool resolving; +}; + +/** @brief BR/EDR discovery result structure */ +struct bt_br_discovery_result { + /** Private data */ + struct bt_br_discovery_priv _priv; + + /** Remote device address */ + bt_addr_t addr; + + /** RSSI from inquiry */ + int8_t rssi; + + /** Class of Device */ + uint8_t cod[3]; + + /** Extended Inquiry Response */ + uint8_t eir[240]; +}; + +/** BR/EDR discovery parameters */ +struct bt_br_discovery_param { + /** Maximum length of the discovery in units of 1.28 seconds. + * Valid range is 0x01 - 0x30. + */ + uint8_t length; + + /** True if limited discovery procedure is to be used. */ + bool limited; +}; + +/** + * @brief Start BR/EDR discovery + * + * Start BR/EDR discovery (inquiry) and provide results through the specified + * callback. The discovery results will be notified through callbacks + * registered by @ref bt_br_discovery_cb_register. + * If more inquiry results were received during session than + * fits in provided result storage, only ones with highest RSSI will be + * reported. + * + * @param param Discovery parameters. + * @param results Storage for discovery results. + * @param count Number of results in storage. Valid range: 1-255. + * + * @return Zero on success or error code otherwise, positive in case + * of protocol error or negative (POSIX) in case of stack internal error + */ +int bt_br_discovery_start(const struct bt_br_discovery_param *param, + struct bt_br_discovery_result *results, size_t count); + +/** + * @brief Stop BR/EDR discovery. + * + * Stops ongoing BR/EDR discovery. If discovery was stopped by this call + * results won't be reported + * + * @return Zero on success or error code otherwise, positive in case of + * protocol error or negative (POSIX) in case of stack internal error. + */ +int bt_br_discovery_stop(void); + +struct bt_br_discovery_cb { + + /** + * @brief An inquiry response received callback. + * + * @param result Storage used for discovery results + */ + void (*recv)(const struct bt_br_discovery_result *result); + + /** @brief The inquiry has stopped after discovery timeout. + * + * @param results Storage used for discovery results + * @param count Number of valid discovery results. + */ + void (*timeout)(const struct bt_br_discovery_result *results, + size_t count); + + sys_snode_t node; +}; + +/** + * @brief Register discovery packet callbacks. + * + * Adds the callback structure to the list of callback structures that monitors + * inquiry activity. + * + * This callback will be called for all inquiry activity, regardless of what + * API was used to start the discovery. + * + * @param cb Callback struct. Must point to memory that remains valid. + */ +void bt_br_discovery_cb_register(struct bt_br_discovery_cb *cb); + +/** + * @brief Unregister discovery packet callbacks. + * + * Remove the callback structure from the list of discovery callbacks. + * + * @param cb Callback struct. Must point to memory that remains valid. + */ +void bt_br_discovery_cb_unregister(struct bt_br_discovery_cb *cb); + +struct bt_br_oob { + /** BR/EDR address. */ + bt_addr_t addr; +}; + +/** + * @brief Get BR/EDR local Out Of Band information + * + * This function allows to get local controller information that are useful + * for Out Of Band pairing or connection creation process. + * + * @param oob Out Of Band information + */ +int bt_br_oob_get_local(struct bt_br_oob *oob); + +/** + * @brief Enable/disable set controller in discoverable state. + * + * Allows make local controller to listen on INQUIRY SCAN channel and responds + * to devices making general inquiry. To enable this state it's mandatory + * to first be in connectable state. + * + * @param enable Value allowing/disallowing controller to become discoverable. + * + * @return Negative if fail set to requested state or requested state has been + * already set. Zero if done successfully. + */ +int bt_br_set_discoverable(bool enable); + +/** + * @brief Enable/disable set controller in connectable state. + * + * Allows make local controller to be connectable. It means the controller + * start listen to devices requests on PAGE SCAN channel. If disabled also + * resets discoverability if was set. + * + * @param enable Value allowing/disallowing controller to be connectable. + * + * @return Negative if fail set to requested state or requested state has been + * already set. Zero if done successfully. + */ +int bt_br_set_connectable(bool enable); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_CLASSIC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/sdp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/sdp.h index 686c0e71..ac0f9d2a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/sdp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/classic/sdp.h @@ -481,8 +481,6 @@ struct bt_sdp_client_result { struct net_buf *resp_buf; /** flag pointing that there are more result chunks for given UUID */ bool next_record_hint; - /** Reference to UUID object on behalf one discovery was started */ - const struct bt_uuid *uuid; }; /** @brief Helper enum to be used as return value of bt_sdp_discover_func_t. @@ -493,6 +491,8 @@ enum { BT_SDP_DISCOVER_UUID_CONTINUE, }; +struct bt_sdp_discover_params; + /** @typedef bt_sdp_discover_func_t * * @brief Callback type reporting to user that there is a resolved result @@ -514,24 +514,41 @@ enum { * * @param conn Connection object identifying connection to queried remote. * @param result Object pointing to logical unparsed SDP record collected on - * base of response driven by given UUID. + * base of response driven by given discover params. + * @param params Discover parameters. * * @return BT_SDP_DISCOVER_UUID_STOP in case of no more need to read next * record data and continue discovery for given UUID. By returning - * BT_SDP_DISCOVER_UUID_CONTINUE user allows this discovery continuation. + * @return BT_SDP_DISCOVER_UUID_CONTINUE user allows this discovery continuation. */ -typedef uint8_t (*bt_sdp_discover_func_t) - (struct bt_conn *conn, struct bt_sdp_client_result *result); +typedef uint8_t (*bt_sdp_discover_func_t)(struct bt_conn *conn, struct bt_sdp_client_result *result, + const struct bt_sdp_discover_params *params); + +/** SDP Discover types */ +enum { + /** Discover Service Search. */ + BT_SDP_DISCOVER_SERVICE_SEARCH, + /** Discover Service Attribute. */ + BT_SDP_DISCOVER_SERVICE_ATTR, + /** Discover Service Search Attribute. */ + BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR, +}; /** @brief Main user structure used in SDP discovery of remote. */ struct bt_sdp_discover_params { - sys_snode_t _node; - /** UUID (service) to be discovered on remote SDP entity */ - const struct bt_uuid *uuid; + sys_snode_t _node; + union { + /** UUID (service) to be discovered on remote SDP entity */ + const struct bt_uuid *uuid; + /** Service record handle */ + uint32_t handle; + }; /** Discover callback to be called on resolved SDP record */ - bt_sdp_discover_func_t func; + bt_sdp_discover_func_t func; /** Memory buffer enabled by user for SDP query results */ - struct net_buf_pool *pool; + struct net_buf_pool *pool; + /** Discover type */ + uint8_t type; }; /** @brief Allows user to start SDP discovery session. @@ -543,6 +560,21 @@ struct bt_sdp_discover_params { * On the service discovery completion the callback function will be * called to get feedback to user about findings. * + * Service Search: The SDP Client generates an + * SDP_SERVICE_SEARCH_REQ to locate service + * records that match the service search + * pattern (`params->uuid`) given as the first + * parameter of the PDU. + * Service Attribute: The SDP Client generates an + * SDP_SERVICE_ATTR_REQ to retrieve specified + * attribute values from a specific service + * record (`params->handle`). + * Service Search Attribute: The SDP Client generates an + * SDP_SERVICE_SEARCH_ATTR_REQ to retrieve + * specified attribute values that match the + * service search pattern (`params->uuid`) + * given as the first parameter of the PDU. + * * @param conn Object identifying connection to remote. * @param params SDP discovery parameters. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/conn.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/conn.h index 5a5525df..73a14b09 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/conn.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/conn.h @@ -74,9 +74,9 @@ struct bt_le_conn_param { * Latency: 0 * Timeout: 4 s */ -#define BT_LE_CONN_PARAM_DEFAULT BT_LE_CONN_PARAM(BT_GAP_INIT_CONN_INT_MIN, \ - BT_GAP_INIT_CONN_INT_MAX, \ - 0, 400) +#define BT_LE_CONN_PARAM_DEFAULT \ + BT_LE_CONN_PARAM(BT_GAP_INIT_CONN_INT_MIN, BT_GAP_INIT_CONN_INT_MAX, 0, \ + BT_GAP_MS_TO_CONN_TIMEOUT(4000)) /** Connection PHY information for LE connections */ struct bt_conn_le_phy_info { @@ -196,6 +196,57 @@ struct bt_conn_le_data_len_param { BT_CONN_LE_DATA_LEN_PARAM(BT_GAP_DATA_LEN_MAX, \ BT_GAP_DATA_TIME_MAX) +/** Connection subrating parameters for LE connections */ +struct bt_conn_le_subrate_param { + /** Minimum subrate factor. */ + uint16_t subrate_min; + /** Maximum subrate factor. */ + uint16_t subrate_max; + /** Maximum Peripheral latency in units of subrated connection intervals. */ + uint16_t max_latency; + /** Minimum number of underlying connection events to remain active + * after a packet containing a Link Layer PDU with a non-zero Length + * field is sent or received. + */ + uint16_t continuation_number; + /** Connection Supervision timeout (N * 10 ms). + * If using @ref bt_conn_le_subrate_set_defaults, this is the + * maximum supervision timeout allowed in requests by a peripheral. + */ + uint16_t supervision_timeout; +}; + +/** Subrating information for LE connections */ +struct bt_conn_le_subrating_info { + /** Connection subrate factor. */ + uint16_t factor; + /** Number of underlying connection events to remain active after + * a packet containing a Link Layer PDU with a non-zero Length + * field is sent or received. + */ + uint16_t continuation_number; +}; + +/** Updated subrating connection parameters for LE connections */ +struct bt_conn_le_subrate_changed { + /** HCI Status from LE Subrate Changed event. + * The remaining parameters will be unchanged if status is not + * BT_HCI_ERR_SUCCESS. + */ + uint8_t status; + /** Connection subrate factor. */ + uint16_t factor; + /** Number of underlying connection events to remain active after + * a packet containing a Link Layer PDU with a non-zero Length + * field is sent or received. + */ + uint16_t continuation_number; + /** Peripheral latency in units of subrated connection intervals. */ + uint16_t peripheral_latency; + /** Connection Supervision timeout (N * 10 ms). */ + uint16_t supervision_timeout; +}; + /** Connection Type */ enum __packed bt_conn_type { /** LE Connection Type */ @@ -211,6 +262,407 @@ enum __packed bt_conn_type { BT_CONN_TYPE_SCO | BT_CONN_TYPE_ISO, }; +/** Supported AA-Only RTT precision. */ +enum bt_conn_le_cs_capability_rtt_aa_only { + /** AA-Only RTT variant is not supported. */ + BT_CONN_LE_CS_RTT_AA_ONLY_NOT_SUPP = 0, + /** 10ns time-of-flight accuracy. */ + BT_CONN_LE_CS_RTT_AA_ONLY_10NS, + /** 150ns time-of-flight accuracy. */ + BT_CONN_LE_CS_RTT_AA_ONLY_150NS, +}; + +/** Supported Sounding Sequence RTT precision. */ +enum bt_conn_le_cs_capability_rtt_sounding { + /** Sounding Sequence RTT variant is not supported. */ + BT_CONN_LE_CS_RTT_SOUNDING_NOT_SUPP = 0, + /** 10ns time-of-flight accuracy. */ + BT_CONN_LE_CS_RTT_SOUNDING_10NS, + /** 150ns time-of-flight accuracy. */ + BT_CONN_LE_CS_RTT_SOUNDING_150NS, +}; + +/** Supported Random Payload RTT precision. */ +enum bt_conn_le_cs_capability_rtt_random_payload { + /** Random Payload RTT variant is not supported. */ + BT_CONN_LE_CS_RTT_RANDOM_PAYLOAD_NOT_SUPP = 0, + /** 10ns time-of-flight accuracy. */ + BT_CONN_LE_CS_RTT_RANDOM_PAYLOAD_10NS, + /** 150ns time-of-flight accuracy. */ + BT_CONN_LE_CS_RTT_RANDOM_PAYLOAD_150NS, +}; + +/** Remote channel sounding capabilities for LE connections supporting CS */ +struct bt_conn_le_cs_capabilities { + /** Number of CS configurations */ + uint8_t num_config_supported; + /** Maximum number of consecutive CS procedures. + * + * When set to zero, indicates support for both fixed and indefinite + * numbers of CS procedures before termination. + */ + uint16_t max_consecutive_procedures_supported; + /** Number of antennas. */ + uint8_t num_antennas_supported; + /** Maximum number of antenna paths. */ + uint8_t max_antenna_paths_supported; + /** Initiator role. */ + bool initiator_supported; + /** Reflector role. */ + bool reflector_supported; + /** Mode-3 */ + bool mode_3_supported; + /** RTT AA-Only */ + enum bt_conn_le_cs_capability_rtt_aa_only rtt_aa_only_precision; + /** RTT Sounding */ + enum bt_conn_le_cs_capability_rtt_sounding rtt_sounding_precision; + /** RTT Random Payload */ + enum bt_conn_le_cs_capability_rtt_random_payload rtt_random_payload_precision; + /** Number of CS steps needed to achieve the + * accuracy requirements for RTT AA Only. + * + * Set to 0 if RTT AA Only isn't supported. + */ + uint8_t rtt_aa_only_n; + /** Number of CS steps needed to achieve the + * accuracy requirements for RTT Sounding. + * + * Set to 0 if RTT Sounding isn't supported + */ + uint8_t rtt_sounding_n; + /** Number of CS steps needed to achieve the + * accuracy requirements for RTT Random Payload. + * + * Set to 0 if RTT Random Payload isn't supported. + */ + uint8_t rtt_random_payload_n; + /** Phase-based normalized attack detector metric + * when a CS_SYNC with sounding sequence is received. + */ + bool phase_based_nadm_sounding_supported; + /** Phase-based normalized attack detector metric + * when a CS_SYNC with random sequence is received. + */ + bool phase_based_nadm_random_supported; + /** CS_SYNC LE 2M PHY. */ + bool cs_sync_2m_phy_supported; + /** CS_SYNC LE 2M 2BT PHY. */ + bool cs_sync_2m_2bt_phy_supported; + /** Subfeature: CS with no Frequency Actuation Error. */ + bool cs_without_fae_supported; + /** Subfeature: Channel Selection Algorithm #3c */ + bool chsel_alg_3c_supported; + /** Subfeature: Phase-based Ranging from RTT sounding sequence. */ + bool pbr_from_rtt_sounding_seq_supported; + /** Optional T_IP1 time durations during CS steps. + * + * - Bit 0: 10 us + * - Bit 1: 20 us + * - Bit 2: 30 us + * - Bit 3: 40 us + * - Bit 4: 50 us + * - Bit 5: 60 us + * - Bit 6: 80 us + */ + uint16_t t_ip1_times_supported; + /** Optional T_IP2 time durations during CS steps. + * + * - Bit 0: 10 us + * - Bit 1: 20 us + * - Bit 2: 30 us + * - Bit 3: 40 us + * - Bit 4: 50 us + * - Bit 5: 60 us + * - Bit 6: 80 us + */ + uint16_t t_ip2_times_supported; + /** Optional T_FCS time durations during CS steps. + * + * - Bit 0: 15 us + * - Bit 1: 20 us + * - Bit 2: 30 us + * - Bit 3: 40 us + * - Bit 4: 50 us + * - Bit 5: 60 us + * - Bit 6: 80 us + * - Bit 7: 100 us + * - Bit 8: 120 us + */ + uint16_t t_fcs_times_supported; + /** Optional T_PM time durations during CS steps. + * + * - Bit 0: 10 us + * - Bit 1: 20 us + */ + uint16_t t_pm_times_supported; + /** Time in microseconds for the antenna switch period of the CS tones. */ + uint8_t t_sw_time; + /** Supported SNR levels used in RTT packets. + * + * - Bit 0: 18dB + * - Bit 1: 21dB + * - Bit 2: 24dB + * - Bit 3: 27dB + * - Bit 4: 30dB + */ + uint8_t tx_snr_capability; +}; + +/** Remote FAE Table for LE connections supporting CS */ +struct bt_conn_le_cs_fae_table { + int8_t *remote_fae_table; +}; + +/** Channel sounding main mode */ +enum bt_conn_le_cs_main_mode { + /** Mode-1 (RTT) */ + BT_CONN_LE_CS_MAIN_MODE_1 = BT_HCI_OP_LE_CS_MAIN_MODE_1, + /** Mode-2 (PBR) */ + BT_CONN_LE_CS_MAIN_MODE_2 = BT_HCI_OP_LE_CS_MAIN_MODE_2, + /** Mode-3 (RTT and PBR) */ + BT_CONN_LE_CS_MAIN_MODE_3 = BT_HCI_OP_LE_CS_MAIN_MODE_3, +}; + +/** Channel sounding sub mode */ +enum bt_conn_le_cs_sub_mode { + /** Unused */ + BT_CONN_LE_CS_SUB_MODE_UNUSED = BT_HCI_OP_LE_CS_SUB_MODE_UNUSED, + /** Mode-1 (RTT) */ + BT_CONN_LE_CS_SUB_MODE_1 = BT_HCI_OP_LE_CS_SUB_MODE_1, + /** Mode-2 (PBR) */ + BT_CONN_LE_CS_SUB_MODE_2 = BT_HCI_OP_LE_CS_SUB_MODE_2, + /** Mode-3 (RTT and PBR) */ + BT_CONN_LE_CS_SUB_MODE_3 = BT_HCI_OP_LE_CS_SUB_MODE_3, +}; + +/** Channel sounding role */ +enum bt_conn_le_cs_role { + /** CS initiator role */ + BT_CONN_LE_CS_ROLE_INITIATOR, + /** CS reflector role */ + BT_CONN_LE_CS_ROLE_REFLECTOR, +}; + +/** Channel sounding RTT type */ +enum bt_conn_le_cs_rtt_type { + /** RTT AA only */ + BT_CONN_LE_CS_RTT_TYPE_AA_ONLY = BT_HCI_OP_LE_CS_RTT_TYPE_AA_ONLY, + /** RTT with 32-bit sounding sequence */ + BT_CONN_LE_CS_RTT_TYPE_32_BIT_SOUNDING = BT_HCI_OP_LE_CS_RTT_TYPE_32BIT_SOUND, + /** RTT with 96-bit sounding sequence */ + BT_CONN_LE_CS_RTT_TYPE_96_BIT_SOUNDING = BT_HCI_OP_LE_CS_RTT_TYPE_96BIT_SOUND, + /** RTT with 32-bit random sequence */ + BT_CONN_LE_CS_RTT_TYPE_32_BIT_RANDOM = BT_HCI_OP_LE_CS_RTT_TYPE_32BIT_RAND, + /** RTT with 64-bit random sequence */ + BT_CONN_LE_CS_RTT_TYPE_64_BIT_RANDOM = BT_HCI_OP_LE_CS_RTT_TYPE_64BIT_RAND, + /** RTT with 96-bit random sequence */ + BT_CONN_LE_CS_RTT_TYPE_96_BIT_RANDOM = BT_HCI_OP_LE_CS_RTT_TYPE_96BIT_RAND, + /** RTT with 128-bit random sequence */ + BT_CONN_LE_CS_RTT_TYPE_128_BIT_RANDOM = BT_HCI_OP_LE_CS_RTT_TYPE_128BIT_RAND, +}; + +/** Channel sounding PHY used for CS sync */ +enum bt_conn_le_cs_sync_phy { + /** LE 1M PHY */ + BT_CONN_LE_CS_SYNC_1M_PHY = BT_HCI_OP_LE_CS_CS_SYNC_1M, + /** LE 2M PHY */ + BT_CONN_LE_CS_SYNC_2M_PHY = BT_HCI_OP_LE_CS_CS_SYNC_2M, + /** LE 2M 2BT PHY */ + BT_CONN_LE_CS_SYNC_2M_2BT_PHY = BT_HCI_OP_LE_CS_CS_SYNC_2M_2BT, +}; + +/** Channel sounding channel selection type */ +enum bt_conn_le_cs_chsel_type { + /** Use Channel Selection Algorithm #3b for non-mode-0 CS steps */ + BT_CONN_LE_CS_CHSEL_TYPE_3B = BT_HCI_OP_LE_CS_TEST_CHSEL_TYPE_3B, + /** Use Channel Selection Algorithm #3c for non-mode-0 CS steps */ + BT_CONN_LE_CS_CHSEL_TYPE_3C = BT_HCI_OP_LE_CS_TEST_CHSEL_TYPE_3C, +}; + +/** Channel sounding channel sequence shape */ +enum bt_conn_le_cs_ch3c_shape { + /** Use Hat shape for user-specified channel sequence */ + BT_CONN_LE_CS_CH3C_SHAPE_HAT = BT_HCI_OP_LE_CS_TEST_CH3C_SHAPE_HAT, + /** Use X shape for user-specified channel sequence */ + BT_CONN_LE_CS_CH3C_SHAPE_X = BT_HCI_OP_LE_CS_TEST_CH3C_SHAPE_X, +}; + +/** Channel sounding configuration */ +struct bt_conn_le_cs_config { + /** CS configuration ID */ + uint8_t id; + /** Main CS mode type */ + enum bt_conn_le_cs_main_mode main_mode_type; + /** Sub CS mode type */ + enum bt_conn_le_cs_sub_mode sub_mode_type; + /** Minimum number of CS main mode steps to be executed before a submode step is executed */ + uint8_t min_main_mode_steps; + /** Maximum number of CS main mode steps to be executed before a submode step is executed */ + uint8_t max_main_mode_steps; + /** Number of main mode steps taken from the end of the last CS subevent to be repeated + * at the beginning of the current CS subevent directly after the last mode-0 step of that + * event + */ + uint8_t main_mode_repetition; + /** Number of CS mode-0 steps to be included at the beginning of each CS subevent */ + uint8_t mode_0_steps; + /** CS role */ + enum bt_conn_le_cs_role role; + /** RTT type */ + enum bt_conn_le_cs_rtt_type rtt_type; + /** CS Sync PHY */ + enum bt_conn_le_cs_sync_phy cs_sync_phy; + /** The number of times the Channel_Map field will be cycled through for non-mode-0 steps + * within a CS procedure + */ + uint8_t channel_map_repetition; + /** Channel selection type */ + enum bt_conn_le_cs_chsel_type channel_selection_type; + /** User-specified channel sequence shape */ + enum bt_conn_le_cs_ch3c_shape ch3c_shape; + /** Number of channels skipped in each rising and falling sequence */ + uint8_t ch3c_jump; + /** Interlude time in microseconds between the RTT packets */ + uint8_t t_ip1_time_us; + /** Interlude time in microseconds between the CS tones */ + uint8_t t_ip2_time_us; + /** Time in microseconds for frequency changes */ + uint8_t t_fcs_time_us; + /** Time in microseconds for the phase measurement period of the CS tones */ + uint8_t t_pm_time_us; + /** Channel map used for CS procedure + * Channels n = 0, 1, 23, 24, 25, 77, and 78 are not allowed and shall be set to zero. + * Channel 79 is reserved for future use and shall be set to zero. + * At least 15 channels shall be enabled. + */ + uint8_t channel_map[10]; +}; + +/** Procedure done status */ +enum bt_conn_le_cs_procedure_done_status { + BT_CONN_LE_CS_PROCEDURE_COMPLETE = BT_HCI_LE_CS_PROCEDURE_DONE_STATUS_COMPLETE, + BT_CONN_LE_CS_PROCEDURE_INCOMPLETE = BT_HCI_LE_CS_PROCEDURE_DONE_STATUS_PARTIAL, + BT_CONN_LE_CS_PROCEDURE_ABORTED = BT_HCI_LE_CS_PROCEDURE_DONE_STATUS_ABORTED, +}; + +/** Subevent done status */ +enum bt_conn_le_cs_subevent_done_status { + BT_CONN_LE_CS_SUBEVENT_COMPLETE = BT_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE, + BT_CONN_LE_CS_SUBEVENT_ABORTED = BT_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED, +}; + +/** Procedure abort reason */ +enum bt_conn_le_cs_procedure_abort_reason { + BT_CONN_LE_CS_PROCEDURE_NOT_ABORTED = BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_NO_ABORT, + BT_CONN_LE_CS_PROCEDURE_ABORT_REQUESTED = + BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_LOCAL_HOST_OR_REMOTE_REQUEST, + BT_CONN_LE_CS_PROCEDURE_ABORT_TOO_FEW_CHANNELS = + BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_TOO_FEW_CHANNELS, + BT_CONN_LE_CS_PROCEDURE_ABORT_CHMAP_INSTANT_PASSED = + BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_CHMAP_INSTANT_PASSED, + BT_CONN_LE_CS_PROCEDURE_ABORT_UNSPECIFIED = BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_UNSPECIFIED, +}; + +/** Subevent abort reason */ +enum bt_conn_le_cs_subevent_abort_reason { + BT_CONN_LE_CS_SUBEVENT_NOT_ABORTED = BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_NO_ABORT, + BT_CONN_LE_CS_SUBEVENT_ABORT_REQUESTED = + BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_LOCAL_HOST_OR_REMOTE_REQUEST, + BT_CONN_LE_CS_SUBEVENT_ABORT_NO_CS_SYNC = + BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_NO_CS_SYNC_RECEIVED, + BT_CONN_LE_CS_SUBEVENT_ABORT_SCHED_CONFLICT = + BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_SCHED_CONFLICT, + BT_CONN_LE_CS_SUBEVENT_ABORT_UNSPECIFIED = BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_UNSPECIFIED, +}; + +/** Subevent data for LE connections supporting CS */ +struct bt_conn_le_cs_subevent_result { + struct { + /** CS configuration identifier. + * + * Range: 0 to 3 + * + * If these results were generated by a CS Test, + * this value will be set to 0 and has no meaning. + */ + uint8_t config_id; + /** Starting ACL connection event counter. + * + * If these results were generated by a CS Test, + * this value will be set to 0 and has no meaning. + */ + uint16_t start_acl_conn_event; + /** CS procedure count associated with these results. + * + * This is the CS procedure count since the completion of + * the Channel Sounding Security Start procedure. + */ + uint16_t procedure_counter; + /** Frequency compensation value in units of 0.01 ppm. + * + * This is a 15-bit signed integer in the range [-100, 100] ppm. + * + * A value of @ref BT_HCI_LE_CS_SUBEVENT_RESULT_FREQ_COMPENSATION_NOT_AVAILABLE + * indicates that the role is not the initiator, or that the + * frequency compensation value is unavailable. + */ + uint16_t frequency_compensation; + /** Reference power level in dBm. + * + * Range: -127 to 20 + * + * A value of @ref BT_HCI_LE_CS_REF_POWER_LEVEL_UNAVAILABLE indicates + * that the reference power level was not available during a subevent. + */ + int8_t reference_power_level; + /** Procedure status. */ + enum bt_conn_le_cs_procedure_done_status procedure_done_status; + /** Subevent status + * + * For aborted subevents, this will be set to @ref BT_CONN_LE_CS_SUBEVENT_ABORTED + * and abort_step will contain the step number on which the subevent was aborted. + * Consider the following example: + * + * subevent_done_status = @ref BT_CONN_LE_CS_SUBEVENT_ABORTED + * num_steps_reported = 160 + * abort_step = 100 + * + * this would mean that steps from 0 to 99 are complete and steps from 100 to 159 + * are aborted. + */ + enum bt_conn_le_cs_subevent_done_status subevent_done_status; + /** Abort reason. + * + * If the procedure status is + * @ref BT_CONN_LE_CS_PROCEDURE_ABORTED, this field will + * specify the reason for the abortion. + */ + enum bt_conn_le_cs_procedure_abort_reason procedure_abort_reason; + /** Abort reason. + * + * If the subevent status is + * @ref BT_CONN_LE_CS_SUBEVENT_ABORTED, this field will + * specify the reason for the abortion. + */ + enum bt_conn_le_cs_subevent_abort_reason subevent_abort_reason; + /** Number of antenna paths used during the phase measurement stage. + */ + uint8_t num_antenna_paths; + /** Number of CS steps in the subevent. + */ + uint8_t num_steps_reported; + /** Step number, on which the subevent was aborted + * if subevent_done_status is @ref BT_CONN_LE_CS_SUBEVENT_COMPLETE + * then abort_step will be unused and set to 255 + */ + uint8_t abort_step; + } header; + /** Pointer to buffer containing step data. + * NULL if num_steps_reported is 0. + */ + struct net_buf_simple *step_data_buf; +}; + /** @brief Increment a connection's reference count. * * Increment the reference count of a connection object. @@ -310,6 +762,11 @@ struct bt_conn_le_info { /* Connection maximum single fragment parameters */ const struct bt_conn_le_data_len_info *data_len; #endif /* defined(CONFIG_BT_USER_DATA_LEN_UPDATE) */ + +#if defined(CONFIG_BT_SUBRATING) + /* Connection subrating parameters */ + const struct bt_conn_le_subrating_info *subrate; +#endif /* defined(CONFIG_BT_SUBRATING) */ }; /** @brief Convert connection interval to milliseconds @@ -676,6 +1133,36 @@ int bt_conn_le_set_path_loss_mon_param(struct bt_conn *conn, */ int bt_conn_le_set_path_loss_mon_enable(struct bt_conn *conn, bool enable); +/** @brief Set Default Connection Subrating Parameters. + * + * Change the default subrating parameters for all future + * ACL connections where the local device is the central. + * This command does not affect any existing connection. + * Parameters set for specific connection will always have precedence. + * + * @note To use this API @kconfig{CONFIG_BT_SUBRATING} and + * @kconfig{CONFIG_BT_CENTRAL} must be set. + * + * @param params Subrating parameters. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_conn_le_subrate_set_defaults(const struct bt_conn_le_subrate_param *params); + +/** @brief Request New Subrating Parameters. + * + * Request a change to the subrating parameters of a connection. + * + * @note To use this API @kconfig{CONFIG_BT_SUBRATING} must be set. + * + * @param conn Connection object. + * @param params Subrating parameters. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_conn_le_subrate_request(struct bt_conn *conn, + const struct bt_conn_le_subrate_param *params); + /** @brief Update the connection parameters. * * If the local device is in the peripheral role then updating the connection @@ -761,10 +1248,24 @@ struct bt_conn_le_create_param { /** Bit-field of create connection options. */ uint32_t options; - /** Scan interval (N * 0.625 ms) */ + /** Scan interval (N * 0.625 ms) + * + * @note When @kconfig{CONFIG_BT_SCAN_AND_INITIATE_IN_PARALLEL} is enabled + * and the application wants to scan and connect in parallel, + * the Bluetooth Controller may require the scan interval used + * for scanning and connection establishment to be equal to + * obtain the best performance. + */ uint16_t interval; - /** Scan window (N * 0.625 ms) */ + /** Scan window (N * 0.625 ms) + * + * @note When @kconfig{CONFIG_BT_SCAN_AND_INITIATE_IN_PARALLEL} is enabled + * and the application wants to scan and connect in parallel, + * the Bluetooth Controller may require the scan window used + * for scanning and connection establishment to be equal to + * obtain the best performance. + */ uint16_t window; /** @brief Scan interval LE Coded PHY (N * 0.625 MS) @@ -838,7 +1339,9 @@ struct bt_conn_le_create_param { * Allows initiate new LE link to remote peer using its address. * * The caller gets a new reference to the connection object which must be - * released with bt_conn_unref() once done using the object. + * released with bt_conn_unref() once done using the object. If + * @kconfig{CONFIG_BT_CONN_CHECK_NULL_BEFORE_CREATE} is enabled, this function + * will return -EINVAL if dereferenced @p conn is not NULL. * * This uses the General Connection Establishment procedure. * @@ -877,7 +1380,9 @@ struct bt_conn_le_create_synced_param { * with Responses (PAwR) train. * * The caller gets a new reference to the connection object which must be - * released with bt_conn_unref() once done using the object. + * released with bt_conn_unref() once done using the object. If + * @kconfig{CONFIG_BT_CONN_CHECK_NULL_BEFORE_CREATE} is enabled, this function + * will return -EINVAL if dereferenced @p conn is not NULL. * * This uses the Periodic Advertising Connection Procedure. * @@ -930,8 +1435,8 @@ int bt_conn_create_auto_stop(void); * * @return Zero on success or error code otherwise. */ -int bt_le_set_auto_conn(const bt_addr_le_t *addr, - const struct bt_le_conn_param *param); +__deprecated int bt_le_set_auto_conn(const bt_addr_le_t *addr, + const struct bt_le_conn_param *param); /** @brief Set security level for a connection. * @@ -1020,6 +1525,86 @@ enum bt_security_err { BT_SECURITY_ERR_UNSPECIFIED, }; +enum bt_conn_le_cs_procedure_enable_state { + BT_CONN_LE_CS_PROCEDURES_DISABLED = BT_HCI_OP_LE_CS_PROCEDURES_DISABLED, + BT_CONN_LE_CS_PROCEDURES_ENABLED = BT_HCI_OP_LE_CS_PROCEDURES_ENABLED, +}; + +/** CS Test Tone Antennna Config Selection. + * + * These enum values are indices in the following table, where N_AP is the maximum + * number of antenna paths (in the range [1, 4]). + * + * +--------------+-------------+-------------------+-------------------+--------+ + * | Config Index | Total Paths | Dev A: # Antennas | Dev B: # Antennas | Config | + * +--------------+-------------+-------------------+-------------------+--------+ + * | 0 | 1 | 1 | 1 | 1:1 | + * | 1 | 2 | 2 | 1 | N_AP:1 | + * | 2 | 3 | 3 | 1 | N_AP:1 | + * | 3 | 4 | 4 | 1 | N_AP:1 | + * | 4 | 2 | 1 | 2 | 1:N_AP | + * | 5 | 3 | 1 | 3 | 1:N_AP | + * | 6 | 4 | 1 | 4 | 1:N_AP | + * | 7 | 4 | 2 | 2 | 2:2 | + * +--------------+-------------+-------------------+-------------------+--------+ + * + * There are therefore four groups of possible antenna configurations: + * + * - 1:1 configuration, where both A and B support 1 antenna each + * - 1:N_AP configuration, where A supports 1 antenna, B supports N_AP antennas, and + * N_AP is a value in the range [2, 4] + * - N_AP:1 configuration, where A supports N_AP antennas, B supports 1 antenna, and + * N_AP is a value in the range [2, 4] + * - 2:2 configuration, where both A and B support 2 antennas and N_AP = 4 + */ +enum bt_conn_le_cs_tone_antenna_config_selection { + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_ONE = BT_HCI_OP_LE_CS_ACI_0, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_TWO = BT_HCI_OP_LE_CS_ACI_1, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_THREE = BT_HCI_OP_LE_CS_ACI_2, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_FOUR = BT_HCI_OP_LE_CS_ACI_3, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_FIVE = BT_HCI_OP_LE_CS_ACI_4, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_SIX = BT_HCI_OP_LE_CS_ACI_5, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_SEVEN = BT_HCI_OP_LE_CS_ACI_6, + BT_LE_CS_TONE_ANTENNA_CONFIGURATION_INDEX_EIGHT = BT_HCI_OP_LE_CS_ACI_7, +}; + +struct bt_conn_le_cs_procedure_enable_complete { + /* The ID associated with the desired configuration (0 to 3) */ + uint8_t config_id; + + /* State of the CS procedure */ + enum bt_conn_le_cs_procedure_enable_state state; + + /* Antenna configuration index */ + enum bt_conn_le_cs_tone_antenna_config_selection tone_antenna_config_selection; + + /* Transmit power level used for CS procedures (-127 to 20 dB; 0x7F if unavailable) */ + int8_t selected_tx_power; + + /* Duration of each CS subevent in microseconds (1250 us to 4 s) */ + uint32_t subevent_len; + + /* Number of CS subevents anchored off the same ACL connection event (0x01 to 0x20) */ + uint8_t subevents_per_event; + + /* Time between consecutive CS subevents anchored off the same ACL connection event in + * units of 0.625 ms + */ + uint16_t subevent_interval; + + /* Number of ACL connection events between consecutive CS event anchor points */ + uint16_t event_interval; + + /* Number of ACL connection events between consecutive CS procedure anchor points */ + uint16_t procedure_interval; + + /* Number of CS procedures to be scheduled (0 if procedures to continue until disabled) */ + uint16_t procedure_count; + + /* Maximum duration for each procedure in units of 0.625 ms (0x0001 to 0xFFFF) */ + uint16_t max_procedure_len; +}; + /** @brief Connection callback structure. * * This structure is used for tracking the state of a connection. @@ -1244,6 +1829,97 @@ struct bt_conn_cb { const struct bt_conn_le_path_loss_threshold_report *report); #endif /* CONFIG_BT_PATH_LOSS_MONITORING */ +#if defined(CONFIG_BT_SUBRATING) + /** @brief LE Subrate Changed event. + * + * This callback notifies the application that the subrating parameters + * of the connection may have changed. + * The connection subrating parameters will be unchanged + * if status is not BT_HCI_ERR_SUCCESS. + * + * @param conn Connection object. + * @param params New subrating parameters. + */ + void (*subrate_changed)(struct bt_conn *conn, + const struct bt_conn_le_subrate_changed *params); +#endif /* CONFIG_BT_SUBRATING */ + +#if defined(CONFIG_BT_CHANNEL_SOUNDING) + /** @brief LE CS Read Remote Supported Capabilities Complete event. + * + * This callback notifies the application that the remote channel + * sounding capabilities have been received from the peer. + * + * @param conn Connection object. + * @param remote_cs_capabilities Remote Channel Sounding Capabilities. + */ + void (*le_cs_remote_capabilities_available)(struct bt_conn *conn, + struct bt_conn_le_cs_capabilities *params); + + /** @brief LE CS Read Remote FAE Table Complete event. + * + * This callback notifies the application that the remote mode-0 + * FAE Table has been received from the peer. + * + * @param conn Connection object. + * @param params FAE Table. + */ + void (*le_cs_remote_fae_table_available)(struct bt_conn *conn, + struct bt_conn_le_cs_fae_table *params); + + /** @brief LE CS Config created. + * + * This callback notifies the application that a Channel Sounding + * Configuration procedure has completed and a new CS config is created + * + * @param conn Connection object. + * @param config CS configuration. + */ + void (*le_cs_config_created)(struct bt_conn *conn, struct bt_conn_le_cs_config *config); + + /** @brief LE CS Config removed. + * + * This callback notifies the application that a Channel Sounding + * Configuration procedure has completed and a CS config is removed + * + * @param conn Connection object. + * @param config_id ID of the CS configuration that was removed. + */ + void (*le_cs_config_removed)(struct bt_conn *conn, uint8_t config_id); + + /** @brief Subevent Results from a CS procedure are available. + * + * This callback notifies the user that CS subevent results are + * available for the given connection object. + * + * @param conn Connection objects. + * @param result Subevent results + */ + void (*le_cs_subevent_data_available)(struct bt_conn *conn, + struct bt_conn_le_cs_subevent_result *result); + + /** @brief LE CS Security Enabled. + * + * This callback notifies the application that a Channel Sounding + * Security Enable procedure has completed + * + * @param conn Connection object. + */ + void (*le_cs_security_enabled)(struct bt_conn *conn); + + /** @brief LE CS Procedure Enabled. + * + * This callback notifies the application that a Channel Sounding + * Procedure Enable procedure has completed + * + * @param conn Connection object. + * @param params CS Procedure Enable parameters + */ + void (*le_cs_procedure_enabled)( + struct bt_conn *conn, struct bt_conn_le_cs_procedure_enable_complete *params); + +#endif + /** @internal Internally used field for list handling */ sys_snode_t _node; }; @@ -1311,6 +1987,17 @@ static inline const char *bt_security_err_to_str(enum bt_security_err err) */ void bt_set_bondable(bool enable); +/** @brief Get bonding flag. + * + * Get current bonding flag. + * The initial value of this flag depends on @kconfig{CONFIG_BT_BONDABLE} Kconfig + * setting. + * The Bonding flag can be updated using bt_set_bondable(). + * + * @return Current bonding flag. + */ +bool bt_get_bondable(void); + /** @brief Set/clear the bonding flag for a given connection. * * Set/clear the Bonding flag in the Authentication Requirements of @@ -1511,7 +2198,8 @@ struct bt_conn_auth_cb { * This callback may be unregistered in which case pairing continues * as if the Kconfig flag was not set. * - * This callback is not called for BR/EDR Secure Simple Pairing (SSP). + * For BR/EDR Secure Simple Pairing (SSP), this callback is called + * when receiving the BT_HCI_EVT_IO_CAPA_REQ hci event. * * @param conn Connection where pairing is initiated. * @param feat Pairing req/resp info. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/cs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/cs.h new file mode 100644 index 00000000..6e712627 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/cs.h @@ -0,0 +1,889 @@ +/** @file + * @brief Bluetooth Channel Sounding handling + */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_CS_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_CS_H_ + +/** + * @brief LE Channel Sounding (CS) + * @defgroup bt_le_cs Channel Sounding (CS) + * @ingroup bluetooth + * @{ + */ + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Macro for getting a specific channel bit in CS channel map + * + * @param[in] chmap Channel map array + * @param[in] bit Bit number to be accessed + * + * @return Bit value, either 1 or 0 + */ +#define BT_LE_CS_CHANNEL_BIT_GET(chmap, bit) (((chmap)[(bit) / 8] >> ((bit) % 8)) & 1) + +/** + * @brief Macro for setting a specific channel bit value in CS channel map + * + * @param[in] chmap Channel map array + * @param[in] bit Bit number to be accessed + * @param[in] val Bit value to be set, either 1 or 0 + */ +#define BT_LE_CS_CHANNEL_BIT_SET_VAL(chmap, bit, val) \ + ((chmap)[(bit) / 8] = ((chmap)[(bit) / 8] & ~BIT((bit) % 8)) | ((val) << ((bit) % 8))) + +enum bt_le_cs_sync_antenna_selection_opt { + /** Use antenna identifier 1 for CS_SYNC packets. */ + BT_LE_CS_ANTENNA_SELECTION_OPT_ONE = BT_HCI_OP_LE_CS_ANTENNA_SEL_ONE, + /** Use antenna identifier 2 for CS_SYNC packets. */ + BT_LE_CS_ANTENNA_SELECTION_OPT_TWO = BT_HCI_OP_LE_CS_ANTENNA_SEL_TWO, + /** Use antenna identifier 3 for CS_SYNC packets. */ + BT_LE_CS_ANTENNA_SELECTION_OPT_THREE = BT_HCI_OP_LE_CS_ANTENNA_SEL_THREE, + /** Use antenna identifier 4 for CS_SYNC packets. */ + BT_LE_CS_ANTENNA_SELECTION_OPT_FOUR = BT_HCI_OP_LE_CS_ANTENNA_SEL_FOUR, + /** Use antennas in repetitive order from 1 to 4 for CS_SYNC packets. */ + BT_LE_CS_ANTENNA_SELECTION_OPT_REPETITIVE = BT_HCI_OP_LE_CS_ANTENNA_SEL_REP, + /** No recommendation for local controller antenna selection. */ + BT_LE_CS_ANTENNA_SELECTION_OPT_NO_RECOMMENDATION = BT_HCI_OP_LE_CS_ANTENNA_SEL_NONE, +}; + +/** Default CS settings in the local Controller */ +struct bt_le_cs_set_default_settings_param { + /** Enable CS initiator role. */ + bool enable_initiator_role; + /** Enable CS reflector role. */ + bool enable_reflector_role; + /** Antenna identifier to be used for CS_SYNC packets by the local controller. + */ + enum bt_le_cs_sync_antenna_selection_opt cs_sync_antenna_selection; + /** Maximum output power (Effective Isotropic Radiated Power) to be used + * for all CS transmissions. + * + * Value range is @ref BT_HCI_OP_LE_CS_MIN_MAX_TX_POWER to + * @ref BT_HCI_OP_LE_CS_MAX_MAX_TX_POWER. + */ + int8_t max_tx_power; +}; + +/** CS Test CS_SYNC Antenna Identifier */ +enum bt_le_cs_test_cs_sync_antenna_selection { + BT_LE_CS_TEST_CS_SYNC_ANTENNA_SELECTION_ONE = BT_HCI_OP_LE_CS_ANTENNA_SEL_ONE, + BT_LE_CS_TEST_CS_SYNC_ANTENNA_SELECTION_TWO = BT_HCI_OP_LE_CS_ANTENNA_SEL_TWO, + BT_LE_CS_TEST_CS_SYNC_ANTENNA_SELECTION_THREE = BT_HCI_OP_LE_CS_ANTENNA_SEL_THREE, + BT_LE_CS_TEST_CS_SYNC_ANTENNA_SELECTION_FOUR = BT_HCI_OP_LE_CS_ANTENNA_SEL_FOUR, +}; + +/** CS SNR control options */ +enum bt_le_cs_snr_control { + BT_LE_CS_SNR_CONTROL_18dB = BT_HCI_OP_LE_CS_SNR_18, + BT_LE_CS_SNR_CONTROL_21dB = BT_HCI_OP_LE_CS_SNR_21, + BT_LE_CS_SNR_CONTROL_24dB = BT_HCI_OP_LE_CS_SNR_24, + BT_LE_CS_SNR_CONTROL_27dB = BT_HCI_OP_LE_CS_SNR_27, + BT_LE_CS_SNR_CONTROL_30dB = BT_HCI_OP_LE_CS_SNR_30, + BT_LE_CS_SNR_CONTROL_NOT_USED = BT_HCI_OP_LE_CS_SNR_NOT_USED, +}; + +/** CS Test Override 3 T_PM Tone Extension */ +enum bt_le_cs_test_override_3_pm_tone_ext { + /** Initiator and reflector tones sent without tone extension */ + BT_LE_CS_TEST_OVERRIDE_3_NO_TONE_EXT = BT_HCI_OP_LE_CS_TEST_TONE_EXT_NONE, + /** Initiator tone sent with extension, reflector tone sent without tone extension */ + BT_LE_CS_TEST_OVERRIDE_3_INITIATOR_TONE_EXT_ONLY = BT_HCI_OP_LE_CS_TEST_TONE_EXT_INIT, + /** Initiator tone sent without extension, reflector tone sent with tone extension */ + BT_LE_CS_TEST_OVERRIDE_3_REFLECTOR_TONE_EXT_ONLY = BT_HCI_OP_LE_CS_TEST_TONE_EXT_REFL, + /** Initiator and reflector tones sent with tone extension */ + BT_LE_CS_TEST_OVERRIDE_3_INITIATOR_AND_REFLECTOR_TONE_EXT = + BT_HCI_OP_LE_CS_TEST_TONE_EXT_BOTH, + /** Applicable for mode-2 and mode-3 only: + * + * Loop through: + * - @ref BT_LE_CS_TEST_OVERRIDE_3_NO_TONE_EXT + * - @ref BT_LE_CS_TEST_OVERRIDE_3_INITIATOR_TONE_EXT_ONLY + * - @ref BT_LE_CS_TEST_OVERRIDE_3_REFLECTOR_TONE_EXT_ONLY + * - @ref BT_LE_CS_TEST_OVERRIDE_3_INITIATOR_AND_REFLECTOR_TONE_EXT + */ + BT_LE_CS_TEST_OVERRIDE_3_REPETITIVE_TONE_EXT = BT_HCI_OP_LE_CS_TEST_TONE_EXT_REPEAT, +}; + +/** CS Test Override 4 Tone Antenna Permutation. + * + * These values represent indices in an antenna path permutation table. + * + * Which table is applicable (and which indices are valid) + * depends on the maximum number of antenna paths (N_AP). + * + * If N_AP = 2, the permutation table is: + * + * +--------------------------------+------------------------------------------+ + * | Antenna Path Permutation Index | Antenna Path Positions After Permutation | + * +--------------------------------+------------------------------------------+ + * | 0 | A1 A2 | + * | 1 | A2 A1 | + * +--------------------------------+------------------------------------------+ + * + * If N_AP = 3, the permutation table is: + * + * +--------------------------------+------------------------------------------+ + * | Antenna Path Permutation Index | Antenna Path Positions After Permutation | + * +--------------------------------+------------------------------------------+ + * | 0 | A1 A2 A3 | + * | 1 | A2 A1 A3 | + * | 2 | A1 A3 A2 | + * | 3 | A3 A1 A2 | + * | 4 | A3 A2 A1 | + * | 5 | A2 A3 A1 | + * +--------------------------------+------------------------------------------+ + * + * If N_AP = 4, the permutation table is: + * + * +--------------------------------+------------------------------------------+ + * | Antenna Path Permutation Index | Antenna Path Positions After Permutation | + * +--------------------------------+------------------------------------------+ + * | 0 | A1 A2 A3 A4 | + * | 1 | A2 A1 A3 A4 | + * | 2 | A1 A3 A2 A4 | + * | 3 | A3 A1 A2 A4 | + * | 4 | A3 A2 A1 A4 | + * | 5 | A2 A3 A1 A4 | + * | 6 | A1 A2 A4 A3 | + * | 7 | A2 A1 A4 A3 | + * | 8 | A1 A4 A2 A3 | + * | 9 | A4 A1 A2 A3 | + * | 10 | A4 A2 A1 A3 | + * | 11 | A2 A4 A1 A3 | + * | 12 | A1 A4 A3 A2 | + * | 13 | A4 A1 A3 A2 | + * | 14 | A1 A3 A4 A2 | + * | 15 | A3 A1 A4 A2 | + * | 16 | A3 A4 A1 A2 | + * | 17 | A4 A3 A1 A2 | + * | 18 | A4 A2 A3 A1 | + * | 19 | A2 A4 A3 A1 | + * | 20 | A4 A3 A2 A1 | + * | 21 | A3 A4 A2 A1 | + * | 22 | A3 A2 A4 A1 | + * | 23 | A2 A3 A4 A1 | + * +--------------------------------+------------------------------------------+ + */ +enum bt_le_cs_test_override_4_tone_antenna_permutation { + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_00 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_00, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_01 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_01, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_02 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_02, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_03 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_03, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_04 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_04, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_05 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_05, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_06 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_06, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_07 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_07, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_08 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_08, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_09 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_09, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_10 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_10, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_11 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_11, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_12 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_12, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_13 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_13, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_14 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_14, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_15 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_15, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_16 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_16, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_17 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_17, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_18 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_18, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_19 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_19, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_20 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_20, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_21 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_21, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_22 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_22, + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_23 = BT_HCI_OP_LE_CS_TEST_AP_INDEX_23, + /** Loop through all valid Antenna Permutation Indices starting + * from the lowest index. + */ + BT_LE_CS_TEST_OVERRIDE_4_ANTENNA_PERMUTATION_INDEX_LOOP = + BT_HCI_OP_LE_CS_TEST_AP_INDEX_LOOP, +}; + +/** CS Test Override 7 Sounding Sequence Marker Value */ +enum bt_le_cs_test_override_7_ss_marker_value { + BT_LE_CS_TEST_OVERRIDE_7_SS_MARKER_VAL_0011 = BT_HCI_OP_LE_CS_TEST_SS_MARKER_VAL_0011, + BT_LE_CS_TEST_OVERRIDE_7_SS_MARKER_VAL_1100 = BT_HCI_OP_LE_CS_TEST_SS_MARKER_VAL_1100, + /** Loop through pattern '0011' and '1100' (in transmission order) */ + BT_LE_CS_TEST_OVERRIDE_7_SS_MARKER_VAL_LOOP = BT_HCI_OP_LE_CS_TEST_SS_MARKER_VAL_LOOP, +}; + +/** CS Test Override 8 CS_SYNC Payload Pattern */ +enum bt_le_cs_test_override_8_cs_sync_payload_pattern { + /** PRBS9 payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_PRBS9 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_PRBS9, + /** Repeated '11110000' payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_11110000 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_11110000, + /** Repeated '10101010' payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_10101010 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_10101010, + /** PRBS15 payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_PRBS15 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_PRBS15, + /** Repeated '11111111' payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_11111111 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_11111111, + /** Repeated '00000000' payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_00000000 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_00000000, + /** Repeated '00001111' payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_00001111 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_00001111, + /** Repeated '01010101' payload sequence. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_01010101 = BT_HCI_OP_LE_CS_TEST_PAYLOAD_01010101, + /** Custom payload provided by the user. */ + BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_USER = BT_HCI_OP_LE_CS_TEST_PAYLOAD_USER, +}; + +/** CS Test parameters */ +struct bt_le_cs_test_param { + /** CS mode to be used during the CS procedure. */ + enum bt_conn_le_cs_main_mode main_mode; + /** CS sub-mode to be used during the CS procedure. */ + enum bt_conn_le_cs_sub_mode sub_mode; + /** Number of main mode steps taken from the end of the last CS subevent + * to be repeated at the beginning of the current CS subevent directly + * after the last mode-0 step of that event. + */ + uint8_t main_mode_repetition; + /** Number of CS mode-0 steps at the beginning of the test CS subevent. */ + uint8_t mode_0_steps; + /** CS Test role */ + enum bt_conn_le_cs_role role; + /** RTT variant */ + enum bt_conn_le_cs_rtt_type rtt_type; + /** CS_SYNC PHY */ + enum bt_conn_le_cs_sync_phy cs_sync_phy; + /** Antenna identifier to be used for CS_SYNC packets. */ + enum bt_le_cs_test_cs_sync_antenna_selection cs_sync_antenna_selection; + /** CS subevent length in microseconds. + * + * Range: 1250us to 4s + */ + uint32_t subevent_len; + /** Gap between the start of two consecutive CS subevents (N * 0.625 ms) + * + * A value of 0 means that there is only one CS subevent. + */ + uint16_t subevent_interval; + /** Maximum allowed number of subevents in the procedure. + * + * A value of 0 means that this parameter is ignored. + */ + uint8_t max_num_subevents; + /** Desired TX power level for the CS procedure. + * + * Value range is @ref BT_HCI_OP_LE_CS_MIN_MAX_TX_POWER to + * @ref BT_HCI_OP_LE_CS_MAX_MAX_TX_POWER. + * + * Special values: + * - @ref BT_HCI_OP_LE_CS_TEST_MAXIMIZE_TX_POWER tells the controller + * it should use as high a transmit power as possible + * - @ref BT_HCI_OP_LE_CS_TEST_MINIMIZE_TX_POWER tells the controller + * it should use as low a transmit power as possible + */ + uint8_t transmit_power_level; + /** Interlude time in microseconds between the RTT packets. + * + * Valid options are: + * - 10 us + * - 20 us + * - 30 us + * - 40 us + * - 50 us + * - 60 us + * - 80 us + * - 145 us + */ + uint8_t t_ip1_time; + /** Interlude time in microseconds between the CS tones. + * + * Valid options are: + * - 10 us + * - 20 us + * - 30 us + * - 40 us + * - 50 us + * - 60 us + * - 80 us + * - 145 us + */ + uint8_t t_ip2_time; + /** Time in microseconds for frequency changes. + * + * Valid options are: + * - 15 us + * - 20 us + * - 30 us + * - 40 us + * - 50 us + * - 60 us + * - 80 us + * - 100 us + * - 120 us + * - 150 us + */ + uint8_t t_fcs_time; + /** Time in microseconds for the phase measurement period of the CS tones. + * + * Valid options are: + * - 10 us + * - 20 us + * - 40 us + */ + uint8_t t_pm_time; + /** Time in microseconds for the antenna switch period of the CS tones. + * + * Valid options are: + * - 0 us + * - 1 us + * - 2 us + * - 4 us + * - 10 us + */ + uint8_t t_sw_time; + /** Antenna Configuration Index used during antenna switching during + * the tone phases of CS steps. + */ + enum bt_conn_le_cs_tone_antenna_config_selection tone_antenna_config_selection; + /** Initiator SNR control options */ + enum bt_le_cs_snr_control initiator_snr_control; + /** Reflector SNR control options */ + enum bt_le_cs_snr_control reflector_snr_control; + /** Determines octets 14 and 15 of the initial value of the DRBG nonce. */ + uint16_t drbg_nonce; + + /** Override configuration. + * + * This parameter is used to override CS parameters from the DRBG. + * Each bit configures a different set of parameters. + * + * All overrides are optional, except for those configured by bit 0. + * + * These are: + * - Bit 0 set: Override using list of channels + * - Bit 0 not set: Override using channel map + * - Bit 2 set: Override main mode steps + * - Bit 3 set: Override T_PM_Tone_Ext + * - Bit 4 set: Override tone antenna permutation + * - Bit 5 set: Override CS_SYNC AA + * - Bit 6 set: Override SS marker positions + * - Bit 7 set: Override SS marker value + * - Bit 8 set: Override CS_SYNC payload pattern and user payload + * - Bit 10 set: Procedure is replaced with a stable phase test + */ + uint16_t override_config; + + /** override config bit 0. */ + struct { + /** Number of times the channels indicated by the channel map or channel field + * are cycled through for non-mode-0 steps within a CS procedure. + */ + uint8_t channel_map_repetition; + union { + struct { + uint8_t num_channels; + uint8_t *channels; + } set; + struct { + uint8_t channel_map[10]; + enum bt_conn_le_cs_chsel_type channel_selection_type; + enum bt_conn_le_cs_ch3c_shape ch3c_shape; + uint8_t ch3c_jump; + } not_set; + }; + } override_config_0; + + /** Override config bit 2. These parameters are ignored if the bit is not set. */ + struct { + uint8_t main_mode_steps; + } override_config_2; + + /** Override config bit 3. These parameters are ignored if the bit is not set. */ + struct { + enum bt_le_cs_test_override_3_pm_tone_ext t_pm_tone_ext; + } override_config_3; + + /** Override config bit 4. These parameters are ignored if the bit is not set. */ + struct { + enum bt_le_cs_test_override_4_tone_antenna_permutation tone_antenna_permutation; + } override_config_4; + + /** Override config bit 5. These parameters are ignored if the bit is not set. */ + struct { + /** Access Address used in CS_SYNC packets sent by the initiator. */ + uint32_t cs_sync_aa_initiator; + /** Access Address used in CS_SYNC packets sent by the reflector. */ + uint32_t cs_sync_aa_reflector; + } override_config_5; + + /** Override config bit 6. These parameters are ignored if the bit is not set. */ + struct { + /** Bit number where the first marker in the channel sounding sequence starts. + * + * Must be between 0 and 28 when using @ref BT_CONN_LE_CS_RTT_TYPE_32_BIT_SOUNDING. + */ + uint8_t ss_marker1_position; + /** Bit number where the second marker in the channel sounding sequence starts. + * + * Must be between 67 and 92 when using @ref + * BT_CONN_LE_CS_RTT_TYPE_96_BIT_SOUNDING. + * + * A value of @ref BT_HCI_OP_LE_CS_TEST_SS_MARKER_2_POSITION_NOT_PRESENT + * indicates that this sounding sequence or marker is not present. + */ + uint8_t ss_marker2_position; + } override_config_6; + + /** Override config bit 7. These parameters are ignored if the bit is not set. */ + struct { + /** Value of the Sounding Sequence marker. */ + enum bt_le_cs_test_override_7_ss_marker_value ss_marker_value; + } override_config_7; + + /** Override config bit 8. These parameters are ignored if the bit is not set. */ + struct { + /** CS_SYNC payload pattern selection. */ + enum bt_le_cs_test_override_8_cs_sync_payload_pattern cs_sync_payload_pattern; + /** User payload for CS_SYNC packets. + * + * This parameter is only used when using + * @ref BT_LE_CS_TEST_OVERRIDE_8_PAYLOAD_PATTERN_USER + * + * The least significant bit corresponds to the most significant bit + * of the CS payload. When the sequence is less than 16 octets, + * the least significant octets shall be padded with zeros. + */ + uint8_t cs_sync_user_payload[16]; + } override_config_8; +}; + +/** CS config creation context */ +enum bt_le_cs_create_config_context { + /** Write CS configuration in local Controller only */ + BT_LE_CS_CREATE_CONFIG_CONTEXT_LOCAL_ONLY, + /** Write CS configuration in both local and remote Controller using Channel Sounding + * Configuration procedure + */ + BT_LE_CS_CREATE_CONFIG_CONTEXT_LOCAL_AND_REMOTE +}; + +/** CS Create Config params */ +struct bt_le_cs_create_config_params { + /** CS configuration ID */ + uint8_t id; + /** Main CS mode type */ + enum bt_conn_le_cs_main_mode main_mode_type; + /** Sub CS mode type */ + enum bt_conn_le_cs_sub_mode sub_mode_type; + /** Minimum number of CS main mode steps to be executed before a submode step is executed */ + uint8_t min_main_mode_steps; + /** Maximum number of CS main mode steps to be executed before a submode step is executed */ + uint8_t max_main_mode_steps; + /** Number of main mode steps taken from the end of the last CS subevent to be repeated + * at the beginning of the current CS subevent directly after the last mode-0 step of that + * event + */ + uint8_t main_mode_repetition; + /** Number of CS mode-0 steps to be included at the beginning of each CS subevent */ + uint8_t mode_0_steps; + /** CS role */ + enum bt_conn_le_cs_role role; + /** RTT type */ + enum bt_conn_le_cs_rtt_type rtt_type; + /** CS Sync PHY */ + enum bt_conn_le_cs_sync_phy cs_sync_phy; + /** The number of times the Channel_Map field will be cycled through for non-mode-0 steps + * within a CS procedure + */ + uint8_t channel_map_repetition; + /** Channel selection type */ + enum bt_conn_le_cs_chsel_type channel_selection_type; + /** User-specified channel sequence shape */ + enum bt_conn_le_cs_ch3c_shape ch3c_shape; + /** Number of channels skipped in each rising and falling sequence */ + uint8_t ch3c_jump; + /** Channel map used for CS procedure + * Channels n = 0, 1, 23, 24, 25, 77, and 78 are not allowed and shall be set to zero. + * Channel 79 is reserved for future use and shall be set to zero. + * At least 15 channels shall be enabled. + */ + uint8_t channel_map[10]; +}; + +/** Callbacks for CS Test */ +struct bt_le_cs_test_cb { + /**@brief CS Test Subevent data. + * + * @param[in] Subevent results. + */ + void (*le_cs_test_subevent_data_available)(struct bt_conn_le_cs_subevent_result *data); + /**@brief CS Test End Complete. */ + void (*le_cs_test_end_complete)(void); +}; + +/** Subevent result step */ +struct bt_le_cs_subevent_step { + /** CS step mode. */ + uint8_t mode; + /** CS step channel index. */ + uint8_t channel; + /** Length of role- and mode-specific information being reported. */ + uint8_t data_len; + /** Pointer to role- and mode-specific information. */ + const uint8_t *data; +}; + +/** Sign-extended IQ value extracted from step data. */ +struct bt_le_cs_iq_sample { + int16_t i; + int16_t q; +}; + +/** @brief Extract in-phase and quadrature terms from HCI-formatted PCT. + * + * Convenience function for processing 24-bit phase correction terms found + * in CS step data. The 12-bit signed real and imaginary components are + * converted to host endianness and sign-extended. + * + * @param pct 24-bit little-endian phase correction term. + * + * @return struct bt_le_cs_iq_sample containing real and imaginary terms as int16_t + */ +struct bt_le_cs_iq_sample bt_le_cs_parse_pct(const uint8_t pct[3]); + +/** @brief Set all valid channel map bits + * + * This command is used to enable all valid channels in a + * given CS channel map + * + * @param channel_map Chanel map + */ +void bt_le_cs_set_valid_chmap_bits(uint8_t channel_map[10]); + +/** @brief Read Remote Supported Capabilities + * + * This command is used to query the CS capabilities that are supported + * by the remote controller. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_read_remote_supported_capabilities(struct bt_conn *conn); + +/** @brief Set Channel Sounding default settings. + * + * This command is used to set default Channel Sounding settings for this + * connection. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param params Channel sounding default settings parameters. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_set_default_settings(struct bt_conn *conn, + const struct bt_le_cs_set_default_settings_param *params); + +/** @brief Read Remote FAE Table + * + * This command is used to read the per-channel mode-0 Frequency Actuation Error + * table of the remote Controller. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_read_remote_fae_table(struct bt_conn *conn); + +/** @brief Register callbacks for the CS Test mode. + * + * Existing callbacks can be unregistered by providing NULL function + * pointers. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING_TEST} must be set. + * + * @param cs_test_cb Set of callbacks to be used with CS Test + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_test_cb_register(struct bt_le_cs_test_cb cs_test_cb); + +/** @brief Start a CS test + * + * This command is used to start a CS test where the IUT is placed in the role + * of either the initiator or reflector. + * + * The first mode-0 channel in the list is used as the starting channel for + * the test. At the beginning of any test, the IUT in the reflector role shall + * listen on the first mode-0 channel until it receives the first transmission + * from the initiator. Similarly, with the IUT in the initiator role, the tester + * will start by listening on the first mode-0 channel and the IUT shall transmit + * on that channel for the first half of the first CS step. Thereafter, the + * parameters of this command describe the required transmit and receive behavior + * for the CS test. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING_TEST} must be set. + * + * @param params CS Test parameters + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_start_test(const struct bt_le_cs_test_param *params); + +/** @brief Create CS configuration + * + * This command is used to create a new CS configuration or update an + * existing one with the config id specified. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param params CS Create Config parameters + * @param context Controls whether the configuration is written to the local controller or + * both the local and the remote controller + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_create_config(struct bt_conn *conn, struct bt_le_cs_create_config_params *params, + enum bt_le_cs_create_config_context context); + +/** @brief Create CS configuration + * + * This command is used to remove a CS configuration from the local controller + * identified by the config_id + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param config_id CS Config ID + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_remove_config(struct bt_conn *conn, uint8_t config_id); + +/** @brief Stop ongoing CS Test + * + * This command is used to stop any CS test that is in progress. + * + * The controller is expected to finish reporting any subevent results + * before completing this termination. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING_TEST} must be set. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_stop_test(void); + +/** @brief Parse CS Subevent Step Data + * + * A helper for parsing HCI-formatted step data found in channel sounding subevent results. + * + * A typical use-case is filtering out data which does not meet certain packet quality or NADM + * requirements. + * + * @warning This function will consume the data when parsing. + * + * @param step_data_buf Pointer to a buffer containing the step data. + * @param func Callback function which will be called for each step data found. + * The callback should return true to continue parsing, or false to stop. + * @param user_data User data to be passed to the callback. + */ +void bt_le_cs_step_data_parse(struct net_buf_simple *step_data_buf, + bool (*func)(struct bt_le_cs_subevent_step *step, void *user_data), + void *user_data); + +/** @brief CS Security Enable + * + * This command is used to start or restart the Channel Sounding Security + * Start procedure in the local Controller for the ACL connection identified + * in the conn parameter. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_security_enable(struct bt_conn *conn); + +struct bt_le_cs_procedure_enable_param { + uint8_t config_id; + enum bt_conn_le_cs_procedure_enable_state enable; +}; + +/** @brief CS Procedure Enable + * + * This command is used to enable or disable the scheduling of CS procedures + * by the local Controller, with the remote device identified in the conn + * parameter. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param params Parameters for the CS Procedure Enable command. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_procedure_enable(struct bt_conn *conn, + const struct bt_le_cs_procedure_enable_param *params); + +enum bt_le_cs_procedure_phy { + BT_LE_CS_PROCEDURE_PHY_1M = BT_HCI_OP_LE_CS_PROCEDURE_PHY_1M, + BT_LE_CS_PROCEDURE_PHY_2M = BT_HCI_OP_LE_CS_PROCEDURE_PHY_2M, + BT_LE_CS_PROCEDURE_PHY_CODED_S8 = BT_HCI_OP_LE_CS_PROCEDURE_PHY_CODED_S8, + BT_LE_CS_PROCEDURE_PHY_CODED_S2 = BT_HCI_OP_LE_CS_PROCEDURE_PHY_CODED_S2, +}; + +#define BT_LE_CS_PROCEDURE_PREFERRED_PEER_ANTENNA_1 BIT(0) +#define BT_LE_CS_PROCEDURE_PREFERRED_PEER_ANTENNA_2 BIT(1) +#define BT_LE_CS_PROCEDURE_PREFERRED_PEER_ANTENNA_3 BIT(2) +#define BT_LE_CS_PROCEDURE_PREFERRED_PEER_ANTENNA_4 BIT(3) + +struct bt_le_cs_set_procedure_parameters_param { + /* The ID associated with the desired configuration (0 to 3) */ + uint8_t config_id; + + /* Max. duration for each CS procedure, where T = N * 0.625 ms (0x0001 to 0xFFFF) */ + uint16_t max_procedure_len; + + /* Min. number of connection events between consecutive CS procedures (0x0001 to 0xFFFF) */ + uint16_t min_procedure_interval; + + /* Max. number of connection events between consecutive CS procedures (0x0001 to 0xFFFF) */ + uint16_t max_procedure_interval; + + /* Max. number of procedures to be scheduled (0x0000 for no limit; otherwise 0x0001 + * to 0xFFFF) + */ + uint16_t max_procedure_count; + + /* Min. suggested duration for each CS subevent in microseconds (1250 us to 4 s) */ + uint32_t min_subevent_len; + + /* Max. suggested duration for each CS subevent in microseconds (1250 us to 4 s) */ + uint32_t max_subevent_len; + + /* Antenna configuration index */ + enum bt_conn_le_cs_tone_antenna_config_selection tone_antenna_config_selection; + + /* Phy */ + enum bt_le_cs_procedure_phy phy; + + /* Transmit power delta, in signed dB, to indicate the recommended difference between the + * remote device's power level for the CS tones and RTT packets and the existing power + * level for the Phy indicated by the Phy parameter (0x80 for no recommendation) + */ + int8_t tx_power_delta; + + /* Preferred peer antenna (Bitmask of BT_LE_CS_PROCEDURE_PREFERRED_PEER_ANTENNA_*) */ + uint8_t preferred_peer_antenna; + + /* Initiator SNR control adjustment */ + enum bt_le_cs_snr_control snr_control_initiator; + + /* Reflector SNR control adjustment */ + enum bt_le_cs_snr_control snr_control_reflector; +}; + +/** @brief CS Set Procedure Parameters + * + * This command is used to set the parameters for the scheduling of one + * or more CS procedures by the local controller. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param params Parameters for the CS Set Procedure Parameters command. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_set_procedure_parameters(struct bt_conn *conn, + const struct bt_le_cs_set_procedure_parameters_param *params); + +/** @brief CS Set Channel Classification + * + * This command is used to update the channel classification based on + * its local information. + * + * The nth bitfield (in the range 0 to 78) contains the value for the CS + * channel index n. Channel Enabled = 1; Channel Disabled = 0. + * + * Channels n = 0, 1, 23, 24, 25, 77, and 78 shall be reserved for future + * use and shall be set to zero. At least 15 channels shall be enabled. + * + * The most significant bit (bit 79) is reserved for future use. + * + * @note To use this API, @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param channel_classification Bit fields + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_set_channel_classification(uint8_t channel_classification[10]); + +/** @brief CS Read Local Supported Capabilities + * + * This command is used to read the CS capabilities that are supported + * by the local Controller. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param ret Return values for the CS Procedure Enable command. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_read_local_supported_capabilities(struct bt_conn_le_cs_capabilities *ret); + +/** @brief CS Write Cached Remote Supported Capabilities + * + * This command is used to write the cached copy of the CS capabilities + * that are supported by the remote Controller for the connection + * identified. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param params Parameters for the CS Write Cached Remote Supported Capabilities command. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_write_cached_remote_supported_capabilities( + struct bt_conn *conn, const struct bt_conn_le_cs_capabilities *params); + +/** @brief CS Write Cached Remote FAE Table + * + * This command is used to write a cached copy of the per-channel mode-0 + * Frequency Actuation Error table of the remote device in the local Controller. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param remote_fae_table Per-channel mode-0 FAE table of the local Controller + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_le_cs_write_cached_remote_fae_table(struct bt_conn *conn, int8_t remote_fae_table[72]); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_CS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gap.h index 16026d21..1b1569e3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gap.h @@ -38,56 +38,62 @@ extern "C" { * @name EIR/AD data type definitions * @{ */ -#define BT_DATA_FLAGS 0x01 /**< AD flags */ -#define BT_DATA_UUID16_SOME 0x02 /**< 16-bit UUID, more available */ -#define BT_DATA_UUID16_ALL 0x03 /**< 16-bit UUID, all listed */ -#define BT_DATA_UUID32_SOME 0x04 /**< 32-bit UUID, more available */ -#define BT_DATA_UUID32_ALL 0x05 /**< 32-bit UUID, all listed */ -#define BT_DATA_UUID128_SOME 0x06 /**< 128-bit UUID, more available */ -#define BT_DATA_UUID128_ALL 0x07 /**< 128-bit UUID, all listed */ -#define BT_DATA_NAME_SHORTENED 0x08 /**< Shortened name */ -#define BT_DATA_NAME_COMPLETE 0x09 /**< Complete name */ -#define BT_DATA_TX_POWER 0x0a /**< Tx Power */ -#define BT_DATA_SM_TK_VALUE 0x10 /**< Security Manager TK Value */ -#define BT_DATA_SM_OOB_FLAGS 0x11 /**< Security Manager OOB Flags */ -#define BT_DATA_PERIPHERAL_INT_RANGE 0x12 /**< Peripheral Connection Interval Range */ -#define BT_DATA_SOLICIT16 0x14 /**< Solicit UUIDs, 16-bit */ -#define BT_DATA_SOLICIT128 0x15 /**< Solicit UUIDs, 128-bit */ -#define BT_DATA_SVC_DATA16 0x16 /**< Service data, 16-bit UUID */ -#define BT_DATA_PUB_TARGET_ADDR 0x17 /**< Public Target Address */ -#define BT_DATA_RAND_TARGET_ADDR 0x18 /**< Random Target Address */ -#define BT_DATA_GAP_APPEARANCE 0x19 /**< GAP appearance */ -#define BT_DATA_ADV_INT 0x1a /**< Advertising Interval */ -#define BT_DATA_LE_BT_DEVICE_ADDRESS 0x1b /**< LE Bluetooth Device Address */ -#define BT_DATA_LE_ROLE 0x1c /**< LE Role */ -#define BT_DATA_SIMPLE_PAIRING_HASH 0x1d /**< Simple Pairing Hash C256 */ -#define BT_DATA_SIMPLE_PAIRING_RAND 0x1e /**< Simple Pairing Randomizer R256 */ -#define BT_DATA_SOLICIT32 0x1f /**< Solicit UUIDs, 32-bit */ -#define BT_DATA_SVC_DATA32 0x20 /**< Service data, 32-bit UUID */ -#define BT_DATA_SVC_DATA128 0x21 /**< Service data, 128-bit UUID */ -#define BT_DATA_LE_SC_CONFIRM_VALUE 0x22 /**< LE SC Confirmation Value */ -#define BT_DATA_LE_SC_RANDOM_VALUE 0x23 /**< LE SC Random Value */ -#define BT_DATA_URI 0x24 /**< URI */ -#define BT_DATA_INDOOR_POS 0x25 /**< Indoor Positioning */ -#define BT_DATA_TRANS_DISCOVER_DATA 0x26 /**< Transport Discovery Data */ -#define BT_DATA_LE_SUPPORTED_FEATURES 0x27 /**< LE Supported Features */ -#define BT_DATA_CHANNEL_MAP_UPDATE_IND 0x28 /**< Channel Map Update Indication */ -#define BT_DATA_MESH_PROV 0x29 /**< Mesh Provisioning PDU */ -#define BT_DATA_MESH_MESSAGE 0x2a /**< Mesh Networking PDU */ -#define BT_DATA_MESH_BEACON 0x2b /**< Mesh Beacon */ -#define BT_DATA_BIG_INFO 0x2c /**< BIGInfo */ -#define BT_DATA_BROADCAST_CODE 0x2d /**< Broadcast Code */ -#define BT_DATA_CSIS_RSI 0x2e /**< CSIS Random Set ID type */ -#define BT_DATA_ADV_INT_LONG 0x2f /**< Advertising Interval long */ -#define BT_DATA_BROADCAST_NAME 0x30 /**< Broadcast Name */ -#define BT_DATA_ENCRYPTED_AD_DATA 0x31 /**< Encrypted Advertising Data */ -#define BT_DATA_3D_INFO 0x3D /**< 3D Information Data */ - -#define BT_DATA_MANUFACTURER_DATA 0xff /**< Manufacturer Specific Data */ - -#define BT_LE_AD_LIMITED 0x01 /**< Limited Discoverable */ -#define BT_LE_AD_GENERAL 0x02 /**< General Discoverable */ -#define BT_LE_AD_NO_BREDR 0x04 /**< BR/EDR not supported */ +#define BT_DATA_FLAGS 0x01 /**< AD flags */ +#define BT_DATA_UUID16_SOME 0x02 /**< 16-bit UUID, more available */ +#define BT_DATA_UUID16_ALL 0x03 /**< 16-bit UUID, all listed */ +#define BT_DATA_UUID32_SOME 0x04 /**< 32-bit UUID, more available */ +#define BT_DATA_UUID32_ALL 0x05 /**< 32-bit UUID, all listed */ +#define BT_DATA_UUID128_SOME 0x06 /**< 128-bit UUID, more available */ +#define BT_DATA_UUID128_ALL 0x07 /**< 128-bit UUID, all listed */ +#define BT_DATA_NAME_SHORTENED 0x08 /**< Shortened name */ +#define BT_DATA_NAME_COMPLETE 0x09 /**< Complete name */ +#define BT_DATA_TX_POWER 0x0a /**< Tx Power */ +#define BT_DATA_DEVICE_CLASS 0x0d /**< Class of Device */ +#define BT_DATA_SIMPLE_PAIRING_HASH_C192 0x0e /**< Simple Pairing Hash C-192 */ +#define BT_DATA_SIMPLE_PAIRING_RAND_C192 0x0f /**< Simple Pairing Randomizer R-192 */ +#define BT_DATA_DEVICE_ID 0x10 /**< Device ID (Profile) */ +#define BT_DATA_SM_TK_VALUE 0x10 /**< Security Manager TK Value */ +#define BT_DATA_SM_OOB_FLAGS 0x11 /**< Security Manager OOB Flags */ +#define BT_DATA_PERIPHERAL_INT_RANGE 0x12 /**< Peripheral Connection Interval Range */ +#define BT_DATA_SOLICIT16 0x14 /**< Solicit UUIDs, 16-bit */ +#define BT_DATA_SOLICIT128 0x15 /**< Solicit UUIDs, 128-bit */ +#define BT_DATA_SVC_DATA16 0x16 /**< Service data, 16-bit UUID */ +#define BT_DATA_PUB_TARGET_ADDR 0x17 /**< Public Target Address */ +#define BT_DATA_RAND_TARGET_ADDR 0x18 /**< Random Target Address */ +#define BT_DATA_GAP_APPEARANCE 0x19 /**< GAP appearance */ +#define BT_DATA_ADV_INT 0x1a /**< Advertising Interval */ +#define BT_DATA_LE_BT_DEVICE_ADDRESS 0x1b /**< LE Bluetooth Device Address */ +#define BT_DATA_LE_ROLE 0x1c /**< LE Role */ +#define BT_DATA_SIMPLE_PAIRING_HASH 0x1d /**< Simple Pairing Hash C256 */ +#define BT_DATA_SIMPLE_PAIRING_RAND 0x1e /**< Simple Pairing Randomizer R256 */ +#define BT_DATA_SOLICIT32 0x1f /**< Solicit UUIDs, 32-bit */ +#define BT_DATA_SVC_DATA32 0x20 /**< Service data, 32-bit UUID */ +#define BT_DATA_SVC_DATA128 0x21 /**< Service data, 128-bit UUID */ +#define BT_DATA_LE_SC_CONFIRM_VALUE 0x22 /**< LE SC Confirmation Value */ +#define BT_DATA_LE_SC_RANDOM_VALUE 0x23 /**< LE SC Random Value */ +#define BT_DATA_URI 0x24 /**< URI */ +#define BT_DATA_INDOOR_POS 0x25 /**< Indoor Positioning */ +#define BT_DATA_TRANS_DISCOVER_DATA 0x26 /**< Transport Discovery Data */ +#define BT_DATA_LE_SUPPORTED_FEATURES 0x27 /**< LE Supported Features */ +#define BT_DATA_CHANNEL_MAP_UPDATE_IND 0x28 /**< Channel Map Update Indication */ +#define BT_DATA_MESH_PROV 0x29 /**< Mesh Provisioning PDU */ +#define BT_DATA_MESH_MESSAGE 0x2a /**< Mesh Networking PDU */ +#define BT_DATA_MESH_BEACON 0x2b /**< Mesh Beacon */ +#define BT_DATA_BIG_INFO 0x2c /**< BIGInfo */ +#define BT_DATA_BROADCAST_CODE 0x2d /**< Broadcast Code */ +#define BT_DATA_CSIS_RSI 0x2e /**< CSIS Random Set ID type */ +#define BT_DATA_ADV_INT_LONG 0x2f /**< Advertising Interval long */ +#define BT_DATA_BROADCAST_NAME 0x30 /**< Broadcast Name */ +#define BT_DATA_ENCRYPTED_AD_DATA 0x31 /**< Encrypted Advertising Data */ +#define BT_DATA_PAWR_TIMING_INFO 0x32 /**< Periodic Advertising Response Timing Info */ +#define BT_DATA_ESL 0x34 /**< Electronic Shelf Label Profile */ +#define BT_DATA_3D_INFO 0x3D /**< 3D Information Data */ + +#define BT_DATA_MANUFACTURER_DATA 0xff /**< Manufacturer Specific Data */ + +#define BT_LE_AD_LIMITED 0x01 /**< Limited Discoverable */ +#define BT_LE_AD_GENERAL 0x02 /**< General Discoverable */ +#define BT_LE_AD_NO_BREDR 0x04 /**< BR/EDR not supported */ /** * @} */ @@ -819,12 +825,225 @@ enum { /** Maximum Periodic Advertising Interval (N * 1.25 ms) */ #define BT_GAP_PER_ADV_MAX_INTERVAL 0xFFFF /* 81.91875 s */ +/** + * @brief Convert periodic advertising interval (N * 0.625 ms) to microseconds + * + * Value range of @p _interval is @ref BT_LE_ADV_INTERVAL_MIN to @ref BT_LE_ADV_INTERVAL_MAX + */ +#define BT_GAP_ADV_INTERVAL_TO_US(_interval) ((uint32_t)((_interval) * 625U)) + +/** + * @brief Convert periodic advertising interval (N * 0.625 ms) to milliseconds + * + * Value range of @p _interval is @ref BT_LE_ADV_INTERVAL_MIN to @ref BT_LE_ADV_INTERVAL_MAX + * + * @note When intervals cannot be represented in milliseconds, this will round down. + * For example BT_GAP_ADV_INTERVAL_TO_MS(0x0021) will become 20 ms instead of 20.625 ms + */ +#define BT_GAP_ADV_INTERVAL_TO_MS(_interval) (BT_GAP_ADV_INTERVAL_TO_US(_interval) / USEC_PER_MSEC) + +/** + * @brief Convert isochronous interval (N * 1.25 ms) to microseconds + * + * Value range of @p _interval is @ref BT_HCI_ISO_INTERVAL_MIN to @ref BT_HCI_ISO_INTERVAL_MAX + */ +#define BT_GAP_ISO_INTERVAL_TO_US(_interval) ((uint32_t)((_interval) * 1250U)) + +/** + * @brief Convert isochronous interval (N * 1.25 ms) to milliseconds + * + * Value range of @p _interval is @ref BT_HCI_ISO_INTERVAL_MIN to @ref BT_HCI_ISO_INTERVAL_MAX + * + * @note When intervals cannot be represented in milliseconds, this will round down. + * For example BT_GAP_ISO_INTERVAL_TO_MS(0x0005) will become 6 ms instead of 6.25 ms + */ +#define BT_GAP_ISO_INTERVAL_TO_MS(_interval) (BT_GAP_ISO_INTERVAL_TO_US(_interval) / USEC_PER_MSEC) + +/** @brief Convert periodic advertising interval (N * 1.25 ms) to microseconds * + * + * Value range of @p _interval is @ref BT_HCI_LE_PER_ADV_INTERVAL_MIN to @ref + * BT_HCI_LE_PER_ADV_INTERVAL_MAX + */ +#define BT_GAP_PER_ADV_INTERVAL_TO_US(_interval) ((uint32_t)((_interval) * 1250U)) + /** * @brief Convert periodic advertising interval (N * 1.25 ms) to milliseconds * - * 5 / 4 represents 1.25 ms unit. + * @note When intervals cannot be represented in milliseconds, this will round down. + * For example BT_GAP_PER_ADV_INTERVAL_TO_MS(0x0009) will become 11 ms instead of 11.25 ms + */ +#define BT_GAP_PER_ADV_INTERVAL_TO_MS(_interval) \ + (BT_GAP_PER_ADV_INTERVAL_TO_US(_interval) / USEC_PER_MSEC) + +/** + * @brief Convert microseconds to advertising interval units (0.625 ms) + * + * Value range of @p _interval is 20000 to 1024000 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_US_TO_ADV_INTERVAL(21000) will become 20625 microseconds + */ +#define BT_GAP_US_TO_ADV_INTERVAL(_interval) ((uint16_t)((_interval) / 625U)) + +/** + * @brief Convert milliseconds to advertising interval units (0.625 ms) + * + * Value range of @p _interval is 20 to 1024 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_ADV_INTERVAL(21) will become 20.625 milliseconds + */ +#define BT_GAP_MS_TO_ADV_INTERVAL(_interval) \ + (BT_GAP_US_TO_ADV_INTERVAL((_interval) * USEC_PER_MSEC)) + +/** + * @brief Convert microseconds to periodic advertising interval units (1.25 ms) + * + * Value range of @p _interval is 7500 to 81918750 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_US_TO_PER_ADV_INTERVAL(11000) will become 10000 microseconds + */ +#define BT_GAP_US_TO_PER_ADV_INTERVAL(_interval) ((uint16_t)((_interval) / 1250U)) + +/** + * @brief Convert milliseconds to periodic advertising interval units (1.25 ms) + * + * Value range of @p _interval is 7.5 to 81918.75 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_PER_ADV_INTERVAL(11) will become 10 milliseconds + */ +#define BT_GAP_MS_TO_PER_ADV_INTERVAL(_interval) \ + (BT_GAP_US_TO_PER_ADV_INTERVAL((_interval) * USEC_PER_MSEC)) + +/** + * @brief Convert milliseconds to periodic advertising sync timeout units (10 ms) + * + * Value range of @p _timeout is 100 to 163840 + * + * @note If @p _timeout is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_PER_ADV_SYNC_TIMEOUT(4005) will become 4000 milliseconds + */ +#define BT_GAP_MS_TO_PER_ADV_SYNC_TIMEOUT(_timeout) ((uint16_t)((_timeout) / 10U)) + +/** + * @brief Convert microseconds to periodic advertising sync timeout units (10 ms) + * + * Value range of @p _timeout is 100000 to 163840000 + * + * @note If @p _timeout is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_PER_ADV_SYNC_TIMEOUT(4005000) will become 4000000 microseconds + */ +#define BT_GAP_US_TO_PER_ADV_SYNC_TIMEOUT(_timeout) \ + (BT_GAP_MS_TO_PER_ADV_SYNC_TIMEOUT((_timeout) / USEC_PER_MSEC)) + +/** + * @brief Convert microseconds to scan interval units (0.625 ms) + * + * Value range of @p _interval is 2500 to 40959375 if @kconfig{CONFIG_BT_EXT_ADV} else + * 2500 to 10240000 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_US_TO_SCAN_INTERVAL(21000) will become 20625 microseconds + */ +#define BT_GAP_US_TO_SCAN_INTERVAL(_interval) ((uint16_t)((_interval) / 625U)) + +/** + * @brief Convert milliseconds to scan interval units (0.625 ms) + * + * Value range of @p _interval is 2.5 to 40959.375 if @kconfig{CONFIG_BT_EXT_ADV} else + * 2500 to 10240 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_SCAN_INTERVAL(21) will become 20.625 milliseconds + */ +#define BT_GAP_MS_TO_SCAN_INTERVAL(_interval) \ + (BT_GAP_US_TO_SCAN_INTERVAL((_interval) * USEC_PER_MSEC)) + +/** + * @brief Convert microseconds to scan window units (0.625 ms) + * + * Value range of @p _window is 2500 to 40959375 if @kconfig{CONFIG_BT_EXT_ADV} else + * 2500 to 10240000 + * + * @note If @p _window is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_US_TO_SCAN_WINDOW(21000) will become 20625 microseconds + */ +#define BT_GAP_US_TO_SCAN_WINDOW(_window) ((uint16_t)((_window) / 625U)) + +/** + * @brief Convert milliseconds to scan window units (0.625 ms) + * + * Value range of @p _window is 2.5 to 40959.375 if @kconfig{CONFIG_BT_EXT_ADV} else + * 2500 to 10240 + * + * @note If @p _window is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_SCAN_WINDOW(21) will become 20.625 milliseconds + */ +#define BT_GAP_MS_TO_SCAN_WINDOW(_window) (BT_GAP_US_TO_SCAN_WINDOW((_window) * USEC_PER_MSEC)) + +/** + * @brief Convert microseconds to connection interval units (1.25 ms) + * + * Value range of @p _interval is 7500 to 4000000 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_US_TO_CONN_INTERVAL(21000) will become 20000 microseconds + */ +#define BT_GAP_US_TO_CONN_INTERVAL(_interval) ((uint16_t)((_interval) / 1250U)) + +/** + * @brief Convert milliseconds to connection interval units (1.25 ms) + * + * Value range of @p _interval is 7.5 to 4000 + * + * @note If @p _interval is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_CONN_INTERVAL(21) will become 20 milliseconds + */ +#define BT_GAP_MS_TO_CONN_INTERVAL(_interval) \ + (BT_GAP_US_TO_CONN_INTERVAL((_interval) * USEC_PER_MSEC)) + +/** + * @brief Convert milliseconds to connection supervision timeout units (10 ms) + * + * Value range of @p _timeout is 100 to 32000 + * + * @note If @p _timeout is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_CONN_TIMEOUT(4005) will become 4000 milliseconds + */ +#define BT_GAP_MS_TO_CONN_TIMEOUT(_timeout) ((uint16_t)((_timeout) / 10U)) + +/** + * @brief Convert microseconds to connection supervision timeout units (10 ms) + + * Value range of @p _timeout is 100000 to 32000000 + * + * @note If @p _timeout is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_CONN_TIMEOUT(4005000) will become 4000000 microseconds + */ +#define BT_GAP_US_TO_CONN_TIMEOUT(_timeout) (BT_GAP_MS_TO_CONN_TIMEOUT((_timeout) / USEC_PER_MSEC)) + +/** + * @brief Convert milliseconds to connection event length units (0.625) + * + * Value range of @p _event_len is 0 to 40959375 + * + * @note If @p _event_len is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_US_TO_CONN_EVENT_LEN(21000) will become 20625 milliseconds + */ +#define BT_GAP_US_TO_CONN_EVENT_LEN(_event_len) ((uint16_t)((_event_len) / 625U)) + +/** + * @brief Convert milliseconds to connection event length units (0.625) + * + * Value range of @p _event_len is 0 to 40959.375 + * + * @note If @p _event_len is not a multiple of the unit, it will round down to nearest. + * For example BT_GAP_MS_TO_CONN_EVENT_LEN(21) will become 20.625 milliseconds */ -#define BT_GAP_PER_ADV_INTERVAL_TO_MS(interval) ((interval) * 5 / 4) +#define BT_GAP_MS_TO_CONN_EVENT_LEN(_event_len) \ + (BT_GAP_US_TO_CONN_EVENT_LEN((_event_len) * USEC_PER_MSEC)) /** Constant Tone Extension (CTE) types */ enum { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gatt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gatt.h index 78a6aab2..5a20771e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gatt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/gatt.h @@ -130,10 +130,25 @@ struct bt_gatt_attr; /** @typedef bt_gatt_attr_read_func_t * @brief Attribute read callback * - * The callback can also be used locally to read the contents of the - * attribute in which case no connection will be set. + * This is the type of the bt_gatt_attr.read() method. * - * @param conn The connection that is requesting to read + * This function may safely assume the Attribute Permissions + * are satisfied for this read. Callers are responsible for + * this. + * + * Callers may set @p conn to emulate a GATT client read, or + * leave it NULL for local reads. + * + * @note GATT server relies on this method to handle read + * operations from remote GATT clients. But this method is not + * reserved for the GATT server. E.g. You can lookup attributes + * in the local ATT database and invoke this method. + * + * @note The GATT server propagates the return value from this + * method back to the remote client. + * + * @param conn The connection that is requesting to read. + * NULL if local. * @param attr The attribute that's being read * @param buf Buffer to place the read result in * @param len Length of data to read @@ -148,7 +163,32 @@ typedef ssize_t (*bt_gatt_attr_read_func_t)(struct bt_conn *conn, uint16_t offset); /** @typedef bt_gatt_attr_write_func_t - * @brief Attribute write callback + * @brief Attribute Value write implementation + * + * This is the type of the bt_gatt_attr.write() method. + * + * This function may safely assume the Attribute Permissions + * are satisfied for this write. Callers are responsible for + * this. + * + * Callers may set @p conn to emulate a GATT client write, or + * leave it NULL for local writes. + * + * If @p flags contains @ref BT_GATT_WRITE_FLAG_PREPARE, then + * the method shall not perform a write, but instead only check + * if the write is authorized and return an error code if not. + * + * Attribute Value write implementations can and often do have + * side effects besides potentially storing the value. E.g. + * togging an LED. + * + * @note GATT server relies on this method to handle write + * operations from remote GATT clients. But this method is not + * reserved for the GATT server. E.g. You can lookup attributes + * in the local ATT database and invoke this method. + * + * @note The GATT server propagates the return value from this + * method back to the remote client. * * @param conn The connection that is requesting to write * @param attr The attribute that's being written @@ -165,23 +205,110 @@ typedef ssize_t (*bt_gatt_attr_write_func_t)(struct bt_conn *conn, const void *buf, uint16_t len, uint16_t offset, uint8_t flags); -/** @brief GATT Attribute structure. */ +/** @brief GATT Attribute + * + * This type primarily represents an ATT Attribute that may be + * an entry in the local ATT database. The objects of this type + * must be part of an array that forms a GATT service. + * + * While the formed GATT service is registered with the local + * GATT server, pointers to this type can typically be given to + * GATT server APIs, like bt_gatt_notify(). + * + * @note This type is given as an argument to the + * bt_gatt_discover() application callback, but it's not a + * proper object of this type. The field @ref perm, and methods + * read() and write() are not available, and it's unsound to + * pass the pointer to GATT server APIs. + */ struct bt_gatt_attr { - /** Attribute UUID */ + /** @brief Attribute Type, aka. "UUID" + * + * The Attribute Type determines the interface that can + * be expected from the read() and write() methods and + * the possible permission configurations. + * + * E.g. Attribute of type @ref BT_UUID_GATT_CPF will act as a + * GATT Characteristic Presentation Format descriptor as + * specified in Core Specification 3.G.3.3.3.5. + * + * You can define a new Attribute Type. + */ const struct bt_uuid *uuid; - /** Attribute read callback */ + + /** @brief Attribute Value read method + * + * Readable Attributes must implement this method. + * + * Must be NULL if the attribute is not readable. + * + * The behavior of this method is determined by the Attribute + * Type. + * + * See @ref bt_gatt_attr_read_func_t. + */ bt_gatt_attr_read_func_t read; - /** Attribute write callback */ + + /** @brief Attribute Value write method + * + * Writeable Attributes must implement this method. + * + * Must be NULL if the attribute is not writable. + * + * The behavior of this method is determined by the Attribute + * Type. + * + * See @ref bt_gatt_attr_write_func_t. + */ bt_gatt_attr_write_func_t write; - /** Attribute user data */ + + /** @brief Private data for read() and write() implementation + * + * The meaning of this field varies and is not specified here. + * + * @note Attributes may have the same Attribute Type but have + * different implementations, with incompatible user data. + * Attribute Type alone must not be used to infer the type of + * the user data. + * + * @sa bt_gatt_discover_func_t about this field. + */ void *user_data; - /** Attribute handle */ + + /** @brief Attribute Handle or zero, maybe? + * + * The meaning of this field varies and is not specified here. + * Some APIs use this field as input/output. It does not always + * contain the Attribute Handle. + * + * @note Use bt_gatt_attr_get_handle() for attributes in the + * local ATT database. + * + * @sa bt_gatt_discover_func_t about this field. + */ uint16_t handle; - /** @brief Attribute permissions. + + /** @brief Attribute Permissions + * + * Bit field of @ref bt_gatt_perm. + * + * The permissions are security requirements that must be + * satisfied before calling read() or write(). * - * Will be 0 if returned from ``bt_gatt_discover()``. + * @sa bt_gatt_discover_func_t about this field. */ - uint16_t perm; + uint16_t perm: 15; + + /** @cond INTERNAL_HIDDEN + * Indicates if the attribute handle was assigned automatically. + * + * This flag is set to 1 if the attribute handle was assigned by the stack, + * and 0 if it was manually set by the application. + * + * @note Applications must not modify this field. + */ + bool _auto_assigned_handle: 1; + /** @endcond */ }; /** @brief GATT Service structure */ @@ -578,7 +705,8 @@ struct bt_gatt_attr *bt_gatt_find_by_uuid(const struct bt_gatt_attr *attr, /** @brief Get Attribute handle. * - * @param attr Attribute object. + * @param attr An attribute object currently registered in the + * local ATT server. * * @return Handle of the corresponding attribute or zero if the attribute * could not be found. @@ -1371,6 +1499,23 @@ bool bt_gatt_is_subscribed(struct bt_conn *conn, */ uint16_t bt_gatt_get_mtu(struct bt_conn *conn); +/** @brief Get Unenhanced ATT (UATT) MTU for a connection + * + * Get UATT connection MTU. + * + * The ATT_MTU defines the largest size of an ATT PDU, encompassing the ATT + * opcode, additional fields, and any attribute value payload. Consequently, + * the maximum size of a value payload is less and varies based on the type + * of ATT PDU. For example, in an ATT_HANDLE_VALUE_NTF PDU, the Attribute Value + * field can contain up to ATT_MTU - 3 octets (size of opcode and handle). + * + * @param conn Connection object. + * + * @return 0 if @p conn does not have an UATT ATT_MTU (e.g: disconnected). + * @return Current UATT ATT_MTU. + */ +uint16_t bt_gatt_get_uatt_mtu(struct bt_conn *conn); + /** @} */ /** @@ -1510,6 +1655,9 @@ enum { BT_GATT_DISCOVER_STD_CHAR_DESC, }; +/** Handle value to denote that the CCC will be automatically discovered */ +#define BT_GATT_AUTO_DISCOVER_CCC_HANDLE 0x0000U + /** @brief GATT Discover Attributes parameters */ struct bt_gatt_discover_params { /** Discover UUID type */ @@ -1759,11 +1907,6 @@ int bt_gatt_write(struct bt_conn *conn, struct bt_gatt_write_params *params); * The number of pending callbacks can be increased with the * @kconfig{CONFIG_BT_CONN_TX_MAX} option. * - * @note By using a callback it also disable the internal flow control - * which would prevent sending multiple commands without waiting for - * their transmissions to complete, so if that is required the caller - * shall not submit more data until the callback is called. - * * This function will block while the ATT request queue is full, except when * called from the BT RX thread, as this would cause a deadlock. * @@ -1915,7 +2058,7 @@ struct bt_gatt_subscribe_params { #if defined(CONFIG_BT_GATT_AUTO_DISCOVER_CCC) || defined(__DOXYGEN__) /** Subscribe End handle (for automatic discovery) */ uint16_t end_handle; - /** Discover parameters used when ccc_handle = 0 */ + /** Discover parameters used when ccc_handle = @ref BT_GATT_AUTO_DISCOVER_CCC_HANDLE */ struct bt_gatt_discover_params *disc_params; #endif /* defined(CONFIG_BT_GATT_AUTO_DISCOVER_CCC) || defined(__DOXYGEN__) */ /** Subscribe value */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci.h index 21b6925e..7687abdb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci.h @@ -11,7 +11,7 @@ #include #include -#include +#include #include #include #include @@ -113,6 +113,18 @@ int bt_hci_cmd_send_sync(uint16_t opcode, struct net_buf *buf, */ int bt_hci_get_conn_handle(const struct bt_conn *conn, uint16_t *conn_handle); +/** @brief Get connection given a connection handle. + * + * The caller gets a new reference to the connection object which must be + * released with bt_conn_unref() once done using the object. + * + * @param handle The connection handle + * + * @returns The corresponding connection object on success. + * NULL if it does not exist. + */ +struct bt_conn *bt_hci_conn_lookup_handle(uint16_t handle); + /** @brief Get advertising handle for an advertising set. * * @param adv Advertising set. @@ -122,6 +134,15 @@ int bt_hci_get_conn_handle(const struct bt_conn *conn, uint16_t *conn_handle); */ int bt_hci_get_adv_handle(const struct bt_le_ext_adv *adv, uint8_t *adv_handle); +/** @brief Get advertising set given an advertising handle + * + * @param handle The advertising handle + * + * @returns The corresponding advertising set on success, + * NULL if it does not exist. + */ +struct bt_le_ext_adv *bt_hci_adv_lookup_handle(uint8_t handle); + /** @brief Get periodic advertising sync handle. * * @param sync Periodic advertising sync set. @@ -131,6 +152,15 @@ int bt_hci_get_adv_handle(const struct bt_le_ext_adv *adv, uint8_t *adv_handle); */ int bt_hci_get_adv_sync_handle(const struct bt_le_per_adv_sync *sync, uint16_t *sync_handle); +/** @brief Get periodic advertising sync given an periodic advertising sync handle. + * + * @param handle The periodic sync set handle + * + * @retval The corresponding periodic advertising sync set object on success, + * NULL if it does not exist. + */ +struct bt_le_per_adv_sync *bt_hci_per_adv_sync_lookup_handle(uint16_t handle); + /** @brief Obtain the version string given a core version number. * * The core version of a controller can be obtained by issuing diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci_types.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci_types.h index 1aa5aa91..e7d20350 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci_types.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/hci_types.h @@ -33,7 +33,8 @@ extern "C" { #define BT_HCI_H4_EVT 0x04 /* HCI Event packet */ #define BT_HCI_H4_ISO 0x05 /* HCI ISO Data packet */ -/* Special own address types for LL privacy (used in adv & scan parameters) */ +#define BT_HCI_OWN_ADDR_PUBLIC 0x00 +#define BT_HCI_OWN_ADDR_RANDOM 0x01 #define BT_HCI_OWN_ADDR_RPA_OR_PUBLIC 0x02 #define BT_HCI_OWN_ADDR_RPA_OR_RANDOM 0x03 #define BT_HCI_OWN_ADDR_RPA_MASK 0x02 @@ -201,6 +202,9 @@ struct bt_hci_cmd_hdr { #define BT_LE_FEAT_BIT_PAWR_ADVERTISER 43 #define BT_LE_FEAT_BIT_PAWR_SCANNER 44 +#define BT_LE_FEAT_BIT_CHANNEL_SOUNDING 46 +#define BT_LE_FEAT_BIT_CHANNEL_SOUNDING_HOST 47 + #define BT_LE_FEAT_TEST(feat, n) (feat[(n) >> 3] & \ BIT((n) & 7)) @@ -268,6 +272,10 @@ struct bt_hci_cmd_hdr { BT_LE_FEAT_BIT_PAWR_ADVERTISER) #define BT_FEAT_LE_PAWR_SCANNER(feat) BT_LE_FEAT_TEST(feat, \ BT_LE_FEAT_BIT_PAWR_SCANNER) +#define BT_FEAT_LE_CHANNEL_SOUNDING(feat) BT_LE_FEAT_TEST(feat, \ + BT_LE_FEAT_BIT_CHANNEL_SOUNDING) +#define BT_FEAT_LE_CHANNEL_SOUNDING_HOST(feat) BT_LE_FEAT_TEST(feat, \ + BT_LE_FEAT_BIT_CHANNEL_SOUNDING_HOST) #define BT_FEAT_LE_CIS(feat) (BT_FEAT_LE_CIS_CENTRAL(feat) | \ BT_FEAT_LE_CIS_PERIPHERAL(feat)) @@ -704,6 +712,26 @@ struct bt_hci_cp_le_set_path_loss_reporting_enable { #define BT_HCI_LE_PATH_LOSS_REPORTING_ENABLE 0x01 #define BT_HCI_OP_LE_SET_PATH_LOSS_REPORTING_ENABLE BT_OP(BT_OGF_LE, 0x0079) /* 0x2079 */ +struct bt_hci_cp_le_set_default_subrate { + uint16_t subrate_min; + uint16_t subrate_max; + uint16_t max_latency; + uint16_t continuation_number; + uint16_t supervision_timeout; +} __packed; + +struct bt_hci_cp_le_subrate_request { + uint16_t handle; + uint16_t subrate_min; + uint16_t subrate_max; + uint16_t max_latency; + uint16_t continuation_number; + uint16_t supervision_timeout; +} __packed; + +#define BT_HCI_OP_LE_SET_DEFAULT_SUBRATE BT_OP(BT_OGF_LE, 0x007D) /* 0x207D */ +#define BT_HCI_OP_LE_SUBRATE_REQUEST BT_OP(BT_OGF_LE, 0x007E) /* 0x207E */ + #define BT_HCI_CTL_TO_HOST_FLOW_DISABLE 0x00 #define BT_HCI_CTL_TO_HOST_FLOW_ENABLE 0x01 #define BT_HCI_OP_SET_CTL_TO_HOST_FLOW BT_OP(BT_OGF_BASEBAND, 0x0031) /* 0x0c31 */ @@ -805,6 +833,7 @@ struct bt_hci_rp_configure_data_path { #define BT_HCI_VERSION_5_2 11 #define BT_HCI_VERSION_5_3 12 #define BT_HCI_VERSION_5_4 13 +#define BT_HCI_VERSION_6_0 14 #define BT_HCI_OP_READ_LOCAL_VERSION_INFO BT_OP(BT_OGF_INFO, 0x0001) /* 0x1001 */ struct bt_hci_rp_read_local_version_info { @@ -2374,6 +2403,313 @@ struct bt_hci_cp_le_tx_test_v4_tx_power { int8_t tx_power; } __packed; +#define BT_HCI_OP_LE_CS_READ_LOCAL_SUPPORTED_CAPABILITIES BT_OP(BT_OGF_LE, 0x0089) /* 0x2089 */ + +struct bt_hci_rp_le_read_local_supported_capabilities { + uint8_t status; + uint8_t num_config_supported; + uint16_t max_consecutive_procedures_supported; + uint8_t num_antennas_supported; + uint8_t max_antenna_paths_supported; + uint8_t roles_supported; + uint8_t modes_supported; + uint8_t rtt_capability; + uint8_t rtt_aa_only_n; + uint8_t rtt_sounding_n; + uint8_t rtt_random_payload_n; + uint16_t nadm_sounding_capability; + uint16_t nadm_random_capability; + uint8_t cs_sync_phys_supported; + uint16_t subfeatures_supported; + uint16_t t_ip1_times_supported; + uint16_t t_ip2_times_supported; + uint16_t t_fcs_times_supported; + uint16_t t_pm_times_supported; + uint8_t t_sw_time_supported; + uint8_t tx_snr_capability; +} __packed; + +#define BT_HCI_OP_LE_CS_READ_REMOTE_SUPPORTED_CAPABILITIES BT_OP(BT_OGF_LE, 0x008A) /* 0x208A */ + +struct bt_hci_cp_le_read_remote_supported_capabilities { + uint16_t handle; +} __packed; + +#define BT_HCI_OP_LE_CS_WRITE_CACHED_REMOTE_SUPPORTED_CAPABILITIES \ + BT_OP(BT_OGF_LE, 0x008B) /* 0x208B */ + +struct bt_hci_cp_le_write_cached_remote_supported_capabilities { + uint16_t handle; + uint8_t num_config_supported; + uint16_t max_consecutive_procedures_supported; + uint8_t num_antennas_supported; + uint8_t max_antenna_paths_supported; + uint8_t roles_supported; + uint8_t modes_supported; + uint8_t rtt_capability; + uint8_t rtt_aa_only_n; + uint8_t rtt_sounding_n; + uint8_t rtt_random_payload_n; + uint16_t nadm_sounding_capability; + uint16_t nadm_random_capability; + uint8_t cs_sync_phys_supported; + uint16_t subfeatures_supported; + uint16_t t_ip1_times_supported; + uint16_t t_ip2_times_supported; + uint16_t t_fcs_times_supported; + uint16_t t_pm_times_supported; + uint8_t t_sw_time_supported; + uint8_t tx_snr_capability; +} __packed; + +#define BT_HCI_OP_LE_CS_SECURITY_ENABLE BT_OP(BT_OGF_LE, 0x008C) /* 0x208C */ + +struct bt_hci_cp_le_security_enable { + uint16_t handle; +} __packed; + +#define BT_HCI_OP_LE_CS_SET_DEFAULT_SETTINGS BT_OP(BT_OGF_LE, 0x008D) /* 0x208D */ + +#define BT_HCI_OP_LE_CS_INITIATOR_ROLE_MASK BIT(0) +#define BT_HCI_OP_LE_CS_REFLECTOR_ROLE_MASK BIT(1) + +#define BT_HCI_OP_LE_CS_MIN_MAX_TX_POWER -127 +#define BT_HCI_OP_LE_CS_MAX_MAX_TX_POWER 20 + +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_ONE 0x01 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_TWO 0x02 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_THREE 0x03 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_FOUR 0x04 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_REP 0xFE +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_NONE 0xFF + +struct bt_hci_cp_le_cs_set_default_settings { + uint16_t handle; + uint8_t role_enable; + uint8_t cs_sync_antenna_selection; + int8_t max_tx_power; +} __packed; + +#define BT_HCI_OP_LE_CS_READ_REMOTE_FAE_TABLE BT_OP(BT_OGF_LE, 0x008E) /* 0x208E */ + +struct bt_hci_cp_le_read_remote_fae_table { + uint16_t handle; +} __packed; + +#define BT_HCI_OP_LE_CS_WRITE_CACHED_REMOTE_FAE_TABLE BT_OP(BT_OGF_LE, 0x008F) /* 0x208F */ + +struct bt_hci_cp_le_write_cached_remote_fae_table { + uint16_t handle; + int8_t remote_fae_table[72]; +} __packed; + +#define BT_HCI_OP_LE_CS_SET_CHANNEL_CLASSIFICATION BT_OP(BT_OGF_LE, 0x0092) /* 0x2092 */ + +#define BT_HCI_OP_LE_CS_SET_PROCEDURE_PARAMETERS BT_OP(BT_OGF_LE, 0x0093) /* 0x2093 */ + +#define BT_HCI_OP_LE_CS_PROCEDURE_PHY_1M 0x01 +#define BT_HCI_OP_LE_CS_PROCEDURE_PHY_2M 0x02 +#define BT_HCI_OP_LE_CS_PROCEDURE_PHY_CODED_S8 0x03 +#define BT_HCI_OP_LE_CS_PROCEDURE_PHY_CODED_S2 0x04 + +struct bt_hci_cp_le_set_procedure_parameters { + uint16_t handle; + uint8_t config_id; + uint16_t max_procedure_len; + uint16_t min_procedure_interval; + uint16_t max_procedure_interval; + uint16_t max_procedure_count; + uint8_t min_subevent_len[3]; + uint8_t max_subevent_len[3]; + uint8_t tone_antenna_config_selection; + uint8_t phy; + uint8_t tx_power_delta; + uint8_t preferred_peer_antenna; + uint8_t snr_control_initiator; + uint8_t snr_control_reflector; +} __packed; + +#define BT_HCI_OP_LE_CS_PROCEDURE_ENABLE BT_OP(BT_OGF_LE, 0x0094) /* 0x2094 */ + +#define BT_HCI_OP_LE_CS_PROCEDURES_DISABLED 0x00 +#define BT_HCI_OP_LE_CS_PROCEDURES_ENABLED 0x01 + +struct bt_hci_cp_le_procedure_enable { + uint16_t handle; + uint8_t config_id; + uint8_t enable; +} __packed; + +#define BT_HCI_OP_LE_CS_TEST BT_OP(BT_OGF_LE, 0x0095) /* 0x2095 */ + +#define BT_HCI_OP_LE_CS_MAIN_MODE_1 0x1 +#define BT_HCI_OP_LE_CS_MAIN_MODE_2 0x2 +#define BT_HCI_OP_LE_CS_MAIN_MODE_3 0x3 + +#define BT_HCI_OP_LE_CS_SUB_MODE_1 0x1 +#define BT_HCI_OP_LE_CS_SUB_MODE_2 0x2 +#define BT_HCI_OP_LE_CS_SUB_MODE_3 0x3 +#define BT_HCI_OP_LE_CS_SUB_MODE_UNUSED 0xFF + +#define BT_HCI_OP_LE_CS_INITIATOR_ROLE 0x0 +#define BT_HCI_OP_LE_CS_REFLECTOR_ROLE 0x1 + +#define BT_HCI_OP_LE_CS_RTT_TYPE_AA_ONLY 0x0 +#define BT_HCI_OP_LE_CS_RTT_TYPE_32BIT_SOUND 0x1 +#define BT_HCI_OP_LE_CS_RTT_TYPE_96BIT_SOUND 0x2 +#define BT_HCI_OP_LE_CS_RTT_TYPE_32BIT_RAND 0x3 +#define BT_HCI_OP_LE_CS_RTT_TYPE_64BIT_RAND 0x4 +#define BT_HCI_OP_LE_CS_RTT_TYPE_96BIT_RAND 0x5 +#define BT_HCI_OP_LE_CS_RTT_TYPE_128BIT_RAND 0x6 + +#define BT_HCI_OP_LE_CS_CS_SYNC_1M 0x1 +#define BT_HCI_OP_LE_CS_CS_SYNC_2M 0x2 +#define BT_HCI_OP_LE_CS_CS_SYNC_2M_2BT 0x3 + +#define BT_HCI_OP_LE_CS_TEST_MINIMIZE_TX_POWER 0x7E +#define BT_HCI_OP_LE_CS_TEST_MAXIMIZE_TX_POWER 0x7F + +#define BT_HCI_OP_LE_CS_ACI_0 0x0 +#define BT_HCI_OP_LE_CS_ACI_1 0x1 +#define BT_HCI_OP_LE_CS_ACI_2 0x2 +#define BT_HCI_OP_LE_CS_ACI_3 0x3 +#define BT_HCI_OP_LE_CS_ACI_4 0x4 +#define BT_HCI_OP_LE_CS_ACI_5 0x5 +#define BT_HCI_OP_LE_CS_ACI_6 0x6 +#define BT_HCI_OP_LE_CS_ACI_7 0x7 + +#define BT_HCI_OP_LE_CS_SNR_18 0x0 +#define BT_HCI_OP_LE_CS_SNR_21 0x1 +#define BT_HCI_OP_LE_CS_SNR_24 0x2 +#define BT_HCI_OP_LE_CS_SNR_27 0x3 +#define BT_HCI_OP_LE_CS_SNR_30 0x4 +#define BT_HCI_OP_LE_CS_SNR_NOT_USED 0xFF + +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_0_MASK BIT(0) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_2_MASK BIT(2) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_3_MASK BIT(3) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_4_MASK BIT(4) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_5_MASK BIT(5) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_6_MASK BIT(6) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_7_MASK BIT(7) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_8_MASK BIT(8) +#define BT_HCI_OP_LE_CS_TEST_OVERRIDE_CONFIG_10_MASK BIT(10) + +#define BT_HCI_OP_LE_CS_TEST_CHSEL_TYPE_3B 0x0 +#define BT_HCI_OP_LE_CS_TEST_CHSEL_TYPE_3C 0x1 + +#define BT_HCI_OP_LE_CS_TEST_CH3C_SHAPE_HAT 0x0 +#define BT_HCI_OP_LE_CS_TEST_CH3C_SHAPE_X 0x1 + +#define BT_HCI_OP_LE_CS_TEST_TONE_EXT_NONE 0x0 +#define BT_HCI_OP_LE_CS_TEST_TONE_EXT_INIT 0x1 +#define BT_HCI_OP_LE_CS_TEST_TONE_EXT_REFL 0x2 +#define BT_HCI_OP_LE_CS_TEST_TONE_EXT_BOTH 0x3 +#define BT_HCI_OP_LE_CS_TEST_TONE_EXT_REPEAT 0x4 + +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_00 0x0 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_01 0x1 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_02 0x2 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_03 0x3 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_04 0x4 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_05 0x5 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_06 0x6 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_07 0x7 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_08 0x8 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_09 0x9 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_10 0xA +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_11 0xB +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_12 0xC +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_13 0xD +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_14 0xE +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_15 0xF +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_16 0x10 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_17 0x11 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_18 0x12 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_19 0x13 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_20 0x14 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_21 0x15 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_22 0x16 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_23 0x17 +#define BT_HCI_OP_LE_CS_TEST_AP_INDEX_LOOP 0xFF + +#define BT_HCI_OP_LE_CS_TEST_SS_MARKER_2_POSITION_NOT_PRESENT 0xFF + +#define BT_HCI_OP_LE_CS_TEST_SS_MARKER_VAL_0011 0x0 +#define BT_HCI_OP_LE_CS_TEST_SS_MARKER_VAL_1100 0x1 +#define BT_HCI_OP_LE_CS_TEST_SS_MARKER_VAL_LOOP 0x2 + +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_PRBS9 0x00 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_11110000 0x01 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_10101010 0x02 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_PRBS15 0x03 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_11111111 0x04 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_00000000 0x05 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_00001111 0x06 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_01010101 0x07 +#define BT_HCI_OP_LE_CS_TEST_PAYLOAD_USER 0x80 + +struct bt_hci_op_le_cs_test { + uint8_t main_mode_type; + uint8_t sub_mode_type; + uint8_t main_mode_repetition; + uint8_t mode_0_steps; + uint8_t role; + uint8_t rtt_type; + uint8_t cs_sync_phy; + uint8_t cs_sync_antenna_selection; + uint8_t subevent_len[3]; + uint16_t subevent_interval; + uint8_t max_num_subevents; + uint8_t transmit_power_level; + uint8_t t_ip1_time; + uint8_t t_ip2_time; + uint8_t t_fcs_time; + uint8_t t_pm_time; + uint8_t t_sw_time; + uint8_t tone_antenna_config_selection; + uint8_t reserved; + uint8_t snr_control_initiator; + uint8_t snr_control_reflector; + uint16_t drbg_nonce; + uint8_t channel_map_repetition; + uint16_t override_config; + uint8_t override_parameters_length; + uint8_t override_parameters_data[]; +} __packed; + +#define BT_HCI_OP_LE_CS_CREATE_CONFIG BT_OP(BT_OGF_LE, 0x0090) /* 0x2090 */ + +struct bt_hci_cp_le_cs_create_config { + uint16_t handle; + uint8_t config_id; + uint8_t create_context; + uint8_t main_mode_type; + uint8_t sub_mode_type; + uint8_t min_main_mode_steps; + uint8_t max_main_mode_steps; + uint8_t main_mode_repetition; + uint8_t mode_0_steps; + uint8_t role; + uint8_t rtt_type; + uint8_t cs_sync_phy; + uint8_t channel_map[10]; + uint8_t channel_map_repetition; + uint8_t channel_selection_type; + uint8_t ch3c_shape; + uint8_t ch3c_jump; + uint8_t reserved; +} __packed; + +#define BT_HCI_OP_LE_CS_REMOVE_CONFIG BT_OP(BT_OGF_LE, 0x0091) /* 0x2091 */ + +struct bt_hci_cp_le_cs_remove_config { + uint16_t handle; + uint8_t config_id; +} __packed; + +#define BT_HCI_OP_LE_CS_TEST_END BT_OP(BT_OGF_LE, 0x0096) /* 0x2096 */ + /* Event definitions */ #define BT_HCI_EVT_UNKNOWN 0x00 @@ -2729,6 +3065,13 @@ struct bt_hci_evt_le_advertising_report { struct bt_hci_evt_le_advertising_info adv_info[0]; } __packed; +/** All limits according to BT Core Spec v5.4 [Vol 4, Part E]. */ +#define BT_HCI_LE_INTERVAL_MIN 0x0006 +#define BT_HCI_LE_INTERVAL_MAX 0x0c80 +#define BT_HCI_LE_PERIPHERAL_LATENCY_MAX 0x01f3 +#define BT_HCI_LE_SUPERVISON_TIMEOUT_MIN 0x000a +#define BT_HCI_LE_SUPERVISON_TIMEOUT_MAX 0x0c80 + #define BT_HCI_EVT_LE_CONN_UPDATE_COMPLETE 0x03 struct bt_hci_evt_le_conn_update_complete { uint8_t status; @@ -3098,6 +3441,403 @@ struct bt_hci_evt_le_biginfo_adv_report { uint8_t encryption; } __packed; +/** All limits according to BT Core Spec v5.4 [Vol 4, Part E]. */ +#define BT_HCI_LE_SUBRATE_FACTOR_MIN 0x0001 +#define BT_HCI_LE_SUBRATE_FACTOR_MAX 0x01f4 +#define BT_HCI_LE_CONTINUATION_NUM_MAX 0x01f3 + +#define BT_HCI_EVT_LE_SUBRATE_CHANGE 0x23 +struct bt_hci_evt_le_subrate_change { + uint8_t status; + uint16_t handle; + uint16_t subrate_factor; + uint16_t peripheral_latency; + uint16_t continuation_number; + uint16_t supervision_timeout; +} __packed; + +#define BT_HCI_LE_CS_INITIATOR_ROLE_MASK BIT(0) +#define BT_HCI_LE_CS_REFLECTOR_ROLE_MASK BIT(1) + +#define BT_HCI_LE_CS_MODES_SUPPORTED_MODE_3_MASK BIT(0) + +#define BT_HCI_LE_CS_RTT_AA_ONLY_N_10NS_MASK BIT(0) +#define BT_HCI_LE_CS_RTT_SOUNDING_N_10NS_MASK BIT(1) +#define BT_HCI_LE_CS_RTT_RANDOM_PAYLOAD_N_10NS_MASK BIT(2) + +#define BT_HCI_LE_CS_NADM_SOUNDING_CAPABILITY_PHASE_BASED_MASK BIT(0) +#define BT_HCI_LE_CS_NADM_RANDOM_CAPABILITY_PHASE_BASED_MASK BIT(0) + +#define BT_HCI_LE_CS_SYNC_PHYS_2M_MASK BIT(1) +#define BT_HCI_LE_CS_SYNC_PHYS_2M_2BT_MASK BIT(2) + +#define BT_HCI_LE_CS_SUBFEATURE_NO_TX_FAE_MASK BIT(1) +#define BT_HCI_LE_CS_SUBFEATURE_CHSEL_ALG_3C_MASK BIT(2) +#define BT_HCI_LE_CS_SUBFEATURE_PBR_FROM_RTT_SOUNDING_SEQ_MASK BIT(3) + +#define BT_HCI_LE_CS_T_IP1_TIME_10US_MASK BIT(0) +#define BT_HCI_LE_CS_T_IP1_TIME_20US_MASK BIT(1) +#define BT_HCI_LE_CS_T_IP1_TIME_30US_MASK BIT(2) +#define BT_HCI_LE_CS_T_IP1_TIME_40US_MASK BIT(3) +#define BT_HCI_LE_CS_T_IP1_TIME_50US_MASK BIT(4) +#define BT_HCI_LE_CS_T_IP1_TIME_60US_MASK BIT(5) +#define BT_HCI_LE_CS_T_IP1_TIME_80US_MASK BIT(6) + +#define BT_HCI_LE_CS_T_IP2_TIME_10US_MASK BIT(0) +#define BT_HCI_LE_CS_T_IP2_TIME_20US_MASK BIT(1) +#define BT_HCI_LE_CS_T_IP2_TIME_30US_MASK BIT(2) +#define BT_HCI_LE_CS_T_IP2_TIME_40US_MASK BIT(3) +#define BT_HCI_LE_CS_T_IP2_TIME_50US_MASK BIT(4) +#define BT_HCI_LE_CS_T_IP2_TIME_60US_MASK BIT(5) +#define BT_HCI_LE_CS_T_IP2_TIME_80US_MASK BIT(6) + +#define BT_HCI_LE_CS_T_FCS_TIME_15US_MASK BIT(0) +#define BT_HCI_LE_CS_T_FCS_TIME_20US_MASK BIT(1) +#define BT_HCI_LE_CS_T_FCS_TIME_30US_MASK BIT(2) +#define BT_HCI_LE_CS_T_FCS_TIME_40US_MASK BIT(3) +#define BT_HCI_LE_CS_T_FCS_TIME_50US_MASK BIT(4) +#define BT_HCI_LE_CS_T_FCS_TIME_60US_MASK BIT(5) +#define BT_HCI_LE_CS_T_FCS_TIME_80US_MASK BIT(6) +#define BT_HCI_LE_CS_T_FCS_TIME_100US_MASK BIT(7) +#define BT_HCI_LE_CS_T_FCS_TIME_1200US_MASK BIT(8) + +#define BT_HCI_LE_CS_T_PM_TIME_10US_MASK BIT(0) +#define BT_HCI_LE_CS_T_PM_TIME_20US_MASK BIT(1) + +#define BT_HCI_LE_CS_TX_SNR_CAPABILITY_18DB_MASK BIT(0) +#define BT_HCI_LE_CS_TX_SNR_CAPABILITY_21DB_MASK BIT(1) +#define BT_HCI_LE_CS_TX_SNR_CAPABILITY_24DB_MASK BIT(2) +#define BT_HCI_LE_CS_TX_SNR_CAPABILITY_27DB_MASK BIT(3) +#define BT_HCI_LE_CS_TX_SNR_CAPABILITY_30DB_MASK BIT(4) + +#define BT_HCI_EVT_LE_CS_READ_REMOTE_SUPPORTED_CAPABILITIES_COMPLETE 0x2C +struct bt_hci_evt_le_cs_read_remote_supported_capabilities_complete { + uint8_t status; + uint16_t conn_handle; + uint8_t num_config_supported; + uint16_t max_consecutive_procedures_supported; + uint8_t num_antennas_supported; + uint8_t max_antenna_paths_supported; + uint8_t roles_supported; + uint8_t modes_supported; + uint8_t rtt_capability; + uint8_t rtt_aa_only_n; + uint8_t rtt_sounding_n; + uint8_t rtt_random_payload_n; + uint16_t nadm_sounding_capability; + uint16_t nadm_random_capability; + uint8_t cs_sync_phys_supported; + uint16_t subfeatures_supported; + uint16_t t_ip1_times_supported; + uint16_t t_ip2_times_supported; + uint16_t t_fcs_times_supported; + uint16_t t_pm_times_supported; + uint8_t t_sw_time_supported; + uint8_t tx_snr_capability; +} __packed; + +#define BT_HCI_EVT_LE_CS_READ_REMOTE_FAE_TABLE_COMPLETE 0x2D +struct bt_hci_evt_le_cs_read_remote_fae_table_complete { + uint8_t status; + uint16_t conn_handle; + int8_t remote_fae_table[72]; +} __packed; + +#define BT_HCI_LE_CS_CONFIG_ACTION_REMOVED 0x00 +#define BT_HCI_LE_CS_CONFIG_ACTION_CREATED 0x01 + +#define BT_HCI_EVT_LE_CS_SECURITY_ENABLE_COMPLETE 0x2E +struct bt_hci_evt_le_cs_security_enable_complete { + uint8_t status; + uint16_t handle; +} __packed; + +#define BT_HCI_EVT_LE_CS_CONFIG_COMPLETE 0x2F +struct bt_hci_evt_le_cs_config_complete { + uint8_t status; + uint16_t handle; + uint8_t config_id; + uint8_t action; + uint8_t main_mode_type; + uint8_t sub_mode_type; + uint8_t min_main_mode_steps; + uint8_t max_main_mode_steps; + uint8_t main_mode_repetition; + uint8_t mode_0_steps; + uint8_t role; + uint8_t rtt_type; + uint8_t cs_sync_phy; + uint8_t channel_map[10]; + uint8_t channel_map_repetition; + uint8_t channel_selection_type; + uint8_t ch3c_shape; + uint8_t ch3c_jump; + uint8_t reserved; + uint8_t t_ip1_time; + uint8_t t_ip2_time; + uint8_t t_fcs_time; + uint8_t t_pm_time; +} __packed; + +#define BT_HCI_LE_CS_TEST_CONN_HANDLE 0x0FFF + +#define BT_HCI_LE_CS_PROCEDURE_DONE_STATUS_COMPLETE 0x0 +#define BT_HCI_LE_CS_PROCEDURE_DONE_STATUS_PARTIAL 0x1 +#define BT_HCI_LE_CS_PROCEDURE_DONE_STATUS_ABORTED 0xF + +#define BT_HCI_LE_CS_SUBEVENT_DONE_STATUS_COMPLETE 0x0 +#define BT_HCI_LE_CS_SUBEVENT_DONE_STATUS_PARTIAL 0x1 +#define BT_HCI_LE_CS_SUBEVENT_DONE_STATUS_ABORTED 0xF + +#define BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_NO_ABORT 0x0 +#define BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_LOCAL_HOST_OR_REMOTE_REQUEST 0x1 +#define BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_TOO_FEW_CHANNELS 0x2 +#define BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_CHMAP_INSTANT_PASSED 0x3 +#define BT_HCI_LE_CS_PROCEDURE_ABORT_REASON_UNSPECIFIED 0xF + +#define BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_NO_ABORT 0x0 +#define BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_LOCAL_HOST_OR_REMOTE_REQUEST 0x1 +#define BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_NO_CS_SYNC_RECEIVED 0x2 +#define BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_SCHED_CONFLICT 0x3 +#define BT_HCI_LE_CS_SUBEVENT_ABORT_REASON_UNSPECIFIED 0xF + +#define BT_HCI_LE_CS_SUBEVENT_RESULT_N_AP_IGNORED 0x00 +#define BT_HCI_LE_CS_SUBEVENT_RESULT_N_AP_1 0x01 +#define BT_HCI_LE_CS_SUBEVENT_RESULT_N_AP_2 0x02 +#define BT_HCI_LE_CS_SUBEVENT_RESULT_N_AP_3 0x03 +#define BT_HCI_LE_CS_SUBEVENT_RESULT_N_AP_4 0x04 + +#define BT_HCI_LE_CS_SUBEVENT_RESULT_FREQ_COMPENSATION_NOT_AVAILABLE 0xC000 + +#define BT_HCI_LE_CS_SUBEVENT_RESULT_PCT_NOT_AVAILABLE 0xFFFFFFFF + +#define BT_HCI_LE_CS_REF_POWER_LEVEL_UNAVAILABLE 0x7F + +#define BT_HCI_LE_CS_PCT_I_MASK 0x000FFF +#define BT_HCI_LE_CS_PCT_Q_MASK 0xFFF000 + +#define BT_HCI_LE_CS_TONE_QUALITY_HIGH 0x0 +#define BT_HCI_LE_CS_TONE_QUALITY_MED 0x1 +#define BT_HCI_LE_CS_TONE_QUALITY_LOW 0x2 +#define BT_HCI_LE_CS_TONE_QUALITY_UNAVAILABLE 0x3 + +#define BT_HCI_LE_CS_NOT_TONE_EXT_SLOT 0x0 +#define BT_HCI_LE_CS_TONE_EXT_SLOT_EXT_NOT_EXPECTED 0x1 +#define BT_HCI_LE_CS_TONE_EXT_SLOT_EXT_EXPECTED 0x2 + +#define BT_HCI_LE_CS_TIME_DIFFERENCE_NOT_AVAILABLE ((int16_t)0x8000) + +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_EXT_UNLIKELY 0x00 +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_VERY_UNLIKELY 0x01 +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_UNLIKELY 0x02 +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_POSSIBLE 0x03 +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_LIKELY 0x04 +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_VERY_LIKELY 0x05 +#define BT_HCI_LE_CS_PACKET_NADM_ATTACK_EXT_LIKELY 0x06 +#define BT_HCI_LE_CS_PACKET_NADM_UNKNOWN 0xFF + +#define BT_HCI_LE_CS_PACKET_QUALITY_AA_CHECK_SUCCESSFUL 0x0 +#define BT_HCI_LE_CS_PACKET_QUALITY_AA_CHECK_BIT_ERRORS_FOUND 0x1 +#define BT_HCI_LE_CS_PACKET_QUALITY_AA_CHECK_AA_NOT_FOUND 0x2 + +#define BT_HCI_LE_CS_PACKET_RSSI_NOT_AVAILABLE 0x7F + +#define BT_HCI_EVT_LE_CS_SUBEVENT_RESULT 0x31 +/** Subevent result step data format: Mode 0 Initiator */ +struct bt_hci_le_cs_step_data_mode_0_initiator { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t packet_quality_aa_check: 4; + uint8_t packet_quality_bit_errors: 4; +#else + uint8_t packet_quality_bit_errors: 4; + uint8_t packet_quality_aa_check: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t packet_rssi; + uint8_t packet_antenna; + uint16_t measured_freq_offset; +} __packed; + +/** Subevent result step data format: Mode 0 Reflector */ +struct bt_hci_le_cs_step_data_mode_0_reflector { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t packet_quality_aa_check: 4; + uint8_t packet_quality_bit_errors: 4; +#else + uint8_t packet_quality_bit_errors: 4; + uint8_t packet_quality_aa_check: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t packet_rssi; + uint8_t packet_antenna; +} __packed; + +/** Subevent result step data format: Mode 1 */ +struct bt_hci_le_cs_step_data_mode_1 { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t packet_quality_aa_check: 4; + uint8_t packet_quality_bit_errors: 4; +#else + uint8_t packet_quality_bit_errors: 4; + uint8_t packet_quality_aa_check: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t packet_nadm; + uint8_t packet_rssi; + union { + int16_t toa_tod_initiator; + int16_t tod_toa_reflector; + }; + uint8_t packet_antenna; +} __packed; + +/** Subevent result step data format: Mode 1 with sounding sequence RTT support */ +struct bt_hci_le_cs_step_data_mode_1_ss_rtt { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t packet_quality_aa_check: 4; + uint8_t packet_quality_bit_errors: 4; +#else + uint8_t packet_quality_bit_errors: 4; + uint8_t packet_quality_aa_check: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t packet_nadm; + uint8_t packet_rssi; + union { + int16_t toa_tod_initiator; + int16_t tod_toa_reflector; + }; + uint8_t packet_antenna; + uint8_t packet_pct1[4]; + uint8_t packet_pct2[4]; +} __packed; + + +/** Format for per-antenna path step data in modes 2 and 3 */ +struct bt_hci_le_cs_step_data_tone_info { + uint8_t phase_correction_term[3]; +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t quality_indicator: 4; + uint8_t extension_indicator: 4; +#else + uint8_t extension_indicator: 4; + uint8_t quality_indicator: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ +} __packed; + +/** Subevent result step data format: Mode 2 */ +struct bt_hci_le_cs_step_data_mode_2 { + uint8_t antenna_permutation_index; + struct bt_hci_le_cs_step_data_tone_info tone_info[]; +} __packed; + +/** Subevent result step data format: Mode 3 */ +struct bt_hci_le_cs_step_data_mode_3 { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t packet_quality_aa_check: 4; + uint8_t packet_quality_bit_errors: 4; +#else + uint8_t packet_quality_bit_errors: 4; + uint8_t packet_quality_aa_check: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t packet_nadm; + uint8_t packet_rssi; + union { + int16_t toa_tod_initiator; + int16_t tod_toa_reflector; + }; + uint8_t packet_antenna; + uint8_t antenna_permutation_index; + struct bt_hci_le_cs_step_data_tone_info tone_info[]; +} __packed; + +/** Subevent result step data format: Mode 3 with sounding sequence RTT support */ +struct bt_hci_le_cs_step_data_mode_3_ss_rtt { +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t packet_quality_aa_check: 4; + uint8_t packet_quality_bit_errors: 4; +#else + uint8_t packet_quality_bit_errors: 4; + uint8_t packet_quality_aa_check: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t packet_nadm; + uint8_t packet_rssi; + union { + int16_t toa_tod_initiator; + int16_t tod_toa_reflector; + }; + uint8_t packet_antenna; + uint8_t packet_pct1[4]; + uint8_t packet_pct2[4]; + uint8_t antenna_permutation_index; + struct bt_hci_le_cs_step_data_tone_info tone_info[]; +} __packed; + +struct bt_hci_evt_le_cs_subevent_result_step { + uint8_t step_mode; + uint8_t step_channel; + uint8_t step_data_length; + uint8_t step_data[]; +} __packed; + +struct bt_hci_evt_le_cs_subevent_result { + uint16_t conn_handle; + uint8_t config_id; + uint16_t start_acl_conn_event_counter; + uint16_t procedure_counter; + uint16_t frequency_compensation; + uint8_t reference_power_level; + uint8_t procedure_done_status; + uint8_t subevent_done_status; +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t procedure_abort_reason: 4; + uint8_t subevent_abort_reason: 4; +#else + uint8_t subevent_abort_reason: 4; + uint8_t procedure_abort_reason: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t num_antenna_paths; + uint8_t num_steps_reported; + uint8_t steps[]; +} __packed; + +#define BT_HCI_EVT_LE_CS_SUBEVENT_RESULT_CONTINUE 0x32 + +struct bt_hci_evt_le_cs_subevent_result_continue { + uint16_t conn_handle; + uint8_t config_id; + uint8_t procedure_done_status; + uint8_t subevent_done_status; +#ifdef CONFIG_LITTLE_ENDIAN + uint8_t procedure_abort_reason: 4; + uint8_t subevent_abort_reason: 4; +#else + uint8_t subevent_abort_reason: 4; + uint8_t procedure_abort_reason: 4; +#endif /* CONFIG_LITTLE_ENDIAN */ + uint8_t num_antenna_paths; + uint8_t num_steps_reported; + uint8_t steps[]; +} __packed; + +#define BT_HCI_EVT_LE_CS_TEST_END_COMPLETE 0x33 +struct bt_hci_evt_le_cs_test_end_complete { + uint8_t status; +} __packed; + +#define BT_HCI_EVT_LE_CS_PROCEDURE_ENABLE_COMPLETE 0x30 +struct bt_hci_evt_le_cs_procedure_enable_complete { + uint8_t status; + uint16_t handle; + uint8_t config_id; + uint8_t state; + uint8_t tone_antenna_config_selection; + uint8_t selected_tx_power; + uint8_t subevent_len[3]; + uint8_t subevents_per_event; + uint16_t subevent_interval; + uint16_t event_interval; + uint16_t procedure_interval; + uint16_t procedure_count; + uint16_t max_procedure_len; +} __packed; + /* Event mask bits */ #define BT_EVT_BIT(n) (1ULL << (n)) @@ -3178,6 +3918,7 @@ struct bt_hci_evt_le_biginfo_adv_report { #define BT_EVT_MASK_LE_PATH_LOSS_THRESHOLD BT_EVT_BIT(31) #define BT_EVT_MASK_LE_TRANSMIT_POWER_REPORTING BT_EVT_BIT(32) #define BT_EVT_MASK_LE_BIGINFO_ADV_REPORT BT_EVT_BIT(33) +#define BT_EVT_MASK_LE_SUBRATE_CHANGE BT_EVT_BIT(34) #define BT_EVT_MASK_LE_PER_ADV_SYNC_ESTABLISHED_V2 BT_EVT_BIT(35) #define BT_EVT_MASK_LE_PER_ADVERTISING_REPORT_V2 BT_EVT_BIT(36) @@ -3186,6 +3927,15 @@ struct bt_hci_evt_le_biginfo_adv_report { #define BT_EVT_MASK_LE_PER_ADV_RESPONSE_REPORT BT_EVT_BIT(39) #define BT_EVT_MASK_LE_ENH_CONN_COMPLETE_V2 BT_EVT_BIT(40) +#define BT_EVT_MASK_LE_CS_READ_REMOTE_SUPPORTED_CAPABILITIES_COMPLETE BT_EVT_BIT(43) +#define BT_EVT_MASK_LE_CS_READ_REMOTE_FAE_TABLE_COMPLETE BT_EVT_BIT(44) +#define BT_EVT_MASK_LE_CS_SECURITY_ENABLE_COMPLETE BT_EVT_BIT(45) +#define BT_EVT_MASK_LE_CS_CONFIG_COMPLETE BT_EVT_BIT(46) +#define BT_EVT_MASK_LE_CS_PROCEDURE_ENABLE_COMPLETE BT_EVT_BIT(47) +#define BT_EVT_MASK_LE_CS_SUBEVENT_RESULT BT_EVT_BIT(48) +#define BT_EVT_MASK_LE_CS_SUBEVENT_RESULT_CONTINUE BT_EVT_BIT(49) +#define BT_EVT_MASK_LE_CS_TEST_END_COMPLETE BT_EVT_BIT(50) + /** HCI Error Codes, BT Core Spec v5.4 [Vol 1, Part F]. */ #define BT_HCI_ERR_SUCCESS 0x00 #define BT_HCI_ERR_UNKNOWN_CMD 0x01 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/iso.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/iso.h index 1aad27be..fea94f62 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/iso.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/iso.h @@ -5,7 +5,7 @@ /* * Copyright (c) 2020 Intel Corporation - * Copyright (c) 2021 Nordic Semiconductor ASA + * Copyright (c) 2021-2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,10 +23,18 @@ * @{ */ -#include +#include + +#include +#include #include #include #include +#include +#include +#include +#include +#include #ifdef __cplusplus extern "C" { @@ -47,6 +55,16 @@ extern "C" { */ #define BT_ISO_SDU_BUF_SIZE(mtu) BT_BUF_ISO_SIZE(mtu) +/** + * Convert BIS index to bit + * + * The BIS indexes start from 0x01, so the lowest allowed bit is + * BIT(0) that represents index 0x01. To synchronize to e.g. BIS + * indexes 0x01 and 0x02, the bitfield value should be BIT(0) | BIT(1). + * As a general notation, to sync to BIS index N use BIT(N - 1). + */ +#define BT_ISO_BIS_INDEX_BIT(x) (BIT((x) - 1)) + /** Value to set the ISO data path over HCi. */ #define BT_ISO_DATA_PATH_HCI 0x00 @@ -123,6 +141,14 @@ extern "C" { /** Maximum pre-transmission offset */ #define BT_ISO_PTO_MAX 0x0FU +/** + * @brief Check if ISO BIS bitfield is valid (BT_ISO_BIS_INDEX_BIT(1)|..|BT_ISO_BIS_INDEX_BIT(31)) + * + * @param _bis_bitfield BIS index bitfield (uint32) + */ +#define BT_ISO_VALID_BIS_BITFIELD(_bis_bitfield) \ + ((_bis_bitfield) != 0U && (_bis_bitfield) <= BIT_MASK(BT_ISO_BIS_INDEX_MAX)) + /** * @brief Life-span states of ISO channel. Used only by internal APIs dealing with setting channel * to proper state depending on operational context. @@ -548,9 +574,10 @@ struct bt_iso_big_sync_param { /** * @brief Bitfield of the BISes to sync to * - * The BIS indexes start from 0x01, so the lowest allowed bit is - * BIT(1) that represents index 0x01. To synchronize to e.g. BIS - * indexes 0x01 and 0x02, the bitfield value should be BIT(1) | BIT(2). + * Use @ref BT_ISO_BIS_INDEX_BIT to convert BIS indexes to a bitfield. + * + * To synchronize to e.g. BIS indexes 0x01 and 0x02, this can be set to + * BT_ISO_BIS_INDEX_BIT(0x01) | BT_ISO_BIS_INDEX_BIT(0x02). */ uint32_t bis_bitfield; @@ -1076,6 +1103,42 @@ int bt_iso_chan_get_info(const struct bt_iso_chan *chan, struct bt_iso_info *inf */ int bt_iso_chan_get_tx_sync(const struct bt_iso_chan *chan, struct bt_iso_tx_info *info); +/** + * @brief Struct to hold the Broadcast Isochronous Group callbacks + * + * These can be registered for usage with bt_iso_big_register_cb(). + */ +struct bt_iso_big_cb { + /** + * @brief The BIG has started and all of the streams are ready for data + * + * @param big The started BIG + */ + void (*started)(struct bt_iso_big *big); + + /** + * @brief The BIG has stopped and none of the streams are ready for data + * + * @param big The stopped BIG + * @param reason The reason why the BIG stopped (see the BT_HCI_ERR_* values) + */ + void (*stopped)(struct bt_iso_big *big, uint8_t reason); + + /** @internal Internally used field for list handling */ + sys_snode_t _node; +}; + +/** + * @brief Registers callbacks for Broadcast Sources + * + * @param cb Pointer to the callback structure. + * + * @retval 0 on success + * @retval -EINVAL if @p cb is NULL + * @retval -EEXIST if @p cb is already registered + */ +int bt_iso_big_register_cb(struct bt_iso_big_cb *cb); + /** * @brief Creates a BIG as a broadcaster * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/l2cap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/l2cap.h index f471c925..8358d62c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/l2cap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/l2cap.h @@ -18,6 +18,7 @@ * @{ */ +#include #include #include @@ -83,6 +84,42 @@ extern "C" { */ #define BT_L2CAP_SDU_BUF_SIZE(mtu) BT_L2CAP_BUF_SIZE(BT_L2CAP_SDU_HDR_SIZE + (mtu)) +/** @brief L2CAP ECRED minimum MTU + * + * The minimum MTU for an L2CAP Enhanced Credit Based Connection. + * + * This requirement is inferred from text in Core 3.A.4.25 v6.0: + * + * L2CAP implementations shall support a minimum MTU size of 64 + * octets for these channels. + */ +#define BT_L2CAP_ECRED_MIN_MTU 64 + +/** @brief L2CAP ECRED minimum MPS + * + * The minimum MPS for an L2CAP Enhanced Credit Based Connection. + * + * This requirement is inferred from text in Core 3.A.4.25 v6.0: + * + * L2CAP implementations shall support a minimum MPS of 64 and may + * support an MPS up to 65533 octets for these channels. + */ +#define BT_L2CAP_ECRED_MIN_MPS 64 + +/** @brief The maximum number of channels in ECRED L2CAP signaling PDUs + * + * Currently, this is the maximum number of channels referred to in the + * following PDUs: + * - L2CAP_CREDIT_BASED_CONNECTION_REQ + * - L2CAP_CREDIT_BASED_RECONFIGURE_REQ + * + * @warning The commonality is inferred between the PDUs. The Bluetooth + * specification treats these as separate numbers and does now + * guarantee the same limit for potential future ECRED L2CAP signaling + * PDUs. + */ +#define BT_L2CAP_ECRED_CHAN_MAX_PER_REQ 5 + struct bt_l2cap_chan; /** @typedef bt_l2cap_chan_destroy_t @@ -272,7 +309,10 @@ struct bt_l2cap_br_chan { struct k_fifo _pdu_tx_queue; }; -/** @brief L2CAP Channel operations structure. */ +/** @brief L2CAP Channel operations structure. + * + * The object has to stay valid and constant for the lifetime of the channel. + */ struct bt_l2cap_chan_ops { /** @brief Channel connected callback * @@ -342,6 +382,15 @@ struct bt_l2cap_chan_ops { * @param chan The channel receiving data. * @param buf Buffer containing incoming data. * + * @note This callback is mandatory, unless + * @kconfig{CONFIG_BT_L2CAP_SEG_RECV} is enabled and seg_recv is + * supplied. + * + * If the application returns @c -EINPROGRESS, the application takes + * ownership of the reference in @p buf. (I.e. This pointer value can + * simply be given to @ref bt_l2cap_chan_recv_complete without any + * calls @ref net_buf_ref or @ref net_buf_unref.) + * * @return 0 in case of success or negative value in case of error. * @return -EINPROGRESS in case where user has to confirm once the data * has been processed by calling @@ -462,6 +511,9 @@ struct bt_l2cap_server { * This callback is called whenever a new incoming connection requires * authorization. * + * @warning It is the responsibility of this callback to zero out the + * parent of the chan object. + * * @param conn The connection that is requesting authorization * @param server Pointer to the server structure this callback relates to * @param chan Pointer to received the allocated channel @@ -516,6 +568,9 @@ int bt_l2cap_br_server_register(struct bt_l2cap_server *server); * each channel connected() callback will be called. If the connection is * rejected disconnected() callback is called instead. * + * @warning It is the responsibility of the caller to zero out the + * parents of the chan objects. + * * @param conn Connection object. * @param chans Array of channel objects. * @param psm Channel PSM to connect to. @@ -539,6 +594,52 @@ int bt_l2cap_ecred_chan_connect(struct bt_conn *conn, */ int bt_l2cap_ecred_chan_reconfigure(struct bt_l2cap_chan **chans, uint16_t mtu); +/** @brief Reconfigure Enhanced Credit Based L2CAP channels + * + * Experimental API to reconfigure L2CAP ECRED channels with explicit MPS and + * MTU values. + * + * Pend a L2CAP ECRED reconfiguration for up to 5 channels. All provided + * channels must share the same @ref bt_conn. + * + * This API cannot decrease the MTU of any channel, and it cannot decrease the + * MPS of any channel when more than one channel is provided. + * + * There is no dedicated callback for this operation, but whenever a peer + * responds to a reconfiguration request, each affected channel's + * reconfigured() callback is invoked. + * + * This function may block. + * + * @warning Known issue: The implementation returns -EBUSY if there already is + * an ongoing reconfigure operation on the same connection. The caller may try + * again later. There is no event signaling when the existing operation + * finishes. + * + * @warning Known issue: The implementation returns -ENOMEM when unable to + * allocate. The caller may try again later. There is no event signaling the + * availability of buffers. + * + * @kconfig_dep{CONFIG_BT_L2CAP_RECONFIGURE_EXPLICIT} + * + * @param chans Array of channels to reconfigure. Must be non-empty and + * contain at most 5 (@ref BT_L2CAP_ECRED_CHAN_MAX_PER_REQ) + * elements. + * @param chan_count Number of channels in the array. + * @param mtu Desired MTU. Must be at least @ref BT_L2CAP_ECRED_MIN_MTU. + * @param mps Desired MPS. Must be in range @ref BT_L2CAP_ECRED_MIN_MPS + * to @ref BT_L2CAP_RX_MTU. + * + * @retval 0 Successfully pended operation. + * @retval -EINVAL Bad arguments. See above requirements. + * @retval -ENOTCONN Connection object is not in connected state. + * @retval -EBUSY Another outgoing reconfiguration is pending on the same + * connection. + * @retval -ENOMEM Host is out of buffers. + */ +int bt_l2cap_ecred_chan_reconfigure_explicit(struct bt_l2cap_chan **chans, size_t chan_count, + uint16_t mtu, uint16_t mps); + /** @brief Connect L2CAP channel * * Connect L2CAP channel by PSM, once the connection is completed channel @@ -551,6 +652,9 @@ int bt_l2cap_ecred_chan_reconfigure(struct bt_l2cap_chan **chans, uint16_t mtu); * the location (address) of bt_l2cap_chan type object which is a member * of both transport dedicated objects. * + * @warning It is the responsibility of the caller to zero out the + * parent of the chan object. + * * @param conn Connection object. * @param chan Channel object. * @param psm Channel PSM to connect to. @@ -600,6 +704,10 @@ int bt_l2cap_chan_disconnect(struct bt_l2cap_chan *chan); * on the stack's global buffer pool (sized * @kconfig{CONFIG_BT_L2CAP_TX_BUF_COUNT}). * + * @warning The buffer's user_data _will_ be overwritten by this function. Do + * not store anything in it. As soon as a call to this function has been made, + * consider ownership of user_data transferred into the stack. + * * @note Buffer ownership is transferred to the stack in case of success, in * case of an error the caller retains the ownership of the buffer. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh.h index fc84814f..c4a211d6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh.h @@ -13,7 +13,7 @@ #include #include -#include +#include #include #include @@ -48,6 +48,8 @@ #include #include #include +#include +#include #include #endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/access.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/access.h index f1fca027..db477ee6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/access.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/access.h @@ -187,6 +187,10 @@ struct bt_mesh_elem { #define BT_MESH_MODEL_ID_REMOTE_PROV_SRV 0x0004 /** Remote Provisioning Client */ #define BT_MESH_MODEL_ID_REMOTE_PROV_CLI 0x0005 +/** Bridge Configuration Sever */ +#define BT_MESH_MODEL_ID_BRG_CFG_SRV 0x0008 +/** Bridge Configuration Client */ +#define BT_MESH_MODEL_ID_BRG_CFG_CLI 0x0009 /** Private Beacon Server */ #define BT_MESH_MODEL_ID_PRIV_BEACON_SRV 0x000a /** Private Beacon Client */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_cli.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_cli.h index 9b591cfd..574ec827 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_cli.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_cli.h @@ -282,6 +282,10 @@ struct blob_cli_broadcast_ctx { * and broadcast_complete calls. */ bool is_inited; + /* Defines a time in ms by which the broadcast API postpones sending the message to a next + * target or completing the broadcast. + */ + uint32_t post_send_delay_ms; }; /** INTERNAL_HIDDEN @endcond */ @@ -299,7 +303,7 @@ struct bt_mesh_blob_cli { struct k_work_delayable retry; /* Represents Client Timeout timer in a timestamp. Used in Pull mode only. */ int64_t cli_timestamp; - struct k_work complete; + struct k_work_delayable complete; uint16_t pending; uint8_t retries; uint8_t sending : 1, @@ -309,6 +313,7 @@ struct bt_mesh_blob_cli { const struct bt_mesh_blob_io *io; const struct bt_mesh_blob_cli_inputs *inputs; const struct bt_mesh_blob_xfer *xfer; + uint32_t chunk_interval_ms; uint16_t block_count; uint16_t chunk_idx; uint16_t mtu_size; @@ -419,6 +424,22 @@ uint8_t bt_mesh_blob_cli_xfer_progress_active_get(struct bt_mesh_blob_cli *cli); */ bool bt_mesh_blob_cli_is_busy(struct bt_mesh_blob_cli *cli); +/** @brief Set chunk sending interval in ms + * + * This function is optional, and can be used to define how fast chunks are sent in the BLOB Client + * Model. + * Without an added delay, for example a Bluetooth Mesh DFU can cause network blockage by + * constantly sending the next chunks, especially if the chunks are sent to group addresses or + * multiple unicast addresses. + * + * @note: Big intervals may cause timeouts. Increasing the @c timeout_base accordingly can + * circumvent this. + * + * @param cli BLOB Transfer Client instance. + * @param interval_ms the delay before each chunk is sent out in ms. + */ +void bt_mesh_blob_cli_set_chunk_interval_ms(struct bt_mesh_blob_cli *cli, uint32_t interval_ms); + /** @cond INTERNAL_HIDDEN */ extern const struct bt_mesh_model_op _bt_mesh_blob_cli_op[]; extern const struct bt_mesh_model_cb _bt_mesh_blob_cli_cb; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_srv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_srv.h index 92c809bd..8a0c6b67 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_srv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/blob_srv.h @@ -127,7 +127,7 @@ struct bt_mesh_blob_srv_cb { const struct bt_mesh_blob_io **io); }; -/** @brief BLOB Transfer Server instance. */ +/** @brief BLOB Transfer Server model instance. */ struct bt_mesh_blob_srv { /** Event handler callbacks. */ const struct bt_mesh_blob_srv_cb *cb; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg.h new file mode 100644 index 00000000..754ecc9e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_H__ +#define ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bt_mesh_brg_cfg Bridge Configuration common header + * @ingroup bt_mesh + * @{ + */ + +/** Subnet Bridge states */ +enum bt_mesh_brg_cfg_state { + /** Subnet bridge functionality is disabled. */ + BT_MESH_BRG_CFG_DISABLED, + /** Subnet bridge state functionality is enabled. */ + BT_MESH_BRG_CFG_ENABLED, +}; + +/* Bridging from Addr1 to Addr2. */ +#define BT_MESH_BRG_CFG_DIR_ONEWAY 1 +/* Bidirectional bridging between Addr1 and Addr2. */ +#define BT_MESH_BRG_CFG_DIR_TWOWAY 2 + +/** Bridging Table state entry corresponding to a entry in the Bridging Table. */ +struct bt_mesh_brg_cfg_table_entry { + /** Allowed directions for the bridged traffic (or bridged traffic not allowed) */ + uint8_t directions; + /** NetKey Index of the first subnet */ + uint16_t net_idx1; + /** NetKey Index of the second subnet */ + uint16_t net_idx2; + /** Address of the node in the first subnet */ + uint16_t addr1; + /** Address of the node in the second subnet */ + uint16_t addr2; +}; + +/** Bridging Table Status response */ +struct bt_mesh_brg_cfg_table_status { + /** Status Code of the requesting message */ + uint8_t status; + /** Requested Bridging Table entry */ + struct bt_mesh_brg_cfg_table_entry entry; +}; + +/** Used to filter set of pairs of NetKey Indexes from the Bridging Table */ +struct bt_mesh_brg_cfg_filter_netkey { + uint16_t filter: 2, /* Filter applied to the set of pairs of NetKey Indexes */ + prohibited: 2, /* Prohibited */ + net_idx: 12; /* NetKey Index used for filtering or ignored */ +}; + +/** Bridged Subnets List response */ +struct bt_mesh_brg_cfg_subnets_list { + /** Filter applied NetKey Indexes, and NetKey Index used for filtering. */ + struct bt_mesh_brg_cfg_filter_netkey net_idx_filter; + /** Start offset in units of bridges */ + uint8_t start_idx; + /** Pointer to allocated buffer for storing filtered of NetKey Indexes */ + struct net_buf_simple *list; +}; + +/** Bridging Table List response */ +struct bt_mesh_brg_cfg_table_list { + /** Status Code of the requesting message */ + uint8_t status; + /** NetKey Index of the first subnet */ + uint16_t net_idx1; + /** NetKey Index of the second subnet */ + uint16_t net_idx2; + /** Start offset in units of bridging table state entries */ + uint16_t start_idx; + /** Pointer to allocated buffer for storing list of bridged addresses and directions */ + struct net_buf_simple *list; +}; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg_cli.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg_cli.h new file mode 100644 index 00000000..37666ac6 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg_cli.h @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_CLI_H__ +#define ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_CLI_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bt_mesh_brg_cfg_cli Bridge Configuration Client Model + * @ingroup bt_mesh + * @{ + * @brief API for the Bluetooth Mesh Bridge Configuration Client model + */ + +struct bt_mesh_brg_cfg_cli; + +/** + * @brief Bridge Configuration Client model Composition Data entry. + * + * @param _cli Pointer to a @ref bt_mesh_brg_cfg_cli instance. + */ +#define BT_MESH_MODEL_BRG_CFG_CLI(_cli) \ + BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_CLI, _bt_mesh_brg_cfg_cli_op, NULL, _cli, \ + &_bt_mesh_brg_cfg_cli_cb) + +/** Mesh Bridge Configuration Client Status messages callback */ +struct bt_mesh_brg_cfg_cli_cb { + /** @brief Optional callback for Subnet Bridge Status message. + * + * Handles received Subnet Bridge Status messages from a Bridge + * Configuration Server. + + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param status Status received from the server. + */ + void (*bridge_status)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + enum bt_mesh_brg_cfg_state status); + + /** @brief Optional callback for Bridging Table Size Status message. + * + * Handles received Bridging Table Size Status messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param size Size received from the server. + */ + void (*table_size_status)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, uint16_t size); + + /** @brief Optional callback for Bridging Table Status message. + * + * Handles received Bridging Table status messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param rsp Response received from the Bridging Configuration Server. + */ + void (*table_status)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + struct bt_mesh_brg_cfg_table_status *rsp); + + /** @brief Optional callback for Bridged Subnets List message. + * + * Handles received Bridged Subnets List messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param rsp Response received from the Bridging Configuration Server. + */ + void (*subnets_list)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + struct bt_mesh_brg_cfg_subnets_list *rsp); + + /** @brief Optional callback for Bridging Table List message. + * + * Handles received Bridging Table List messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param rsp Response received from the Bridging Configuration Server. + */ + void (*table_list)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + struct bt_mesh_brg_cfg_table_list *rsp); +}; + +/** Bridge Configuration Client Model Context */ +struct bt_mesh_brg_cfg_cli { + /** Bridge Configuration model entry pointer */ + const struct bt_mesh_model *model; + + /** Event handler callbacks */ + const struct bt_mesh_brg_cfg_cli_cb *cb; + + /* Internal parameters for tracking message responses. */ + struct bt_mesh_msg_ack_ctx ack_ctx; +}; + +/** @brief Sends a Subnet Bridge Get message to the given destination address + * + * This function sends a Subnet Bridge Get message to the given destination + * address to query the value of the Subnet Bridge state of a subnet. The + * Subnet Bridge state indicates whether the subnet bridged feature is enabled + * or not. The function expects a Subnet Bridge Status message as a response + * from the destination node. + * + * This method can be used asynchronously by setting @p status as NULL. This + * way the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param status Status response parameter, returns one of + * @ref BT_MESH_BRG_CFG_DISABLED or + * @ref BT_MESH_BRG_CFG_ENABLED on success. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_get(uint16_t net_idx, uint16_t addr, enum bt_mesh_brg_cfg_state *status); + +/** @brief Sends a Subnet Bridge Set message to the given destination address + * with the given parameters + * + * This function sends a Subnet Bridge Set message to the given destination + * address with the given parameters to set the value of the Subnet Bridge + * state of a subnet. The Subnet Bridge state indicates whether the subnet + * bridge feature is enabled or not. The function expects a Subnet Bridge + * Status message as a response from the destination node. + * + * This method can be used asynchronously by setting @p status as NULL. This + * way the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param val Value to set the Subnet Bridge state to. Must be one of + * @ref BT_MESH_BRG_CFG_DISABLED or + * @ref BT_MESH_BRG_CFG_ENABLED. + * @param status Status response parameter, returns one of + * @ref BT_MESH_BRG_CFG_DISABLED or + * @ref BT_MESH_BRG_CFG_ENABLED on success. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_set(uint16_t net_idx, uint16_t addr, enum bt_mesh_brg_cfg_state val, + enum bt_mesh_brg_cfg_state *status); + +/** @brief Sends a Bridging Table Size Get message to the given destination + * address with the given parameters + * + * This function sends a Bridging Table Size Get message to the given + * destination address with the given parameters to get the size of the Bridging + * Table of the node. The Bridging Table size indicates the maximum number of + * entries that can be stored in the Bridging Table. The function expects a + * Bridging Table Size Status message as a response from the destination node. + * + * This method can be used asynchronously by setting @p size as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param size Bridging Table size response parameter. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_table_size_get(uint16_t net_idx, uint16_t addr, uint16_t *size); + +/** @brief Sends a Bridging Table Add message to the given destination address + * with the given parameters + * + * This function sends a Bridging Table Add message to the given destination + * address with the given parameters to add an entry to the Bridging Table. The + * Bridging Table contains the net keys and addresses that are authorized to be + * bridged by the node. The function expects a Bridging Table Status message as + * a response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param entry Pointer to bridging Table entry to add. + * @param rsp Status response parameter + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_table_add(uint16_t net_idx, uint16_t addr, + struct bt_mesh_brg_cfg_table_entry *entry, + struct bt_mesh_brg_cfg_table_status *rsp); + +/** @brief Sends a Bridging Table Remove message to the given destination + * address with the given parameters + * + * This function sends a Bridging Table Remove message to the given destination + * address with the given parameters to remove an entry from the Bridging + * Table. The Bridging Table contains the net keys and addresses that are + * authorized to be bridged by the node. The function expects a Bridging Table + * Status message as a response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param net_idx1 NetKey Index of the first subnet + * @param net_idx2 NetKey Index of the second subnet + * @param addr1 Address of the node in the first subnet + * @param addr2 Address of the node in the second subnet + * @param rsp Pointer to a struct storing the received response from the + * server, or NULL to not wait for a response. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_table_remove(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, + uint16_t net_idx2, uint16_t addr1, uint16_t addr2, + struct bt_mesh_brg_cfg_table_status *rsp); + +/** @brief Sends a Bridged Subnets Get message to the given destination address + * with the given parameters + * + * This function sends a Bridged Subnets Get message to the given destination + * address with the given parameters to get the list of subnets that are + * bridged by the node. The function expects a Bridged Subnets List message as + * a response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * When @c rsp is set, the user is responsible for providing a buffer for the + * filtered set of N pairs of NetKey Indexes in + * @ref bt_mesh_brg_cfg_subnets_list::list. If a buffer is not provided, the + * bridged subnets won't be copied. + + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param filter_net_idx Filter and NetKey Index used for filtering + * @param start_idx Start offset to read in units of Bridging Table state entries + * @param rsp Pointer to a struct storing the received response + * from the server, or NULL to not wait for a response. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_subnets_get(uint16_t net_idx, uint16_t addr, + struct bt_mesh_brg_cfg_filter_netkey filter_net_idx, + uint8_t start_idx, struct bt_mesh_brg_cfg_subnets_list *rsp); + +/** @brief Sends a Bridging Table Get message to the given destination address + * with the given parameters + * + * This function sends a Bridging Table Get message to the given destination + * address with the given parameters to get the contents of the Bridging Table. + * The Bridging Table contains the addresses that are authorized to be bridged + * by the node. The function expects a Bridging Table List message as a + * response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * When @c rsp is set, the user is responsible for providing a buffer for the + * filtered set of N pairs of NetKey Indexes in + * @ref bt_mesh_brg_cfg_table_list::list. If a buffer is not provided, + * the bridged addresses won't be copied. If a buffer size is shorter than + * received list, only those many entries that fit in the buffer will be copied + * from the list, and rest will be discarded. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param net_idx1 NetKey Index of the first subnet. + * @param net_idx2 NetKey Index of the second subnet. + * @param start_idx Start offset to read in units of Bridging Table state entries. + * @param rsp Pointer to a struct storing the received response from the + * server, or NULL to not wait for a response. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_table_get(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, + uint16_t net_idx2, uint16_t start_idx, + struct bt_mesh_brg_cfg_table_list *rsp); + +/** @brief Get the current transmission timeout value. + * + * @return The configured transmission timeout in milliseconds. + */ +int32_t bt_mesh_brg_cfg_cli_timeout_get(void); + +/** @brief Set the transmission timeout value. + * + * @param timeout The new transmission timeout. + */ +void bt_mesh_brg_cfg_cli_timeout_set(int32_t timeout); + +/** @cond INTERNAL_HIDDEN */ +extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_cli_op[]; +extern const struct bt_mesh_model_cb _bt_mesh_brg_cfg_cli_cb; +/** @endcond */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_CLI_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg_srv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg_srv.h new file mode 100644 index 00000000..0440be6f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/brg_cfg_srv.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Bluetooth Mesh Bridge Configuration Server Model APIs. + */ +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_SRV_H__ +#define ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_SRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bt_mesh_brg_cfg_srv Bridge Configuration Server Model + * @ingroup bt_mesh + * @{ + * @brief API for the Bluetooth Mesh Bridge Configuration Server model + */ + +/** + * + * @brief Bridge Configuration Server model Composition Data entry. + */ +#define BT_MESH_MODEL_BRG_CFG_SRV \ + BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_SRV, _bt_mesh_brg_cfg_srv_op, NULL, NULL, \ + &_bt_mesh_brg_cfg_srv_cb) + +/** @cond INTERNAL_HIDDEN */ +extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[]; +extern const struct bt_mesh_model_cb _bt_mesh_brg_cfg_srv_cb; +/** @endcond */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_SRV_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/msg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/msg.h index 8a7ce1a7..d5d93111 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/msg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/mesh/msg.h @@ -18,7 +18,7 @@ */ #include -#include +#include #ifdef __cplusplus extern "C" { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/bas.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/bas.h index 59413346..c6215901 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/bas.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/bas.h @@ -1,4 +1,5 @@ /* + * Copyright (c) 2024 Demant A/S * Copyright (c) 2018 Nordic Semiconductor ASA * Copyright (c) 2016 Intel Corporation * @@ -19,11 +20,187 @@ */ #include +#include #ifdef __cplusplus extern "C" { #endif +/** + * @brief Battery Critical Status Characteristic flags. + * + * Enumeration for the flags indicating the presence + * of various fields in the Battery Critical Status characteristic. + */ +enum bt_bas_bcs_flags { + /** Battery Critical Status Bit 0: Critical Power State */ + BT_BAS_BCS_BATTERY_CRITICAL_STATE = BIT(0), + + /** Battery Critical Status Bit 1: Immediate Service Required */ + BT_BAS_BCS_IMMEDIATE_SERVICE_REQUIRED = BIT(1), +}; + +/** + * @brief Battery Level Status Characteristic flags. + * + * Enumeration for the flags indicating the presence + * of various fields in the Battery Level Status characteristic. + */ +enum bt_bas_bls_flags { + /** Bit indicating that the Battery Level Status identifier is present. */ + BT_BAS_BLS_FLAG_IDENTIFIER_PRESENT = BIT(0), + + /** Bit indicating that the Battery Level is present. */ + BT_BAS_BLS_FLAG_BATTERY_LEVEL_PRESENT = BIT(1), + + /** Bit indicating that additional status information is present. */ + BT_BAS_BLS_FLAG_ADDITIONAL_STATUS_PRESENT = BIT(2), +}; + +/** @brief Battery Present Status + * + * Enumeration for the presence of the battery. + */ +enum bt_bas_bls_battery_present { + /** Battery is not present. */ + BT_BAS_BLS_BATTERY_NOT_PRESENT = 0, + + /** Battery is present. */ + BT_BAS_BLS_BATTERY_PRESENT = 1 +}; + +/** @brief Wired External Power Source Status + * + * Enumeration for the status of the wired external power source. + */ +enum bt_bas_bls_wired_power_source { + /** Wired external power source is not connected. */ + BT_BAS_BLS_WIRED_POWER_NOT_CONNECTED = 0, + + /** Wired external power source is connected. */ + BT_BAS_BLS_WIRED_POWER_CONNECTED = 1, + + /** Wired external power source status is unknown. */ + BT_BAS_BLS_WIRED_POWER_UNKNOWN = 2 +}; + +/** @brief Wireless External Power Source Status + * + * Enumeration for the status of the wireless external power source. + */ +enum bt_bas_bls_wireless_power_source { + /** Wireless external power source is not connected. */ + BT_BAS_BLS_WIRELESS_POWER_NOT_CONNECTED = 0, + + /** Wireless external power source is connected. */ + BT_BAS_BLS_WIRELESS_POWER_CONNECTED = 1, + + /** Wireless external power source status is unknown. */ + BT_BAS_BLS_WIRELESS_POWER_UNKNOWN = 2 +}; + +/** @brief Battery Charge State + * + * Enumeration for the charge state of the battery. + */ +enum bt_bas_bls_battery_charge_state { + /** Battery charge state is unknown. */ + BT_BAS_BLS_CHARGE_STATE_UNKNOWN = 0, + + /** Battery is currently charging. */ + BT_BAS_BLS_CHARGE_STATE_CHARGING = 1, + + /** Battery is discharging actively. */ + BT_BAS_BLS_CHARGE_STATE_DISCHARGING_ACTIVE = 2, + + /** Battery is discharging but inactive. */ + BT_BAS_BLS_CHARGE_STATE_DISCHARGING_INACTIVE = 3 +}; + +/** @brief Battery Charge Level + * + * Enumeration for the level of charge in the battery. + */ +enum bt_bas_bls_battery_charge_level { + /** Battery charge level is unknown. */ + BT_BAS_BLS_CHARGE_LEVEL_UNKNOWN = 0, + + /** Battery charge level is good. */ + BT_BAS_BLS_CHARGE_LEVEL_GOOD = 1, + + /** Battery charge level is low. */ + BT_BAS_BLS_CHARGE_LEVEL_LOW = 2, + + /** Battery charge level is critical. */ + BT_BAS_BLS_CHARGE_LEVEL_CRITICAL = 3 +}; + +/** @brief Battery Charge Type + * + * Enumeration for the type of charging applied to the battery. + */ +enum bt_bas_bls_battery_charge_type { + /** Battery charge type is unknown or not charging. */ + BT_BAS_BLS_CHARGE_TYPE_UNKNOWN = 0, + + /** Battery is charged using constant current. */ + BT_BAS_BLS_CHARGE_TYPE_CONSTANT_CURRENT = 1, + + /** Battery is charged using constant voltage. */ + BT_BAS_BLS_CHARGE_TYPE_CONSTANT_VOLTAGE = 2, + + /** Battery is charged using trickle charge. */ + BT_BAS_BLS_CHARGE_TYPE_TRICKLE = 3, + + /** Battery is charged using float charge. */ + BT_BAS_BLS_CHARGE_TYPE_FLOAT = 4 +}; + +/** @brief Charging Fault Reason + * + * Enumeration for the reasons of charging faults. + */ +enum bt_bas_bls_charging_fault_reason { + /** No charging fault. */ + BT_BAS_BLS_FAULT_REASON_NONE = 0, + + /** Charging fault due to battery issue. */ + BT_BAS_BLS_FAULT_REASON_BATTERY = BIT(0), + + /** Charging fault due to external power source issue. */ + BT_BAS_BLS_FAULT_REASON_EXTERNAL_POWER = BIT(1), + + /** Charging fault for other reasons. */ + BT_BAS_BLS_FAULT_REASON_OTHER = BIT(2) +}; + +/** @brief Service Required Status + * + * Enumeration for whether the service is required. + */ +enum bt_bas_bls_service_required { + /** Service is not required. */ + BT_BAS_BLS_SERVICE_REQUIRED_FALSE = 0, + + /** Service is required. */ + BT_BAS_BLS_SERVICE_REQUIRED_TRUE = 1, + + /** Service requirement is unknown. */ + BT_BAS_BLS_SERVICE_REQUIRED_UNKNOWN = 2 +}; + +/** @brief Battery Fault Status + * + * Enumeration for the fault status of the battery. + */ +enum bt_bas_bls_battery_fault { + /** No battery fault. */ + BT_BAS_BLS_BATTERY_FAULT_NO = 0, + + /** Battery fault present. */ + BT_BAS_BLS_BATTERY_FAULT_YES = 1 +}; + /** @brief Read battery level value. * * Read the characteristic value of the battery level @@ -43,6 +220,81 @@ uint8_t bt_bas_get_battery_level(void); */ int bt_bas_set_battery_level(uint8_t level); +/** + * @brief Set the battery present status. + * + * @param present The battery present status to set. + */ +void bt_bas_bls_set_battery_present(enum bt_bas_bls_battery_present present); + +/** + * @brief Set the wired external power source status. + * + * @param source The wired external power source status to set. + */ +void bt_bas_bls_set_wired_external_power_source(enum bt_bas_bls_wired_power_source source); + +/** + * @brief Set the wireless external power source status. + * + * @param source The wireless external power source status to set. + */ +void bt_bas_bls_set_wireless_external_power_source(enum bt_bas_bls_wireless_power_source source); + +/** + * @brief Set the battery charge state. + * + * @param state The battery charge state to set. + */ +void bt_bas_bls_set_battery_charge_state(enum bt_bas_bls_battery_charge_state state); + +/** + * @brief Set the battery charge level. + * + * @param level The battery charge level to set. + */ +void bt_bas_bls_set_battery_charge_level(enum bt_bas_bls_battery_charge_level level); + +/** + * @brief Set the battery charge type. + * + * @param type The battery charge type to set. + */ +void bt_bas_bls_set_battery_charge_type(enum bt_bas_bls_battery_charge_type type); + +/** + * @brief Set the charging fault reason. + * + * @param reason The charging fault reason to set. + */ +void bt_bas_bls_set_charging_fault_reason(enum bt_bas_bls_charging_fault_reason reason); + +/** + * @brief Set the identifier of the battery. + * + * @kconfig_dep{CONFIG_BT_BAS_BLS_IDENTIFIER_PRESENT} + * + * @param identifier Identifier to set. + */ +void bt_bas_bls_set_identifier(uint16_t identifier); + +/** + * @brief Set the service required status. + * + * @kconfig_dep{CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT} + * + * @param value Service required status to set. + */ +void bt_bas_bls_set_service_required(enum bt_bas_bls_service_required value); + +/** + * @brief Set the battery fault status. + * + * @kconfig_dep{CONFIG_BT_BAS_BLS_ADDITIONAL_STATUS_PRESENT} + * + * @param value Battery fault status to set. + */ +void bt_bas_bls_set_battery_fault(enum bt_bas_bls_battery_fault value); #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/cts.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/cts.h new file mode 100644 index 00000000..5b1c780f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/cts.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2024 Croxel Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_SERVICES_CTS_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_SERVICES_CTS_H_ + +/** + * @brief Current Time Service (CTS) + * @defgroup bt_cts Current Time Service (CTS) + * @ingroup bluetooth + * @{ + * + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief CTS time update reason bits as defined in the specification + */ +enum bt_cts_update_reason { + /* Unknown reason of update no bit is set */ + BT_CTS_UPDATE_REASON_UNKNOWN = 0, + /* When time is changed manually e.g. through UI */ + BT_CTS_UPDATE_REASON_MANUAL = BIT(0), + /* If time is changed through external reference */ + BT_CTS_UPDATE_REASON_EXTERNAL_REF = BIT(1), + /* time changed due to timezone adjust */ + BT_CTS_UPDATE_REASON_TIME_ZONE_CHANGE = BIT(2), + /* time changed due to dst offset change */ + BT_CTS_UPDATE_REASON_DAYLIGHT_SAVING = BIT(3), +}; + +/** + * @brief Current Time service data format, Please refer to + * specifications for more details + */ +struct bt_cts_time_format { + uint16_t year; + uint8_t mon; + uint8_t mday; + uint8_t hours; + uint8_t min; + uint8_t sec; + uint8_t wday; + uint8_t fractions256; + uint8_t reason; +} __packed; + +/** @brief Current Time Service callback structure */ +struct bt_cts_cb { + /** @brief Current Time Service notifications changed + * + * @param enabled True if notifications are enabled, false if disabled + */ + void (*notification_changed)(bool enabled); + + /** + * @brief The Current Time has been updated by a peer. + * It is the responsibility of the application to store the new time. + * + * @param cts_time [IN] updated time + * + * @return 0 application has decoded it successfully + * @return negative error codes on failure + * + */ + int (*cts_time_write)(struct bt_cts_time_format *cts_time); + + /** + * @brief When current time Read request or notification is triggered, CTS uses + * this callback to retrieve current time information from application. Application + * must implement it and provide cts formatted current time information + * + * @note this callback is mandatory + * + * @param cts_time [IN] updated time + * + * @return 0 application has encoded it successfully + * @return negative error codes on failure + */ + int (*fill_current_cts_time)(struct bt_cts_time_format *cts_time); +}; + +/** + * @brief This API should be called at application init. + * it is safe to call this API before or after bt_enable API + * + * @param cb pointer to required callback + * + * @return 0 on success + * @return negative error codes on failure + */ +int bt_cts_init(const struct bt_cts_cb *cb); + +/** + * @brief Notify all connected clients that have enabled the + * current time update notification + * + * @param reason update reason to be sent to the clients + * + * @return 0 on success + * @return negative error codes on failure + */ +int bt_cts_send_notification(enum bt_cts_update_reason reason); + +/** + * @brief Helper API to decode CTS formatted time into milliseconds since epoch + * + * @note @kconfig{CONFIG_BT_CTS_HELPER_API} needs to be enabled to use this API. + * + * @param ct_time [IN] cts time formatted time + * @param unix_ms [OUT] pointer to store parsed millisecond since epoch + * + * @return 0 on success + * @return negative error codes on failure + */ +int bt_cts_time_to_unix_ms(const struct bt_cts_time_format *ct_time, int64_t *unix_ms); + +/** + * @brief Helper API to encode milliseconds since epoch to CTS formatted time + * + * @note @kconfig{CONFIG_BT_CTS_HELPER_API} needs to be enabled to use this API. + * + * @param ct_time [OUT] Pointer to store CTS formatted time + * @param unix_ms [IN] milliseconds since epoch to be converted + * + * @return 0 on success + * @return negative error codes on failure + */ +int bt_cts_time_from_unix_ms(struct bt_cts_time_format *ct_time, int64_t unix_ms); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_SERVICES_CTS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/hrs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/hrs.h index f19b2924..52897037 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/hrs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/services/hrs.h @@ -25,6 +25,11 @@ extern "C" { #endif +/** + * @brief Server shall restart the accumulation of energy expended from zero + */ +#define BT_HRS_CONTROL_POINT_RESET_ENERGY_EXPANDED_REQ 0x01 + /** @brief Heart rate service callback structure */ struct bt_hrs_cb { /** @brief Heart rate notifications changed @@ -34,6 +39,22 @@ struct bt_hrs_cb { */ void (*ntf_changed)(bool enabled); + /** + * @brief Heart rate control point write callback + * + * @note if Server supports the Energy Expended feature then application + * shall implement and support @ref BT_HRS_CONTROL_POINT_RESET_ENERGY_EXPANDED_REQ + * request code + * + * @param request control point request code + * + * @return 0 on successful handling of control point request + * @return -ENOTSUP if not supported. It can be used to pass handling to other + * listeners in case of multiple listeners + * @return other negative error codes will result in immediate error response + */ + int (*ctrl_point_write)(uint8_t request); + /** Internal member to form a list of callbacks */ sys_snode_t _node; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/testing.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/testing.h index 74806a53..3ac48c7b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/testing.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/testing.h @@ -1,106 +1,27 @@ -/** - * @file testing.h - * @brief Internal API for Bluetooth testing. - */ - -/* - * Copyright (c) 2017 Intel Corporation - * +/* Copyright (c) 2024 Nordic Semiconductor ASA * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_BLUETOOTH_TESTING_H_ -#define ZEPHYR_INCLUDE_BLUETOOTH_TESTING_H_ - -#include -#if defined(CONFIG_BT_MESH) -#include -#endif /* CONFIG_BT_MESH */ - -/** - * @brief Bluetooth testing - * @defgroup bt_test_cb Bluetooth testing callbacks - * @ingroup bluetooth - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @brief Bluetooth Testing callbacks structure. - * - * Callback structure to be used for Bluetooth testing purposes. - * Allows access to Bluetooth stack internals, not exposed by public API. - */ -struct bt_test_cb { -#if defined(CONFIG_BT_MESH) - void (*mesh_net_recv)(uint8_t ttl, uint8_t ctl, uint16_t src, uint16_t dst, - const void *payload, size_t payload_len); - void (*mesh_model_recv)(uint16_t src, uint16_t dst, const void *payload, - size_t payload_len); - void (*mesh_model_bound)(uint16_t addr, const struct bt_mesh_model *model, - uint16_t key_idx); - void (*mesh_model_unbound)(uint16_t addr, const struct bt_mesh_model *model, - uint16_t key_idx); - void (*mesh_prov_invalid_bearer)(uint8_t opcode); - void (*mesh_trans_incomp_timer_exp)(void); -#endif /* CONFIG_BT_MESH */ - - sys_snode_t node; -}; - -/** Register callbacks for Bluetooth testing purposes - * - * @param cb bt_test_cb callback structure +/** @brief Internal testing interfaces for Bluetooth + * @file + * @internal * - * @retval 0 Success. - * @retval -EEXIST if @p cb was already registered. + * The interfaces in this file are internal and not stable. */ -int bt_test_cb_register(struct bt_test_cb *cb); -/** Unregister callbacks for Bluetooth testing purposes - * - * @param cb bt_test_cb callback structure - */ -void bt_test_cb_unregister(struct bt_test_cb *cb); +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_TESTING_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_TESTING_H_ -/** Send Friend Subscription List Add message. - * - * Used by Low Power node to send the group address for which messages are to - * be stored by Friend node. - * - * @param group Group address - * - * @return Zero on success or (negative) error code otherwise. - */ -int bt_test_mesh_lpn_group_add(uint16_t group); +#include -/** Send Friend Subscription List Remove message. +/** @brief Hook for `acl_in_pool.destroy` * - * Used by Low Power node to remove the group addresses from Friend node - * subscription list. Messages sent to those addresses will not be stored - * by Friend node. + * Weak-function interface. The user can simply define this + * function, and it will automatically become the event + * listener. * - * @param groups Group addresses - * @param groups_count Group addresses count - * - * @return Zero on success or (negative) error code otherwise. - */ -int bt_test_mesh_lpn_group_remove(uint16_t *groups, size_t groups_count); - -/** Clear replay protection list cache. - * - * @return Zero on success or (negative) error code otherwise. + * @kconfig_dep{CONFIG_BT_TESTING} */ -int bt_test_mesh_rpl_clear(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif +void bt_testing_trace_event_acl_pool_destroy(struct net_buf *buf); #endif /* ZEPHYR_INCLUDE_BLUETOOTH_TESTING_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/uuid.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/uuid.h index 24232f04..aa0413dc 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/uuid.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/bluetooth/uuid.h @@ -5090,6 +5090,16 @@ struct bt_uuid_128 { #define BT_UUID_GATT_SL \ BT_UUID_DECLARE_16(BT_UUID_GATT_SL_VAL) +/** + * @brief GATT Characteristic UDI for Medical Devices UUID Value + */ +#define BT_UUID_UDI_FOR_MEDICAL_DEVICES_VAL 0x2bff +/** + * @brief GATT Characteristic UDI for Medical Devices + */ +#define BT_UUID_UDI_FOR_MEDICAL_DEVICES \ + BT_UUID_DECLARE_16(BT_UUID_UDI_FOR_MEDICAL_DEVICES_VAL) + /** * @brief Gaming Service UUID value */ @@ -5185,6 +5195,8 @@ struct bt_uuid_128 { #define BT_UUID_HCRP_NOTE BT_UUID_DECLARE_16(BT_UUID_HCRP_NOTE_VAL) #define BT_UUID_AVCTP_VAL 0x0017 #define BT_UUID_AVCTP BT_UUID_DECLARE_16(BT_UUID_AVCTP_VAL) +#define BT_UUID_AVCTP_BROWSING_VAL 0x0018 +#define BT_UUID_AVCTP_BROWSING BT_UUID_DECLARE_16(BT_UUID_AVCTP_BROWSING_VAL) #define BT_UUID_AVDTP_VAL 0x0019 #define BT_UUID_AVDTP BT_UUID_DECLARE_16(BT_UUID_AVDTP_VAL) #define BT_UUID_CMTP_VAL 0x001b diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/canbus/isotp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/canbus/isotp.h index 222cef70..d2fc8591 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/canbus/isotp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/canbus/isotp.h @@ -23,7 +23,7 @@ #include #include -#include +#include /* * Abbreviations diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/json.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/json.h index f140a8b4..2e8182fd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/json.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/json.h @@ -42,6 +42,8 @@ enum json_tokens { JSON_TOK_OPAQUE = '2', JSON_TOK_OBJ_ARRAY = '3', JSON_TOK_ENCODED_OBJ = '4', + JSON_TOK_INT64 = '5', + JSON_TOK_UINT64 = '6', JSON_TOK_TRUE = 't', JSON_TOK_FALSE = 'f', JSON_TOK_NULL = 'n', diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/jwt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/jwt.h index 42dc26ae..d198251f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/jwt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/data/jwt.h @@ -15,7 +15,7 @@ extern "C" { #endif /** - * @brief JSON Web Token (JWT) + * @brief JSON Web Token (JWT) - RFC 7519 * @defgroup jwt JSON Web Token (JWT) * @ingroup json * @{ @@ -24,10 +24,10 @@ extern "C" { /** * @brief JWT data tracking. * - * JSON Web Tokens contain several sections, each encoded in base-64. + * JSON Web Tokens contain several sections, each encoded in Base64URL. * This structure tracks the token as it is being built, including * limits on the amount of available space. It should be initialized - * with jwt_init(). + * with jwt_init_builder(). */ struct jwt_builder { /** The base of the buffer we are writing to. */ @@ -37,7 +37,7 @@ struct jwt_builder { */ char *buf; - /** The length remaining to write. */ + /** The remaining free space in @p buf. */ size_t len; /** @@ -57,23 +57,37 @@ struct jwt_builder { * @brief Initialize the JWT builder. * * Initialize the given JWT builder for the creation of a fresh token. - * The buffer size should at least be as long as JWT_BUILDER_MAX_SIZE - * returns. + * The buffer size should be long enough to store the entire token. * * @param builder The builder to initialize. * @param buffer The buffer to write the token to. * @param buffer_size The size of this buffer. The token will be NULL * terminated, which needs to be allowed for in this size. * - * @retval 0 Success - * @retval -ENOSPC Buffer is insufficient to initialize + * @retval 0 Success. + * @retval -ENOSPC Buffer is insufficient to initialize. */ int jwt_init_builder(struct jwt_builder *builder, char *buffer, size_t buffer_size); /** - * @brief add JWT primary payload. + * @brief Add JWT payload. + * + * Add JWT payload to a previously initialized builder with the following fields: + * - Expiration Time + * - Issued At + * - Audience + * + * See RFC 7519 section 4.1 to get more information about these fields. + * + * @param builder A previously initialized builder. + * @param exp Expiration Time (epoch format). + * @param iat Issued At (epoch format). + * @param aud Audience. + * + * @retval 0 Success. + * @retval <0 Failure. */ int jwt_add_payload(struct jwt_builder *builder, int32_t exp, @@ -81,18 +95,21 @@ int jwt_add_payload(struct jwt_builder *builder, const char *aud); /** - * @brief Sign the JWT token. + * @brief Sign the JWT. + * + * Sign a previously initialized with payload JWT. + * + * @param builder A previously initialized builder with payload. + * @param der_key Private key to use in DER format. + * @param der_key_len Size of the private key in bytes. + * + * @retval 0 Success. + * @retval <0 Failure. */ int jwt_sign(struct jwt_builder *builder, const char *der_key, size_t der_key_len); - -static inline size_t jwt_payload_len(struct jwt_builder *builder) -{ - return (builder->buf - builder->base); -} - #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coredump.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coredump.h index f61f4e94..5ebdca5f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coredump.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coredump.h @@ -142,10 +142,13 @@ struct coredump_cmd_copy_arg { #include #include -#define COREDUMP_HDR_VER 1 +#define COREDUMP_HDR_VER 2 #define COREDUMP_ARCH_HDR_ID 'A' +#define THREADS_META_HDR_ID 'T' +#define THREADS_META_HDR_VER 1 + #define COREDUMP_MEM_HDR_ID 'M' #define COREDUMP_MEM_HDR_VER 1 @@ -192,6 +195,18 @@ struct coredump_arch_hdr_t { uint16_t num_bytes; } __packed; +/* Threads metadata header */ +struct coredump_threads_meta_hdr_t { + /* THREADS_META_HDR_ID */ + char id; + + /* Header version */ + uint16_t hdr_version; + + /* Number of bytes in this block (excluding header) */ + uint16_t num_bytes; +} __packed; + /* Memory block header */ struct coredump_mem_hdr_t { /* COREDUMP_MEM_HDR_ID */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coresight/cs_trace_defmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coresight/cs_trace_defmt.h new file mode 100644 index 00000000..b9920672 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/coresight/cs_trace_defmt.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DEBUG_CORESIGHT_CS_TRACE_DEFMT_H__ +#define ZEPHYR_INCLUDE_DEBUG_CORESIGHT_CS_TRACE_DEFMT_H__ + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup coresight_apis Coresight APIs + * @{ + * @} + * @defgroup cs_trace_defmt Coresight Trace Deformatter + * @ingroup coresight_apis + * @{ + */ + +/** @brief Callback signature. + * + * @param id Stream ID. + * @param data Data. + * @param len Data length. + */ +typedef void (*cs_trace_defmt_cb)(uint32_t id, const uint8_t *data, size_t len); + +/** @brief Size of trace deformatter frame size in 32 bit words. */ +#define CORESIGHT_TRACE_FRAME_SIZE32 4 + +/** @brief Size of trace deformatter frame size in bytes. */ +#define CORESIGHT_TRACE_FRAME_SIZE (CORESIGHT_TRACE_FRAME_SIZE32 * sizeof(uint32_t)) + +/** @brief Initialize Coresight Trace Deformatter. + * + * @param cb Callback. + */ +int cs_trace_defmt_init(cs_trace_defmt_cb cb); + +/** @brief Decode data from the stream. + * + * Trace formatter puts data in the 16 byte long blocks. + * + * Callback is called with decoded data. + * + * @param data Data. + * @param len Data length. Must equal 16. + * + * @retval 0 On successful deformatting. + * @retval -EINVAL If wrong length is provided. + */ +int cs_trace_defmt_process(const uint8_t *data, size_t len); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DEBUG_CORESIGHT_CS_TRACE_DEFMT_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/mipi_stp_decoder.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/mipi_stp_decoder.h index 31ffb982..c3a87e7a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/mipi_stp_decoder.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/mipi_stp_decoder.h @@ -27,7 +27,7 @@ enum mipi_stp_decoder_ctrl_type { STP_DATA32 = 8, STP_DATA64 = 16, STP_DECODER_NULL = 128, - STP_DECODER_MASTER, + STP_DECODER_MAJOR, STP_DECODER_MERROR, STP_DECODER_CHANNEL, STP_DECODER_VERSION, @@ -50,7 +50,7 @@ enum mipi_stp_decoder_ctrl_type { _type == STP_DATA32 ? "DATA32" : (\ _type == STP_DATA64 ? "DATA64" : (\ _type == STP_DECODER_NULL ? "NULL" : (\ - _type == STP_DECODER_MASTER ? "MASTER" : (\ + _type == STP_DECODER_MAJOR ? "MAJOR" : (\ _type == STP_DECODER_MERROR ? "MERROR" : (\ _type == STP_DECODER_CHANNEL ? "CHANNEL" : (\ _type == STP_DECODER_VERSION ? "VERSION" : (\ @@ -62,7 +62,7 @@ enum mipi_stp_decoder_ctrl_type { /** @brief Union with data associated with a given STP opcode. */ union mipi_stp_decoder_data { - /** ID - used for master and channel. */ + /** ID - used for major and channel. */ uint16_t id; /** Frequency. */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/symtab.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/symtab.h index ba4e8c57..19afb594 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/symtab.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/symtab.h @@ -46,7 +46,7 @@ struct symtab_info { * * @return Pointer to the symbol table. */ -const struct symtab_info *const symtab_get(void); +const struct symtab_info *symtab_get(void); /** * @brief Find the symbol name with a binary search @@ -57,7 +57,7 @@ const struct symtab_info *const symtab_get(void); * * @return Name of the nearest symbol if found, otherwise "?" is returned. */ -const char *const symtab_find_symbol_name(uintptr_t addr, uint32_t *offset); +const char *symtab_find_symbol_name(uintptr_t addr, uint32_t *offset); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/thread_analyzer.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/thread_analyzer.h index d9c0f855..d3d419bd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/thread_analyzer.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/debug/thread_analyzer.h @@ -39,6 +39,14 @@ struct thread_analyzer_info { k_thread_runtime_stats_t usage; #endif #endif + +#ifdef CONFIG_THREAD_ANALYZER_PRIV_STACK_USAGE + /** Total size of privileged stack */ + size_t priv_stack_size; + + /** Privileged stack size in used */ + size_t priv_stack_used; +#endif }; /** @brief Thread analyzer stack size callback function @@ -52,18 +60,25 @@ typedef void (*thread_analyzer_cb)(struct thread_analyzer_info *info); /** @brief Run the thread analyzer and provide information to the callback * * This function analyzes the current state for all threads and calls - * a given callback on every thread found. + * a given callback on every thread found. In the special case when Kconfig + * option THREAD_ANALYZER_AUTO_SEPARATE_CORES is set, the function analyzes + * only the threads running on the specified cpu. * * @param cb The callback function handler + * @param cpu cpu to analyze, ignored if THREAD_ANALYZER_AUTO_SEPARATE_CORES=n */ -void thread_analyzer_run(thread_analyzer_cb cb); +void thread_analyzer_run(thread_analyzer_cb cb, unsigned int cpu); /** @brief Run the thread analyzer and print stack size statistics. * - * This function runs the thread analyzer and prints the output in standard - * form. + * This function runs the thread analyzer and prints the output in + * standard form. In the special case when Kconfig option + * THREAD_ANALYZER_AUTO_SEPARATE_CORES is set, the function analyzes + * only the threads running on the specified cpu. + * + * @param cpu cpu to analyze, ignored if THREAD_ANALYZER_AUTO_SEPARATE_CORES=n */ -void thread_analyzer_print(void); +void thread_analyzer_print(unsigned int cpu); /** @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/device.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/device.h index 7d783397..2362f1a5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/device.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/device.h @@ -207,8 +207,7 @@ typedef int16_t device_handle_t; DEVICE_DT_NAME(node_id), init_fn, pm, data, config, \ level, prio, api, \ &Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_ID(node_id)), \ - __VA_ARGS__) \ - IF_ENABLED(CONFIG_LLEXT_EXPORT_DEVICES, (; Z_DEVICE_EXPORT(node_id))) \ + __VA_ARGS__) /** * @brief Like DEVICE_DT_DEFINE(), but uses an instance of a `DT_DRV_COMPAT` @@ -318,7 +317,7 @@ typedef int16_t device_handle_t; * @return a @ref device reference for the node identifier, which may be `NULL`. */ #define DEVICE_DT_GET_OR_NULL(node_id) \ - COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(node_id), \ (DEVICE_DT_GET(node_id)), (NULL)) /** @@ -932,11 +931,14 @@ __syscall const struct device *device_get_by_dt_nodelabel(const char *nodelabel) /** * @brief Get the devicetree node labels associated with a device * @param dev device whose metadata to look up - * @return information about the devicetree node labels + * @return information about the devicetree node labels or NULL if not available */ static inline const struct device_dt_nodelabels * device_get_dt_nodelabels(const struct device *dev) { + if (dev->dt_meta == NULL) { + return NULL; + } return dev->dt_meta->nl; } @@ -1081,24 +1083,16 @@ device_get_dt_nodelabels(const struct device *dev) Z_DEVICE_SECTION_NAME(level, prio), DEVICE_NAME_GET(dev_id)) = \ Z_DEVICE_INIT(name, pm, data, config, api, state, deps, node_id, dev_id) -/* deprecated device initialization levels */ -#define Z_DEVICE_LEVEL_DEPRECATED_EARLY \ - __WARN("EARLY device driver level is deprecated") -#define Z_DEVICE_LEVEL_DEPRECATED_PRE_KERNEL_1 -#define Z_DEVICE_LEVEL_DEPRECATED_PRE_KERNEL_2 -#define Z_DEVICE_LEVEL_DEPRECATED_POST_KERNEL -#define Z_DEVICE_LEVEL_DEPRECATED_APPLICATION \ - __WARN("APPLICATION device driver level is deprecated") -#define Z_DEVICE_LEVEL_DEPRECATED_SMP \ - __WARN("SMP device driver level is deprecated") - /** - * @brief Issue a warning if the given init level is deprecated. + * @brief Issue an error if the given init level is not supported. * * @param level Init level */ -#define Z_DEVICE_LEVEL_CHECK_DEPRECATED_LEVEL(level) \ - Z_DEVICE_LEVEL_DEPRECATED_##level +#define Z_DEVICE_CHECK_INIT_LEVEL(level) \ + COND_CODE_1(Z_INIT_PRE_KERNEL_1_##level, (), \ + (COND_CODE_1(Z_INIT_PRE_KERNEL_2_##level, (), \ + (COND_CODE_1(Z_INIT_POST_KERNEL_##level, (), \ + (ZERO_OR_COMPILE_ERROR(0))))))) /** * @brief Define the init entry for a device. @@ -1111,7 +1105,7 @@ device_get_dt_nodelabels(const struct device *dev) * @param prio Initialization priority. */ #define Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, init_fn_, level, prio) \ - Z_DEVICE_LEVEL_CHECK_DEPRECATED_LEVEL(level) \ + Z_DEVICE_CHECK_INIT_LEVEL(level) \ \ static const Z_DECL_ALIGN(struct init_entry) __used __noasan Z_INIT_ENTRY_SECTION( \ level, prio, Z_DEVICE_INIT_SUB_PRIO(node_id)) \ @@ -1177,12 +1171,15 @@ device_get_dt_nodelabels(const struct device *dev) (Z_DEVICE_DT_METADATA_DEFINE(node_id, dev_id);))))\ \ Z_DEVICE_BASE_DEFINE(node_id, dev_id, name, pm, data, config, level, \ - prio, api, state, Z_DEVICE_DEPS_NAME(dev_id)); \ + prio, api, state, Z_DEVICE_DEPS_NAME(dev_id)); \ COND_CODE_1(DEVICE_DT_DEFER(node_id), \ (Z_DEFER_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, \ init_fn)), \ (Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, init_fn, \ - level, prio))); + level, prio))); \ + IF_ENABLED(CONFIG_LLEXT_EXPORT_DEVICES, \ + (IF_ENABLED(DT_NODE_EXISTS(node_id), \ + (Z_DEVICE_EXPORT(node_id);)))) \ /** * @brief Declare a device for each status "okay" devicetree node. @@ -1200,8 +1197,47 @@ device_get_dt_nodelabels(const struct device *dev) DT_FOREACH_STATUS_OKAY_NODE(Z_MAYBE_DEVICE_DECLARE_INTERNAL) +/** @brief Expands to the full type. */ +#define Z_DEVICE_API_TYPE(_class) _CONCAT(_class, _driver_api) + /** @endcond */ +/** + * @brief Wrapper macro for declaring device API structs inside iterable sections. + * + * @param _class The device API class. + * @param _name The API instance name. + */ +#define DEVICE_API(_class, _name) const STRUCT_SECTION_ITERABLE(Z_DEVICE_API_TYPE(_class), _name) + +/** + * @brief Expands to the pointer of a device's API for a given class. + * + * @param _class The device API class. + * @param _dev The device instance pointer. + * + * @return the pointer to the device API. + */ +#define DEVICE_API_GET(_class, _dev) ((const struct Z_DEVICE_API_TYPE(_class) *)_dev->api) + +/** + * @brief Macro that evaluates to a boolean that can be used to check if + * a device is of a particular class. + * + * @param _class The device API class. + * @param _dev The device instance pointer. + * + * @retval true If the device is of the given class + * @retval false If the device is not of the given class + */ +#define DEVICE_API_IS(_class, _dev) \ + ({ \ + STRUCT_SECTION_START_EXTERN(Z_DEVICE_API_TYPE(_class)); \ + STRUCT_SECTION_END_EXTERN(Z_DEVICE_API_TYPE(_class)); \ + (DEVICE_API_GET(_class, _dev) < STRUCT_SECTION_END(Z_DEVICE_API_TYPE(_class)) && \ + DEVICE_API_GET(_class, _dev) >= STRUCT_SECTION_START(Z_DEVICE_API_TYPE(_class))); \ + }) + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree.h index 2cb08aa7..1ee4181d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree.h @@ -13,8 +13,8 @@ * API for accessing the current application's devicetree macros. */ -#ifndef DEVICETREE_H -#define DEVICETREE_H +#ifndef ZEPHYR_INCLUDE_DEVICETREE_H_ +#define ZEPHYR_INCLUDE_DEVICETREE_H_ #include #include @@ -29,7 +29,7 @@ * @brief devicetree.h API * @defgroup devicetree Devicetree * @since 2.2 - * @version 1.1.0 + * @version 1.2.0 * @{ * @} */ @@ -47,10 +47,6 @@ * * _ENUM_IDX: property's value as an index into bindings enum * _ENUM_VAL__EXISTS property's value as a token exists - * _ENUM_TOKEN: property's value as a token into bindings enum (string - * enum values are identifiers) [deprecated, use _STRING_TOKEN] - * _ENUM_UPPER_TOKEN: like _ENUM_TOKEN, but uppercased [deprecated, use - * _STRING_UPPER_TOKEN] * _EXISTS: property is defined * _FOREACH_PROP_ELEM: helper for "iterating" over values in the property * _FOREACH_PROP_ELEM_VARGS: foreach functions with variable number of arguments @@ -239,6 +235,13 @@ */ #define DT_ALIAS(alias) DT_CAT(DT_N_ALIAS_, alias) +/** + * @brief Test if the devicetree has a given alias + * @param alias_name lowercase-and-underscores devicetree alias name + * @return 1 if the alias exists and refers to a node, 0 otherwise + */ +#define DT_HAS_ALIAS(alias_name) DT_NODE_EXISTS(DT_ALIAS(alias_name)) + /** * @brief Get a node identifier for an instance of a compatible * @@ -523,6 +526,92 @@ */ #define DT_NODE_FULL_NAME(node_id) DT_CAT(node_id, _FULL_NAME) +/** + * @brief Get the node's full name, including the unit-address, as an unquoted + * sequence of tokens + * + * This macro returns removed "the quotes" from the node's full name. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_UNQUOTED(DT_NODELABEL(node)) // my-node@12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as a sequence of tokens, + * with no quotes + */ +#define DT_NODE_FULL_NAME_UNQUOTED(node_id) DT_CAT(node_id, _FULL_NAME_UNQUOTED) + +/** + * @brief Get the node's full name, including the unit-address, as a token. + * + * This macro returns removed "the quotes" from the node's full name and + * converting any non-alphanumeric characters to underscores. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_TOKEN(DT_NODELABEL(node)) // my_node_12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as a token, i.e. without any quotes + * and with special characters converted to underscores + */ +#define DT_NODE_FULL_NAME_TOKEN(node_id) DT_CAT(node_id, _FULL_NAME_TOKEN) + +/** + * @brief Like DT_NODE_FULL_NAME_TOKEN(), but uppercased. + * + * This macro returns removed "the quotes" from the node's full name, + * converting any non-alphanumeric characters to underscores, and + * capitalizing the result. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * node: my-node@12345678 { ... }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * DT_NODE_FULL_NAME_UPPER_TOKEN(DT_NODELABEL(node)) // MY_NODE_12345678 + * @endcode + * + * @param node_id node identifier + * @return the node's full name with unit-address as an uppercased token, + * i.e. without any quotes and with special characters converted + * to underscores + */ +#define DT_NODE_FULL_NAME_UPPER_TOKEN(node_id) DT_CAT(node_id, _FULL_NAME_UPPER_TOKEN) + /** * @brief Get a devicetree node's index into its parent's list of children * @@ -809,6 +898,17 @@ #define DT_PROP_BY_IDX(node_id, prop, idx) \ DT_CAT5(node_id, _P_, prop, _IDX_, idx) +/** + * @brief Get the last element of an array type property + * + * @param node_id node identifier + * @param prop lowercase-and-underscores property name + * + * @return a representation of the last element of the property + */ +#define DT_PROP_LAST(node_id, prop) \ + DT_PROP_BY_IDX(node_id, prop, UTIL_DEC(DT_PROP_LEN(node_id, prop))) + /** * @brief Like DT_PROP(), but with a fallback to @p default_value * @@ -827,75 +927,122 @@ (DT_PROP(node_id, prop)), (default_value)) /** - * @brief Get a property value's index into its enumeration values + * @brief Get a property array value's index into its enumeration values * * The return values start at zero. * * Example devicetree fragment: * * @code{.dts} - * usb1: usb@12340000 { - * maximum-speed = "full-speed"; - * }; - * usb2: usb@12341000 { - * maximum-speed = "super-speed"; + * some_node: some-node { + * compat = "vend,enum-string-array"; + * foos = + * <&phandle val1>, + * <&phandle val2>, + * <&phandle val3>; + * foo-names = "default", "option3", "option1"; * }; * @endcode * * Example bindings fragment: * * @code{.yaml} - * properties: - * maximum-speed: - * type: string - * enum: - * - "low-speed" - * - "full-speed" - * - "high-speed" - * - "super-speed" + * compatible: vend,enum-string-array + * properties: + * foos: + * type: phandle-array + * description: | + * Explanation about what this phandle-array exactly is for. + * + * foo-names: + * type: string-array + * description: | + * Some explanation about the available options + * default: explain default + * option1: explain option1 + * option2: explain option2 + * option3: explain option3 + * enum: + * - default + * - option1 + * - option2 + * - option3 * @endcode * * Example usage: * * @code{.c} - * DT_ENUM_IDX(DT_NODELABEL(usb1), maximum_speed) // 1 - * DT_ENUM_IDX(DT_NODELABEL(usb2), maximum_speed) // 3 + * DT_ENUM_IDX_BY_IDX(DT_NODELABEL(some_node), foo_names, 0) // 0 + * DT_ENUM_IDX_BY_IDX(DT_NODELABEL(some_node), foo_names, 2) // 1 * @endcode * * @param node_id node identifier * @param prop lowercase-and-underscores property name + * @param idx the index to get * @return zero-based index of the property's value in its enum: list */ -#define DT_ENUM_IDX(node_id, prop) DT_CAT4(node_id, _P_, prop, _ENUM_IDX) +#define DT_ENUM_IDX_BY_IDX(node_id, prop, idx) \ + DT_CAT6(node_id, _P_, prop, _IDX_, idx, _ENUM_IDX) /** - * @brief Like DT_ENUM_IDX(), but with a fallback to a default enum index + * @brief Equivalent to @ref DT_ENUM_IDX_BY_IDX(node_id, prop, 0). + * @param node_id node identifier + * @param prop lowercase-and-underscores property name + * @return zero-based index of the property's value in its enum: list + */ +#define DT_ENUM_IDX(node_id, prop) DT_ENUM_IDX_BY_IDX(node_id, prop, 0) + +/** + * @brief Like DT_ENUM_IDX_BY_IDX(), but with a fallback to a default enum index * * If the value exists, this expands to its zero based index value thanks to - * DT_ENUM_IDX(node_id, prop). + * DT_ENUM_IDX_BY_IDX(node_id, prop, idx). * * Otherwise, this expands to provided default index enum value. * * @param node_id node identifier * @param prop lowercase-and-underscores property name + * @param idx the index to get + * @param default_idx_value a fallback index value to expand to + * @return zero-based index of the property's value in its enum if present, + * default_idx_value otherwise + */ +#define DT_ENUM_IDX_BY_IDX_OR(node_id, prop, idx, default_idx_value) \ + COND_CODE_1(DT_PROP_HAS_IDX(node_id, prop, idx), \ + (DT_ENUM_IDX_BY_IDX(node_id, prop, idx)), (default_idx_value)) + +/** + * @brief Equivalent to DT_ENUM_IDX_BY_IDX_OR(node_id, prop, 0, default_idx_value). + * @param node_id node identifier + * @param prop lowercase-and-underscores property name * @param default_idx_value a fallback index value to expand to * @return zero-based index of the property's value in its enum if present, * default_idx_value otherwise */ #define DT_ENUM_IDX_OR(node_id, prop, default_idx_value) \ - COND_CODE_1(DT_NODE_HAS_PROP(node_id, prop), \ - (DT_ENUM_IDX(node_id, prop)), (default_idx_value)) + DT_ENUM_IDX_BY_IDX_OR(node_id, prop, 0, default_idx_value) /** - * @brief Does a node enumeration property have a given value? + * @brief Does a node enumeration property array have a given value? * * @param node_id node identifier * @param prop lowercase-and-underscores property name + * @param idx the index to get + * @param value lowercase-and-underscores enumeration value + * @return 1 if the node property has the value @a value, 0 otherwise. + */ +#define DT_ENUM_HAS_VALUE_BY_IDX(node_id, prop, idx, value) \ + IS_ENABLED(DT_CAT8(node_id, _P_, prop, _IDX_, idx, _ENUM_VAL_, value, _EXISTS)) + +/** + * @brief Equivalent to DT_ENUM_HAS_VALUE_BY_IDX(node_id, prop, 0, value). + * @param node_id node identifier + * @param prop lowercase-and-underscores property name * @param value lowercase-and-underscores enumeration value * @return 1 if the node property has the value @a value, 0 otherwise. */ #define DT_ENUM_HAS_VALUE(node_id, prop, value) \ - IS_ENABLED(DT_CAT6(node_id, _P_, prop, _ENUM_VAL_, value, _EXISTS)) + DT_ENUM_HAS_VALUE_BY_IDX(node_id, prop, 0, value) /** * @brief Get a string property's value as a token. @@ -2243,6 +2390,34 @@ #define DT_REG_HAS_NAME(node_id, name) \ IS_ENABLED(DT_CAT4(node_id, _REG_NAME_, name, _EXISTS)) +/** + * @brief Get the base raw address of the register block at index @p idx + * + * Get the base address of the register block at index @p idx without any + * type suffix. This can be used to index other devicetree properties, use the + * non _RAW macros for assigning values in actual code. + * + * @param node_id node identifier + * @param idx index of the register whose address to return + * @return address of the idx-th register block + */ +#define DT_REG_ADDR_BY_IDX_RAW(node_id, idx) \ + DT_CAT4(node_id, _REG_IDX_, idx, _VAL_ADDRESS) + +/** + * @brief Get a node's (only) register block raw address + * + * Get a node's only register block address without any type suffix. This can + * be used to index other devicetree properties, use the non _RAW macros for + * assigning values in actual code. + * + * Equivalent to DT_REG_ADDR_BY_IDX_RAW(node_id, 0). + * @param node_id node identifier + * @return node's register block address + */ +#define DT_REG_ADDR_RAW(node_id) \ + DT_REG_ADDR_BY_IDX_RAW(node_id, 0) + /** * @brief Get the base address of the register block at index @p idx * @param node_id node identifier @@ -2250,7 +2425,7 @@ * @return address of the idx-th register block */ #define DT_REG_ADDR_BY_IDX(node_id, idx) \ - DT_CAT4(node_id, _REG_IDX_, idx, _VAL_ADDRESS) + DT_U32_C(DT_REG_ADDR_BY_IDX_RAW(node_id, idx)) /** * @brief Get the size of the register block at index @p idx @@ -2264,7 +2439,7 @@ * @return size of the idx-th register block */ #define DT_REG_SIZE_BY_IDX(node_id, idx) \ - DT_CAT4(node_id, _REG_IDX_, idx, _VAL_SIZE) + DT_U32_C(DT_CAT4(node_id, _REG_IDX_, idx, _VAL_SIZE)) /** * @brief Get a node's (only) register block address @@ -2285,7 +2460,7 @@ * @param node_id node identifier * @return node's register block address */ -#define DT_REG_ADDR_U64(node_id) DT_U64_C(DT_REG_ADDR(node_id)) +#define DT_REG_ADDR_U64(node_id) DT_U64_C(DT_REG_ADDR_BY_IDX_RAW(node_id, 0)) /** * @brief Get a node's (only) register block size @@ -2303,7 +2478,7 @@ * @return address of the register block specified by name */ #define DT_REG_ADDR_BY_NAME(node_id, name) \ - DT_CAT4(node_id, _REG_NAME_, name, _VAL_ADDRESS) + DT_U32_C(DT_CAT4(node_id, _REG_NAME_, name, _VAL_ADDRESS)) /** * @brief Like DT_REG_ADDR_BY_NAME(), but with a fallback to @p default_value @@ -2330,7 +2505,7 @@ * @return address of the register block specified by name */ #define DT_REG_ADDR_BY_NAME_U64(node_id, name) \ - DT_U64_C(DT_REG_ADDR_BY_NAME(node_id, name)) + DT_U64_C(DT_CAT4(node_id, _REG_NAME_, name, _VAL_ADDRESS)) /** * @brief Get a register block's size by name @@ -2339,7 +2514,7 @@ * @return size of the register block specified by name */ #define DT_REG_SIZE_BY_NAME(node_id, name) \ - DT_CAT4(node_id, _REG_NAME_, name, _VAL_SIZE) + DT_U32_C(DT_CAT4(node_id, _REG_NAME_, name, _VAL_SIZE)) /** * @brief Like DT_REG_SIZE_BY_NAME(), but with a fallback to @p default_value @@ -3201,7 +3376,7 @@ */ #define DT_FOREACH_STATUS_OKAY(compat, fn) \ COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(compat), \ - (DT_CAT(DT_FOREACH_OKAY_, compat)(fn)), \ + (UTIL_CAT(DT_FOREACH_OKAY_, compat)(fn)), \ ()) /** @@ -3254,6 +3429,25 @@ compat)(fn, __VA_ARGS__)), \ ()) +/** + * @brief Call @p fn on all nodes with compatible `compat` + * and status `okay` with multiple arguments + * + * + * @param compat lowercase-and-underscores devicetree compatible + * @param fn Macro to call for each enabled node. Must accept a + * devicetree compatible and instance number. + * @param ... Additional arguments to pass to @p fn + * + * @see DT_INST_FOREACH_STATUS_OKAY_VARGS + */ +#define DT_COMPAT_FOREACH_STATUS_OKAY_VARGS(compat, fn, ...) \ + COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(compat), \ + (UTIL_CAT(DT_FOREACH_OKAY_INST_VARGS_, \ + compat)(fn, compat, __VA_ARGS__)), \ + ()) + + /** * @brief Invokes @p fn for each node label of a given node * @@ -3384,6 +3578,28 @@ #define DT_NODE_HAS_STATUS(node_id, status) \ DT_NODE_HAS_STATUS_INTERNAL(node_id, status) +/** + * @brief Does a node identifier refer to a node with a status `okay`? + * + * Example uses: + * + * @code{.c} + * DT_NODE_HAS_STATUS_OKAY(DT_PATH(soc, i2c_12340000)) + * @endcode + * + * Tests whether a node identifier refers to a node which: + * + * - exists in the devicetree, and + * - has a status property as `okay` + * + * As usual, both a missing status and an `ok` status are treated as + * `okay`. + * + * @param node_id a node identifier + * @return 1 if the node has status as `okay`, 0 otherwise. + */ +#define DT_NODE_HAS_STATUS_OKAY(node_id) DT_NODE_HAS_STATUS(node_id, okay) + /** * @brief Does the devicetree have a status `okay` node with a compatible? * @@ -3809,6 +4025,16 @@ #define DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(inst, fn, sep, ...) \ DT_FOREACH_CHILD_STATUS_OKAY_SEP_VARGS(DT_DRV_INST(inst), fn, sep, __VA_ARGS__) +/** + * @brief Get a `DT_DRV_COMPAT` property array value's index into its enumeration values + * @param inst instance number + * @param prop lowercase-and-underscores property name + * @param idx the index to get + * @return zero-based index of the property's value in its enum: list + */ +#define DT_INST_ENUM_IDX_BY_IDX(inst, prop, idx) \ + DT_ENUM_IDX_BY_IDX(DT_DRV_INST(inst), prop, idx) + /** * @brief Get a `DT_DRV_COMPAT` value's index into its enumeration values * @param inst instance number @@ -3818,6 +4044,18 @@ #define DT_INST_ENUM_IDX(inst, prop) \ DT_ENUM_IDX(DT_DRV_INST(inst), prop) +/** + * @brief Like DT_INST_ENUM_IDX_BY_IDX(), but with a fallback to a default enum index + * @param inst instance number + * @param prop lowercase-and-underscores property name + * @param idx the index to get + * @param default_idx_value a fallback index value to expand to + * @return zero-based index of the property's value in its enum if present, + * default_idx_value otherwise + */ +#define DT_INST_ENUM_IDX_BY_IDX_OR(inst, prop, idx, default_idx_value) \ + DT_ENUM_IDX_BY_IDX_OR(DT_DRV_INST(inst), prop, idx, default_idx_value) + /** * @brief Like DT_INST_ENUM_IDX(), but with a fallback to a default enum index * @param inst instance number @@ -3829,6 +4067,17 @@ #define DT_INST_ENUM_IDX_OR(inst, prop, default_idx_value) \ DT_ENUM_IDX_OR(DT_DRV_INST(inst), prop, default_idx_value) +/** + * @brief Does a `DT_DRV_COMPAT` enumeration property have a given value by index? + * @param inst instance number + * @param prop lowercase-and-underscores property name + * @param idx the index to get + * @param value lowercase-and-underscores enumeration value + * @return zero-based index of the property's value in its enum + */ +#define DT_INST_ENUM_HAS_VALUE_BY_IDX(inst, prop, idx, value) \ + DT_ENUM_HAS_VALUE_BY_IDX(DT_DRV_INST(inst), prop, idx, value) + /** * @brief Does a `DT_DRV_COMPAT` enumeration property have a given value? * @@ -4116,6 +4365,14 @@ */ #define DT_INST_REG_HAS_NAME(inst, name) DT_REG_HAS_NAME(DT_DRV_INST(inst), name) +/** + * @brief Get a `DT_DRV_COMPAT` instance's idx-th register block's raw address + * @param inst instance number + * @param idx index of the register whose address to return + * @return address of the instance's idx-th register block + */ +#define DT_INST_REG_ADDR_BY_IDX_RAW(inst, idx) DT_REG_ADDR_BY_IDX_RAW(DT_DRV_INST(inst), idx) + /** * @brief Get a `DT_DRV_COMPAT` instance's idx-th register block's address * @param inst instance number @@ -4166,7 +4423,7 @@ * @return address of the register block with the given @p name */ #define DT_INST_REG_ADDR_BY_NAME_U64(inst, name) \ - DT_U64_C(DT_INST_REG_ADDR_BY_NAME(inst, name)) + DT_REG_ADDR_BY_NAME_U64(DT_DRV_INST(inst), name) /** * @brief Get a `DT_DRV_COMPAT`'s register block size by name @@ -4188,6 +4445,13 @@ #define DT_INST_REG_SIZE_BY_NAME_OR(inst, name, default_value) \ DT_REG_SIZE_BY_NAME_OR(DT_DRV_INST(inst), name, default_value) +/** + * @brief Get a `DT_DRV_COMPAT`'s (only) register block raw address + * @param inst instance number + * @return instance's register block address + */ +#define DT_INST_REG_ADDR_RAW(inst) DT_INST_REG_ADDR_BY_IDX_RAW(inst, 0) + /** * @brief Get a `DT_DRV_COMPAT`'s (only) register block address * @param inst instance number @@ -4206,7 +4470,7 @@ * @param inst instance number * @return instance's register block address */ -#define DT_INST_REG_ADDR_U64(inst) DT_U64_C(DT_INST_REG_ADDR(inst)) +#define DT_INST_REG_ADDR_U64(inst) DT_REG_ADDR_U64(DT_DRV_INST(inst)) /** * @brief Get a `DT_DRV_COMPAT`'s (only) register block size @@ -4215,6 +4479,14 @@ */ #define DT_INST_REG_SIZE(inst) DT_INST_REG_SIZE_BY_IDX(inst, 0) +/** + * @brief Get a `DT_DRV_COMPAT`'s number of interrupts + * + * @param inst instance number + * @return number of interrupts + */ +#define DT_INST_NUM_IRQS(inst) DT_NUM_IRQS(DT_DRV_INST(inst)) + /** * @brief Get a `DT_DRV_COMPAT` interrupt level * @@ -4459,6 +4731,103 @@ #define DT_ANY_INST_HAS_PROP_STATUS_OKAY(prop) \ COND_CODE_1(IS_EMPTY(DT_ANY_INST_HAS_PROP_STATUS_OKAY_(prop)), (0), (1)) +/** + * @brief Check if any device node with status `okay` has a given + * property. + * + * @param compat lowercase-and-underscores devicetree compatible + * @param prop lowercase-and-underscores property name + * + * Example devicetree overlay: + * + * @code{.dts} + * &i2c0 { + * sensor0: sensor@0 { + * compatible = "vnd,some-sensor"; + * status = "okay"; + * reg = <0>; + * foo = <1>; + * bar = <2>; + * }; + * + * sensor1: sensor@1 { + * compatible = "vnd,some-sensor"; + * status = "okay"; + * reg = <1>; + * foo = <2>; + * }; + * + * sensor2: sensor@2 { + * compatible = "vnd,some-sensor"; + * status = "disabled"; + * reg = <2>; + * baz = <1>; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * + * DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(vnd_some_sensor, foo) // 1 + * DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(vnd_some_sensor, bar) // 1 + * DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(vnd_some_sensor, baz) // 0 + * @endcode + */ +#define DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(compat, prop) \ + (DT_COMPAT_FOREACH_STATUS_OKAY_VARGS(compat, DT_COMPAT_NODE_HAS_PROP_AND_OR, prop) 0) + +/** + * @brief Check if any `DT_DRV_COMPAT` node with status `okay` has a given + * boolean property that exists. + * + * This differs from @ref DT_ANY_INST_HAS_PROP_STATUS_OKAY because even when not present + * on a node, the boolean property is generated with a value of 0 and therefore exists. + * + * @param prop lowercase-and-underscores property name + * + * Example devicetree overlay: + * + * @code{.dts} + * &i2c0 { + * sensor0: sensor@0 { + * compatible = "vnd,some-sensor"; + * status = "okay"; + * reg = <0>; + * foo; + * bar; + * }; + * + * sensor1: sensor@1 { + * compatible = "vnd,some-sensor"; + * status = "okay"; + * reg = <1>; + * foo; + * }; + * + * sensor2: sensor@2 { + * compatible = "vnd,some-sensor"; + * status = "disabled"; + * reg = <2>; + * baz; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * #define DT_DRV_COMPAT vnd_some_sensor + * + * DT_ANY_INST_HAS_BOOL_STATUS_OKAY(foo) // 1 + * DT_ANY_INST_HAS_BOOL_STATUS_OKAY(bar) // 1 + * DT_ANY_INST_HAS_BOOL_STATUS_OKAY(baz) // 0 + * @endcode + */ +#define DT_ANY_INST_HAS_BOOL_STATUS_OKAY(prop) \ + COND_CODE_1(IS_EMPTY(DT_ANY_INST_HAS_BOOL_STATUS_OKAY_(prop)), (0), (1)) + /** * @brief Call @p fn on all nodes with compatible `DT_DRV_COMPAT` * and status `okay` @@ -4536,15 +4905,16 @@ * * * @param fn Macro to call for each enabled node. Must accept an - * instance number as its only parameter. + * instance number. * @param ... variable number of arguments to pass to @p fn * * @see DT_INST_FOREACH_STATUS_OKAY + * @see DT_COMPAT_FOREACH_STATUS_OKAY_VARGS */ #define DT_INST_FOREACH_STATUS_OKAY_VARGS(fn, ...) \ - COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT), \ - (UTIL_CAT(DT_FOREACH_OKAY_INST_VARGS_, \ - DT_DRV_COMPAT)(fn, __VA_ARGS__)), \ + COND_CODE_1(DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT), \ + (UTIL_CAT(DT_FOREACH_OKAY_INST_VARGS_, \ + DT_DRV_COMPAT)(fn, __VA_ARGS__)), \ ()) /** @@ -4755,6 +5125,35 @@ #define DT_ANY_INST_HAS_PROP_STATUS_OKAY_(prop) \ DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_ANY_INST_HAS_PROP_STATUS_OKAY__, prop) +/** @brief Helper for DT_ANY_INST_HAS_BOOL_STATUS_OKAY_ + * + * This macro generates token "1," for instance of a device, + * identified by index @p idx, if instance has boolean property + * @p prop with value 1. + * + * @param idx instance number + * @param prop property to check for + * + * @return Macro evaluates to `1,` if instance property value is 1, + * otherwise it evaluates to literal nothing. + */ +#define DT_ANY_INST_HAS_BOOL_STATUS_OKAY__(idx, prop) \ + COND_CODE_1(DT_INST_PROP(idx, prop), (1,), ()) +/** @brief Helper for DT_ANY_INST_HAS_BOOL_STATUS_OKAY + * + * This macro uses DT_ANY_INST_HAS_BOOL_STATUS_OKAY_ with + * DT_INST_FOREACH_STATUS_OKAY_VARG to generate comma separated list of 1, + * where each 1 on the list represents instance that has a property + * @p prop of value 1; the list may be empty, and the upper bound on number of + * list elements is number of device instances. + * + * @param prop property to check + * + * @return Evaluates to list of 1s (e.g: 1,1,1,) or nothing. + */ +#define DT_ANY_INST_HAS_BOOL_STATUS_OKAY_(prop) \ + DT_INST_FOREACH_STATUS_OKAY_VARGS(DT_ANY_INST_HAS_BOOL_STATUS_OKAY__, prop) + #define DT_PATH_INTERNAL(...) \ UTIL_CAT(DT_ROOT, MACRO_MAP_CAT(DT_S_PREFIX, __VA_ARGS__)) /** @brief DT_PATH_INTERNAL() helper: prepends _S_ to a node name @@ -4806,6 +5205,22 @@ #define DT_NODE_HAS_STATUS_INTERNAL(node_id, status) \ IS_ENABLED(DT_CAT3(node_id, _STATUS_, status)) +/** @brief Helper macro to OR multiple has property checks in a loop macro + * (for the specified device) + */ +#define DT_COMPAT_NODE_HAS_PROP_AND_OR(inst, compat, prop) \ + DT_NODE_HAS_PROP(DT_INST(inst, compat), prop) || + +/** + * @def DT_U32_C + * @brief Macro to add 32bit unsigned postfix to the devicetree address constants + */ +#if defined(_LINKER) || defined(_ASMLANGUAGE) +#define DT_U32_C(_v) (_v) +#else +#define DT_U32_C(_v) UINT32_C(_v) +#endif + /** * @def DT_U64_C * @brief Macro to add ULL postfix to the devicetree address constants @@ -4838,5 +5253,6 @@ #include #include #include +#include -#endif /* DEVICETREE_H */ +#endif /* ZEPHYR_INCLUDE_DEVICETREE_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/dma.h index 0b69272e..3dff8292 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/dma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/dma.h @@ -220,6 +220,25 @@ extern "C" { #define DT_DMAS_CELL_BY_NAME(node_id, name, cell) \ DT_PHA_BY_NAME(node_id, dmas, name, cell) +/** + * @brief Like DT_DMAS_CELL_BY_NAME(), but with a fallback to @p default_value + * + * If the value exists, this expands to DT_DMAS_CELL_BY_NAME(node_id, + * name, cell). The @p default_value parameter is not expanded in this case. + * + * Otherwise, this expands to @p default_value. + * + * @param node_id node identifier for a node with a dmas property + * @param name lowercase-and-underscores name of a dmas element + * as defined by the node's dma-names property + * @param cell lowercase-and-underscores cell name + * @param default_value a fallback value to expand to + * @return the cell's value or @p default_value + * @see DT_PHA_BY_NAME_OR() + */ +#define DT_DMAS_CELL_BY_NAME_OR(node_id, name, cell, default_value) \ + DT_PHA_BY_NAME_OR(node_id, dmas, name, cell, default_value) + /** * @brief Get a DT_DRV_COMPAT instance's DMA specifier's cell value by name * @param inst DT_DRV_COMPAT instance number diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/port-endpoint.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/port-endpoint.h new file mode 100644 index 00000000..08ff0ee3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/port-endpoint.h @@ -0,0 +1,275 @@ +/** + * @file + * @brief Port / Endpoint Devicetree macro public API header file. + */ + +/* + * Copyright 2024 NXP + * Copyright (c) 2024 tinyVision.ai Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DEVICETREE_PORT_ENDPOINT_H_ +#define ZEPHYR_INCLUDE_DEVICETREE_PORT_ENDPOINT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup devicetree-port-endpoint Devicetree Port Endpoint API + * @ingroup devicetree + * @{ + */ + +/** + * @brief Helper for @ref DT_INST_PORT_BY_ID + * + * This behaves the same way as @ref DT_INST_PORT_BY_ID but does not work if there is only + * a single port without address. + * + * @param inst instance number + * @param pid port ID + * @return port node associated with @p pid + */ +#define _DT_INST_PORT_BY_ID(inst, pid) \ + COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, ports)), \ + (DT_CHILD(DT_INST_CHILD(inst, ports), port_##pid)), (DT_INST_CHILD(inst, port_##pid))) + +/** + * @brief Get a port node from its id + * + * Given a device instance number, return a port node specified by its ID. + * It handles various ways of how a port could be defined. + * + * Example usage with DT_INST_PORT_BY_ID() to get the @c port@0 or @c port node: + * + * @code{.c} + * DT_INST_PORT_BY_ID(inst, 0) + * @endcode + * + * Example devicetree fragment: + * + * @code{.dts} + * &device { + * ports { + * #address-cells = <1>; + * #size-cells = <0>; + * port@0 { + * reg = <0x0>; + * }; + * }; + * }; + * @endcode + * + * @code{.dts} + * &device { + * #address-cells = <1>; + * #size-cells = <0>; + * port@0 { + * reg = <0x0>; + * }; + * }; + * @endcode + * + * @code{.dts} + * &device { + * port { + * }; + * }; + * @endcode + * + * @param inst instance number + * @param pid port ID + * @return port node associated with @p pid + */ +#define DT_INST_PORT_BY_ID(inst, pid) \ + COND_CODE_1(DT_NODE_EXISTS(_DT_INST_PORT_BY_ID(inst, pid)), \ + (_DT_INST_PORT_BY_ID(inst, pid)), (DT_INST_CHILD(inst, port))) + +/** + * @brief Helper for @ref DT_INST_ENDPOINT_BY_ID + * + * This behaves the same way as @ref DT_INST_PORT_BY_ID but does not work if there is only + * a single endpoint without address. + * + * @param inst instance number + * @param pid port ID + * @param eid endpoint ID + * @return endpoint node associated with @p eid and @p pid + */ +#define _DT_INST_ENDPOINT_BY_ID(inst, pid, eid) \ + DT_CHILD(DT_INST_PORT_BY_ID(inst, pid), endpoint_##eid) + +/** + * @brief Get an endpoint node from its id and its parent port id + * + * Given a device instance number, a port ID and an endpoint ID, return the endpoint node. + * It handles various ways of how a port and an endpoint could be defined as described in + * @ref DT_INST_PORT_BY_ID and below. + * + * Example usage with DT_INST_ENDPOINT_BY_ID() to get the @c endpoint or @c endpoint@0 node: + * + * @code{.c} + * DT_INST_ENDPOINT_BY_ID(inst, 0, 0) + * @endcode + * + * Example devicetree fragment: + * + * @code{.dts} + * &device { + * port { + * endpoint { + * }; + * }; + * }; + * @endcode + * + * @code{.dts} + * &device { + * port { + * #address-cells = <1>; + * #size-cells = <0>; + * endpoint@0 { + * reg = <0x0>; + * }; + * }; + * }; + * @endcode + * + * @code{.dts} + * &device { + * ports { + * #address-cells = <1>; + * #size-cells = <0>; + * port@0 { + * reg = <0x0>; + * #address-cells = <1>; + * #size-cells = <0>; + * endpoint@0 { + * reg = <0x0>; + * }; + * }; + * }; + * }; + * @endcode + * + * @param inst instance number + * @param pid port ID + * @param eid endpoint ID + * @return endpoint node associated with @p eid and @p pid + */ +#define DT_INST_ENDPOINT_BY_ID(inst, pid, eid) \ + COND_CODE_1(DT_NODE_EXISTS(_DT_INST_ENDPOINT_BY_ID(inst, pid, eid)), \ + (_DT_INST_ENDPOINT_BY_ID(inst, pid, eid)), \ + (DT_CHILD(DT_INST_PORT_BY_ID(inst, pid), endpoint))) + +/** + * @brief Get the device node from its endpoint node. + * + * Given an endpoint node id, return its device node id. + * This handles various ways of how a port and an endpoint could be defined as described in + * @ref DT_NODE_BY_ENDPOINT. + * + * Example usage with DT_NODE_BY_ENDPOINT() to get the @c &device node from its @c ep0 node: + * + * @code{.c} + * DT_NODE_BY_ENDPOINT(DT_NODELABEL(ep0)) + * @endcode + * + * Example devicetree fragment: + * + * @code{.dts} + * &device { + * port { + * #address-cells = <1>; + * #size-cells = <0>; + * ep0: endpoint@0 { + * reg = <0x0>; + * }; + * }; + * }; + * @endcode + * + * @code{.dts} + * &device { + * ports { + * #address-cells = <1>; + * #size-cells = <0>; + * port@0 { + * reg = <0x0>; + * #address-cells = <1>; + * #size-cells = <0>; + * ep0: endpoint@0 { + * reg = <0x0>; + * }; + * }; + * }; + * }; + * @endcode + * + * @param ep endpoint node + * @return device node associated with @p ep + */ +#define DT_NODE_BY_ENDPOINT(ep) \ + COND_CODE_1(DT_NODE_EXISTS(DT_CHILD(DT_PARENT(DT_GPARENT(ep)), ports)), \ + (DT_PARENT(DT_GPARENT(ep))), (DT_GPARENT(ep))) + +/** + * @brief Get the remote device node from a local endpoint node. + * + * Given an endpoint node id, return the remote device node that connects to this device via this + * local endpoint. This handles various ways of how a port and an endpoint could be defined as + * described in @ref DT_INST_PORT_BY_ID and @ref DT_INST_ENDPOINT_BY_ID. + * + * Example usage with DT_NODE_REMOTE_DEVICE() to get the remote device node @c &device1 from the + * local endpoint @c endpoint@0 node of the device @c &device0 node: + * + * @code{.c} + * DT_NODE_REMOTE_DEVICE(DT_NODELABEL(device0_ep_out)) + * @endcode + * + * Example devicetree fragment: + * + * @code{.dts} + * &device0 { + * port { + * #address-cells = <1>; + * #size-cells = <0>; + * device0_ep_out: endpoint@0 { + * reg = <0x0>; + * remote-endpoint-label = "device1_ep_in"; + * }; + * }; + * }; + * + * &device1 { + * ports { + * #address-cells = <1>; + * #size-cells = <0>; + * port@0 { + * reg = <0x0>; + * device1_ep_in: endpoint { + * remote-endpoint-label = "device0_ep_out"; + * }; + * }; + * }; + * }; + * @endcode + * + * @param ep endpoint node + * @return remote device node that connects to this device via @p ep + */ +#define DT_NODE_REMOTE_DEVICE(ep) \ + DT_NODE_BY_ENDPOINT(DT_NODELABEL(DT_STRING_TOKEN(ep, remote_endpoint_label))) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DEVICETREE_PORT_ENDPOINT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/spi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/spi.h index d1f916c3..db1b4996 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/spi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/devicetree/spi.h @@ -148,7 +148,7 @@ extern "C" { * @return node identifier for spi_dev's chip select GPIO controller */ #define DT_SPI_DEV_CS_GPIOS_CTLR(spi_dev) \ - DT_GPIO_CTLR_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev)) + DT_GPIO_CTLR_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR_RAW(spi_dev)) /** * @brief Get a SPI device's chip select GPIO pin number @@ -181,7 +181,7 @@ extern "C" { * @return pin number of spi_dev's chip select GPIO */ #define DT_SPI_DEV_CS_GPIOS_PIN(spi_dev) \ - DT_GPIO_PIN_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev)) + DT_GPIO_PIN_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR_RAW(spi_dev)) /** * @brief Get a SPI device's chip select GPIO flags @@ -209,7 +209,7 @@ extern "C" { * zero if there is none */ #define DT_SPI_DEV_CS_GPIOS_FLAGS(spi_dev) \ - DT_GPIO_FLAGS_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR(spi_dev)) + DT_GPIO_FLAGS_BY_IDX(DT_BUS(spi_dev), cs_gpios, DT_REG_ADDR_RAW(spi_dev)) /** * @brief Equivalent to DT_SPI_DEV_HAS_CS_GPIOS(DT_DRV_INST(inst)). diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/display/cfb.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/display/cfb.h index 6d10debe..9cdf81e2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/display/cfb.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/display/cfb.h @@ -9,8 +9,8 @@ * @brief Public Monochrome Character Framebuffer API */ -#ifndef __CFB_H__ -#define __CFB_H__ +#ifndef ZEPHYR_INCLUDE_DISPLAY_CFB_H_ +#define ZEPHYR_INCLUDE_DISPLAY_CFB_H_ #include #include @@ -256,4 +256,4 @@ void cfb_framebuffer_deinit(const struct device *dev); * @} */ -#endif /* __CFB_H__ */ +#endif /* ZEPHYR_INCLUDE_DISPLAY_CFB_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc.h index dc7d975a..1c95baa9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc.h @@ -321,7 +321,7 @@ struct adc_dt_spec { DT_FOREACH_CHILD_VARGS(ctlr, ADC_FOREACH_INPUT, input) #define ADC_FOREACH_INPUT(node, input) \ - IF_ENABLED(IS_EQ(DT_REG_ADDR(node), input), (node)) + IF_ENABLED(IS_EQ(DT_REG_ADDR_RAW(node), input), (node)) #define ADC_CHANNEL_CFG_FROM_DT_NODE(node_id) \ IF_ENABLED(DT_NODE_EXISTS(node_id), \ @@ -726,10 +726,7 @@ __syscall int adc_channel_setup(const struct device *dev, static inline int z_impl_adc_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg) { - const struct adc_driver_api *api = - (const struct adc_driver_api *)dev->api; - - return api->channel_setup(dev, channel_cfg); + return DEVICE_API_GET(adc, dev)->channel_setup(dev, channel_cfg); } /** @@ -777,10 +774,7 @@ __syscall int adc_read(const struct device *dev, static inline int z_impl_adc_read(const struct device *dev, const struct adc_sequence *sequence) { - const struct adc_driver_api *api = - (const struct adc_driver_api *)dev->api; - - return api->read(dev, sequence); + return DEVICE_API_GET(adc, dev)->read(dev, sequence); } /** @@ -828,10 +822,7 @@ static inline int z_impl_adc_read_async(const struct device *dev, const struct adc_sequence *sequence, struct k_poll_signal *async) { - const struct adc_driver_api *api = - (const struct adc_driver_api *)dev->api; - - return api->read_async(dev, sequence, async); + return DEVICE_API_GET(adc, dev)->read_async(dev, sequence, async); } #endif /* CONFIG_ADC_ASYNC */ @@ -846,10 +837,7 @@ static inline int z_impl_adc_read_async(const struct device *dev, */ static inline uint16_t adc_ref_internal(const struct device *dev) { - const struct adc_driver_api *api = - (const struct adc_driver_api *)dev->api; - - return api->ref_internal; + return DEVICE_API_GET(adc, dev)->ref_internal; } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc/current_sense_amplifier.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc/current_sense_amplifier.h index 888167b1..05c9a98d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc/current_sense_amplifier.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/adc/current_sense_amplifier.h @@ -12,9 +12,9 @@ struct current_sense_amplifier_dt_spec { const struct adc_dt_spec port; - uint32_t sense_micro_ohms; - uint32_t sense_gain_mult; - uint32_t sense_gain_div; + uint32_t sense_milli_ohms; + uint16_t sense_gain_mult; + uint16_t sense_gain_div; struct gpio_dt_spec power_gpio; }; @@ -31,7 +31,7 @@ struct current_sense_amplifier_dt_spec { #define CURRENT_SENSE_AMPLIFIER_DT_SPEC_GET(node_id) \ { \ .port = ADC_DT_SPEC_GET(node_id), \ - .sense_micro_ohms = DT_PROP(node_id, sense_resistor_micro_ohms), \ + .sense_milli_ohms = DT_PROP(node_id, sense_resistor_milli_ohms), \ .sense_gain_mult = DT_PROP(node_id, sense_gain_mult), \ .sense_gain_div = DT_PROP(node_id, sense_gain_div), \ .power_gpio = GPIO_DT_SPEC_GET_OR(node_id, power_gpios, {0}), \ @@ -51,8 +51,10 @@ current_sense_amplifier_scale_dt(const struct current_sense_amplifier_dt_spec *s /* store in a temporary 64 bit variable to prevent overflow during calculation */ int64_t tmp = *v_to_i; - /* multiplies by 1,000,000 before dividing by sense resistance in micro-ohms. */ - tmp = tmp * 1000000 / spec->sense_micro_ohms * spec->sense_gain_div / spec->sense_gain_mult; + /* (INT32_MAX * 1000 * UINT16_MAX) < INT64_MAX + * Therefore all multiplications can be done before divisions, preserving resolution. + */ + tmp = tmp * 1000 * spec->sense_gain_div / spec->sense_milli_ohms / spec->sense_gain_mult; *v_to_i = (int32_t)tmp; } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/bluetooth.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/bluetooth.h index 2f969c40..330ac850 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/bluetooth.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/bluetooth.h @@ -21,7 +21,7 @@ #include #include -#include +#include #include #include #include @@ -46,6 +46,14 @@ enum { * initial connection data length parameters are not equal to the * default data length parameters. Therefore the host should initiate * the DLE procedure after connection establishment. + * + * That requirement is stated in Core Spec v5.4 Vol 6 Part B. 4.5.10 + * Data PDU length management: + * + * > For a new connection: + * > - ... If either value is not 27, then the Controller should + * > initiate the Data Length Update procedure at the earliest + * > practical opportunity. */ BT_HCI_QUIRK_NO_AUTO_DLE = BIT(1), }; @@ -61,10 +69,15 @@ enum bt_hci_bus { BT_HCI_BUS_SDIO = 6, BT_HCI_BUS_SPI = 7, BT_HCI_BUS_I2C = 8, - BT_HCI_BUS_IPM = 9, + BT_HCI_BUS_SMD = 9, + BT_HCI_BUS_VIRTIO = 10, + BT_HCI_BUS_IPC = 11, + /* IPM is deprecated and simply an alias for IPC */ + BT_HCI_BUS_IPM = BT_HCI_BUS_IPC, }; -#define BT_DT_HCI_QUIRK_OR(node_id, prop, idx) DT_STRING_TOKEN_BY_IDX(node_id, prop, idx) +#define BT_DT_HCI_QUIRK_OR(node_id, prop, idx) \ + UTIL_CAT(BT_HCI_QUIRK_, DT_STRING_UPPER_TOKEN_BY_IDX(node_id, prop, idx)) #define BT_DT_HCI_QUIRKS_GET(node_id) COND_CODE_1(DT_NODE_HAS_PROP(node_id, bt_hci_quirks), \ (DT_FOREACH_PROP_ELEM_SEP(node_id, \ bt_hci_quirks, \ @@ -76,7 +89,8 @@ enum bt_hci_bus { #define BT_DT_HCI_NAME_GET(node_id) DT_PROP_OR(node_id, bt_hci_name, "HCI") #define BT_DT_HCI_NAME_INST_GET(inst) BT_DT_HCI_NAME_GET(DT_DRV_INST(inst)) -#define BT_DT_HCI_BUS_GET(node_id) DT_STRING_TOKEN_OR(node_id, bt_hci_bus, BT_HCI_BUS_VIRTUAL) +#define BT_DT_HCI_BUS_GET(node_id) \ + UTIL_CAT(BT_HCI_BUS_, DT_STRING_UPPER_TOKEN_OR(node_id, bt_hci_bus, VIRTUAL)) #define BT_DT_HCI_BUS_INST_GET(inst) BT_DT_HCI_BUS_GET(DT_DRV_INST(inst)) typedef int (*bt_hci_recv_t)(const struct device *dev, struct net_buf *buf); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can.h index 0d72cc64..5f32b8c3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can.h @@ -45,26 +45,17 @@ extern "C" { * @brief Bit mask for a standard (11-bit) CAN identifier. */ #define CAN_STD_ID_MASK 0x7FFU -/** - * @brief Maximum value for a standard (11-bit) CAN identifier. - * - * @deprecated Use ``CAN_STD_ID_MASK`` instead. - */ -#define CAN_MAX_STD_ID CAN_STD_ID_MASK __DEPRECATED_MACRO + /** * @brief Bit mask for an extended (29-bit) CAN identifier. */ #define CAN_EXT_ID_MASK 0x1FFFFFFFU -/** - * @brief Maximum value for an extended (29-bit) CAN identifier. - * - * @deprecated Use ``CAN_EXT_ID_MASK`` instead. - */ -#define CAN_MAX_EXT_ID CAN_EXT_ID_MASK __DEPRECATED_MACRO + /** * @brief Maximum data length code for CAN 2.0A/2.0B. */ #define CAN_MAX_DLC 8U + /** * @brief Maximum data length code for CAN FD. */ @@ -835,8 +826,16 @@ static inline int z_impl_can_get_core_clock(const struct device *dev, uint32_t * * * Get the minimum supported bitrate for the CAN controller/transceiver combination. * + * @note The minimum bitrate represents limitations of the CAN controller/transceiver + * combination. Whether the CAN controller can achieve this bitrate depends on the CAN core clock + * rate and the minimum CAN timing limits. + * + * @see can_get_core_clock() + * @see can_get_timing_min() + * @see can_get_timing_data_min() + * * @param dev Pointer to the device structure for the driver instance. - * @return Minimum supported bitrate in bits/s + * @return Minimum supported bitrate in bits/s. A value of 0 means the lower limit is unspecified. */ __syscall uint32_t can_get_bitrate_min(const struct device *dev); @@ -847,31 +846,19 @@ static inline uint32_t z_impl_can_get_bitrate_min(const struct device *dev) return common->min_bitrate; } -/** - * @brief Get minimum supported bitrate - * - * Get the minimum supported bitrate for the CAN controller/transceiver combination. - * - * @deprecated Use @a can_get_bitrate_min() instead. - * - * @param dev Pointer to the device structure for the driver instance. - * @param[out] min_bitrate Minimum supported bitrate in bits/s - * - * @retval -EIO General input/output error. - * @retval -ENOSYS If this function is not implemented by the driver. - */ -__deprecated static inline int can_get_min_bitrate(const struct device *dev, uint32_t *min_bitrate) -{ - *min_bitrate = can_get_bitrate_min(dev); - - return 0; -} - /** * @brief Get maximum supported bitrate * * Get the maximum supported bitrate for the CAN controller/transceiver combination. * + * @note The maximum bitrate represents limitations of the CAN controller/transceiver + * combination. Whether the CAN controller can achieve this bitrate depends on the CAN core clock + * rate and the maximum CAN timing limits. + * + * @see can_get_core_clock() + * @see can_get_timing_max() + * @see can_get_timing_data_max() + * * @param dev Pointer to the device structure for the driver instance. * @return Maximum supported bitrate in bits/s */ @@ -884,27 +871,6 @@ static inline uint32_t z_impl_can_get_bitrate_max(const struct device *dev) return common->max_bitrate; } -/** - * @brief Get maximum supported bitrate - * - * Get the maximum supported bitrate for the CAN controller/transceiver combination. - * - * @deprecated Use @a can_get_bitrate_max() instead. - * - * @param dev Pointer to the device structure for the driver instance. - * @param[out] max_bitrate Maximum supported bitrate in bits/s - * - * @retval 0 If successful. - * @retval -EIO General input/output error. - * @retval -ENOSYS If this function is not implemented by the driver. - */ -__deprecated static inline int can_get_max_bitrate(const struct device *dev, uint32_t *max_bitrate) -{ - *max_bitrate = can_get_bitrate_max(dev); - - return 0; -} - /** * @brief Get the minimum supported timing parameter values. * @@ -1087,29 +1053,6 @@ __syscall int can_set_timing_data(const struct device *dev, */ __syscall int can_set_bitrate_data(const struct device *dev, uint32_t bitrate_data); -/** - * @brief Fill in the prescaler value for a given bitrate and timing - * - * Fill the prescaler value in the timing struct. The sjw, prop_seg, phase_seg1 - * and phase_seg2 must be given. - * - * The returned bitrate error is remainder of the division of the clock rate by - * the bitrate times the timing segments. - * - * @deprecated This function allows for bitrate errors, but bitrate errors between nodes on the same - * network leads to them drifting apart after the start-of-frame (SOF) synchronization - * has taken place. - * - * @param dev Pointer to the device structure for the driver instance. - * @param timing Result is written into the can_timing struct provided. - * @param bitrate Target bitrate. - * - * @retval 0 or positive bitrate error. - * @retval Negative error code on error. - */ -__deprecated int can_calc_prescaler(const struct device *dev, struct can_timing *timing, - uint32_t bitrate); - /** * @brief Configure the bus timing of a CAN controller. * @@ -1425,7 +1368,7 @@ static inline void z_impl_can_remove_rx_filter(const struct device *dev, int fil { const struct can_driver_api *api = (const struct can_driver_api *)dev->api; - return api->remove_rx_filter(dev, filter_id); + api->remove_rx_filter(dev, filter_id); } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can/transceiver.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can/transceiver.h index c6f0b3c8..9dcf2caf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can/transceiver.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/can/transceiver.h @@ -65,10 +65,7 @@ __subsystem struct can_transceiver_driver_api { */ static inline int can_transceiver_enable(const struct device *dev, can_mode_t mode) { - const struct can_transceiver_driver_api *api = - (const struct can_transceiver_driver_api *)dev->api; - - return api->enable(dev, mode); + return DEVICE_API_GET(can_transceiver, dev)->enable(dev, mode); } /** @@ -87,10 +84,7 @@ static inline int can_transceiver_enable(const struct device *dev, can_mode_t mo */ static inline int can_transceiver_disable(const struct device *dev) { - const struct can_transceiver_driver_api *api = - (const struct can_transceiver_driver_api *)dev->api; - - return api->disable(dev); + return DEVICE_API_GET(can_transceiver, dev)->disable(dev); } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/adi_max32_clock_control.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/adi_max32_clock_control.h index 2922b5e2..cd889d37 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/adi_max32_clock_control.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/adi_max32_clock_control.h @@ -30,6 +30,8 @@ struct max32_perclk { * ADI_MAX32_PRPH_CLK_SRC_INRO * ADI_MAX32_PRPH_CLK_SRC_ISO * ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8 + * ADI_MAX32_PRPH_CLK_SRC_IPLL + * ADI_MAX32_PRPH_CLK_SRC_EBO */ uint32_t clk_src; }; @@ -38,11 +40,13 @@ struct max32_perclk { #define ADI_MAX32_SYSCLK_PRESCALER DT_PROP_OR(DT_NODELABEL(gcr), sysclk_prescaler, 1) #define ADI_MAX32_CLK_IPO_FREQ DT_PROP(DT_NODELABEL(clk_ipo), clock_frequency) -#define ADI_MAX32_CLK_ERFO_FREQ DT_PROP(DT_NODELABEL(clk_erfo), clock_frequency) +#define ADI_MAX32_CLK_ERFO_FREQ DT_PROP_OR(DT_NODELABEL(clk_erfo), clock_frequency, 0) #define ADI_MAX32_CLK_IBRO_FREQ DT_PROP(DT_NODELABEL(clk_ibro), clock_frequency) #define ADI_MAX32_CLK_ISO_FREQ DT_PROP_OR(DT_NODELABEL(clk_iso), clock_frequency, 0) #define ADI_MAX32_CLK_INRO_FREQ DT_PROP(DT_NODELABEL(clk_inro), clock_frequency) #define ADI_MAX32_CLK_ERTCO_FREQ DT_PROP(DT_NODELABEL(clk_ertco), clock_frequency) +#define ADI_MAX32_CLK_IPLL_FREQ DT_PROP_OR(DT_NODELABEL(clk_ipll), clock_frequency, 0) +#define ADI_MAX32_CLK_EBO_FREQ DT_PROP_OR(DT_NODELABEL(clk_ebo), clock_frequency, 0) /* External clock may not be defined so _OR is used */ #define ADI_MAX32_CLK_EXTCLK_FREQ DT_PROP_OR(DT_NODELABEL(clk_extclk), clock_frequency, 0) @@ -76,6 +80,14 @@ struct max32_perclk { #define ADI_MAX32_SYSCLK_SRC ADI_MAX32_CLK_EXTCLK #define ADI_MAX32_SYSCLK_FREQ (ADI_MAX32_CLK_EXTCLK_FREQ / ADI_MAX32_SYSCLK_PRESCALER) #endif +#if DT_SAME_NODE(DT_GCR_CLOCKS_CTRL, DT_NODELABEL(clk_ipll)) +#define ADI_MAX32_SYSCLK_SRC ADI_MAX32_CLK_IPLL +#define ADI_MAX32_SYSCLK_FREQ (ADI_MAX32_CLK_IPLL_FREQ / ADI_MAX32_SYSCLK_PRESCALER) +#endif +#if DT_SAME_NODE(DT_GCR_CLOCKS_CTRL, DT_NODELABEL(clk_ebo)) +#define ADI_MAX32_SYSCLK_SRC ADI_MAX32_CLK_EBO +#define ADI_MAX32_SYSCLK_FREQ (ADI_MAX32_CLK_EBO_FREQ / ADI_MAX32_SYSCLK_PRESCALER) +#endif #ifndef ADI_MAX32_SYSCLK_SRC #define ADI_MAX32_SYSCLK_SRC ADI_MAX32_CLK_IPO @@ -93,6 +105,8 @@ struct max32_perclk { : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_ISO ? ADI_MAX32_CLK_ISO_FREQ \ : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8 ? (ADI_MAX32_CLK_IBRO_FREQ / 8) \ : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_EXTCLK ? ADI_MAX32_CLK_EXTCLK_FREQ \ + : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_IPLL ? ADI_MAX32_CLK_IPLL_FREQ \ + : (clk_src) == ADI_MAX32_PRPH_CLK_SRC_EBO ? ADI_MAX32_CLK_EBO_FREQ \ : 0) #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_ADI_MAX32_CLOCK_CONTROL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/clock_control_silabs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/clock_control_silabs.h new file mode 100644 index 00000000..d608b1da --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/clock_control_silabs.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ + +#include + +#if defined(CONFIG_SOC_SERIES_EFR32MG21) +#include +#elif defined(CONFIG_SOC_SERIES_EFR32BG22) +#include +#elif defined(CONFIG_SOC_SERIES_EFR32MG24) +#include +#elif defined(CONFIG_SOC_SERIES_EFR32BG27) +#include +#endif + +struct silabs_clock_control_cmu_config { + uint32_t bus_clock; + uint8_t branch; +}; + +#define SILABS_DT_CLOCK_CFG(node_id) \ + { \ + .bus_clock = DT_CLOCKS_CELL(node_id, enable), \ + .branch = DT_CLOCKS_CELL(node_id, branch), \ + } + +#define SILABS_DT_INST_CLOCK_CFG(inst) \ + { \ + .bus_clock = DT_INST_CLOCKS_CELL(inst, enable), \ + .branch = DT_INST_CLOCKS_CELL(inst, branch), \ + } + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/esp32_clock_control.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/esp32_clock_control.h index aa83d78e..eb6bebc1 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/esp32_clock_control.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/esp32_clock_control.h @@ -13,6 +13,8 @@ #include #elif defined(CONFIG_SOC_SERIES_ESP32S3) #include +#elif defined(CONFIG_SOC_SERIES_ESP32C2) +#include #elif defined(CONFIG_SOC_SERIES_ESP32C3) #include #elif defined(CONFIG_SOC_SERIES_ESP32C6) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/nrf_clock_control.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/nrf_clock_control.h index 5ec40977..f9466770 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/nrf_clock_control.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/nrf_clock_control.h @@ -8,7 +8,9 @@ #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CONTROL_H_ #include +#ifdef NRF_CLOCK #include +#endif #include #include @@ -16,6 +18,8 @@ extern "C" { #endif +#if defined(CONFIG_CLOCK_CONTROL_NRF) + /** @brief Clocks handled by the CLOCK peripheral. * * Enum shall be used as a sys argument in clock_control API. @@ -113,6 +117,13 @@ int z_nrf_clock_calibration_count(void); */ int z_nrf_clock_calibration_skips_count(void); + +/** @brief Returns information if LF clock calibration is in progress. + * + * @return True if calibration is in progress, false otherwise. + */ +bool z_nrf_clock_calibration_is_in_progress(void); + /** @brief Get onoff service for given clock subsystem. * * @param sys Subsystem. @@ -151,6 +162,187 @@ void z_nrf_clock_bt_ctlr_hf_request(void); */ void z_nrf_clock_bt_ctlr_hf_release(void); +#endif /* defined(CONFIG_CLOCK_CONTROL_NRF) */ + + +#if defined(CONFIG_CLOCK_CONTROL_NRF2) + +/* Specifies to use the maximum available frequency for a given clock. */ +#define NRF_CLOCK_CONTROL_FREQUENCY_MAX UINT32_MAX + +/* Specifies to use the maximum available accuracy for a given clock. */ +#define NRF_CLOCK_CONTROL_ACCURACY_MAX 1 +/* Specifies the required clock accuracy in parts-per-million. */ +#define NRF_CLOCK_CONTROL_ACCURACY_PPM(ppm) (ppm) + +/* Specifies that high precision of the clock is required. */ +#define NRF_CLOCK_CONTROL_PRECISION_HIGH 1 +/* Specifies that default precision of the clock is sufficient. */ +#define NRF_CLOCK_CONTROL_PRECISION_DEFAULT 0 + +struct nrf_clock_spec { + uint32_t frequency; + uint16_t accuracy : 15; + uint16_t precision : 1; +}; + +__subsystem struct nrf_clock_control_driver_api { + struct clock_control_driver_api std_api; + + int (*request)(const struct device *dev, + const struct nrf_clock_spec *spec, + struct onoff_client *cli); + int (*release)(const struct device *dev, + const struct nrf_clock_spec *spec); + int (*cancel_or_release)(const struct device *dev, + const struct nrf_clock_spec *spec, + struct onoff_client *cli); +}; + +/** + * @brief Request a reservation to use a given clock with specified attributes. + * + * The return value indicates the success or failure of an attempt to initiate + * an operation to request the clock be made available. If initiation of the + * operation succeeds, the result of the request operation is provided through + * the configured client notification method, possibly before this call returns. + * + * Note that the call to this function may succeed in a case where the actual + * request fails. Always check the operation completion result. + * + * @param dev pointer to the clock device structure. + * @param spec specification of minimal acceptable attributes, like frequency, + * accuracy, and precision, required for the clock. + * Value of 0 has the meaning of "default" and can be passed + * instead of a given attribute if there is no strict requirement + * in this regard. If there is no specific requirement for any of + * the attributes, this parameter can be NULL. + * @param cli pointer to client state providing instructions on synchronous + * expectations and how to notify the client when the request + * completes. Behavior is undefined if client passes a pointer + * object associated with an incomplete service operation. + * + * @retval non-negative the observed state of the on-off service associated + * with the clock machine at the time the request was + * processed (see onoff_request()), if successful. + * @retval -EIO if service has recorded an error. + * @retval -EINVAL if the function parameters are invalid or the clock + * attributes cannot be provided (e.g. the requested accuracy + * is unavailable). + * @retval -EAGAIN if the reference count would overflow. + */ +static inline +int nrf_clock_control_request(const struct device *dev, + const struct nrf_clock_spec *spec, + struct onoff_client *cli) +{ + const struct nrf_clock_control_driver_api *api = + (const struct nrf_clock_control_driver_api *)dev->api; + + return api->request(dev, spec, cli); +} + +/** + * @brief Synchronously request a reservation to use a given clock with specified attributes. + * + * Function can only be called from thread context as it blocks until request is completed. + * @see nrf_clock_control_request(). + * + * @param dev pointer to the clock device structure. + * @param spec See nrf_clock_control_request(). + * @param timeout Request timeout. + * + * @retval 0 if request is fulfilled. + * @retval -EWOULDBLOCK if request is called from the interrupt context. + * @retval negative See error codes returned by nrf_clock_control_request(). + */ +int nrf_clock_control_request_sync(const struct device *dev, + const struct nrf_clock_spec *spec, + k_timeout_t timeout); + +/** + * @brief Release a reserved use of a clock. + * + * @param dev pointer to the clock device structure. + * @param spec the same specification of the clock attributes that was used + * in the reservation request (so that the clock control module + * can keep track of what attributes are still requested). + * + * @retval non-negative the observed state of the on-off service associated + * with the clock machine at the time the request was + * processed (see onoff_release()), if successful. + * @retval -EIO if service has recorded an error. + * @retval -ENOTSUP if the service is not in a state that permits release. + */ +static inline +int nrf_clock_control_release(const struct device *dev, + const struct nrf_clock_spec *spec) +{ + const struct nrf_clock_control_driver_api *api = + (const struct nrf_clock_control_driver_api *)dev->api; + + return api->release(dev, spec); +} + +/** + * @brief Safely cancel a reservation request. + * + * It may be that a client has issued a reservation request but needs to + * shut down before the request has completed. This function attempts to + * cancel the request and issues a release if cancellation fails because + * the request was completed. This synchronously ensures that ownership + * data reverts to the client so is available for a future request. + * + * @param dev pointer to the clock device structure. + * @param spec the same specification of the clock attributes that was used + * in the reservation request. + * @param cli a pointer to the same client state that was provided + * when the operation to be cancelled was issued. + * + * @retval ONOFF_STATE_TO_ON if the cancellation occurred before the transition + * completed. + * @retval ONOFF_STATE_ON if the cancellation occurred after the transition + * completed. + * @retval -EINVAL if the parameters are invalid. + * @retval negative other errors produced by onoff_release(). + */ +static inline +int nrf_clock_control_cancel_or_release(const struct device *dev, + const struct nrf_clock_spec *spec, + struct onoff_client *cli) +{ + const struct nrf_clock_control_driver_api *api = + (const struct nrf_clock_control_driver_api *)dev->api; + + return api->cancel_or_release(dev, spec, cli); +} + +/** @brief Request the HFXO from Zero Latency Interrupt context. + * + * Function is optimized for use in Zero Latency Interrupt context. + * It does not give notification when the HFXO is ready, so each + * user must put the request early enough to make sure the HFXO + * ramp-up has finished on time. + * + * This function uses reference counting so the caller must ensure + * that every nrf_clock_control_hfxo_request() call has a matching + * nrf_clock_control_hfxo_release() call. + */ +void nrf_clock_control_hfxo_request(void); + +/** @brief Release the HFXO from Zero Latency Interrupt context. + * + * Function is optimized for use in Zero Latency Interrupt context. + * + * Calls to this function must be coupled with prior calls + * to nrf_clock_control_hfxo_request(), because it uses basic + * reference counting to make sure the HFXO is released when + * there are no more pending requests. + */ +void nrf_clock_control_hfxo_release(void); + +#endif /* defined(CONFIG_CLOCK_CONTROL_NRF2) */ + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/renesas_ra_cgc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/renesas_ra_cgc.h index 940d5e34..1c29c9c8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/renesas_ra_cgc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/renesas_ra_cgc.h @@ -9,13 +9,72 @@ #include #include +#define RA_CGC_PROP_HAS_STATUS_OKAY_OR(node_id, prop, default_value) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (DT_PROP(node_id, prop)), (default_value)) + +#define RA_CGC_CLK_SRC(node_id) \ + COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), \ + (UTIL_CAT(BSP_CLOCKS_SOURCE_, DT_NODE_FULL_NAME_UPPER_TOKEN(node_id))), \ + (BSP_CLOCKS_CLOCK_DISABLED)) + +#define RA_CGC_CLK_DIV(clk, prop, default_value) \ + UTIL_CAT(RA_CGC_DIV_, DT_NODE_FULL_NAME_UPPER_TOKEN(clk)) \ + (RA_CGC_PROP_HAS_STATUS_OKAY_OR(clk, prop, default_value)) + +#define RA_CGC_DIV_BCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_CANFDCLK(n) UTIL_CAT(BSP_CLOCKS_CANFD_CLOCK_DIV_, n) +#define RA_CGC_DIV_CECCLK(n) UTIL_CAT(BSP_CLOCKS_CEC_CLOCK_DIV_, n) +#define RA_CGC_DIV_CLKOUT(n) UTIL_CAT(BSP_CLOCKS_CLKOUT_DIV_, n) +#define RA_CGC_DIV_CPUCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_FCLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_I3CCLK(n) UTIL_CAT(BSP_CLOCKS_I3C_CLOCK_DIV_, n) +#define RA_CGC_DIV_ICLK(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_LCDCLK(n) UTIL_CAT(BSP_CLOCKS_LCD_CLOCK_DIV_, n) +#define RA_CGC_DIV_OCTASPICLK(n) UTIL_CAT(BSP_CLOCKS_OCTA_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKA(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKB(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKC(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKD(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PCLKE(n) UTIL_CAT(BSP_CLOCKS_SYS_CLOCK_DIV_, n) +#define RA_CGC_DIV_PLL(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLLP(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLLQ(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLLR(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2P(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2Q(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_PLL2R(n) UTIL_CAT(BSP_CLOCKS_PLL_DIV_, n) +#define RA_CGC_DIV_SCICLK(n) UTIL_CAT(BSP_CLOCKS_SCI_CLOCK_DIV_, n) +#define RA_CGC_DIV_SPICLK(n) UTIL_CAT(BSP_CLOCKS_SPI_CLOCK_DIV_, n) +#define RA_CGC_DIV_U60CLK(n) UTIL_CAT(BSP_CLOCKS_USB60_CLOCK_DIV_, n) +#define RA_CGC_DIV_UCLK(n) UTIL_CAT(BSP_CLOCKS_USB_CLOCK_DIV_, n) + +#define BSP_CLOCKS_SOURCE_PLL BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLLP BSP_CLOCKS_SOURCE_CLOCK_PLL +#define BSP_CLOCKS_SOURCE_PLLQ BSP_CLOCKS_SOURCE_CLOCK_PLL1Q +#define BSP_CLOCKS_SOURCE_PLLR BSP_CLOCKS_SOURCE_CLOCK_PLL1R + +#define BSP_CLOCKS_SOURCE_PLL2 BSP_CLOCKS_SOURCE_CLOCK_PLL2 +#define BSP_CLOCKS_SOURCE_PLL2P BSP_CLOCKS_SOURCE_CLOCK_PLL2 +#define BSP_CLOCKS_SOURCE_PLL2Q BSP_CLOCKS_SOURCE_CLOCK_PLL2Q +#define BSP_CLOCKS_SOURCE_PLL2R BSP_CLOCKS_SOURCE_CLOCK_PLL2R + +#define BSP_CLOCKS_CLKOUT_DIV_1 (0) +#define BSP_CLOCKS_CLKOUT_DIV_2 (1) +#define BSP_CLOCKS_CLKOUT_DIV_4 (2) +#define BSP_CLOCKS_CLKOUT_DIV_8 (3) +#define BSP_CLOCKS_CLKOUT_DIV_16 (4) +#define BSP_CLOCKS_CLKOUT_DIV_32 (5) +#define BSP_CLOCKS_CLKOUT_DIV_64 (6) +#define BSP_CLOCKS_CLKOUT_DIV_128 (7) + struct clock_control_ra_pclk_cfg { uint32_t clk_src; uint32_t clk_div; }; struct clock_control_ra_subsys_cfg { - volatile uint32_t *mstp; + uint32_t mstp; uint32_t stop_bit; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/stm32_clock_control.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/stm32_clock_control.h index a9ce911e..753aa0ea 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -17,12 +17,17 @@ #elif defined(CONFIG_SOC_SERIES_STM32F0X) #include #elif defined(CONFIG_SOC_SERIES_STM32F1X) +#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE) +#include +#else #include +#endif #elif defined(CONFIG_SOC_SERIES_STM32F3X) #include #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ defined(CONFIG_SOC_SERIES_STM32F4X) #include +#include #elif defined(CONFIG_SOC_SERIES_STM32F7X) #include #elif defined(CONFIG_SOC_SERIES_STM32G0X) @@ -38,6 +43,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32WBX) #include +#elif defined(CONFIG_SOC_SERIES_STM32WB0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32WLX) #include #elif defined(CONFIG_SOC_SERIES_STM32H5X) @@ -46,6 +53,8 @@ #include #elif defined(CONFIG_SOC_SERIES_STM32H7RSX) #include +#elif defined(CONFIG_SOC_SERIES_STM32U0X) +#include #elif defined(CONFIG_SOC_SERIES_STM32U5X) #include #elif defined(CONFIG_SOC_SERIES_STM32WBAX) @@ -142,6 +151,7 @@ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u0_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \ @@ -174,6 +184,8 @@ #define STM32_PLLI2S_ENABLED 1 #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m) #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) +#define STM32_PLLI2S_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_q) +#define STM32_PLLI2S_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_q, 1) #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) #endif @@ -241,7 +253,7 @@ #endif /** PLL/PLL1 clock source */ -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) && \ +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) @@ -266,7 +278,7 @@ #endif /** PLL2 clock source */ -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) && \ +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks) #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2)) #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) @@ -282,7 +294,7 @@ #endif /** PLL3 clock source */ -#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll3), okay) && \ +#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \ DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks) #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3)) #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) @@ -422,7 +434,8 @@ /** Driver structure definition */ struct stm32_pclken { - uint32_t bus; + uint32_t bus : STM32_CLOCK_DIV_SHIFT; + uint32_t div : (32 - STM32_CLOCK_DIV_SHIFT); uint32_t enr; }; @@ -431,7 +444,9 @@ struct stm32_pclken { #define STM32_CLOCK_INFO(clk_index, node_id) \ { \ .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \ - .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) \ + .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) & 0xff, \ + .div = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) >> \ + STM32_CLOCK_DIV_SHIFT, \ } #define STM32_DT_CLOCKS(node_id) \ { \ @@ -484,6 +499,38 @@ struct stm32_pclken { #define STM32_CLOCK_VAL_GET(clock) \ (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK) +/** + * @brief Obtain register field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_REG_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_REG_SHIFT) & STM32_MCO_CFGR_REG_MASK) + +/** + * @brief Obtain position field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_SHIFT_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_SHIFT_SHIFT) & STM32_MCO_CFGR_SHIFT_MASK) + +/** + * @brief Obtain mask field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_MASK_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_MASK_SHIFT) & STM32_MCO_CFGR_MASK_MASK) + +/** + * @brief Obtain value field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_VAL_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_VAL_SHIFT) & STM32_MCO_CFGR_VAL_MASK) + #if defined(STM32_HSE_CSS) /** * @brief Called if the HSE clock security system detects a clock fault. @@ -496,4 +543,25 @@ struct stm32_pclken { void stm32_hse_css_callback(void); #endif +#ifdef CONFIG_SOC_SERIES_STM32WB0X +/** + * @internal + * @brief Type definition for LSI frequency update callbacks + */ +typedef void (*lsi_update_cb_t)(uint32_t new_lsi_frequency); + +/** + * @internal + * @brief Registers a callback to invoke after each runtime measure and + * update of the LSI frequency is completed. + * + * @param cb Callback to invoke + * @return 0 Registration successful + * @return ENOMEM Too many callbacks registered + * + * @note Callbacks are NEVER invoked if runtime LSI measurement is disabled + */ +int stm32wb0_register_lsi_update_callback(lsi_update_cb_t cb); +#endif /* CONFIG_SOC_SERIES_STM32WB0X */ + #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator.h new file mode 100644 index 00000000..1a6609ca --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_H_ +#define ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_H_ + +/** + * @brief Comparator Interface + * @defgroup comparator_interface Comparator Interface + * @since 4.0 + * @version 0.1.0 + * @ingroup io_interfaces + * @{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Comparator trigger enumerations */ +enum comparator_trigger { + /** No trigger */ + COMPARATOR_TRIGGER_NONE = 0, + /** Trigger on rising edge of comparator output */ + COMPARATOR_TRIGGER_RISING_EDGE, + /** Trigger on falling edge of comparator output */ + COMPARATOR_TRIGGER_FALLING_EDGE, + /** Trigger on both edges of comparator output */ + COMPARATOR_TRIGGER_BOTH_EDGES +}; + +/** Comparator callback template */ +typedef void (*comparator_callback_t)(const struct device *dev, void *user_data); + +/** @cond INTERNAL_HIDDEN */ + +typedef int (*comparator_api_get_output)(const struct device *dev); +typedef int (*comparator_api_set_trigger)(const struct device *dev, + enum comparator_trigger trigger); +typedef int (*comparator_api_set_trigger_callback)(const struct device *dev, + comparator_callback_t callback, + void *user_data); +typedef int (*comparator_api_trigger_is_pending)(const struct device *dev); + +__subsystem struct comparator_driver_api { + comparator_api_get_output get_output; + comparator_api_set_trigger set_trigger; + comparator_api_set_trigger_callback set_trigger_callback; + comparator_api_trigger_is_pending trigger_is_pending; +}; + +/** @endcond */ + +/** + * @brief Get comparator's output state + * + * @param dev Comparator device + * + * @retval 1 Output state is high + * @retval 0 Output state is low + * @retval -errno code Failure + */ +__syscall int comparator_get_output(const struct device *dev); + +static inline int z_impl_comparator_get_output(const struct device *dev) +{ + return DEVICE_API_GET(comparator, dev)->get_output(dev); +} + +/** + * @brief Set comparator's trigger + * + * @param dev Comparator device + * @param trigger Trigger for signal and callback + * + * @retval 0 Successful + * @retval -errno code Failure + */ +__syscall int comparator_set_trigger(const struct device *dev, + enum comparator_trigger trigger); + +static inline int z_impl_comparator_set_trigger(const struct device *dev, + enum comparator_trigger trigger) +{ + return DEVICE_API_GET(comparator, dev)->set_trigger(dev, trigger); +} + +/** + * @brief Set comparator's trigger callback + * + * @param dev Comparator device + * @param callback Trigger callback + * @param user_data User data passed to callback + * + * @retval 0 Successful + * @retval -errno code Failure + * + * @note Set callback to NULL to disable callback + * @note Callback is called immediately if trigger is pending + */ +static inline int comparator_set_trigger_callback(const struct device *dev, + comparator_callback_t callback, + void *user_data) +{ + return DEVICE_API_GET(comparator, dev)->set_trigger_callback(dev, callback, user_data); +} + +/** + * @brief Check if comparator's trigger is pending and clear it + * + * @param dev Comparator device + * + * @retval 1 Trigger was pending + * @retval 0 Trigger was cleared + * @retval -errno code Failure + */ +__syscall int comparator_trigger_is_pending(const struct device *dev); + +static inline int z_impl_comparator_trigger_is_pending(const struct device *dev) +{ + return DEVICE_API_GET(comparator, dev)->trigger_is_pending(dev); +} + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#include + +#endif /* ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/fake_comp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/fake_comp.h new file mode 100644 index 00000000..c24858c1 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/fake_comp.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_FAKE_H_ +#define ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_FAKE_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +DECLARE_FAKE_VALUE_FUNC(int, + comp_fake_comp_get_output, + const struct device *); + +DECLARE_FAKE_VALUE_FUNC(int, + comp_fake_comp_set_trigger, + const struct device *, + enum comparator_trigger); + +DECLARE_FAKE_VALUE_FUNC(int, + comp_fake_comp_set_trigger_callback, + const struct device *, + comparator_callback_t, + void *); + +DECLARE_FAKE_VALUE_FUNC(int, + comp_fake_comp_trigger_is_pending, + const struct device *); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_COMPARATOR_FAKE_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/mcux_acmp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/mcux_acmp.h new file mode 100644 index 00000000..3d06644f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/mcux_acmp.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_COMP_MCUX_ACMP_H_ +#define ZEPHYR_INCLUDE_DRIVERS_COMP_MCUX_ACMP_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum comp_mcux_acmp_offset_mode { + COMP_MCUX_ACMP_OFFSET_MODE_LEVEL0 = 0, + COMP_MCUX_ACMP_OFFSET_MODE_LEVEL1, +}; + +enum comp_mcux_acmp_hysteresis_mode { + COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL0 = 0, + COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL1, + COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL2, + COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL3, +}; + +struct comp_mcux_acmp_mode_config { + enum comp_mcux_acmp_offset_mode offset_mode; + enum comp_mcux_acmp_hysteresis_mode hysteresis_mode; + bool enable_high_speed_mode; + bool invert_output; + bool use_unfiltered_output; + bool enable_pin_output; +}; + +enum comp_mcux_acmp_mux_input { + COMP_MCUX_ACMP_MUX_INPUT_IN0 = 0, + COMP_MCUX_ACMP_MUX_INPUT_IN1, + COMP_MCUX_ACMP_MUX_INPUT_IN2, + COMP_MCUX_ACMP_MUX_INPUT_IN3, + COMP_MCUX_ACMP_MUX_INPUT_IN4, + COMP_MCUX_ACMP_MUX_INPUT_IN5, + COMP_MCUX_ACMP_MUX_INPUT_IN6, + COMP_MCUX_ACMP_MUX_INPUT_IN7, +}; + +enum comp_mcux_acmp_port_input { + COMP_MCUX_ACMP_PORT_INPUT_DAC = 0, + COMP_MCUX_ACMP_PORT_INPUT_MUX, +}; + +struct comp_mcux_acmp_input_config { + enum comp_mcux_acmp_mux_input positive_mux_input; + enum comp_mcux_acmp_mux_input negative_mux_input; + enum comp_mcux_acmp_port_input positive_port_input; + enum comp_mcux_acmp_port_input negative_port_input; +}; + +struct comp_mcux_acmp_filter_config { + bool enable_sample; + uint8_t filter_count; + uint8_t filter_period; +}; + +enum comp_mcux_acmp_dac_vref_source { + COMP_MCUX_ACMP_DAC_VREF_SOURCE_VIN1 = 0, + COMP_MCUX_ACMP_DAC_VREF_SOURCE_VIN2, +}; + +struct comp_mcux_acmp_dac_config { + enum comp_mcux_acmp_dac_vref_source vref_source; + uint8_t value; + bool enable_output; + bool enable_high_speed_mode; +}; + +enum comp_mcux_acmp_dm_clock { + COMP_MCUX_ACMP_DM_CLOCK_SLOW = 0, + COMP_MCUX_ACMP_DM_CLOCK_FAST, +}; + +enum comp_mcux_acmp_dm_sample_time { + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T1 = 0, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T2, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T4, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T8, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T16, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T32, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T64, + COMP_MCUX_ACMP_DM_SAMPLE_TIME_T256, +}; + +enum comp_mcux_acmp_dm_phase_time { + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT0 = 0, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT1, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT2, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT3, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT4, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT5, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT6, + COMP_MCUX_ACMP_DM_PHASE_TIME_ALT7, +}; + +struct comp_mcux_acmp_dm_config { + bool enable_positive_channel; + bool enable_negative_channel; + bool enable_resistor_divider; + enum comp_mcux_acmp_dm_clock clock_source; + enum comp_mcux_acmp_dm_sample_time sample_time; + enum comp_mcux_acmp_dm_phase_time phase1_time; + enum comp_mcux_acmp_dm_phase_time phase2_time; +}; + +int comp_mcux_acmp_set_mode_config(const struct device *dev, + const struct comp_mcux_acmp_mode_config *config); + +int comp_mcux_acmp_set_input_config(const struct device *dev, + const struct comp_mcux_acmp_input_config *config); + +int comp_mcux_acmp_set_filter_config(const struct device *dev, + const struct comp_mcux_acmp_filter_config *config); + +int comp_mcux_acmp_set_dac_config(const struct device *dev, + const struct comp_mcux_acmp_dac_config *config); + +int comp_mcux_acmp_set_dm_config(const struct device *dev, + const struct comp_mcux_acmp_dm_config *config); + +int comp_mcux_acmp_set_window_mode(const struct device *dev, bool enable); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_COMP_MCUX_ACMP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/nrf_comp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/nrf_comp.h new file mode 100644 index 00000000..59e1cbbb --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/nrf_comp.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_COMP_NRF_COMP_H_ +#define ZEPHYR_INCLUDE_DRIVERS_COMP_NRF_COMP_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Positive input selection */ +enum comp_nrf_comp_psel { + /** AIN0 external input */ + COMP_NRF_COMP_PSEL_AIN0, + /** AIN1 external input */ + COMP_NRF_COMP_PSEL_AIN1, + /** AIN2 external input */ + COMP_NRF_COMP_PSEL_AIN2, + /** AIN3 external input */ + COMP_NRF_COMP_PSEL_AIN3, + /** AIN4 external input */ + COMP_NRF_COMP_PSEL_AIN4, + /** AIN5 external input */ + COMP_NRF_COMP_PSEL_AIN5, + /** AIN6 external input */ + COMP_NRF_COMP_PSEL_AIN6, + /** AIN7 external input */ + COMP_NRF_COMP_PSEL_AIN7, + /** VDD / 2 */ + COMP_NRF_COMP_PSEL_VDD_DIV2, + /** VDDH / 5 */ + COMP_NRF_COMP_PSEL_VDDH_DIV5, +}; + +/** External reference selection */ +enum comp_nrf_comp_extrefsel { + /** AIN0 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN0, + /** AIN1 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN1, + /** AIN2 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN2, + /** AIN3 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN3, + /** AIN4 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN4, + /** AIN5 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN5, + /** AIN6 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN6, + /** AIN7 external input */ + COMP_NRF_COMP_EXTREFSEL_AIN7, +}; + +/** Reference selection */ +enum comp_nrf_comp_refsel { + /** Internal 1.2V reference */ + COMP_NRF_COMP_REFSEL_INT_1V2, + /** Internal 1.8V reference */ + COMP_NRF_COMP_REFSEL_INT_1V8, + /** Internal 2.4V reference */ + COMP_NRF_COMP_REFSEL_INT_2V4, + /** AVDD 1.8V reference */ + COMP_NRF_COMP_REFSEL_AVDDAO1V8, + /** VDD reference */ + COMP_NRF_COMP_REFSEL_VDD, + /** Use external analog reference */ + COMP_NRF_COMP_REFSEL_AREF, +}; + +/** Speed mode selection */ +enum comp_nrf_comp_sp_mode { + /** Low-power mode */ + COMP_NRF_COMP_SP_MODE_LOW, + /** Normal mode */ + COMP_NRF_COMP_SP_MODE_NORMAL, + /** High-speed mode */ + COMP_NRF_COMP_SP_MODE_HIGH, +}; + +/** Current source configuration */ +enum comp_nrf_comp_isource { + /** Current source disabled */ + COMP_NRF_COMP_ISOURCE_DISABLED, + /** 2.5uA current source enabled */ + COMP_NRF_COMP_ISOURCE_2UA5, + /** 5uA current source enabled */ + COMP_NRF_COMP_ISOURCE_5UA, + /** 10uA current source enabled */ + COMP_NRF_COMP_ISOURCE_10UA, +}; + +/** + * @brief Single-ended mode configuration structure + * + * @note extrefsel is only used if refsel == COMP_NRF_COMP_REFSEL_AREF + * @note Hysteresis down in volts = ((th_down + 1) / 64) * ref + * @note Hysteresis up in volts = ((th_up + 1) / 64) * ref + */ +struct comp_nrf_comp_se_config { + /** Positive input selection */ + enum comp_nrf_comp_psel psel; + /** Speed mode selection */ + enum comp_nrf_comp_sp_mode sp_mode; + /** Current source configuration */ + enum comp_nrf_comp_isource isource; + /** External reference selection */ + enum comp_nrf_comp_extrefsel extrefsel; + /** Reference selection */ + enum comp_nrf_comp_refsel refsel; + /** Hysteresis down threshold configuration */ + uint8_t th_down; + /** Hysteresis up threshold configuration */ + uint8_t th_up; +}; + +/** + * @brief Configure comparator in single-ended mode + * + * @param dev Comparator device instance + * @param config Single-ended mode configuration + * + * @retval 0 if successful + * @retval negative errno-code otherwise + */ +int comp_nrf_comp_configure_se(const struct device *dev, + const struct comp_nrf_comp_se_config *config); + +/** Differential mode configuration structure */ +struct comp_nrf_comp_diff_config { + /** Positive input selection */ + enum comp_nrf_comp_psel psel; + /** Speed mode selection */ + enum comp_nrf_comp_sp_mode sp_mode; + /** Current source configuration */ + enum comp_nrf_comp_isource isource; + /** Negative input selection */ + enum comp_nrf_comp_extrefsel extrefsel; + /** Hysteresis configuration */ + bool enable_hyst; +}; + +/** + * @brief Configure comparator in differential mode + * + * @param dev Comparator device instance + * @param config Differential mode configuration + * + * @retval 0 if successful + * @retval negative errno-code otherwise + */ +int comp_nrf_comp_configure_diff(const struct device *dev, + const struct comp_nrf_comp_diff_config *config); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_COMP_NRF_COMP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/nrf_lpcomp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/nrf_lpcomp.h new file mode 100644 index 00000000..e1f2343a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/comparator/nrf_lpcomp.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_COMP_NRF_LPCOMP_H_ +#define ZEPHYR_INCLUDE_DRIVERS_COMP_NRF_LPCOMP_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Positive input selection */ +enum comp_nrf_lpcomp_psel { + /** AIN0 external input */ + COMP_NRF_LPCOMP_PSEL_AIN0, + /** AIN1 external input */ + COMP_NRF_LPCOMP_PSEL_AIN1, + /** AIN2 external input */ + COMP_NRF_LPCOMP_PSEL_AIN2, + /** AIN3 external input */ + COMP_NRF_LPCOMP_PSEL_AIN3, + /** AIN4 external input */ + COMP_NRF_LPCOMP_PSEL_AIN4, + /** AIN5 external input */ + COMP_NRF_LPCOMP_PSEL_AIN5, + /** AIN6 external input */ + COMP_NRF_LPCOMP_PSEL_AIN6, + /** AIN7 external input */ + COMP_NRF_LPCOMP_PSEL_AIN7, +}; + +/** External reference selection */ +enum comp_nrf_lpcomp_extrefsel { + /** AIN0 external input */ + COMP_NRF_LPCOMP_EXTREFSEL_AIN0, + /** AIN1 external input */ + COMP_NRF_LPCOMP_EXTREFSEL_AIN1, +}; + +/** Reference selection */ +enum comp_nrf_lpcomp_refsel { + /** Use (VDD * (1/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_1_8, + /** Use (VDD * (2/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_2_8, + /** Use (VDD * (3/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_3_8, + /** Use (VDD * (4/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_4_8, + /** Use (VDD * (5/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_5_8, + /** Use (VDD * (6/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_6_8, + /** Use (VDD * (7/8)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_7_8, + /** Use (VDD * (1/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_1_16, + /** Use (VDD * (3/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_3_16, + /** Use (VDD * (5/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_5_16, + /** Use (VDD * (7/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_7_16, + /** Use (VDD * (9/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_9_16, + /** Use (VDD * (11/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_11_16, + /** Use (VDD * (13/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_13_16, + /** Use (VDD * (15/16)) as reference */ + COMP_NRF_LPCOMP_REFSEL_VDD_15_16, + /** Use external analog reference */ + COMP_NRF_LPCOMP_REFSEL_AREF, +}; + +/** + * @brief Configuration structure + * + * @note extrefsel is only used if refsel == COMP_NRF_LPCOMP_REFSEL_AREF + */ +struct comp_nrf_lpcomp_config { + /** Positive input selection */ + enum comp_nrf_lpcomp_psel psel; + /** External reference selection */ + enum comp_nrf_lpcomp_extrefsel extrefsel; + /** Reference selection */ + enum comp_nrf_lpcomp_refsel refsel; + /** Hysteresis configuration */ + bool enable_hyst; +}; + +/** + * @brief Configure comparator + * + * @param dev Comparator device instance + * @param config Configuration + * + * @retval 0 if successful + * @retval negative errno-code otherwise + */ +int comp_nrf_lpcomp_configure(const struct device *dev, + const struct comp_nrf_lpcomp_config *config); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_COMP_NRF_LPCOMP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dac.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dac.h index 8e384320..fea4e329 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dac.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dac.h @@ -27,6 +27,12 @@ extern "C" { * @{ */ +/** + * @brief Broadcast channel identifier for DACs that support it. + * @note Only for use in dac_write_value(). + */ +#define DAC_CHANNEL_BROADCAST 0xFF + /** * @brief Structure for specifying the configuration of a DAC channel. */ @@ -39,7 +45,12 @@ struct dac_channel_cfg { * This is relevant for instance if the output is directly connected to the load, * without an amplifierin between. The actual details on this are hardware dependent. */ - bool buffered; + bool buffered: 1; + /** Enable internal output path for this channel. This is relevant for channels that + * support directly connecting to on-chip peripherals via internal paths. The actual + * details on this are hardware dependent. + */ + bool internal: 1; }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dai.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dai.h index 3e6dbfa4..7af4157d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dai.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dai.h @@ -330,6 +330,8 @@ __subsystem struct dai_driver_api { int (*ts_stop)(const struct device *dev, struct dai_ts_cfg *cfg); int (*ts_get)(const struct device *dev, struct dai_ts_cfg *cfg, struct dai_ts_data *tsd); + int (*config_update)(const struct device *dev, const void *bespoke_cfg, + size_t size); }; /** @@ -475,8 +477,9 @@ static inline int dai_ts_config(const struct device *dev, struct dai_ts_cfg *cfg { const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api; - if (!api->ts_config) + if (!api->ts_config) { return -EINVAL; + } return api->ts_config(dev, cfg); } @@ -494,8 +497,9 @@ static inline int dai_ts_start(const struct device *dev, struct dai_ts_cfg *cfg) { const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api; - if (!api->ts_start) + if (!api->ts_start) { return -EINVAL; + } return api->ts_start(dev, cfg); } @@ -513,8 +517,9 @@ static inline int dai_ts_stop(const struct device *dev, struct dai_ts_cfg *cfg) { const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api; - if (!api->ts_stop) + if (!api->ts_stop) { return -EINVAL; + } return api->ts_stop(dev, cfg); } @@ -534,12 +539,45 @@ static inline int dai_ts_get(const struct device *dev, struct dai_ts_cfg *cfg, { const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api; - if (!api->ts_get) + if (!api->ts_get) { return -EINVAL; + } return api->ts_get(dev, cfg, tsd); } +/** + * @brief Update DAI configuration at runtime. + * + * This function updates the configuration of a DAI interface at runtime. + * It allows setting bespoke configuration parameters that are specific to + * the DAI implementation, enabling updates outside of the regular flow with + * the full configuration blob. The details of the bespoke configuration are + * specific to each DAI implementation. This function should only be called + * when the DAI is in the READY state, ensuring that the configuration updates + * are applied before data transmission or reception begins. + * + * @param dev Pointer to the device structure for the driver instance. + * @param bespoke_cfg Pointer to the buffer containing bespoke configuration parameters. + * @param size Size of the bespoke_cfg buffer in bytes. + * + * @retval 0 If successful. + * @retval -ENOSYS If the configuration update operation is not implemented. + * @retval Negative errno code if failure. + */ +static inline int dai_config_update(const struct device *dev, + const void *bespoke_cfg, + size_t size) +{ + const struct dai_driver_api *api = (const struct dai_driver_api *)dev->api; + + if (!api->config_update) { + return -ENOSYS; + } + + return api->config_update(dev, bespoke_cfg, size); +} + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/display.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/display.h index 067d441d..8fd26978 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/display.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/display.h @@ -127,6 +127,8 @@ struct display_buffer_descriptor { uint16_t height; /** Number of pixels between consecutive rows in the data buffer */ uint16_t pitch; + /** Indicates that this is not the last write buffer of the frame */ + bool frame_incomplete; }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma.h index b7853ed8..5237f78b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma.h @@ -352,6 +352,20 @@ typedef int (*dma_api_get_attribute)(const struct device *dev, uint32_t type, ui typedef bool (*dma_api_chan_filter)(const struct device *dev, int channel, void *filter_param); +/** + * @typedef dma_chan_release + * @brief channel release function call + * + * used to release channel resources "allocated" during the + * request phase. These resources can refer to enabled PDs, IRQs + * etc... + * + * @param dev Pointer to the DMA device instance + * @param channel channel id to use + */ +typedef void (*dma_api_chan_release)(const struct device *dev, + uint32_t channel); + __subsystem struct dma_driver_api { dma_api_config config; dma_api_reload reload; @@ -362,6 +376,7 @@ __subsystem struct dma_driver_api { dma_api_get_status get_status; dma_api_get_attribute get_attribute; dma_api_chan_filter chan_filter; + dma_api_chan_release chan_release; }; /** * @endcond @@ -538,7 +553,9 @@ static inline int z_impl_dma_resume(const struct device *dev, uint32_t channel) * request DMA channel resources * return -EINVAL if there is no valid channel available. * - * @funcprops \isr_ok + * @note It is safe to use this function in contexts where blocking + * is not allowed, e.g. ISR, provided the implementation of the filter + * function does not block. * * @param dev Pointer to the device structure for the driver instance. * @param filter_param filter function parameter @@ -583,7 +600,9 @@ static inline int z_impl_dma_request_channel(const struct device *dev, * * release DMA channel resources * - * @funcprops \isr_ok + * @note It is safe to use this function in contexts where blocking + * is not allowed, e.g. ISR, provided the implementation of the release + * function does not block. * * @param dev Pointer to the device structure for the driver instance. * @param channel channel number @@ -595,6 +614,8 @@ __syscall void dma_release_channel(const struct device *dev, static inline void z_impl_dma_release_channel(const struct device *dev, uint32_t channel) { + const struct dma_driver_api *api = + (const struct dma_driver_api *)dev->api; struct dma_context *dma_ctx = (struct dma_context *)dev->data; if (dma_ctx->magic != DMA_MAGIC) { @@ -602,6 +623,10 @@ static inline void z_impl_dma_release_channel(const struct device *dev, } if ((int)channel < dma_ctx->dma_channels) { + if (api->chan_release) { + api->chan_release(dev, channel); + } + atomic_clear_bit(dma_ctx->atomic, channel); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_pxp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_pxp.h index 7cddab2c..47082a94 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_pxp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_pxp.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -38,4 +38,20 @@ #define DMA_MCUX_PXP_FMT_RGB888 1 #define DMA_MCUX_PXP_FMT_ARGB8888 2 +#define DMA_MCUX_PXP_FLIP_MASK 0x3 +#define DMA_MCUX_PXP_FLIP_SHIFT 0x0 + +/* + * In order to configure the PXP to flip, the user should + * supply a flip setting as the DMA linked_channel parameter, like so: + * linked_channel |= DMA_MCUX_PXP_FLIP(DMA_MCUX_PXP_FLIP_HORIZONTAL) + */ + +#define DMA_MCUX_PXP_FLIP(x) ((x << DMA_MCUX_PXP_FLIP_SHIFT) & DMA_MCUX_PXP_FLIP_MASK) + +#define DMA_MCUX_PXP_FLIP_DISABLE 0 +#define DMA_MCUX_PXP_FLIP_HORIZONTAL 1 +#define DMA_MCUX_PXP_FLIP_VERTICAL 2 +#define DMA_MCUX_PXP_FLIP_BOTH 3 + #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_PXP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_smartdma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_smartdma.h index 0e09d348..5171a549 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_smartdma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_mcux_smartdma.h @@ -7,34 +7,6 @@ #ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_SMARTDMA_H_ #define ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_SMARTDMA_H_ -/* Write RGB565 data to MIPI DSI via DMA. */ -#define DMA_SMARTDMA_MIPI_RGB565_DMA 0 -/* Write RGB888 data to MIPI DSI via DMA */ -#define DMA_SMARTDMA_MIPI_RGB888_DMA 1 -/* Write RGB565 data to MIPI DSI via DMA. Rotate output data by 180 degrees */ -#define DMA_SMARTDMA_MIPI_RGB565_180 2 -/* Write RGB888 data to MIPI DSI via DMA. Rotate output data by 180 degrees */ -#define DMA_SMARTDMA_MIPI_RGB888_180 3 - -/* Write RGB565 data to MIPI DSI via DMA. Swap data endianness, so that - * little endian RGB565 data will be written big endian style. - */ -#define DMA_SMARTDMA_MIPI_RGB565_DMA_SWAP 4 -/* Write RGB888 data to MIPI DSI via DMA. Swap data endianness, so that - * little endian RGB888 data will be written big endian style. - */ -#define DMA_SMARTDMA_MIPI_RGB888_DMA_SWAP 5 -/* Write RGB565 data to MIPI DSI via DMA. Rotate output data by 180 degrees, - * and swap data endianness - */ -#define DMA_SMARTDMA_MIPI_RGB565_180_SWAP 6 -/* Write RGB888 data to MIPI DSI via DMA. Rotate output data by 180 degrees, - * and swap data endianness - */ -#define DMA_SMARTDMA_MIPI_RGB888_180_SWAP 7 - - - /** * @brief install SMARTDMA firmware * @@ -48,6 +20,4 @@ void dma_smartdma_install_fw(const struct device *dev, uint8_t *firmware, uint32_t len); -#define GD32_DMA_FEATURES_FIFO_THRESHOLD(threshold) (threshold & 0x3) - #endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_MCUX_SMARTDMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_smartbond.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_smartbond.h index c1544880..fba98aae 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_smartbond.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/dma/dma_smartbond.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef DMA_SMARTBOND_H_ -#define DMA_SMARTBOND_H_ +#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_SMARTBOND_H_ +#define ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_SMARTBOND_H_ /** * @brief Vendror-specific DMA peripheral triggering sources. @@ -30,4 +30,4 @@ enum dma_smartbond_trig_mux { DMA_SMARTBOND_TRIG_MUX_NONE = 0xF }; -#endif /* DMA_SMARTBOND_H_ */ +#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_DMA_SMARTBOND_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/emul.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/emul.h index a41b48b8..a2067957 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/emul.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/emul.h @@ -28,6 +28,7 @@ struct emul; #include #include #include +#include #include /** @@ -38,6 +39,7 @@ enum emul_bus_type { EMUL_BUS_TYPE_ESPI, EMUL_BUS_TYPE_SPI, EMUL_BUS_TYPE_MSPI, + EMUL_BUS_TYPE_UART, EMUL_BUS_TYPE_NONE, }; @@ -94,6 +96,7 @@ struct emul { struct espi_emul *espi; struct spi_emul *spi; struct mspi_emul *mspi; + struct uart_emul *uart; struct no_bus_emul *none; } bus; /** Address of the API structure exposed by the emulator instance */ @@ -111,15 +114,17 @@ struct emul { * the bus its on. Intended for use in other internal macros when declaring {bus}_emul * structs in peripheral emulators. */ -#define Z_EMUL_REG_BUS_IDENTIFIER(_dev_node_id) (_CONCAT(_CONCAT(__emulreg_, _dev_node_id), _bus)) +#define Z_EMUL_REG_BUS_IDENTIFIER(_dev_node_id) _CONCAT(_CONCAT(__emulreg_, _dev_node_id), _bus) /* Conditionally places text based on what bus _dev_node_id is on. */ -#define Z_EMUL_BUS(_dev_node_id, _i2c, _espi, _spi, _mspi, _none) \ +#define Z_EMUL_BUS(_dev_node_id, _i2c, _espi, _spi, _mspi, _uart, _none) \ COND_CODE_1(DT_ON_BUS(_dev_node_id, i2c), (_i2c), \ - (COND_CODE_1(DT_ON_BUS(_dev_node_id, espi), (_espi), \ - (COND_CODE_1(DT_ON_BUS(_dev_node_id, spi), (_spi), \ - (COND_CODE_1(DT_ON_BUS(_dev_node_id, mspi), (_mspi), \ - (_none)))))))) + (COND_CODE_1(DT_ON_BUS(_dev_node_id, espi), (_espi), \ + (COND_CODE_1(DT_ON_BUS(_dev_node_id, spi), (_spi), \ + (COND_CODE_1(DT_ON_BUS(_dev_node_id, mspi), (_mspi), \ + (COND_CODE_1(DT_ON_BUS(_dev_node_id, uart), (_uart), \ + (_none)))))))))) + /** * @brief Define a new emulator * @@ -135,20 +140,21 @@ struct emul { * @param _backend_api emulator-specific backend api */ #define EMUL_DT_DEFINE(node_id, init_fn, data_ptr, cfg_ptr, bus_api, _backend_api) \ - static struct Z_EMUL_BUS(node_id, i2c_emul, espi_emul, spi_emul, mspi_emul, no_bus_emul) \ - Z_EMUL_REG_BUS_IDENTIFIER(node_id) = { \ - .api = bus_api, \ - .Z_EMUL_BUS(node_id, addr, chipsel, chipsel, dev_idx, addr) = \ - DT_REG_ADDR(node_id), \ - }; \ + static struct Z_EMUL_BUS(node_id, i2c_emul, espi_emul, spi_emul, mspi_emul, uart_emul, \ + no_bus_emul) Z_EMUL_REG_BUS_IDENTIFIER(node_id) = { \ + .api = bus_api, \ + IF_ENABLED(DT_NODE_HAS_PROP(node_id, reg), \ + (.Z_EMUL_BUS(node_id, addr, chipsel, chipsel, dev_idx, dummy, addr) = \ + DT_REG_ADDR(node_id),))}; \ const STRUCT_SECTION_ITERABLE(emul, EMUL_DT_NAME_GET(node_id)) __used = { \ .init = (init_fn), \ .dev = DEVICE_DT_GET(node_id), \ .cfg = (cfg_ptr), \ .data = (data_ptr), \ .bus_type = Z_EMUL_BUS(node_id, EMUL_BUS_TYPE_I2C, EMUL_BUS_TYPE_ESPI, \ - EMUL_BUS_TYPE_SPI, EMUL_BUS_TYPE_MSPI, EMUL_BUS_TYPE_NONE), \ - .bus = {.Z_EMUL_BUS(node_id, i2c, espi, spi, mspi, none) = \ + EMUL_BUS_TYPE_SPI, EMUL_BUS_TYPE_MSPI, EMUL_BUS_TYPE_UART, \ + EMUL_BUS_TYPE_NONE), \ + .bus = {.Z_EMUL_BUS(node_id, i2c, espi, spi, mspi, uart, none) = \ &(Z_EMUL_REG_BUS_IDENTIFIER(node_id))}, \ .backend_api = (_backend_api), \ }; @@ -189,7 +195,7 @@ struct emul { * @return a @ref emul reference for the node identifier, which may be `NULL`. */ #define EMUL_DT_GET_OR_NULL(node_id) \ - COND_CODE_1(DT_NODE_HAS_STATUS(node_id, okay), (EMUL_DT_GET(node_id)), (NULL)) + COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(node_id), (EMUL_DT_GET(node_id)), (NULL)) /** * @brief Set up a list of emulators diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h index 1ec5adaf..0d85c073 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/ethernet/eth_nxp_enet_qos.h @@ -11,7 +11,7 @@ #include /* Different platforms named the peripheral different in the register definitions */ -#ifdef CONFIG_SOC_FAMILY_NXP_MCX +#ifdef CONFIG_SOC_SERIES_MCXN #undef ENET #define ENET_QOS_NAME ENET #define ENET_QOS_ALIGNMENT 4 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/clk.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/clk.h new file mode 100644 index 00000000..e56fc9df --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/clk.h @@ -0,0 +1,96 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief SCMI clock protocol helpers + */ + +#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_ +#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_ + +#include + +#define SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK GENMASK(1, 0) +#define SCMI_CLK_CONFIG_ENABLE_DISABLE(x)\ + ((uint32_t)(x) & SCMI_CLK_CONFIG_DISABLE_ENABLE_MASK) + +#define SCMI_CLK_ATTRIBUTES_CLK_NUM(x) ((x) & GENMASK(15, 0)) + +/** + * @struct scmi_clock_config + * + * @brief Describes the parameters for the CLOCK_CONFIG_SET + * command + */ +struct scmi_clock_config { + uint32_t clk_id; + uint32_t attributes; + uint32_t extended_cfg_val; +}; + +/** + * @brief Clock protocol command message IDs + */ +enum scmi_clock_message { + SCMI_CLK_MSG_PROTOCOL_VERSION = 0x0, + SCMI_CLK_MSG_PROTOCOL_ATTRIBUTES = 0x1, + SCMI_CLK_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2, + SCMI_CLK_MSG_CLOCK_ATTRIBUTES = 0x3, + SCMI_CLK_MSG_CLOCK_DESCRIBE_RATES = 0x4, + SCMI_CLK_MSG_CLOCK_RATE_SET = 0x5, + SCMI_CLK_MSG_CLOCK_RATE_GET = 0x6, + SCMI_CLK_MSG_CLOCK_CONFIG_SET = 0x7, + SCMI_CLK_MSG_CLOCK_NAME_GET = 0x8, + SCMI_CLK_MSG_CLOCK_RATE_NOTIFY = 0x9, + SCMI_CLK_MSG_CLOCK_RATE_CHANGE_REQUESTED_NOTIFY = 0xa, + SCMI_CLK_MSG_CLOCK_CONFIG_GET = 0xb, + SCMI_CLK_MSG_CLOCK_POSSIBLE_PARENTS_GET = 0xc, + SCMI_CLK_MSG_CLOCK_PARENT_SET = 0xd, + SCMI_CLK_MSG_CLOCK_PARENT_GET = 0xe, + SCMI_CLK_MSG_CLOCK_GET_PERMISSIONS = 0xf, + SCMI_CLK_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10, +}; + +/** + * @brief Send the PROTOCOL_ATTRIBUTES command and get its reply + * + * @param proto pointer to SCMI clock protocol data + * @param attributes pointer to attributes to be set via + * this command + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_clock_protocol_attributes(struct scmi_protocol *proto, + uint32_t *attributes); + +/** + * @brief Send the CLOCK_CONFIG_SET command and get its reply + * + * @param proto pointer to SCMI clock protocol data + * @param cfg pointer to structure containing configuration + * to be set + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_clock_config_set(struct scmi_protocol *proto, + struct scmi_clock_config *cfg); +/** + * @brief Query the rate of a clock + * + * @param proto pointer to SCMI clock protocol data + * @param clk_id ID of the clock for which the query is done + * @param rate pointer to rate to be set via this command + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_clock_rate_get(struct scmi_protocol *proto, + uint32_t clk_id, uint32_t *rate); + +#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/pinctrl.h new file mode 100644 index 00000000..3906b91d --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/pinctrl.h @@ -0,0 +1,103 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief SCMI pinctrl protocol helpers + */ + +#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_ +#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_ + +#include + +#define ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE (10 * 2) + +#define SCMI_PINCTRL_NO_FUNCTION 0xFFFFFFFF + +#define SCMI_PINCTRL_CONFIG_ATTRIBUTES(fid_valid, cfg_num, selector) \ + (SCMI_FIELD_MAKE(fid_valid, BIT(1), 10) | \ + SCMI_FIELD_MAKE(cfg_num, GENMASK(7, 0), 2) | \ + SCMI_FIELD_MAKE(selector, GENMASK(1, 0), 0)) + +#define SCMI_PINCTRL_SELECTOR_PIN 0x0 +#define SCMI_PINCTRL_SELECTOR_GROUP 0x1 + +#define SCMI_PINCTRL_ATTRIBUTES_CONFIG_NUM(attributes)\ + (((attributes) & GENMASK(9, 2)) >> 2) + +/** + * @brief Pinctrl protocol command message IDs + */ +enum scmi_pinctrl_message { + SCMI_PINCTRL_MSG_PROTOCOL_VERSION = 0x0, + SCMI_PINCTRL_MSG_PROTOCOL_ATTRIBUTES = 0x1, + SCMI_PINCTRL_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2, + SCMI_PINCTRL_MSG_PINCTRL_ATTRIBUTES = 0x3, + SCMI_PINCTRL_MSG_PINCTRL_LIST_ASSOCIATIONS = 0x4, + SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_GET = 0x5, + SCMI_PINCTRL_MSG_PINCTRL_SETTINGS_CONFIGURE = 0x6, + SCMI_PINCTRL_MSG_PINCTRL_REQUEST = 0x7, + SCMI_PINCTRL_MSG_PINCTRL_RELEASE = 0x8, + SCMI_PINCTRL_MSG_PINCTRL_NAME_GET = 0x9, + SCMI_PINCTRL_MSG_PINCTRL_SET_PERMISSIONS = 0xa, + SCMI_PINCTRL_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10, +}; + +/** + * @brief Pinctrl configurations + */ +enum scmi_pinctrl_config { + SCMI_PINCTRL_DEFAULT = 0, + SCMI_PINCTRL_BIAS_BUS_HOLD = 1, + SCMI_PINCTRL_BIAS_DISABLE = 2, + SCMI_PINCTRL_BIAS_HIGH_Z = 3, + SCMI_PINCTRL_BIAS_PULL_UP = 4, + SCMI_PINCTRL_BIAS_PULL_DEFAULT = 5, + SCMI_PINCTRL_BIAS_PULL_DOWN = 6, + SCMI_PINCTRL_DRIVE_OPEN_DRAIN = 7, + SCMI_PINCTRL_DRIVE_OPEN_SOURCE = 8, + SCMI_PCINTRL_DRIVE_PUSH_PULL = 9, + SCMI_PCINTRL_DRIVE_STRENGTH = 10, + SCMI_PINCTRL_INPUT_DEBOUNCE = 11, + SCMI_PINCTRL_INPUT_MODE = 12, + SCMI_PINCTRL_PULL_MODE = 13, + SCMI_PINCTRL_INPUT_VALUE = 14, + SCMI_PINCTRL_INPUT_SCHMITT = 15, + SCMI_PINCTRL_LP_MODE = 16, + SCMI_PINCTRL_OUTPUT_MODE = 17, + SCMI_PINCTRL_OUTPUT_VALUE = 18, + SCMI_PINCTRL_POWER_SOURCE = 19, + SCMI_PINCTRL_SLEW_RATE = 20, + SCMI_PINCTRL_RESERVED_START = 21, + SCMI_PINCTRL_RESERVED_END = 191, + SCMI_PINCTRL_VENDOR_START = 192, +}; + +/** + * @struct scmi_pinctrl_settings + * + * @brief Describes the parameters for the PINCTRL_SETTINGS_CONFIGURE + * command + */ +struct scmi_pinctrl_settings { + uint32_t id; + uint32_t function; + uint32_t attributes; + uint32_t config[ARM_SCMI_PINCTRL_MAX_CONFIG_SIZE]; +}; + +/** + * @brief Send the PINCTRL_SETTINGS_CONFIGURE command and get its reply + * + * @param settings pointer to settings to be applied + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_pinctrl_settings_configure(struct scmi_pinctrl_settings *settings); + +#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/protocol.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/protocol.h new file mode 100644 index 00000000..13ac8ba2 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/protocol.h @@ -0,0 +1,122 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief SCMI protocol generic functions and structures + */ + +#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_ +#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_ + +#include +#include +#include +#include + +/** + * @brief Build an SCMI message header + * + * Builds an SCMI message header based on the + * fields that make it up. + * + * @param id message ID + * @param type message type + * @param proto protocol ID + * @param token message token + */ +#define SCMI_MESSAGE_HDR_MAKE(id, type, proto, token) \ + (SCMI_FIELD_MAKE(id, GENMASK(7, 0), 0) | \ + SCMI_FIELD_MAKE(type, GENMASK(1, 0), 8) | \ + SCMI_FIELD_MAKE(proto, GENMASK(7, 0), 10) | \ + SCMI_FIELD_MAKE(token, GENMASK(9, 0), 18)) + +struct scmi_channel; + +/** + * @brief SCMI message type + */ +enum scmi_message_type { + /** command message */ + SCMI_COMMAND = 0x0, + /** delayed reply message */ + SCMI_DELAYED_REPLY = 0x2, + /** notification message */ + SCMI_NOTIFICATION = 0x3, +}; + +/** + * @brief SCMI status codes + */ +enum scmi_status_code { + SCMI_SUCCESS = 0, + SCMI_NOT_SUPPORTED = -1, + SCMI_INVALID_PARAMETERS = -2, + SCMI_DENIED = -3, + SCMI_NOT_FOUND = -4, + SCMI_OUT_OF_RANGE = -5, + SCMI_BUSY = -6, + SCMI_COMMS_ERROR = -7, + SCMI_GENERIC_ERROR = -8, + SCMI_HARDWARE_ERROR = -9, + SCMI_PROTOCOL_ERROR = -10, + SCMI_IN_USE = -11, +}; + +/** + * @struct scmi_protocol + * + * @brief SCMI protocol structure + */ +struct scmi_protocol { + /** protocol ID */ + uint32_t id; + /** TX channel */ + struct scmi_channel *tx; + /** transport layer device */ + const struct device *transport; + /** protocol private data */ + void *data; +}; + +/** + * @struct scmi_message + * + * @brief SCMI message structure + */ +struct scmi_message { + uint32_t hdr; + uint32_t len; + void *content; +}; + +/** + * @brief Convert an SCMI status code to its Linux equivalent (if possible) + * + * @param scmi_status SCMI status code as shown in `enum scmi_status_code` + * + * @retval Linux equivalent status code + */ +int scmi_status_to_errno(int scmi_status); + +/** + * @brief Send an SCMI message and wait for its reply + * + * Blocking function used to send an SCMI message over + * a given channel and wait for its reply + * + * @param proto pointer to SCMI protocol + * @param msg pointer to SCMI message to send + * @param reply pointer to SCMI message in which the reply is to be + * written + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_send_message(struct scmi_protocol *proto, + struct scmi_message *msg, struct scmi_message *reply); + +#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_PROTOCOL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/shmem.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/shmem.h new file mode 100644 index 00000000..a655a361 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/shmem.h @@ -0,0 +1,67 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief SCMI SHMEM API + */ + +#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_ +#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_ + +#include +#include +#include + +#define SCMI_SHMEM_CHAN_STATUS_BUSY_BIT BIT(0) +#define SCMI_SHMEM_CHAN_FLAG_IRQ_BIT BIT(0) + +struct scmi_message; + +/** + * @brief Write a message in the SHMEM area + * + * @param shmem pointer to shmem device + * @param msg message to write + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_shmem_write_message(const struct device *shmem, + struct scmi_message *msg); + +/** + * @brief Read a message from a SHMEM area + * + * @param shmem pointer to shmem device + * @param msg message to write the data into + * + * @retval 0 if successful + * @retval negative errno if failure + */ +int scmi_shmem_read_message(const struct device *shmem, + struct scmi_message *msg); + +/** + * @brief Update the channel flags + * + * @param shmem pointer to shmem device + * @param mask value to negate and bitwise-and the old + * channel flags value + * @param val value to bitwise and with the mask and + * bitwise-or with the masked old value + */ +void scmi_shmem_update_flags(const struct device *shmem, + uint32_t mask, uint32_t val); + +/** + * @brief Read a channel's status + * + * @param shmem pointer to shmem device + */ +uint32_t scmi_shmem_channel_status(const struct device *shmem); + +#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/transport.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/transport.h new file mode 100644 index 00000000..2cb72a2b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/transport.h @@ -0,0 +1,274 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Public APIs for the SCMI transport layer drivers + */ + +#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_ +#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_ + +#include +#include + +struct scmi_message; +struct scmi_channel; + +/** + * @typedef scmi_channel_cb + * + * @brief Callback function for message replies + * + * This function should be called by the transport layer + * driver whenever a reply to a previously sent message + * has been received. Its purpose is to notifying the SCMI + * core of the reply's arrival so that proper action can + * be taken. + * + * @param chan pointer to SCMI channel on which the reply + * arrived + */ +typedef void (*scmi_channel_cb)(struct scmi_channel *chan); + +/** + * @struct scmi_channel + * @brief SCMI channel structure + * + * An SCMI channel is a medium through which a protocol + * is able to transmit/receive messages. Each of the SCMI + * channels is represented by a `struct scmi_channel`. + */ +struct scmi_channel { + /** + * channel lock. This is meant to be initialized + * and used only by the SCMI core to assure that + * only one protocol can send/receive messages + * through a channel at a given moment. + */ + struct k_mutex lock; + /** + * binary semaphore. This is meant to be initialized + * and used only by the SCMI core. Its purpose is to + * signal that a reply has been received. + */ + struct k_sem sem; + /** channel private data */ + void *data; + /** + * callback function. This is meant to be set by + * the SCMI core and should be called by the SCMI + * transport layer driver whenever a reply has + * been received. + */ + scmi_channel_cb cb; + /** is the channel ready to be used by a protocol? */ + bool ready; +}; + +struct scmi_transport_api { + int (*init)(const struct device *transport); + int (*send_message)(const struct device *transport, + struct scmi_channel *chan, + struct scmi_message *msg); + int (*setup_chan)(const struct device *transport, + struct scmi_channel *chan, + bool tx); + int (*read_message)(const struct device *transport, + struct scmi_channel *chan, + struct scmi_message *msg); + bool (*channel_is_free)(const struct device *transport, + struct scmi_channel *chan); + struct scmi_channel *(*request_channel)(const struct device *transport, + uint32_t proto, bool tx); +}; + +/** + * @brief Request an SCMI channel dynamically + * + * Whenever the SCMI transport layer driver doesn't support + * static channel allocation, the SCMI core will try to bind + * a channel to a protocol dynamically using this function. + * Note that no setup needs to be performed on the channel + * in this function as the core will also call the channel + * setup() function. + * + * @param transport pointer to the device structure for the + * transport layer + * @param proto ID of the protocol for which the core is + * requesting the channel + * @param tx true if the channel is TX, false if RX + * + * @retval pointer to SCMI channel that's to be bound + * to the protocol + * @retval NULL if operation was not successful + */ +static inline struct scmi_channel * +scmi_transport_request_channel(const struct device *transport, + uint32_t proto, bool tx) +{ + const struct scmi_transport_api *api = + (const struct scmi_transport_api *)transport->api; + + if (api->request_channel) { + return api->request_channel(transport, proto, tx); + } + + return NULL; +} + +/** + * @brief Perform initialization for the transport layer driver + * + * The transport layer driver can't be initialized directly + * (i.e via a call to its init() function) during system initialization. + * This is because the macro used to define an SCMI transport places + * `scmi_core_transport_init()` in the init section instead of the + * driver's init() function. As such, `scmi_core_transport_init()` + * needs to call this function to perfrom transport layer driver + * initialization if required. + * + * This operation is optional. + * + * @param transport pointer to the device structure for the + * transport layer + * + * @retval 0 if successful + * @retval negative errno code if failure + */ +static inline int scmi_transport_init(const struct device *transport) +{ + const struct scmi_transport_api *api = + (const struct scmi_transport_api *)transport->api; + + if (api->init) { + return api->init(transport); + } + + return 0; +} + +/** + * @brief Setup an SCMI channel + * + * Before being able to send/receive messages, an SCMI channel needs + * to be prepared, which is what this function does. If it returns + * successfully, an SCMI protocol will be able to use this channel + * to send/receive messages. + * + * @param transport pointer to the device structure for the + * transport layer + * @param chan pointer to SCMI channel to be prepared + * @param tx true if the channel is TX, false if RX + * + * @retval 0 if successful + * @retval negative errno code if failure + */ +static inline int scmi_transport_setup_chan(const struct device *transport, + struct scmi_channel *chan, + bool tx) +{ + const struct scmi_transport_api *api = + (const struct scmi_transport_api *)transport->api; + + if (!api || !api->setup_chan) { + return -ENOSYS; + } + + return api->setup_chan(transport, chan, tx); +} + +/** + * @brief Send an SCMI channel + * + * Send an SCMI message using given SCMI channel. This function is + * not allowed to block. + * + * @param transport pointer to the device structure for the + * transport layer + * @param chan pointer to SCMI channel on which the message + * is to be sent + * @param msg pointer to message the caller wishes to send + * + * @retval 0 if successful + * @retval negative errno code if failure + */ +static inline int scmi_transport_send_message(const struct device *transport, + struct scmi_channel *chan, + struct scmi_message *msg) +{ + const struct scmi_transport_api *api = + (const struct scmi_transport_api *)transport->api; + + if (!api || !api->send_message) { + return -ENOSYS; + } + + return api->send_message(transport, chan, msg); +} + +/** + * @brief Read an SCMI message + * + * @param transport pointer to the device structure for the + * transport layer + * @param chan pointer to SCMI channel on which the message + * is to be read + * @param msg pointer to message the caller wishes to read + * + * @retval 0 if successful + * @retval negative errno code if failure + */ +static inline int scmi_transport_read_message(const struct device *transport, + struct scmi_channel *chan, + struct scmi_message *msg) +{ + const struct scmi_transport_api *api = + (const struct scmi_transport_api *)transport->api; + + if (!api || !api->read_message) { + return -ENOSYS; + } + + return api->read_message(transport, chan, msg); +} + +/** + * @brief Check if an SCMI channel is free + * + * @param transport pointer to the device structure for + * the transport layer + * @param chan pointer to SCMI channel the query is to be + * performed on + * + * @retval 0 if successful + * @retval negative errno code if failure + */ +static inline bool scmi_transport_channel_is_free(const struct device *transport, + struct scmi_channel *chan) +{ + const struct scmi_transport_api *api = + (const struct scmi_transport_api *)transport->api; + + if (!api || !api->channel_is_free) { + return -ENOSYS; + } + + return api->channel_is_free(transport, chan); +} + +/** + * @brief Perfrom SCMI core initialization + * + * @param transport pointer to the device structure for + * the transport layer + * + * @retval 0 if successful + * @retval negative errno code if failure + */ +int scmi_core_transport_init(const struct device *transport); + +#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_TRANSPORT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/util.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/util.h new file mode 100644 index 00000000..cd05f984 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/firmware/scmi/util.h @@ -0,0 +1,286 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief ARM SCMI utility header + * + * Contains various utility macros and macros used for protocol and + * transport "registration". + */ + +#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_ +#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_ + +/** + * @brief Build protocol name from its ID + * + * Given a protocol ID, this macro builds the protocol + * name. This is done by concatenating the scmi_protocol_ + * construct with the given protocol ID. + * + * @param proto protocol ID in decimal format + * + * @return protocol name + */ +#define SCMI_PROTOCOL_NAME(proto) CONCAT(scmi_protocol_, proto) + +#ifdef CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS + +#ifdef CONFIG_ARM_SCMI_MAILBOX_TRANSPORT +/** @brief Check if a protocol node has an associated channel + * + * This macro, when applied to a protocol node, checks if + * the node has a dedicated static channel allocated to it. + * This definition is specific to the mailbox driver and + * each new transport layer driver should define its own + * version of this macro based on the devicetree properties + * that indicate the presence of a dedicated channel. + * + * @param node_id protocol node identifier + * @idx channel index. Should be 0 for TX channels and 1 for + * RX channels + */ +#define DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, idx)\ + DT_PROP_HAS_IDX(node_id, shmem, idx) +#else /* CONFIG_ARM_SCMI_MAILBOX_TRANSPORT */ +#error "Transport with static channels needs to define HAS_CHAN macro" +#endif /* CONFIG_ARM_SCMI_MAILBOX_TRANSPORT */ + +#define SCMI_TRANSPORT_CHAN_NAME(proto, idx) CONCAT(scmi_channel_, proto, _, idx) + +/** + * @brief Declare a TX SCMI channel + * + * Given a node_id for a protocol, this macro declares the SCMI + * TX channel statically bound to said protocol via the "extern" + * qualifier. This is useful when the transport layer driver + * supports static channels since all channel structures are + * defined inside the transport layer driver. + * + * @param node_id protocol node identifier + */ +#define DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(node_id) \ + COND_CODE_1(DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, 0), \ + (extern struct scmi_channel \ + SCMI_TRANSPORT_CHAN_NAME(DT_REG_ADDR_RAW(node_id), 0);), \ + (extern struct scmi_channel \ + SCMI_TRANSPORT_CHAN_NAME(SCMI_PROTOCOL_BASE, 0);)) \ + +/** + * @brief Declare SCMI TX/RX channels + * + * Given a node_id for a protocol, this macro declares the + * SCMI TX and RX channels statically bound to said protocol via + * the "extern" qualifier. Since RX channels are currently not + * supported, this is equivalent to DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(). + * Despite this, users should opt for this macro instead of the TX-specific + * one. + * + * @param node_id protocol node identifier + */ +#define DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \ + DT_SCMI_TRANSPORT_TX_CHAN_DECLARE(node_id) \ + +/** + * @brief Declare SCMI TX/RX channels using node instance number + * + * Same as DT_SCMI_TRANSPORT_CHANNELS_DECLARE() but uses the + * protocol's node instance number and the DT_DRV_COMPAT macro. + * + * @param protocol node instance number + */ +#define DT_INST_SCMI_TRANSPORT_CHANNELS_DECLARE(inst) \ + DT_SCMI_TRANSPORT_CHANNELS_DECLARE(DT_INST(inst, DT_DRV_COMPAT)) + +/** + * @brief Get a reference to a protocol's SCMI TX channel + * + * Given a node_id for a protocol, this macro returns a + * reference to an SCMI TX channel statically bound to said + * protocol. + * + * @param node_id protocol node identifier + * + * @return reference to the struct scmi_channel of the TX channel + * bound to the protocol identifier by node_id + */ +#define DT_SCMI_TRANSPORT_TX_CHAN(node_id) \ + COND_CODE_1(DT_SCMI_TRANSPORT_PROTO_HAS_CHAN(node_id, 0), \ + (&SCMI_TRANSPORT_CHAN_NAME(DT_REG_ADDR_RAW(node_id), 0)), \ + (&SCMI_TRANSPORT_CHAN_NAME(SCMI_PROTOCOL_BASE, 0))) + +/** + * @brief Define an SCMI channel for a protocol + * + * This macro defines a struct scmi_channel for a given protocol. + * This should be used by the transport layer driver to statically + * define SCMI channels for the protocols. + * + * @param node_id protocol node identifier + * @param idx channel index. Should be 0 for TX channels and 1 + * for RX channels + * @param proto protocol ID in decimal format + */ +#define DT_SCMI_TRANSPORT_CHAN_DEFINE(node_id, idx, proto, pdata) \ + struct scmi_channel SCMI_TRANSPORT_CHAN_NAME(proto, idx) = \ + { \ + .data = pdata, \ + } + +/** + * @brief Define an SCMI protocol's data + * + * Each SCMI protocol is identified by a struct scmi_protocol + * placed in a linker section called scmi_protocol. Each protocol + * driver is required to use this macro for "registration". Using + * this macro directly is higly discouraged and users should opt + * for macros such as DT_SCMI_PROTOCOL_DEFINE_NODEV() or + * DT_SCMI_PROTOCOL_DEFINE(), which also takes care of the static + * channel declaration (if applicable). + * + * @param node_id protocol node identifier + * @param proto protocol ID in decimal format + * @param pdata protocol private data + */ +#define DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, proto, pdata) \ + STRUCT_SECTION_ITERABLE(scmi_protocol, SCMI_PROTOCOL_NAME(proto)) = \ + { \ + .id = proto, \ + .tx = DT_SCMI_TRANSPORT_TX_CHAN(node_id), \ + .data = pdata, \ + } + +#else /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */ + +#define DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) + +#define DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, proto, pdata) \ + STRUCT_SECTION_ITERABLE(scmi_protocol, SCMI_PROTOCOL_NAME(proto)) = \ + { \ + .id = proto, \ + .data = pdata, \ + } + +#endif /* CONFIG_ARM_SCMI_TRANSPORT_HAS_STATIC_CHANNELS */ + +/** + * @brief Define an SCMI transport driver + * + * This is merely a wrapper over DEVICE_DT_INST_DEFINE(), but is + * required since transport layer drivers are not allowed to place + * their own init() function in the init section. Instead, transport + * layer drivers place the scmi_core_transport_init() function in the + * init section, which, in turn, will call the transport layer driver + * init() function. This is required because the SCMI core needs to + * perform channel binding and setup during the transport layer driver's + * initialization. + */ +#define DT_INST_SCMI_TRANSPORT_DEFINE(inst, pm, data, config, level, prio, api) \ + DEVICE_DT_INST_DEFINE(inst, &scmi_core_transport_init, \ + pm, data, config, level, prio, api) + +/** + * @brief Define an SCMI protocol + * + * This macro performs three important functions: + * 1) It defines a `struct scmi_protocol`, which is + * needed by all protocol drivers to work with the SCMI API. + * + * 2) It declares the static channels bound to the protocol. + * This is only applicable if the transport layer driver + * supports static channels. + * + * 3) It creates a `struct device` a sets the `data` field + * to the newly defined `struct scmi_protocol`. This is + * needed because the protocol driver needs to work with the + * SCMI API **and** the subsystem API. + * + * @param node_id protocol node identifier + * @param init_fn pointer to protocol's initialization function + * @param api pointer to protocol's subsystem API + * @param pm pointer to the protocol's power management resources + * @param data pointer to protocol's private data + * @param config pointer to protocol's private constant data + * @param level protocol initialization level + * @param prio protocol's priority within its initialization level + */ +#define DT_SCMI_PROTOCOL_DEFINE(node_id, init_fn, pm, data, config, \ + level, prio, api) \ + DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \ + DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, DT_REG_ADDR_RAW(node_id), data); \ + DEVICE_DT_DEFINE(node_id, init_fn, pm, \ + &SCMI_PROTOCOL_NAME(DT_REG_ADDR_RAW(node_id)), \ + config, level, prio, api) + +/** + * @brief Just like DT_SCMI_PROTOCOL_DEFINE(), but uses an instance + * of a `DT_DRV_COMPAT` compatible instead of a node identifier + * + * @param inst instance number + * @param init_fn pointer to protocol's initialization function + * @param api pointer to protocol's subsystem API + * @param pm pointer to the protocol's power management resources + * @param data pointer to protocol's private data + * @param config pointer to protocol's private constant data + * @param level protocol initialization level + * @param prio protocol's priority within its initialization level + */ +#define DT_INST_SCMI_PROTOCOL_DEFINE(inst, init_fn, pm, data, config, \ + level, prio, api) \ + DT_SCMI_PROTOCOL_DEFINE(DT_INST(inst, DT_DRV_COMPAT), init_fn, pm, \ + data, config, level, prio, api) + +/** + * @brief Define an SCMI protocol with no device + * + * Variant of DT_SCMI_PROTOCOL_DEFINE(), but no `struct device` is + * created and no initialization function is called during system + * initialization. This is useful for protocols that are not really + * part of a subsystem with an API (e.g: pinctrl). + * + * @param node_id protocol node identifier + * @param data protocol private data + */ +#define DT_SCMI_PROTOCOL_DEFINE_NODEV(node_id, data) \ + DT_SCMI_TRANSPORT_CHANNELS_DECLARE(node_id) \ + DT_SCMI_PROTOCOL_DATA_DEFINE(node_id, DT_REG_ADDR_RAW(node_id), data) + +/** + * @brief Create an SCMI message field + * + * Data might not necessarily be encoded in the first + * x bits of an SCMI message parameter/return value. + * This comes in handy when building said parameters/ + * return values. + * + * @param x value to encode + * @param mask value to perform bitwise-and with `x` + * @param shift value to left-shift masked `x` + */ +#define SCMI_FIELD_MAKE(x, mask, shift)\ + (((uint32_t)(x) & (mask)) << (shift)) + +/** + * @brief SCMI protocol IDs + * + * Each SCMI protocol is identified by an ID. Each + * of these IDs needs to be in decimal since they + * might be used to build protocol and static channel + * names. + */ +#define SCMI_PROTOCOL_BASE 16 +#define SCMI_PROTOCOL_POWER_DOMAIN 17 +#define SCMI_PROTOCOL_SYSTEM 18 +#define SCMI_PROTOCOL_PERF 19 +#define SCMI_PROTOCOL_CLOCK 20 +#define SCMI_PROTOCOL_SENSOR 21 +#define SCMI_PROTOCOL_RESET_DOMAIN 22 +#define SCMI_PROTOCOL_VOLTAGE_DOMAIN 23 +#define SCMI_PROTOCOL_PCAP_MONITOR 24 +#define SCMI_PROTOCOL_PINCTRL 25 + +#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_UTIL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash.h index f7b31b15..b72e551e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash.h @@ -155,6 +155,18 @@ typedef int (*flash_api_write)(const struct device *dev, off_t offset, typedef int (*flash_api_erase)(const struct device *dev, off_t offset, size_t size); +/** + * @brief Get device size in bytes. + * + * Returns total logical device size in bytes. + * + * @param[in] dev flash device. + * @param[out] size device size in bytes. + * + * @return 0 on success, negative errno code on error. + */ +typedef int (*flash_api_get_size)(const struct device *dev, uint64_t *size); + typedef const struct flash_parameters* (*flash_api_get_parameters)(const struct device *dev); #if defined(CONFIG_FLASH_PAGE_LAYOUT) @@ -195,6 +207,7 @@ __subsystem struct flash_driver_api { flash_api_write write; flash_api_erase erase; flash_api_get_parameters get_parameters; + flash_api_get_size get_size; #if defined(CONFIG_FLASH_PAGE_LAYOUT) flash_api_pages_layout page_layout; #endif /* CONFIG_FLASH_PAGE_LAYOUT */ @@ -321,6 +334,33 @@ static inline int z_impl_flash_erase(const struct device *dev, off_t offset, return rc; } +/** + * @brief Get device size in bytes. + * + * Returns total logical device size in bytes. Not all devices may support + * returning size, specifically those with non uniform page layouts or banked, + * in which case the function will return -ENOTSUP, and user has to rely + * on Flash page layout functions enabled by CONFIG_FLASH_PAGE_LAYOUT. + * + * @param[in] dev flash device. + * @param[out] size device size in bytes. + * + * @return 0 on success, negative errno code on error. + */ +__syscall int flash_get_size(const struct device *dev, uint64_t *size); + +static inline int z_impl_flash_get_size(const struct device *dev, uint64_t *size) +{ + int rc = -ENOSYS; + const struct flash_driver_api *api = (const struct flash_driver_api *)dev->api; + + if (api->get_size != NULL) { + rc = api->get_size(dev, size); + } + + return rc; +} + /** * @brief Fill selected range of device with specified value * @@ -583,6 +623,37 @@ static inline const struct flash_parameters *z_impl_flash_get_parameters(const s __syscall int flash_ex_op(const struct device *dev, uint16_t code, const uintptr_t in, void *out); +/** + * @brief Copy flash memory from one device to another. + * + * Copy a region of flash memory from one place to another. The source and + * destination flash devices may be the same or different devices. However, + * this function will fail if the source and destination devices are the same + * if memory regions overlap and are not identical. + * + * The caller must supply a buffer of suitable size and ensure that the + * destination is erased beforehand, if necessary. + * + * @note If the source and destination devices are the same, and the source + * and destination offsets are also the same, this function succeeds without + * performing any copy operation. + * + * @param src_dev Source flash device. + * @param dst_dev Destination flash device. + * @param src_offset Offset within the source flash device. + * @param dst_offset Offset within the destination flash device. + * @param size Size of the region to copy, in bytes. + * @param[out] buf Pointer to a buffer of size @a buf_size. + * @param buf_size Size of the buffer pointed to by @a buf. + * + * @retval 0 on success + * @retval -EINVAL if an argument is invalid. + * @retval -EIO if an I/O error occurs. + * @retval -ENODEV if either @a src_dev or @a dst_dev are not ready. + */ +__syscall int flash_copy(const struct device *src_dev, off_t src_offset, + const struct device *dst_dev, off_t dst_offset, off_t size, uint8_t *buf, + size_t buf_size); /* * Extended operation interface provides flexible way for supporting flash * controller features. Code space is divided equally into Zephyr codes diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash/ra_flash_api_extensions.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash/ra_flash_api_extensions.h index a61a179f..465c98ac 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash/ra_flash_api_extensions.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/flash/ra_flash_api_extensions.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2024 Renesas Electronics Corporation + * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +11,6 @@ enum ra_ex_ops { FLASH_RA_EX_OP_WRITE_PROTECT = FLASH_EX_OP_VENDOR_BASE, - FLASH_RA_EX_OP_READ_PROTECT, }; typedef struct { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gnss.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gnss.h index 5a373ac5..c5d2b917 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gnss.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gnss.h @@ -21,6 +21,7 @@ * @{ */ +#include #include #include #include @@ -48,27 +49,6 @@ typedef int (*gnss_set_fix_rate_t)(const struct device *dev, uint32_t fix_interv /** API for getting fix rate */ typedef int (*gnss_get_fix_rate_t)(const struct device *dev, uint32_t *fix_interval_ms); -/** - * @brief GNSS periodic tracking configuration - * - * @note Setting either active_time or inactive_time to 0 will disable periodic - * function. - */ -struct gnss_periodic_config { - /** The time the GNSS will spend in the active state in ms */ - uint32_t active_time_ms; - /** The time the GNSS will spend in the inactive state in ms */ - uint32_t inactive_time_ms; -}; - -/** API for setting periodic tracking configuration */ -typedef int (*gnss_set_periodic_config_t)(const struct device *dev, - const struct gnss_periodic_config *periodic_config); - -/** API for setting periodic tracking configuration */ -typedef int (*gnss_get_periodic_config_t)(const struct device *dev, - struct gnss_periodic_config *periodic_config); - /** GNSS navigation modes */ enum gnss_navigation_mode { /** Dynamics have no impact on tracking */ @@ -121,6 +101,9 @@ typedef int (*gnss_get_enabled_systems_t)(const struct device *dev, gnss_systems /** API for getting enabled systems */ typedef int (*gnss_get_supported_systems_t)(const struct device *dev, gnss_systems_t *systems); +/** API for getting timestamp of last PPS pulse */ +typedef int (*gnss_get_latest_timepulse_t)(const struct device *dev, k_ticks_t *timestamp); + /** GNSS fix status */ enum gnss_fix_status { /** No GNSS fix acquired */ @@ -169,7 +152,7 @@ struct gnss_time { uint8_t hour; /** Minute [0, 59] */ uint8_t minute; - /** Millisecond [0, 59999] */ + /** Millisecond [0, 60999] */ uint16_t millisecond; /** Day of month [1, 31] */ uint8_t month_day; @@ -183,13 +166,12 @@ struct gnss_time { __subsystem struct gnss_driver_api { gnss_set_fix_rate_t set_fix_rate; gnss_get_fix_rate_t get_fix_rate; - gnss_set_periodic_config_t set_periodic_config; - gnss_get_periodic_config_t get_periodic_config; gnss_set_navigation_mode_t set_navigation_mode; gnss_get_navigation_mode_t get_navigation_mode; gnss_set_enabled_systems_t set_enabled_systems; gnss_get_enabled_systems_t get_enabled_systems; gnss_get_supported_systems_t get_supported_systems; + gnss_get_latest_timepulse_t get_latest_timepulse; }; /** GNSS data structure */ @@ -286,54 +268,6 @@ static inline int z_impl_gnss_get_fix_rate(const struct device *dev, uint32_t *f return api->get_fix_rate(dev, fix_interval_ms); } -/** - * @brief Set the GNSS periodic tracking configuration - * - * @param dev Device instance - * @param config Periodic tracking configuration to set - * - * @return 0 if successful - * @return -errno negative errno code on failure - */ -__syscall int gnss_set_periodic_config(const struct device *dev, - const struct gnss_periodic_config *config); - -static inline int z_impl_gnss_set_periodic_config(const struct device *dev, - const struct gnss_periodic_config *config) -{ - const struct gnss_driver_api *api = (const struct gnss_driver_api *)dev->api; - - if (api->set_periodic_config == NULL) { - return -ENOSYS; - } - - return api->set_periodic_config(dev, config); -} - -/** - * @brief Get the GNSS periodic tracking configuration - * - * @param dev Device instance - * @param config Destination for periodic tracking configuration - * - * @return 0 if successful - * @return -errno negative errno code on failure - */ -__syscall int gnss_get_periodic_config(const struct device *dev, - struct gnss_periodic_config *config); - -static inline int z_impl_gnss_get_periodic_config(const struct device *dev, - struct gnss_periodic_config *config) -{ - const struct gnss_driver_api *api = (const struct gnss_driver_api *)dev->api; - - if (api->get_periodic_config == NULL) { - return -ENOSYS; - } - - return api->get_periodic_config(dev, config); -} - /** * @brief Set the GNSS navigation mode * @@ -451,6 +385,33 @@ static inline int z_impl_gnss_get_supported_systems(const struct device *dev, return api->get_supported_systems(dev, systems); } +/** + * @brief Get the timestamp of the latest PPS timepulse + * + * @note The timestamp is considered valid when the timepulse pin is actively toggling. + * + * @param dev Device instance + * @param timestamp Kernel tick count at the time of the PPS pulse + * + * @retval 0 if successful + * @retval -ENOSYS if driver does not support API + * @retval -ENOTSUP if driver does not have PPS pin connected + * @retval -EAGAIN if PPS pulse is not considered valid + */ +__syscall int gnss_get_latest_timepulse(const struct device *dev, k_ticks_t *timestamp); + +static inline int z_impl_gnss_get_latest_timepulse(const struct device *dev, + k_ticks_t *timestamp) +{ + const struct gnss_driver_api *api = (const struct gnss_driver_api *)dev->api; + + if (api->get_latest_timepulse == NULL) { + return -ENOSYS; + } + + return api->get_latest_timepulse(dev, timestamp); +} + /** * @brief Register a callback structure for GNSS data published * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio.h index 4473b49e..077a6950 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio.h @@ -19,6 +19,7 @@ #include #include +#include #include #include @@ -550,7 +551,7 @@ struct gpio_dt_spec { * .ngpios = 32, * .gpios_reserved = 0xdeadbeef, * // 0b1101 1110 1010 1101 1011 1110 1110 1111 - * + * }; * static const struct some_config dev_cfg_b = { * .ngpios = 18, * .gpios_reserved = 0xfffc0418, @@ -845,6 +846,8 @@ static inline bool gpio_is_ready_dt(const struct gpio_dt_spec *spec) * not controlled directly by the GPIO module. That is, pins which are * routed to other modules such as I2C, SPI, UART. * + * @funcprops \isr_ok + * * @param port Pointer to device structure for the driver instance. * @param pin Pin number. * @param flags Interrupt configuration flags as defined by GPIO_INT_*. @@ -875,8 +878,12 @@ static inline int z_impl_gpio_pin_interrupt_configure(const struct device *port, (const struct gpio_driver_data *)port->data; enum gpio_int_trig trig; enum gpio_int_mode mode; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_pin, interrupt_configure, port, pin, flags); if (api->pin_interrupt_configure == NULL) { + SYS_PORT_TRACING_FUNC_EXIT(gpio_pin, interrupt_configure, port, pin, -ENOSYS); return -ENOSYS; } @@ -921,12 +928,16 @@ static inline int z_impl_gpio_pin_interrupt_configure(const struct device *port, mode = (enum gpio_int_mode)(flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE)); #endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */ - return api->pin_interrupt_configure(port, pin, mode, trig); + ret = api->pin_interrupt_configure(port, pin, mode, trig); + SYS_PORT_TRACING_FUNC_EXIT(gpio_pin, interrupt_configure, port, pin, ret); + return ret; } /** * @brief Configure pin interrupts from a @p gpio_dt_spec. * + * @funcprops \isr_ok + * * This is equivalent to: * * gpio_pin_interrupt_configure(spec->port, spec->pin, flags); @@ -972,6 +983,9 @@ static inline int z_impl_gpio_pin_configure(const struct device *port, (const struct gpio_driver_config *)port->config; struct gpio_driver_data *data = (struct gpio_driver_data *)port->data; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_pin, configure, port, pin, flags); __ASSERT((flags & GPIO_INT_MASK) == 0, "Interrupt flags are not supported"); @@ -1011,7 +1025,9 @@ static inline int z_impl_gpio_pin_configure(const struct device *port, data->invert &= ~(gpio_port_pins_t)BIT(pin); } - return api->pin_configure(port, pin, flags); + ret = api->pin_configure(port, pin, flags); + SYS_PORT_TRACING_FUNC_EXIT(gpio_pin, configure, port, pin, ret); + return ret; } /** @@ -1060,12 +1076,18 @@ static inline int z_impl_gpio_port_get_direction(const struct device *port, gpio gpio_port_pins_t *outputs) { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_port, get_direction, port, map, inputs, outputs); if (api->port_get_direction == NULL) { + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, get_direction, port, -ENOSYS); return -ENOSYS; } - return api->port_get_direction(port, map, inputs, outputs); + ret = api->port_get_direction(port, map, inputs, outputs); + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, get_direction, port, ret); + return ret; } #endif /* CONFIG_GPIO_GET_DIRECTION */ @@ -1184,11 +1206,18 @@ static inline int z_impl_gpio_pin_get_config(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_pin, get_config, port, pin, *flags); - if (api->pin_get_config == NULL) + if (api->pin_get_config == NULL) { + SYS_PORT_TRACING_FUNC_EXIT(gpio_pin, get_config, port, pin, -ENOSYS); return -ENOSYS; + } - return api->pin_get_config(port, pin, flags); + ret = api->pin_get_config(port, pin, flags); + SYS_PORT_TRACING_FUNC_EXIT(gpio_pin, get_config, port, pin, ret); + return ret; } #endif @@ -1230,13 +1259,16 @@ static inline int gpio_pin_get_config_dt(const struct gpio_dt_spec *spec, __syscall int gpio_port_get_raw(const struct device *port, gpio_port_value_t *value); -static inline int z_impl_gpio_port_get_raw(const struct device *port, - gpio_port_value_t *value) +static inline int z_impl_gpio_port_get_raw(const struct device *port, gpio_port_value_t *value) { - const struct gpio_driver_api *api = - (const struct gpio_driver_api *)port->api; + const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; - return api->port_get_raw(port, value); + SYS_PORT_TRACING_FUNC_ENTER(gpio_port, get_raw, port, value); + + ret = api->port_get_raw(port, value); + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, get_raw, port, ret); + return ret; } /** @@ -1299,8 +1331,13 @@ static inline int z_impl_gpio_port_set_masked_raw(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_port, set_masked_raw, port, mask, value); - return api->port_set_masked_raw(port, mask, value); + ret = api->port_set_masked_raw(port, mask, value); + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, set_masked_raw, port, ret); + return ret; } /** @@ -1353,8 +1390,13 @@ static inline int z_impl_gpio_port_set_bits_raw(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_port, set_bits_raw, port, pins); - return api->port_set_bits_raw(port, pins); + ret = api->port_set_bits_raw(port, pins); + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, set_bits_raw, port, ret); + return ret; } /** @@ -1391,8 +1433,13 @@ static inline int z_impl_gpio_port_clear_bits_raw(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_port, clear_bits_raw, port, pins); - return api->port_clear_bits_raw(port, pins); + ret = api->port_clear_bits_raw(port, pins); + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, clear_bits_raw, port, ret); + return ret; } /** @@ -1429,8 +1476,13 @@ static inline int z_impl_gpio_port_toggle_bits(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio_port, toggle_bits, port, pins); - return api->port_toggle_bits(port, pins); + ret = api->port_toggle_bits(port, pins); + SYS_PORT_TRACING_FUNC_EXIT(gpio_port, toggle_bits, port, ret); + return ret; } /** @@ -1693,11 +1745,15 @@ static inline void gpio_init_callback(struct gpio_callback *callback, gpio_callback_handler_t handler, gpio_port_pins_t pin_mask) { + SYS_PORT_TRACING_FUNC_ENTER(gpio, init_callback, callback, handler, pin_mask); + __ASSERT(callback, "Callback pointer should not be NULL"); __ASSERT(handler, "Callback handler pointer should not be NULL"); callback->handler = handler; callback->pin_mask = pin_mask; + + SYS_PORT_TRACING_FUNC_EXIT(gpio, init_callback, callback); } /** @@ -1719,12 +1775,18 @@ static inline int gpio_add_callback(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio, add_callback, port, callback); if (api->manage_callback == NULL) { + SYS_PORT_TRACING_FUNC_EXIT(gpio, add_callback, port, -ENOSYS); return -ENOSYS; } - return api->manage_callback(port, callback, true); + ret = api->manage_callback(port, callback, true); + SYS_PORT_TRACING_FUNC_EXIT(gpio, add_callback, port, ret); + return ret; } /** @@ -1767,12 +1829,18 @@ static inline int gpio_remove_callback(const struct device *port, { const struct gpio_driver_api *api = (const struct gpio_driver_api *)port->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio, remove_callback, port, callback); if (api->manage_callback == NULL) { + SYS_PORT_TRACING_FUNC_EXIT(gpio, remove_callback, port, -ENOSYS); return -ENOSYS; } - return api->manage_callback(port, callback, false); + ret = api->manage_callback(port, callback, false); + SYS_PORT_TRACING_FUNC_EXIT(gpio, remove_callback, port, ret); + return ret; } /** @@ -1812,12 +1880,18 @@ static inline int z_impl_gpio_get_pending_int(const struct device *dev) { const struct gpio_driver_api *api = (const struct gpio_driver_api *)dev->api; + int ret; + + SYS_PORT_TRACING_FUNC_ENTER(gpio, get_pending_int, dev); if (api->get_pending_int == NULL) { + SYS_PORT_TRACING_FUNC_EXIT(gpio, get_pending_int, dev, -ENOSYS); return -ENOSYS; } - return api->get_pending_int(dev); + ret = api->get_pending_int(dev); + SYS_PORT_TRACING_FUNC_EXIT(gpio, get_pending_int, dev, ret); + return ret; } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_intel.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_intel.h index b20c3e60..a5be9802 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_intel.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_intel.h @@ -4,6 +4,13 @@ * SPDX-License-Identifier: Apache-2.0 */ +#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_INTEL_H_ +#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_INTEL_H_ + +#ifdef __cplusplus +extern "C" { +#endif + struct gpio_acpi_res { uint8_t num_pins; uint32_t pad_base; @@ -13,3 +20,9 @@ struct gpio_acpi_res { uint16_t base_num; uintptr_t reg_base; }; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_INTEL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_mmio32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_mmio32.h index e959efd4..005f7205 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_mmio32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_mmio32.h @@ -11,6 +11,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + extern const struct gpio_driver_api gpio_mmio32_api; struct gpio_mmio32_config { @@ -68,5 +72,8 @@ DEVICE_DT_DEFINE(node_id, \ #endif +#ifdef __cplusplus +} +#endif #endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_nct38xx.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_nct38xx.h index 785515e8..a6f53b7c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_nct38xx.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_nct38xx.h @@ -7,6 +7,10 @@ #ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NCT38XX_H_ #define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NCT38XX_H_ +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Dispatch all GPIO ports ISR in the NCT38XX device. * @@ -14,4 +18,8 @@ */ void nct38xx_gpio_alert_handler(const struct device *dev); +#ifdef __cplusplus +} +#endif + #endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_NCT38XX_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_pcal64xxa.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_pcal64xxa.h new file mode 100644 index 00000000..07e4a722 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_pcal64xxa.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 SILA Embedded Solutions GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_PCAL64XXA_H_ +#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_PCAL64XXA_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Manually reset a PCAL64XXA + * + * Resetting a PCAL64XXA manually is only necessary if the by default + * enabled automatic reset has been disabled. + * + * @param dev Pointer to the device structure for the driver instance. + * + * @retval 0 If successful. + */ +int pcal64xxa_reset(const struct device *dev); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_PCAL64XXA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_sx1509b.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_sx1509b.h index 77705721..9ccdab08 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_sx1509b.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_sx1509b.h @@ -10,6 +10,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + /** * @brief Configure a pin for LED intensity. * @@ -42,4 +46,8 @@ int sx1509b_led_intensity_pin_configure(const struct device *dev, int sx1509b_led_intensity_pin_set(const struct device *dev, gpio_pin_t pin, uint8_t intensity_val); +#ifdef __cplusplus +} +#endif + #endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_SX1509B_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_utils.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_utils.h index 43818f41..3ee77f34 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_utils.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/gpio/gpio_utils.h @@ -16,6 +16,11 @@ #include #include #include +#include + +#ifdef __cplusplus +extern "C" { +#endif #define GPIO_PORT_PIN_MASK_FROM_NGPIOS(ngpios) \ ((gpio_port_pins_t)(((uint64_t)1 << (ngpios)) - 1U)) @@ -88,12 +93,20 @@ static inline void gpio_fire_callbacks(sys_slist_t *list, { struct gpio_callback *cb, *tmp; + sys_port_trace_gpio_fire_callbacks_enter(list, port, pins); + SYS_SLIST_FOR_EACH_CONTAINER_SAFE(list, cb, tmp, node) { if (cb->pin_mask & pins) { __ASSERT(cb->handler, "No callback handler!"); + cb->handler(port, cb, cb->pin_mask & pins); + sys_port_trace_gpio_fire_callback(port, cb); } } } +#ifdef __cplusplus +} +#endif + #endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_UTILS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/haptics.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/haptics.h new file mode 100644 index 00000000..bc76959f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/haptics.h @@ -0,0 +1,88 @@ +/* + * Copyright 2024 Cirrus Logic, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_HAPTICS_H_ +#define ZEPHYR_INCLUDE_DRIVERS_HAPTICS_H_ + +/** + * @brief Haptics Interface + * @defgroup haptics_interface Haptics Interface + * @ingroup io_interfaces + * @{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @typedef haptics_stop_output_t + * @brief Set the haptic device to stop output + * @param dev Pointer to the device structure for haptic device instance + */ +typedef int (*haptics_stop_output_t)(const struct device *dev); + +/** + * @typedef haptics_start_output_t + * @brief Set the haptic device to start output for a playback event + */ +typedef int (*haptics_start_output_t)(const struct device *dev); + +/** + * @brief Haptic device API + */ +__subsystem struct haptics_driver_api { + haptics_start_output_t start_output; + haptics_stop_output_t stop_output; +}; + +/** + * @brief Set the haptic device to start output for a playback event + * + * @param dev Pointer to the device structure for haptic device instance + * + * @retval 0 if successful + * @retval <0 if failed + */ +__syscall int haptics_start_output(const struct device *dev); + +static inline int z_impl_haptics_start_output(const struct device *dev) +{ + const struct haptics_driver_api *api = (const struct haptics_driver_api *)dev->api; + + return api->start_output(dev); +} + +/** + * @brief Set the haptic device to stop output for a playback event + * + * @param dev Pointer to the device structure for haptic device instance + * + * @retval 0 if successful + * @retval <0 if failed + */ +__syscall int haptics_stop_output(const struct device *dev); + +static inline int z_impl_haptics_stop_output(const struct device *dev) +{ + const struct haptics_driver_api *api = (const struct haptics_driver_api *)dev->api; + + return api->stop_output(dev); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#include + +#endif /* ZEPHYR_INCLUDE_DRIVERS_HAPTICS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/haptics/drv2605.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/haptics/drv2605.h new file mode 100644 index 00000000..ada27d09 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/haptics/drv2605.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2024 Cirrus Logic, Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_HAPTICS_DRV2605_H_ +#define ZEPHYR_INCLUDE_DRIVERS_HAPTICS_DRV2605_H_ + +#include +#include + +#define DRV2605_WAVEFORM_SEQUENCER_MAX 8 + +enum drv2605_library { + DRV2605_LIBRARY_EMPTY = 0, + DRV2605_LIBRARY_TS2200_A, + DRV2605_LIBRARY_TS2200_B, + DRV2605_LIBRARY_TS2200_C, + DRV2605_LIBRARY_TS2200_D, + DRV2605_LIBRARY_TS2200_E, + DRV2605_LIBRARY_LRA, +}; + +enum drv2605_mode { + DRV2605_MODE_INTERNAL_TRIGGER = 0, + DRV2605_MODE_EXTERNAL_EDGE_TRIGGER, + DRV2605_MODE_EXTERNAL_LEVEL_TRIGGER, + DRV2605_MODE_PWM_ANALOG_INPUT, + DRV2605_MODE_AUDIO_TO_VIBE, + DRV2605_MODE_RTP, + DRV2605_MODE_DIAGNOSTICS, + DRV2605_MODE_AUTO_CAL, +}; + +/** + * @brief DRV2605 haptic driver signal sources + */ +enum drv2605_haptics_source { + /** The playback source is device ROM */ + DRV2605_HAPTICS_SOURCE_ROM, + /** The playback source is the RTP buffer */ + DRV2605_HAPTICS_SOURCE_RTP, + /** The playback source is audio */ + DRV2605_HAPTICS_SOURCE_AUDIO, + /** The playback source is a PWM signal */ + DRV2605_HAPTICS_SOURCE_PWM, + /** The playback source is an analog signal */ + DRV2605_HAPTICS_SOURCE_ANALOG, +}; + +struct drv2605_rom_data { + enum drv2605_mode trigger; + enum drv2605_library library; + uint8_t seq_regs[DRV2605_WAVEFORM_SEQUENCER_MAX]; + uint8_t overdrive_time; + uint8_t sustain_pos_time; + uint8_t sustain_neg_time; + uint8_t brake_time; +}; + +struct drv2605_rtp_data { + size_t size; + uint32_t *rtp_hold_us; + uint8_t *rtp_input; +}; + +union drv2605_config_data { + struct drv2605_rom_data *rom_data; + struct drv2605_rtp_data *rtp_data; +}; + +/** + * @brief Configure the DRV2605 device for a particular signal source + * + * @param dev Pointer to the device structure for haptic device instance + * @param source The type of haptic signal source desired + * @param config_data Pointer to the configuration data union for the source + * + * @retval 0 if successful + * @retval -ENOTSUP if the signal source is not supported + * @retval <0 if failed + */ +int drv2605_haptic_config(const struct device *dev, enum drv2605_haptics_source source, + const union drv2605_config_data *config_data); + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/hwspinlock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/hwspinlock.h index c6e5b480..c1e6c02d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/hwspinlock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/hwspinlock.h @@ -78,8 +78,9 @@ static inline int z_impl_hwspinlock_trylock(const struct device *dev, uint32_t i const struct hwspinlock_driver_api *api = (const struct hwspinlock_driver_api *)dev->api; - if (api->trylock == NULL) + if (api->trylock == NULL) { return -ENOSYS; + } return api->trylock(dev, id); } @@ -100,8 +101,9 @@ static inline void z_impl_hwspinlock_lock(const struct device *dev, uint32_t id) const struct hwspinlock_driver_api *api = (const struct hwspinlock_driver_api *)dev->api; - if (api->lock != NULL) + if (api->lock != NULL) { api->lock(dev, id); + } } /** @@ -120,8 +122,9 @@ static inline void z_impl_hwspinlock_unlock(const struct device *dev, uint32_t i const struct hwspinlock_driver_api *api = (const struct hwspinlock_driver_api *)dev->api; - if (api->unlock != NULL) + if (api->unlock != NULL) { api->unlock(dev, id); + } } /** @@ -142,8 +145,9 @@ static inline uint32_t z_impl_hwspinlock_get_max_id(const struct device *dev) const struct hwspinlock_driver_api *api = (const struct hwspinlock_driver_api *)dev->api; - if (api->get_max_id == NULL) + if (api->get_max_id == NULL) { return 0; + } return api->get_max_id(dev); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i2c.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i2c.h index 240d6132..5f1c3fbe 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i2c.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i2c.h @@ -474,14 +474,26 @@ static inline bool i2c_is_ready_dt(const struct i2c_dt_spec *spec) * @brief Check if the current message is a read operation * * @param msg The message to check - * @return true if the I2C message is sa read operation + * @return true if the I2C message is a read operation * @return false if the I2C message is a write operation */ -static inline bool i2c_is_read_op(struct i2c_msg *msg) +static inline bool i2c_is_read_op(const struct i2c_msg *msg) { return (msg->flags & I2C_MSG_READ) == I2C_MSG_READ; } +/** + * @brief Check if the current message includes a stop. + * + * @param msg The message to check + * @return true if the I2C message includes a stop + * @return false if the I2C message includes a stop + */ +static inline bool i2c_is_stop_op(const struct i2c_msg *msg) +{ + return (msg->flags & I2C_MSG_STOP) == I2C_MSG_STOP; +} + /** * @brief Dump out an I2C message * @@ -785,6 +797,14 @@ static inline int z_impl_i2c_transfer(const struct device *dev, const struct i2c_driver_api *api = (const struct i2c_driver_api *)dev->api; + if (!num_msgs) { + return 0; + } + + if (!IS_ENABLED(CONFIG_I2C_ALLOW_NO_STOP_TRANSACTIONS)) { + msgs[num_msgs - 1].flags |= I2C_MSG_STOP; + } + int res = api->transfer(dev, msgs, num_msgs, addr); i2c_xfer_stats(dev, msgs, num_msgs); @@ -821,18 +841,28 @@ static inline int z_impl_i2c_transfer(const struct device *dev, * @retval -EWOULDBLOCK If the device is temporarily busy doing another transfer */ static inline int i2c_transfer_cb(const struct device *dev, - struct i2c_msg *msgs, - uint8_t num_msgs, - uint16_t addr, - i2c_callback_t cb, - void *userdata) + struct i2c_msg *msgs, + uint8_t num_msgs, + uint16_t addr, + i2c_callback_t cb, + void *userdata) { - const struct i2c_driver_api *api = (const struct i2c_driver_api *)dev->api; + const struct i2c_driver_api *api = + (const struct i2c_driver_api *)dev->api; if (api->transfer_cb == NULL) { return -ENOSYS; } + if (!num_msgs) { + cb(dev, 0, userdata); + return 0; + } + + if (!IS_ENABLED(CONFIG_I2C_ALLOW_NO_STOP_TRANSACTIONS)) { + msgs[num_msgs - 1].flags |= I2C_MSG_STOP; + } + return api->transfer_cb(dev, msgs, num_msgs, addr, cb, userdata); } @@ -982,6 +1012,18 @@ static inline int i2c_transfer_signal(const struct device *dev, #if defined(CONFIG_I2C_RTIO) || defined(__DOXYGEN__) +/** + * @brief Fallback submit implementation + * + * This implementation will schedule a blocking I2C transaction on the bus via the RTIO work + * queue. It is only used if the I2C driver did not implement the iodev_submit function. + * + * @param dev Pointer to the device structure for an I2C controller driver. + * @param iodev_sqe Prepared submissions queue entry connected to an iodev + * defined by I2C_DT_IODEV_DEFINE. + */ +void i2c_iodev_submit_fallback(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); + /** * @brief Submit request(s) to an I2C device with RTIO * @@ -994,6 +1036,10 @@ static inline void i2c_iodev_submit(struct rtio_iodev_sqe *iodev_sqe) const struct device *dev = dt_spec->bus; const struct i2c_driver_api *api = (const struct i2c_driver_api *)dev->api; + if (api->iodev_submit == NULL) { + rtio_iodev_sqe_err(iodev_sqe, -ENOSYS); + return; + } api->iodev_submit(dt_spec->bus, iodev_sqe); } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c.h index fb94f5f7..f3581663 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c.h @@ -17,14 +17,18 @@ * @{ */ -#include -#include +#include +#include +#include +#include #include #include #include #include #include +#include +#include #ifdef __cplusplus extern "C" { @@ -32,6 +36,7 @@ extern "C" { /** * @name Bus Characteristic Register (BCR) + * @anchor I3C_BCR * * - BCR[7:6]: Device Role * - 0: I3C Target @@ -121,11 +126,8 @@ extern "C" { /** Device Role - I3C Controller Capable. */ #define I3C_BCR_DEVICE_ROLE_I3C_CONTROLLER_CAPABLE 1U -/** Device Role bit shift value. */ -#define I3C_BCR_DEVICE_ROLE_SHIFT 6U - /** Device Role bit shift mask. */ -#define I3C_BCR_DEVICE_ROLE_MASK (0x03U << I3C_BCR_DEVICE_ROLE_SHIFT) +#define I3C_BCR_DEVICE_ROLE_MASK GENMASK(7U, 6U) /** * @brief Device Role @@ -135,12 +137,13 @@ extern "C" { * @param bcr BCR value */ #define I3C_BCR_DEVICE_ROLE(bcr) \ - (((bcr) & I3C_BCR_DEVICE_ROLE_MASK) >> I3C_BCR_DEVICE_ROLE_SHIFT) + FIELD_GET(I3C_BCR_DEVICE_ROLE_MASK, (bcr)) /** @} */ /** * @name Legacy Virtual Register (LVR) + * @anchor I3C_LVR * * Legacy Virtual Register (LVR) * - LVR[7:5]: I2C device index: @@ -164,9 +167,6 @@ extern "C" { /** I2C FM Mode. */ #define I3C_LVR_I2C_FM_MODE 1 -/** I2C Mode Indicator bit shift value. */ -#define I3C_LVR_I2C_MODE_SHIFT 4 - /** I2C Mode Indicator bitmask. */ #define I3C_LVR_I2C_MODE_MASK BIT(4) @@ -178,7 +178,7 @@ extern "C" { * @param lvr LVR value */ #define I3C_LVR_I2C_MODE(lvr) \ - (((lvr) & I3C_LVR_I2C_MODE_MASK) >> I3C_LVR_I2C_MODE_SHIFT) + FIELD_GET(I3C_LVR_I2C_MODE_MASK, (lvr)) /** * @brief I2C Device Index 0. @@ -204,11 +204,8 @@ extern "C" { */ #define I3C_LVR_I2C_DEV_IDX_2 2 -/** I2C Device Index bit shift value. */ -#define I3C_LVR_I2C_DEV_IDX_SHIFT 5 - /** I2C Device Index bitmask. */ -#define I3C_LVR_I2C_DEV_IDX_MASK (0x07U << I3C_LVR_I2C_DEV_IDX_SHIFT) +#define I3C_LVR_I2C_DEV_IDX_MASK GENMASK(7U, 5U) /** * @brief I2C Device Index @@ -218,7 +215,7 @@ extern "C" { * @param lvr LVR value */ #define I3C_LVR_I2C_DEV_IDX(lvr) \ - (((lvr) & I3C_LVR_I2C_DEV_IDX_MASK) >> I3C_LVR_I2C_DEV_IDX_SHIFT) + FIELD_GET(I3C_LVR_I2C_DEV_IDX_MASK, (lvr)) /** @} */ @@ -299,7 +296,7 @@ enum i3c_data_rate { * * These are error codes defined by the I3C specification. * - * @c I3C_ERROR_CE_UNKNOWN and @c I3C_ERROR_CE_NONE are not + * #I3C_ERROR_CE_UNKNOWN and #I3C_ERROR_CE_NONE are not * official error codes according to the specification. * These are there simply to aid in error handling during * interactions with the I3C drivers and subsystem. @@ -332,7 +329,7 @@ enum i3c_sdr_controller_error_codes { * * These are error codes defined by the I3C specification. * - * @c I3C_ERROR_TE_UNKNOWN and @c I3C_ERROR_TE_NONE are not + * #I3C_ERROR_TE_UNKNOWN and #I3C_ERROR_TE_NONE are not * official error codes according to the specification. * These are there simply to aid in error handling during * interactions with the I3C drivers and subsystem. @@ -470,7 +467,7 @@ enum i3c_sdr_target_error_codes { * Invocations of i3c_transfer() may not indicate an error when an * unsupported configuration is encountered. In some cases drivers * will generate separate transactions for each message fragment, with - * or without presence of @ref I3C_MSG_RESTART in #flags. + * or without presence of #I3C_MSG_RESTART in #flags. */ struct i3c_msg { /** Data buffer in bytes */ @@ -493,7 +490,7 @@ struct i3c_msg { /** * HDR mode (@c I3C_MSG_HDR_MODE*) for transfer - * if any @c I3C_MSG_HDR_* is set in @c flags. + * if any @c I3C_MSG_HDR_* is set in #flags. * * Use SDR mode if none is set. */ @@ -545,7 +542,7 @@ struct i3c_config_controller { * @brief Custom I3C configuration parameters. * * This can be used to configure the I3C hardware on parameters - * not covered by @see i3c_config_controller or @see i3c_config_target. + * not covered by i3c_config_controller or i3c_config_target. * Mostly used to configure vendor specific parameters of the I3C * hardware. */ @@ -584,21 +581,23 @@ __subsystem struct i3c_driver_api { * * @see i2c_driver_api for more information. * - * (DO NOT MOVE! Must be at the beginning.) + * @internal + * @warning DO NOT MOVE! Must be at the beginning. + * @endinternal */ struct i2c_driver_api i2c_api; /** * Configure the I3C hardware. * - * @see i3c_configure + * @see i3c_configure() * * @param dev Pointer to controller device driver instance. * @param type Type of configuration parameters being passed * in @p config. * @param config Pointer to the configuration parameters. * - * @return @see i3c_configure + * @return See i3c_configure() */ int (*configure)(const struct device *dev, enum i3c_config_type type, void *config); @@ -606,14 +605,14 @@ __subsystem struct i3c_driver_api { /** * Get configuration of the I3C hardware. * - * @see i3c_config_get + * @see i3c_config_get() * * @param[in] dev Pointer to controller device driver instance. * @param[in] type Type of configuration parameters being passed * in @p config. * @param[in, out] config Pointer to the configuration parameters. * - * @return @see i3c_config_get + * @return See i3c_config_get() */ int (*config_get)(const struct device *dev, enum i3c_config_type type, void *config); @@ -623,11 +622,11 @@ __subsystem struct i3c_driver_api { * * Controller only API. * - * @see i3c_recover_bus + * @see i3c_recover_bus() * * @param dev Pointer to controller device driver instance. * - * @return @see i3c_recover_bus + * @return See i3c_recover_bus() */ int (*recover_bus)(const struct device *dev); @@ -636,30 +635,28 @@ __subsystem struct i3c_driver_api { * * Optional API. * - * @see i3c_attach_i3c_device + * @see i3c_attach_i3c_device() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. - * @param addr Address to attach with * - * @return @see i3c_attach_i3c_device + * @return See i3c_attach_i3c_device() */ int (*attach_i3c_device)(const struct device *dev, - struct i3c_device_desc *target, - uint8_t addr); + struct i3c_device_desc *target); /** * I3C Address Update * * Optional API. * - * @see i3c_reattach_i3c_device + * @see i3c_reattach_i3c_device() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * @param old_dyn_addr Old dynamic address * - * @return @see i3c_reattach_i3c_device + * @return See i3c_reattach_i3c_device() */ int (*reattach_i3c_device)(const struct device *dev, struct i3c_device_desc *target, @@ -670,12 +667,12 @@ __subsystem struct i3c_driver_api { * * Optional API. * - * @see i3c_detach_i3c_device + * @see i3c_detach_i3c_device() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * - * @return @see i3c_detach_i3c_device + * @return See i3c_detach_i3c_device() */ int (*detach_i3c_device)(const struct device *dev, struct i3c_device_desc *target); @@ -685,12 +682,12 @@ __subsystem struct i3c_driver_api { * * Optional API. * - * @see i3c_attach_i2c_device + * @see i3c_attach_i2c_device() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * - * @return @see i3c_attach_i2c_device + * @return See i3c_attach_i2c_device() */ int (*attach_i2c_device)(const struct device *dev, struct i3c_i2c_device_desc *target); @@ -700,12 +697,12 @@ __subsystem struct i3c_driver_api { * * Optional API. * - * @see i3c_detach_i2c_device + * @see i3c_detach_i2c_device() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * - * @return @see i3c_detach_i2c_device + * @return See i3c_detach_i2c_device() */ int (*detach_i2c_device)(const struct device *dev, struct i3c_i2c_device_desc *target); @@ -715,11 +712,11 @@ __subsystem struct i3c_driver_api { * * Controller only API. * - * @see i3c_do_daa + * @see i3c_do_daa() * * @param dev Pointer to controller device driver instance. * - * @return @see i3c_do_daa + * @return See i3c_do_daa() */ int (*do_daa)(const struct device *dev); @@ -728,12 +725,12 @@ __subsystem struct i3c_driver_api { * * Controller only API. * - * @see i3c_do_ccc + * @see i3c_do_ccc() * * @param dev Pointer to controller device driver instance. * @param payload Pointer to the CCC payload. * - * @return @see i3c_do_ccc + * @return See i3c_do_ccc() */ int (*do_ccc)(const struct device *dev, struct i3c_ccc_payload *payload); @@ -741,14 +738,14 @@ __subsystem struct i3c_driver_api { /** * Transfer messages in I3C mode. * - * @see i3c_transfer + * @see i3c_transfer() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * @param msg Pointer to I3C messages. * @param num_msgs Number of messages to transfer. * - * @return @see i3c_transfer + * @return See i3c_transfer() */ int (*i3c_xfers)(const struct device *dev, struct i3c_device_desc *target, @@ -766,7 +763,7 @@ __subsystem struct i3c_driver_api { * @param dev Pointer to controller device driver instance. * @param id Pointer to I3C device ID. * - * @return @see i3c_device_find. + * @return See i3c_device_find(). */ struct i3c_device_desc *(*i3c_device_find)(const struct device *dev, const struct i3c_device_id *id); @@ -776,12 +773,12 @@ __subsystem struct i3c_driver_api { * * Target device only API. * - * @see i3c_ibi_request + * @see i3c_ibi_request() * * @param dev Pointer to controller device driver instance. * @param request Pointer to IBI request struct. * - * @return @see i3c_ibi_request + * @return See i3c_ibi_request() */ int (*ibi_raise)(const struct device *dev, struct i3c_ibi *request); @@ -791,12 +788,12 @@ __subsystem struct i3c_driver_api { * * Controller only API. * - * @see i3c_ibi_enable + * @see i3c_ibi_enable() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * - * @return @see i3c_ibi_enable + * @return See i3c_ibi_enable() */ int (*ibi_enable)(const struct device *dev, struct i3c_device_desc *target); @@ -806,12 +803,12 @@ __subsystem struct i3c_driver_api { * * Controller only API. * - * @see i3c_ibi_disable + * @see i3c_ibi_disable() * * @param dev Pointer to controller device driver instance. * @param target Pointer to target device descriptor. * - * @return @see i3c_ibi_disable + * @return See i3c_ibi_disable() */ int (*ibi_disable)(const struct device *dev, struct i3c_device_desc *target); @@ -824,12 +821,12 @@ __subsystem struct i3c_driver_api { * * Target device only API. * - * @see i3c_target_register + * @see i3c_target_register() * * @param dev Pointer to the controller device driver instance. * @param cfg I3C target device configuration * - * @return @see i3c_target_register + * @return See i3c_target_register() */ int (*target_register)(const struct device *dev, struct i3c_target_config *cfg); @@ -842,12 +839,12 @@ __subsystem struct i3c_driver_api { * * Target device only API. * - * @see i3c_target_unregister + * @see i3c_target_unregister() * * @param dev Pointer to the controller device driver instance. * @param cfg I3C target device configuration * - * @return @see i3c_target_unregister + * @return See i3c_target_unregister() */ int (*target_unregister)(const struct device *dev, struct i3c_target_config *cfg); @@ -859,16 +856,17 @@ __subsystem struct i3c_driver_api { * * Target device only API. * - * @see i3c_target_tx_write + * @see i3c_target_tx_write() * * @param dev Pointer to the controller device driver instance. * @param buf Pointer to the buffer * @param len Length of the buffer + * @param hdr_mode HDR mode * - * @return @see i3c_target_tx_write + * @return See i3c_target_tx_write() */ int (*target_tx_write)(const struct device *dev, - uint8_t *buf, uint16_t len); + uint8_t *buf, uint16_t len, uint8_t hdr_mode); }; /** @@ -886,8 +884,8 @@ struct i3c_device_id { /** * @brief Structure initializer for i3c_device_id from PID * - * This helper macro expands to a static initializer for a struct - * i3c_device_id by populating the PID (Provisioned ID) field. + * This helper macro expands to a static initializer for a i3c_device_id + * by populating the PID (Provisioned ID) field. * * @param pid Provisioned ID. */ @@ -905,22 +903,15 @@ struct i3c_device_id { * - i3c_transfers() to initiate data transfers between controller and * target device. * - * Fields @c bus, @c pid and @c static_addr must be initialized by - * the module that implements the target device behavior prior to - * passing the object reference to I3C controller device APIs. - * @c static_addr can be zero if target device does not have static - * address. + * Fields #bus, #pid and #static_addr must be initialized by the module that + * implements the target device behavior prior to passing the object reference + * to I3C controller device APIs. #static_addr can be zero if target device does + * not have static address. * - * Field @c node should not be initialized or modified manually. + * Internal field @c node should not be initialized or modified manually. */ struct i3c_device_desc { - /** - * Used to attach this node onto a linked list. - * - * @cond INTERNAL_HIDDEN - */ sys_snode_t node; - /** @endcond */ /** I3C bus to which this target device is attached */ const struct device * const bus; @@ -956,6 +947,14 @@ struct i3c_device_desc { */ const uint8_t init_dynamic_addr; + /** + * Device support for SETAASA + * + * This will be used as an optimization for bus initializtion if the + * device supports SETAASA. + */ + const bool supports_setaasa; + /** * Dynamic Address for this target device used for communication. * @@ -978,38 +977,14 @@ struct i3c_device_desc { * - Set Group Address (SETGRPA) * * 0 if group address has not been assigned. + * Only available if @kconfig{CONFIG_I3C_USE_GROUP_ADDR} is set. */ uint8_t group_addr; #endif /* CONFIG_I3C_USE_GROUP_ADDR */ /** * Bus Characteristic Register (BCR) - * - BCR[7:6]: Device Role - * - 0: I3C Target - * - 1: I3C Controller capable - * - 2: Reserved - * - 3: Reserved - * - BCR[5]: Advanced Capabilities - * - 0: Does not support optional advanced capabilities. - * - 1: Supports optional advanced capabilities which - * can be viewed via GETCAPS CCC. - * - BCR[4}: Virtual Target Support - * - 0: Is not a virtual target. - * - 1: Is a virtual target. - * - BCR[3]: Offline Capable - * - 0: Will always response to I3C commands. - * - 1: Will not always response to I3C commands. - * - BCR[2]: IBI Payload - * - 0: No data bytes following the accepted IBI. - * - 1: One data byte (MDB, Mandatory Data Byte) follows - * the accepted IBI. Additional data bytes may also - * follows. - * - BCR[1]: IBI Request Capable - * - 0: Not capable - * - 1: Capable - * - BCR[0]: Max Data Speed Limitation - * - 0: No Limitation - * - 1: Limitation obtained via GETMXDS CCC. + * @see @ref I3C_BCR */ uint8_t bcr; @@ -1095,10 +1070,9 @@ struct i3c_device_desc { uint8_t getcap4; } getcaps; + /** @cond INTERNAL_HIDDEN */ /** * Private data by the controller to aid in transactions. Do not modify. - * - * @cond INTERNAL_HIDDEN */ void *controller_priv; /** @endcond */ @@ -1106,6 +1080,7 @@ struct i3c_device_desc { #if defined(CONFIG_I3C_USE_IBI) || defined(__DOXYGEN__) /** * In-Band Interrupt (IBI) callback. + * Only available if @kconfig{CONFIG_I3C_USE_IBI} is set. */ i3c_target_ibi_cb_t ibi_cb; #endif /* CONFIG_I3C_USE_IBI */ @@ -1125,13 +1100,7 @@ struct i3c_device_desc { * reference to I3C controller device APIs. */ struct i3c_i2c_device_desc { - /** - * Used to attach this node onto a linked list. - * - * @cond INTERNAL_HIDDEN - */ sys_snode_t node; - /** @endcond */ /** I3C bus to which this I2C device is attached */ const struct device *bus; @@ -1141,24 +1110,13 @@ struct i3c_i2c_device_desc { /** * Legacy Virtual Register (LVR) - * - LVR[7:5]: I2C device index: - * - 0: I2C device has a 50 ns spike filter where - * it is not affected by high frequency on SCL. - * - 1: I2C device does not have a 50 ns spike filter - * but can work with high frequency on SCL. - * - 2: I2C device does not have a 50 ns spike filter - * and cannot work with high frequency on SCL. - * - LVR[4]: I2C mode indicator: - * - 0: FM+ mode - * - 1: FM mode - * - LVR[3:0]: Reserved. + * @see @ref I3C_LVR */ const uint8_t lvr; + /** @cond INTERNAL_HIDDEN */ /** * Private data by the controller to aid in transactions. Do not modify. - * - * @cond INTERNAL_HIDDEN */ void *controller_priv; /** @endcond */ @@ -1246,6 +1204,28 @@ struct i3c_driver_data { struct i3c_dev_attached_list attached_dev; }; +/** + * @brief iterate over all I3C devices present on the bus + * + * @param bus: the I3C bus device pointer + * @param desc: an I3C device descriptor pointer updated to point to the current slot + * at each iteration of the loop + */ +#define I3C_BUS_FOR_EACH_I3CDEV(bus, desc) \ + SYS_SLIST_FOR_EACH_CONTAINER( \ + &((struct i3c_driver_data *)(bus->data))->attached_dev.devices.i3c, desc, node) + +/** + * @brief iterate over all I2C devices present on the bus + * + * @param bus: the I3C bus device pointer + * @param desc: an I2C device descriptor pointer updated to point to the current slot + * at each iteration of the loop + */ +#define I3C_BUS_FOR_EACH_I2CDEV(bus, desc) \ + SYS_SLIST_FOR_EACH_CONTAINER( \ + &((struct i3c_driver_data *)(bus->data))->attached_dev.devices.i2c, desc, node) + /** * @brief Find a I3C target device descriptor by ID. * @@ -1256,7 +1236,7 @@ struct i3c_driver_data { * @param id Pointer to I3C device ID struct. * * @return Pointer to the I3C target device descriptor, or - * NULL if none is found. + * `NULL` if none is found. */ struct i3c_device_desc *i3c_dev_list_find(const struct i3c_dev_list *dev_list, const struct i3c_device_id *id); @@ -1267,13 +1247,13 @@ struct i3c_device_desc *i3c_dev_list_find(const struct i3c_dev_list *dev_list, * This finds the I3C target device descriptor in the attached * device list matching the dynamic address (@p addr) * - * @param dev_list Pointer to the device list struct. + * @param dev Pointer to controller device driver instance. * @param addr Dynamic address to be matched. * * @return Pointer to the I3C target device descriptor, or - * NULL if none is found. + * `NULL` if none is found. */ -struct i3c_device_desc *i3c_dev_list_i3c_addr_find(struct i3c_dev_attached_list *dev_list, +struct i3c_device_desc *i3c_dev_list_i3c_addr_find(const struct device *dev, uint8_t addr); /** @@ -1282,30 +1262,15 @@ struct i3c_device_desc *i3c_dev_list_i3c_addr_find(struct i3c_dev_attached_list * This finds the I2C target device descriptor in the attached * device list matching the address (@p addr) * - * @param dev_list Pointer to the device list struct. + * @param dev Pointer to controller device driver instance. * @param addr Address to be matched. * * @return Pointer to the I2C target device descriptor, or - * NULL if none is found. + * `NULL` if none is found. */ -struct i3c_i2c_device_desc *i3c_dev_list_i2c_addr_find(struct i3c_dev_attached_list *dev_list, +struct i3c_i2c_device_desc *i3c_dev_list_i2c_addr_find(const struct device *dev, uint16_t addr); -/** - * @brief Helper function to find the default address an i3c device is attached with - * - * This is a helper function to find the default address the - * device will be loaded with. This could be either it's static - * address, a requested dynamic address, or just a dynamic address - * that is available - * @param[in] target The pointer of the device descriptor - * @param[out] addr Address to be assigned to target device. - * - * @retval 0 if successful. - * @retval -EINVAL if the expected default address is already in use - */ -int i3c_determine_default_addr(struct i3c_device_desc *target, uint8_t *addr); - /** * @brief Helper function to find a usable address during ENTDAA. * @@ -1314,7 +1279,7 @@ int i3c_determine_default_addr(struct i3c_device_desc *target, uint8_t *addr); * search through the device list for the matching device * descriptor. If the device descriptor indicates that there is * a preferred address (i.e. assigned-address in device tree, - * @see i3c_device_desc::init_dynamic_addr), this preferred + * i3c_device_desc::init_dynamic_addr), this preferred * address will be returned if this address is still available. * If it is not available, another free address will be returned. * @@ -1328,14 +1293,14 @@ int i3c_determine_default_addr(struct i3c_device_desc *target, uint8_t *addr); * * If @p assigned_okay is true, it will return the same address * already assigned to the device - * (@see i3c_device_desc::dynamic_addr). If no address has been + * (i3c_device_desc::dynamic_addr). If no address has been * assigned, it behaves as if @p assigned_okay is false. * This is useful for assigning the same address to the same * device (for example, hot-join after device coming back from * suspend). * * If @p assigned_okay is false, the device cannot have an address - * assigned already (that @see i3c_device_desc::dynamic_addr is not + * assigned already (that i3c_device_desc::dynamic_addr is not * zero). This is mainly used during the initial DAA. * * @param[in] addr_slots Pointer to address slots struct. @@ -1403,7 +1368,7 @@ static inline int i3c_configure(const struct device *dev, * in @p config. * @param[in,out] config Pointer to the configuration parameters. * - * Note that if @p type is @c I3C_CONFIG_CUSTOM, @p config must contain + * Note that if @p type is #I3C_CONFIG_CUSTOM, @p config must contain * the ID of the parameter to be retrieved. * * @retval 0 If successful. @@ -1628,15 +1593,15 @@ static inline int z_impl_i3c_do_ccc(const struct device *dev, * to a target device synchronously. Use i3c_read()/i3c_write() * for simple read or write. * - * The array of message @a msgs must not be NULL. The number of - * message @a num_msgs may be zero, in which case no transfer occurs. + * The array of message @p msgs must not be `NULL`. The number of + * message @p num_msgs may be zero, in which case no transfer occurs. * * @note Not all scatter/gather transactions can be supported by all * drivers. As an example, a gather write (multiple consecutive - * `i3c_msg` buffers all configured for `I3C_MSG_WRITE`) may be packed + * i3c_msg buffers all configured for #I3C_MSG_WRITE) may be packed * into a single transaction by some drivers, but others may emit each * fragment as a distinct write transaction, which will not produce - * the same behavior. See the documentation of `struct i3c_msg` for + * the same behavior. See the documentation of i3c_msg for * limitations on support for multi-message bus transactions. * * @param target I3C target device descriptor. @@ -1672,7 +1637,7 @@ static inline int z_impl_i3c_transfer(struct i3c_device_desc *target, * @param dev Pointer to controller device driver instance. * @param id Pointer to I3C device ID. * - * @return Pointer to I3C device descriptor, or NULL if + * @return Pointer to I3C device descriptor, or `NULL` if * no I3C device found matching incoming @p id. */ static inline @@ -1775,7 +1740,7 @@ static inline int i3c_ibi_disable(struct i3c_device_desc *target) * whether IBI from device has payload. * * Note that BCR must have been obtained from device and - * @see i3c_device_desc::bcr must be set. + * i3c_device_desc::bcr must be set. * * @return True if IBI has payload, false otherwise. */ @@ -1792,7 +1757,7 @@ static inline int i3c_ibi_has_payload(struct i3c_device_desc *target) * whether device is capable of IBI. * * Note that BCR must have been obtained from device and - * @see i3c_device_desc::bcr must be set. + * i3c_device_desc::bcr must be set. * * @return True if IBI has payload, false otherwise. */ @@ -1802,6 +1767,23 @@ static inline int i3c_device_is_ibi_capable(struct i3c_device_desc *target) == I3C_BCR_IBI_REQUEST_CAPABLE; } +/** + * @brief Check if the target is controller capable + * + * This reads the BCR from the device descriptor struct to determine + * whether the target is controller capable + * + * Note that BCR must have been obtained from device and + * i3c_device_desc::bcr must be set. + * + * @return True if target is controller capable, false otherwise. + */ +static inline int i3c_device_is_controller_capable(struct i3c_device_desc *target) +{ + return I3C_BCR_DEVICE_ROLE(target->bcr) + == I3C_BCR_DEVICE_ROLE_I3C_CONTROLLER_CAPABLE; +} + /** @} */ /** @@ -1830,6 +1812,7 @@ static inline int i3c_write(struct i3c_device_desc *target, msg.buf = (uint8_t *)buf; msg.len = num_bytes; msg.flags = I3C_MSG_WRITE | I3C_MSG_STOP; + msg.hdr_mode = 0; msg.hdr_cmd_code = 0; return i3c_transfer(target, &msg, 1); @@ -1856,6 +1839,7 @@ static inline int i3c_read(struct i3c_device_desc *target, msg.buf = buf; msg.len = num_bytes; msg.flags = I3C_MSG_READ | I3C_MSG_STOP; + msg.hdr_mode = 0; msg.hdr_cmd_code = 0; return i3c_transfer(target, &msg, 1); @@ -1887,11 +1871,13 @@ static inline int i3c_write_read(struct i3c_device_desc *target, msg[0].buf = (uint8_t *)write_buf; msg[0].len = num_write; msg[0].flags = I3C_MSG_WRITE; + msg[0].hdr_mode = 0; msg[0].hdr_cmd_code = 0; msg[1].buf = (uint8_t *)read_buf; msg[1].len = num_read; msg[1].flags = I3C_MSG_RESTART | I3C_MSG_READ | I3C_MSG_STOP; + msg[1].hdr_mode = 0; msg[1].hdr_cmd_code = 0; return i3c_transfer(target, msg, 2); @@ -1954,11 +1940,13 @@ static inline int i3c_burst_write(struct i3c_device_desc *target, msg[0].buf = &start_addr; msg[0].len = 1U; msg[0].flags = I3C_MSG_WRITE; + msg[0].hdr_mode = 0; msg[0].hdr_cmd_code = 0; msg[1].buf = (uint8_t *)buf; msg[1].len = num_bytes; msg[1].flags = I3C_MSG_WRITE | I3C_MSG_STOP; + msg[1].hdr_mode = 0; msg[1].hdr_cmd_code = 0; return i3c_transfer(target, msg, 2); @@ -2117,6 +2105,31 @@ int i3c_bus_init(const struct device *dev, */ int i3c_device_basic_info_get(struct i3c_device_desc *target); +/** + * @brief Check if the bus has a secondary controller. + * + * This reads the BCR from the device descriptor struct of all targets + * to determine whether a device is a secondary controller. + * + * @param dev Pointer to controller device driver instance. + * + * @return True if the bus has a secondary controller, false otherwise. + */ +bool i3c_bus_has_sec_controller(const struct device *dev); + +/** + * @brief Send the CCC DEFTGTS + * + * This builds the payload required for DEFTGTS and transmits it out + * + * @param dev Pointer to controller device driver instance. + * + * @retval 0 if successful. + * @retval -ENOMEM No memory to build the payload. + * @retval -EIO General Input/Output error. + */ +int i3c_bus_deftgts(const struct device *dev); + /* * This needs to be after declaration of struct i3c_driver_api, * or else compiler complains about undefined type inside @@ -2124,6 +2137,11 @@ int i3c_device_basic_info_get(struct i3c_device_desc *target); */ #include +/* + * Include High-Data-Rate (HDR) inline helper functions + */ +#include + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/addresses.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/addresses.h index c85255d8..8d485e9b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/addresses.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/addresses.h @@ -14,8 +14,9 @@ * @{ */ -#include -#include +#include + +#include #include #ifdef __cplusplus diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ccc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ccc.h index 2274878b..8d662258 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ccc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ccc.h @@ -15,7 +15,8 @@ * @{ */ -#include +#include + #include #include #include @@ -450,6 +451,9 @@ struct i3c_ccc_deftgts_target { * this CCC. */ struct i3c_ccc_deftgts { + /** Number of Targets (and Groups) present on the I3C Bus */ + uint8_t count; + /** Data describing the active controller */ struct i3c_ccc_deftgts_active_controller active_controller; @@ -457,6 +461,19 @@ struct i3c_ccc_deftgts { struct i3c_ccc_deftgts_target targets[]; } __packed; +/** + * @brief Defining byte values for ENTTM. + */ +enum i3c_ccc_enttm_defbyte { + /** Remove all I3C Devices from Test Mode */ + ENTTM_EXIT_TEST_MODE = 0x00U, + + /** Indicates that I3C Devices shall return a random 32-bit value + * in the PID during the Dynamic Address Assignment procedure + */ + ENTTM_VENDOR_TEST_MODE = 0x01U, +}; + /** * @brief Payload for a single device address. * @@ -479,7 +496,7 @@ struct i3c_ccc_address { * - For GETACCCR, the correct address of Secondary * Controller. * - * @note For SETDATA, SETNEWDA and SETGRAP, + * @note For SETDATA, SETNEWDA and SETGRPA, * the address is left-shift by 1, and bit[0] is always 0. * * @note Fpr SET GETACCCR, the address is left-shift by 1, @@ -592,12 +609,8 @@ union i3c_ccc_getstatus { /** GETSTATUS Format 1 - Protocol Error bit. */ #define I3C_CCC_GETSTATUS_PROTOCOL_ERR BIT(5) -/** GETSTATUS Format 1 - Activity Mode bit shift value. */ -#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT 6 - /** GETSTATUS Format 1 - Activity Mode bitmask. */ -#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK \ - (0x03U << I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT) +#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK GENMASK(7U, 6U) /** * @brief GETSTATUS Format 1 - Activity Mode @@ -608,15 +621,10 @@ union i3c_ccc_getstatus { * @param status GETSTATUS Format 1 value */ #define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status) \ - (((status) & I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK) \ - >> I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT) - -/** GETSTATUS Format 1 - Number of Pending Interrupts bit shift value. */ -#define I3C_CCC_GETSTATUS_NUM_INT_SHIFT 0 + FIELD_GET(I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK, (status)) /** GETSTATUS Format 1 - Number of Pending Interrupts bitmask. */ -#define I3C_CCC_GETSTATUS_NUM_INT_MASK \ - (0x0FU << I3C_CCC_GETSTATUS_NUM_INT_SHIFT) +#define I3C_CCC_GETSTATUS_NUM_INT_MASK GENMASK(3U, 0U) /** * @brief GETSTATUS Format 1 - Number of Pending Interrupts @@ -627,8 +635,7 @@ union i3c_ccc_getstatus { * @param status GETSTATUS Format 1 value */ #define I3C_CCC_GETSTATUS_NUM_INT(status) \ - (((status) & I3C_CCC_GETSTATUS_NUM_INT_MASK) \ - >> I3C_CCC_GETSTATUS_NUM_INT_SHIFT) + FIELD_GET(I3C_CCC_GETSTATUS_NUM_INT_MASK, (status)) /** GETSTATUS Format 2 - PERCR - Deep Sleep Detected bit. */ #define I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED BIT(0) @@ -674,10 +681,40 @@ struct i3c_ccc_setbrgtgt { struct i3c_ccc_setbrgtgt_tgt targets[]; } __packed; +/** + * @brief Indicate which format of getmxds to use. + */ +enum i3c_ccc_getmxds_fmt { + /** GETMXDS Format 1 */ + GETMXDS_FORMAT_1, + + /** GETMXDS Format 2 */ + GETMXDS_FORMAT_2, + + /** GETMXDS Format 3 */ + GETMXDS_FORMAT_3, +}; + +/** + * @brief Enum for I3C Get Max Data Speed (GETMXDS) Format 3 Defining Byte Values. + */ +enum i3c_ccc_getmxds_defbyte { + /** Standard Target Write/Read speed parameters, and optional Maximum Read Turnaround Time + */ + GETMXDS_FORMAT_3_WRRDTURN = 0x00U, + + /** Delay parameters for a Controller-capable Device, and it's expected Activity State + * during a Controller Handoff + */ + GETMXDS_FORMAT_3_CRHDLY = 0x91U, + + /** Invalid defining byte. */ + GETMXDS_FORMAT_3_INVALID = 0x100, +}; + + /** * @brief Payload for GETMXDS CCC (Get Max Data Speed). - * - * @note This is only for GETMXDS Format 1 and Format 2. */ union i3c_ccc_getmxds { struct { @@ -709,7 +746,7 @@ union i3c_ccc_getmxds { * * @see i3c_ccc_getmxds::fmt2 */ - uint8_t wrrdturn; + uint8_t wrrdturn[5]; /** * Defining Byte 0x91: CRHDLY @@ -756,12 +793,8 @@ union i3c_ccc_getmxds { /** Get Max Data Speed (GETMXDS) - maxWr - Optional Defining Byte Support. */ #define I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT BIT(3) -/** Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bit shift value. */ -#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT 0 - /** Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bitmask. */ -#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK \ - (0x07U << I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT) +#define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK GENMASK(2U, 0U) /** * @brief Get Max Data Speed (GETMXDS) - maxWr - Max Sustained Data Rate @@ -772,19 +805,13 @@ union i3c_ccc_getmxds { * @param maxwr GETMXDS maxWr value. */ #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr) \ - (((maxwr) & \ - I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK) \ - >> I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT) + FIELD_GET(I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK, (maxwr)) /** Get Max Data Speed (GETMXDS) - maxRd - Write-to-Read Permits Stop Between. */ #define I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN BIT(6) -/** Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bit shift value. */ -#define I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT 3 - /** Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bitmask. */ -#define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK \ - (0x07U << I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT) +#define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK GENMASK(5U, 3U) /** * @brief Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround @@ -795,15 +822,10 @@ union i3c_ccc_getmxds { * @param maxrd GETMXDS maxRd value. */ #define I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd) \ - (((maxrd) & I3C_CCC_GETMXDS_MAXRD_TSCO_MASK) \ - >> I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT) - -/** Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bit shift value. */ -#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT 0 + FIELD_GET(I3C_CCC_GETMXDS_MAXRD_TSCO_MASK, (maxrd)) /** Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bitmask. */ -#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK \ - (0x07U << I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT) +#define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK GENMASK(2U, 0U) /** * @brief Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate @@ -814,19 +836,13 @@ union i3c_ccc_getmxds { * @param maxrd GETMXDS maxRd value. */ #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd) \ - (((maxrd) & \ - I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK) \ - >> I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT) + FIELD_GET(I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK, (maxrd)) /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Set Bus Activity State bit shift value. */ #define I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE BIT(2) -/** Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bit shift value. */ -#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT 0 - /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bitmask. */ -#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK \ - (0x03U << I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT) +#define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK GENMASK(1U, 0U) /** * @brief Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State @@ -837,9 +853,7 @@ union i3c_ccc_getmxds { * @param crhdly1 GETMXDS value. */ #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1) \ - (((crhdly1) & \ - I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK) \ - >> I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT) + FIELD_GET(I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK, (chrdly1)) /** * @brief Indicate which format of GETCAPS to use. @@ -1016,18 +1030,11 @@ union i3c_ccc_getcaps { /** Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - HDR-DDR Abort CRC bit. */ #define I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC BIT(7) -/** - * @brief Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - - * Group Address Capabilities bit shift value. - */ -#define I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT 4 - /** * @brief Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - * Group Address Capabilities bitmask. */ -#define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK \ - (0x03U << I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT) +#define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK GENMASK(5U, 4U) /** * @brief Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - Group Address Capabilities. @@ -1038,22 +1045,13 @@ union i3c_ccc_getcaps { * @param getcaps2 GETCAPS2 value. */ #define I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2) \ - (((getcaps2) & \ - I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK) \ - >> I3C_CCC_GETCAPS_GRPADDR_CAP_SHIFT) - -/** - * @brief Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - - * I3C 1.x Specification Version bit shift value. - */ -#define I3C_CCC_GETCAPS2_SPEC_VER_SHIFT 0 + FIELD_GET(I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK, (getcaps2)) /** * @brief Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - * I3C 1.x Specification Version bitmask. */ -#define I3C_CCC_GETCAPS2_SPEC_VER_MASK \ - (0x0FU << I3C_CCC_GETCAPS2_SPEC_VER_SHIFT) +#define I3C_CCC_GETCAPS2_SPEC_VER_MASK GENMASK(3U, 0U) /** * @brief Get Optional Feature Capabilities Byte 2 (GETCAPS) Format 1 - @@ -1065,9 +1063,7 @@ union i3c_ccc_getcaps { * @param getcaps2 GETCAPS2 value. */ #define I3C_CCC_GETCAPS2_SPEC_VER(getcaps2) \ - (((getcaps2) & \ - I3C_CCC_GETCAPS2_SPEC_VER_MASK) \ - >> I3C_CCC_GETCAPS_SPEC_VER_SHIFT) + FIELD_GET(I3C_CCC_GETCAPS2_SPEC_VER_MASK, (getcaps2)) /** * @brief Get Optional Feature Capabilities Byte 3 (GETCAPS) Format 1 - @@ -1183,12 +1179,8 @@ union i3c_ccc_getcaps { */ #define I3C_CCC_GETCAPS_CRCAPS2_DELAYED_CONTROLLER_HANDOFF BIT(3) -/** Get Capabilities (GETCAPS) - VTCAP1 - Virtual Target Type bit shift value. */ -#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT 0 - /** Get Capabilities (GETCAPS) - VTCAP1 - Virtual Target Type bitmask. */ -#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK \ - (0x07U << I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT) +#define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK GENMASK(2U, 0U) /** * @brief Get Capabilities (GETCAPS) - VTCAP1 - Virtual Target Type @@ -1199,9 +1191,7 @@ union i3c_ccc_getcaps { * @param vtcap1 VTCAP1 value. */ #define I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE(vtcap1) \ - (((vtcap1) & \ - I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK) \ - >> I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_SHIFT) + FIELD_GET(I3C_CCC_GETCAPS_VTCAP1_VITRUAL_TARGET_TYPE_MASK, (vtcap1)) /** * @brief Get Virtual Target Capabilities Byte 1 (GETCAPS) Format 2 - @@ -1215,12 +1205,8 @@ union i3c_ccc_getcaps { */ #define I3C_CCC_GETCAPS_VTCAP1_SHARED_PERIPH_DETECT BIT(5) -/** Get Capabilities (GETCAPS) - VTCAP2 - Interrupt Requests bit shift value. */ -#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT 0 - /** Get Capabilities (GETCAPS) - VTCAP2 - Interrupt Requests bitmask. */ -#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK \ - (0x03U << I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT) +#define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK GENMASK(1U, 0U) /** * @brief Get Capabilities (GETCAPS) - VTCAP2 - Interrupt Requests @@ -1231,9 +1217,7 @@ union i3c_ccc_getcaps { * @param vtcap2 VTCAP2 value. */ #define I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS(vtcap2) \ - (((vtcap2) & \ - I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK) \ - >> I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_SHIFT) + FIELD_GET(I3C_CCC_GETCAPS_VTCAP2_INTERRUPT_REQUESTS_MASK, (vtcap2)) /** * @brief Get Virtual Target Capabilities Byte 2 (GETCAPS) Format 2 - @@ -1241,12 +1225,8 @@ union i3c_ccc_getcaps { */ #define I3C_CCC_GETCAPS_VTCAP2_ADDRESS_REMAPPING BIT(2) -/** Get Capabilities (GETCAPS) - VTCAP2 - Bus Context and Condition bit shift value. */ -#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT 3 - /** Get Capabilities (GETCAPS) - VTCAP2 - Bus Context and Condition bitmask. */ -#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK \ - (0x03U << I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT) +#define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK GENMASK(4U, 3U) /** * @brief Get Capabilities (GETCAPS) - VTCAP2 - Bus Context and Condition @@ -1257,9 +1237,7 @@ union i3c_ccc_getcaps { * @param vtcap2 VTCAP2 value. */ #define I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND(vtcap2) \ - (((vtcap2) & \ - I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK) \ - >> I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_SHIFT) + FIELD_GET(I3C_CCC_GETCAPS_VTCAP2_BUS_CONTEXT_AND_COND_MASK, (vtcap2)) /** * @brief Enum for I3C Reset Action (RSTACT) Defining Byte Values. @@ -1279,8 +1257,107 @@ enum i3c_ccc_rstact_defining_byte { /** Virtual Target Detect. */ I3C_CCC_RSTACT_VIRTUAL_TARGET_DETECT = 0x04U, + + /** Return Time to Reset Peripheral */ + I3C_CCC_RSTACT_RETURN_TIME_TO_RESET_PERIPHERAL = 0x81U, + + /** Return Time to Reset Whole Target */ + I3C_CCC_RSTACT_RETURN_TIME_TO_WHOLE_TARGET = 0x82U, + + /** Return Time for Debug Network Adapter Reset */ + I3C_CCC_RSTACT_RETURN_TIME_FOR_DEBUG_NETWORK_ADAPTER_RESET = 0x83U, + + /** Return Virtual Target Indication */ + I3C_CCC_RSTACT_RETURN_VIRTUAL_TARGET_INDICATION = 0x84U, }; +/** + * @name Set Bus Context MIPI I3C Specification v1.Y Minor Version (SETBUSCON) + * @anchor I3C_CCC_SETBUSCON_I3C_SPEC + * + * - CONTEXT[7:6]: 2'b00 + * + * - CONTEXT[5]: I3C Specification Editorial Revision (within Minor Version) + * - 0: Version 1.Y.0 + * - 1: Version 1.Y.1 or greater + * + * - CONTEXT[4]: I3C Specification Family + * - 0: MIPI I3C Specification + * - 1: MIPI I3C Basic Specification + * + * - CONTEXT[3:0]: I3C Specification Minor Version (v1.Y) + * - 0: Illegal, do not use (see Note below) + * (It would encode v1.0, but SETBUSCON was not available in I3C Basic v1.0) + * - 1-15: Version 1.1 - Version 1.15 + * + * Examples: Bit[5] Bit[4] Bits[3:0] + * I3C Basic v1.1.0: 1’b0 || 1’b1 || 4’b0001 or 8’b00010001 + * I3C Basic v1.1.1: 1’b1 || 1’b1 || 4’b0001 or 8’b00110001 + * I3C Basic v1.2.0: 1’b0 || 1’b1 || 4’b0010 or 8’b00010010 + * + * @{ + */ + +/** I3C Specification Minor Version shift mask */ +#define I3C_CCC_SETBUSCON_I3C_SPEC_MINOR_VER_MASK GENMASK(3U, 0U) + +/** + * @brief I3C Specification Minor Version (v1.Y) + * + * Set the context bits for SETBUSCON + * + * @param y I3C Specification Minor Version Number + */ +#define I3C_CCC_SETBUSCON_I3C_SPEC_MINOR_VER(y) \ + FIELD_PREP(I3C_CCC_SETBUSCON_I3C_SPEC_MINOR_VER_MASK, (y)) + +/** MIPI I3C Specification */ +#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_SPEC 0 + +/** MIPI I3C Basic Specification */ +#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_BASIC_SPEC BIT(4) + +/** Version 1.Y.0 */ +#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_SPEC_EDITORIAL_1_Y_0 0 + +/** Version 1.Y.1 or greater */ +#define I3C_CCC_SETBUSCON_I3C_SPEC_I3C_SPEC_EDITORIAL_1_Y_1 BIT(5) + +/** @} */ + +/** + * @name Set Bus Context Other Standards Organizations (SETBUSCON) + * @anchor I3C_CCC_SETBUSCON_OTHER_STANDARDS + * + * @{ + */ + +/** + * @brief JEDEC Sideband + * + * JEDEC SideBand Bus device, compliant to JESD403 Specification v1.0 or later. + */ +#define I3C_CCC_SETBUSCON_OTHER_STANDARDS_JEDEC_SIDEBAND 128 + +/** + * @brief MCTP + * + * MCTP for system manageability (conforming to the content protocol defined in + * the MCTP I3C Transport Binding Specification, released by DMTF, version 1.0 + * or newer) + */ +#define I3C_CCC_SETBUSCON_OTHER_STANDARDS_MCTP 129 + +/** + * @brief ETSI + * + * ETSI for Secure Smart Platform Devices used for mobile networks authentication + * and other ETSI security functions in mobile ecosystem + */ +#define I3C_CCC_SETBUSCON_OTHER_STANDARDS_ETSI 130 + +/** @} */ + /** * @brief Test if I3C CCC payload is for broadcast. * @@ -1339,10 +1416,10 @@ int i3c_ccc_do_getpid(struct i3c_device_desc *target, struct i3c_ccc_getpid *pid); /** - * @brief Broadcast RSTACT to reset I3C Peripheral. + * @brief Broadcast RSTACT to reset I3C Peripheral (Format 1). * * Helper function to broadcast Target Reset Action (RSTACT) to - * all connected targets to Reset the I3C Peripheral Only (0x01). + * all connected targets. * * @param[in] controller Pointer to the controller device driver instance. * @param[in] action What reset action to perform. @@ -1352,6 +1429,60 @@ int i3c_ccc_do_getpid(struct i3c_device_desc *target, int i3c_ccc_do_rstact_all(const struct device *controller, enum i3c_ccc_rstact_defining_byte action); +/** + * @brief Single target RSTACT to reset I3C Peripheral. + * + * Helper function to do Target Reset Action (RSTACT) to + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] action What reset action to perform. + * @param[in] get True if a get, False if set + * @param[out] data Pointer to RSTACT payload received. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_rstact(const struct i3c_device_desc *target, + enum i3c_ccc_rstact_defining_byte action, + bool get, + uint8_t *data); + +/** + * @brief Single target RSTACT to reset I3C Peripheral (Format 2). + * + * Helper function to do Target Reset Action (RSTACT, format 2) to + * one target. This is a Direct Write. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] action What reset action to perform. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_rstact_fmt2(const struct i3c_device_desc *target, + enum i3c_ccc_rstact_defining_byte action) +{ + return i3c_ccc_do_rstact(target, action, false, NULL); +} + +/** + * @brief Single target RSTACT to reset I3C Peripheral (Format 3). + * + * Helper function to do Target Reset Action (RSTACT, format 3) to + * one target. This is a Direct Read. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] action What reset action to perform. + * @param[out] data Pointer to RSTACT payload received. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_rstact_fmt3(const struct i3c_device_desc *target, + enum i3c_ccc_rstact_defining_byte action, + uint8_t *data) +{ + return i3c_ccc_do_rstact(target, action, true, data); +} + /** * @brief Broadcast RSTDAA to reset dynamic addresses for all targets. * @@ -1373,10 +1504,12 @@ int i3c_ccc_do_rstdaa_all(const struct device *controller); * * @param[in] target Pointer to the target device descriptor where * the device is configured with a static address. + * @param[in] da Struct of the Dynamic address * * @return @see i3c_do_ccc */ -int i3c_ccc_do_setdasa(const struct i3c_device_desc *target); +int i3c_ccc_do_setdasa(const struct i3c_device_desc *target, + struct i3c_ccc_address da); /** * @brief Set New Dynamic Address for a target @@ -1387,7 +1520,7 @@ int i3c_ccc_do_setdasa(const struct i3c_device_desc *target); * * @param[in] target Pointer to the target device descriptor where * the device is configured with a static address. - * @param[in] new_da Pointer to the new_da struct. + * @param[in] new_da Struct of the Dynamic address * * @return @see i3c_do_ccc */ @@ -1424,6 +1557,147 @@ int i3c_ccc_do_events_all_set(const struct device *controller, int i3c_ccc_do_events_set(struct i3c_device_desc *target, bool enable, struct i3c_ccc_events *events); +/** + * @brief Direct ENTAS to set the Activity State. + * + * Helper function to broadcast Activity State Command on a single + * target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] as Activity State level + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_entas(const struct i3c_device_desc *target, uint8_t as); + +/** + * @brief Direct ENTAS0 + * + * Helper function to do ENTAS0 setting the minimum bus activity level to 1us + * on a single target. + * + * @param[in] target Pointer to the target device descriptor. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas0(const struct i3c_device_desc *target) +{ + return i3c_ccc_do_entas(target, 0); +} + +/** + * @brief Direct ENTAS1 + * + * Helper function to do ENTAS1 setting the minimum bus activity level to 100us + * on a single target. + * + * @param[in] target Pointer to the target device descriptor. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas1(const struct i3c_device_desc *target) +{ + return i3c_ccc_do_entas(target, 1); +} + +/** + * @brief Direct ENTAS2 + * + * Helper function to do ENTAS2 setting the minimum bus activity level to 2ms + * on a single target. + * + * @param[in] target Pointer to the target device descriptor. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas2(const struct i3c_device_desc *target) +{ + return i3c_ccc_do_entas(target, 2); +} + +/** + * @brief Direct ENTAS3 + * + * Helper function to do ENTAS3 setting the minimum bus activity level to 50ms + * on a single target. + * + * @param[in] target Pointer to the target device descriptor. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas3(const struct i3c_device_desc *target) +{ + return i3c_ccc_do_entas(target, 3); +} + +/** + * @brief Broadcast ENTAS to set the Activity State. + * + * Helper function to broadcast Activity State Command. + * + * @param[in] controller Pointer to the controller device driver instance. + * @param[in] as Activity State level + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_entas_all(const struct device *controller, uint8_t as); + +/** + * @brief Broadcast ENTAS0 + * + * Helper function to do ENTAS0 setting the minimum bus activity level to 1us + * + * @param[in] controller Pointer to the controller device driver instance. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas0_all(const struct device *controller) +{ + return i3c_ccc_do_entas_all(controller, 0); +} + +/** + * @brief Broadcast ENTAS1 + * + * Helper function to do ENTAS1 setting the minimum bus activity level to 100us + * + * @param[in] controller Pointer to the controller device driver instance. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas1_all(const struct device *controller) +{ + return i3c_ccc_do_entas_all(controller, 1); +} + +/** + * @brief Broadcast ENTAS2 + * + * Helper function to do ENTAS2 setting the minimum bus activity level to 2ms + * + * @param[in] controller Pointer to the controller device driver instance. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas2_all(const struct device *controller) +{ + return i3c_ccc_do_entas_all(controller, 2); +} + +/** + * @brief Broadcast ENTAS3 + * + * Helper function to do ENTAS3 setting the minimum bus activity level to 50ms + * + * @param[in] controller Pointer to the controller device driver instance. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_entas3_all(const struct device *controller) +{ + return i3c_ccc_do_entas_all(controller, 3); +} + /** * @brief Broadcast SETMWL to Set Maximum Write Length. * @@ -1517,6 +1791,19 @@ int i3c_ccc_do_setmrl(const struct i3c_device_desc *target, int i3c_ccc_do_getmrl(const struct i3c_device_desc *target, struct i3c_ccc_mrl *mrl); +/** + * @brief Broadcast ENTTM + * + * Helper function to do ENTTM (Enter Test Mode) to all devices + * + * @param[in] controller Pointer to the controller device driver instance. + * @param[in] defbyte Defining Byte for ENTTM. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_enttm(const struct device *controller, + enum i3c_ccc_enttm_defbyte defbyte); + /** * @brief Single target GETSTATUS to Get Target Status. * @@ -1637,6 +1924,201 @@ static inline int i3c_ccc_do_getcaps_fmt2(const struct i3c_device_desc *target, GETCAPS_FORMAT_2, defbyte); } +/** + * @brief Single target to Set Vendor / Standard Extension CCC + * + * Helper function to set Vendor / Standard Extension CCC of + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] id Vendor CCC ID. + * @param[in] payload Pointer to payload. + * @param[in] len Length of payload. 0 if no payload. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_setvendor(const struct i3c_device_desc *target, + uint8_t id, + uint8_t *payload, + size_t len); + +/** + * @brief Single target to Get Vendor / Standard Extension CCC + * + * Helper function to get Vendor / Standard Extension CCC of + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] id Vendor CCC ID. + * @param[out] payload Pointer to payload. + * @param[in] len Maximum Expected Length of the payload + * @param[out] num_xfer Length of the received payload + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_getvendor(const struct i3c_device_desc *target, + uint8_t id, + uint8_t *payload, + size_t len, + size_t *num_xfer); + +/** + * @brief Single target to Get Vendor / Standard Extension CCC + * with a defining byte + * + * Helper function to get Vendor / Standard Extension CCC of + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[in] id Vendor CCC ID. + * @param[in] defbyte Defining Byte + * @param[out] payload Pointer to payload. + * @param[in] len Maximum Expected Length of the payload + * @param[out] num_xfer Length of the received payload + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_getvendor_defbyte(const struct i3c_device_desc *target, + uint8_t id, + uint8_t defbyte, + uint8_t *payload, + size_t len, + size_t *num_xfer); + +/** + * @brief Broadcast Set Vendor / Standard Extension CCC + * + * Helper function to broadcast Vendor / Standard Extension CCC + * + * @param[in] controller Pointer to the controller device driver instance. + * @param[in] id Vendor CCC ID. + * @param[in] payload Pointer to payload. + * @param[in] len Length of payload. 0 if no payload. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_setvendor_all(const struct device *controller, + uint8_t id, + uint8_t *payload, + size_t len); + +/** + * @brief Broadcast SETAASA to set all target's dynamic address to their + * static address. + * + * Helper function to set dynamic addresses of all connected targets to + * their static address. + * + * @param[in] controller Pointer to the controller device driver instance. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_setaasa_all(const struct device *controller); + +/** + * @brief Single target GETMXDS to Get Max Data Speed. + * + * Helper function to do GETMXDS (Get Max Data Speed) of + * one target. + * + * This should only be supported if Max Data Speed Limit Bit of + * the BCR is set + * + * @param[in] target Pointer to the target device descriptor. + * @param[out] caps Pointer to GETMXDS payload. + * @param[in] fmt Which GETMXDS to use. + * @param[in] defbyte Defining Byte if using format 3. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_getmxds(const struct i3c_device_desc *target, + union i3c_ccc_getmxds *caps, + enum i3c_ccc_getmxds_fmt fmt, + enum i3c_ccc_getmxds_defbyte defbyte); + +/** + * @brief Single target GETMXDS to Get Max Data Speed (Format 1). + * + * Helper function to do GETMXDS (Get Max Data Speed, format 1) of + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[out] caps Pointer to GETMXDS payload. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_getmxds_fmt1(const struct i3c_device_desc *target, + union i3c_ccc_getmxds *caps) +{ + return i3c_ccc_do_getmxds(target, caps, + GETMXDS_FORMAT_1, + GETMXDS_FORMAT_3_INVALID); +} + +/** + * @brief Single target GETMXDS to Get Max Data Speed (Format 2). + * + * Helper function to do GETMXDS (Get Max Data Speed, format 2) of + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[out] caps Pointer to GETMXDS payload. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_getmxds_fmt2(const struct i3c_device_desc *target, + union i3c_ccc_getmxds *caps) +{ + return i3c_ccc_do_getmxds(target, caps, + GETMXDS_FORMAT_2, + GETMXDS_FORMAT_3_INVALID); +} + +/** + * @brief Single target GETMXDS to Get Max Data Speed (Format 3). + * + * Helper function to do GETMXDS (Get Max Data Speed, format 3) of + * one target. + * + * @param[in] target Pointer to the target device descriptor. + * @param[out] caps Pointer to GETMXDS payload. + * @param[in] defbyte Defining Byte for GETMXDS format 3. + * + * @return @see i3c_do_ccc + */ +static inline int i3c_ccc_do_getmxds_fmt3(const struct i3c_device_desc *target, + union i3c_ccc_getmxds *caps, + enum i3c_ccc_getmxds_defbyte defbyte) +{ + return i3c_ccc_do_getmxds(target, caps, + GETMXDS_FORMAT_3, defbyte); +} + +/** + * @brief Broadcast DEFTGTS + * + * @param[in] controller Pointer to the controller device driver instance. + * @param[in] deftgts Pointer to the deftgts payload. + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_deftgts_all(const struct device *controller, + struct i3c_ccc_deftgts *deftgts); + +/** + * @brief Broadcast SETBUSCON to set the bus context + * + * Helper function to set the bus context of all connected targets. + * + * @param[in] controller Pointer to the controller device driver instance. + * @param[in] context Pointer to context byte values + * @param[in] length Length of the context buffer + * + * @return @see i3c_do_ccc + */ +int i3c_ccc_do_setbuscon(const struct device *controller, + uint8_t *context, uint16_t length); + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/devicetree.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/devicetree.h index 3b53a853..803f17d5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/devicetree.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/devicetree.h @@ -14,9 +14,10 @@ * @{ */ +#include + #include -#include -#include +#include #include #ifdef __cplusplus @@ -42,7 +43,9 @@ extern "C" { * @brief Structure initializer for i3c_device_id from devicetree instance * * This is equivalent to - * I3C_DEVICE_ID_DT(DT_DRV_INST(inst)). + * @code{.c} + * I3C_DEVICE_ID_DT(DT_DRV_INST(inst)) + * @endcode * * @param inst Devicetree instance number */ @@ -68,13 +71,17 @@ extern "C" { | DT_PROP_BY_IDX(node_id, reg, 2), \ .init_dynamic_addr = \ DT_PROP_OR(node_id, assigned_address, 0), \ + .supports_setaasa = DT_PROP(node_id, supports_setaasa), \ }, /** * @brief Structure initializer for i3c_device_desc from devicetree instance * * This is equivalent to - * I3C_DEVICE_DESC_DT(DT_DRV_INST(inst)). + * + * @code{.c} + * I3C_DEVICE_DESC_DT(DT_DRV_INST(inst)) + * @endcode * * @param inst Devicetree instance number */ @@ -84,7 +91,7 @@ extern "C" { /** * @brief Structure initializer for i3c_device_desc from devicetree * - * This is mainly used by I3C_DEVICE_ARRAY_DT() to only + * This is mainly used by I3C_DEVICE_ARRAY_DT() to only * create a struct if and only if it is an I3C device. */ #define I3C_DEVICE_DESC_DT_FILTERED(node_id) \ @@ -110,7 +117,9 @@ extern "C" { * @brief Array initializer for a list of i3c_device_desc from devicetree instance * * This is equivalent to - * I3C_DEVICE_ARRAY_DT(DT_DRV_INST(inst)). + * @code{.c} + * I3C_DEVICE_ARRAY_DT(DT_DRV_INST(inst)) + * @endcode * * @param inst Devicetree instance number of the I3C controller */ @@ -126,7 +135,7 @@ extern "C" { * * @param init_fn Name of the init function of the driver. * - * @param pm PM device resources reference (NULL if device does not use PM). + * @param pm PM device resources reference (`NULL` if device does not use PM). * * @param data Pointer to the device's private data. * @@ -151,7 +160,7 @@ extern "C" { * @brief Like I3C_TARGET_DT_DEFINE() for an instance of a DT_DRV_COMPAT compatible * * @param inst instance number. This is replaced by - * DT_DRV_COMPAT(inst) in the call to I3C_TARGET_DT_DEFINE(). + * `DT_DRV_COMPAT(inst)` in the call to I3C_TARGET_DT_DEFINE(). * * @param ... other parameters as expected by I3C_TARGET_DT_DEFINE(). */ @@ -161,9 +170,8 @@ extern "C" { /** * @brief Structure initializer for i3c_i2c_device_desc from devicetree * - * This helper macro expands to a static initializer for a struct - * i3c_i2c_device_desc by reading the relevant bus and device data - * from the devicetree. + * This helper macro expands to a static initializer for a i3c_i2c_device_desc + * by reading the relevant bus and device data from the devicetree. * * @param node_id Devicetree node identifier for the I3C device whose * struct i3c_i2c_device_desc to create an initializer for @@ -179,7 +187,9 @@ extern "C" { * @brief Structure initializer for i3c_i2c_device_desc from devicetree instance * * This is equivalent to - * I3C_I2C_DEVICE_DESC_DT(DT_DRV_INST(inst)). + * @code{.c} + * I3C_I2C_DEVICE_DESC_DT(DT_DRV_INST(inst)) + * @endcode * * @param inst Devicetree instance number */ @@ -190,7 +200,7 @@ extern "C" { /** * @brief Structure initializer for i3c_i2c_device_desc from devicetree * - * This is mainly used by I3C_I2C_DEVICE_ARRAY_DT() to only + * This is mainly used by I3C_I2C_DEVICE_ARRAY_DT() to only * create a struct if and only if it is an I2C device. */ #define I3C_I2C_DEVICE_DESC_DT_FILTERED(node_id) \ @@ -216,7 +226,9 @@ extern "C" { * @brief Array initializer for a list of i3c_i2c_device_desc from devicetree instance * * This is equivalent to - * I3C_I2C_DEVICE_ARRAY_DT(DT_DRV_INST(inst)). + * @code{.c} + * I3C_I2C_DEVICE_ARRAY_DT(DT_DRV_INST(inst)) + * @endcode * * @param inst Devicetree instance number of the I3C controller */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/hdr_ddr.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/hdr_ddr.h new file mode 100644 index 00000000..6aaff610 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/hdr_ddr.h @@ -0,0 +1,131 @@ +/* + * Copyright 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_HDR_DDR_H_ +#define ZEPHYR_INCLUDE_DRIVERS_I3C_HDR_DDR_H_ + +/** + * @brief I3C HDR DDR API + * @defgroup i3c_hdr_ddr I3C HDR DDR API + * @ingroup i3c_interface + * @{ + */ + +#include +#include +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Write a set amount of data to an I3C target device with HDR DDR. + * + * This routine writes a set amount of data synchronously. + * + * @param target I3C target device descriptor. + * @param cmd 7-bit command code + * @param buf Memory pool from which the data is transferred. + * @param num_bytes Number of bytes to write. + * + * @retval 0 If successful. + * @retval -EBUSY Bus is busy. + * @retval -EIO General input / output error. + */ +static inline int i3c_hdr_ddr_write(struct i3c_device_desc *target, uint8_t cmd, + uint8_t *buf, uint32_t num_bytes) +{ + struct i3c_msg msg; + + msg.buf = buf; + msg.len = num_bytes; + msg.flags = I3C_MSG_WRITE | I3C_MSG_STOP | I3C_MSG_HDR; + msg.hdr_mode = I3C_MSG_HDR_DDR; + msg.hdr_cmd_code = cmd; + + return i3c_transfer(target, &msg, 1); +} + +/** + * @brief Read a set amount of data from an I3C target device with HDR DDR. + * + * This routine reads a set amount of data synchronously. + * + * @param target I3C target device descriptor. + * @param cmd 7-bit command code + * @param buf Memory pool that stores the retrieved data. + * @param num_bytes Number of bytes to read. + * + * @retval 0 If successful. + * @retval -EBUSY Bus is busy. + * @retval -EIO General input / output error. + */ +static inline int i3c_hdr_ddr_read(struct i3c_device_desc *target, uint8_t cmd, + uint8_t *buf, uint32_t num_bytes) +{ + struct i3c_msg msg; + + msg.buf = buf; + msg.len = num_bytes; + msg.flags = I3C_MSG_STOP | I3C_MSG_HDR; + msg.hdr_mode = I3C_MSG_HDR_DDR; + msg.hdr_cmd_code = cmd; + + return i3c_transfer(target, &msg, 1); +} + +/** + * @brief Write then read data from an I3C target device with HDR DDR. + * + * This supports the common operation "this is what I want", "now give + * it to me" transaction pair through a combined write-then-read bus + * transaction. + * + * @param target I3C target device descriptor. + * @param write_buf Pointer to the data to be written + * @param num_write Number of bytes to write + * @param write_cmd 7-bit command code for write + * @param read_buf Pointer to storage for read data + * @param num_read Number of bytes to read + * @param read_cmd 7-bit command code for read + * + * @retval 0 if successful + * @retval -EBUSY Bus is busy. + * @retval -EIO General input / output error. + */ +static inline int i3c_hdr_ddr_write_read(struct i3c_device_desc *target, + const void *write_buf, size_t num_write, uint8_t read_cmd, + void *read_buf, size_t num_read, uint8_t write_cmd) +{ + struct i3c_msg msg[2]; + + msg[0].buf = (uint8_t *)write_buf; + msg[0].len = num_write; + msg[0].flags = I3C_MSG_WRITE | I3C_MSG_HDR; + msg[0].hdr_mode = I3C_MSG_HDR_DDR; + msg[0].hdr_cmd_code = write_cmd; + + msg[1].buf = (uint8_t *)read_buf; + msg[1].len = num_read; + msg[1].flags = I3C_MSG_RESTART | I3C_MSG_READ | I3C_MSG_HDR | I3C_MSG_STOP; + msg[1].hdr_mode = I3C_MSG_HDR_DDR; + msg[1].hdr_cmd_code = read_cmd; + + return i3c_transfer(target, msg, 2); +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_DRIVERS_I3C_HDR_DDR_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ibi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ibi.h index 2483b5de..6020609b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ibi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/ibi.h @@ -14,10 +14,11 @@ * @{ */ +#include + #include #include -#include -#include +#include #ifndef CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE #define CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE 0 @@ -86,13 +87,7 @@ struct i3c_ibi_payload { * @brief Node about a queued IBI. */ struct i3c_ibi_work { - /** - * @cond INTERNAL_HIDDEN - * - * Used for keeping track of work in a queue. - */ sys_snode_t node; - /** @endcond */ /** * k_work struct. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/target_device.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/target_device.h index 1f4df840..7d85e03b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/target_device.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/i3c/target_device.h @@ -14,10 +14,12 @@ * @{ */ +#include +#include +#include + #include -#include -#include -#include +#include #ifdef __cplusplus extern "C" { @@ -39,7 +41,15 @@ struct i3c_config_target { bool enable; /** - * I3C target address. + * I3C target dynamic address. + * + * Used when operates as secondary controller + * or as a target device. + */ + uint8_t dynamic_addr; + + /** + * I3C target static address. * * Used used when operates as secondary controller * or as a target device. @@ -90,7 +100,6 @@ struct i3c_config_target { * reference to i3c_target_register(). */ struct i3c_target_config { - /** Private, do not modify */ sys_snode_t node; /** @@ -193,6 +202,49 @@ struct i3c_target_callbacks { int (*read_processed_cb)(struct i3c_target_config *config, uint8_t *val); +#ifdef CONFIG_I3C_TARGET_BUFFER_MODE + /** @brief Function called when a write to the device is completed. + * + * This function is invoked by the controller when it completes + * reception of data from the source buffer to the destination + * buffer in an ongoing write operation to the device. + * + * @param config Configuration structure associated with the + * device to which the operation is addressed. + * + * @param ptr pointer to the buffer that contains the data to be transferred. + * + * @param len the length of the data to be transferred. + */ + void (*buf_write_received_cb)(struct i3c_target_config *config, uint8_t *ptr, uint32_t len); + + /** @brief Function called when a read from the device is initiated. + * + * This function is invoked by the controller when the bus is ready to + * provide additional data by buffer for a read operation from the address + * associated with the device. + * + * The value returned in @p **ptr and @p *len will be transmitted. A success + * return shall cause the controller to react to additional read operations. + * An error return shall cause the controller to ignore bus operations until + * a new start condition is received. + * + * @param config the configuration structure associated with the + * device to which the operation is addressed. + * + * @param ptr pointer to storage for the address of data buffer to return + * for the read request. + * + * @param len pointer to storage for the length of the data to be transferred + * for the read request. + * + * @param hdr_mode HDR mode + * + * @return 0 if data has been provided, or a negative error code. + */ + int (*buf_read_requested_cb)(struct i3c_target_config *config, uint8_t **ptr, uint32_t *len, + uint8_t *hdr_mode); +#endif /** * @brief Function called when a stop condition is observed after a * start condition addressed to a particular device. @@ -233,14 +285,15 @@ __subsystem struct i3c_target_driver_api { * driver configured in target mode. * @param buf Pointer to the buffer * @param len Length of the buffer + * @param hdr_mode HDR mode see @c I3C_MSG_HDR_MODE* * * @retval Total number of bytes written - * @retval -ENOTSUP Not in Target Mode + * @retval -ENOTSUP Not in Target Mode or HDR Mode not supported * @retval -ENOSPC No space in Tx FIFO * @retval -ENOSYS If target mode is not implemented */ static inline int i3c_target_tx_write(const struct device *dev, - uint8_t *buf, uint16_t len) + uint8_t *buf, uint16_t len, uint8_t hdr_mode) { const struct i3c_driver_api *api = (const struct i3c_driver_api *)dev->api; @@ -249,7 +302,7 @@ static inline int i3c_target_tx_write(const struct device *dev, return -ENOSYS; } - return api->target_tx_write(dev, buf, len); + return api->target_tx_write(dev, buf, len, hdr_mode); } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gic.h index f8d10ff8..ab6aeffe 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gic.h @@ -302,6 +302,13 @@ bool arm_gic_irq_is_enabled(unsigned int irq); */ bool arm_gic_irq_is_pending(unsigned int irq); +/** + * @brief Set interrupt as pending + * + * @param irq interrupt ID + */ +void arm_gic_irq_set_pending(unsigned int irq); + /** * @brief Clear the pending irq * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gpio_intc_stm32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gpio_intc_stm32.h new file mode 100644 index 00000000..9f6cd308 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/gpio_intc_stm32.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2016 Open-RnD Sp. z o.o. + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief GPIO interrupt controller API for STM32 MCUs + * + * This API is used to interact with the GPIO interrupt controller + * of STM32 microcontrollers. + */ + +#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_GPIO_INTC_STM32_H_ +#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_GPIO_INTC_STM32_H_ + +#include +#include + +/** + * @brief Opaque type representing a GPIO interrupt line + */ +typedef uint32_t stm32_gpio_irq_line_t; + +/** + * @brief Get the GPIO interrupt line value corresponding + * to specified @p pin of GPIO port @p port + */ +stm32_gpio_irq_line_t stm32_gpio_intc_get_pin_irq_line(uint32_t port, gpio_pin_t pin); + +/** + * @brief Enable GPIO interrupts for specified line + * + * @param line GPIO interrupt line + */ +void stm32_gpio_intc_enable_line(stm32_gpio_irq_line_t line); + +/** + * @brief Disable GPIO interrupts for specified line + * + * @param line GPIO interrupt line + */ +void stm32_gpio_intc_disable_line(stm32_gpio_irq_line_t line); + +/** + * @brief GPIO interrupt trigger flags + */ +enum stm32_gpio_irq_trigger { + /* No trigger */ + STM32_GPIO_IRQ_TRIG_NONE = 0x0, + /* Trigger on rising edge */ + STM32_GPIO_IRQ_TRIG_RISING = 0x1, + /* Trigger on falling edge */ + STM32_GPIO_IRQ_TRIG_FALLING = 0x2, + /* Trigger on both rising and falling edge */ + STM32_GPIO_IRQ_TRIG_BOTH = 0x3, + /* Trigger on high level */ + STM32_GPIO_IRQ_TRIG_HIGH_LEVEL = 0x4, + /* Trigger on low level */ + STM32_GPIO_IRQ_TRIG_LOW_LEVEL = 0x5 +}; + +/** + * @brief Select trigger for interrupt on specified GPIO line + * + * @param line GPIO interrupt line + * @param trg Interrupt trigger (see @ref stm32_gpio_irq_trigger) + */ +void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t trg); + +/** + * @brief GPIO interrupt callback function signature + * + * @param pin GPIO pin on which interrupt occurred + * @param user @p data provided to @ref stm32_gpio_intc_set_irq_callback + * + * @note This callback is invoked in ISR context. + */ +typedef void (*stm32_gpio_irq_cb_t)(gpio_port_pins_t pin, void *user); + +/** + * @brief Set callback invoked when an interrupt occurs on specified GPIO line + * + * @param line GPIO interrupt line + * @param cb Interrupt callback function + * @param user Custom user data for usage by the callback + * @returns 0 on success, -EBUSY if a callback is already set for @p line + */ +int stm32_gpio_intc_set_irq_callback(stm32_gpio_irq_line_t line, + stm32_gpio_irq_cb_t cb, void *user); + +/** + * @brief Removes the interrupt callback of specified EXTI line + * + * @param line EXTI interrupt line + */ +void stm32_gpio_intc_remove_irq_callback(stm32_gpio_irq_line_t line); + +/** Hardware-specific API extensions */ + +#if defined(CONFIG_EXTI_STM32) /* EXTI-specific extensions */ +/** + * @brief Set which GPIO port triggers events on specified EXTI line. + * + * @param line EXTI line number (= pin number) + * @param port GPIO port number (STM32_PORTA, STM32_PORTB, ...) + */ +void stm32_exti_set_line_src_port(gpio_pin_t line, uint32_t port); + +/** + * @brief Get port which is triggering events on specified EXTI line. + * + * @param line EXTI line number (= pin number) + * @returns GPIO port number (STM32_PORTA, STM32_PORTB, ...) + */ +uint32_t stm32_exti_get_line_src_port(gpio_pin_t line); +#endif /* CONFIG_EXTI_STM32 */ + +#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_GPIO_INTC_STM32_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h index 7f96be34..ee161e5e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_eirq_nxp_s32.h @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,57 +12,67 @@ #ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_EIRQ_NXP_S32_H_ #define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_EIRQ_NXP_S32_H_ -#include - -/* Wrapper callback for EIRQ line */ +/** NXP SIUL2 EIRQ callback */ typedef void (*eirq_nxp_s32_callback_t)(uint8_t pin, void *arg); /** - * @brief Unset EIRQ callback for line + * @brief NXP SIUL2 EIRQ pin activation type + */ +enum eirq_nxp_s32_trigger { + /** Interrupt triggered on rising edge */ + EIRQ_NXP_S32_RISING_EDGE, + /** Interrupt triggered on falling edge */ + EIRQ_NXP_S32_FALLING_EDGE, + /** Interrupt triggered on either edge */ + EIRQ_NXP_S32_BOTH_EDGES, +}; + +/** + * @brief Unset interrupt callback * - * @param dev EIRQ device - * @param line EIRQ line + * @param dev SIUL2 EIRQ device + * @param irq interrupt number */ -void eirq_nxp_s32_unset_callback(const struct device *dev, uint8_t line); +void eirq_nxp_s32_unset_callback(const struct device *dev, uint8_t irq); /** - * @brief Set EIRQ callback for line + * @brief Set callback for an interrupt associated with a given pin * - * @param dev EIRQ device - * @param line EIRQ line - * @param cb Callback - * @param pin GPIO pin - * @param arg Callback data + * @param dev SIUL2 EIRQ device + * @param irq interrupt number + * @param pin GPIO pin associated with the interrupt + * @param cb callback to install + * @param arg user data to include in callback * - * @retval 0 on SUCCESS - * @retval -EBUSY if callback for the line is already set + * @retval 0 on success + * @retval -EBUSY if callback for the interrupt is already set */ -int eirq_nxp_s32_set_callback(const struct device *dev, uint8_t line, - eirq_nxp_s32_callback_t cb, uint8_t pin, void *arg); +int eirq_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin, + eirq_nxp_s32_callback_t cb, void *arg); /** - * @brief Set edge event and enable interrupt for EIRQ line + * @brief Enable interrupt on a given trigger event * - * @param dev EIRQ device - * @param line EIRQ line - * @param edge_type Type of edge event + * @param dev SIUL2 EIRQ device + * @param irq interrupt number + * @param trigger trigger event */ -void eirq_nxp_s32_enable_interrupt(const struct device *dev, uint8_t line, - Siul2_Icu_Ip_EdgeType edge_type); +void eirq_nxp_s32_enable_interrupt(const struct device *dev, uint8_t irq, + enum eirq_nxp_s32_trigger trigger); /** - * @brief Disable interrupt for EIRQ line + * @brief Disable interrupt * - * @param dev EIRQ device - * @param line EIRQ line + * @param dev SIUL2 EIRQ device + * @param irq interrupt number */ -void eirq_nxp_s32_disable_interrupt(const struct device *dev, uint8_t line); +void eirq_nxp_s32_disable_interrupt(const struct device *dev, uint8_t irq); /** - * @brief Get pending interrupt for EIRQ device + * @brief Get pending interrupts * - * @param dev EIRQ device - * @return A mask contains pending flags + * @param dev SIUL2 EIRQ device + * @return A bitmask containing pending pending interrupts */ uint32_t eirq_nxp_s32_get_pending(const struct device *dev); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32.h index c1e86068..5b5ce8d9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DRIVERS_ESP_INTR_ALLOC_H__ -#define ZEPHYR_INCLUDE_DRIVERS_ESP_INTR_ALLOC_H__ +#ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32_H_ +#define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32_H_ #include #include @@ -44,6 +44,17 @@ ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ ESP_INTR_FLAG_NMI) +/* + * Get the interrupt flags from the supplied priority. + */ +#define ESP_PRIO_TO_FLAGS(priority) \ + ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0) + +/* + * Check interrupt flags from input and filter unallowed values. + */ +#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED) + /* * The esp_intr_alloc* functions can allocate an int for all *_INTR_SOURCE int sources that * are routed through the interrupt mux. Apart from these sources, each core also has some internal @@ -295,10 +306,9 @@ int esp_intr_set_in_iram(struct intr_handle_data_t *handle, bool is_in_iram); */ void esp_intr_noniram_disable(void); - /** * @brief Re-enable interrupts disabled by esp_intr_noniram_disable */ void esp_intr_noniram_enable(void); -#endif +#endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h index 775a2e36..a30dc16e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DRIVERS_ESP_INTR_ALLOC_H__ -#define ZEPHYR_INCLUDE_DRIVERS_ESP_INTR_ALLOC_H__ +#ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ +#define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ #include #include @@ -40,6 +40,18 @@ ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \ ESP_INTR_FLAG_NMI) +/* + * Get the interrupt flags from the supplied priority. + */ +#define ESP_PRIO_TO_FLAGS(priority) \ + ((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0) + +/* + * Check interrupt flags from input and filter unallowed values. + */ +#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED) + + /* Function prototype for interrupt handler function */ typedef void (*isr_handler_t)(const void *arg); @@ -106,4 +118,4 @@ int esp_intr_enable(int source); */ uint32_t esp_intr_get_enabled_intmask(int status_mask_number); -#endif +#endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h index c87a783e..9c4e9511 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intc_wkpu_nxp_s32.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,57 +11,67 @@ #ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_WKPU_NXP_S32_H_ #define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_WKPU_NXP_S32_H_ -#include - -/* Wrapper callback for WKPU line */ +/** NXP WKPU callback */ typedef void (*wkpu_nxp_s32_callback_t)(uint8_t pin, void *arg); +/** + * @brief NXP WKPU pin activation type + */ +enum wkpu_nxp_s32_trigger { + /** Interrupt triggered on rising edge */ + WKPU_NXP_S32_RISING_EDGE, + /** Interrupt triggered on falling edge */ + WKPU_NXP_S32_FALLING_EDGE, + /** Interrupt triggered on either edge */ + WKPU_NXP_S32_BOTH_EDGES, +}; + /** * @brief Unset WKPU callback for line * * @param dev WKPU device - * @param line WKPU line + * @param irq WKPU interrupt number */ -void wkpu_nxp_s32_unset_callback(const struct device *dev, uint8_t line); +void wkpu_nxp_s32_unset_callback(const struct device *dev, uint8_t irq); /** * @brief Set WKPU callback for line * * @param dev WKPU device - * @param line WKPU line - * @param cb Callback + * @param irq WKPU interrupt number * @param pin GPIO pin + * @param cb Callback * @param arg Callback data * * @retval 0 on SUCCESS * @retval -EBUSY if callback for the line is already set */ -int wkpu_nxp_s32_set_callback(const struct device *dev, uint8_t line, - wkpu_nxp_s32_callback_t cb, uint8_t pin, void *arg); +int wkpu_nxp_s32_set_callback(const struct device *dev, uint8_t irq, uint8_t pin, + wkpu_nxp_s32_callback_t cb, void *arg); /** * @brief Set edge event and enable interrupt for WKPU line * * @param dev WKPU device - * @param line WKPU line - * @param edge_type Type of edge event + * @param irq WKPU interrupt number + * @param trigger pin activation trigger */ -void wkpu_nxp_s32_enable_interrupt(const struct device *dev, uint8_t line, - Wkpu_Ip_EdgeType edge_type); +void wkpu_nxp_s32_enable_interrupt(const struct device *dev, uint8_t irq, + enum wkpu_nxp_s32_trigger trigger); /** * @brief Disable interrupt for WKPU line * * @param dev WKPU device - * @param line WKPU line + * @param irq WKPU interrupt number */ -void wkpu_nxp_s32_disable_interrupt(const struct device *dev, uint8_t line); +void wkpu_nxp_s32_disable_interrupt(const struct device *dev, uint8_t irq); /** * @brief Get pending interrupt for WKPU device * * @param dev WKPU device - * @return A mask contains pending flags + * @return A bitmask containing pending interrupts */ uint64_t wkpu_nxp_s32_get_pending(const struct device *dev); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intel_vtd.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intel_vtd.h index b91834c7..ecf86813 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intel_vtd.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/intel_vtd.h @@ -215,7 +215,7 @@ static inline void vtd_set_irte_msi(const struct device *dev, const struct vtd_driver_api *api = (const struct vtd_driver_api *)dev->api; - return api->set_irte_msi(dev, irte_idx, msi); + api->set_irte_msi(dev, irte_idx, msi); } static inline bool vtd_irte_is_msi(const struct device *dev, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_clic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_clic.h index 1e5fe78d..633edbf3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_clic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_clic.h @@ -43,4 +43,11 @@ int riscv_clic_irq_is_enabled(uint32_t irq); */ void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags); +/** + * @brief Set vector mode of interrupt + * + * @param irq interrupt ID + */ +void riscv_clic_irq_vector_set(uint32_t irq); + #endif /* ZEPHYR_INCLUDE_DRIVERS_RISCV_CLIC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_plic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_plic.h index 22c57a4b..ff273d9f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_plic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/interrupt_controller/riscv_plic.h @@ -44,9 +44,28 @@ int riscv_plic_irq_is_enabled(uint32_t irq); */ void riscv_plic_set_priority(uint32_t irq, uint32_t prio); +/** + * @brief Set IRQ affinity. + * + * @param irq IRQ line. + * @param cpumask CPU bit mask. + * + * @return 0 if success, negative errno value otherwise + */ +int riscv_plic_irq_set_affinity(uint32_t irq, uint32_t cpumask); + +/** + * @brief Set interrupt as pending + * + * @param irq Multi-level encoded interrupt ID + */ +void riscv_plic_irq_set_pending(uint32_t irq); + /** * @brief Get active interrupt ID * + * @note Should be called with interrupt locked + * * @return Returns the ID of an active interrupt */ unsigned int riscv_plic_get_irq(void); @@ -54,6 +73,8 @@ unsigned int riscv_plic_get_irq(void); /** * @brief Get active interrupt controller device * + * @note Should be called with interrupt locked + * * @return Returns device pointer of the active interrupt device */ const struct device *riscv_plic_get_dev(void); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/kscan.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/kscan.h index f2f87c7c..f12e2809 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/kscan.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/kscan.h @@ -30,11 +30,13 @@ extern "C" { * @defgroup kscan_interface Keyboard Scan Driver APIs * @since 2.1 * @version 1.0.0 + * @deprecated * @ingroup io_interfaces * @{ */ /** + * @deprecated * @brief Keyboard scan callback called when user press/release * a key on a matrix keyboard. * @@ -48,6 +50,7 @@ typedef void (*kscan_callback_t)(const struct device *dev, uint32_t row, bool pressed); /** + * @deprecated * @cond INTERNAL_HIDDEN * * Keyboard scan driver API definition and system call entry points. @@ -69,6 +72,7 @@ __subsystem struct kscan_driver_api { */ /** + * @deprecated * @brief Configure a Keyboard scan instance. * * @param dev Pointer to the device structure for the driver instance. @@ -90,6 +94,7 @@ static inline int z_impl_kscan_config(const struct device *dev, return api->config(dev, callback); } /** + * @deprecated * @brief Enables callback. * @param dev Pointer to the device structure for the driver instance. * @@ -111,6 +116,7 @@ static inline int z_impl_kscan_enable_callback(const struct device *dev) } /** + * @deprecated * @brief Disables callback. * @param dev Pointer to the device structure for the driver instance. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/led.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/led.h index fbb66b5f..dc0bd133 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/led.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/led.h @@ -330,6 +330,135 @@ static inline int z_impl_led_off(const struct device *dev, uint32_t led) return api->off(dev, led); } +/* + * LED DT helpers. + */ + +/** + * @brief Container for an LED information specified in devicetree. + * + * This type contains a pointer to and LED device and an LED index. + * + * @see LED_DT_SPEC_GET + * @see LED_DT_SPEC_GET_OR + */ +struct led_dt_spec { + /** LED device instance. */ + const struct device *dev; + /** Index of the LED on the controller. */ + uint32_t index; +}; + +/** + * @brief Set LED brightness from a led_dt_spec. + * + * @param spec LED device specification from devicetree. + * @param value Brightness value to set in percent. + * @return 0 on success, negative on error. + * + * @see led_set_brightness() + */ +static inline int led_set_brightness_dt(const struct led_dt_spec *spec, + uint8_t value) +{ + return led_set_brightness(spec->dev, spec->index, value); +} + +/** + * @brief Turn on an LED from a struct led_dt_spec. + * + * @param spec LED device specification from devicetree. + * @return 0 on success, negative on error. + * + * @see led_on() + */ +static inline int led_on_dt(const struct led_dt_spec *spec) +{ + return led_on(spec->dev, spec->index); +} + +/** + * @brief Turn off an LED from a struct led_dt_spec. + * + * @param spec LED device specification from devicetree. + * @return 0 on success, negative on error. + * + * @see led_off() + */ +static inline int led_off_dt(const struct led_dt_spec *spec) +{ + return led_off(spec->dev, spec->index); +} + +/** + * @brief Validate that the LED device is ready. + * + * @param spec LED specification from devicetree. + * + * @retval true If the LED device is ready for use. + * @retval false If the LED device is not ready for use. + */ +static inline bool led_is_ready_dt(const struct led_dt_spec *spec) +{ + return device_is_ready(spec->dev); +} + +/** + * @brief Static initializer for a struct led_dt_spec + * + * This returns a static initializer for a struct led_dt_spec given a devicetree + * node identifier. + * + * Example devicetree fragment: + * + * @code{.dts} + * leds { + * compatible = "gpio-leds"; + * led0: led_0 { + * ... + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * const struct led_dt_spec spec = LED_DT_SPEC_GET(DT_NODELABEL(led0)); + * + * // Initializes 'spec' to: + * // { + * // .dev = DEVICE_DT_GET(DT_PARENT(led0)), + * // .index = 0, + * // } + * @endcode + * + * The device (dev) must still be checked for readiness, e.g. using + * device_is_ready(). + * + * @param node_id Devicetree node identifier. + * + * @return Static initializer for a struct led_dt_spec for the property. + */ +#define LED_DT_SPEC_GET(node_id) \ + { \ + .dev = DEVICE_DT_GET(DT_PARENT(node_id)), \ + .index = DT_NODE_CHILD_IDX(node_id), \ + } + +/** + * @brief Like LED_DT_SPEC_GET(), with a fallback value if the node does not exist. + * + * @param node_id Devicetree node identifier. + * + * @return Static initializer for a struct led_dt_spec for the property. + * + * @see LED_DT_SPEC_GET + */ +#define LED_DT_SPEC_GET_OR(node_id, default_value) \ + COND_CODE_1(DT_NODE_EXISTS(node_id), \ + (LED_DT_SPEC_GET(node_id)), \ + (default_value)) + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mbox.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mbox.h index 3f8ffc65..1945879b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mbox.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mbox.h @@ -201,7 +201,7 @@ typedef int (*mbox_register_callback_t)(const struct device *dev, * * @param dev MBOX device instance * @param channel_id Channel ID - * @param enables Set to 0 to disable and to nonzero to enable. + * @param enabled Set to 0 to disable and to nonzero to enable. * * @return See return values for mbox_set_enabled() * @see mbox_set_enabled() diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/ad559x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/ad559x.h index 095cdd3e..60c86431 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/ad559x.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/ad559x.h @@ -13,6 +13,7 @@ extern "C" { #include #define AD559X_REG_SEQ_ADC 0x02U +#define AD559X_REG_GEN_CTRL 0x03U #define AD559X_REG_ADC_CONFIG 0x04U #define AD559X_REG_LDAC_EN 0x05U #define AD559X_REG_GPIO_PULLDOWN 0x06U @@ -21,8 +22,11 @@ extern "C" { #define AD559X_REG_GPIO_SET 0x09U #define AD559X_REG_GPIO_INPUT_EN 0x0AU #define AD559X_REG_PD_REF_CTRL 0x0BU +#define AD559X_REG_IO_TS_CONFIG 0x0DU -#define AD559X_EN_REF BIT(9) +#define AD559X_DAC_RANGE BIT(4) +#define AD559X_ADC_RANGE BIT(5) +#define AD559X_EN_REF BIT(9) #define AD559X_PIN_MAX 8U diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/aw9523b.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/aw9523b.h new file mode 100644 index 00000000..68abdc0d --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/aw9523b.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 TOKITA Hiroshi + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_AW9523B_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_AW9523B_H_ + +struct k_sem; +struct device; + +#define AW9523B_REG_INPUT0 0x00 +#define AW9523B_REG_INPUT1 0x01 +#define AW9523B_REG_OUTPUT0 0x02 +#define AW9523B_REG_OUTPUT1 0x03 +#define AW9523B_REG_CONFIG0 0x04 +#define AW9523B_REG_CONFIG1 0x05 +#define AW9523B_REG_INT0 0x06 +#define AW9523B_REG_INT1 0x07 +#define AW9523B_REG_ID 0x10 +#define AW9523B_REG_CTL 0x11 +#define AW9523B_REG_MODE0 0x12 +#define AW9523B_REG_MODE1 0x13 +#define AW9523B_REG_DIM0 0x20 +#define AW9523B_REG_DIM1 0x21 +#define AW9523B_REG_DIM2 0x22 +#define AW9523B_REG_DIM3 0x23 +#define AW9523B_REG_DIM4 0x24 +#define AW9523B_REG_DIM5 0x25 +#define AW9523B_REG_DIM6 0x26 +#define AW9523B_REG_DIM7 0x27 +#define AW9523B_REG_DIM8 0x28 +#define AW9523B_REG_DIM9 0x29 +#define AW9523B_REG_DIM10 0x2A +#define AW9523B_REG_DIM11 0x2B +#define AW9523B_REG_DIM12 0x2C +#define AW9523B_REG_DIM13 0x2D +#define AW9523B_REG_DIM14 0x2E +#define AW9523B_REG_DIM15 0x2F +#define AW9523B_REG_SW_RSTN 0x7F + +struct k_sem *aw9523b_get_lock(const struct device *dev); + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_AW9523B_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/mfd_ite_it8801.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/mfd_ite_it8801.h new file mode 100644 index 00000000..94104fbd --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/mfd_ite_it8801.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2024 ITE Corporation. All Rights Reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_ITE_IT8801_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_ITE_IT8801_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * IC clock and power management controller register fields + */ +/* 0xf9: Gather interrupt status register */ +#define IT8801_REG_GISR 0xf9 +#define IT8801_REG_MASK_GISR_GKSIIS BIT(6) +/* 0xfb: Gather interrupt enable control register */ +#define IT8801_REG_GIECR 0xfb +#define IT8801_REG_MASK_GKSIIE BIT(3) +#define IT8801_REG_MASK_GGPIOIE BIT(2) + +/* + * General control register fields + */ +#define IT8801_REG_LBVIDR 0xfe +#define IT8801_REG_HBVIDR 0xff + +struct it8801_vendor_id_t { + uint8_t chip_id; + uint8_t reg; +}; + +static const struct it8801_vendor_id_t it8801_id_verify[] = { + {0x12, IT8801_REG_HBVIDR}, + {0x83, IT8801_REG_LBVIDR}, +}; + +/* + * SMbus interface register fields + */ +/* 0xfa: SMBus control register */ +#define IT8801_REG_SMBCR 0xfa +#define IT8801_REG_MASK_ARE BIT(4) + +/* + * GPIO register fields + */ +#define IT8801_GPIOAFS_FUN1 0x0 +#define IT8801_GPIOAFS_FUN2 0x01 +#define IT8801_GPIOAFS_FUN3 0x02 +/* GPIO control register */ +/* GPIO direction */ +#define IT8801_GPIODIR BIT(5) +/* GPIO input and output type */ +#define IT8801_GPIOIOT_OD BIT(4) +#define IT8801_GPIOIOT_INT_FALL BIT(4) +#define IT8801_GPIOIOT_INT_RISE BIT(3) +/* GPIO polarity */ +#define IT8801_GPIOPOL BIT(2) +/* GPIO pull-down enable */ +#define IT8801_GPIOPDE BIT(1) +/* GPIO pull-up enable */ +#define IT8801_GPIOPUE BIT(0) + +/* + * Keyboard matrix scan controller register fields + */ +/* 0x40: Keyboard scan out mode control register */ +#define IT8801_REG_MASK_KSOSDIC BIT(7) +#define IT8801_REG_MASK_KSE BIT(6) +#define IT8801_REG_MASK_AKSOSC BIT(5) + +/* + * PWM register fields + */ +#define PWM_IT8801_FREQ 32895 +/* Control push-pull flag */ +#define PWM_IT8801_PUSH_PULL BIT(8) +/* 0x5f: PWM output open-drain disable register */ +#define IT8801_REG_PWMODDSR 0x5f +/* PWM mode control register */ +#define IT8801_PWMMCR_MCR_MASK GENMASK(1, 0) +#define IT8801_PWMMCR_MCR_OFF 0 +#define IT8801_PWMMCR_MCR_BLINKING 1 +#define IT8801_PWMMCR_MCR_BREATHING 2 +#define IT8801_PWMMCR_MCR_ON 3 + +/* + * For IT8801 MFD alternate function controller + */ +#define IT8801_DT_INST_MFDCTRL(inst, idx) DT_INST_PHANDLE_BY_IDX(inst, mfdctrl, idx) + +#define IT8801_DT_INST_MFDCTRL_LEN(inst) DT_INST_PROP_LEN_OR(inst, mfdctrl, 0) + +#define IT8801_DEV_MFD(idx, inst) \ + DEVICE_DT_GET(DT_PHANDLE(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls)) +#define IT8801_DEV_MFD_PIN(idx, inst) DT_PHA(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls, pin) +#define IT8801_DEV_MFD_FUNC(idx, inst) DT_PHA(IT8801_DT_INST_MFDCTRL(inst, idx), altctrls, alt_func) + +#define IT8801_DT_MFD_ITEMS_FUNC(idx, inst) \ + { \ + .gpiocr = IT8801_DEV_MFD(idx, inst), \ + .pin = IT8801_DEV_MFD_PIN(idx, inst), \ + .alt_func = IT8801_DEV_MFD_FUNC(idx, inst), \ + } + +#define IT8801_DT_MFD_ITEMS_LIST(inst) \ + {LISTIFY(IT8801_DT_INST_MFDCTRL_LEN(inst), \ + IT8801_DT_MFD_ITEMS_FUNC, (,), \ + inst) } + +/* + * Configure alternate function pin + */ +int mfd_it8801_configure_pins(const struct i2c_dt_spec *i2c_dev, const struct device *dev, + uint8_t pin, uint8_t func); + +/* Define the IT8801 MFD interrupt callback function handler */ +typedef void (*it8801_callback_handler_t)(const struct device *dev); + +struct it8801_mfd_callback { + sys_snode_t node; + it8801_callback_handler_t cb; + const struct device *dev; +}; +/* Register the interrupt of IT8801 MFD callback function */ +void mfd_it8801_register_interrupt_callback(const struct device *mfd, + struct it8801_mfd_callback *callback); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_ITE_IT8801_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/npm2100.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/npm2100.h new file mode 100644 index 00000000..8a45925a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mfd/npm2100.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_NPM2100_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MFD_NPM2100_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mdf_interface_npm2100 MFD NPM2100 Interface + * @ingroup mfd_interfaces + * @{ + */ + +#include +#include + +#include +#include + +enum mfd_npm2100_event { + NPM2100_EVENT_SYS_DIETEMP_WARN, + NPM2100_EVENT_SYS_SHIPHOLD_FALL, + NPM2100_EVENT_SYS_SHIPHOLD_RISE, + NPM2100_EVENT_SYS_PGRESET_FALL, + NPM2100_EVENT_SYS_PGRESET_RISE, + NPM2100_EVENT_SYS_TIMER_EXPIRY, + NPM2100_EVENT_ADC_VBAT_READY, + NPM2100_EVENT_ADC_DIETEMP_READY, + NPM2100_EVENT_ADC_DROOP_DETECT, + NPM2100_EVENT_ADC_VOUT_READY, + NPM2100_EVENT_GPIO0_FALL, + NPM2100_EVENT_GPIO0_RISE, + NPM2100_EVENT_GPIO1_FALL, + NPM2100_EVENT_GPIO1_RISE, + NPM2100_EVENT_BOOST_VBAT_WARN, + NPM2100_EVENT_BOOST_VOUT_MIN, + NPM2100_EVENT_BOOST_VOUT_WARN, + NPM2100_EVENT_BOOST_VOUT_DPS, + NPM2100_EVENT_BOOST_VOUT_OK, + NPM2100_EVENT_LDOSW_OCP, + NPM2100_EVENT_LDOSW_VINTFAIL, + NPM2100_EVENT_MAX +}; + +enum mfd_npm2100_timer_mode { + NPM2100_TIMER_MODE_GENERAL_PURPOSE, + NPM2100_TIMER_MODE_WDT_RESET, + NPM2100_TIMER_MODE_WDT_POWER_CYCLE, + NPM2100_TIMER_MODE_WAKEUP, +}; + +/** + * @brief Write npm2100 timer register + * + * The timer tick resolution is 1/64 seconds. + * This function does not start the timer (see mfd_npm2100_start_timer()). + * + * @param dev npm2100 mfd device + * @param time_ms timer value in ms + * @param mode timer mode + * @retval 0 If successful + * @retval -EINVAL if time value is too large + * @retval -errno In case of any bus error (see i2c_write_dt()) + */ +int mfd_npm2100_set_timer(const struct device *dev, uint32_t time_ms, + enum mfd_npm2100_timer_mode mode); + +/** + * @brief Start npm2100 timer + * + * @param dev npm2100 mfd device + * @retval 0 If successful + * @retval -errno In case of any bus error (see i2c_write_dt()) + */ +int mfd_npm2100_start_timer(const struct device *dev); + +/** + * @brief npm2100 full power reset + * + * @param dev npm2100 mfd device + * @retval 0 If successful + * @retval -errno In case of any bus error (see i2c_write_dt()) + */ +int mfd_npm2100_reset(const struct device *dev); + +/** + * @brief npm2100 hibernate + * + * Enters low power state, and wakes after specified time or "shphld" pin signal. + * + * @param dev npm2100 mfd device + * @param time_ms timer value in ms. Set to 0 to disable timer. + * @retval 0 If successful + * @retval -EINVAL if time value is too large + * @retval -EBUSY if the timer is already in use. + * @retval -errno In case of any bus error (see i2c_write_dt()) + */ +int mfd_npm2100_hibernate(const struct device *dev, uint32_t time_ms); + +/** + * @brief Add npm2100 event callback + * + * @param dev npm2100 mfd device + * @param callback callback + * @return 0 on success, -errno on failure + */ +int mfd_npm2100_add_callback(const struct device *dev, struct gpio_callback *callback); + +/** + * @brief Remove npm2100 event callback + * + * @param dev npm2100 mfd device + * @param callback callback + * @return 0 on success, -errno on failure + */ +int mfd_npm2100_remove_callback(const struct device *dev, struct gpio_callback *callback); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_NPM2100_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mipi_dbi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mipi_dbi.h index d6ffcaf3..109741e3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mipi_dbi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mipi_dbi.h @@ -15,7 +15,7 @@ * 1. 9 write clocks per byte, final bit is command/data selection bit * 2. Same as above, but 16 write clocks per byte * 3. 8 write clocks per byte. Command/data selected via GPIO pin - * The current driver interface only supports type C modes 1 and 3 + * The current driver interface does not support type C with 16 write clocks (option 2). */ #ifndef ZEPHYR_INCLUDE_DRIVERS_MIPI_DBI_H_ @@ -63,7 +63,7 @@ extern "C" { .cs = { \ .gpio = GPIO_DT_SPEC_GET_BY_IDX_OR(DT_PHANDLE(DT_PARENT(node_id), \ spi_dev), cs_gpios, \ - DT_REG_ADDR(node_id), \ + DT_REG_ADDR_RAW(node_id), \ {}), \ .delay = (delay_), \ }, \ @@ -96,7 +96,7 @@ extern "C" { */ #define MIPI_DBI_CONFIG_DT(node_id, operation_, delay_) \ { \ - .mode = DT_PROP(node_id, mipi_mode), \ + .mode = DT_STRING_UPPER_TOKEN(node_id, mipi_mode), \ .config = MIPI_DBI_SPI_CONFIG_DT(node_id, operation_, delay_), \ } @@ -112,13 +112,37 @@ extern "C" { #define MIPI_DBI_CONFIG_DT_INST(inst, operation_, delay_) \ MIPI_DBI_CONFIG_DT(DT_DRV_INST(inst), operation_, delay_) +/** + * @brief Get the MIPI DBI TE mode from devicetree + * + * Gets the MIPI DBI TE mode from a devicetree property. + * @param node_id Devicetree node identifier for the MIPI DBI device with the + * TE mode property + * @param edge_prop Property name for the TE mode that should be read from + * devicetree + */ +#define MIPI_DBI_TE_MODE_DT(node_id, edge_prop) \ + DT_STRING_UPPER_TOKEN(node_id, edge_prop) + +/** + * @brief Get the MIPI DBI TE mode for device instance + * + * Gets the MIPI DBI TE mode from a devicetree property. Equivalent to + * MIPI_DBI_TE_MODE_DT(DT_DRV_INST(inst), edge_mode). + * @param inst Instance of the device to get the TE mode for + * @param edge_prop Property name for the TE mode that should be read from + * devicetree + */ +#define MIPI_DBI_TE_MODE_DT_INST(inst, edge_prop) \ + DT_STRING_UPPER_TOKEN(DT_DRV_INST(inst), edge_prop) + /** * @brief MIPI DBI controller configuration * * Configuration for MIPI DBI controller write */ struct mipi_dbi_config { - /** MIPI DBI mode (SPI 3 wire or 4 wire) */ + /** MIPI DBI mode */ uint8_t mode; /** SPI configuration */ struct spi_config config; @@ -138,9 +162,12 @@ __subsystem struct mipi_dbi_driver_api { const uint8_t *framebuf, struct display_buffer_descriptor *desc, enum display_pixel_format pixfmt); - int (*reset)(const struct device *dev, uint32_t delay); + int (*reset)(const struct device *dev, k_timeout_t delay); int (*release)(const struct device *dev, const struct mipi_dbi_config *config); + int (*configure_te)(const struct device *dev, + uint8_t edge, + k_timeout_t delay); }; /** @@ -247,13 +274,13 @@ static inline int mipi_dbi_write_display(const struct device *dev, * * Resets the attached display controller. * @param dev mipi dbi controller - * @param delay duration to set reset signal for, in milliseconds + * @param delay_ms duration to set reset signal for, in milliseconds * @retval 0 reset succeeded * @retval -EIO I/O error * @retval -ENOSYS not implemented * @retval -ENOTSUP not supported */ -static inline int mipi_dbi_reset(const struct device *dev, uint32_t delay) +static inline int mipi_dbi_reset(const struct device *dev, uint32_t delay_ms) { const struct mipi_dbi_driver_api *api = (const struct mipi_dbi_driver_api *)dev->api; @@ -261,7 +288,7 @@ static inline int mipi_dbi_reset(const struct device *dev, uint32_t delay) if (api->reset == NULL) { return -ENOSYS; } - return api->reset(dev, delay); + return api->reset(dev, K_MSEC(delay_ms)); } /** @@ -293,6 +320,45 @@ static inline int mipi_dbi_release(const struct device *dev, return api->release(dev, config); } +/** + * @brief Configures MIPI DBI tearing effect signal + * + * Many displays provide a tearing effect signal, which can be configured + * to pulse at each vsync interval or each hsync interval. This signal can be + * used by the MCU to determine when to transmit a new frame so that the + * read pointer of the display never overlaps with the write pointer from the + * MCU. This function configures the MIPI DBI controller to delay transmitting + * display frames until the selected tearing effect signal edge occurs. + * + * The delay will occur on the on each call to @ref mipi_dbi_write_display + * where the ``frame_incomplete`` flag was set within the buffer descriptor + * provided with the prior call, as this indicates the buffer being written + * in this call is the first buffer of a new frame. + * + * Note that most display controllers will need to enable the TE signal + * using vendor specific commands before the MIPI DBI controller can react + * to it. + * + * @param dev mipi dbi controller + * @param edge which edge of the TE signal to start transmitting on + * @param delay_us how many microseconds after TE edge to start transmission + * @retval -EIO I/O error + * @retval -ENOSYS not implemented + * @retval -ENOTSUP not supported + */ +static inline int mipi_dbi_configure_te(const struct device *dev, + uint8_t edge, + uint32_t delay_us) +{ + const struct mipi_dbi_driver_api *api = + (const struct mipi_dbi_driver_api *)dev->api; + + if (api->configure_te == NULL) { + return -ENOSYS; + } + return api->configure_te(dev, edge, K_USEC(delay_us)); +} + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/coresight/nrf_etr.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/coresight/nrf_etr.h new file mode 100644 index 00000000..062afa3b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/coresight/nrf_etr.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ +#define _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Flush data from the ETR buffer. */ +void nrf_etr_flush(void); + +#ifdef __cplusplus +} +#endif + +#endif /* _ZEPHYR_DRIVERS_MISC_CORESIGHT_NRF_ETR_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/coresight/stmesp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/coresight/stmesp.h new file mode 100644 index 00000000..d14e6e42 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/coresight/stmesp.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ +#define ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ + +#include + +/** + * @brief Coresight STMESP (STM Extended Stimulus Port) Interface + * @defgroup stmsp_interface Coresight STMESP interface + * @ingroup misc_interfaces + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN + * @brief STMESP register structure. + */ +typedef struct { + volatile uint32_t G_DMTS[2]; + volatile uint32_t G_DM[2]; + volatile uint32_t G_DTS[2]; + volatile uint32_t G_D[2]; + volatile uint32_t RESERVED0[16]; + volatile uint32_t G_FLAGTS[2]; + volatile uint32_t G_FLAG[2]; + volatile uint32_t G_TRIGTS[2]; + volatile uint32_t G_TRIG[2]; + volatile uint32_t I_DMTS[2]; + volatile uint32_t I_DM[2]; + volatile uint32_t I_DTS[2]; + volatile uint32_t I_D[2]; + volatile uint32_t RESERVED1[16]; + volatile uint32_t I_FLAGTS[2]; + volatile uint32_t I_FLAG[2]; + volatile uint32_t I_TRIGTS[2]; + volatile uint32_t I_TRIG[2]; +} STMESP_Type; + +/** @brief Helper function for getting target register. + * + * @param reg STMESP register set. + * @param ts Use timestamp. + * @param marked Use marked register. + * @param guaranteed True to use guaranteed access. + * + * @return Address of the register. + */ +static inline volatile void *_stmesp_get_data_reg(STMESP_Type *reg, bool ts, + bool marked, bool guaranteed) +{ + if (ts) { + if (guaranteed) { + if (marked) { + return ®->G_DMTS[0]; + } else { + return ®->G_DTS[0]; + } + } else { + if (marked) { + return ®->I_DMTS[0]; + } else { + return ®->I_DTS[0]; + } + } + } else { + if (guaranteed) { + if (marked) { + return ®->G_DM[0]; + } else { + return ®->G_D[0]; + } + } else { + if (marked) { + return ®->I_DM[0]; + } else { + return ®->I_D[0]; + } + } + } +} + +/** @endcond */ + +/** @brief Write flag to STMESP + * + * @param reg STMESP register set. + * @param data Data written to the flag register. + * @param ts If true add timestamp. + * @param guaranteed If true guaranteed write and invariant if false. + */ +static inline void stmesp_flag(STMESP_Type *reg, uint32_t data, bool ts, bool guaranteed) +{ + if (ts) { + if (guaranteed) { + reg->G_FLAGTS[0] = data; + } else { + reg->I_FLAGTS[0] = data; + } + } else { + if (guaranteed) { + reg->G_FLAG[0] = data; + } else { + reg->I_FLAG[0] = data; + } + } +} + +/** @brief Write 8 bit data to STMESP + * + * @param reg STMESP register set. + * @param data Byte to write. + * @param ts If true add timestamp. + * @param marked If true marked write. + * @param guaranteed If true guaranteed write and invariant if false. + */ +static inline void stmesp_data8(STMESP_Type *reg, uint8_t data, bool ts, + bool marked, bool guaranteed) +{ + *(volatile uint8_t *)_stmesp_get_data_reg(reg, ts, marked, guaranteed) = data; +} + +/** @brief Write 16 bit data to STMESP + * + * @param reg STMESP register set. + * @param data Half word to write. + * @param ts If true add timestamp. + * @param marked If true marked write. + * @param guaranteed If true guaranteed write and invariant if false. + */ +static inline void stmesp_data16(STMESP_Type *reg, uint16_t data, bool ts, + bool marked, bool guaranteed) +{ + *(volatile uint16_t *)_stmesp_get_data_reg(reg, ts, marked, guaranteed) = data; +} + +/** @brief Write 32 bit data to STMESP + * + * @param reg STMESP register set. + * @param data Word to write. + * @param ts If true add timestamp. + * @param marked If true marked write. + * @param guaranteed If true guaranteed write and invariant if false. + */ +static inline void stmesp_data32(STMESP_Type *reg, uint32_t data, bool ts, + bool marked, bool guaranteed) +{ + *(volatile uint32_t *)_stmesp_get_data_reg(reg, ts, marked, guaranteed) = data; +} + +/** + * @brief Return address of a STM extended stimulus port. + * + * Function return a port from the local STMESP instance. + * + * @param[in] idx Index of the requested stimulus port. + * @param[out] port Location where pointer to the port is written. + * + * @retval -EINVAL if @p idx or @p port is invalid. + * @retval 0 on success. + */ +static inline int stmesp_get_port(uint32_t idx, STMESP_Type **port) + +{ + /* Check if index is within STM ports */ + if ((port == NULL) || + (idx >= (DT_REG_SIZE(DT_NODELABEL(stmesp)) / sizeof(STMESP_Type)))) { + return -EINVAL; + } + + STMESP_Type *const base = (STMESP_Type *const)DT_REG_ADDR(DT_NODELABEL(stmesp)); + + *port = &base[idx]; + + return 0; +} + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_DRIVERS_MISC_CORESIGHT_STMESP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/devmux/devmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/devmux/devmux.h index 8b01d633..4c084199 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/devmux/devmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/misc/devmux/devmux.h @@ -62,7 +62,7 @@ extern "C" { * @return The index (>= 0) of the currently active multiplexed device on success * @retval -EINVAL If @p dev is invalid */ -__syscall ssize_t devmux_select_get(const struct device *dev); +__syscall int devmux_select_get(const struct device *dev); /** * @brief Set the selection of a devmux device. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi.h index fefa48fa..3c8a535a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi.h @@ -204,7 +204,10 @@ enum mspi_timing_param { * @brief Stub for struct timing_cfg */ struct mspi_timing_cfg { - +#ifdef __cplusplus + /* For C++ compatibility. */ + uint8_t dummy; +#endif }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi/devicetree.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi/devicetree.h index c720071c..a3e5b653 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi/devicetree.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/mspi/devicetree.h @@ -212,7 +212,8 @@ extern "C" { * @return #gpio_dt_spec struct corresponding with mspi_dev's chip enable */ #define MSPI_DEV_CE_GPIOS_DT_SPEC_GET(mspi_dev) \ - GPIO_DT_SPEC_GET_BY_IDX_OR(DT_BUS(mspi_dev), ce_gpios, DT_REG_ADDR(mspi_dev), {}) + GPIO_DT_SPEC_GET_BY_IDX_OR(DT_BUS(mspi_dev), ce_gpios, \ + DT_REG_ADDR_RAW(mspi_dev), {}) /** * @brief Get a struct gpio_dt_spec for a MSPI device's chip enable pin diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl.h index 3c2fefbe..cfababd1 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl.h @@ -157,10 +157,10 @@ struct pinctrl_dev_config { #define Z_PINCTRL_STATE_INIT(state_idx, node_id) \ COND_CODE_1(Z_PINCTRL_SKIP_STATE(state_idx, node_id), (), \ ({ \ - .id = Z_PINCTRL_STATE_ID(state_idx, node_id), \ .pins = Z_PINCTRL_STATE_PINS_NAME(state_idx, node_id), \ .pin_cnt = ARRAY_SIZE(Z_PINCTRL_STATE_PINS_NAME(state_idx, \ - node_id)) \ + node_id)), \ + .id = Z_PINCTRL_STATE_ID(state_idx, node_id) \ })) /** @@ -414,9 +414,9 @@ static inline int pinctrl_apply_state(const struct pinctrl_dev_config *config, */ #define PINCTRL_DT_STATE_INIT(prop, state) \ { \ - .id = state, \ .pins = prop ## _pins, \ - .pin_cnt = ARRAY_SIZE(prop ## _pins) \ + .pin_cnt = ARRAY_SIZE(prop ## _pins), \ + .id = state \ } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h new file mode 100644 index 00000000..e7976b5c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h @@ -0,0 +1,78 @@ +/* + * Copyright 2022, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * @file + * NXP PORT SOC specific helpers for pinctrl driver + */ + + +#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_ +#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_ + +/** @cond INTERNAL_HIDDEN */ + +#include +#include + +/* Include SOC headers, so we get definitions for PCR bitmasks */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Some PORT IP instantiations lack certain features, include input buffers, + * open drain, and slew rate. If masks aren't defined for these bitfields, + * define them to have no effect + */ +#ifndef PORT_PCR_IBE_MASK /* Input buffer enable */ +#define PORT_PCR_IBE_MASK 0x0 +#define PORT_PCR_IBE(x) 0x0 +#endif + +#ifndef PORT_PCR_SRE_MASK /* Slew rate */ +#define PORT_PCR_SRE_MASK 0x0 +#define PORT_PCR_SRE(x) 0x0 +#endif + +#ifndef PORT_PCR_ODE_MASK /* Open drain */ +#define PORT_PCR_ODE_MASK 0x0 +#define PORT_PCR_ODE(x) 0x0 +#endif + + +typedef uint32_t pinctrl_soc_pin_t; + +#define Z_PINCTRL_NXP_PORT_PINCFG(node_id) \ + (PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \ + PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \ + PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \ + PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \ + PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \ + PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \ + PORT_PCR_IBE(DT_PROP(node_id, input_enable)) | \ + PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter))) + +#define Z_PINCTRL_NXP_PORT_PCR_MASK \ + (PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | \ + PORT_PCR_IBE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK) + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_NXP_PORT_PINCFG(group), + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)}; + +#ifdef __cplusplus +} +#endif + +/** @endcond */ + +#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pwm/pwm_fake.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pwm/pwm_fake.h new file mode 100644 index 00000000..4d430e75 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/pwm/pwm_fake.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024, Kickmaker + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef INCLUDE_DRIVERS_PWM_PWM_FAKE_H_ +#define INCLUDE_DRIVERS_PWM_PWM_FAKE_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +DECLARE_FAKE_VALUE_FUNC(int, fake_pwm_set_cycles, const struct device *, uint32_t, uint32_t, + uint32_t, pwm_flags_t); + +#ifdef __cplusplus +} +#endif + +#endif /* INCLUDE_DRIVERS_PWM_PWM_FAKE_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/regulator.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/regulator.h index 463777ea..1d8e2255 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/regulator.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/regulator.h @@ -179,7 +179,7 @@ struct regulator_common_config { uint8_t allowed_modes_cnt; /** Regulator initial mode */ regulator_mode_t initial_mode; - /** Flags (@reg REGULATOR_FLAGS). */ + /** Flags (@ref REGULATOR_FLAGS). */ uint8_t flags; }; @@ -313,6 +313,28 @@ static inline int regulator_common_get_min_voltage(const struct device *dev, int return 0; } +/** + * @brief Get maximum supported voltage. + * + * @param dev Regulator device instance. + * @param max_uv Where maximum voltage will be stored, in microvolts. + * + * @retval 0 If successful + * @retval -ENOENT If maximum voltage is not specified. + */ +static inline int regulator_common_get_max_voltage(const struct device *dev, int32_t *max_uv) +{ + const struct regulator_common_config *config = + (const struct regulator_common_config *)dev->config; + + if (config->max_uv == INT32_MAX) { + return -ENOENT; + } + + *max_uv = config->max_uv; + return 0; +} + /** @endcond */ /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc.h index b042af0a..946d6e30 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc.h @@ -199,9 +199,7 @@ __syscall int rtc_set_time(const struct device *dev, const struct rtc_time *time static inline int z_impl_rtc_set_time(const struct device *dev, const struct rtc_time *timeptr) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - return api->set_time(dev, timeptr); + return DEVICE_API_GET(rtc, dev)->set_time(dev, timeptr); } /** @@ -218,9 +216,7 @@ __syscall int rtc_get_time(const struct device *dev, struct rtc_time *timeptr); static inline int z_impl_rtc_get_time(const struct device *dev, struct rtc_time *timeptr) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - return api->get_time(dev, timeptr); + return DEVICE_API_GET(rtc, dev)->get_time(dev, timeptr); } /** @@ -249,13 +245,11 @@ __syscall int rtc_alarm_get_supported_fields(const struct device *dev, uint16_t static inline int z_impl_rtc_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->alarm_get_supported_fields == NULL) { + if (DEVICE_API_GET(rtc, dev)->alarm_get_supported_fields == NULL) { return -ENOSYS; } - return api->alarm_get_supported_fields(dev, id, mask); + return DEVICE_API_GET(rtc, dev)->alarm_get_supported_fields(dev, id, mask); } /** @@ -287,13 +281,11 @@ __syscall int rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t static inline int z_impl_rtc_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask, const struct rtc_time *timeptr) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->alarm_set_time == NULL) { + if (DEVICE_API_GET(rtc, dev)->alarm_set_time == NULL) { return -ENOSYS; } - return api->alarm_set_time(dev, id, mask, timeptr); + return DEVICE_API_GET(rtc, dev)->alarm_set_time(dev, id, mask, timeptr); } /** @@ -317,13 +309,11 @@ __syscall int rtc_alarm_get_time(const struct device *dev, uint16_t id, uint16_t static inline int z_impl_rtc_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask, struct rtc_time *timeptr) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->alarm_get_time == NULL) { + if (DEVICE_API_GET(rtc, dev)->alarm_get_time == NULL) { return -ENOSYS; } - return api->alarm_get_time(dev, id, mask, timeptr); + return DEVICE_API_GET(rtc, dev)->alarm_get_time(dev, id, mask, timeptr); } /** @@ -345,13 +335,11 @@ __syscall int rtc_alarm_is_pending(const struct device *dev, uint16_t id); static inline int z_impl_rtc_alarm_is_pending(const struct device *dev, uint16_t id) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->alarm_is_pending == NULL) { + if (DEVICE_API_GET(rtc, dev)->alarm_is_pending == NULL) { return -ENOSYS; } - return api->alarm_is_pending(dev, id); + return DEVICE_API_GET(rtc, dev)->alarm_is_pending(dev, id); } /** @@ -386,13 +374,11 @@ __syscall int rtc_alarm_set_callback(const struct device *dev, uint16_t id, static inline int z_impl_rtc_alarm_set_callback(const struct device *dev, uint16_t id, rtc_alarm_callback callback, void *user_data) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->alarm_set_callback == NULL) { + if (DEVICE_API_GET(rtc, dev)->alarm_set_callback == NULL) { return -ENOSYS; } - return api->alarm_set_callback(dev, id, callback, user_data); + return DEVICE_API_GET(rtc, dev)->alarm_set_callback(dev, id, callback, user_data); } #endif /* CONFIG_RTC_ALARM */ @@ -431,13 +417,11 @@ __syscall int rtc_update_set_callback(const struct device *dev, rtc_update_callb static inline int z_impl_rtc_update_set_callback(const struct device *dev, rtc_update_callback callback, void *user_data) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->update_set_callback == NULL) { + if (DEVICE_API_GET(rtc, dev)->update_set_callback == NULL) { return -ENOSYS; } - return api->update_set_callback(dev, callback, user_data); + return DEVICE_API_GET(rtc, dev)->update_set_callback(dev, callback, user_data); } #endif /* CONFIG_RTC_UPDATE */ @@ -473,13 +457,11 @@ __syscall int rtc_set_calibration(const struct device *dev, int32_t calibration) static inline int z_impl_rtc_set_calibration(const struct device *dev, int32_t calibration) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->set_calibration == NULL) { + if (DEVICE_API_GET(rtc, dev)->set_calibration == NULL) { return -ENOSYS; } - return api->set_calibration(dev, calibration); + return DEVICE_API_GET(rtc, dev)->set_calibration(dev, calibration); } /** @@ -496,13 +478,11 @@ __syscall int rtc_get_calibration(const struct device *dev, int32_t *calibration static inline int z_impl_rtc_get_calibration(const struct device *dev, int32_t *calibration) { - const struct rtc_driver_api *api = (const struct rtc_driver_api *)dev->api; - - if (api->get_calibration == NULL) { + if (DEVICE_API_GET(rtc, dev)->get_calibration == NULL) { return -ENOSYS; } - return api->get_calibration(dev, calibration); + return DEVICE_API_GET(rtc, dev)->get_calibration(dev, calibration); } #endif /* CONFIG_RTC_CALIBRATION */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc/rtc_fake.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc/rtc_fake.h index ad3a2751..d421a561 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc/rtc_fake.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/rtc/rtc_fake.h @@ -19,19 +19,19 @@ DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_get_time, const struct device *, struct rt #ifdef CONFIG_RTC_ALARM DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_supported_fields, const struct device *, uint16_t, - uint16_t); + uint16_t *); DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_time, const struct device *, uint16_t, uint16_t, - constr struct rtc_time *); -DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t, + const struct rtc_time *); +DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_get_time, const struct device *, uint16_t, uint16_t *, struct rtc_time *); DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_is_pending, const struct device *, uint16_t); -DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *uint16_t, +DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_alarm_set_callback, const struct device *, uint16_t, rtc_alarm_callback, void *); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_UPDATE -DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *rtc_alarm_callback, - void *); +DECLARE_FAKE_VALUE_FUNC(int, rtc_fake_update_set_callback, const struct device *, + rtc_update_callback, void *); #endif /* CONFIG_RTC_UPDATE */ #ifdef CONFIG_RTC_CALIBRATION diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor.h index f23830c8..6cd8cc70 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor.h @@ -343,7 +343,10 @@ enum sensor_attribute { /** Hardware batch duration in ticks */ SENSOR_ATTR_BATCH_DURATION, - + /* Configure the gain of a sensor. */ + SENSOR_ATTR_GAIN, + /* Configure the resolution of a sensor. */ + SENSOR_ATTR_RESOLUTION, /** * Number of all common sensor attributes. */ @@ -938,6 +941,30 @@ struct __attribute__((__packed__)) sensor_data_generic_header { ((chan) == SENSOR_CHAN_ACCEL_XYZ || (chan) == SENSOR_CHAN_GYRO_XYZ || \ (chan) == SENSOR_CHAN_MAGN_XYZ || (chan) == SENSOR_CHAN_POS_DXYZ) +/** + * @brief checks if a given channel is an Accelerometer + * + * @param[in] chan The channel to check + * @retval true if @p chan is any of @ref SENSOR_CHAN_ACCEL_XYZ, @ref SENSOR_CHAN_ACCEL_X, or + * @ref SENSOR_CHAN_ACCEL_Y, or @ref SENSOR_CHAN_ACCEL_Z + * @retval false otherwise + */ +#define SENSOR_CHANNEL_IS_ACCEL(chan) \ + ((chan) == SENSOR_CHAN_ACCEL_XYZ || (chan) == SENSOR_CHAN_ACCEL_X || \ + (chan) == SENSOR_CHAN_ACCEL_Y || (chan) == SENSOR_CHAN_ACCEL_Z) + +/** + * @brief checks if a given channel is a Gyroscope + * + * @param[in] chan The channel to check + * @retval true if @p chan is any of @ref SENSOR_CHAN_GYRO_XYZ, @ref SENSOR_CHAN_GYRO_X, or + * @ref SENSOR_CHAN_GYRO_Y, or @ref SENSOR_CHAN_GYRO_Z + * @retval false otherwise + */ +#define SENSOR_CHANNEL_IS_GYRO(chan) \ + ((chan) == SENSOR_CHAN_GYRO_XYZ || (chan) == SENSOR_CHAN_GYRO_X || \ + (chan) == SENSOR_CHAN_GYRO_Y || (chan) == SENSOR_CHAN_GYRO_Z) + /** * @brief Get the sensor's decoder API * @@ -1061,7 +1088,7 @@ static inline int sensor_read(struct rtio_iodev *iodev, struct rtio *ctx, uint8_ struct rtio_cqe *cqe = rtio_cqe_consume_block(ctx); int res = cqe->result; - __ASSERT(cqe->userdata != buf, + __ASSERT(cqe->userdata == buf, "consumed non-matching completion for sensor read into buffer %p\n", buf); rtio_cqe_release(ctx, cqe); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/battery.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/battery.h new file mode 100644 index 00000000..61581419 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/battery.h @@ -0,0 +1,87 @@ +/* + * Copyright 2024 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_BATTERY_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_BATTERY_H_ + +#include +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief battery API + * @defgroup battery_apis battery APIs + * @{ + */ + +/* Battery chemistry enumeration. + * Value names must match those from dts/bindings/battery.yaml + */ +enum battery_chemistry { + BATTERY_CHEMISTRY_UNKNOWN = 0, + BATTERY_CHEMISTRY_NICKEL_CADMIUM, + BATTERY_CHEMISTRY_NICKEL_METAL_HYDRIDE, + BATTERY_CHEMISTRY_LITHIUM_ION, + BATTERY_CHEMISTRY_LITHIUM_ION_POLYMER, + BATTERY_CHEMISTRY_LITHIUM_ION_IRON_PHOSPHATE, + BATTERY_CHEMISTRY_LITHIUM_ION_MANGANESE_OXIDE, +}; + +/* Length of open circuit voltage table */ +#define BATTERY_OCV_TABLE_LEN 11 + +/** + * @brief Get the battery chemistry enum value + * + * @param node_id node identifier + */ +#define BATTERY_CHEMISTRY_DT_GET(node_id) \ + UTIL_CAT(BATTERY_CHEMISTRY_, DT_STRING_UPPER_TOKEN_OR(node_id, device_chemistry, UNKNOWN)) + +/** + * @brief Get the OCV curve for a given table + * + * @param node_id node identifier + * @param table table to retrieve + */ +#define BATTERY_OCV_TABLE_DT_GET(node_id, table) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, table), \ + ({DT_FOREACH_PROP_ELEM_SEP(node_id, table, DT_PROP_BY_IDX, (,))}), ({-1})) + +/** + * @brief Convert an OCV table and battery voltage to a charge percentage + * + * @param ocv_table Open circuit voltage curve + * @param voltage_uv Battery voltage in microVolts + * + * @returns Battery state of charge in milliPercent + */ +static inline int32_t battery_soc_lookup(const int32_t ocv_table[BATTERY_OCV_TABLE_LEN], + uint32_t voltage_uv) +{ + static const int32_t soc_axis[BATTERY_OCV_TABLE_LEN] = { + 0, 10000, 20000, 30000, 40000, 50000, 60000, 70000, 80000, 90000, 100000}; + + /* Convert voltage to SoC */ + return linear_interpolate(ocv_table, soc_axis, BATTERY_OCV_TABLE_LEN, voltage_uv); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_BATTERY_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mcux_acmp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mcux_acmp.h index 3bbfc22e..2bd2addd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mcux_acmp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mcux_acmp.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2020 Vestas Wind Systems A/S - * Copyright 2022 NXP + * Copyright 2022, 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,6 +43,12 @@ extern "C" { #define MCUX_ACMP_HAS_DISCRETE_MODE 0 #endif +#if defined(FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT) && (FSL_FEATURE_ACMP_HAS_C0_HYSTCTR_BIT == 1U) +#define MCUX_ACMP_HAS_HYSTCTR 1 +#else +#define MCUX_ACMP_HAS_HYSTCTR 0 +#endif + enum sensor_channel_mcux_acmp { /** Analog Comparator Output. */ SENSOR_CHAN_MCUX_ACMP_OUTPUT = SENSOR_CHAN_PRIV_START, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mmc56x3.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mmc56x3.h new file mode 100644 index 00000000..b59ea4a4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/mmc56x3.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2023 Kurtis Dinelle + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Extended public API for Memsic MMC56X3 magnetometer and temperature sensor + * + * This exposes attributes for the MMC56X3 which can be used for + * setting the continuous mode and bandwidth selection bits. + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MMC56X3_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MMC56X3_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum sensor_attribute_mmc56x3 { + /* Bandwidth selection bit 0. + * + * Adjust length of decimation filter. Controls duration of + * each measurement. Affects ODR; see datasheet for details. + */ + SENSOR_ATTR_BANDWIDTH_SELECTION_BITS_0 = SENSOR_ATTR_PRIV_START + 1, + + /* Bandwidth selection bit 1. + * + * Adjust length of decimation filter. Controls duration of + * each measurement. Affects ODR; see datasheet for details. + */ + SENSOR_ATTR_BANDWIDTH_SELECTION_BITS_1, + + /* Automatic self reset. + * + * Enable automatic self-reset function. + * Affects ODR; see datasheet for details. + */ + SENSOR_ATTR_AUTOMATIC_SELF_RESET, +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MMC56X3_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm1300_charger.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm1300_charger.h index eb13f959..d2a16634 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm1300_charger.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm1300_charger.h @@ -12,6 +12,17 @@ enum sensor_channel_npm1300_charger { SENSOR_CHAN_NPM1300_CHARGER_STATUS = SENSOR_CHAN_PRIV_START, SENSOR_CHAN_NPM1300_CHARGER_ERROR, + SENSOR_CHAN_NPM1300_CHARGER_VBUS_STATUS, +}; + +/* NPM1300 charger specific attributes */ +enum sensor_attribute_npm1300_charger { + SENSOR_ATTR_NPM1300_CHARGER_VBUS_PRESENT = SENSOR_ATTR_PRIV_START, + SENSOR_ATTR_NPM1300_CHARGER_VBUS_CUR_LIMIT, + SENSOR_ATTR_NPM1300_CHARGER_VBUS_OVERVLT_PROT, + SENSOR_ATTR_NPM1300_CHARGER_VBUS_UNDERVLT, + SENSOR_ATTR_NPM1300_CHARGER_VBUS_SUSPENDED, + SENSOR_ATTR_NPM1300_CHARGER_VBUS_BUSOUT, }; #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm2100_vbat.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm2100_vbat.h new file mode 100644 index 00000000..50165775 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/npm2100_vbat.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_NPM2100_VBAT_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_NPM2100_VBAT_H_ + +#include + +/* NPM2100 vbat specific channels */ +enum sensor_channel_npm2100_vbat { + SENSOR_CHAN_NPM2100_VBAT_STATUS = SENSOR_CHAN_PRIV_START, + SENSOR_CHAN_NPM2100_VOLT_DROOP, + SENSOR_CHAN_NPM2100_DPS_COUNT, + SENSOR_CHAN_NPM2100_DPS_TIMER, + SENSOR_CHAN_NPM2100_DPS_DURATION, +}; + +/* NPM2100 vbat specific attributes */ +enum sensor_attr_npm2100_vbat { + SENSOR_ATTR_NPM2100_ADC_DELAY = SENSOR_ATTR_PRIV_START, +}; + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/scd4x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/scd4x.h new file mode 100644 index 00000000..edae9693 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/scd4x.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 Jan Fäh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_SCD4X_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_SCD4X_H_ + +#include + +enum sensor_attribute_scd4x { + /* Offset temperature: Toffset_actual = Tscd4x – Treference + Toffset_previous + * 0 - 20°C + */ + SENSOR_ATTR_SCD4X_TEMPERATURE_OFFSET = SENSOR_ATTR_PRIV_START, + /* Altidude of the sensor; + * 0 - 3000m + */ + SENSOR_ATTR_SCD4X_SENSOR_ALTITUDE, + /* Ambient pressure in hPa + * 700 - 1200hPa + */ + SENSOR_ATTR_SCD4X_AMBIENT_PRESSURE, + /* Set the current state (enabled: 1 / disabled: 0). + * Default: enabled. + */ + SENSOR_ATTR_SCD4X_AUTOMATIC_CALIB_ENABLE, + /* Set the initial period for automatic self calibration correction in hours. Allowed values + * are integer multiples of 4 hours. + * Default: 44 + */ + SENSOR_ATTR_SCD4X_SELF_CALIB_INITIAL_PERIOD, + /* Set the standard period for automatic self calibration correction in hours. Allowed + * values are integer multiples of 4 hours. Default: 156 + */ + SENSOR_ATTR_SCD4X_SELF_CALIB_STANDARD_PERIOD, +}; + +/** + * @brief Performs a forced recalibration. + * + * Operate the SCD4x in the operation mode for at least 3 minutes in an environment with a + * homogeneous and constant CO2 concentration. Otherwise the recalibratioin will fail. The sensor + * must be operated at the voltage desired for the application when performing the FRC sequence. + * + * @param dev Pointer to the sensor device + * @param target_concentration Reference CO2 concentration. + * @param frc_correction Previous differences from the target concentration + * + * @return 0 if successful, negative errno code if failure. + */ +int scd4x_forced_recalibration(const struct device *dev, uint16_t target_concentration, + uint16_t *frc_correction); + +/** + * @brief Performs a self test. + * + * The self_test command can be used as an end-of-line test to check the sensor functionality + * + * @param dev Pointer to the sensor device + * + * @return 0 if successful, negative errno code if failure. + */ +int scd4x_self_test(const struct device *dev); + +/** + * @brief Performs a self test. + * + * The persist_settings command can be used to save the actual configuration. This command + * should only be sent when persistence is required and if actual changes to the configuration have + * been made. The EEPROM is guaranteed to withstand at least 2000 write cycles + * + * @param dev Pointer to the sensor device + * + * @return 0 if successful, negative errno code if failure. + */ +int scd4x_persist_settings(const struct device *dev); + +/** + * @brief Performs a factory reset. + * + * The perform_factory_reset command resets all configuration settings stored in the EEPROM and + * erases the FRC and ASC algorithm history. + * + * @param dev Pointer to the sensor device + * + * @return 0 if successful, negative errno code if failure. + */ +int scd4x_factory_reset(const struct device *dev); + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_SCD4X_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tmp116.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tmp116.h index 6b11426a..5efb4ad2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tmp116.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tmp116.h @@ -8,8 +8,18 @@ #define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_ #include +#include #include +enum sensor_attribute_tmp_116 { + /** Turn on power saving/one shot mode */ + SENSOR_ATTR_TMP116_ONE_SHOT_MODE = SENSOR_ATTR_PRIV_START, + /** Shutdown the sensor */ + SENSOR_ATTR_TMP116_SHUTDOWN_MODE, + /** Turn on continuous conversion */ + SENSOR_ATTR_TMP116_CONTINUOUS_CONVERSION_MODE, +}; + #define EEPROM_TMP116_SIZE (4 * sizeof(uint16_t)) int tmp116_eeprom_read(const struct device *dev, off_t offset, void *data, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tsl2540.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tsl2540.h index 63a2adfe..b0306e91 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tsl2540.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/tsl2540.h @@ -22,10 +22,8 @@ extern "C" { #endif enum sensor_attribute_tsl2540 { - /* Sensor Gain */ - SENSOR_ATTR_GAIN = SENSOR_ATTR_PRIV_START + 1, /* Sensor Integration Time (in ms) */ - SENSOR_ATTR_INTEGRATION_TIME, + SENSOR_ATTR_INTEGRATION_TIME = SENSOR_ATTR_PRIV_START + 1, /* Sensor ALS interrupt persistence filters */ SENSOR_ATTR_INT_APERS, /* Shutdown the sensor */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/wsen_hids_2525020210002.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/wsen_hids_2525020210002.h new file mode 100644 index 00000000..f140e22c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sensor/wsen_hids_2525020210002.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Extended public API for WSEN-HIDS-2525020210002 Sensor + * + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_HIDS_2525020210002_H_ +#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_HIDS_2525020210002_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +enum sensor_attribute_wsen_hids_2525020210002 { + SENSOR_ATTR_WSEN_HIDS_2525020210002_PRECISION = SENSOR_ATTR_PRIV_START, + SENSOR_ATTR_WSEN_HIDS_2525020210002_HEATER +}; + +typedef enum { + hids_2525020210002_precision_Low = 0x0, + hids_2525020210002_precision_Medium = 0x1, + hids_2525020210002_precision_High = 0x2 +} hids_2525020210002_precision_t; + +typedef enum { + hids_2525020210002_heater_Off = 0x0, + hids_2525020210002_heater_On_200mW_1s = 0x1, + hids_2525020210002_heater_On_200mW_100ms = 0x2, + hids_2525020210002_heater_On_110mW_1s = 0x3, + hids_2525020210002_heater_On_110mW_100ms = 0x4, + hids_2525020210002_heater_On_20mW_1s = 0x5, + hids_2525020210002_heater_On_20mW_100ms = 0x6, +} hids_2525020210002_heater_t; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_HIDS_2525020210002_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/serial/uart_async_to_irq.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/serial/uart_async_to_irq.h index d5116dee..3b80c906 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/serial/uart_async_to_irq.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/serial/uart_async_to_irq.h @@ -109,13 +109,11 @@ void uart_async_to_irq_trampoline_cb(const struct device *dev); /** @brief Initialize the adaptation layer. * - * @param data Data associated with the given adaptation layer instance. - * @param config Configuration structure. Must be persistent. + * @param dev UART device. Device must support asynchronous API. * * @retval 0 On successful initialization. */ -int uart_async_to_irq_init(struct uart_async_to_irq_data *data, - const struct uart_async_to_irq_config *config); +int uart_async_to_irq_init(const struct device *dev); /* @brief Enable RX for interrupt driven API. * @@ -202,7 +200,7 @@ struct uart_async_to_irq_tx_data { size_t len; }; -/** @briref Data associated with the asynchronous to the interrupt driven API adaptation layer. */ +/** @brief Data associated with the asynchronous to the interrupt driven API adaptation layer. */ struct uart_async_to_irq_data { /** User callback for interrupt driven API. */ uart_irq_callback_user_data_t callback; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sip_svc/sip_svc_driver.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sip_svc/sip_svc_driver.h index 07b8f7f8..560b9a79 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sip_svc/sip_svc_driver.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/sip_svc/sip_svc_driver.h @@ -224,7 +224,7 @@ static inline void z_impl_sip_svc_plat_update_trans_id(const struct device *dev, "sip_svc_plat_update_trans_id func shouldn't be NULL"); __ASSERT(request, "request shouldn't be NULL"); - return api->sip_svc_plat_update_trans_id(dev, request, trans_id); + api->sip_svc_plat_update_trans_id(dev, request, trans_id); } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi.h index 6e394ba8..db6e2baf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi.h @@ -100,10 +100,10 @@ extern "C" { #define SPI_WORD_SIZE_SHIFT (5U) #define SPI_WORD_SIZE_MASK (0x3FU << SPI_WORD_SIZE_SHIFT) /** @endcond */ -/** Get SPI word size. */ +/** Get SPI word size (data frame size) in bits. */ #define SPI_WORD_SIZE_GET(_operation_) \ (((_operation_) & SPI_WORD_SIZE_MASK) >> SPI_WORD_SIZE_SHIFT) -/** Set SPI word size. */ +/** Set SPI word size (data frame size) in bits. */ #define SPI_WORD_SET(_word_size_) \ ((_word_size_) << SPI_WORD_SIZE_SHIFT) /** @} */ @@ -211,7 +211,7 @@ struct spi_cs_control { */ #define SPI_CS_GPIOS_DT_SPEC_GET(spi_dev) \ GPIO_DT_SPEC_GET_BY_IDX_OR(DT_BUS(spi_dev), cs_gpios, \ - DT_REG_ADDR(spi_dev), {}) + DT_REG_ADDR_RAW(spi_dev), {}) /** * @brief Get a struct gpio_dt_spec for a SPI device's chip select pin @@ -309,7 +309,7 @@ struct spi_config { * - 0: Master or slave. * - 1..3: Polarity, phase and loop mode. * - 4: LSB or MSB first. - * - 5..10: Size of a data frame in bits. + * - 5..10: Size of a data frame (word) in bits. * - 11: Full/half duplex. * - 12: Hold on the CS line if possible. * - 13: Keep resource locked for the caller. @@ -418,13 +418,47 @@ struct spi_dt_spec { #define SPI_DT_SPEC_INST_GET(inst, operation_, delay_) \ SPI_DT_SPEC_GET(DT_DRV_INST(inst), operation_, delay_) +/** + * @brief Value that will never compare true with any valid overrun character + */ +#define SPI_MOSI_OVERRUN_UNKNOWN 0x100 + +/** + * @brief The value sent on MOSI when all TX bytes are sent, but RX continues + * + * For drivers where the MOSI line state when receiving is important, this value + * can be queried at compile-time to determine whether allocating a constant + * array is necessary. + * + * @param node_id Devicetree node identifier for the SPI device to query + * + * @retval SPI_MOSI_OVERRUN_UNKNOWN if controller does not export the value + * @retval byte default MOSI value otherwise + */ +#define SPI_MOSI_OVERRUN_DT(node_id) \ + DT_PROP_OR(node_id, overrun_character, SPI_MOSI_OVERRUN_UNKNOWN) + +/** + * @brief The value sent on MOSI when all TX bytes are sent, but RX continues + * + * This is equivalent to + * SPI_MOSI_OVERRUN_DT(DT_DRV_INST(inst)). + * + * @param inst Devicetree instance number + * + * @retval SPI_MOSI_OVERRUN_UNKNOWN if controller does not export the value + * @retval byte default MOSI value otherwise + */ +#define SPI_MOSI_OVERRUN_DT_INST(inst) \ + DT_INST_PROP_OR(inst, overrun_character, SPI_MOSI_OVERRUN_UNKNOWN) + /** * @brief SPI buffer structure */ struct spi_buf { /** Valid pointer to a data buffer, or NULL otherwise */ void *buf; - /** Length of the buffer @a buf. + /** Length of the buffer @a buf in bytes. * If @a buf is NULL, length which as to be sent as dummy bytes (as TX * buffer) or the length of bytes that should be skipped (as RX buffer). */ @@ -437,7 +471,7 @@ struct spi_buf { struct spi_buf_set { /** Pointer to an array of spi_buf, or NULL */ const struct spi_buf *buffers; - /** Length of the array pointed by @a buffers */ + /** Length of the array (number of buffers) pointed by @a buffers */ size_t count; }; @@ -593,6 +627,17 @@ static inline void spi_transceive_stats(const struct device *dev, int error, #endif /*CONFIG_SPI_STATS*/ +/** + * @brief Like SPI_DEVICE_DT_DEFINE(), but uses an instance of a `DT_DRV_COMPAT` + * compatible instead of a node identifier. + * + * @param inst Instance number. The `node_id` argument to SPI_DEVICE_DT_DEFINE() is + * set to `DT_DRV_INST(inst)`. + * @param ... Other parameters as expected by SPI_DEVICE_DT_DEFINE(). + */ +#define SPI_DEVICE_DT_INST_DEFINE(inst, ...) \ + SPI_DEVICE_DT_DEFINE(DT_DRV_INST(inst), __VA_ARGS__) + /** * @typedef spi_api_io * @brief Callback API for I/O @@ -1051,164 +1096,6 @@ static inline bool spi_is_ready_iodev(const struct rtio_iodev *spi_iodev) return spi_is_ready_dt(spec); } -/** - * @brief Copy the tx_bufs and rx_bufs into a set of RTIO requests - * - * @param[in] r rtio context - * @param[in] iodev iodev to transceive with - * @param[in] tx_bufs transmit buffer set - * @param[in] rx_bufs receive buffer set - * @param[out] last_sqe last sqe submitted, NULL if not enough memory - * - * @retval Number of submission queue entries - * @retval -ENOMEM out of memory - */ -static inline int spi_rtio_copy(struct rtio *r, - struct rtio_iodev *iodev, - const struct spi_buf_set *tx_bufs, - const struct spi_buf_set *rx_bufs, - struct rtio_sqe **last_sqe) -{ - int ret = 0; - size_t tx_count = tx_bufs ? tx_bufs->count : 0; - size_t rx_count = rx_bufs ? rx_bufs->count : 0; - - uint32_t tx = 0, tx_len = 0; - uint32_t rx = 0, rx_len = 0; - uint8_t *tx_buf, *rx_buf; - - struct rtio_sqe *sqe = NULL; - - if (tx < tx_count) { - tx_buf = tx_bufs->buffers[tx].buf; - tx_len = tx_bufs->buffers[tx].len; - } else { - tx_buf = NULL; - tx_len = rx_bufs->buffers[rx].len; - } - - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = tx_bufs->buffers[tx].len; - } - - - while ((tx < tx_count || rx < rx_count) && (tx_len > 0 || rx_len > 0)) { - sqe = rtio_sqe_acquire(r); - - if (sqe == NULL) { - ret = -ENOMEM; - rtio_sqe_drop_all(r); - goto out; - } - - ret++; - - /* If tx/rx len are same, we can do a simple transceive */ - if (tx_len == rx_len) { - if (tx_buf == NULL) { - rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, - rx_buf, rx_len, NULL); - } else if (rx_buf == NULL) { - rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, - tx_buf, tx_len, NULL); - } else { - rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, - tx_buf, rx_buf, rx_len, NULL); - } - tx++; - rx++; - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = 0; - } - if (tx < tx_count) { - tx_buf = tx_bufs->buffers[tx].buf; - tx_len = tx_bufs->buffers[tx].len; - } else { - tx_buf = NULL; - tx_len = 0; - } - } else if (tx_len == 0) { - rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)rx_buf, - (uint32_t)rx_len, - NULL); - rx++; - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = 0; - } - } else if (rx_len == 0) { - rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)tx_buf, - (uint32_t)tx_len, - NULL); - tx++; - if (tx < tx_count) { - tx_buf = rx_bufs->buffers[rx].buf; - tx_len = rx_bufs->buffers[rx].len; - } else { - tx_buf = NULL; - tx_len = 0; - } - } else if (tx_len > rx_len) { - rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)tx_buf, - (uint8_t *)rx_buf, - (uint32_t)rx_len, - NULL); - tx_len -= rx_len; - tx_buf += rx_len; - rx++; - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = tx_len; - } - } else if (rx_len > tx_len) { - rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)tx_buf, - (uint8_t *)rx_buf, - (uint32_t)tx_len, - NULL); - rx_len -= tx_len; - rx_buf += tx_len; - tx++; - if (tx < tx_count) { - tx_buf = tx_bufs->buffers[tx].buf; - tx_len = tx_bufs->buffers[tx].len; - } else { - tx_buf = NULL; - tx_len = rx_len; - } - } else { - __ASSERT_NO_MSG("Invalid spi_rtio_copy state"); - } - - sqe->flags = RTIO_SQE_TRANSACTION; - } - - if (sqe != NULL) { - sqe->flags = 0; - *last_sqe = sqe; - } - -out: - return ret; -} - #endif /* CONFIG_SPI_RTIO */ /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi/rtio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi/rtio.h new file mode 100644 index 00000000..04d5bad8 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/spi/rtio.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2024 Croxel, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_SPI_RTIO_H_ +#define ZEPHYR_DRIVERS_SPI_RTIO_H_ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Driver context for implementing SPI with RTIO + */ +struct spi_rtio { + struct k_spinlock lock; + struct rtio *r; + struct mpsc io_q; + struct rtio_iodev iodev; + struct rtio_iodev_sqe *txn_head; + struct rtio_iodev_sqe *txn_curr; + struct spi_dt_spec dt_spec; +}; + +/** + * @brief Statically define a spi_rtio context + * + * @param _name Symbolic name of the context + * @param _sq_sz Submission queue entry pool size + * @param _cq_sz Completion queue entry pool size + */ +#define SPI_RTIO_DEFINE(_name, _sq_sz, _cq_sz) \ + RTIO_DEFINE(CONCAT(_name, _r), _sq_sz, _cq_sz); \ + static struct spi_rtio _name = { \ + .r = &CONCAT(_name, _r), \ + }; + +/** + * @brief Copy the tx_bufs and rx_bufs into a set of RTIO requests + * + * @param[in] r rtio context + * @param[in] iodev iodev to transceive with + * @param[in] tx_bufs transmit buffer set + * @param[in] rx_bufs receive buffer set + * @param[out] last_sqe last sqe submitted, NULL if not enough memory + * + * @retval Number of submission queue entries + * @retval -ENOMEM out of memory + */ +int spi_rtio_copy(struct rtio *r, + struct rtio_iodev *iodev, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + struct rtio_sqe **last_sqe); + +/** + * @brief Initialize a SPI RTIO context + * + * @param ctx SPI RTIO driver context + * @param dev SPI bus + */ +void spi_rtio_init(struct spi_rtio *ctx, const struct device *dev); + +/** + * @brief Signal that the current (ctx->txn_curr) submission has been completed + * + * @param ctx SPI RTIO driver context + * @param status Completion status, negative values are errors + * + * @retval true Next submission is ready to start + * @retval false No more submissions to work on + */ +bool spi_rtio_complete(struct spi_rtio *ctx, int status); + +/** + * @brief Submit, atomically, a submission to work on at some point + * + * @retval true Next submission is ready to start + * @retval false No new submission to start or submissions are in progress already + */ +bool spi_rtio_submit(struct spi_rtio *ctx, struct rtio_iodev_sqe *iodev_sqe); + +/** + * @brief Perform a SPI Transfer (transceive) in a blocking call + * + * Provides a compatible API for the existing spi_transceive API by blocking + * the caller until the operation is complete. + * For details see @ref spi_transceive. + */ +int spi_rtio_transceive(struct spi_rtio *ctx, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs); + +/** + * @brief Fallback SPI RTIO submit implementation. + * + * Default RTIO SPI implementation for drivers who do no yet have + * native support. For details, see @ref spi_iodev_submit. + */ +void spi_rtio_iodev_default_submit(const struct device *dev, + struct rtio_iodev_sqe *iodev_sqe); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_DRIVERS_SPI_RTIO_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper.h new file mode 100644 index 00000000..0257f51b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper.h @@ -0,0 +1,483 @@ +/** + * @file drivers/stepper.h + * + * @brief Public API for Stepper Driver + * + */ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG + * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_ +#define ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_ + +/** + * @brief Stepper Controller Interface + * @defgroup stepper_interface Stepper Controller Interface + * @ingroup io_interfaces + * @{ + */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define MICRO_STEP_RES_INDEX(res) LOG2(res) + +/** + * @brief Stepper Motor micro step resolution options + */ +enum stepper_micro_step_resolution { + /** Full step resolution */ + STEPPER_MICRO_STEP_1 = 1, + /** 2 micro steps per full step */ + STEPPER_MICRO_STEP_2 = 2, + /** 4 micro steps per full step */ + STEPPER_MICRO_STEP_4 = 4, + /** 8 micro steps per full step */ + STEPPER_MICRO_STEP_8 = 8, + /** 16 micro steps per full step */ + STEPPER_MICRO_STEP_16 = 16, + /** 32 micro steps per full step */ + STEPPER_MICRO_STEP_32 = 32, + /** 64 micro steps per full step */ + STEPPER_MICRO_STEP_64 = 64, + /** 128 micro steps per full step */ + STEPPER_MICRO_STEP_128 = 128, + /** 256 micro steps per full step */ + STEPPER_MICRO_STEP_256 = 256, +}; + +/** + * @brief Stepper Motor direction options + */ +enum stepper_direction { + /** Negative direction */ + STEPPER_DIRECTION_NEGATIVE = 0, + /** Positive direction */ + STEPPER_DIRECTION_POSITIVE = 1, +}; + +/** + * @brief Stepper Motor run mode options + */ +enum stepper_run_mode { + /** Hold Mode */ + STEPPER_RUN_MODE_HOLD = 0, + /** Position Mode*/ + STEPPER_RUN_MODE_POSITION = 1, + /** Velocity Mode */ + STEPPER_RUN_MODE_VELOCITY = 2, +}; + +/** + * @brief Stepper Events + */ +enum stepper_event { + /** Steps set using move or set_target_position have been executed */ + STEPPER_EVENT_STEPS_COMPLETED = 0, + /** Stall detected */ + STEPPER_EVENT_STALL_DETECTED = 1, + /** Left end switch status changes to pressed */ + STEPPER_EVENT_LEFT_END_STOP_DETECTED = 2, + /** Right end switch status changes to pressed */ + STEPPER_EVENT_RIGHT_END_STOP_DETECTED = 3, +}; + +/** + * @cond INTERNAL_HIDDEN + * + * Stepper motor controller driver API definition and system call entry points. + * + */ + +/** + * @brief enable or disable the stepper motor controller. + * + * @see stepper_enable() for details. + */ +typedef int (*stepper_enable_t)(const struct device *dev, const bool enable); + +/** + * @brief Move the stepper motor relatively by a given number of micro_steps. + * + * @see stepper_move_by() for details. + */ +typedef int (*stepper_move_by_t)(const struct device *dev, const int32_t micro_steps); + +/** + * @brief Set the max velocity in micro_steps per seconds. + * + * @see stepper_set_max_velocity() for details. + */ +typedef int (*stepper_set_max_velocity_t)(const struct device *dev, + const uint32_t micro_steps_per_second); + +/** + * @brief Set the micro-step resolution + * + * @see stepper_set_micro_step_res() for details. + */ +typedef int (*stepper_set_micro_step_res_t)(const struct device *dev, + const enum stepper_micro_step_resolution resolution); + +/** + * @brief Get the micro-step resolution + * + * @see stepper_get_micro_step_res() for details. + */ +typedef int (*stepper_get_micro_step_res_t)(const struct device *dev, + enum stepper_micro_step_resolution *resolution); +/** + * @brief Set the reference position of the stepper + * + * @see stepper_set_actual_position() for details. + */ +typedef int (*stepper_set_reference_position_t)(const struct device *dev, const int32_t value); + +/** + * @brief Get the actual a.k.a reference position of the stepper + * + * @see stepper_get_actual_position() for details. + */ +typedef int (*stepper_get_actual_position_t)(const struct device *dev, int32_t *value); + +/** + * @brief Move the stepper motor absolutely by a given number of micro_steps. + * + * @see stepper_move_to() for details. + */ +typedef int (*stepper_move_to_t)(const struct device *dev, const int32_t micro_steps); + +/** + * @brief Is the target position fo the stepper reached + * + * @see stepper_is_moving() for details. + */ +typedef int (*stepper_is_moving_t)(const struct device *dev, bool *is_moving); + +/** + * @brief Run the stepper with a given velocity in a given direction + * + * @see stepper_run() for details. + */ +typedef int (*stepper_run_t)(const struct device *dev, const enum stepper_direction direction, + const uint32_t value); + +/** + * @brief Callback function for stepper events + */ +typedef void (*stepper_event_callback_t)(const struct device *dev, const enum stepper_event event, + void *user_data); + +/** + * @brief Set the callback function to be called when a stepper event occurs + * + * @see stepper_set_event_callback() for details. + */ +typedef int (*stepper_set_event_callback_t)(const struct device *dev, + stepper_event_callback_t callback, void *user_data); + +/** + * @brief Stepper Motor Controller API + */ +__subsystem struct stepper_driver_api { + stepper_enable_t enable; + stepper_move_by_t move_by; + stepper_set_max_velocity_t set_max_velocity; + stepper_set_micro_step_res_t set_micro_step_res; + stepper_get_micro_step_res_t get_micro_step_res; + stepper_set_reference_position_t set_reference_position; + stepper_get_actual_position_t get_actual_position; + stepper_move_to_t move_to; + stepper_is_moving_t is_moving; + stepper_run_t run; + stepper_set_event_callback_t set_event_callback; +}; + +/** + * @endcond + */ + +/** + * @brief Enable or Disable Motor Controller + * + * @param dev pointer to the stepper motor controller instance + * @param enable Input enable or disable motor controller + * + * @retval -EIO Error during Enabling + * @retval 0 Success + */ +__syscall int stepper_enable(const struct device *dev, const bool enable); + +static inline int z_impl_stepper_enable(const struct device *dev, const bool enable) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + return api->enable(dev, enable); +} + +/** + * @brief Set the micro_steps to be moved from the current position i.e. relative movement + * + * @details The motor will move by the given number of micro_steps from the current position. + * This function is non-blocking. + * + * @param dev pointer to the stepper motor controller instance + * @param micro_steps target micro_steps to be moved from the current position + * + * @retval -EIO General input / output error + * @retval 0 Success + */ +__syscall int stepper_move_by(const struct device *dev, int32_t micro_steps); + +static inline int z_impl_stepper_move_by(const struct device *dev, const int32_t micro_steps) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + return api->move_by(dev, micro_steps); +} + +/** + * @brief Set the target velocity to be reached by the motor + * + * @details For controllers such as DRV8825 where you + * toggle the STEP Pin, the pulse_length would have to be calculated based on this parameter in the + * driver. For controllers where velocity can be set, this parameter corresponds to max_velocity + * @note Setting max velocity does not set the motor into motion, a combination of set_max_velocity + * and move is required to set the motor into motion. + * + * @param dev pointer to the stepper motor controller instance + * @param micro_steps_per_second speed in micro_steps per second + * + * @retval -EIO General input / output error + * @retval -EINVAL If the requested velocity is not supported + * @retval 0 Success + */ +__syscall int stepper_set_max_velocity(const struct device *dev, uint32_t micro_steps_per_second); + +static inline int z_impl_stepper_set_max_velocity(const struct device *dev, + const uint32_t micro_steps_per_second) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + return api->set_max_velocity(dev, micro_steps_per_second); +} + +/** + * @brief Set the microstep resolution in stepper motor controller + * + * @param dev pointer to the stepper motor controller instance + * @param resolution microstep resolution + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval -ENOTSUP If the requested resolution is not supported + * @retval 0 Success + */ +__syscall int stepper_set_micro_step_res(const struct device *dev, + enum stepper_micro_step_resolution resolution); + +static inline int z_impl_stepper_set_micro_step_res(const struct device *dev, + enum stepper_micro_step_resolution resolution) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->set_micro_step_res == NULL) { + return -ENOSYS; + } + return api->set_micro_step_res(dev, resolution); +} + +/** + * @brief Get the microstep resolution in stepper motor controller + * + * @param dev pointer to the stepper motor controller instance + * @param resolution microstep resolution + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_get_micro_step_res(const struct device *dev, + enum stepper_micro_step_resolution *resolution); + +static inline int z_impl_stepper_get_micro_step_res(const struct device *dev, + enum stepper_micro_step_resolution *resolution) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->get_micro_step_res == NULL) { + return -ENOSYS; + } + return api->get_micro_step_res(dev, resolution); +} + +/** + * @brief Set the reference position of the stepper + * + * @param dev Pointer to the stepper motor controller instance. + * @param value The reference position to set in micro-steps. + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_set_reference_position(const struct device *dev, int32_t value); + +static inline int z_impl_stepper_set_reference_position(const struct device *dev, + const int32_t value) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->set_reference_position == NULL) { + return -ENOSYS; + } + return api->set_reference_position(dev, value); +} + +/** + * @brief Get the actual a.k.a reference position of the stepper + * + * @param dev pointer to the stepper motor controller instance + * @param value The actual position to get in micro_steps + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_get_actual_position(const struct device *dev, int32_t *value); + +static inline int z_impl_stepper_get_actual_position(const struct device *dev, int32_t *value) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->get_actual_position == NULL) { + return -ENOSYS; + } + return api->get_actual_position(dev, value); +} + +/** + * @brief Set the absolute target position of the stepper + * + * @details The motor will move to the given micro_steps position from the reference position. + * This function is non-blocking. + * + * @param dev pointer to the stepper motor controller instance + * @param micro_steps target position to set in micro_steps + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_move_to(const struct device *dev, int32_t micro_steps); + +static inline int z_impl_stepper_move_to(const struct device *dev, const int32_t micro_steps) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->move_to == NULL) { + return -ENOSYS; + } + return api->move_to(dev, micro_steps); +} + +/** + * @brief Check if the stepper motor is currently moving + * + * @param dev pointer to the stepper motor controller instance + * @param is_moving Pointer to a boolean to store the moving status of the stepper motor + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_is_moving(const struct device *dev, bool *is_moving); + +static inline int z_impl_stepper_is_moving(const struct device *dev, bool *is_moving) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->is_moving == NULL) { + return -ENOSYS; + } + return api->is_moving(dev, is_moving); +} + +/** + * @brief Run the stepper with a given velocity in a given direction + * + * @details If velocity > 0, motor shall be set into motion and run incessantly until and unless + * stalled or stopped using some other command, for instance, motor_enable(false). + * This function is non-blocking. + * + * @param dev pointer to the stepper motor controller instance + * @param direction The direction to set + * @param velocity The velocity to set in microsteps per second + * - > 0: Run the stepper with the given velocity in a given direction + * - 0: Stop the stepper + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_run(const struct device *dev, enum stepper_direction direction, + uint32_t velocity); + +static inline int z_impl_stepper_run(const struct device *dev, + const enum stepper_direction direction, + const uint32_t velocity) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->run == NULL) { + return -ENOSYS; + } + return api->run(dev, direction, velocity); +} + +/** + * @brief Set the callback function to be called when a stepper event occurs + * + * @param dev pointer to the stepper motor controller instance + * @param callback Callback function to be called when a stepper event occurs + * passing NULL will disable the callback + * @param user_data User data to be passed to the callback function + * + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +__syscall int stepper_set_event_callback(const struct device *dev, + stepper_event_callback_t callback, void *user_data); + +static inline int z_impl_stepper_set_event_callback(const struct device *dev, + stepper_event_callback_t callback, + void *user_data) +{ + const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api; + + if (api->set_event_callback == NULL) { + return -ENOSYS; + } + return api->set_event_callback(dev, callback, user_data); +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#include + +#endif /* ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper/stepper_fake.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper/stepper_fake.h new file mode 100644 index 00000000..292fdbc0 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper/stepper_fake.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2024 Fabian Blatz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_STEPPER_STEPPER_FAKE_H_ +#define ZEPHYR_INCLUDE_DRIVERS_STEPPER_STEPPER_FAKE_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_enable, const struct device *, bool); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_move_by, const struct device *, int32_t); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_max_velocity, const struct device *, uint32_t); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_micro_step_res, const struct device *, + enum stepper_micro_step_resolution); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_get_micro_step_res, const struct device *, + enum stepper_micro_step_resolution *); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_reference_position, const struct device *, int32_t); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_get_actual_position, const struct device *, int32_t *); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_move_to, const struct device *, int32_t); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_is_moving, const struct device *, bool *); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_run, const struct device *, enum stepper_direction, + uint32_t); + +DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_event_callback, const struct device *, + stepper_event_callback_t, void *); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_STEPPER_STEPPER_FAKE_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper/stepper_trinamic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper/stepper_trinamic.h new file mode 100644 index 00000000..6afe8c92 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/stepper/stepper_trinamic.h @@ -0,0 +1,173 @@ +/** + * @file drivers/stepper/stepper_trinamic.h + * + * @brief Public API for Trinamic Stepper Controller Specific Functions + * + */ + +/* + * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_STEPPER_STEPPER_TRINAMIC_H_ +#define ZEPHYR_INCLUDE_DRIVERS_STEPPER_STEPPER_TRINAMIC_H_ + +/** + * @brief Trinamic Stepper Controller Interface + * @defgroup trinamic_stepper_interface Trinamic Stepper Controller Interface + * @ingroup stepper_interface + * @{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Trinamic stepper controller ramp generator data limits + */ +#define TMC_RAMP_VSTART_MAX GENMASK(17, 0) +#define TMC_RAMP_VSTART_MIN 0 +#define TMC_RAMP_V1_MAX GENMASK(19, 0) +#define TMC_RAMP_V1_MIN 0 +#define TMC_RAMP_VMAX_MAX (GENMASK(22, 0) - 512) +#define TMC_RAMP_VMAX_MIN 0 +#define TMC_RAMP_A1_MAX GENMASK(15, 0) +#define TMC_RAMP_A1_MIN 0 +#define TMC_RAMP_AMAX_MAX GENMASK(15, 0) +#define TMC_RAMP_AMAX_MIN 0 +#define TMC_RAMP_D1_MAX GENMASK(15, 0) +#define TMC_RAMP_D1_MIN 1 +#define TMC_RAMP_DMAX_MAX GENMASK(15, 0) +#define TMC_RAMP_DMAX_MIN 0 +#define TMC_RAMP_VSTOP_MAX GENMASK(17, 0) +#define TMC_RAMP_VSTOP_MIN 1 +#define TMC_RAMP_TZEROWAIT_MAX (GENMASK(15, 0) - 512) +#define TMC_RAMP_TZEROWAIT_MIN 0 +#define TMC_RAMP_VCOOLTHRS_MAX GENMASK(22, 0) +#define TMC_RAMP_VCOOLTHRS_MIN 0 +#define TMC_RAMP_VHIGH_MAX GENMASK(22, 0) +#define TMC_RAMP_VHIGH_MIN 0 +#define TMC_RAMP_IHOLD_IRUN_MAX GENMASK(4, 0) +#define TMC_RAMP_IHOLD_IRUN_MIN 0 +#define TMC_RAMP_IHOLDDELAY_MAX GENMASK(3, 0) +#define TMC_RAMP_IHOLDDELAY_MIN 0 +#define TMC_RAMP_VACTUAL_SHIFT 22 + +/** + * @brief Trinamic Stepper Ramp Generator data + */ +struct tmc_ramp_generator_data { + uint32_t vstart; + uint32_t v1; + uint32_t vmax; + uint16_t a1; + uint16_t amax; + uint16_t d1; + uint16_t dmax; + uint32_t vstop; + uint16_t tzerowait; + uint32_t vcoolthrs; + uint32_t vhigh; + uint32_t iholdrun; +}; + +/** + * @brief Check if Ramp DT data is within limits + */ +#define CHECK_RAMP_DT_DATA(node) \ + COND_CODE_1(DT_PROP_EXISTS(node, vstart), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, vstart), TMC_RAMP_VSTART_MIN, \ + TMC_RAMP_VSTART_MAX), "vstart out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, v1), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, v1), TMC_RAMP_V1_MIN, \ + TMC_RAMP_V1_MAX), "v1 out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, vmax), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, vmax), TMC_RAMP_VMAX_MIN, \ + TMC_RAMP_VMAX_MAX), "vmax out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, a1), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, a1), TMC_RAMP_A1_MIN, \ + TMC_RAMP_A1_MAX), "a1 out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, amax), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, amax), TMC_RAMP_AMAX_MIN, \ + TMC_RAMP_AMAX_MAX), "amax out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, d1), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, d1), TMC_RAMP_D1_MIN, \ + TMC_RAMP_D1_MAX), "d1 out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, dmax), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, dmax), TMC_RAMP_DMAX_MIN, \ + TMC_RAMP_DMAX_MAX), "dmax out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, vstop), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, vstop), TMC_RAMP_VSTOP_MIN, \ + TMC_RAMP_VSTOP_MAX), "vstop out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, tzerowait), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, tzerowait), TMC_RAMP_TZEROWAIT_MIN, \ + TMC_RAMP_TZEROWAIT_MAX), "tzerowait out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, vcoolthrs), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, vcoolthrs), TMC_RAMP_VCOOLTHRS_MIN, \ + TMC_RAMP_VCOOLTHRS_MAX), "vcoolthrs out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, vhigh), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, vhigh), TMC_RAMP_VHIGH_MIN, \ + TMC_RAMP_VHIGH_MAX), "vhigh out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, ihold), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, ihold), TMC_RAMP_IHOLD_IRUN_MIN, \ + TMC_RAMP_IHOLD_IRUN_MAX), "ihold out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, irun), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, irun), TMC_RAMP_IHOLD_IRUN_MIN, \ + TMC_RAMP_IHOLD_IRUN_MAX), "irun out of range"), ()); \ + COND_CODE_1(DT_PROP_EXISTS(node, iholddelay), \ + BUILD_ASSERT(IN_RANGE(DT_PROP(node, iholddelay), TMC_RAMP_IHOLDDELAY_MIN, \ + TMC_RAMP_IHOLDDELAY_MAX), "iholddelay out of range"), ()); + +/** + * @brief Get Trinamic Stepper Ramp Generator data from DT + * + * @param node DT node identifier + * + * @return struct tmc_ramp_generator_data + */ +#define TMC_RAMP_DT_SPEC_GET(node) \ + { \ + .vstart = DT_PROP(node, vstart), \ + .v1 = DT_PROP(node, v1), \ + .vmax = DT_PROP(node, vmax), \ + .a1 = DT_PROP(node, a1), \ + .amax = DT_PROP(node, amax), \ + .d1 = DT_PROP(node, d1), \ + .dmax = DT_PROP(node, dmax), \ + .vstop = DT_PROP(node, vstop), \ + .tzerowait = DT_PROP(node, tzerowait), \ + .vcoolthrs = DT_PROP(node, vcoolthrs), \ + .vhigh = DT_PROP(node, vhigh), \ + .iholdrun = (TMC5XXX_IRUN(DT_PROP(node, irun)) | \ + TMC5XXX_IHOLD(DT_PROP(node, ihold)) | \ + TMC5XXX_IHOLDDELAY(DT_PROP(node, iholddelay))), \ + } + +/** + * @brief Configure Trinamic Stepper Ramp Generator + * + * @param dev Pointer to the stepper motor controller instance + * @param ramp_data Pointer to a struct containing the required ramp parameters + * + * @retval -EIO General input / output error + * @retval -ENOSYS If not implemented by device driver + * @retval 0 Success + */ +int tmc5041_stepper_set_ramp(const struct device *dev, + const struct tmc_ramp_generator_data *ramp_data); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_DRIVERS_STEPPER_STEPPER_TRINAMIC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart.h index 845949ea..d6ce894c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart.h @@ -22,7 +22,6 @@ * @{ */ -#include #include #include @@ -141,13 +140,6 @@ struct uart_config { typedef void (*uart_irq_callback_user_data_t)(const struct device *dev, void *user_data); -/** - * @brief For configuring IRQ on each individual UART device. - * - * @param dev UART device instance. - */ -typedef void (*uart_irq_config_func_t)(const struct device *dev); - /** * @} * @@ -328,135 +320,6 @@ typedef void (*uart_callback_t)(const struct device *dev, * @} */ -/** - * @cond INTERNAL_HIDDEN - * - * For internal driver use only, skip these in public documentation. - */ - -/** @brief Driver API structure. */ -__subsystem struct uart_driver_api { - -#ifdef CONFIG_UART_ASYNC_API - - int (*callback_set)(const struct device *dev, - uart_callback_t callback, - void *user_data); - - int (*tx)(const struct device *dev, const uint8_t *buf, size_t len, - int32_t timeout); - int (*tx_abort)(const struct device *dev); - - int (*rx_enable)(const struct device *dev, uint8_t *buf, size_t len, - int32_t timeout); - int (*rx_buf_rsp)(const struct device *dev, uint8_t *buf, size_t len); - int (*rx_disable)(const struct device *dev); - -#ifdef CONFIG_UART_WIDE_DATA - int (*tx_u16)(const struct device *dev, const uint16_t *buf, - size_t len, int32_t timeout); - int (*rx_enable_u16)(const struct device *dev, uint16_t *buf, - size_t len, int32_t timeout); - int (*rx_buf_rsp_u16)(const struct device *dev, uint16_t *buf, - size_t len); -#endif - -#endif - - /** Console I/O function */ - int (*poll_in)(const struct device *dev, unsigned char *p_char); - void (*poll_out)(const struct device *dev, unsigned char out_char); - -#ifdef CONFIG_UART_WIDE_DATA - int (*poll_in_u16)(const struct device *dev, uint16_t *p_u16); - void (*poll_out_u16)(const struct device *dev, uint16_t out_u16); -#endif - - /** Console I/O function */ - int (*err_check)(const struct device *dev); - -#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE - /** UART configuration functions */ - int (*configure)(const struct device *dev, - const struct uart_config *cfg); - int (*config_get)(const struct device *dev, struct uart_config *cfg); -#endif - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - - /** Interrupt driven FIFO fill function */ - int (*fifo_fill)(const struct device *dev, const uint8_t *tx_data, - int len); - -#ifdef CONFIG_UART_WIDE_DATA - int (*fifo_fill_u16)(const struct device *dev, const uint16_t *tx_data, - int len); -#endif - - /** Interrupt driven FIFO read function */ - int (*fifo_read)(const struct device *dev, uint8_t *rx_data, - const int size); - -#ifdef CONFIG_UART_WIDE_DATA - int (*fifo_read_u16)(const struct device *dev, uint16_t *rx_data, - const int size); -#endif - - /** Interrupt driven transfer enabling function */ - void (*irq_tx_enable)(const struct device *dev); - - /** Interrupt driven transfer disabling function */ - void (*irq_tx_disable)(const struct device *dev); - - /** Interrupt driven transfer ready function */ - int (*irq_tx_ready)(const struct device *dev); - - /** Interrupt driven receiver enabling function */ - void (*irq_rx_enable)(const struct device *dev); - - /** Interrupt driven receiver disabling function */ - void (*irq_rx_disable)(const struct device *dev); - - /** Interrupt driven transfer complete function */ - int (*irq_tx_complete)(const struct device *dev); - - /** Interrupt driven receiver ready function */ - int (*irq_rx_ready)(const struct device *dev); - - /** Interrupt driven error enabling function */ - void (*irq_err_enable)(const struct device *dev); - - /** Interrupt driven error disabling function */ - void (*irq_err_disable)(const struct device *dev); - - /** Interrupt driven pending status function */ - int (*irq_is_pending)(const struct device *dev); - - /** Interrupt driven interrupt update function */ - int (*irq_update)(const struct device *dev); - - /** Set the irq callback function */ - void (*irq_callback_set)(const struct device *dev, - uart_irq_callback_user_data_t cb, - void *user_data); - -#endif - -#ifdef CONFIG_UART_LINE_CTRL - int (*line_ctrl_set)(const struct device *dev, uint32_t ctrl, - uint32_t val); - int (*line_ctrl_get)(const struct device *dev, uint32_t ctrl, - uint32_t *val); -#endif - -#ifdef CONFIG_UART_DRV_CMD - int (*drv_cmd)(const struct device *dev, uint32_t cmd, uint32_t p); -#endif - -}; - -/** @endcond */ - /** * @brief Check whether an error was detected. * @@ -468,18 +331,6 @@ __subsystem struct uart_driver_api { */ __syscall int uart_err_check(const struct device *dev); -static inline int z_impl_uart_err_check(const struct device *dev) -{ - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->err_check == NULL) { - return -ENOSYS; - } - - return api->err_check(dev); -} - /** * @defgroup uart_polling Polling UART API * @{ @@ -505,19 +356,6 @@ static inline int z_impl_uart_err_check(const struct device *dev) */ __syscall int uart_poll_in(const struct device *dev, unsigned char *p_char); -static inline int z_impl_uart_poll_in(const struct device *dev, - unsigned char *p_char) -{ - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->poll_in == NULL) { - return -ENOSYS; - } - - return api->poll_in(dev, p_char); -} - /** * @brief Read a 16-bit datum from the device for input. * @@ -539,32 +377,14 @@ static inline int z_impl_uart_poll_in(const struct device *dev, */ __syscall int uart_poll_in_u16(const struct device *dev, uint16_t *p_u16); -static inline int z_impl_uart_poll_in_u16(const struct device *dev, - uint16_t *p_u16) -{ -#ifdef CONFIG_UART_WIDE_DATA - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->poll_in_u16 == NULL) { - return -ENOSYS; - } - - return api->poll_in_u16(dev, p_u16); -#else - ARG_UNUSED(dev); - ARG_UNUSED(p_u16); - return -ENOTSUP; -#endif -} - /** * @brief Write a character to the device for output. * - * This routine checks if the transmitter is full. When the + * This routine checks if the transmitter is full. When the * transmitter is not full, it writes a character to the data - * register. It waits and blocks the calling thread, otherwise. This - * function is a blocking call. + * register. It waits and blocks the calling thread otherwise. This + * function is a blocking call. It blocks the calling thread until the + * character is sent. * * To send a character when hardware flow control is enabled, the handshake * signal CTS must be asserted. @@ -575,15 +395,6 @@ static inline int z_impl_uart_poll_in_u16(const struct device *dev, __syscall void uart_poll_out(const struct device *dev, unsigned char out_char); -static inline void z_impl_uart_poll_out(const struct device *dev, - unsigned char out_char) -{ - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - api->poll_out(dev, out_char); -} - /** * @brief Write a 16-bit datum to the device for output. * @@ -600,20 +411,6 @@ static inline void z_impl_uart_poll_out(const struct device *dev, */ __syscall void uart_poll_out_u16(const struct device *dev, uint16_t out_u16); -static inline void z_impl_uart_poll_out_u16(const struct device *dev, - uint16_t out_u16) -{ -#ifdef CONFIG_UART_WIDE_DATA - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - api->poll_out_u16(dev, out_u16); -#else - ARG_UNUSED(dev); - ARG_UNUSED(out_u16); -#endif -} - /** * @} */ @@ -635,24 +432,6 @@ static inline void z_impl_uart_poll_out_u16(const struct device *dev, __syscall int uart_configure(const struct device *dev, const struct uart_config *cfg); -static inline int z_impl_uart_configure(const struct device *dev, - const struct uart_config *cfg) -{ -#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->configure == NULL) { - return -ENOSYS; - } - return api->configure(dev, cfg); -#else - ARG_UNUSED(dev); - ARG_UNUSED(cfg); - return -ENOTSUP; -#endif -} - /** * @brief Get UART configuration. * @@ -670,25 +449,6 @@ static inline int z_impl_uart_configure(const struct device *dev, __syscall int uart_config_get(const struct device *dev, struct uart_config *cfg); -static inline int z_impl_uart_config_get(const struct device *dev, - struct uart_config *cfg) -{ -#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->config_get == NULL) { - return -ENOSYS; - } - - return api->config_get(dev, cfg); -#else - ARG_UNUSED(dev); - ARG_UNUSED(cfg); - return -ENOTSUP; -#endif -} - /** * @addtogroup uart_interrupt * @{ @@ -714,26 +474,7 @@ static inline int z_impl_uart_config_get(const struct device *dev, * @retval -ENOSYS if this function is not supported * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_fifo_fill(const struct device *dev, - const uint8_t *tx_data, - int size) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->fifo_fill == NULL) { - return -ENOSYS; - } - - return api->fifo_fill(dev, tx_data, size); -#else - ARG_UNUSED(dev); - ARG_UNUSED(tx_data); - ARG_UNUSED(size); - return -ENOTSUP; -#endif -} +static inline int uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size); /** * @brief Fill FIFO with wide data. @@ -755,26 +496,7 @@ static inline int uart_fifo_fill(const struct device *dev, * @retval -ENOSYS If this function is not implemented * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_fifo_fill_u16(const struct device *dev, - const uint16_t *tx_data, - int size) -{ -#if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_UART_WIDE_DATA) - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->fifo_fill_u16 == NULL) { - return -ENOSYS; - } - - return api->fifo_fill_u16(dev, tx_data, size); -#else - ARG_UNUSED(dev); - ARG_UNUSED(tx_data); - ARG_UNUSED(size); - return -ENOTSUP; -#endif -} +static inline int uart_fifo_fill_u16(const struct device *dev, const uint16_t *tx_data, int size); /** * @brief Read data from FIFO. @@ -797,25 +519,7 @@ static inline int uart_fifo_fill_u16(const struct device *dev, * @retval -ENOSYS If this function is not implemented. * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_fifo_read(const struct device *dev, uint8_t *rx_data, - const int size) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->fifo_read == NULL) { - return -ENOSYS; - } - - return api->fifo_read(dev, rx_data, size); -#else - ARG_UNUSED(dev); - ARG_UNUSED(rx_data); - ARG_UNUSED(size); - return -ENOTSUP; -#endif -} +static inline int uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size); /** * @brief Read wide data from FIFO. @@ -838,26 +542,7 @@ static inline int uart_fifo_read(const struct device *dev, uint8_t *rx_data, * @retval -ENOSYS If this function is not implemented. * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_fifo_read_u16(const struct device *dev, - uint16_t *rx_data, - const int size) -{ -#if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_UART_WIDE_DATA) - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->fifo_read_u16 == NULL) { - return -ENOSYS; - } - - return api->fifo_read_u16(dev, rx_data, size); -#else - ARG_UNUSED(dev); - ARG_UNUSED(rx_data); - ARG_UNUSED(size); - return -ENOTSUP; -#endif -} +static inline int uart_fifo_read_u16(const struct device *dev, uint16_t *rx_data, const int size); /** * @brief Enable TX interrupt in IER. @@ -866,20 +551,6 @@ static inline int uart_fifo_read_u16(const struct device *dev, */ __syscall void uart_irq_tx_enable(const struct device *dev); -static inline void z_impl_uart_irq_tx_enable(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_tx_enable != NULL) { - api->irq_tx_enable(dev); - } -#else - ARG_UNUSED(dev); -#endif -} - /** * @brief Disable TX interrupt in IER. * @@ -887,24 +558,10 @@ static inline void z_impl_uart_irq_tx_enable(const struct device *dev) */ __syscall void uart_irq_tx_disable(const struct device *dev); -static inline void z_impl_uart_irq_tx_disable(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_tx_disable != NULL) { - api->irq_tx_disable(dev); - } -#else - ARG_UNUSED(dev); -#endif -} - /** - * @brief Check if UART TX buffer can accept a new char + * @brief Check if UART TX buffer can accept bytes * - * @details Check if UART TX buffer can accept at least one character + * @details Check if UART TX buffer can accept more bytes * for transmission (i.e. uart_fifo_fill() will succeed and return * non-zero). This function must be called in a UART interrupt * handler, or its result is undefined. Before calling this function @@ -913,28 +570,15 @@ static inline void z_impl_uart_irq_tx_disable(const struct device *dev) * * @param dev UART device instance. * - * @retval 1 If TX interrupt is enabled and at least one char can be - * written to UART. * @retval 0 If device is not ready to write a new byte. + * @retval >0 Minimum number of bytes that can be written in a single call to + * @ref uart_fifo_fill. It may be possible to write more bytes, but + * the actual number written must be checked in the return code from + * @ref uart_fifo_fill. * @retval -ENOSYS If this function is not implemented. * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_irq_tx_ready(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_tx_ready == NULL) { - return -ENOSYS; - } - - return api->irq_tx_ready(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} +static inline int uart_irq_tx_ready(const struct device *dev); /** * @brief Enable RX interrupt. @@ -943,20 +587,6 @@ static inline int uart_irq_tx_ready(const struct device *dev) */ __syscall void uart_irq_rx_enable(const struct device *dev); -static inline void z_impl_uart_irq_rx_enable(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_rx_enable != NULL) { - api->irq_rx_enable(dev); - } -#else - ARG_UNUSED(dev); -#endif -} - /** * @brief Disable RX interrupt. * @@ -964,20 +594,6 @@ static inline void z_impl_uart_irq_rx_enable(const struct device *dev) */ __syscall void uart_irq_rx_disable(const struct device *dev); -static inline void z_impl_uart_irq_rx_disable(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_rx_disable != NULL) { - api->irq_rx_disable(dev); - } -#else - ARG_UNUSED(dev); -#endif -} - /** * @brief Check if UART TX block finished transmission * @@ -997,21 +613,7 @@ static inline void z_impl_uart_irq_rx_disable(const struct device *dev) * @retval -ENOSYS If this function is not implemented. * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_irq_tx_complete(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_tx_complete == NULL) { - return -ENOSYS; - } - return api->irq_tx_complete(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} +static inline int uart_irq_tx_complete(const struct device *dev); /** * @brief Check if UART RX buffer has a received char @@ -1033,21 +635,8 @@ static inline int uart_irq_tx_complete(const struct device *dev) * @retval -ENOSYS If this function is not implemented. * @retval -ENOTSUP If API is not enabled. */ -static inline int uart_irq_rx_ready(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_rx_ready == NULL) { - return -ENOSYS; - } - return api->irq_rx_ready(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} +static inline int uart_irq_rx_ready(const struct device *dev); + /** * @brief Enable error interrupt. * @@ -1055,20 +644,6 @@ static inline int uart_irq_rx_ready(const struct device *dev) */ __syscall void uart_irq_err_enable(const struct device *dev); -static inline void z_impl_uart_irq_err_enable(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_err_enable) { - api->irq_err_enable(dev); - } -#else - ARG_UNUSED(dev); -#endif -} - /** * @brief Disable error interrupt. * @@ -1076,20 +651,6 @@ static inline void z_impl_uart_irq_err_enable(const struct device *dev) */ __syscall void uart_irq_err_disable(const struct device *dev); -static inline void z_impl_uart_irq_err_disable(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_err_disable) { - api->irq_err_disable(dev); - } -#else - ARG_UNUSED(dev); -#endif -} - /** * @brief Check if any IRQs is pending. * @@ -1102,22 +663,6 @@ static inline void z_impl_uart_irq_err_disable(const struct device *dev) */ __syscall int uart_irq_is_pending(const struct device *dev); -static inline int z_impl_uart_irq_is_pending(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_is_pending == NULL) { - return -ENOSYS; - } - return api->irq_is_pending(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} - /** * @brief Start processing interrupts in ISR. * @@ -1145,22 +690,6 @@ static inline int z_impl_uart_irq_is_pending(const struct device *dev) */ __syscall int uart_irq_update(const struct device *dev); -static inline int z_impl_uart_irq_update(const struct device *dev) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->irq_update == NULL) { - return -ENOSYS; - } - return api->irq_update(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} - /** * @brief Set the IRQ callback function pointer. * @@ -1178,25 +707,7 @@ static inline int z_impl_uart_irq_update(const struct device *dev) */ static inline int uart_irq_callback_user_data_set(const struct device *dev, uart_irq_callback_user_data_t cb, - void *user_data) -{ -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if ((api != NULL) && (api->irq_callback_set != NULL)) { - api->irq_callback_set(dev, cb, user_data); - return 0; - } else { - return -ENOSYS; - } -#else - ARG_UNUSED(dev); - ARG_UNUSED(cb); - ARG_UNUSED(user_data); - return -ENOTSUP; -#endif -} + void *user_data); /** * @brief Set the IRQ callback function pointer (legacy). @@ -1212,10 +723,7 @@ static inline int uart_irq_callback_user_data_set(const struct device *dev, * @retval -ENOTSUP If API is not enabled. */ static inline int uart_irq_callback_set(const struct device *dev, - uart_irq_callback_user_data_t cb) -{ - return uart_irq_callback_user_data_set(dev, cb, NULL); -} + uart_irq_callback_user_data_t cb); /** * @} @@ -1243,24 +751,7 @@ static inline int uart_irq_callback_set(const struct device *dev, */ static inline int uart_callback_set(const struct device *dev, uart_callback_t callback, - void *user_data) -{ -#ifdef CONFIG_UART_ASYNC_API - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->callback_set == NULL) { - return -ENOSYS; - } - - return api->callback_set(dev, callback, user_data); -#else - ARG_UNUSED(dev); - ARG_UNUSED(callback); - ARG_UNUSED(user_data); - return -ENOTSUP; -#endif -} + void *user_data); /** * @brief Send given number of bytes from buffer through UART. @@ -1283,24 +774,6 @@ __syscall int uart_tx(const struct device *dev, const uint8_t *buf, size_t len, int32_t timeout); -static inline int z_impl_uart_tx(const struct device *dev, const uint8_t *buf, - size_t len, int32_t timeout) - -{ -#ifdef CONFIG_UART_ASYNC_API - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->tx(dev, buf, len, timeout); -#else - ARG_UNUSED(dev); - ARG_UNUSED(buf); - ARG_UNUSED(len); - ARG_UNUSED(timeout); - return -ENOTSUP; -#endif -} - /** * @brief Send given number of datum from buffer through UART. * @@ -1321,25 +794,6 @@ static inline int z_impl_uart_tx(const struct device *dev, const uint8_t *buf, __syscall int uart_tx_u16(const struct device *dev, const uint16_t *buf, size_t len, int32_t timeout); -static inline int z_impl_uart_tx_u16(const struct device *dev, - const uint16_t *buf, - size_t len, int32_t timeout) - -{ -#if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_WIDE_DATA) - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->tx_u16(dev, buf, len, timeout); -#else - ARG_UNUSED(dev); - ARG_UNUSED(buf); - ARG_UNUSED(len); - ARG_UNUSED(timeout); - return -ENOTSUP; -#endif -} - /** * @brief Abort current TX transmission. * @@ -1354,19 +808,6 @@ static inline int z_impl_uart_tx_u16(const struct device *dev, */ __syscall int uart_tx_abort(const struct device *dev); -static inline int z_impl_uart_tx_abort(const struct device *dev) -{ -#ifdef CONFIG_UART_ASYNC_API - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->tx_abort(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} - /** * @brief Start receiving data through UART. * @@ -1392,24 +833,6 @@ __syscall int uart_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int32_t timeout); -static inline int z_impl_uart_rx_enable(const struct device *dev, - uint8_t *buf, - size_t len, int32_t timeout) -{ -#ifdef CONFIG_UART_ASYNC_API - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->rx_enable(dev, buf, len, timeout); -#else - ARG_UNUSED(dev); - ARG_UNUSED(buf); - ARG_UNUSED(len); - ARG_UNUSED(timeout); - return -ENOTSUP; -#endif -} - /** * @brief Start receiving wide data through UART. * @@ -1434,24 +857,6 @@ static inline int z_impl_uart_rx_enable(const struct device *dev, __syscall int uart_rx_enable_u16(const struct device *dev, uint16_t *buf, size_t len, int32_t timeout); -static inline int z_impl_uart_rx_enable_u16(const struct device *dev, - uint16_t *buf, size_t len, - int32_t timeout) -{ -#if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_WIDE_DATA) - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->rx_enable_u16(dev, buf, len, timeout); -#else - ARG_UNUSED(dev); - ARG_UNUSED(buf); - ARG_UNUSED(len); - ARG_UNUSED(timeout); - return -ENOTSUP; -#endif -} - /** * @brief Provide receive buffer in response to #UART_RX_BUF_REQUEST event. * @@ -1473,20 +878,7 @@ static inline int z_impl_uart_rx_enable_u16(const struct device *dev, * @retval -errno Other negative errno value in case of failure. */ static inline int uart_rx_buf_rsp(const struct device *dev, uint8_t *buf, - size_t len) -{ -#ifdef CONFIG_UART_ASYNC_API - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->rx_buf_rsp(dev, buf, len); -#else - ARG_UNUSED(dev); - ARG_UNUSED(buf); - ARG_UNUSED(len); - return -ENOTSUP; -#endif -} + size_t len); /** * @brief Provide wide data receive buffer in response to #UART_RX_BUF_REQUEST @@ -1510,20 +902,7 @@ static inline int uart_rx_buf_rsp(const struct device *dev, uint8_t *buf, * @retval -errno Other negative errno value in case of failure. */ static inline int uart_rx_buf_rsp_u16(const struct device *dev, uint16_t *buf, - size_t len) -{ -#if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_WIDE_DATA) - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->rx_buf_rsp_u16(dev, buf, len); -#else - ARG_UNUSED(dev); - ARG_UNUSED(buf); - ARG_UNUSED(len); - return -ENOTSUP; -#endif -} + size_t len); /** * @brief Disable RX @@ -1542,19 +921,6 @@ static inline int uart_rx_buf_rsp_u16(const struct device *dev, uint16_t *buf, */ __syscall int uart_rx_disable(const struct device *dev); -static inline int z_impl_uart_rx_disable(const struct device *dev) -{ -#ifdef CONFIG_UART_ASYNC_API - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - return api->rx_disable(dev); -#else - ARG_UNUSED(dev); - return -ENOTSUP; -#endif -} - /** * @} */ @@ -1574,25 +940,6 @@ static inline int z_impl_uart_rx_disable(const struct device *dev) __syscall int uart_line_ctrl_set(const struct device *dev, uint32_t ctrl, uint32_t val); -static inline int z_impl_uart_line_ctrl_set(const struct device *dev, - uint32_t ctrl, uint32_t val) -{ -#ifdef CONFIG_UART_LINE_CTRL - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->line_ctrl_set == NULL) { - return -ENOSYS; - } - return api->line_ctrl_set(dev, ctrl, val); -#else - ARG_UNUSED(dev); - ARG_UNUSED(ctrl); - ARG_UNUSED(val); - return -ENOTSUP; -#endif -} - /** * @brief Retrieve line control for UART. * @@ -1608,25 +955,6 @@ static inline int z_impl_uart_line_ctrl_set(const struct device *dev, __syscall int uart_line_ctrl_get(const struct device *dev, uint32_t ctrl, uint32_t *val); -static inline int z_impl_uart_line_ctrl_get(const struct device *dev, - uint32_t ctrl, uint32_t *val) -{ -#ifdef CONFIG_UART_LINE_CTRL - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->line_ctrl_get == NULL) { - return -ENOSYS; - } - return api->line_ctrl_get(dev, ctrl, val); -#else - ARG_UNUSED(dev); - ARG_UNUSED(ctrl); - ARG_UNUSED(val); - return -ENOTSUP; -#endif -} - /** * @brief Send extra command to driver. * @@ -1644,25 +972,6 @@ static inline int z_impl_uart_line_ctrl_get(const struct device *dev, */ __syscall int uart_drv_cmd(const struct device *dev, uint32_t cmd, uint32_t p); -static inline int z_impl_uart_drv_cmd(const struct device *dev, uint32_t cmd, - uint32_t p) -{ -#ifdef CONFIG_UART_DRV_CMD - const struct uart_driver_api *api = - (const struct uart_driver_api *)dev->api; - - if (api->drv_cmd == NULL) { - return -ENOSYS; - } - return api->drv_cmd(dev, cmd, p); -#else - ARG_UNUSED(dev); - ARG_UNUSED(cmd); - ARG_UNUSED(p); - return -ENOTSUP; -#endif -} - #ifdef __cplusplus } #endif @@ -1671,6 +980,7 @@ static inline int z_impl_uart_drv_cmd(const struct device *dev, uint32_t cmd, * @} */ +#include #include #endif /* ZEPHYR_INCLUDE_DRIVERS_UART_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart/uart_internal.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart/uart_internal.h new file mode 100644 index 00000000..59dab601 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart/uart_internal.h @@ -0,0 +1,679 @@ +/* + * Copyright (c) 2018-2019 Nordic Semiconductor ASA + * Copyright (c) 2015 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Internal APIs for UART drivers + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_UART_INTERNAL_H_ +#define ZEPHYR_INCLUDE_DRIVERS_UART_UART_INTERNAL_H_ + +#include +#include + +#include + +/** + * @cond INTERNAL_HIDDEN + * + * For internal driver use only, skip these in public documentation. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief For configuring IRQ on each individual UART device. + * + * @param dev UART device instance. + */ +typedef void (*uart_irq_config_func_t)(const struct device *dev); + +/** @brief Driver API structure. */ +__subsystem struct uart_driver_api { + +#ifdef CONFIG_UART_ASYNC_API + + int (*callback_set)(const struct device *dev, uart_callback_t callback, void *user_data); + + int (*tx)(const struct device *dev, const uint8_t *buf, size_t len, int32_t timeout); + int (*tx_abort)(const struct device *dev); + + int (*rx_enable)(const struct device *dev, uint8_t *buf, size_t len, int32_t timeout); + int (*rx_buf_rsp)(const struct device *dev, uint8_t *buf, size_t len); + int (*rx_disable)(const struct device *dev); + +#ifdef CONFIG_UART_WIDE_DATA + int (*tx_u16)(const struct device *dev, const uint16_t *buf, size_t len, int32_t timeout); + int (*rx_enable_u16)(const struct device *dev, uint16_t *buf, size_t len, int32_t timeout); + int (*rx_buf_rsp_u16)(const struct device *dev, uint16_t *buf, size_t len); +#endif + +#endif + + /** Console I/O function */ + int (*poll_in)(const struct device *dev, unsigned char *p_char); + void (*poll_out)(const struct device *dev, unsigned char out_char); + +#ifdef CONFIG_UART_WIDE_DATA + int (*poll_in_u16)(const struct device *dev, uint16_t *p_u16); + void (*poll_out_u16)(const struct device *dev, uint16_t out_u16); +#endif + + /** Console I/O function */ + int (*err_check)(const struct device *dev); + +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + /** UART configuration functions */ + int (*configure)(const struct device *dev, const struct uart_config *cfg); + int (*config_get)(const struct device *dev, struct uart_config *cfg); +#endif + +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + + /** Interrupt driven FIFO fill function */ + int (*fifo_fill)(const struct device *dev, const uint8_t *tx_data, int len); + +#ifdef CONFIG_UART_WIDE_DATA + int (*fifo_fill_u16)(const struct device *dev, const uint16_t *tx_data, int len); +#endif + + /** Interrupt driven FIFO read function */ + int (*fifo_read)(const struct device *dev, uint8_t *rx_data, const int size); + +#ifdef CONFIG_UART_WIDE_DATA + int (*fifo_read_u16)(const struct device *dev, uint16_t *rx_data, const int size); +#endif + + /** Interrupt driven transfer enabling function */ + void (*irq_tx_enable)(const struct device *dev); + + /** Interrupt driven transfer disabling function */ + void (*irq_tx_disable)(const struct device *dev); + + /** Interrupt driven transfer ready function */ + int (*irq_tx_ready)(const struct device *dev); + + /** Interrupt driven receiver enabling function */ + void (*irq_rx_enable)(const struct device *dev); + + /** Interrupt driven receiver disabling function */ + void (*irq_rx_disable)(const struct device *dev); + + /** Interrupt driven transfer complete function */ + int (*irq_tx_complete)(const struct device *dev); + + /** Interrupt driven receiver ready function */ + int (*irq_rx_ready)(const struct device *dev); + + /** Interrupt driven error enabling function */ + void (*irq_err_enable)(const struct device *dev); + + /** Interrupt driven error disabling function */ + void (*irq_err_disable)(const struct device *dev); + + /** Interrupt driven pending status function */ + int (*irq_is_pending)(const struct device *dev); + + /** Interrupt driven interrupt update function */ + int (*irq_update)(const struct device *dev); + + /** Set the irq callback function */ + void (*irq_callback_set)(const struct device *dev, uart_irq_callback_user_data_t cb, + void *user_data); + +#endif + +#ifdef CONFIG_UART_LINE_CTRL + int (*line_ctrl_set)(const struct device *dev, uint32_t ctrl, uint32_t val); + int (*line_ctrl_get)(const struct device *dev, uint32_t ctrl, uint32_t *val); +#endif + +#ifdef CONFIG_UART_DRV_CMD + int (*drv_cmd)(const struct device *dev, uint32_t cmd, uint32_t p); +#endif +}; + +static inline int z_impl_uart_err_check(const struct device *dev) +{ + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->err_check == NULL) { + return -ENOSYS; + } + + return api->err_check(dev); +} + +static inline int z_impl_uart_poll_in(const struct device *dev, unsigned char *p_char) +{ + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->poll_in == NULL) { + return -ENOSYS; + } + + return api->poll_in(dev, p_char); +} + +static inline int z_impl_uart_poll_in_u16(const struct device *dev, uint16_t *p_u16) +{ +#ifdef CONFIG_UART_WIDE_DATA + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->poll_in_u16 == NULL) { + return -ENOSYS; + } + + return api->poll_in_u16(dev, p_u16); +#else + ARG_UNUSED(dev); + ARG_UNUSED(p_u16); + return -ENOTSUP; +#endif +} + +static inline void z_impl_uart_poll_out(const struct device *dev, unsigned char out_char) +{ + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + api->poll_out(dev, out_char); +} + +static inline void z_impl_uart_poll_out_u16(const struct device *dev, uint16_t out_u16) +{ +#ifdef CONFIG_UART_WIDE_DATA + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + api->poll_out_u16(dev, out_u16); +#else + ARG_UNUSED(dev); + ARG_UNUSED(out_u16); +#endif +} + +static inline int z_impl_uart_configure(const struct device *dev, const struct uart_config *cfg) +{ +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->configure == NULL) { + return -ENOSYS; + } + return api->configure(dev, cfg); +#else + ARG_UNUSED(dev); + ARG_UNUSED(cfg); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_config_get(const struct device *dev, struct uart_config *cfg) +{ +#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->config_get == NULL) { + return -ENOSYS; + } + + return api->config_get(dev, cfg); +#else + ARG_UNUSED(dev); + ARG_UNUSED(cfg); + return -ENOTSUP; +#endif +} + +static inline int uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->fifo_fill == NULL) { + return -ENOSYS; + } + + return api->fifo_fill(dev, tx_data, size); +#else + ARG_UNUSED(dev); + ARG_UNUSED(tx_data); + ARG_UNUSED(size); + return -ENOTSUP; +#endif +} + +static inline int uart_fifo_fill_u16(const struct device *dev, const uint16_t *tx_data, int size) +{ +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_UART_WIDE_DATA) + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->fifo_fill_u16 == NULL) { + return -ENOSYS; + } + + return api->fifo_fill_u16(dev, tx_data, size); +#else + ARG_UNUSED(dev); + ARG_UNUSED(tx_data); + ARG_UNUSED(size); + return -ENOTSUP; +#endif +} + +static inline int uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->fifo_read == NULL) { + return -ENOSYS; + } + + return api->fifo_read(dev, rx_data, size); +#else + ARG_UNUSED(dev); + ARG_UNUSED(rx_data); + ARG_UNUSED(size); + return -ENOTSUP; +#endif +} + +static inline int uart_fifo_read_u16(const struct device *dev, uint16_t *rx_data, const int size) +{ +#if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_UART_WIDE_DATA) + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->fifo_read_u16 == NULL) { + return -ENOSYS; + } + + return api->fifo_read_u16(dev, rx_data, size); +#else + ARG_UNUSED(dev); + ARG_UNUSED(rx_data); + ARG_UNUSED(size); + return -ENOTSUP; +#endif +} + +static inline void z_impl_uart_irq_tx_enable(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_tx_enable != NULL) { + api->irq_tx_enable(dev); + } +#else + ARG_UNUSED(dev); +#endif +} + +static inline void z_impl_uart_irq_tx_disable(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_tx_disable != NULL) { + api->irq_tx_disable(dev); + } +#else + ARG_UNUSED(dev); +#endif +} + +static inline int uart_irq_tx_ready(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_tx_ready == NULL) { + return -ENOSYS; + } + + return api->irq_tx_ready(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline void z_impl_uart_irq_rx_enable(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_rx_enable != NULL) { + api->irq_rx_enable(dev); + } +#else + ARG_UNUSED(dev); +#endif +} + +static inline void z_impl_uart_irq_rx_disable(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_rx_disable != NULL) { + api->irq_rx_disable(dev); + } +#else + ARG_UNUSED(dev); +#endif +} + +static inline int uart_irq_tx_complete(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_tx_complete == NULL) { + return -ENOSYS; + } + return api->irq_tx_complete(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline int uart_irq_rx_ready(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_rx_ready == NULL) { + return -ENOSYS; + } + return api->irq_rx_ready(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline void z_impl_uart_irq_err_enable(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_err_enable) { + api->irq_err_enable(dev); + } +#else + ARG_UNUSED(dev); +#endif +} + +static inline void z_impl_uart_irq_err_disable(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_err_disable) { + api->irq_err_disable(dev); + } +#else + ARG_UNUSED(dev); +#endif +} + +static inline int z_impl_uart_irq_is_pending(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_is_pending == NULL) { + return -ENOSYS; + } + return api->irq_is_pending(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_irq_update(const struct device *dev) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->irq_update == NULL) { + return -ENOSYS; + } + return api->irq_update(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline int uart_irq_callback_user_data_set(const struct device *dev, + uart_irq_callback_user_data_t cb, void *user_data) +{ +#ifdef CONFIG_UART_INTERRUPT_DRIVEN + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if ((api != NULL) && (api->irq_callback_set != NULL)) { + api->irq_callback_set(dev, cb, user_data); + return 0; + } else { + return -ENOSYS; + } +#else + ARG_UNUSED(dev); + ARG_UNUSED(cb); + ARG_UNUSED(user_data); + return -ENOTSUP; +#endif +} + +static inline int uart_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb) +{ + return uart_irq_callback_user_data_set(dev, cb, NULL); +} + +static inline int uart_callback_set(const struct device *dev, uart_callback_t callback, + void *user_data) +{ +#ifdef CONFIG_UART_ASYNC_API + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->callback_set == NULL) { + return -ENOSYS; + } + + return api->callback_set(dev, callback, user_data); +#else + ARG_UNUSED(dev); + ARG_UNUSED(callback); + ARG_UNUSED(user_data); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_tx(const struct device *dev, const uint8_t *buf, size_t len, + int32_t timeout) + +{ +#ifdef CONFIG_UART_ASYNC_API + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->tx(dev, buf, len, timeout); +#else + ARG_UNUSED(dev); + ARG_UNUSED(buf); + ARG_UNUSED(len); + ARG_UNUSED(timeout); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_tx_u16(const struct device *dev, const uint16_t *buf, size_t len, + int32_t timeout) + +{ +#if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_WIDE_DATA) + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->tx_u16(dev, buf, len, timeout); +#else + ARG_UNUSED(dev); + ARG_UNUSED(buf); + ARG_UNUSED(len); + ARG_UNUSED(timeout); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_tx_abort(const struct device *dev) +{ +#ifdef CONFIG_UART_ASYNC_API + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->tx_abort(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_rx_enable(const struct device *dev, uint8_t *buf, size_t len, + int32_t timeout) +{ +#ifdef CONFIG_UART_ASYNC_API + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->rx_enable(dev, buf, len, timeout); +#else + ARG_UNUSED(dev); + ARG_UNUSED(buf); + ARG_UNUSED(len); + ARG_UNUSED(timeout); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_rx_enable_u16(const struct device *dev, uint16_t *buf, size_t len, + int32_t timeout) +{ +#if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_WIDE_DATA) + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->rx_enable_u16(dev, buf, len, timeout); +#else + ARG_UNUSED(dev); + ARG_UNUSED(buf); + ARG_UNUSED(len); + ARG_UNUSED(timeout); + return -ENOTSUP; +#endif +} + +static inline int uart_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len) +{ +#ifdef CONFIG_UART_ASYNC_API + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->rx_buf_rsp(dev, buf, len); +#else + ARG_UNUSED(dev); + ARG_UNUSED(buf); + ARG_UNUSED(len); + return -ENOTSUP; +#endif +} + +static inline int uart_rx_buf_rsp_u16(const struct device *dev, uint16_t *buf, size_t len) +{ +#if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_WIDE_DATA) + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->rx_buf_rsp_u16(dev, buf, len); +#else + ARG_UNUSED(dev); + ARG_UNUSED(buf); + ARG_UNUSED(len); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_rx_disable(const struct device *dev) +{ +#ifdef CONFIG_UART_ASYNC_API + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + return api->rx_disable(dev); +#else + ARG_UNUSED(dev); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_line_ctrl_set(const struct device *dev, uint32_t ctrl, uint32_t val) +{ +#ifdef CONFIG_UART_LINE_CTRL + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->line_ctrl_set == NULL) { + return -ENOSYS; + } + return api->line_ctrl_set(dev, ctrl, val); +#else + ARG_UNUSED(dev); + ARG_UNUSED(ctrl); + ARG_UNUSED(val); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_line_ctrl_get(const struct device *dev, uint32_t ctrl, uint32_t *val) +{ +#ifdef CONFIG_UART_LINE_CTRL + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->line_ctrl_get == NULL) { + return -ENOSYS; + } + return api->line_ctrl_get(dev, ctrl, val); +#else + ARG_UNUSED(dev); + ARG_UNUSED(ctrl); + ARG_UNUSED(val); + return -ENOTSUP; +#endif +} + +static inline int z_impl_uart_drv_cmd(const struct device *dev, uint32_t cmd, uint32_t p) +{ +#ifdef CONFIG_UART_DRV_CMD + const struct uart_driver_api *api = (const struct uart_driver_api *)dev->api; + + if (api->drv_cmd == NULL) { + return -ENOSYS; + } + return api->drv_cmd(dev, cmd, p); +#else + ARG_UNUSED(dev); + ARG_UNUSED(cmd); + ARG_UNUSED(p); + return -ENOTSUP; +#endif +} + +#ifdef __cplusplus +} +#endif + +/** @endcond */ + +#endif /* ZEPHYR_INCLUDE_DRIVERS_UART_UART_INTERNAL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart_emul.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart_emul.h new file mode 100644 index 00000000..c2f16bd4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/uart_emul.h @@ -0,0 +1,76 @@ +/* + * Copyright 2024 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_UART_EMUL_H_ +#define ZEPHYR_INCLUDE_DRIVERS_UART_EMUL_H_ + +#include +#include +#include +#include +#include + +/** + * @file + * + * @brief Public APIs for the UART device emulation drivers. + */ + +/** + * @brief UART Emulation Interface + * @defgroup uart_emul_interface UART Emulation Interface + * @ingroup io_emulators + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +struct uart_emul_device_api; + +/** + * @brief Define the emulation callback function signature + * + * @param dev UART device instance + * @param size Number of available bytes in TX buffer + * @param target pointer to emulation context + */ +typedef void (*uart_emul_device_tx_data_ready_t)(const struct device *dev, size_t size, + const struct emul *target); + +/** Node in a linked list of emulators for UART devices */ +struct uart_emul { + sys_snode_t node; + /** Target emulator - REQUIRED for all emulated bus nodes of any type */ + const struct emul *target; + /** API provided for this device */ + const struct uart_emul_device_api *api; +}; + +/** Definition of the emulator API */ +struct uart_emul_device_api { + uart_emul_device_tx_data_ready_t tx_data_ready; +}; + +/** + * Register an emulated device on the controller + * + * @param dev Device that will use the emulator + * @param emul UART emulator to use + * @return 0 indicating success + */ +int uart_emul_register(const struct device *dev, struct uart_emul *emul); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_DRIVERS_UART_EMUL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc.h index 2e4d4dbc..cd1e0385 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc.h @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include @@ -76,6 +76,8 @@ struct udc_ep_caps { uint32_t bulk : 1; /** ISO transfer capable endpoint */ uint32_t iso : 1; + /** High-Bandwidth (interrupt or iso) capable endpoint */ + uint32_t high_bandwidth : 1; /** IN transfer capable endpoint */ uint32_t in : 1; /** OUT transfer capable endpoint */ @@ -277,8 +279,10 @@ struct udc_data { struct udc_device_caps caps; /** Driver access mutex */ struct k_mutex mutex; - /** Callback to submit an UDC event to upper layer */ + /** Callback to submit an UDC event to higher layer */ udc_event_cb_t event_cb; + /** Opaque pointer to store higher layer context */ + const void *event_ctx; /** USB device controller status */ atomic_t status; /** Internal used Control Sequence Stage */ @@ -293,6 +297,8 @@ struct udc_data { * @brief New USB device controller (UDC) driver API * @defgroup udc_api USB device controller driver API * @ingroup io_interfaces + * @since 3.3 + * @version 0.1.0 * @{ */ @@ -345,14 +351,16 @@ static inline bool udc_is_suspended(const struct device *dev) * After initialization controller driver should be able to detect * power state of the bus and signal power state changes. * - * @param[in] dev Pointer to device struct of the driver instance - * @param[in] event_cb Event callback from the higher layer (USB device stack) + * @param[in] dev Pointer to device struct of the driver instance + * @param[in] event_cb Event callback from the higher layer (USB device stack) + * @param[in] event_ctx Opaque pointer to higher layer context * * @return 0 on success, all other values should be treated as error. * @retval -EINVAL on parameter error (no callback is passed) * @retval -EALREADY already initialized */ -int udc_init(const struct device *dev, udc_event_cb_t event_cb); +int udc_init(const struct device *dev, + udc_event_cb_t event_cb, const void *const event_ctx); /** * @brief Enable USB device controller @@ -365,6 +373,7 @@ int udc_init(const struct device *dev, udc_event_cb_t event_cb); * @return 0 on success, all other values should be treated as error. * @retval -EPERM controller is not initialized * @retval -EALREADY already enabled + * @retval -ETIMEDOUT enable operation timed out */ int udc_enable(const struct device *dev); @@ -702,6 +711,36 @@ static inline struct udc_buf_info *udc_get_buf_info(const struct net_buf *const return (struct udc_buf_info *)net_buf_user_data(buf); } + +/** + * @brief Get pointer to higher layer context + * + * The address of the context is passed as an argument to the udc_init() + * function and is stored in the UDC data. + * + * @param[in] dev Pointer to device struct of the driver instance + * + * @return Opaque pointer to higher layer context + */ +static inline const void *udc_get_event_ctx(const struct device *dev) +{ + struct udc_data *data = dev->data; + + return data->event_ctx; +} + +/** + * @brief Get endpoint size from UDC endpoint configuration + * + * @param[in] cfg Pointer to UDC endpoint configuration + * + * @return Endpoint size + */ +static inline uint16_t udc_mps_ep_size(const struct udc_ep_config *const cfg) +{ + return USB_MPS_EP_SIZE(cfg->mps); +} + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc_buf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc_buf.h new file mode 100644 index 00000000..6e1ca15e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/udc_buf.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Buffers for USB device support + */ + +#ifndef ZEPHYR_INCLUDE_UDC_BUF_H +#define ZEPHYR_INCLUDE_UDC_BUF_H + +#include +#include + +#if defined(CONFIG_DCACHE) && !defined(CONFIG_UDC_BUF_FORCE_NOCACHE) +/* + * Here we try to get DMA-safe buffers, but we lack a consistent source of + * information about data cache properties, such as line cache size, and a + * consistent source of information about what part of memory is DMA'able. + * For now, we simply assume that all available memory is DMA'able and use + * Kconfig option DCACHE_LINE_SIZE for alignment and granularity. + */ +#define Z_UDC_BUF_ALIGN CONFIG_DCACHE_LINE_SIZE +#define Z_UDC_BUF_GRANULARITY CONFIG_DCACHE_LINE_SIZE +#else +/* + * Default alignment and granularity to pointer size if the platform does not + * have a data cache or buffers are placed in nocache memory region. + */ +#define Z_UDC_BUF_ALIGN sizeof(void *) +#define Z_UDC_BUF_GRANULARITY sizeof(void *) +#endif + +/** + * @brief Buffer macros and definitions used in USB device support + * @defgroup udc_buf Buffer macros and definitions used in USB device support + * @ingroup usb + * @since 4.0 + * @version 0.1.0 + * @{ + */ + +/** Buffer alignment required by the UDC driver */ +#define UDC_BUF_ALIGN Z_UDC_BUF_ALIGN + +/** Buffer granularity required by the UDC driver */ +#define UDC_BUF_GRANULARITY Z_UDC_BUF_GRANULARITY + +/** + * @brief Define a UDC driver-compliant static buffer + * + * This macro should be used if the application defines its own buffers to be + * used for USB transfers. + * + * @param name Buffer name + * @param size Buffer size + */ +#define UDC_STATIC_BUF_DEFINE(name, size) \ + static uint8_t __aligned(UDC_BUF_ALIGN) name[ROUND_UP(size, UDC_BUF_GRANULARITY)]; + +/** + * @brief Verify that the buffer is aligned as required by the UDC driver + * + * @see IS_ALIGNED + * + * @param buf Buffer pointer + */ +#define IS_UDC_ALIGNED(buf) IS_ALIGNED(buf, UDC_BUF_ALIGN) + +/** + * @cond INTERNAL_HIDDEN + */ +#define UDC_HEAP_DEFINE(name, bytes, in_section) \ + uint8_t in_section __aligned(UDC_BUF_ALIGN) \ + kheap_##name[MAX(bytes, Z_HEAP_MIN_SIZE)]; \ + STRUCT_SECTION_ITERABLE(k_heap, name) = { \ + .heap = { \ + .init_mem = kheap_##name, \ + .init_bytes = MAX(bytes, Z_HEAP_MIN_SIZE), \ + }, \ + } + +#define UDC_K_HEAP_DEFINE(name, size) \ + COND_CODE_1(CONFIG_UDC_BUF_FORCE_NOCACHE, \ + (UDC_HEAP_DEFINE(name, size, __nocache)), \ + (UDC_HEAP_DEFINE(name, size, __noinit))) + +extern const struct net_buf_data_cb net_buf_dma_cb; +/** @endcond */ + +/** + * @brief Define a new pool for UDC buffers with variable-size payloads + * + * This macro is similar to `NET_BUF_POOL_VAR_DEFINE`, but provides buffers + * with alignment and granularity suitable for use by UDC driver. + * + * @see NET_BUF_POOL_VAR_DEFINE + * + * @param pname Name of the pool variable. + * @param count Number of buffers in the pool. + * @param size Maximum data payload per buffer. + * @param ud_size User data space to reserve per buffer. + * @param fdestroy Optional destroy callback when buffer is freed. + */ +#define UDC_BUF_POOL_VAR_DEFINE(pname, count, size, ud_size, fdestroy) \ + _NET_BUF_ARRAY_DEFINE(pname, count, ud_size); \ + UDC_K_HEAP_DEFINE(net_buf_mem_pool_##pname, size); \ + static const struct net_buf_data_alloc net_buf_data_alloc_##pname = { \ + .cb = &net_buf_dma_cb, \ + .alloc_data = &net_buf_mem_pool_##pname, \ + .max_alloc_size = 0, \ + }; \ + static STRUCT_SECTION_ITERABLE(net_buf_pool, pname) = \ + NET_BUF_POOL_INITIALIZER(pname, &net_buf_data_alloc_##pname, \ + _net_buf_##pname, count, ud_size, \ + fdestroy) + +/** + * @brief Define a new pool for UDC buffers based on fixed-size data + * + * This macro is similar to `NET_BUF_POOL_DEFINE`, but provides buffers + * with alignment and granularity suitable for use by UDC driver. + * + * @see NET_BUF_POOL_DEFINE + + * @param pname Name of the pool variable. + * @param count Number of buffers in the pool. + * @param size Maximum data payload per buffer. + * @param ud_size User data space to reserve per buffer. + * @param fdestroy Optional destroy callback when buffer is freed. + */ +#define UDC_BUF_POOL_DEFINE(pname, count, size, ud_size, fdestroy) \ + _NET_BUF_ARRAY_DEFINE(pname, count, ud_size); \ + BUILD_ASSERT((UDC_BUF_GRANULARITY) % (UDC_BUF_ALIGN) == 0, \ + "Code assumes granurality is multiple of alignment"); \ + static uint8_t __nocache __aligned(UDC_BUF_ALIGN) \ + net_buf_data_##pname[count][ROUND_UP(size, UDC_BUF_GRANULARITY)];\ + static const struct net_buf_pool_fixed net_buf_fixed_##pname = { \ + .data_pool = (uint8_t *)net_buf_data_##pname, \ + }; \ + static const struct net_buf_data_alloc net_buf_fixed_alloc_##pname = { \ + .cb = &net_buf_fixed_cb, \ + .alloc_data = (void *)&net_buf_fixed_##pname, \ + .max_alloc_size = ROUND_UP(size, UDC_BUF_GRANULARITY), \ + }; \ + static STRUCT_SECTION_ITERABLE(net_buf_pool, pname) = \ + NET_BUF_POOL_INITIALIZER(pname, &net_buf_fixed_alloc_##pname, \ + _net_buf_##pname, count, ud_size, \ + fdestroy) + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_UDC_BUF_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/uhc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/uhc.h index 5f499af6..a2224d24 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/uhc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/uhc.h @@ -14,7 +14,7 @@ #include #include -#include +#include #include #include @@ -22,6 +22,8 @@ * @brief USB host controller (UHC) driver API * @defgroup uhc_api USB host controller driver API * @ingroup io_interfaces + * @since 3.3 + * @version 0.1.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/usb_dc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/usb_dc.h index 1d7762f8..7c5506d7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/usb_dc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb/usb_dc.h @@ -22,6 +22,8 @@ /** * @brief USB Device Controller API * @defgroup _usb_device_controller_api USB Device Controller API + * @since 1.5 + * @version 1.0.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/tcpci_priv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/tcpci_priv.h new file mode 100644 index 00000000..8c5d67f5 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/tcpci_priv.h @@ -0,0 +1,119 @@ +/* + * Copyright 2024 Google LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Helper functions to use by the TCPCI-compliant drivers + * + * This file contains generic TCPCI functions that may be used by the drivers to TCPCI-compliant + * devices that want to implement vendor-specific functionality without the need to reimplement the + * TCPCI generic functionality and register operations. + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_USBC_TCPCI_PRIV_H_ +#define ZEPHYR_INCLUDE_DRIVERS_USBC_TCPCI_PRIV_H_ + +#include +#include +#include + +/** + * @brief Structure used to bind the register address to name in registers dump + */ +struct tcpci_reg_dump_map { + /** Address of I2C device register */ + uint8_t addr; + /** Human readable name of register */ + const char *name; + /** Size in bytes of the register */ + uint8_t size; +}; + +/** Size of the array containing the standard registers used by tcpci dump command */ +#define TCPCI_STD_REGS_SIZE 38 +/** + * @brief Array containing the standard TCPCI registers list. + * If the TCPC driver contain any vendor-specific registers, it may override the TCPCI dump_std_reg + * function tp dump them and should also dump the standard registers using this array. + * + */ +extern const struct tcpci_reg_dump_map tcpci_std_regs[TCPCI_STD_REGS_SIZE]; + +/** + * @brief Function to read the 8-bit register of TCPCI device + * + * @param bus I2C bus + * @param reg Address of TCPCI register + * @param value Pointer to variable that will store the register value + * @return int Status of I2C operation, 0 in case of success + */ +int tcpci_read_reg8(const struct i2c_dt_spec *bus, uint8_t reg, uint8_t *value); + +/** + * @brief Function to write a value to the 8-bit register of TCPCI device + * + * @param bus I2C bus + * @param reg Address of TCPCI register + * @param value Value that will be written to the device register + * @return int Status of I2C operation, 0 in case of success + */ +int tcpci_write_reg8(const struct i2c_dt_spec *bus, uint8_t reg, uint8_t value); + +/** + * @brief Function to read and update part of the 8-bit register of TCPCI device + * The function is NOT performing this operation atomically. + * + * @param bus I2C bus + * @param reg Address of TCPCI register + * @param mask Bitmask specifying which bits of the device register will be modified + * @param value Value that will be written to the device register after being ANDed with mask + * @return int Status of I2C operation, 0 in case of success + */ +int tcpci_update_reg8(const struct i2c_dt_spec *bus, uint8_t reg, uint8_t mask, uint8_t value); + +/** + * @brief Function to read the 16-bit register of TCPCI device + * + * @param bus I2C bus + * @param reg Address of TCPCI register + * @param value Pointer to variable that will store the register value + * @return int Status of I2C operation, 0 in case of success + */ +int tcpci_read_reg16(const struct i2c_dt_spec *bus, uint8_t reg, uint16_t *value); + +/** + * @brief Function to write a value to the 16-bit register of TCPCI device + * + * @param bus I2C bus + * @param reg Address of TCPCI register + * @param value Value that will be written to the device register + * @return int Status of I2C operation, 0 in case of success + */ +int tcpci_write_reg16(const struct i2c_dt_spec *bus, uint8_t reg, uint16_t value); + +/** + * @brief Function that converts the TCPCI alert register to the tcpc_alert enum + * The hard reset value takes priority, where the rest are returned in the bit order from least + * significant to most significant. + * + * @param reg Value of the TCPCI alert register. This parameter must have value other than zero. + * @return enum tcpc_alert Value of one of the flags being set in the alert register + */ +enum tcpc_alert tcpci_alert_reg_to_enum(uint16_t reg); + +/** + * @brief Function that reads the CC status registers and converts read values to enums + * representing voltages state and partner detection status. + * + * @param bus I2C bus + * @param cc1 pointer to variable where detected CC1 voltage state will be stored + * @param cc2 pointer to variable where detected CC2 voltage state will be stored + * @return -EINVAL if cc1 or cc2 pointer is NULL + * @return int Status of I2C operation, 0 in case of success + */ +int tcpci_tcpm_get_cc(const struct i2c_dt_spec *bus, enum tc_cc_voltage_state *cc1, + enum tc_cc_voltage_state *cc2); + +#endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_TCPCI_PRIV_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/usbc_tcpc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/usbc_tcpc.h index 7b94e3f9..33daa314 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/usbc_tcpc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/usb_c/usbc_tcpc.h @@ -118,17 +118,17 @@ struct tcpc_chip_info { }; }; -typedef int (*tcpc_vconn_control_cb_t)(const struct device *dev, - enum tc_cc_polarity pol, bool enable); -typedef int (*tcpc_vconn_discharge_cb_t)(const struct device *dev, - enum tc_cc_polarity pol, bool enable); +typedef int (*tcpc_vconn_control_cb_t)(const struct device *dev, enum tc_cc_polarity pol, + bool enable); +typedef int (*tcpc_vconn_discharge_cb_t)(const struct device *dev, enum tc_cc_polarity pol, + bool enable); typedef void (*tcpc_alert_handler_cb_t)(const struct device *dev, void *data, - enum tcpc_alert alert); + enum tcpc_alert alert); __subsystem struct tcpc_driver_api { int (*init)(const struct device *dev); int (*get_cc)(const struct device *dev, enum tc_cc_voltage_state *cc1, - enum tc_cc_voltage_state *cc2); + enum tc_cc_voltage_state *cc2); int (*select_rp_value)(const struct device *dev, enum tc_rp_value rp); int (*get_rp_value)(const struct device *dev, enum tc_rp_value *rp); int (*set_cc)(const struct device *dev, enum tc_cc_pull pull); @@ -137,7 +137,7 @@ __subsystem struct tcpc_driver_api { int (*vconn_discharge)(const struct device *dev, bool enable); int (*set_vconn)(const struct device *dev, bool enable); int (*set_roles)(const struct device *dev, enum tc_power_role power_role, - enum tc_data_role data_role); + enum tc_data_role data_role); int (*get_rx_pending_msg)(const struct device *dev, struct pd_msg *msg); int (*set_rx_enable)(const struct device *dev, bool enable); int (*set_cc_polarity)(const struct device *dev, enum tc_cc_polarity polarity); @@ -145,11 +145,11 @@ __subsystem struct tcpc_driver_api { int (*dump_std_reg)(const struct device *dev); void (*alert_handler_cb)(const struct device *dev, void *data, enum tcpc_alert alert); int (*get_status_register)(const struct device *dev, enum tcpc_status_reg reg, - int32_t *status); + uint32_t *status); int (*clear_status_register)(const struct device *dev, enum tcpc_status_reg reg, - uint32_t mask); + uint32_t mask); int (*mask_status_register)(const struct device *dev, enum tcpc_status_reg reg, - uint32_t mask); + uint32_t mask); int (*set_debug_accessory)(const struct device *dev, bool enable); int (*set_debug_detach)(const struct device *dev); int (*set_drp_toggle)(const struct device *dev, bool enable); @@ -162,7 +162,7 @@ __subsystem struct tcpc_driver_api { int (*sop_prime_enable)(const struct device *dev, bool enable); int (*set_bist_test_mode)(const struct device *dev, bool enable); int (*set_alert_handler_cb)(const struct device *dev, tcpc_alert_handler_cb_t handler, - void *data); + void *data); }; /** @@ -170,15 +170,13 @@ __subsystem struct tcpc_driver_api { */ static inline int tcpc_is_cc_rp(enum tc_cc_voltage_state cc) { - return (cc == TC_CC_VOLT_RP_DEF) || (cc == TC_CC_VOLT_RP_1A5) || - (cc == TC_CC_VOLT_RP_3A0); + return (cc == TC_CC_VOLT_RP_DEF) || (cc == TC_CC_VOLT_RP_1A5) || (cc == TC_CC_VOLT_RP_3A0); } /** * @brief Returns true if both CC lines are completely open */ -static inline int tcpc_is_cc_open(enum tc_cc_voltage_state cc1, - enum tc_cc_voltage_state cc2) +static inline int tcpc_is_cc_open(enum tc_cc_voltage_state cc1, enum tc_cc_voltage_state cc2) { return (cc1 < TC_CC_VOLT_RD) && (cc2 < TC_CC_VOLT_RD); } @@ -186,8 +184,7 @@ static inline int tcpc_is_cc_open(enum tc_cc_voltage_state cc1, /** * @brief Returns true if we detect the port partner is a snk debug accessory */ -static inline int tcpc_is_cc_snk_dbg_acc(enum tc_cc_voltage_state cc1, - enum tc_cc_voltage_state cc2) +static inline int tcpc_is_cc_snk_dbg_acc(enum tc_cc_voltage_state cc1, enum tc_cc_voltage_state cc2) { return cc1 == TC_CC_VOLT_RD && cc2 == TC_CC_VOLT_RD; } @@ -195,8 +192,7 @@ static inline int tcpc_is_cc_snk_dbg_acc(enum tc_cc_voltage_state cc1, /** * @brief Returns true if we detect the port partner is a src debug accessory */ -static inline int tcpc_is_cc_src_dbg_acc(enum tc_cc_voltage_state cc1, - enum tc_cc_voltage_state cc2) +static inline int tcpc_is_cc_src_dbg_acc(enum tc_cc_voltage_state cc1, enum tc_cc_voltage_state cc2) { return tcpc_is_cc_rp(cc1) && tcpc_is_cc_rp(cc2); } @@ -204,8 +200,7 @@ static inline int tcpc_is_cc_src_dbg_acc(enum tc_cc_voltage_state cc1, /** * @brief Returns true if the port partner is an audio accessory */ -static inline int tcpc_is_cc_audio_acc(enum tc_cc_voltage_state cc1, - enum tc_cc_voltage_state cc2) +static inline int tcpc_is_cc_audio_acc(enum tc_cc_voltage_state cc1, enum tc_cc_voltage_state cc2) { return cc1 == TC_CC_VOLT_RA && cc2 == TC_CC_VOLT_RA; } @@ -222,8 +217,7 @@ static inline int tcpc_is_cc_at_least_one_rd(enum tc_cc_voltage_state cc1, /** * @brief Returns true if the port partner is presenting Rd on only one CC line */ -static inline int tcpc_is_cc_only_one_rd(enum tc_cc_voltage_state cc1, - enum tc_cc_voltage_state cc2) +static inline int tcpc_is_cc_only_one_rd(enum tc_cc_voltage_state cc1, enum tc_cc_voltage_state cc2) { return tcpc_is_cc_at_least_one_rd(cc1, cc2) && cc1 != cc2; } @@ -239,11 +233,9 @@ static inline int tcpc_is_cc_only_one_rd(enum tc_cc_voltage_state cc1, */ static inline int tcpc_init(const struct device *dev) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; - __ASSERT(api->init != NULL, - "Callback pointer should not be NULL"); + __ASSERT(api->init != NULL, "Callback pointer should not be NULL"); return api->init(dev); } @@ -259,12 +251,10 @@ static inline int tcpc_init(const struct device *dev) * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_get_cc(const struct device *dev, - enum tc_cc_voltage_state *cc1, +static inline int tcpc_get_cc(const struct device *dev, enum tc_cc_voltage_state *cc1, enum tc_cc_voltage_state *cc2) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->get_cc == NULL) { return -ENOSYS; @@ -285,8 +275,7 @@ static inline int tcpc_get_cc(const struct device *dev, */ static inline int tcpc_select_rp_value(const struct device *dev, enum tc_rp_value rp) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->select_rp_value == NULL) { return -ENOSYS; @@ -307,8 +296,7 @@ static inline int tcpc_select_rp_value(const struct device *dev, enum tc_rp_valu */ static inline int tcpc_get_rp_value(const struct device *dev, enum tc_rp_value *rp) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->get_rp_value == NULL) { return -ENOSYS; @@ -328,11 +316,9 @@ static inline int tcpc_get_rp_value(const struct device *dev, enum tc_rp_value * */ static inline int tcpc_set_cc(const struct device *dev, enum tc_cc_pull pull) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; - __ASSERT(api->set_cc != NULL, - "Callback pointer should not be NULL"); + __ASSERT(api->set_cc != NULL, "Callback pointer should not be NULL"); return api->set_cc(dev, pull); } @@ -347,16 +333,13 @@ static inline int tcpc_set_cc(const struct device *dev, enum tc_cc_pull pull) * @param dev Runtime device structure * @param vconn_cb pointer to the callback function that controls vconn */ -static inline void tcpc_set_vconn_cb(const struct device *dev, - tcpc_vconn_control_cb_t vconn_cb) +static inline void tcpc_set_vconn_cb(const struct device *dev, tcpc_vconn_control_cb_t vconn_cb) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; - __ASSERT(api->set_vconn_cb != NULL, - "Callback pointer should not be NULL"); + __ASSERT(api->set_vconn_cb != NULL, "Callback pointer should not be NULL"); - return api->set_vconn_cb(dev, vconn_cb); + api->set_vconn_cb(dev, vconn_cb); } /** @@ -370,15 +353,13 @@ static inline void tcpc_set_vconn_cb(const struct device *dev, * @param cb pointer to the callback function that discharges vconn */ static inline void tcpc_set_vconn_discharge_cb(const struct device *dev, - tcpc_vconn_discharge_cb_t cb) + tcpc_vconn_discharge_cb_t cb) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; - __ASSERT(api->set_vconn_discharge_cb != NULL, - "Callback pointer should not be NULL"); + __ASSERT(api->set_vconn_discharge_cb != NULL, "Callback pointer should not be NULL"); - return api->set_vconn_discharge_cb(dev, cb); + api->set_vconn_discharge_cb(dev, cb); } /** @@ -396,8 +377,7 @@ static inline void tcpc_set_vconn_discharge_cb(const struct device *dev, */ static inline int tcpc_vconn_discharge(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->vconn_discharge == NULL) { return -ENOSYS; @@ -421,8 +401,7 @@ static inline int tcpc_vconn_discharge(const struct device *dev, bool enable) */ static inline int tcpc_set_vconn(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_vconn == NULL) { return -ENOSYS; @@ -444,12 +423,10 @@ static inline int tcpc_set_vconn(const struct device *dev, bool enable) * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_set_roles(const struct device *dev, - enum tc_power_role power_role, +static inline int tcpc_set_roles(const struct device *dev, enum tc_power_role power_role, enum tc_data_role data_role) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_roles == NULL) { return -ENOSYS; @@ -493,8 +470,7 @@ static inline int tcpc_get_rx_pending_msg(const struct device *dev, struct pd_ms */ static inline int tcpc_set_rx_enable(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_rx_enable == NULL) { return -ENOSYS; @@ -512,14 +488,11 @@ static inline int tcpc_set_rx_enable(const struct device *dev, bool enable) * @retval 0 on success * @retval -EIO on failure */ -static inline int tcpc_set_cc_polarity(const struct device *dev, - enum tc_cc_polarity polarity) +static inline int tcpc_set_cc_polarity(const struct device *dev, enum tc_cc_polarity polarity) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; - __ASSERT(api->set_cc_polarity != NULL, - "Callback pointer should not be NULL"); + __ASSERT(api->set_cc_polarity != NULL, "Callback pointer should not be NULL"); return api->set_cc_polarity(dev, polarity); } @@ -534,11 +507,9 @@ static inline int tcpc_set_cc_polarity(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_transmit_data(const struct device *dev, - struct pd_msg *msg) +static inline int tcpc_transmit_data(const struct device *dev, struct pd_msg *msg) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->transmit_data == NULL) { return -ENOSYS; @@ -558,8 +529,7 @@ static inline int tcpc_transmit_data(const struct device *dev, */ static inline int tcpc_dump_std_reg(const struct device *dev) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->dump_std_reg == NULL) { return -ENOSYS; @@ -582,14 +552,11 @@ static inline int tcpc_dump_std_reg(const struct device *dev) * @retval -EINVAL on failure */ static inline int tcpc_set_alert_handler_cb(const struct device *dev, - tcpc_alert_handler_cb_t handler, - void *data) + tcpc_alert_handler_cb_t handler, void *data) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; - __ASSERT(api->set_alert_handler_cb != NULL, - "Callback pointer should not be NULL"); + __ASSERT(api->set_alert_handler_cb != NULL, "Callback pointer should not be NULL"); return api->set_alert_handler_cb(dev, handler, data); } @@ -605,12 +572,10 @@ static inline int tcpc_set_alert_handler_cb(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_get_status_register(const struct device *dev, - enum tcpc_status_reg reg, - int32_t *status) +static inline int tcpc_get_status_register(const struct device *dev, enum tcpc_status_reg reg, + uint32_t *status) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->get_status_register == NULL) { return -ENOSYS; @@ -631,12 +596,10 @@ static inline int tcpc_get_status_register(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_clear_status_register(const struct device *dev, - enum tcpc_status_reg reg, +static inline int tcpc_clear_status_register(const struct device *dev, enum tcpc_status_reg reg, uint32_t mask) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->clear_status_register == NULL) { return -ENOSYS; @@ -657,12 +620,10 @@ static inline int tcpc_clear_status_register(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_mask_status_register(const struct device *dev, - enum tcpc_status_reg reg, +static inline int tcpc_mask_status_register(const struct device *dev, enum tcpc_status_reg reg, uint32_t mask) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->mask_status_register == NULL) { return -ENOSYS; @@ -681,11 +642,9 @@ static inline int tcpc_mask_status_register(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_set_debug_accessory(const struct device *dev, - bool enable) +static inline int tcpc_set_debug_accessory(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_debug_accessory == NULL) { return -ENOSYS; @@ -705,8 +664,7 @@ static inline int tcpc_set_debug_accessory(const struct device *dev, */ static inline int tcpc_set_debug_detach(const struct device *dev) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_debug_detach == NULL) { return -ENOSYS; @@ -727,8 +685,7 @@ static inline int tcpc_set_debug_detach(const struct device *dev) */ static inline int tcpc_set_drp_toggle(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_drp_toggle == NULL) { return -ENOSYS; @@ -748,8 +705,7 @@ static inline int tcpc_set_drp_toggle(const struct device *dev, bool enable) */ static inline int tcpc_get_snk_ctrl(const struct device *dev) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->get_snk_ctrl == NULL) { return -ENOSYS; @@ -788,8 +744,7 @@ static inline int tcpc_set_snk_ctrl(const struct device *dev, bool enable) */ static inline int tcpc_get_src_ctrl(const struct device *dev) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->get_src_ctrl == NULL) { return -ENOSYS; @@ -828,11 +783,9 @@ static inline int tcpc_set_src_ctrl(const struct device *dev, bool enable) * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_set_bist_test_mode(const struct device *dev, - bool enable) +static inline int tcpc_set_bist_test_mode(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_bist_test_mode == NULL) { return -ENOSYS; @@ -851,11 +804,9 @@ static inline int tcpc_set_bist_test_mode(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_get_chip_info(const struct device *dev, - struct tcpc_chip_info *chip_info) +static inline int tcpc_get_chip_info(const struct device *dev, struct tcpc_chip_info *chip_info) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->get_chip_info == NULL) { return -ENOSYS; @@ -874,11 +825,9 @@ static inline int tcpc_get_chip_info(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_set_low_power_mode(const struct device *dev, - bool enable) +static inline int tcpc_set_low_power_mode(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->set_low_power_mode == NULL) { return -ENOSYS; @@ -897,11 +846,9 @@ static inline int tcpc_set_low_power_mode(const struct device *dev, * @retval -EIO on failure * @retval -ENOSYS if not implemented */ -static inline int tcpc_sop_prime_enable(const struct device *dev, - bool enable) +static inline int tcpc_sop_prime_enable(const struct device *dev, bool enable) { - const struct tcpc_driver_api *api = - (const struct tcpc_driver_api *)dev->api; + const struct tcpc_driver_api *api = (const struct tcpc_driver_api *)dev->api; if (api->sop_prime_enable == NULL) { return -ENOSYS; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video-controls.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video-controls.h index 7912ab0d..b67e5a87 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video-controls.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video-controls.h @@ -1,72 +1,162 @@ -/** - * @file - * - * @brief Public APIs for Video. - */ - /* * Copyright (c) 2019 Linaro Limited. + * Copyright (c) 2024 tinyVision.ai Inc. * * SPDX-License-Identifier: Apache-2.0 */ #ifndef ZEPHYR_INCLUDE_VIDEO_CONTROLS_H_ #define ZEPHYR_INCLUDE_VIDEO_CONTROLS_H_ +/** + * @file + * + * @brief Public APIs for Video. + */ + /** * @brief Video controls * @defgroup video_controls Video Controls * @ingroup io_interfaces + * + * The Video control IDs (CIDs) are introduced with the same name as + * Linux V4L2 subsystem and under the same class. This facilitates + * inter-operability and debugging devices end-to-end across Linux and + * Zephyr. + * + * This list is maintained compatible to the Linux kernel definitions in + * @c linux/include/uapi/linux/v4l2-controls.h + * * @{ */ -#include -#include -#include - -#include - #ifdef __cplusplus extern "C" { #endif /** - * @name Control classes + * @name Base class control IDs + * @{ + */ +#define VIDEO_CID_BASE 0x00980900 + +/** Amount of perceived light of the image, the luma (Y') value. */ +#define VIDEO_CID_BRIGHTNESS (VIDEO_CID_BASE + 0) + +/** Amount of difference between the bright colors and dark colors. */ +#define VIDEO_CID_CONTRAST (VIDEO_CID_BASE + 1) + +/** Colorfulness of the image while preserving its brightness */ +#define VIDEO_CID_SATURATION (VIDEO_CID_BASE + 2) + +/** Shift in the tint of every colors, clockwise in a RGB color wheel */ +#define VIDEO_CID_HUE (VIDEO_CID_BASE + 3) + +/** Amount of time an image sensor is exposed to light, affecting the brightness */ +#define VIDEO_CID_EXPOSURE (VIDEO_CID_BASE + 17) + +/** Amount of amplification performed to each pixel electrical signal, affecting the brightness */ +#define VIDEO_CID_GAIN (VIDEO_CID_BASE + 19) + +/** Flip the image horizontally: the left side becomes the right side */ +#define VIDEO_CID_HFLIP (VIDEO_CID_BASE + 20) + +/** Flip the image vertically: the top side becomes the bottom side */ +#define VIDEO_CID_VFLIP (VIDEO_CID_BASE + 21) + +/** Frequency of the power line to compensate for, avoiding flicker due to artificial lighting */ +#define VIDEO_CID_POWER_LINE_FREQUENCY (VIDEO_CID_BASE + 24) +enum video_power_line_frequency { + VIDEO_CID_POWER_LINE_FREQUENCY_DISABLED = 0, + VIDEO_CID_POWER_LINE_FREQUENCY_50HZ = 1, + VIDEO_CID_POWER_LINE_FREQUENCY_60HZ = 2, + VIDEO_CID_POWER_LINE_FREQUENCY_AUTO = 3, +}; + +/** Balance of colors in direction of blue (cold) or red (warm) */ +#define VIDEO_CID_WHITE_BALANCE_TEMPERATURE (VIDEO_CID_BASE + 26) + +/** + * @} + */ + +/** + * @name Stateful codec controls IDs + * @{ + */ +#define VIDEO_CID_CODEC_CLASS_BASE 0x00990900 + +/** + * @} + */ + +/** + * @name Camera class controls IDs + * @{ + */ +#define VIDEO_CID_CAMERA_CLASS_BASE 0x009a0900 + +/** Amount of optical zoom applied through to the camera optics */ +#define VIDEO_CID_ZOOM_ABSOLUTE (VIDEO_CID_CAMERA_CLASS_BASE + 13) + +/** + * @} + */ + +/** + * @name Camera Flash class control IDs + * @{ + */ +#define VIDEO_CID_FLASH_CLASS_BASE 0x009c0900 + +/** + * @} + */ + +/** + * @name JPEG class control IDs * @{ */ -#define VIDEO_CTRL_CLASS_GENERIC 0x00000000 /**< Generic class controls */ -#define VIDEO_CTRL_CLASS_CAMERA 0x00010000 /**< Camera class controls */ -#define VIDEO_CTRL_CLASS_MPEG 0x00020000 /**< MPEG-compression controls */ -#define VIDEO_CTRL_CLASS_JPEG 0x00030000 /**< JPEG-compression controls */ -#define VIDEO_CTRL_CLASS_VENDOR 0xFFFF0000 /**< Vendor-specific class controls */ +#define VIDEO_CID_JPEG_CLASS_BASE 0x009d0900 + +/** Quality (Q) factor of the JPEG algorithm, also increasing the data size */ +#define VIDEO_CID_JPEG_COMPRESSION_QUALITY (VIDEO_CID_JPEG_CLASS_BASE + 3) + /** * @} */ /** - * @name Generic class control IDs + * @name Image Source class control IDs * @{ */ -/** Mirror the picture horizontally */ -#define VIDEO_CID_HFLIP (VIDEO_CTRL_CLASS_GENERIC + 0) -/** Mirror the picture vertically */ -#define VIDEO_CID_VFLIP (VIDEO_CTRL_CLASS_GENERIC + 1) +#define VIDEO_CID_IMAGE_SOURCE_CLASS_BASE 0x009e0900 + /** * @} */ /** - * @name Camera class control IDs + * @name Image Processing class control IDs * @{ */ -#define VIDEO_CID_CAMERA_EXPOSURE (VIDEO_CTRL_CLASS_CAMERA + 0) -#define VIDEO_CID_CAMERA_GAIN (VIDEO_CTRL_CLASS_CAMERA + 1) -#define VIDEO_CID_CAMERA_ZOOM (VIDEO_CTRL_CLASS_CAMERA + 2) -#define VIDEO_CID_CAMERA_BRIGHTNESS (VIDEO_CTRL_CLASS_CAMERA + 3) -#define VIDEO_CID_CAMERA_SATURATION (VIDEO_CTRL_CLASS_CAMERA + 4) -#define VIDEO_CID_CAMERA_WHITE_BAL (VIDEO_CTRL_CLASS_CAMERA + 5) -#define VIDEO_CID_CAMERA_CONTRAST (VIDEO_CTRL_CLASS_CAMERA + 6) -#define VIDEO_CID_CAMERA_COLORBAR (VIDEO_CTRL_CLASS_CAMERA + 7) -#define VIDEO_CID_CAMERA_QUALITY (VIDEO_CTRL_CLASS_CAMERA + 8) +#define VIDEO_CID_IMAGE_PROC_CLASS_BASE 0x009f0900 + +/** Pixel rate (pixels/second) in the device's pixel array. This control is read-only. */ +#define VIDEO_CID_PIXEL_RATE (VIDEO_CID_IMAGE_PROC_CLASS_BASE + 2) + +/** Selection of the type of test pattern to represent */ +#define VIDEO_CID_TEST_PATTERN (VIDEO_CID_IMAGE_PROC_CLASS_BASE + 3) + +/** + * @} + */ + +/** + * @name Vendor-specific class control IDs + * @{ + */ +#define VIDEO_CID_PRIVATE_BASE 0x08000000 + /** * @} */ @@ -75,9 +165,6 @@ extern "C" { } #endif -/* Controls */ - - /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video.h index 84b55583..959083a4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/video.h @@ -16,7 +16,7 @@ * @brief Video Interface * @defgroup video_interface Video Interface * @since 2.1 - * @version 1.0.0 + * @version 1.1.0 * @ingroup io_interfaces * @{ */ @@ -27,12 +27,15 @@ #include -#include - #ifdef __cplusplus extern "C" { #endif +/* + * Flag used by @ref video_caps structure to indicate endpoint operates on + * buffers the size of the video frame + */ +#define LINE_COUNT_HEIGHT (-1) /** * @struct video_format @@ -57,7 +60,6 @@ struct video_format { uint32_t pitch; }; - /** * @struct video_format_cap * @brief Video format capability @@ -94,6 +96,22 @@ struct video_caps { * the stream. */ uint8_t min_vbuf_count; + /** Denotes minimum line count of a video buffer that this endpoint + * can fill or process. Each line is expected to consume the number + * of bytes the selected video format's pitch uses, so the video + * buffer must be at least `pitch` * `min_line_count` bytes. + * `LINE_COUNT_HEIGHT` is a special value, indicating the endpoint + * only supports video buffers with at least enough bytes to store + * a full video frame + */ + int16_t min_line_count; + /** + * Denotes maximum line count of a video buffer that this endpoint + * can fill or process. Similar constraints to `min_line_count`, + * but `LINE_COUNT_HEIGHT` indicates that the endpoint will never + * fill or process more than a full video frame in one video buffer. + */ + int16_t max_line_count; }; /** @@ -116,6 +134,72 @@ struct video_buffer { * endpoints. */ uint32_t timestamp; + /** Line offset within frame this buffer represents, from the + * beginning of the frame. This offset is given in pixels, + * so `line_offset` * `pitch` provides offset from the start of + * the frame in bytes. + */ + uint16_t line_offset; +}; + +/** + * @brief video_frmival_type enum + * + * Supported frame interval type of a video device. + */ +enum video_frmival_type { + /** discrete frame interval type */ + VIDEO_FRMIVAL_TYPE_DISCRETE = 1, + /** stepwise frame interval type */ + VIDEO_FRMIVAL_TYPE_STEPWISE = 2, +}; + +/** + * @struct video_frmival + * @brief Video frame interval structure + * + * Used to describe a video frame interval. + */ +struct video_frmival { + /** numerator of the frame interval */ + uint32_t numerator; + /** denominator of the frame interval */ + uint32_t denominator; +}; + +/** + * @struct video_frmival_stepwise + * @brief Video frame interval stepwise structure + * + * Used to describe the video frame interval stepwise type. + */ +struct video_frmival_stepwise { + /** minimum frame interval in seconds */ + struct video_frmival min; + /** maximum frame interval in seconds */ + struct video_frmival max; + /** frame interval step size in seconds */ + struct video_frmival step; +}; + +/** + * @struct video_frmival_enum + * @brief Video frame interval enumeration structure + * + * Used to describe the supported video frame intervals of a given video format. + */ +struct video_frmival_enum { + /** frame interval index during enumeration */ + uint32_t index; + /** video format for which the query is made */ + const struct video_format *format; + /** frame interval type the device supports */ + enum video_frmival_type type; + /** the actual frame interval */ + union { + struct video_frmival discrete; + struct video_frmival_stepwise stepwise; + }; }; /** @@ -124,10 +208,14 @@ struct video_buffer { * Identify the video device endpoint. */ enum video_endpoint_id { - VIDEO_EP_NONE, - VIDEO_EP_ANY, - VIDEO_EP_IN, - VIDEO_EP_OUT, + /** Targets some part of the video device not bound to an endpoint */ + VIDEO_EP_NONE = -1, + /** Targets all input or output endpoints of the device */ + VIDEO_EP_ALL = -2, + /** Targets all input endpoints of the device: those consuming data */ + VIDEO_EP_IN = -3, + /** Targets all output endpoints of the device: those producing data */ + VIDEO_EP_OUT = -4, }; /** @@ -147,8 +235,7 @@ enum video_signal_result { * * See video_set_format() for argument descriptions. */ -typedef int (*video_api_set_format_t)(const struct device *dev, - enum video_endpoint_id ep, +typedef int (*video_api_set_format_t)(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt); /** @@ -157,18 +244,43 @@ typedef int (*video_api_set_format_t)(const struct device *dev, * * See video_get_format() for argument descriptions. */ -typedef int (*video_api_get_format_t)(const struct device *dev, - enum video_endpoint_id ep, +typedef int (*video_api_get_format_t)(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt); +/** + * @typedef video_api_set_frmival_t + * @brief Set video frame interval + * + * See video_set_frmival() for argument descriptions. + */ +typedef int (*video_api_set_frmival_t)(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival *frmival); + +/** + * @typedef video_api_get_frmival_t + * @brief Get current video frame interval + * + * See video_get_frmival() for argument descriptions. + */ +typedef int (*video_api_get_frmival_t)(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival *frmival); + +/** + * @typedef video_api_enum_frmival_t + * @brief List all supported frame intervals of a given format + * + * See video_enum_frmival() for argument descriptions. + */ +typedef int (*video_api_enum_frmival_t)(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival_enum *fie); + /** * @typedef video_api_enqueue_t * @brief Enqueue a buffer in the driver’s incoming queue. * * See video_enqueue() for argument descriptions. */ -typedef int (*video_api_enqueue_t)(const struct device *dev, - enum video_endpoint_id ep, +typedef int (*video_api_enqueue_t)(const struct device *dev, enum video_endpoint_id ep, struct video_buffer *buf); /** @@ -177,10 +289,8 @@ typedef int (*video_api_enqueue_t)(const struct device *dev, * * See video_dequeue() for argument descriptions. */ -typedef int (*video_api_dequeue_t)(const struct device *dev, - enum video_endpoint_id ep, - struct video_buffer **buf, - k_timeout_t timeout); +typedef int (*video_api_dequeue_t)(const struct device *dev, enum video_endpoint_id ep, + struct video_buffer **buf, k_timeout_t timeout); /** * @typedef video_api_flush_t @@ -189,9 +299,7 @@ typedef int (*video_api_dequeue_t)(const struct device *dev, * * See video_flush() for argument descriptions. */ -typedef int (*video_api_flush_t)(const struct device *dev, - enum video_endpoint_id ep, - bool cancel); +typedef int (*video_api_flush_t)(const struct device *dev, enum video_endpoint_id ep, bool cancel); /** * @typedef video_api_stream_start_t @@ -215,9 +323,7 @@ typedef int (*video_api_stream_stop_t)(const struct device *dev); * * See video_set_ctrl() for argument descriptions. */ -typedef int (*video_api_set_ctrl_t)(const struct device *dev, - unsigned int cid, - void *value); +typedef int (*video_api_set_ctrl_t)(const struct device *dev, unsigned int cid, void *value); /** * @typedef video_api_get_ctrl_t @@ -225,9 +331,7 @@ typedef int (*video_api_set_ctrl_t)(const struct device *dev, * * See video_get_ctrl() for argument descriptions. */ -typedef int (*video_api_get_ctrl_t)(const struct device *dev, - unsigned int cid, - void *value); +typedef int (*video_api_get_ctrl_t)(const struct device *dev, unsigned int cid, void *value); /** * @typedef video_api_get_caps_t @@ -235,8 +339,7 @@ typedef int (*video_api_get_ctrl_t)(const struct device *dev, * * See video_get_caps() for argument descriptions. */ -typedef int (*video_api_get_caps_t)(const struct device *dev, - enum video_endpoint_id ep, +typedef int (*video_api_get_caps_t)(const struct device *dev, enum video_endpoint_id ep, struct video_caps *caps); /** @@ -245,8 +348,7 @@ typedef int (*video_api_get_caps_t)(const struct device *dev, * * See video_set_signal() for argument descriptions. */ -typedef int (*video_api_set_signal_t)(const struct device *dev, - enum video_endpoint_id ep, +typedef int (*video_api_set_signal_t)(const struct device *dev, enum video_endpoint_id ep, struct k_poll_signal *signal); __subsystem struct video_driver_api { @@ -261,8 +363,11 @@ __subsystem struct video_driver_api { video_api_dequeue_t dequeue; video_api_flush_t flush; video_api_set_ctrl_t set_ctrl; - video_api_set_ctrl_t get_ctrl; + video_api_get_ctrl_t get_ctrl; video_api_set_signal_t set_signal; + video_api_set_frmival_t set_frmival; + video_api_get_frmival_t get_frmival; + video_api_enum_frmival_t enum_frmival; }; /** @@ -279,12 +384,10 @@ __subsystem struct video_driver_api { * @retval -ENOTSUP If format is not supported. * @retval -EIO General input / output error. */ -static inline int video_set_format(const struct device *dev, - enum video_endpoint_id ep, +static inline int video_set_format(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->set_format == NULL) { return -ENOSYS; @@ -304,12 +407,10 @@ static inline int video_set_format(const struct device *dev, * * @retval pointer to video format */ -static inline int video_get_format(const struct device *dev, - enum video_endpoint_id ep, +static inline int video_get_format(const struct device *dev, enum video_endpoint_id ep, struct video_format *fmt) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->get_format == NULL) { return -ENOSYS; @@ -318,6 +419,91 @@ static inline int video_get_format(const struct device *dev, return api->get_format(dev, ep, fmt); } +/** + * @brief Set video frame interval. + * + * Configure video device with a specific frame interval. + * + * Drivers must not return an error solely because the requested interval doesn’t match the device + * capabilities. They must instead modify the interval to match what the hardware can provide. + * + * @param dev Pointer to the device structure for the driver instance. + * @param ep Endpoint ID. + * @param frmival Pointer to a video frame interval struct. + * + * @retval 0 If successful. + * @retval -ENOSYS If API is not implemented. + * @retval -EINVAL If parameters are invalid. + * @retval -EIO General input / output error. + */ +static inline int video_set_frmival(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival *frmival) +{ + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; + + if (api->set_frmival == NULL) { + return -ENOSYS; + } + + return api->set_frmival(dev, ep, frmival); +} + +/** + * @brief Get video frame interval. + * + * Get current frame interval of the video device. + * + * @param dev Pointer to the device structure for the driver instance. + * @param ep Endpoint ID. + * @param frmival Pointer to a video frame interval struct. + * + * @retval 0 If successful. + * @retval -ENOSYS If API is not implemented. + * @retval -EINVAL If parameters are invalid. + * @retval -EIO General input / output error. + */ +static inline int video_get_frmival(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival *frmival) +{ + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; + + if (api->get_frmival == NULL) { + return -ENOSYS; + } + + return api->get_frmival(dev, ep, frmival); +} + +/** + * @brief List video frame intervals. + * + * List all supported video frame intervals of a given format. + * + * Applications should fill the pixelformat, width and height fields of the + * video_frmival_enum struct first to form a query. Then, the index field is + * used to iterate through the supported frame intervals list. + * + * @param dev Pointer to the device structure for the driver instance. + * @param ep Endpoint ID. + * @param fie Pointer to a video frame interval enumeration struct. + * + * @retval 0 If successful. + * @retval -ENOSYS If API is not implemented. + * @retval -EINVAL If parameters are invalid. + * @retval -EIO General input / output error. + */ +static inline int video_enum_frmival(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival_enum *fie) +{ + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; + + if (api->enum_frmival == NULL) { + return -ENOSYS; + } + + return api->enum_frmival(dev, ep, fie); +} + /** * @brief Enqueue a video buffer. * @@ -332,12 +518,10 @@ static inline int video_get_format(const struct device *dev, * @retval -EINVAL If parameters are invalid. * @retval -EIO General input / output error. */ -static inline int video_enqueue(const struct device *dev, - enum video_endpoint_id ep, +static inline int video_enqueue(const struct device *dev, enum video_endpoint_id ep, struct video_buffer *buf) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->enqueue == NULL) { return -ENOSYS; @@ -361,13 +545,10 @@ static inline int video_enqueue(const struct device *dev, * @retval -EINVAL If parameters are invalid. * @retval -EIO General input / output error. */ -static inline int video_dequeue(const struct device *dev, - enum video_endpoint_id ep, - struct video_buffer **buf, - k_timeout_t timeout) +static inline int video_dequeue(const struct device *dev, enum video_endpoint_id ep, + struct video_buffer **buf, k_timeout_t timeout) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->dequeue == NULL) { return -ENOSYS; @@ -376,7 +557,6 @@ static inline int video_dequeue(const struct device *dev, return api->dequeue(dev, ep, buf, timeout); } - /** * @brief Flush endpoint buffers. * @@ -391,12 +571,9 @@ static inline int video_dequeue(const struct device *dev, * * @retval 0 Is successful, -ERRNO code otherwise. */ -static inline int video_flush(const struct device *dev, - enum video_endpoint_id ep, - bool cancel) +static inline int video_flush(const struct device *dev, enum video_endpoint_id ep, bool cancel) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->flush == NULL) { return -ENOSYS; @@ -419,8 +596,7 @@ static inline int video_flush(const struct device *dev, */ static inline int video_stream_start(const struct device *dev) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->stream_start == NULL) { return -ENOSYS; @@ -440,8 +616,7 @@ static inline int video_stream_start(const struct device *dev) */ static inline int video_stream_stop(const struct device *dev) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; int ret; if (api->stream_stop == NULL) { @@ -449,7 +624,7 @@ static inline int video_stream_stop(const struct device *dev) } ret = api->stream_stop(dev); - video_flush(dev, VIDEO_EP_ANY, true); + video_flush(dev, VIDEO_EP_ALL, true); return ret; } @@ -463,12 +638,10 @@ static inline int video_stream_stop(const struct device *dev) * * @retval 0 Is successful, -ERRNO code otherwise. */ -static inline int video_get_caps(const struct device *dev, - enum video_endpoint_id ep, +static inline int video_get_caps(const struct device *dev, enum video_endpoint_id ep, struct video_caps *caps) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->get_caps == NULL) { return -ENOSYS; @@ -492,11 +665,9 @@ static inline int video_get_caps(const struct device *dev, * @retval -ENOTSUP If format is not supported. * @retval -EIO General input / output error. */ -static inline int video_set_ctrl(const struct device *dev, unsigned int cid, - void *value) +static inline int video_set_ctrl(const struct device *dev, unsigned int cid, void *value) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->set_ctrl == NULL) { return -ENOSYS; @@ -520,11 +691,9 @@ static inline int video_set_ctrl(const struct device *dev, unsigned int cid, * @retval -ENOTSUP If format is not supported. * @retval -EIO General input / output error. */ -static inline int video_get_ctrl(const struct device *dev, unsigned int cid, - void *value) +static inline int video_get_ctrl(const struct device *dev, unsigned int cid, void *value) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->get_ctrl == NULL) { return -ENOSYS; @@ -546,12 +715,10 @@ static inline int video_get_ctrl(const struct device *dev, unsigned int cid, * * @retval 0 Is successful, -ERRNO code otherwise. */ -static inline int video_set_signal(const struct device *dev, - enum video_endpoint_id ep, +static inline int video_set_signal(const struct device *dev, enum video_endpoint_id ep, struct k_poll_signal *signal) { - const struct video_driver_api *api = - (const struct video_driver_api *)dev->api; + const struct video_driver_api *api = (const struct video_driver_api *)dev->api; if (api->set_signal == NULL) { return -ENOSYS; @@ -565,19 +732,21 @@ static inline int video_set_signal(const struct device *dev, * * @param size Size of the video buffer (in bytes). * @param align Alignment of the requested memory, must be a power of two. + * @param timeout Timeout duration or K_NO_WAIT * * @retval pointer to allocated video buffer */ -struct video_buffer *video_buffer_aligned_alloc(size_t size, size_t align); +struct video_buffer *video_buffer_aligned_alloc(size_t size, size_t align, k_timeout_t timeout); /** * @brief Allocate video buffer. * * @param size Size of the video buffer (in bytes). + * @param timeout Timeout duration or K_NO_WAIT * * @retval pointer to allocated video buffer */ -struct video_buffer *video_buffer_alloc(size_t size); +struct video_buffer *video_buffer_alloc(size_t size, k_timeout_t timeout); /** * @brief Release a video buffer. @@ -586,12 +755,67 @@ struct video_buffer *video_buffer_alloc(size_t size); */ void video_buffer_release(struct video_buffer *buf); +/** + * @brief Search for a format that matches in a list of capabilities + * + * @param fmts The format capability list to search. + * @param fmt The format to find in the list. + * @param idx The pointer to a number of the first format that matches. + * + * @return 0 when a format is found. + * @return -ENOENT when no matching format is found. + */ +int video_format_caps_index(const struct video_format_cap *fmts, const struct video_format *fmt, + size_t *idx); + +/** + * @brief Compute the difference between two frame intervals + * + * @param frmival Frame interval to turn into microseconds. + * + * @return The frame interval value in microseconds. + */ +static inline uint64_t video_frmival_nsec(const struct video_frmival *frmival) +{ + return (uint64_t)NSEC_PER_SEC * frmival->numerator / frmival->denominator; +} + +/** + * @brief Find the closest match to a frame interval value within a stepwise frame interval. + * + * @param stepwise The stepwise frame interval range to search + * @param desired The frame interval for which find the closest match + * @param match The resulting frame interval closest to @p desired + */ +void video_closest_frmival_stepwise(const struct video_frmival_stepwise *stepwise, + const struct video_frmival *desired, + struct video_frmival *match); + +/** + * @brief Find the closest match to a frame interval value within a video device. + * + * To compute the closest match, fill @p match with the following fields: + * + * - @c match->format to the @ref video_format of interest. + * - @c match->type to @ref VIDEO_FRMIVAL_TYPE_DISCRETE. + * - @c match->discrete to the desired frame interval. + * + * The result will be loaded into @p match, with the following fields set: + * + * - @c match->discrete to the value of the closest frame interval. + * - @c match->index to the index of the closest frame interval. + * + * @param dev Video device to query. + * @param ep Video endpoint ID to query. + * @param match Frame interval enumerator with the query, and loaded with the result. + */ +void video_closest_frmival(const struct device *dev, enum video_endpoint_id ep, + struct video_frmival_enum *match); /* fourcc - four-character-code */ -#define video_fourcc(a, b, c, d)\ +#define video_fourcc(a, b, c, d) \ ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) - /** * @defgroup video_pixel_formats Video pixel formats * @{ @@ -603,13 +827,13 @@ void video_buffer_release(struct video_buffer *buf); */ /** BGGR8 pixel format */ -#define VIDEO_PIX_FMT_BGGR8 video_fourcc('B', 'G', 'G', 'R') /* 8 BGBG.. GRGR.. */ +#define VIDEO_PIX_FMT_BGGR8 video_fourcc('B', 'G', 'G', 'R') /* 8 BGBG.. GRGR.. */ /** GBRG8 pixel format */ -#define VIDEO_PIX_FMT_GBRG8 video_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ +#define VIDEO_PIX_FMT_GBRG8 video_fourcc('G', 'B', 'R', 'G') /* 8 GBGB.. RGRG.. */ /** GRBG8 pixel format */ -#define VIDEO_PIX_FMT_GRBG8 video_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ +#define VIDEO_PIX_FMT_GRBG8 video_fourcc('G', 'R', 'B', 'G') /* 8 GRGR.. BGBG.. */ /** RGGB8 pixel format */ -#define VIDEO_PIX_FMT_RGGB8 video_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */ +#define VIDEO_PIX_FMT_RGGB8 video_fourcc('R', 'G', 'G', 'B') /* 8 RGRG.. GBGB.. */ /** * @} @@ -652,7 +876,7 @@ void video_buffer_release(struct video_buffer *buf); */ /** JPEG pixel format */ -#define VIDEO_PIX_FMT_JPEG video_fourcc('J', 'P', 'E', 'G') /* 8 JPEG */ +#define VIDEO_PIX_FMT_JPEG video_fourcc('J', 'P', 'E', 'G') /* 8 JPEG */ /** * @} @@ -662,6 +886,30 @@ void video_buffer_release(struct video_buffer *buf); * @} */ +/** + * @brief Get number of bytes per pixel of a pixel format + * + * @param pixfmt FourCC pixel format value (\ref video_pixel_formats). + */ +static inline unsigned int video_pix_fmt_bpp(uint32_t pixfmt) +{ + switch (pixfmt) { + case VIDEO_PIX_FMT_BGGR8: + case VIDEO_PIX_FMT_GBRG8: + case VIDEO_PIX_FMT_GRBG8: + case VIDEO_PIX_FMT_RGGB8: + return 1; + case VIDEO_PIX_FMT_RGB565: + case VIDEO_PIX_FMT_YUYV: + return 2; + case VIDEO_PIX_FMT_XRGB32: + case VIDEO_PIX_FMT_XYUV32: + return 4; + default: + return 0; + } +} + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/w1.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/w1.h index a233712a..fe264489 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/w1.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/w1.h @@ -435,7 +435,7 @@ struct w1_rom { /** @brief The 1-Wire family code identifying the slave device type. * * An incomplete list of family codes is available at: - * https://www.maximintegrated.com/en/app-notes/index.mvp/id/155 + * https://www.analog.com/en/resources/technical-articles/1wire-software-resource-guide-device-description.html * others are documented in the respective device data sheet. */ uint8_t family; @@ -584,7 +584,7 @@ int w1_write_read(const struct device *dev, const struct w1_slave_config *config * If a callback is passed, the callback is called for each found slave. * * The algorithm mostly follows the suggestions of - * https://pdfserv.maximintegrated.com/en/an/AN187.pdf + * https://www.analog.com/en/resources/app-notes/1wire-search-algorithm.html * * Note: Filtering on families is not supported. * @@ -695,7 +695,7 @@ static inline uint8_t w1_crc8(const uint8_t *src, size_t len) * X^16 + X^15 * + X^2 + 1 with the initial value set to 0x0000. * See also APPLICATION NOTE 27: * "UNDERSTANDING AND USING CYCLIC REDUNDANCY CHECKS WITH MAXIM 1-WIRE AND IBUTTON PRODUCTS" - * https://www.maximintegrated.com/en/design/technical-documents/app-notes/2/27.html + * https://www.analog.com/en/resources/technical-articles/understanding-and-using-cyclic-redundancy-checks-with-maxim-1wire-and-ibutton-products.html * * @param seed Init value for the CRC, it is usually set to 0x0000. * @param[in] src Input bytes for the computation. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h new file mode 100644 index 00000000..e66db6c4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing QSPI device interface specific declarations for the + * Zephyr OS layer of the Wi-Fi driver. + */ + +#ifndef __QSPI_IF_H__ +#define __QSPI_IF_H__ + +#include +#include +#ifdef CONFIG_NRF70_ON_QSPI +#include +#endif + +#define RPU_WAKEUP_NOW BIT(0) /* WAKEUP RPU - RW */ +#define RPU_AWAKE_BIT BIT(1) /* RPU AWAKE FROM SLEEP - RO */ +#define RPU_READY_BIT BIT(2) /* RPU IS READY - RO*/ + +struct qspi_config { +#ifdef CONFIG_NRF70_ON_QSPI + nrf_qspi_addrmode_t addrmode; + nrf_qspi_readoc_t readoc; + nrf_qspi_writeoc_t writeoc; + nrf_qspi_frequency_t sckfreq; +#endif + unsigned char RDC4IO; + bool easydma; + bool single_op; + bool quad_spi; + bool encryption; + bool CMD_CNONCE; + bool enc_enabled; + struct k_sem lock; + unsigned int addrmask; + unsigned char qspi_slave_latency; +#if defined(CONFIG_NRF70_ON_QSPI) && (NRF_QSPI_HAS_XIP_ENC || NRF_QSPI_HAS_DMA_ENC) + nrf_qspi_encryption_t p_cfg; +#endif /*CONFIG_NRF70_ON_QSPI && (NRF_QSPI_HAS_XIP_ENC || NRF_QSPI_HAS_DMA_ENC)*/ + int test_hlread; + char *test_name; + int test_start; + int test_end; + int test_iterations; + int test_timediff_read; + int test_timediff_write; + int test_status; + int test_iteration; +}; +struct qspi_dev { + int (*deinit)(void); + void *config; + int (*init)(struct qspi_config *config); + int (*write)(unsigned int addr, const void *data, int len); + int (*read)(unsigned int addr, void *data, int len); + int (*hl_read)(unsigned int addr, void *data, int len); + void (*hard_reset)(void); +}; + +int qspi_cmd_wakeup_rpu(const struct device *dev, uint8_t data); + +int qspi_init(struct qspi_config *config); + +int qspi_write(unsigned int addr, const void *data, int len); + +int qspi_read(unsigned int addr, void *data, int len); + +int qspi_hl_read(unsigned int addr, void *data, int len); + +int qspi_deinit(void); + +void gpio_free_irq(int pin, struct gpio_callback *button_cb_data); + +int gpio_request_irq(int pin, struct gpio_callback *button_cb_data, void (*irq_handler)()); + +struct qspi_config *qspi_defconfig(void); + +struct qspi_dev *qspi_dev(void); +struct qspi_config *qspi_get_config(void); + +int qspi_cmd_sleep_rpu(const struct device *dev); + +void hard_reset(void); +void get_sleep_stats(uint32_t addr, uint32_t *buff, uint32_t wrd_len); + +extern struct device qspi_perip; + +int qspi_validate_rpu_wake_writecmd(const struct device *dev); +int qspi_cmd_wakeup_rpu(const struct device *dev, uint8_t data); +int qspi_wait_while_rpu_awake(const struct device *dev); + +int qspi_RDSR1(const struct device *dev, uint8_t *rdsr1); +int qspi_RDSR2(const struct device *dev, uint8_t *rdsr2); +int qspi_WRSR2(const struct device *dev, const uint8_t wrsr2); + +#ifdef CONFIG_NRF_WIFI_LOW_POWER +int func_rpu_sleep(void); +int func_rpu_wake(void); +int func_rpu_sleep_status(void); +#endif /* CONFIG_NRF_WIFI_LOW_POWER */ + +#define QSPI_KEY_LEN_BYTES 16 + +/*! \brief Enable encryption + * + * \param key Pointer to the 128-bit key + * \return 0 on success, negative errno code on failure. + */ +int qspi_enable_encryption(uint8_t *key); + +#endif /* __QSPI_IF_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/bus/rpu_hw_if.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/bus/rpu_hw_if.h new file mode 100644 index 00000000..2524b64a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/bus/rpu_hw_if.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @brief Header containing common functions for RPU hardware interaction + * using QSPI and SPI that can be invoked by shell or the driver. + */ + +#ifndef __RPU_HW_IF_H_ +#define __RPU_HW_IF_H_ + +#include +#include +#include + +enum { + SYSBUS = 0, + EXT_SYS_BUS, + PBUS, + PKTRAM, + GRAM, + LMAC_ROM, + LMAC_RET_RAM, + LMAC_SRC_RAM, + UMAC_ROM, + UMAC_RET_RAM, + UMAC_SRC_RAM, + NUM_MEM_BLOCKS +}; + +extern char blk_name[][15]; +extern uint32_t rpu_7002_memmap[][3]; + +int rpu_read(unsigned int addr, void *data, int len); +int rpu_write(unsigned int addr, const void *data, int len); + +int rpu_sleep(void); +int rpu_wakeup(void); +int rpu_sleep_status(void); +void rpu_get_sleep_stats(uint32_t addr, uint32_t *buff, uint32_t wrd_len); +int rpu_irq_config(struct gpio_callback *irq_callback_data, void (*irq_handler)()); +int rpu_irq_remove(struct gpio_callback *irq_callback_data); + +int rpu_wrsr2(uint8_t data); +int rpu_rdsr2(void); +int rpu_rdsr1(void); +int rpu_clks_on(void); + +int rpu_init(void); +int rpu_enable(void); +int rpu_disable(void); + +#ifdef CONFIG_NRF70_SR_COEX_RF_SWITCH +int sr_ant_switch(unsigned int ant_switch); +int sr_gpio_remove(void); +int sr_gpio_config(void); +#endif /* CONFIG_NRF70_SR_COEX_RF_SWITCH */ +#endif /* __RPU_HW_IF_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/off_raw_tx/off_raw_tx_api.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/off_raw_tx/off_raw_tx_api.h new file mode 100644 index 00000000..b14ae394 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/drivers/wifi/nrf_wifi/off_raw_tx/off_raw_tx_api.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +/** @file + * + * @addtogroup nrf70_off_raw_tx_api nRF70 Offloaded raw TX API + * @{ + * + * @brief File containing API's for the Offloaded raw TX feature. + */ + +#ifndef INCLUDE_ZEPHYR_DRIVERS_OFF_RAW_TX_API_H_ +#define INCLUDE_ZEPHYR_DRIVERS_OFF_RAW_TX_API_H_ + +#include +#include +#include "osal_api.h" + +/* Minimum frame size for raw packet transmission */ +#define NRF_WIFI_OFF_RAW_TX_FRAME_SIZE_MIN 26 +/* Maximum frame size for raw packet transmission */ +#define NRF_WIFI_OFF_RAW_TX_FRAME_SIZE_MAX 600 +/* Maximum length of country code*/ +#define NRF_WIFI_COUNTRY_CODE_LEN 2 +/** + * @brief- Transmission rates + * Rate to be used for transmitting a packet. + */ +enum nrf_wifi_off_raw_tx_rate { + /** 1 Mbps */ + RATE_1M, + /** 2 Mbps */ + RATE_2M, + /** 5.5 Mbps */ + RATE_5_5M, + /** 11 Mbps */ + RATE_11M, + /** 6 Mbps */ + RATE_6M, + /** 9 Mbps */ + RATE_9M, + /** 12 Mbps */ + RATE_12M, + /** 18 Mbps */ + RATE_18M, + /** 24 Mbps */ + RATE_24M, + /** 36 Mbps */ + RATE_36M, + /** 48 Mbps */ + RATE_48M, + /** 54 Mbps */ + RATE_54M, + /** MCS 0 */ + RATE_MCS0, + /** MCS 1 */ + RATE_MCS1, + /** MCS 2 */ + RATE_MCS2, + /** MCS 3 */ + RATE_MCS3, + /** MCS 4 */ + RATE_MCS4, + /** MCS 5 */ + RATE_MCS5, + /** MCS 6 */ + RATE_MCS6, + /** MCS 7 */ + RATE_MCS7, + /** Invalid rate */ + RATE_MAX +}; + + +/** + * @brief- HE guard interval value + * Value of the guard interval to be used between symbols when transmitting using HE. + */ +enum nrf_wifi_off_raw_tx_he_gi { + /** 800 ns */ + HE_GI_800NS, + /** 1600 ns */ + HE_GI_1600NS, + /** 3200 ns */ + HE_GI_3200NS, + /** Invalid value */ + HE_GI_MAX +}; + + +/** + * @brief- HE long training field duration + * Value of the long training field duration to be used when transmitting using HE. + */ +enum nrf_wifi_off_raw_tx_he_ltf { + /** 3.2us */ + HE_LTF_3200NS, + /** 6.4us */ + HE_LTF_6400NS, + /** 12.8us */ + HE_LTF_12800NS, + /** Invalid value */ + HE_LTF_MAX +}; + +/** + * @brief- Throughput mode + * Throughput mode to be used for transmitting the packet. + */ +enum nrf_wifi_off_raw_tx_tput_mode { + /** Legacy mode */ + TPUT_MODE_LEGACY, + /** High Throughput mode (11n) */ + TPUT_MODE_HT, + /** Very high throughput mode (11ac) */ + TPUT_MODE_VHT, + /** HE SU mode */ + TPUT_MODE_HE_SU, + /** HE ER SU mode */ + TPUT_MODE_HE_ER_SU, + /** HE TB mode */ + TPUT_MODE_HE_TB, + /** Highest throughput mode currently defined */ + TPUT_MODE_MAX +}; + +/** + * @brief This structure defines the Offloaded raw tx debug statistics. + * + */ +struct nrf_wifi_off_raw_tx_stats { + /** Number of packets sent */ + unsigned int off_raw_tx_pkt_sent; +}; + +/** + * @brief- Configuration parameters for offloaded raw TX + * Parameters which can be used to configure the offloaded raw TX operation. + */ +struct nrf_wifi_off_raw_tx_conf { + /** Time interval (in microseconds) between transmissions */ + unsigned int period_us; + /** Transmit power in dBm (0 to 20) */ + unsigned int tx_pwr; + /** Channel number on which to transmit */ + unsigned int chan; + /** Set to TRUE to use short preamble for FALSE to disable short preamble */ + bool short_preamble; + /* Number of times a packet should be retried at each possible rate */ + unsigned int num_retries; + /** Throughput mode for packet transmittion. Refer &enum nrf_wifi_off_raw_tx_tput_mode */ + enum nrf_wifi_off_raw_tx_tput_mode tput_mode; + /* Rate at which packet needs to be transmitted. Refer &enum nrf_wifi_off_raw_tx_rate */ + enum nrf_wifi_off_raw_tx_rate rate; + /** HE GI. Refer &enum nrf_wifi_off_raw_tx_he_gi */ + enum nrf_wifi_off_raw_tx_he_gi he_gi; + /** HE GI. Refer &enum nrf_wifi_off_raw_tx_he_ltf */ + enum nrf_wifi_off_raw_tx_he_ltf he_ltf; + /* Pointer to packet to be transmitted */ + void *pkt; + /** Packet length of the frame to be transmitted, (min 26 bytes and max 600 bytes) */ + unsigned int pkt_len; +}; + + +/** + * @brief Initialize the nRF70 for operating in the offloaded raw TX mode. + * @param mac_addr MAC address to be used for the nRF70 device. + * @param country_code Country code to be set for regularity domain. + * + * This function is initializes the nRF70 device for offloaded raw TX mode by: + * - Powering it up, + * - Downloading a firmware patch (if any). + * - Initializing the firmware to accept further commands + * + * The mac_addr parameter is used to set the MAC address of the nRF70 device. + * This address can be used to override the MAC addresses programmed in the OTP and + * the value configured (if any) in CONFIG_WIFI_FIXED_MAC_ADDRESS. + * The priority order in which the MAC address values for the nRF70 device are used is: + * - If mac_addr is provided, the MAC address is set to the value provided. + * - If CONFIG_WIFI_FIXED_MAC_ADDRESS is enabled, the MAC address uses the Kconfig value. + * - If none of the above are provided, the MAC address is set to the value programmed in the OTP. + * + * @retval 0 If the operation was successful. + * @retval -1 If the operation failed. + */ +int nrf70_off_raw_tx_init(uint8_t *mac_addr, unsigned char *country_code); + +/** + * @brief Initialize the nRF70 for operating in the offloaded raw TX mode. + * + * This function is deinitializes the nRF70 device. + * + */ +void nrf70_off_raw_tx_deinit(void); + +/** + * @brief Update the configured offloaded raw TX parameters. + * @param conf Configuration parameters to be updated for the offloaded raw TX operation. + * + * This function is used to update configured parameters for offloaded raw TX operation. + * This function should be used to when the parameters need to be updated during an ongoing + * raw TX operation without having to stop it. + * + * @retval 0 If the operation was successful. + * @retval -1 If the operation failed. + */ +int nrf70_off_raw_tx_conf_update(struct nrf_wifi_off_raw_tx_conf *conf); + +/** + * @brief Start the offloaded raw TX. + * @param conf Configuration parameters necessary for the offloaded raw TX operation. + * + * This function is used to start offloaded raw TX operation. When this function is invoked + * the nRF70 device will start transmitting frames as per the configuration specified by @p conf. + * + * @retval 0 If the operation was successful. + * @retval -1 If the operation failed. + */ +int nrf70_off_raw_tx_start(struct nrf_wifi_off_raw_tx_conf *conf); + +/** + * @brief Stop the offloaded raw TX. + * + * This function is used to stop offloaded raw TX operation. When this function is invoked + * the nRF70 device will stop transmitting frames. + * + * @retval 0 If the operation was successful. + * @retval -1 If the operation failed. + */ +int nrf70_off_raw_tx_stop(void); + +/** + * @brief Get the MAC address of the nRF70 device. + * @param mac_addr Buffer to store the MAC address. + * + * This function is used to get the MAC address of the nRF70 device. + * The MAC address is stored in the buffer pointed by mac_addr. + * The MAC address is expected to be a 6 byte value. + * + * @retval 0 If the operation was successful. + * @retval -1 If the operation failed. + */ +int nrf70_off_raw_tx_mac_addr_get(uint8_t *mac_addr); + +/** + * @brief Get statistics of the offloaded raw TX. + * @param off_raw_tx_stats Statistics of the offloaded raw TX operation. + * + * This function is used to get statistics of offloaded raw TX operation. When this function + * is invoked the nRF70 device will show statistics. + * + * @retval 0 If the operation was successful. + * @retval -1 If the operation failed. + */ +int nrf70_off_raw_tx_stats(struct nrf_wifi_off_raw_tx_stats *off_raw_tx_stats); +/** + * @} + */ +#endif /* INCLUDE_ZEPHYR_DRIVERS_OFF_RAW_TX_API_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath.h index 0c85ca62..173731d0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath.h @@ -8,8 +8,8 @@ * @brief Public APIs for DSP basicmath */ -#ifndef INCLUDE_ZEPHYR_DSP_BASICMATH_H_ -#define INCLUDE_ZEPHYR_DSP_BASICMATH_H_ +#ifndef ZEPHYR_INCLUDE_DSP_BASICMATH_H_ +#define ZEPHYR_INCLUDE_DSP_BASICMATH_H_ #include @@ -929,4 +929,4 @@ DSP_FUNC_SCOPE void zdsp_clip_q7(const DSP_DATA q7_t *src, DSP_DATA q7_t *dst, q #include #endif /* CONFIG_FP16 */ -#endif /* INCLUDE_ZEPHYR_DSP_BASICMATH_H_ */ +#endif /* ZEPHYR_INCLUDE_DSP_BASICMATH_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath_f16.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath_f16.h index 23239e9a..84401da9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath_f16.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/basicmath_f16.h @@ -8,8 +8,8 @@ * @brief Public APIs for DSP basicmath for 16 bit floating point */ -#ifndef INCLUDE_ZEPHYR_DSP_BASICMATH_F16_H_ -#define INCLUDE_ZEPHYR_DSP_BASICMATH_F16_H_ +#ifndef ZEPHYR_INCLUDE_DSP_BASICMATH_F16_H_ +#define ZEPHYR_INCLUDE_DSP_BASICMATH_F16_H_ #ifndef CONFIG_FP16 #error "Cannot use float16 DSP functionality without CONFIG_FP16 enabled" @@ -121,4 +121,4 @@ DSP_FUNC_SCOPE void zdsp_clip_f16(const float16_t *src, float16_t *dst, float16_ } #endif -#endif /* INCLUDE_ZEPHYR_DSP_BASICMATH_F16_H_ */ +#endif /* ZEPHYR_INCLUDE_DSP_BASICMATH_F16_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/dsp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/dsp.h index beef08fb..1ffa2111 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/dsp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/dsp.h @@ -8,8 +8,8 @@ * @brief Public APIs for Digital Signal Processing (DSP) math. */ -#ifndef INCLUDE_ZEPHYR_DSP_DSP_H_ -#define INCLUDE_ZEPHYR_DSP_DSP_H_ +#ifndef ZEPHYR_INCLUDE_DSP_DSP_H_ +#define ZEPHYR_INCLUDE_DSP_DSP_H_ #ifdef CONFIG_DSP_BACKEND_HAS_STATIC #define DSP_FUNC_SCOPE static @@ -44,4 +44,4 @@ #include "zdsp_backend.h" -#endif /* INCLUDE_ZEPHYR_DSP_DSP_H_ */ +#endif /* ZEPHYR_INCLUDE_DSP_DSP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/print_format.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/print_format.h index dd7d7128..014aebee 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/print_format.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/print_format.h @@ -2,8 +2,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_ZEPHYR_DSP_PRINT_FORMAT_H -#define ZEPHYR_INCLUDE_ZEPHYR_DSP_PRINT_FORMAT_H +#ifndef ZEPHYR_INCLUDE_DSP_PRINT_FORMAT_H_ +#define ZEPHYR_INCLUDE_DSP_PRINT_FORMAT_H_ #include #include @@ -63,4 +63,4 @@ static inline int64_t ___PRIq_arg_shift(int64_t q, int shift) * @} */ -#endif /* ZEPHYR_INCLUDE_ZEPHYR_DSP_PRINT_FORMAT_H */ +#endif /* ZEPHYR_INCLUDE_DSP_PRINT_FORMAT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/types.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/types.h index 52ce2ab2..2ee02fb0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/types.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dsp/types.h @@ -2,8 +2,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef INCLUDE_ZEPHYR_DSP_TYPES_H_ -#define INCLUDE_ZEPHYR_DSP_TYPES_H_ +#ifndef ZEPHYR_INCLUDE_DSP_TYPES_H_ +#define ZEPHYR_INCLUDE_DSP_TYPES_H_ #include @@ -68,4 +68,4 @@ typedef double float64_t; * @} */ -#endif /* INCLUDE_ZEPHYR_DSP_TYPES_H_ */ +#endif /* ZEPHYR_INCLUDE_DSP_TYPES_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h index 1d875b8e..62d9b7cc 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-adc.h @@ -18,15 +18,4 @@ #define NRF_ADC_AIN6 BIT(6) #define NRF_ADC_AIN7 BIT(7) -#define NRF_SAADC_AIN0 1 -#define NRF_SAADC_AIN1 2 -#define NRF_SAADC_AIN2 3 -#define NRF_SAADC_AIN3 4 -#define NRF_SAADC_AIN4 5 -#define NRF_SAADC_AIN5 6 -#define NRF_SAADC_AIN6 7 -#define NRF_SAADC_AIN7 8 -#define NRF_SAADC_VDD 9 -#define NRF_SAADC_VDDHDIV5 13 - #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_ADC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h new file mode 100644 index 00000000..19da4ff6 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h @@ -0,0 +1,15 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Nordic Semiconductor ASA + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_NRF54L_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_NRF54L_H_ + +#include + +#define NRF_SAADC_AVDD 10 +#define NRF_SAADC_DVDD 11 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_NRF54L_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v2.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v2.h new file mode 100644 index 00000000..f5f72bec --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v2.h @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Nordic Semiconductor ASA + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V2_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V2_H_ + +#include + +#define NRF_SAADC_VDD 9 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V2_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v3.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v3.h new file mode 100644 index 00000000..c51bab1a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc-v3.h @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Nordic Semiconductor ASA + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V3_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V3_H_ + +#include + +#define NRF_SAADC_VDDHDIV5 13 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_V3_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc.h new file mode 100644 index 00000000..4a3deb95 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/adc/nrf-saadc.h @@ -0,0 +1,19 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Nordic Semiconductor ASA + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_ + +#define NRF_SAADC_AIN0 1 +#define NRF_SAADC_AIN1 2 +#define NRF_SAADC_AIN2 3 +#define NRF_SAADC_AIN3 4 +#define NRF_SAADC_AIN4 5 +#define NRF_SAADC_AIN5 6 +#define NRF_SAADC_AIN6 7 +#define NRF_SAADC_AIN7 8 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_NRF_SAADC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/battery/battery.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/battery/battery.h new file mode 100644 index 00000000..d04242ea --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/battery/battery.h @@ -0,0 +1,37 @@ +/* + * Copyright 2024 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + * + * The following open-circuit voltage curves have been extracted from the datasheets of the + * listed battery parts. They will not be 100% correct for all batteries of the chemistry, + * but should provide a good baseline. These curves will also be affected by ambient temperature + * and discharge current. + * + * Each curve is 11 elements representing the OCV voltage in microvolts for each charge percentage + * from 0% to 100% inclusive in 10% increments. + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_BATTERY_BATTERY_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_BATTERY_BATTERY_H_ + +/* Panasonic KR-1800SCE */ +#define BATTERY_OCV_CURVE_NICKEL_CADMIUM_DEFAULT \ + 800000 1175000 1207000 1217000 1221000 1226000 1233000 1245000 1266000 1299000 1366000 + +/* Panasonic BK-1100FHU */ +#define BATTERY_OCV_CURVE_NICKEL_METAL_HYDRIDE_DEFAULT \ + 1004000 1194000 1231000 1244000 1254000 1257000 1263000 1266000 1274000 1315000 1420000 + +/* Panasonic NCR18650BF */ +#define BATTERY_OCV_CURVE_LITHIUM_ION_POLYMER_DEFAULT \ + 2502000 3146000 3372000 3449000 3532000 3602000 3680000 3764000 3842000 3936000 4032000 + +/* Drypower IFR18650 E1600 */ +#define BATTERY_OCV_CURVE_LITHIUM_IRON_PHOSPHATE_DEFAULT \ + 2013000 3068000 3159000 3194000 3210000 3221000 3229000 3246000 3256000 3262000 3348000 + +/* FDK CR14250SE */ +#define BATTERY_OCV_CURVE_LITHIUM_MANGANESE_DEFAULT \ + 1906000 2444000 2689000 2812000 2882000 2927000 2949000 2955000 2962000 2960000 2985000 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_BATTERY_BATTERY_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/adi_max32_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/adi_max32_clock.h index 44fb918c..e0cd17c2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/adi_max32_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/adi_max32_clock.h @@ -21,5 +21,7 @@ #define ADI_MAX32_PRPH_CLK_SRC_INRO 5 /* Internal Nano Ring Oscillator */ #define ADI_MAX32_PRPH_CLK_SRC_ISO 6 /* Internal Secondary Oscillator */ #define ADI_MAX32_PRPH_CLK_SRC_IBRO_DIV8 7 /* IBRO/8 */ +#define ADI_MAX32_PRPH_CLK_SRC_IPLL 8 /* Internal Phase Lock Loop Oscillator */ +#define ADI_MAX32_PRPH_CLK_SRC_EBO 9 /* External Base Oscillator */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ADI_MAX32_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h new file mode 100644 index 00000000..128e370e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __CH32V00X_CLOCKS_H__ +#define __CH32V00X_CLOCKS_H__ + +#define CH32V00X_AHB_PCENR_OFFSET 0 +#define CH32V00X_APB2_PCENR_OFFSET 1 +#define CH32V00X_APB1_PCENR_OFFSET 2 + +#define CH32V00X_CLOCK_CONFIG(bus, bit) (((CH32V00X_##bus##_PCENR_OFFSET) << 5) | (bit)) + +#define CH32V00X_CLOCK_DMA1 CH32V00X_CLOCK_CONFIG(AHB, 0) +#define CH32V00X_CLOCK_SRAM CH32V00X_CLOCK_CONFIG(AHB, 2) +#define CH32V00X_CLOCK_FLITF CH32V00X_CLOCK_CONFIG(AHB, 4) +#define CH32V00X_CLOCK_CRC CH32V00X_CLOCK_CONFIG(AHB, 6) +#define CH32V00X_CLOCK_USB CH32V00X_CLOCK_CONFIG(AHB, 12) + +#define CH32V00X_CLOCK_AFIO CH32V00X_CLOCK_CONFIG(APB2, 0) +#define CH32V00X_CLOCK_IOPA CH32V00X_CLOCK_CONFIG(APB2, 2) +#define CH32V00X_CLOCK_IOPB CH32V00X_CLOCK_CONFIG(APB2, 3) +#define CH32V00X_CLOCK_IOPC CH32V00X_CLOCK_CONFIG(APB2, 4) +#define CH32V00X_CLOCK_IOPD CH32V00X_CLOCK_CONFIG(APB2, 5) +#define CH32V00X_CLOCK_ADC1 CH32V00X_CLOCK_CONFIG(APB2, 9) +#define CH32V00X_CLOCK_ADC2 CH32V00X_CLOCK_CONFIG(APB2, 10) +#define CH32V00X_CLOCK_TIM1 CH32V00X_CLOCK_CONFIG(APB2, 11) +#define CH32V00X_CLOCK_SPI1 CH32V00X_CLOCK_CONFIG(APB2, 12) +#define CH32V00X_CLOCK_USART1 CH32V00X_CLOCK_CONFIG(APB2, 14) + +#define CH32V00X_CLOCK_TIM2 CH32V00X_CLOCK_CONFIG(APB1, 0) +#define CH32V00X_CLOCK_TIM3 CH32V00X_CLOCK_CONFIG(APB1, 1) +#define CH32V00X_CLOCK_WWDG CH32V00X_CLOCK_CONFIG(APB1, 11) +#define CH32V00X_CLOCK_USART2 CH32V00X_CLOCK_CONFIG(APB1, 17) +#define CH32V00X_CLOCK_I2C1 CH32V00X_CLOCK_CONFIG(APB1, 21) +#define CH32V00X_CLOCK_BKP CH32V00X_CLOCK_CONFIG(APB1, 27) +#define CH32V00X_CLOCK_PWR CH32V00X_CLOCK_CONFIG(APB1, 28) +#define CH32V00X_CLOCK_USB CH32V00X_CLOCK_CONFIG(APB1, 23) + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/esp32c2_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/esp32c2_clock.h new file mode 100644 index 00000000..03b66cfe --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/esp32c2_clock.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ + +/* Supported CPU clock Sources */ +#define ESP32_CPU_CLK_SRC_XTAL 0U +#define ESP32_CPU_CLK_SRC_PLL 1U +#define ESP32_CLK_SRC_RC_FAST 2U + +/* Supported CPU frequencies */ +#define ESP32_CLK_CPU_PLL_40M 40000000 +#define ESP32_CLK_CPU_PLL_60M 60000000 +#define ESP32_CLK_CPU_PLL_80M 80000000 +#define ESP32_CLK_CPU_PLL_120M 120000000 +#define ESP32_CLK_CPU_RC_FAST_FREQ 8750000 + +/* Supported XTAL frequencies */ +#define ESP32_CLK_XTAL_26M 26000000 +#define ESP32_CLK_XTAL_32M 32000000 +#define ESP32_CLK_XTAL_40M 40000000 + +/* Supported RTC fast clock sources */ +#define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 0 +#define ESP32_RTC_FAST_CLK_SRC_RC_FAST 1 + +/* Supported RTC slow clock sources */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0 +#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW 1 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256 2 + +/* RTC slow clock frequencies */ +#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000 +#define ESP32_RTC_SLOW_CLK_SRC_OSC_SLOW_FREQ 32768 +#define ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256_FREQ 68359 + +/* Modules IDs + * These IDs are actually offsets in CLK and RST Control registers. + * These IDs shouldn't be changed unless there is a Hardware change + * from Espressif. + * + * Basic Modules + * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG + */ +#define ESP32_LEDC_MODULE 0 +#define ESP32_UART0_MODULE 1 +#define ESP32_UART1_MODULE 2 +#define ESP32_I2C0_MODULE 3 +#define ESP32_TIMG0_MODULE 4 +#define ESP32_TIMG1_MODULE 5 /* No timg1 on esp32c2, TODO: IDF-3825 */ +#define ESP32_UHCI0_MODULE 6 +#define ESP32_SPI_MODULE 7 /* SPI1 */ +#define ESP32_SPI2_MODULE 8 /* SPI2 */ +#define ESP32_RNG_MODULE 9 +#define ESP32_WIFI_MODULE 10 +#define ESP32_BT_MODULE 11 +#define ESP32_WIFI_BT_COMMON_MODULE 12 +#define ESP32_BT_BASEBAND_MODULE 13 +#define ESP32_BT_LC_MODULE 14 +#define ESP32_AES_MODULE 15 +#define ESP32_SHA_MODULE 16 +#define ESP32_ECC_MODULE 17 +#define ESP32_GDMA_MODULE 18 +#define ESP32_SYSTIMER_MODULE 19 +#define ESP32_SARADC_MODULE 20 +#define ESP32_TEMPSENSOR_MODULE 21 +#define ESP32_MODEM_RPA_MODULE 22 +#define ESP32_MODULE_MAX 23 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C2_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx95_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx95_clock.h new file mode 100644 index 00000000..c0b74ab9 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx95_clock.h @@ -0,0 +1,177 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_ + +#define IMX95_CLK_32K 1 +#define IMX95_CLK_24M 2 +#define IMX95_CLK_FRO 3 +#define IMX95_CLK_SYSPLL1_VCO 4 +#define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 +#define IMX95_CLK_SYSPLL1_PFD0 6 +#define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 +#define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 +#define IMX95_CLK_SYSPLL1_PFD1 9 +#define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 +#define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 +#define IMX95_CLK_SYSPLL1_PFD2 12 +#define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 +#define IMX95_CLK_AUDIOPLL1_VCO 14 +#define IMX95_CLK_AUDIOPLL1 15 +#define IMX95_CLK_AUDIOPLL2_VCO 16 +#define IMX95_CLK_AUDIOPLL2 17 +#define IMX95_CLK_VIDEOPLL1_VCO 18 +#define IMX95_CLK_VIDEOPLL1 19 +#define IMX95_CLK_RESERVED20 20 +#define IMX95_CLK_RESERVED21 21 +#define IMX95_CLK_RESERVED22 22 +#define IMX95_CLK_RESERVED23 23 +#define IMX95_CLK_ARMPLL_VCO 24 +#define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 +#define IMX95_CLK_ARMPLL_PFD0 26 +#define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 +#define IMX95_CLK_ARMPLL_PFD1 28 +#define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 +#define IMX95_CLK_ARMPLL_PFD2 30 +#define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 +#define IMX95_CLK_ARMPLL_PFD3 32 +#define IMX95_CLK_DRAMPLL_VCO 33 +#define IMX95_CLK_DRAMPLL 34 +#define IMX95_CLK_HSIOPLL_VCO 35 +#define IMX95_CLK_HSIOPLL 36 +#define IMX95_CLK_LDBPLL_VCO 37 +#define IMX95_CLK_LDBPLL 38 +#define IMX95_CLK_EXT1 39 +#define IMX95_CLK_EXT2 40 + +#define IMX95_CCM_NUM_CLK_SRC 41 + +#define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0) +#define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1) +#define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2) +#define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3) +#define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4) +#define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5) +#define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6) +#define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7) +#define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8) +#define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9) +#define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10) +#define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11) +#define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12) +#define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13) +#define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14) +#define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15) +#define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16) +#define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17) +#define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18) +#define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19) +#define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20) +#define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21) +#define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22) +#define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23) +#define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24) +#define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25) +#define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26) +#define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27) +#define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28) +#define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29) +#define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30) +#define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31) +#define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32) +#define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33) +#define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34) +#define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35) +#define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36) +#define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37) +#define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38) +#define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39) +#define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40) +#define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41) +#define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42) +#define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43) +#define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44) +#define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45) +#define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46) +#define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47) +#define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48) +#define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49) +#define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50) +#define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51) +#define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52) +#define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53) +#define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54) +#define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55) +#define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56) +#define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57) +#define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58) +#define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59) +#define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60) +#define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61) +#define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62) +#define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63) +#define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64) +#define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65) +#define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66) +#define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67) +#define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68) +#define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69) +#define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70) +#define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71) +#define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72) +#define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73) +#define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74) +#define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75) +#define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76) +#define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77) +#define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78) +#define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79) +#define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80) +#define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81) +#define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82) +#define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83) +#define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84) +#define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85) +#define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86) +#define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87) +#define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88) +#define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89) +#define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90) +#define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91) +#define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92) +#define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93) +#define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94) +#define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95) +#define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96) +#define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97) +#define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98) +#define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99) +#define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100) +#define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101) +#define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102) +#define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103) +#define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104) +#define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105) +#define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106) +#define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107) +#define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108) +#define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109) +#define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110) +#define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111) +#define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112) +#define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113) +#define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114) +#define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115) +#define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116) +#define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117) +#define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118) +#define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119) +#define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120) +#define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121) +#define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX95_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h index 18c44cab..f7d6b7af 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h @@ -23,11 +23,17 @@ /* LPUART */ #define IMX_CCM_LPUART_CLK 0x300UL #define IMX_CCM_LPUART1_CLK 0x300UL +#define IMX_CCM_LPUART0102_CLK 0x300UL #define IMX_CCM_LPUART2_CLK 0x301UL +#define IMX_CCM_LPUART0304_CLK 0x301UL #define IMX_CCM_LPUART3_CLK 0x302UL +#define IMX_CCM_LPUART0506_CLK 0x302UL #define IMX_CCM_LPUART4_CLK 0x303UL +#define IMX_CCM_LPUART0708_CLK 0x303UL #define IMX_CCM_LPUART5_CLK 0x304UL +#define IMX_CCM_LPUART0910_CLK 0x304UL #define IMX_CCM_LPUART6_CLK 0x305UL +#define IMX_CCM_LPUART1112_CLK 0x305UL #define IMX_CCM_LPUART7_CLK 0x306UL #define IMX_CCM_LPUART8_CLK 0x307UL #define IMX_CCM_LPUART9_CLK 0x308UL @@ -37,12 +43,16 @@ /* LPI2C */ #define IMX_CCM_LPI2C_CLK 0x400UL +#define IMX_CCM_LPI2C0102_CLK 0x400UL #define IMX_CCM_LPI2C1_CLK 0x400UL #define IMX_CCM_LPI2C2_CLK 0x401UL +#define IMX_CCM_LPI2C0304_CLK 0x401UL #define IMX_CCM_LPI2C3_CLK 0x402UL #define IMX_CCM_LPI2C4_CLK 0x403UL +#define IMX_CCM_LPI2C0506_CLK 0x402UL #define IMX_CCM_LPI2C5_CLK 0x404UL #define IMX_CCM_LPI2C6_CLK 0x405UL +#define IMX_CCM_LPI2C0708_CLK 0x403UL #define IMX_CCM_LPI2C7_CLK 0x406UL #define IMX_CCM_LPI2C8_CLK 0x407UL @@ -116,6 +126,19 @@ #define IMX_CCM_TPM5_CLK 0x1604UL #define IMX_CCM_TPM6_CLK 0x1605UL +/* FLEXIO */ +#define IMX_CCM_FLEXIO_CLK 0x1700UL +#define IMX_CCM_FLEXIO1_CLK 0x1700UL +#define IMX_CCM_FLEXIO2_CLK 0x1701UL + +/* NETC */ +#define IMX_CCM_NETC_CLK 0x1800UL + +/* MIPI CSI2RX */ +#define IMX_CCM_MIPI_CSI2RX_ROOT_CLK 0x1900UL +#define IMX_CCM_MIPI_CSI2RX_UI_CLK 0x2000UL +#define IMX_CCM_MIPI_CSI2RX_ESC_CLK 0x2100UL + /* QTMR */ #define IMX_CCM_QTMR_CLK 0x6000UL #define IMX_CCM_QTMR1_CLK 0x6000UL diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/kinetis_sim.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/kinetis_sim.h index 75e81791..9a199663 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/kinetis_sim.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/kinetis_sim.h @@ -15,6 +15,9 @@ #define KINETIS_SIM_DMAMUX_CLK KINETIS_SIM_BUS_CLK #define KINETIS_SIM_DMA_CLK KINETIS_SIM_CORESYS_CLK #define KINETIS_SIM_SIM_SOPT7 7 +#define KINETIS_SIM_OSCERCLK 8 +#define KINETIS_SIM_MCGIRCLK 12 +#define KINETIS_SIM_MCGPCLK 18 #define KINETIS_SIM_PLLFLLSEL_MCGFLLCLK 0 #define KINETIS_SIM_PLLFLLSEL_MCGPLLCLK 1 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index 68fcb1df..c2673517 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -16,77 +16,86 @@ /* These IDs are used within SOC macros, and thus cannot be defined * using the standard MCUX_LPC_CLK_ID form */ -#define MCUX_CTIMER0_CLK 0 -#define MCUX_CTIMER1_CLK 1 -#define MCUX_CTIMER2_CLK 2 -#define MCUX_CTIMER3_CLK 3 -#define MCUX_CTIMER4_CLK 4 +#define MCUX_CTIMER0_CLK 0 +#define MCUX_CTIMER1_CLK 1 +#define MCUX_CTIMER2_CLK 2 +#define MCUX_CTIMER3_CLK 3 +#define MCUX_CTIMER4_CLK 4 -#define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00) -#define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01) -#define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02) -#define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03) -#define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04) -#define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05) -#define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06) -#define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07) -#define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08) -#define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09) -#define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A) -#define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B) -#define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C) -#define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D) -#define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E) -#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK -#define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) -#define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) +#define MCUX_FLEXCOMM0_CLK MCUX_LPC_CLK_ID(0x01, 0x00) +#define MCUX_FLEXCOMM1_CLK MCUX_LPC_CLK_ID(0x01, 0x01) +#define MCUX_FLEXCOMM2_CLK MCUX_LPC_CLK_ID(0x01, 0x02) +#define MCUX_FLEXCOMM3_CLK MCUX_LPC_CLK_ID(0x01, 0x03) +#define MCUX_FLEXCOMM4_CLK MCUX_LPC_CLK_ID(0x01, 0x04) +#define MCUX_FLEXCOMM5_CLK MCUX_LPC_CLK_ID(0x01, 0x05) +#define MCUX_FLEXCOMM6_CLK MCUX_LPC_CLK_ID(0x01, 0x06) +#define MCUX_FLEXCOMM7_CLK MCUX_LPC_CLK_ID(0x01, 0x07) +#define MCUX_FLEXCOMM8_CLK MCUX_LPC_CLK_ID(0x01, 0x08) +#define MCUX_FLEXCOMM9_CLK MCUX_LPC_CLK_ID(0x01, 0x09) +#define MCUX_FLEXCOMM10_CLK MCUX_LPC_CLK_ID(0x01, 0x0A) +#define MCUX_FLEXCOMM11_CLK MCUX_LPC_CLK_ID(0x01, 0x0B) +#define MCUX_FLEXCOMM12_CLK MCUX_LPC_CLK_ID(0x01, 0x0C) +#define MCUX_FLEXCOMM13_CLK MCUX_LPC_CLK_ID(0x01, 0x0D) +#define MCUX_HS_SPI_CLK MCUX_LPC_CLK_ID(0x01, 0x0E) +#define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK +#define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) +#define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) -#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) -#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) +#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) +#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) -#define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) +#define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) -#define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00) +#define MCUX_BUS_CLK MCUX_LPC_CLK_ID(0x04, 0x00) -#define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00) +#define MCUX_SDIF_CLK MCUX_LPC_CLK_ID(0x05, 0x00) -#define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00) +#define MCUX_I3C_CLK MCUX_LPC_CLK_ID(0x06, 0x00) +#define MCUX_I3C2_CLK MCUX_LPC_CLK_ID(0x06, 0x01) -#define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00) -#define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01) +#define MCUX_MIPI_DSI_DPHY_CLK MCUX_LPC_CLK_ID(0x07, 0x00) +#define MCUX_MIPI_DSI_ESC_CLK MCUX_LPC_CLK_ID(0x07, 0x01) -#define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00) +#define MCUX_LCDIF_PIXEL_CLK MCUX_LPC_CLK_ID(0x08, 0x00) -#define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00) +#define MCUX_SCTIMER_CLK MCUX_LPC_CLK_ID(0x09, 0x00) -#define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) +#define MCUX_DMIC_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) -#define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) -#define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01) +#define MCUX_FLEXSPI_CLK MCUX_LPC_CLK_ID(0x0A, 0x00) +#define MCUX_FLEXSPI2_CLK MCUX_LPC_CLK_ID(0x0A, 0x01) -#define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00) -#define MCUX_FREEMRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x01) +#define MCUX_MRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x00) +#define MCUX_FREEMRT_CLK MCUX_LPC_CLK_ID(0x0B, 0x01) -#define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00) -#define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01) -#define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02) -#define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03) -#define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04) -#define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05) +#define MCUX_PORT0_CLK MCUX_LPC_CLK_ID(0x0C, 0x00) +#define MCUX_PORT1_CLK MCUX_LPC_CLK_ID(0x0C, 0x01) +#define MCUX_PORT2_CLK MCUX_LPC_CLK_ID(0x0C, 0x02) +#define MCUX_PORT3_CLK MCUX_LPC_CLK_ID(0x0C, 0x03) +#define MCUX_PORT4_CLK MCUX_LPC_CLK_ID(0x0C, 0x04) +#define MCUX_PORT5_CLK MCUX_LPC_CLK_ID(0x0C, 0x05) -#define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00) +#define MCUX_ENET_QOS_CLK MCUX_LPC_CLK_ID(0x0D, 0x00) -#define MCUX_ENET_CLK MCUX_LPC_CLK_ID(0x0D, 0x80) -#define MCUX_ENET_PLL MCUX_LPC_CLK_ID(0x0D, 0x81) +#define MCUX_ENET_CLK MCUX_LPC_CLK_ID(0x0D, 0x80) +#define MCUX_ENET_PLL MCUX_LPC_CLK_ID(0x0D, 0x81) -#define MCUX_LCDIC_CLK MCUX_LPC_CLK_ID(0x0E, 0x00) +#define MCUX_LCDIC_CLK MCUX_LPC_CLK_ID(0x0E, 0x00) -#define MCUX_LPADC1_CLK MCUX_LPC_CLK_ID(0x0F, 0x00) -#define MCUX_LPADC2_CLK MCUX_LPC_CLK_ID(0x0F, 0x01) +#define MCUX_LPADC1_CLK MCUX_LPC_CLK_ID(0x0F, 0x00) +#define MCUX_LPADC2_CLK MCUX_LPC_CLK_ID(0x0F, 0x01) -#define MCUX_FLEXCAN0_CLK MCUX_LPC_CLK_ID(0x10, 0x00) -#define MCUX_FLEXCAN1_CLK MCUX_LPC_CLK_ID(0x10, 0x01) +#define MCUX_FLEXCAN0_CLK MCUX_LPC_CLK_ID(0x10, 0x00) +#define MCUX_FLEXCAN1_CLK MCUX_LPC_CLK_ID(0x10, 0x01) -#define MCUX_FLEXIO0_CLK MCUX_LPC_CLK_ID(0x11, 0x00) +#define MCUX_FLEXIO0_CLK MCUX_LPC_CLK_ID(0x11, 0x00) + +#define MCUX_AUDIO_MCLK MCUX_LPC_CLK_ID(0x12, 0x00) + +#define MCUX_LPUART0_CLK MCUX_LPC_CLK_ID(0x13, 0x00) +#define MCUX_LPUART1_CLK MCUX_LPC_CLK_ID(0x13, 0x01) +#define MCUX_LPUART2_CLK MCUX_LPC_CLK_ID(0x13, 0x02) +#define MCUX_LPUART3_CLK MCUX_LPC_CLK_ID(0x13, 0x03) +#define MCUX_LPUART4_CLK MCUX_LPC_CLK_ID(0x13, 0x04) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/npcm_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/npcm_clock.h new file mode 100644 index 00000000..d4a1b0c3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/npcm_clock.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ + +/* clock bus references */ +#define NPCM_CLOCK_GROUP_OFFSET(N) ((N) << 3) + +#define NPCM_CLOCK_PWM_I (NPCM_CLOCK_GROUP_OFFSET(0) + 0) +#define NPCM_CLOCK_PWM_J (NPCM_CLOCK_GROUP_OFFSET(0) + 1) +#define NPCM_CLOCK_I3CI (NPCM_CLOCK_GROUP_OFFSET(0) + 2) +#define NPCM_CLOCK_UART3 (NPCM_CLOCK_GROUP_OFFSET(0) + 5) +#define NPCM_CLOCK_UART2 (NPCM_CLOCK_GROUP_OFFSET(0) + 6) +#define NPCM_CLOCK_SPIM (NPCM_CLOCK_GROUP_OFFSET(1) + 0) +#define NPCM_CLOCK_FIU (NPCM_CLOCK_GROUP_OFFSET(1) + 2) +#define NPCM_CLOCK_USB20 (NPCM_CLOCK_GROUP_OFFSET(1) + 3) +#define NPCM_CLOCK_UART (NPCM_CLOCK_GROUP_OFFSET(1) + 4) +#define NPCM_CLOCK_MFT1 (NPCM_CLOCK_GROUP_OFFSET(1) + 5) +#define NPCM_CLOCK_MFT2 (NPCM_CLOCK_GROUP_OFFSET(1) + 6) +#define NPCM_CLOCK_MFT3 (NPCM_CLOCK_GROUP_OFFSET(1) + 7) +#define NPCM_CLOCK_PWM_A (NPCM_CLOCK_GROUP_OFFSET(2) + 0) +#define NPCM_CLOCK_PWM_B (NPCM_CLOCK_GROUP_OFFSET(2) + 1) +#define NPCM_CLOCK_PWM_C (NPCM_CLOCK_GROUP_OFFSET(2) + 2) +#define NPCM_CLOCK_PWM_D (NPCM_CLOCK_GROUP_OFFSET(2) + 3) +#define NPCM_CLOCK_PWM_E (NPCM_CLOCK_GROUP_OFFSET(2) + 4) +#define NPCM_CLOCK_PWM_F (NPCM_CLOCK_GROUP_OFFSET(2) + 5) +#define NPCM_CLOCK_PWM_G (NPCM_CLOCK_GROUP_OFFSET(2) + 6) +#define NPCM_CLOCK_PWM_H (NPCM_CLOCK_GROUP_OFFSET(2) + 7) +#define NPCM_CLOCK_SMB1 (NPCM_CLOCK_GROUP_OFFSET(3) + 0) +#define NPCM_CLOCK_SMB2 (NPCM_CLOCK_GROUP_OFFSET(3) + 1) +#define NPCM_CLOCK_SMB3 (NPCM_CLOCK_GROUP_OFFSET(3) + 2) +#define NPCM_CLOCK_SMB4 (NPCM_CLOCK_GROUP_OFFSET(3) + 3) +#define NPCM_CLOCK_SMB5 (NPCM_CLOCK_GROUP_OFFSET(3) + 4) +#define NPCM_CLOCK_SMB6 (NPCM_CLOCK_GROUP_OFFSET(3) + 5) +#define NPCM_CLOCK_GDMA (NPCM_CLOCK_GROUP_OFFSET(3) + 7) +#define NPCM_CLOCK_ITIM1 (NPCM_CLOCK_GROUP_OFFSET(4) + 0) +#define NPCM_CLOCK_ITIM2 (NPCM_CLOCK_GROUP_OFFSET(4) + 1) +#define NPCM_CLOCK_ITIM3 (NPCM_CLOCK_GROUP_OFFSET(4) + 2) +#define NPCM_CLOCK_SMB_DMA (NPCM_CLOCK_GROUP_OFFSET(4) + 3) +#define NPCM_CLOCK_ADC (NPCM_CLOCK_GROUP_OFFSET(4) + 4) +#define NPCM_CLOCK_PECI (NPCM_CLOCK_GROUP_OFFSET(4) + 5) +#define NPCM_CLOCK_SPIP1 (NPCM_CLOCK_GROUP_OFFSET(4) + 7) +#define NPCM_CLOCK_UART4 (NPCM_CLOCK_GROUP_OFFSET(5) + 0) +#define NPCM_CLOCK_C2HACC (NPCM_CLOCK_GROUP_OFFSET(5) + 3) +#define NPCM_CLOCK_SHM_REG (NPCM_CLOCK_GROUP_OFFSET(5) + 4) +#define NPCM_CLOCK_SHM (NPCM_CLOCK_GROUP_OFFSET(5) + 5) +#define NPCM_CLOCK_DP80 (NPCM_CLOCK_GROUP_OFFSET(5) + 6) +#define NPCM_CLOCK_MSWC (NPCM_CLOCK_GROUP_OFFSET(5) + 7) +#define NPCM_CLOCK_ITIM4 (NPCM_CLOCK_GROUP_OFFSET(6) + 0) +#define NPCM_CLOCK_ITIM5 (NPCM_CLOCK_GROUP_OFFSET(6) + 1) +#define NPCM_CLOCK_ITIM6 (NPCM_CLOCK_GROUP_OFFSET(6) + 2) +#define NPCM_CLOCK_RNG (NPCM_CLOCK_GROUP_OFFSET(6) + 3) +#define NPCM_CLOCK_SHA (NPCM_CLOCK_GROUP_OFFSET(6) + 5) +#define NPCM_CLOCK_ESPI (NPCM_CLOCK_GROUP_OFFSET(6) + 7) +#define NPCM_CLOCK_SMB7 (NPCM_CLOCK_GROUP_OFFSET(7) + 0) +#define NPCM_CLOCK_SMB8 (NPCM_CLOCK_GROUP_OFFSET(7) + 1) +#define NPCM_CLOCK_SMB9 (NPCM_CLOCK_GROUP_OFFSET(7) + 2) +#define NPCM_CLOCK_SMB10 (NPCM_CLOCK_GROUP_OFFSET(7) + 3) +#define NPCM_CLOCK_SMB11 (NPCM_CLOCK_GROUP_OFFSET(7) + 4) +#define NPCM_CLOCK_SMB12 (NPCM_CLOCK_GROUP_OFFSET(7) + 5) +#define NPCM_CLOCK_SIOX2 (NPCM_CLOCK_GROUP_OFFSET(7) + 6) +#define NPCM_CLOCK_SIOX1 (NPCM_CLOCK_GROUP_OFFSET(7) + 7) +#define NPCM_CLOCK_I3CI2 (NPCM_CLOCK_GROUP_OFFSET(8) + 0) +#define NPCM_CLOCK_I3CI3 (NPCM_CLOCK_GROUP_OFFSET(8) + 1) +#define NPCM_CLOCK_I3CI4 (NPCM_CLOCK_GROUP_OFFSET(8) + 2) +#define NPCM_CLOCK_I3CI5 (NPCM_CLOCK_GROUP_OFFSET(8) + 3) +#define NPCM_CLOCK_I3CI6 (NPCM_CLOCK_GROUP_OFFSET(8) + 4) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCM_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h index fab7f656..85f411cf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m2l31x_clock.h @@ -271,4 +271,17 @@ #define NUMAKER_LPADC0_MODULE 0xB5431218 #define NUMAKER_OPA_MODULE 0xA000001B +#define NUMAKER_CLK_PMUCTL_PDMSEL_PD 0x00000000 +#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD0 0x00000000 +#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD1 0x00000001 +#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD2 0x00000002 +#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD3 0x00000003 +#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD4 0x00000004 +#define NUMAKER_CLK_PMUCTL_PDMSEL_NPD5 0x00000005 +#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD0 0x00000008 +#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD1 0x00000009 +#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD2 0x0000000A +#define NUMAKER_CLK_PMUCTL_PDMSEL_DPD0 0x0000000C +#define NUMAKER_CLK_PMUCTL_PDMSEL_DPD1 0x0000000D + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m46x_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m46x_clock.h index 9243ab76..82deb4dc 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m46x_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/numaker_m46x_clock.h @@ -1300,4 +1300,10 @@ /* End of M460 BSP clk.h copy */ +#define NUMAKER_CLK_PMUCTL_PDMSEL_PD 0x00000000 +#define NUMAKER_CLK_PMUCTL_PDMSEL_LLPD 0x00000001 +#define NUMAKER_CLK_PMUCTL_PDMSEL_FWPD 0x00000002 +#define NUMAKER_CLK_PMUCTL_PDMSEL_SPD 0x00000004 +#define NUMAKER_CLK_PMUCTL_PDMSEL_DPD 0x00000006 + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h index 6471a2c5..b19e44ef 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/nxp_s32z2_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 NXP + * Copyright 2023-2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -292,9 +292,5 @@ #define NXP_S32_SPI9_CLK 284U #define NXP_S32_SRX0_CLK 285U #define NXP_S32_SRX1_CLK 286U -#define NXP_S32_CORE_PLL_REFCLKOUT 287U -#define NXP_S32_CORE_PLL_FBCLKOUT 288U -#define NXP_S32_PERIPH_PLL_REFCLKOUT 289U -#define NXP_S32_PERIPH_PLL_FBCLKOUT 290U #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NXP_S32Z2_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ra_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ra_clock.h index 09035308..97fc2e41 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ra_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/ra_clock.h @@ -7,129 +7,10 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ -#define RA_PLL_SOURCE_HOCO 0 -#define RA_PLL_SOURCE_MOCO 1 -#define RA_PLL_SOURCE_LOCO 2 -#define RA_PLL_SOURCE_MAIN_OSC 3 -#define RA_PLL_SOURCE_SUBCLOCK 4 -#define RA_PLL_SOURCE_DISABLE 0xff - -#define RA_CLOCK_SOURCE_HOCO 0 -#define RA_CLOCK_SOURCE_MOCO 1 -#define RA_CLOCK_SOURCE_LOCO 2 -#define RA_CLOCK_SOURCE_MAIN_OSC 3 -#define RA_CLOCK_SOURCE_SUBCLOCK 4 -#define RA_CLOCK_SOURCE_PLL 5 -#define RA_CLOCK_SOURCE_PLL1P RA_CLOCK_SOURCE_PLL -#define RA_CLOCK_SOURCE_PLL2 6 -#define RA_CLOCK_SOURCE_PLL2P RA_CLOCK_SOURCE_PLL2 -#define RA_CLOCK_SOURCE_PLL1Q 7 -#define RA_CLOCK_SOURCE_PLL1R 8 -#define RA_CLOCK_SOURCE_PLL2Q 9 -#define RA_CLOCK_SOURCE_PLL2R 10 -#define RA_CLOCK_SOURCE_DISABLE 0xff - -#define RA_SYS_CLOCK_DIV_1 0 -#define RA_SYS_CLOCK_DIV_2 1 -#define RA_SYS_CLOCK_DIV_4 2 -#define RA_SYS_CLOCK_DIV_8 3 -#define RA_SYS_CLOCK_DIV_16 4 -#define RA_SYS_CLOCK_DIV_32 5 -#define RA_SYS_CLOCK_DIV_64 6 -#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */ -#define RA_SYS_CLOCK_DIV_3 8 -#define RA_SYS_CLOCK_DIV_6 9 -#define RA_SYS_CLOCK_DIV_12 10 - -/* PLL divider options. */ -#define RA_PLL_DIV_1 0 -#define RA_PLL_DIV_2 1 -#define RA_PLL_DIV_3 2 -#define RA_PLL_DIV_4 3 -#define RA_PLL_DIV_5 4 -#define RA_PLL_DIV_6 5 -#define RA_PLL_DIV_8 7 -#define RA_PLL_DIV_9 8 -#define RA_PLL_DIV_16 15 - -/* USB clock divider options. */ -#define RA_USB_CLOCK_DIV_1 0 -#define RA_USB_CLOCK_DIV_2 1 -#define RA_USB_CLOCK_DIV_3 2 -#define RA_USB_CLOCK_DIV_4 3 -#define RA_USB_CLOCK_DIV_5 4 -#define RA_USB_CLOCK_DIV_6 5 -#define RA_USB_CLOCK_DIV_8 7 - -/* USB60 clock divider options. */ -#define RA_USB60_CLOCK_DIV_1 0 -#define RA_USB60_CLOCK_DIV_2 1 -#define RA_USB60_CLOCK_DIV_3 5 -#define RA_USB60_CLOCK_DIV_4 2 -#define RA_USB60_CLOCK_DIV_5 6 -#define RA_USB60_CLOCK_DIV_6 3 -#define RA_USB60_CLOCK_DIV_8 4 - -/* OCTA clock divider options. */ -#define RA_OCTA_CLOCK_DIV_1 0 -#define RA_OCTA_CLOCK_DIV_2 1 -#define RA_OCTA_CLOCK_DIV_4 2 -#define RA_OCTA_CLOCK_DIV_6 3 -#define RA_OCTA_CLOCK_DIV_8 4 - -/* CANFD clock divider options. */ -#define RA_CANFD_CLOCK_DIV_1 0 -#define RA_CANFD_CLOCK_DIV_2 1 -#define RA_CANFD_CLOCK_DIV_3 5 -#define RA_CANFD_CLOCK_DIV_4 2 -#define RA_CANFD_CLOCK_DIV_5 6 -#define RA_CANFD_CLOCK_DIV_6 3 -#define RA_CANFD_CLOCK_DIV_8 4 - -/* SCI clock divider options. */ -#define RA_SCI_CLOCK_DIV_1 0 -#define RA_SCI_CLOCK_DIV_2 1 -#define RA_SCI_CLOCK_DIV_3 5 -#define RA_SCI_CLOCK_DIV_4 2 -#define RA_SCI_CLOCK_DIV_5 6 -#define RA_SCI_CLOCK_DIV_6 3 -#define RA_SCI_CLOCK_DIV_8 4 - -/* SPI clock divider options. */ -#define RA_SPI_CLOCK_DIV_1 0 -#define RA_SPI_CLOCK_DIV_2 1 -#define RA_SPI_CLOCK_DIV_3 5 -#define RA_SPI_CLOCK_DIV_4 2 -#define RA_SPI_CLOCK_DIV_5 6 -#define RA_SPI_CLOCK_DIV_6 3 -#define RA_SPI_CLOCK_DIV_8 4 - -/* CEC clock divider options. */ -#define RA_CEC_CLOCK_DIV_1 0 -#define RA_CEC_CLOCK_DIV_2 1 - -/* I3C clock divider options. */ -#define RA_I3C_CLOCK_DIV_1 0 -#define RA_I3C_CLOCK_DIV_2 1 -#define RA_I3C_CLOCK_DIV_3 5 -#define RA_I3C_CLOCK_DIV_4 2 -#define RA_I3C_CLOCK_DIV_5 6 -#define RA_I3C_CLOCK_DIV_6 3 -#define RA_I3C_CLOCK_DIV_8 4 - -/* LCD clock divider options. */ -#define RA_LCD_CLOCK_DIV_1 0 -#define RA_LCD_CLOCK_DIV_2 1 -#define RA_LCD_CLOCK_DIV_3 5 -#define RA_LCD_CLOCK_DIV_4 2 -#define RA_LCD_CLOCK_DIV_5 6 -#define RA_LCD_CLOCK_DIV_6 3 -#define RA_LCD_CLOCK_DIV_8 4 - -#define MSTPA 0x40203000 -#define MSTPB 0x40203004 -#define MSTPC 0x40203008 -#define MSTPD 0x4020300C -#define MSTPE 0x40203010 +#define MSTPA 0 +#define MSTPB 1 +#define MSTPC 2 +#define MSTPD 3 +#define MSTPE 4 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/scg_k4.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/scg_k4.h new file mode 100644 index 00000000..985629a1 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/scg_k4.h @@ -0,0 +1,14 @@ +/* + * Copyright 2023 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#define SCG_K4_CORESYS_CLK 0U +#define SCG_K4_SLOW_CLK 1U +#define SCG_K4_PLAT_CLK 2U +#define SCG_K4_SYS_CLK 3U +#define SCG_K4_BUS_CLK 4U +#define SCG_K4_SYSOSC_CLK 5U +#define SCG_K4_SIRC_CLK 6U +#define SCG_K4_FIRC_CLK 7U +#define SCG_K4_RTCOSC_CLK 8U diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/common-clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/common-clock.h new file mode 100644 index 00000000..1b5aa5d7 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/common-clock.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ + +/* + * DT macros for clock branches. + * Must stay in sync with the enum sl_clock_branch_t in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_BRANCH_SYSCLK 0 +#define CLOCK_BRANCH_HCLK 1 +#define CLOCK_BRANCH_HCLKRADIO 2 +#define CLOCK_BRANCH_PCLK 3 +#define CLOCK_BRANCH_LSPCLK 4 +#define CLOCK_BRANCH_TRACECLK 5 +#define CLOCK_BRANCH_ADCCLK 6 +#define CLOCK_BRANCH_EXPORTCLK 7 +#define CLOCK_BRANCH_EM01GRPACLK 8 +#define CLOCK_BRANCH_EM01GRPBCLK 9 +#define CLOCK_BRANCH_EM01GRPCCLK 10 +#define CLOCK_BRANCH_EM01GRPDCLK 11 +#define CLOCK_BRANCH_EM23GRPACLK 12 +#define CLOCK_BRANCH_EM4GRPACLK 13 +#define CLOCK_BRANCH_QSPISYSCLK 14 +#define CLOCK_BRANCH_IADCCLK 15 +#define CLOCK_BRANCH_WDOG0CLK 16 +#define CLOCK_BRANCH_WDOG1CLK 17 +#define CLOCK_BRANCH_RTCCCLK 18 +#define CLOCK_BRANCH_SYSRTCCLK 19 +#define CLOCK_BRANCH_EUART0CLK 20 +#define CLOCK_BRANCH_EUSART0CLK 21 +#define CLOCK_BRANCH_DPLLREFCLK 22 +#define CLOCK_BRANCH_I2C0CLK 23 +#define CLOCK_BRANCH_LCDCLK 24 +#define CLOCK_BRANCH_PIXELRZCLK 25 +#define CLOCK_BRANCH_PCNT0CLK 26 +#define CLOCK_BRANCH_PRORTCCLK 27 +#define CLOCK_BRANCH_SYSTICKCLK 28 +#define CLOCK_BRANCH_LESENSEHFCLK 29 +#define CLOCK_BRANCH_VDAC0CLK 30 +#define CLOCK_BRANCH_VDAC1CLK 31 +#define CLOCK_BRANCH_USB0CLK 32 +#define CLOCK_BRANCH_FLPLLREFCLK 33 +#define CLOCK_BRANCH_INVALID 34 + +#define CLOCK_BIT_MASK 0x03FUL +#define CLOCK_REG_MASK 0x1C0UL + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg21-clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg21-clock.h new file mode 100644 index 00000000..dcfcb4ae --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg21-clock.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_AUTO 0xFFFFFFFFUL + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg22-clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg22-clock.h new file mode 100644 index 00000000..ef9c8623 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg22-clock.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_EUART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg23-clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg23-clock.h new file mode 100644 index 00000000..29914ecd --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg23-clock.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_EUSART2 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_LCD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LESENSE (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg24-clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg24-clock.h new file mode 100644 index 00000000..7fca2a5b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg24-clock.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_MVP (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_VDAC1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg27-clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg27-clock.h new file mode 100644 index 00000000..c21a9e5c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/silabs/xg27-clock.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ETAMPDET (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_clock.h index a669f49b..37241a26 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_clock.h @@ -23,4 +23,9 @@ #define STM32_CLOCK_BUS_AXI 13 #define STM32_CLOCK_BUS_MLAHB 14 +#define STM32_CLOCK_DIV_SHIFT 12 + +/** Clock divider */ +#define STM32_CLOCK_DIV(div) (((div) - 1) << STM32_CLOCK_DIV_SHIFT) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_common_clocks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_common_clocks.h index 030ec2d9..5c101547 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_common_clocks.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32_common_clocks.h @@ -15,4 +15,48 @@ /** Dummy: Add a specifier when no selection is possible */ #define NO_SEL 0xFF +#define STM32_CLOCK_DIV_SHIFT 12 + +/** Clock divider */ +#define STM32_CLOCK_DIV(div) (((div) - 1) << STM32_CLOCK_DIV_SHIFT) + +/** STM32 MCO configuration values */ +#define STM32_MCO_CFGR_REG_MASK 0xFFFFU +#define STM32_MCO_CFGR_REG_SHIFT 0U +#define STM32_MCO_CFGR_SHIFT_MASK 0x3FU +#define STM32_MCO_CFGR_SHIFT_SHIFT 16U +#define STM32_MCO_CFGR_MASK_MASK 0x1FU +#define STM32_MCO_CFGR_MASK_SHIFT 22U +#define STM32_MCO_CFGR_VAL_MASK 0x1FU +#define STM32_MCO_CFGR_VAL_SHIFT 27U + +/** + * @brief STM32 MCO configuration register bit field + * + * @param reg Offset to RCC register holding MCO configuration + * @param shift Position of field within RCC register (= field LSB's index) + * @param mask Mask of register field in RCC register + * @param val Clock configuration field value (0~0x1F) + * + * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ] + * @note 'shift' range: 0~63 [ 16 : 21 ] + * @note 'mask' range: 0x00~0x1F [ 22 : 26 ] + * @note 'val' range: 0x00~0x1F [ 27 : 31 ] + * + */ +#define STM32_MCO_CFGR(val, mask, shift, reg) \ + ((((reg) & STM32_MCO_CFGR_REG_MASK) << STM32_MCO_CFGR_REG_SHIFT) | \ + (((shift) & STM32_MCO_CFGR_SHIFT_MASK) << STM32_MCO_CFGR_SHIFT_SHIFT) | \ + (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) | \ + (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT)) + +/** + * Pack RCC clock register offset and bit in two 32-bit values + * as expected for the Device Tree `clocks` property on STM32. + * + * @param bus STM32 bus name (expands to STM32_CLOCK_BUS_{bus}) + * @param bit Clock bit + */ +#define STM32_CLOCK(bus, bit) (STM32_CLOCK_BUS_##bus) (1 << bit) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32c0_clock.h index 224bd151..9564f411 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32c0_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32c0_clock.h @@ -51,7 +51,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -63,13 +63,32 @@ /** @brief RCC_CSR1 register offset */ #define CSR1_REG 0x5C +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x08 + /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) /** CSR1 devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, CSR1_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG) + +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 0 +#define MCO_PRE_DIV_2 1 +#define MCO_PRE_DIV_4 2 +#define MCO_PRE_DIV_8 3 +#define MCO_PRE_DIV_16 4 +#define MCO_PRE_DIV_32 5 +#define MCO_PRE_DIV_64 6 +#define MCO_PRE_DIV_128 7 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f0_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f0_clock.h index 11645735..7572c1c4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f0_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f0_clock.h @@ -52,13 +52,14 @@ * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x04 #define CFGR3_REG 0x30 /** @brief RCC_BDCR register offset */ @@ -66,13 +67,17 @@ /** @brief Device domain clocks selection helpers */ /** CFGR3 devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) -#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG) -#define USB_SEL(val) STM32_CLOCK(val, 1, 7, CFGR3_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) +#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) +#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f10x_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f10x_clock.h new file mode 100644 index 00000000..05f2b598 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f10x_clock.h @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2024, Joakim Andersson + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ + +#include "stm32_common_clocks.h" +/* Ensure correct order by including generic F1 definitions first. */ +#include "stm32f1_clock.h" + +/** Fixed clocks */ +/* Low speed clocks defined in stm32_common_clocks.h */ +/* Common clocks with stm32f1x defined in stm32f1_clock.h */ +#define STM32_SRC_PLL2CLK (STM32_SRC_PLLCLK + 1) +#define STM32_SRC_PLL3CLK (STM32_SRC_PLL2CLK + 1) + +/** CFGR1 devices */ +#undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity line devices. */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) +/* No MCO prescaler support on STM32F1 series. */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f1_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f1_clock.h index 571014dd..f6777932 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f1_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f1_clock.h @@ -23,9 +23,10 @@ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ -#define STM32_SRC_HSI (STM32_SRC_LSI + 1) -#define STM32_SRC_HSE (STM32_SRC_HSI + 1) - +#define STM32_SRC_HSI (STM32_SRC_LSI + 1) +#define STM32_SRC_HSE (STM32_SRC_HSI + 1) +#define STM32_SRC_EXT_HSE (STM32_SRC_HSE + 1) +#define STM32_SRC_PLLCLK (STM32_SRC_EXT_HSE + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U @@ -49,13 +50,14 @@ * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) -/** @brief RCC_CFGR2 register offset */ +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x04 #define CFGR2_REG 0x2C /** @brief RCC_BDCR register offset */ @@ -63,9 +65,13 @@ /** @brief Device domain clocks selection helpers */ /** CFGR2 devices */ -#define I2S2_SEL(val) STM32_CLOCK(val, 1, 17, CFGR2_REG) -#define I2S3_SEL(val) STM32_CLOCK(val, 1, 18, CFGR2_REG) +#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG) +#define I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) +/* No MCO prescaler support on STM32F1 series. */ #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f3_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f3_clock.h index 377eb4fd..c00d1dd5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f3_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f3_clock.h @@ -53,7 +53,7 @@ * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -68,25 +68,27 @@ /** @brief Device domain clocks selection helpers) */ /** CFGR devices */ -#define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) +#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) /** CFGR3 devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 1, 5, CFGR3_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 1, 6, CFGR3_REG) -#define TIM1_SEL(val) STM32_CLOCK(val, 1, 8, CFGR3_REG) -#define TIM8_SEL(val) STM32_CLOCK(val, 1, 9, CFGR3_REG) -#define TIM15_SEL(val) STM32_CLOCK(val, 1, 10, CFGR3_REG) -#define TIM16_SEL(val) STM32_CLOCK(val, 1, 11, CFGR3_REG) -#define TIM17_SEL(val) STM32_CLOCK(val, 1, 13, CFGR3_REG) -#define TIM20_SEL(val) STM32_CLOCK(val, 1, 15, CFGR3_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 16, CFGR3_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 18, CFGR3_REG) -#define USART4_SEL(val) STM32_CLOCK(val, 3, 20, CFGR3_REG) -#define USART5_SEL(val) STM32_CLOCK(val, 3, 22, CFGR3_REG) -#define TIM2_SEL(val) STM32_CLOCK(val, 1, 24, CFGR3_REG) -#define TIM3_4_SEL(val) STM32_CLOCK(val, 1, 25, CFGR3_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG) +#define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG) +#define TIM8_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG) +#define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG) +#define TIM16_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG) +#define TIM17_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG) +#define TIM20_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG) +#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG) +#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG) +#define TIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG) +#define TIM3_4_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f410_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f410_clock.h index 073d7c3b..fffd4732 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f410_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f410_clock.h @@ -12,19 +12,19 @@ /** @brief Device domain clocks selection helpers */ /** DCKCFGR devices */ -#define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) -#define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) -#define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) -#define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) -#define I2S1_SEL(val) STM32_CLOCK(val, 3, 25, DCKCFGR_REG) -#define I2S2_SEL(val) STM32_CLOCK(val, 3, 27, DCKCFGR_REG) -#define CKDFSDM_SEL(val) STM32_CLOCK(val, 1, 31, DCKCFGR_REG) +#define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG) +#define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG) +#define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG) +#define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG) +#define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG) +#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG) +#define CKDFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG) /** DCKCFGR2 devices */ -#define I2CFMP1_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) -#define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG) -#define SDIO_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 30, DCKCFGR2_REG) +#define I2CFMP1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG) +#define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) +#define SDIO_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG) /* F4 generic I2S_SEL is not compatible with F410 devices */ #ifdef I2S_SEL diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f427_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f427_clock.h index 46370be5..97d22836 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f427_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f427_clock.h @@ -11,12 +11,12 @@ /** @brief Device domain clocks selection helpers */ /** DCKCFGR devices */ -#define CKDFSDM2A_SEL(val) STM32_CLOCK(val, 1, 14, DCKCFGR_REG) -#define CKDFSDM1A_SEL(val) STM32_CLOCK(val, 1, 15, DCKCFGR_REG) -#define SAI1A_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR_REG) -#define SAI1B_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR_REG) -#define CLK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR_REG) -#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR_REG) -#define DSI_SEL(val) STM32_CLOCK(val, 1, 29, DCKCFGR_REG) +#define CKDFSDM2A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG) +#define CKDFSDM1A_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG) +#define SAI1A_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG) +#define SAI1B_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG) +#define CLK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG) +#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG) +#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f4_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f4_clock.h index 93355865..02290fc1 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f4_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f4_clock.h @@ -11,15 +11,15 @@ /** Domain clocks */ /** Bus clocks */ -#define STM32_CLOCK_BUS_AHB1 0x030 -#define STM32_CLOCK_BUS_AHB2 0x034 -#define STM32_CLOCK_BUS_AHB3 0x038 -#define STM32_CLOCK_BUS_APB1 0x040 -#define STM32_CLOCK_BUS_APB2 0x044 -#define STM32_CLOCK_BUS_APB3 0x0A8 +#define STM32_CLOCK_BUS_AHB1 0x030 +#define STM32_CLOCK_BUS_AHB2 0x034 +#define STM32_CLOCK_BUS_AHB3 0x038 +#define STM32_CLOCK_BUS_APB1 0x040 +#define STM32_CLOCK_BUS_APB2 0x044 +#define STM32_CLOCK_BUS_APB3 0x0A8 -#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 -#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 +#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 +#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB3 /** Domain clocks */ /* RM0386, 0390, 0402, 0430 § Dedicated Clock configuration register (RCC_DCKCFGRx) */ @@ -28,16 +28,21 @@ /* defined in stm32_common_clocks.h */ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ +#define STM32_SRC_HSI (STM32_SRC_LSI + 1) +#define STM32_SRC_HSE (STM32_SRC_HSI + 1) /** PLL clock outputs */ -#define STM32_SRC_PLL_P (STM32_SRC_LSI + 1) +#define STM32_SRC_PLL_P (STM32_SRC_HSE + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /** I2S sources */ -#define STM32_SRC_PLLI2S_R (STM32_SRC_PLL_R + 1) +#define STM32_SRC_PLLI2S_Q (STM32_SRC_PLL_R + 1) +#define STM32_SRC_PLLI2S_R (STM32_SRC_PLLI2S_Q + 1) +/* CLK48MHz sources */ +#define STM32_SRC_CK48 (STM32_SRC_PLLI2S_R + 1) + /* I2S_CKIN not supported yet */ /* #define STM32_SRC_I2S_CKIN TBD */ - #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U #define STM32_CLOCK_SHIFT_MASK 0x1FU @@ -60,21 +65,32 @@ * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ - ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ - (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ - (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ + ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ + (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ + (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) -/** @brief RCC_CFGR register offset */ -#define CFGR_REG 0x08 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x08 /** @brief RCC_BDCR register offset */ -#define BDCR_REG 0x70 +#define BDCR_REG 0x70 /** @brief Device domain clocks selection helpers */ /** CFGR devices */ -#define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) +#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 0 +#define MCO_PRE_DIV_2 4 +#define MCO_PRE_DIV_3 5 +#define MCO_PRE_DIV_4 6 +#define MCO_PRE_DIV_5 7 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F4_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f7_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f7_clock.h index 92d3b7e1..a729aea8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f7_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32f7_clock.h @@ -30,13 +30,16 @@ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) +#define STM32_SRC_HSE (STM32_SRC_HSI + 1) /** PLL clock outputs */ -#define STM32_SRC_PLL_P (STM32_SRC_HSI + 1) +#define STM32_SRC_PLL_P (STM32_SRC_HSE + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /** Peripheral bus clock */ #define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1) +#define STM32_SRC_PLLI2S_R (STM32_SRC_PCLK + 1) + #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U @@ -60,7 +63,7 @@ * @param mask Mask for the RCC_CFGRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -74,9 +77,21 @@ /** @brief Device domain clocks selection helpers */ /** CFGR devices */ -#define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) +#define I2S_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 0 +#define MCO_PRE_DIV_2 4 +#define MCO_PRE_DIV_3 5 +#define MCO_PRE_DIV_4 6 +#define MCO_PRE_DIV_5 7 + /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) /** @brief RCC_DKCFGR register offset */ #define DCKCFGR1_REG 0x8C @@ -84,23 +99,23 @@ /** @brief Dedicated clocks configuration register selection helpers */ /** DKCFGR2 devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, DCKCFGR2_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, DCKCFGR2_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, DCKCFGR2_REG) -#define USART4_SEL(val) STM32_CLOCK(val, 3, 6, DCKCFGR2_REG) -#define USART5_SEL(val) STM32_CLOCK(val, 3, 8, DCKCFGR2_REG) -#define USART6_SEL(val) STM32_CLOCK(val, 3, 10, DCKCFGR2_REG) -#define USART7_SEL(val) STM32_CLOCK(val, 3, 12, DCKCFGR2_REG) -#define USART8_SEL(val) STM32_CLOCK(val, 3, 14, DCKCFGR2_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, DCKCFGR2_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 3, 18, DCKCFGR2_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 20, DCKCFGR2_REG) -#define I2C4_SEL(val) STM32_CLOCK(val, 3, 22, DCKCFGR2_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 24, DCKCFGR2_REG) -#define CEC_SEL(val) STM32_CLOCK(val, 1, 26, DCKCFGR2_REG) -#define CK48M_SEL(val) STM32_CLOCK(val, 1, 27, DCKCFGR2_REG) -#define SDMMC1_SEL(val) STM32_CLOCK(val, 1, 28, DCKCFGR2_REG) -#define SDMMC2_SEL(val) STM32_CLOCK(val, 1, 29, DCKCFGR2_REG) -#define DSI_SEL(val) STM32_CLOCK(val, 1, 30, DCKCFGR2_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG) +#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG) +#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG) +#define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG) +#define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG) +#define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG) +#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG) +#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG) +#define CK48M_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG) +#define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG) +#define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG) +#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h index 86d93e83..b7d7714b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g0_clock.h @@ -57,7 +57,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -72,26 +72,26 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) -#define CEC_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR_REG) -#define LPUART2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C2_I2S1_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) -#define TIM1_SEL(val) STM32_CLOCK(val, 1, 22, CCIPR_REG) -#define TIM15_SEL(val) STM32_CLOCK(val, 1, 24, CCIPR_REG) -#define RNG_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) +#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG) +#define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C2_I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) +#define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CCIPR_REG) +#define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) /** CCIPR2 devices */ -#define I2S1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG) -#define I2S2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR2_REG) -#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR2_REG) -#define USB_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG) +#define I2S1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG) +#define I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR2_REG) +#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR2_REG) +#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h index 0cc0b1be..a7d928c8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32g4_clock.h @@ -61,7 +61,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -76,26 +76,26 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) -#define USART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG) -#define USART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) -#define SAI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) -#define I2S23_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) -#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR_REG) -#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) -#define ADC12_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) -#define ADC34_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) +#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) +#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) +#define I2S23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) +#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG) +#define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) +#define ADC12_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) +#define ADC34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) /** CCIPR2 devices */ -#define I2C4_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG) -#define QSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) +#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG) +#define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h5_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h5_clock.h index 070f3b3a..cbac2d66 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h5_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h5_clock.h @@ -20,8 +20,13 @@ #define STM32_SRC_CSI (STM32_SRC_HSE + 1) #define STM32_SRC_HSI (STM32_SRC_CSI + 1) #define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) +/** Bus clock */ +#define STM32_SRC_HCLK (STM32_SRC_HSI48 + 1) +#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1) +#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1) +#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1) /** PLL outputs */ -#define STM32_SRC_PLL1_P (STM32_SRC_HSI48 + 1) +#define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) @@ -68,7 +73,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -84,62 +89,88 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0xF0 +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x1C + /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR1_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 7, 3, CCIPR1_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 7, 6, CCIPR1_REG) -#define USART4_SEL(val) STM32_CLOCK(val, 7, 9, CCIPR1_REG) -#define USART5_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR1_REG) -#define USART6_SEL(val) STM32_CLOCK(val, 7, 15, CCIPR1_REG) -#define USART7_SEL(val) STM32_CLOCK(val, 7, 18, CCIPR1_REG) -#define USART8_SEL(val) STM32_CLOCK(val, 7, 21, CCIPR1_REG) -#define USART9_SEL(val) STM32_CLOCK(val, 7, 24, CCIPR1_REG) -#define USART10_SEL(val) STM32_CLOCK(val, 7, 27, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR1_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR1_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR1_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR1_REG) +#define USART4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR1_REG) +#define USART5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR1_REG) +#define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR1_REG) +#define USART7_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 18, CCIPR1_REG) +#define USART8_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, CCIPR1_REG) +#define USART9_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR1_REG) +#define USART10_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 27, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG) /** CCIPR2 devices */ -#define USART11_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG) -#define USART12_SEL(val) STM32_CLOCK(val, 7, 4, CCIPR2_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR2_REG) -#define LPTIM3_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR2_REG) -#define LPTIM4_SEL(val) STM32_CLOCK(val, 7, 20, CCIPR2_REG) -#define LPTIM5_SEL(val) STM32_CLOCK(val, 7, 24, CCIPR2_REG) -#define LPTIM6_SEL(val) STM32_CLOCK(val, 7, 28, CCIPR2_REG) +#define USART11_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG) +#define USART12_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, CCIPR2_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR2_REG) +#define LPTIM3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR2_REG) +#define LPTIM4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 20, CCIPR2_REG) +#define LPTIM5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR2_REG) +#define LPTIM6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, CCIPR2_REG) /** CCIPR3 devices */ -#define SPI1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG) -#define SPI2_SEL(val) STM32_CLOCK(val, 7, 3, CCIPR3_REG) -#define SPI3_SEL(val) STM32_CLOCK(val, 7, 6, CCIPR3_REG) -#define SPI4_SEL(val) STM32_CLOCK(val, 7, 9, CCIPR3_REG) -#define SPI5_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG) -#define SPI6_SEL(val) STM32_CLOCK(val, 7, 15, CCIPR2_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 24, CCIPR3_REG) +#define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG) +#define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR3_REG) +#define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR3_REG) +#define SPI4_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR3_REG) +#define SPI5_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG) +#define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR2_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR3_REG) /** CCIPR4 devices */ -#define OCTOSPI1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR4_REG) -#define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR4_REG) -#define USB_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR4_REG) -#define SDMMC1_SEL(val) STM32_CLOCK(val, 1, 6, CCIPR4_REG) -#define SDMMC2_SEL(val) STM32_CLOCK(val, 1, 7, CCIPR4_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR4_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR4_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR4_REG) -#define I2C4_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR4_REG) -#define I3C1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR4_REG) +#define OCTOSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR4_REG) +#define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR4_REG) +#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR4_REG) +#define SDMMC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR4_REG) +#define SDMMC2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 7, CCIPR4_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR4_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR4_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR4_REG) +#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR4_REG) +#define I3C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR4_REG) /** CCIPR5 devices */ -#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR5_REG) -#define DAC_SEL(val) STM32_CLOCK(val, 1, 3, CCIPR5_REG) -#define RNG_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR5_REG) -#define CEC_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR5_REG) -#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR5_REG) -#define SAI1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR5_REG) -#define SAI2_SEL(val) STM32_CLOCK(val, 7, 19, CCIPR5_REG) -#define CKPER_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR5_REG) +#define ADCDAC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR5_REG) +#define DAC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 3, CCIPR5_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR5_REG) +#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR5_REG) +#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR5_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR5_REG) +#define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 19, CCIPR5_REG) +#define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR5_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0xF, 18, CFGR1_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR1_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR1_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 1 +#define MCO_PRE_DIV_2 2 +#define MCO_PRE_DIV_3 3 +#define MCO_PRE_DIV_4 4 +#define MCO_PRE_DIV_5 5 +#define MCO_PRE_DIV_6 6 +#define MCO_PRE_DIV_7 7 +#define MCO_PRE_DIV_8 8 +#define MCO_PRE_DIV_9 9 +#define MCO_PRE_DIV_10 10 +#define MCO_PRE_DIV_11 11 +#define MCO_PRE_DIV_12 12 +#define MCO_PRE_DIV_13 13 +#define MCO_PRE_DIV_14 14 +#define MCO_PRE_DIV_15 15 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7_clock.h index 02ed14f2..92c954cd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7_clock.h @@ -80,7 +80,7 @@ * @param mask Mask for the RCC_DxCCIP field. * @param val Clock value (0, 1, 2 or 3). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -95,42 +95,67 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x10 + /** @brief Device domain clocks selection helpers (RM0399.pdf) */ /** D1CCIPR devices */ -#define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG) -#define QSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) -#define DSI_SEL(val) STM32_CLOCK(val, 1, 8, D1CCIPR_REG) -#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 16, D1CCIPR_REG) -#define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG) +#define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) +#define QSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) +#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG) +#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG) +#define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) /* Device domain clocks selection helpers (RM0468.pdf) */ -#define OSPI_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) +#define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) /** D2CCIP1R devices */ -#define SAI1_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP1R_REG) -#define SAI23_SEL(val) STM32_CLOCK(val, 7, 6, D2CCIP1R_REG) -#define SPI123_SEL(val) STM32_CLOCK(val, 7, 12, D2CCIP1R_REG) -#define SPI45_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIP1R_REG) -#define SPDIF_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP1R_REG) -#define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 24, D2CCIP1R_REG) -#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 28, D2CCIP1R_REG) -#define SWP_SEL(val) STM32_CLOCK(val, 1, 31, D2CCIP1R_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG) +#define SAI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG) +#define SPI123_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG) +#define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG) +#define SPDIF_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG) +#define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG) +#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG) +#define SWP_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG) /** D2CCIP2R devices */ -#define USART2345678_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIP2R_REG) -#define USART16_SEL(val) STM32_CLOCK(val, 7, 3, D2CCIP2R_REG) -#define RNG_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIP2R_REG) -#define I2C123_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIP2R_REG) -#define USB_SEL(val) STM32_CLOCK(val, 3, 20, D2CCIP2R_REG) -#define CEC_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIP2R_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 28, D2CCIP2R_REG) +#define USART2345678_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG) +#define USART16_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG) +#define I2C123_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG) +#define USB_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG) +#define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG) /** D3CCIPR devices */ -#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG) -#define I2C4_SEL(val) STM32_CLOCK(val, 3, 8, D3CCIPR_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 7, 10, D3CCIPR_REG) -#define LPTIM345_SEL(val) STM32_CLOCK(val, 7, 13, D3CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 16, D3CCIPR_REG) -#define SAI4A_SEL(val) STM32_CLOCK(val, 7, 21, D3CCIPR_REG) -#define SAI4B_SEL(val) STM32_CLOCK(val, 7, 24, D3CCIPR_REG) -#define SPI6_SEL(val) STM32_CLOCK(val, 7, 28, D3CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG) +#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG) +#define LPTIM345_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG) +#define SAI4A_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG) +#define SAI4B_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG) +#define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 1 +#define MCO_PRE_DIV_2 2 +#define MCO_PRE_DIV_3 3 +#define MCO_PRE_DIV_4 4 +#define MCO_PRE_DIV_5 5 +#define MCO_PRE_DIV_6 6 +#define MCO_PRE_DIV_7 7 +#define MCO_PRE_DIV_8 8 +#define MCO_PRE_DIV_9 9 +#define MCO_PRE_DIV_10 10 +#define MCO_PRE_DIV_11 11 +#define MCO_PRE_DIV_12 12 +#define MCO_PRE_DIV_13 13 +#define MCO_PRE_DIV_14 14 +#define MCO_PRE_DIV_15 15 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h index 579ae56b..e2c1ed81 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h @@ -76,7 +76,7 @@ * @param mask Mask for the RCC_DxCCIP field. * @param val Clock value (0, 1, 2 or 3). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -91,41 +91,67 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x10 + /** @brief Device domain clocks selection helpers (RM0477.pdf) */ /* TODO to be completed */ /** D1CCIPR devices */ -#define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG) -#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 2, D1CCIPR_REG) -#define XSPI1_SEL(val) STM32_CLOCK(val, 3, 4, D1CCIPR_REG) -#define XSPI2_SEL(val) STM32_CLOCK(val, 3, 6, D1CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 24, D1CCIPR_REG) -#define CKPER_SEL(val) STM32_CLOCK(val, 3, 28, D1CCIPR_REG) +#define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) +#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG) +#define XSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) +#define XSPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG) +#define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) /** D2CCIPR devices */ -#define USART234578_SEL(val) STM32_CLOCK(val, 7, 0, D2CCIPR_REG) -#define SPI23_SEL(val) STM32_CLOCK(val, 7, 4, D2CCIPR_REG) -#define I2C23_SEL(val) STM32_CLOCK(val, 3, 8, D2CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIPR_REG) -#define I3C1_SEL(val) STM32_CLOCK(val, 3, 12, D2CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 7, 16, D2CCIPR_REG) -#define FDCAN_SEL(val) STM32_CLOCK(val, 3, 22, D2CCIPR_REG) +#define USART234578_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG) +#define SPI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG) +#define I2C23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG) +#define I3C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIPR_REG) +#define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIPR_REG) /** D3CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 7, 0, D3CCIPR_REG) -#define SPI45_SEL(val) STM32_CLOCK(val, 7, 4, D3CCIPR_REG) -#define SPI1_SEL(val) STM32_CLOCK(val, 7, 8, D3CCIPR_REG) -#define SAI1_SEL(val) STM32_CLOCK(val, 7, 16, D3CCIPR_REG) -#define SAI2_SEL(val) STM32_CLOCK(val, 7, 20, D3CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG) +#define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D3CCIPR_REG) +#define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, D3CCIPR_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D3CCIPR_REG) +#define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 20, D3CCIPR_REG) /** D4CCIPR devices */ -#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, D4CCIPR_REG) -#define SPI6_SEL(val) STM32_CLOCK(val, 7, 4, D4CCIPR_REG) -#define LPTIM23_SEL(val) STM32_CLOCK(val, 7, 8, D4CCIPR_REG) -#define LPTIM45_SEL(val) STM32_CLOCK(val, 7, 12, D4CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D4CCIPR_REG) +#define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D4CCIPR_REG) +#define LPTIM23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, D4CCIPR_REG) +#define LPTIM45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D4CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +/** CFGR devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0xF, 18, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0xF, 25, CFGR_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 1 +#define MCO_PRE_DIV_2 2 +#define MCO_PRE_DIV_3 3 +#define MCO_PRE_DIV_4 4 +#define MCO_PRE_DIV_5 5 +#define MCO_PRE_DIV_6 6 +#define MCO_PRE_DIV_7 7 +#define MCO_PRE_DIV_8 8 +#define MCO_PRE_DIV_9 9 +#define MCO_PRE_DIV_10 10 +#define MCO_PRE_DIV_11 11 +#define MCO_PRE_DIV_12 12 +#define MCO_PRE_DIV_13 13 +#define MCO_PRE_DIV_14 14 +#define MCO_PRE_DIV_15 15 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l0_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l0_clock.h index 5c4d80a2..c16e367a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l0_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l0_clock.h @@ -53,7 +53,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -67,14 +67,14 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) -#define HSI48_SEL(val) STM32_CLOCK(val, 1, 26, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define HSI48_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 26, CCIPR_REG) /** CSR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l1_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l1_clock.h index 1dd1fbb9..f958f7b6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l1_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l1_clock.h @@ -24,6 +24,7 @@ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) +#define STM32_SRC_HSI (STM32_SRC_HSE + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U @@ -47,7 +48,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -56,6 +57,6 @@ /** @brief RCC_CSR register offset */ #define CSR_REG 0x34 -#define RTC_SEL(val) STM32_CLOCK(val, 3, 16, CSR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l4_clock.h index 8249a1bf..3e865f9a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l4_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32l4_clock.h @@ -59,7 +59,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -72,35 +72,41 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x90 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x08 + /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR_REG) -#define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR_REG) -#define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) -#define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) -#define SAI2_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR_REG) -#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) -#define SWPMI1_SEL(val) STM32_CLOCK(val, 1, 30, CCIPR_REG) -#define DFSDM1_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG) +#define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) +#define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) +#define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG) +#define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) +#define SWPMI1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 30, CCIPR_REG) +#define DFSDM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR_REG) /** CCIPR2 devices */ -#define I2C4_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR2_REG) -#define DFSDM_SEL(val) STM32_CLOCK(val, 1, 2, CCIPR2_REG) -#define ADFSDM_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR2_REG) -/* #define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG) */ -/* #define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) */ -#define DSI_SEL(val) STM32_CLOCK(val, 1, 12, CCIPR2_REG) -#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG) -#define OSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) +#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG) +#define DFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, CCIPR2_REG) +#define ADFSDM_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR2_REG) +/* #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG) */ +/* #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG) */ +#define DSI_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 12, CCIPR2_REG) +#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG) +#define OSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u0_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u0_clock.h new file mode 100644 index 00000000..476c4236 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u0_clock.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ + +#include "stm32_common_clocks.h" + +/** Bus gatting clocks */ +#define STM32_CLOCK_BUS_AHB1 0x48 +#define STM32_CLOCK_BUS_IOP 0x4C +#define STM32_CLOCK_BUS_APB1 0x58 +#define STM32_CLOCK_BUS_APB1_2 0x60 + +#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 +#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1_2 + +/** Domain clocks */ +/* RM0503, clock configuration register (RCC_CCIPR) */ + +/** System clock */ +/* defined in stm32_common_clocks.h */ + +/** Fixed clocks */ +/* Low speed clocks defined in stm32_common_clocks.h */ +#define STM32_SRC_HSI (STM32_SRC_LSI + 1) +#define STM32_SRC_HSI48 (STM32_SRC_HSI + 1) +#define STM32_SRC_MSI (STM32_SRC_HSI48 + 1) +#define STM32_SRC_HSE (STM32_SRC_MSI + 1) +/** Peripheral bus clock */ +#define STM32_SRC_PCLK (STM32_SRC_HSE + 1) +/** PLL clock outputs */ +#define STM32_SRC_PLL_P (STM32_SRC_PCLK + 1) +#define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) +#define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) + +#define STM32_CLOCK_REG_MASK 0xFFU +#define STM32_CLOCK_REG_SHIFT 0U +#define STM32_CLOCK_SHIFT_MASK 0x1FU +#define STM32_CLOCK_SHIFT_SHIFT 8U +#define STM32_CLOCK_MASK_MASK 0x7U +#define STM32_CLOCK_MASK_SHIFT 13U +#define STM32_CLOCK_VAL_MASK 0x7U +#define STM32_CLOCK_VAL_SHIFT 16U + +/** + * @brief STM32 clock configuration bit field. + * + * - reg (1/2/3) [ 0 : 7 ] + * - shift (0..31) [ 8 : 12 ] + * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] + * - val (0..7) [ 16 : 18 ] + * + * @param reg RCC_CCIPRx register offset + * @param shift Position within RCC_CCIPRx. + * @param mask Mask for the RCC_CCIPRx field. + * @param val Clock value (0, 1, ... 7). + */ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ + ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ + (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ + (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ + (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) + +/** @brief RCC_CCIPR register offset */ +#define CCIPR_REG 0x88 + +/** @brief RCC_BDCR register offset */ +#define BDCR_REG 0x90 + +/** @brief Device domain clocks selection helpers */ +/** CCIPR devices */ +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) +#define LPUART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG) +#define LPUART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) +#define LPTIM3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) +#define TIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG) +#define TIM15_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 25, CCIPR_REG) +#define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) +/** BDCR devices */ +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u5_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u5_clock.h index 6f240fb3..4bb1f349 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u5_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32u5_clock.h @@ -21,8 +21,13 @@ #define STM32_SRC_HSI48 (STM32_SRC_HSI16 + 1) #define STM32_SRC_MSIS (STM32_SRC_HSI48 + 1) #define STM32_SRC_MSIK (STM32_SRC_MSIS + 1) +/** Bus clock */ +#define STM32_SRC_HCLK (STM32_SRC_MSIK + 1) +#define STM32_SRC_PCLK1 (STM32_SRC_HCLK + 1) +#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1) +#define STM32_SRC_PCLK3 (STM32_SRC_PCLK2 + 1) /** PLL outputs */ -#define STM32_SRC_PLL1_P (STM32_SRC_MSIK + 1) +#define STM32_SRC_PLL1_P (STM32_SRC_PCLK3 + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) @@ -69,7 +74,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -83,48 +88,62 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0xF0 +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x1C + /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG) -#define USART3_SEL(val) STM32_CLOCK(val, 3, 4, CCIPR1_REG) -#define UART4_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR1_REG) -#define UART5_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR1_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR1_REG) -#define I2C4_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR1_REG) -#define SPI2_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR1_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG) -#define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG) -#define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG) -#define FDCAN1_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR1_REG) -#define ICKLK_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_CLOCK(val, 7, 29, CCIPR1_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) +#define USART3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG) +#define UART4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG) +#define UART5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG) +#define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG) +#define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG) +#define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG) +#define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG) +#define FDCAN1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR1_REG) +#define ICKLK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 29, CCIPR1_REG) /** CCIPR2 devices */ -#define MDF1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR2_REG) -#define SAI1_SEL(val) STM32_CLOCK(val, 7, 5, CCIPR2_REG) -#define SAI2_SEL(val) STM32_CLOCK(val, 7, 8, CCIPR2_REG) -#define SAE_SEL(val) STM32_CLOCK(val, 1, 11, CCIPR2_REG) -#define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG) -#define SDMMC_SEL(val) STM32_CLOCK(val, 1, 14, CCIPR2_REG) -#define DSIHOST_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR2_REG) -#define USART6_SEL(val) STM32_CLOCK(val, 1, 16, CCIPR2_REG) -#define LTDC_SEL(val) STM32_CLOCK(val, 1, 18, CCIPR2_REG) -#define OCTOSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) -#define HSPI_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR2_REG) -#define I2C5_SEL(val) STM32_CLOCK(val, 3, 24, CCIPR2_REG) -#define I2C6_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR2_REG) -#define USBPHYC_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR2_REG) +#define MDF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG) +#define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG) +#define SAE_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 11, CCIPR2_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG) +#define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG) +#define DSIHOST_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR2_REG) +#define USART6_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 16, CCIPR2_REG) +#define LTDC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 18, CCIPR2_REG) +#define OCTOSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG) +#define HSPI_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG) +#define I2C5_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG) +#define I2C6_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG) +#define OTGHS_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG) /** CCIPR3 devices */ -#define LPUART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR3_REG) -#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG) -#define LPTIM34_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR3_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG) -#define ADCDAC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG) -#define DAC1_SEL(val) STM32_CLOCK(val, 1, 15, CCIPR3_REG) -#define ADF1_SEL(val) STM32_CLOCK(val, 7, 16, CCIPR3_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG) +#define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG) +#define LPTIM34_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR3_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG) +#define ADCDAC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG) +#define DAC1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR3_REG) +#define ADF1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR3_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) + +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) + +/* MCO prescaler : division factor */ +#define MCO_PRE_DIV_1 0 +#define MCO_PRE_DIV_2 1 +#define MCO_PRE_DIV_4 2 +#define MCO_PRE_DIV_8 3 +#define MCO_PRE_DIV_16 4 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb0_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb0_clock.h new file mode 100644 index 00000000..23ba8e99 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb0_clock.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ + +/** Define system & low-speed clocks */ +#include "stm32_common_clocks.h" + +/** Other fixed clocks. + * - CLKSLOWMUX: used to query slow clock tree frequency + * - CLK16MHZ: secondary clock for LPUART, SPI3/I2S and BLE + * - CLK32MHZ: secondary clock for SPI3/I2S and BLE + */ +#define STM32_SRC_CLKSLOWMUX (STM32_SRC_LSI + 1) +#define STM32_SRC_CLK16MHZ (STM32_SRC_CLKSLOWMUX + 1) +#define STM32_SRC_CLK32MHZ (STM32_SRC_CLK16MHZ + 1) + +/** Bus clocks */ +#define STM32_CLOCK_BUS_AHB0 0x50 +#define STM32_CLOCK_BUS_APB0 0x54 +#define STM32_CLOCK_BUS_APB1 0x58 +#define STM32_CLOCK_BUS_APB2 0x60 + +#define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB0 +#define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB2 + +#define STM32_CLOCK_REG_MASK (0xFFFFU) +#define STM32_CLOCK_REG_SHIFT (0U) +#define STM32_CLOCK_SHIFT_MASK (0x3FU) +#define STM32_CLOCK_SHIFT_SHIFT (16U) +#define STM32_CLOCK_MASK_MASK (0x1FU) +#define STM32_CLOCK_MASK_SHIFT (22U) +#define STM32_CLOCK_VAL_MASK STM32_CLOCK_MASK_MASK +#define STM32_CLOCK_VAL_SHIFT (27U) + +/** + * @brief STM32 clock configuration bit field + * + * @param reg Offset to target configuration register in RCC + * @param shift Position of field within RCC register (= field LSB's index) + * @param mask Mask of field in RCC register + * @param val Field value + * + * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ] + * @note 'shift' range: 0~63 [ 16 : 21 ] + * @note 'mask' range: 0x00~0x1F [ 22 : 26 ] + * @note 'val' range: 0x00~0x1F [ 27 : 31 ] + */ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ + ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ + (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ + (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ + (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) + +/** @brief RCC_CFGR register offset */ +#define CFGR_REG 0x08 + +/** @brief RCC_APB2ENR register offset */ +#define APB2ENR_REG 0x60 + +/** @brief Device clk sources selection helpers */ +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */ +#define SPI2_I2S2_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG) /* WB06/WB07 only */ +/* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */ +#define SPI3_I2S3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb_clock.h index d90b640d..31786c86 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wb_clock.h @@ -60,7 +60,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -77,19 +77,19 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) -#define SAI1_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) -#define CLK48_SEL(val) STM32_CLOCK(val, 3, 26, CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) -#define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) +#define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) +#define CLK48_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) /** CSR devices */ -#define RFWKP_SEL(val) STM32_CLOCK(val, 3, 14, CSR_REG) +#define RFWKP_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wba_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wba_clock.h index 4dc686e8..b8baaada 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wba_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wba_clock.h @@ -18,8 +18,14 @@ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSE (STM32_SRC_LSI + 1) #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1) +/** Bus clock */ +#define STM32_SRC_HCLK1 (STM32_SRC_HSI16 + 1) +#define STM32_SRC_HCLK5 (STM32_SRC_HCLK1 + 1) +#define STM32_SRC_PCLK1 (STM32_SRC_HCLK5 + 1) +#define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1) +#define STM32_SRC_PCLK7 (STM32_SRC_PCLK2 + 1) /** PLL outputs */ -#define STM32_SRC_PLL1_P (STM32_SRC_HSI16 + 1) +#define STM32_SRC_PLL1_P (STM32_SRC_PCLK7 + 1) #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) @@ -62,7 +68,7 @@ #define STM32_CLOCK_VAL_MASK 0x7U #define STM32_CLOCK_VAL_SHIFT 16U -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -77,22 +83,22 @@ /** @brief Device clk sources selection helpers */ /** CCIPR1 devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR1_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR1_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR1_REG) -#define SPI1_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR1_REG) -#define SYSTICK_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR1_REG) -#define TIMIC_SEL(val) STM32_CLOCK(val, 1, 31, CCIPR1_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG) +#define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG) +#define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG) +#define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG) /** CCIPR2 devices */ -#define RNG_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR2_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG) /** CCIPR3 devices */ -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR3_REG) -#define SPI3_SEL(val) STM32_CLOCK(val, 3, 3, CCIPR3_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 6, CCIPR3_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR3_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 7, 12, CCIPR3_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR3_REG) +#define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG) /** BCDR1 devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BCDR1_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BCDR1_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wl_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wl_clock.h index 125e9a76..73847032 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wl_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/clock/stm32wl_clock.h @@ -60,7 +60,7 @@ * @param mask Mask for the RCC_CCIPRx field. * @param val Clock value (0, 1, ... 7). */ -#define STM32_CLOCK(val, mask, shift, reg) \ +#define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ @@ -74,19 +74,19 @@ /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ -#define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) -#define USART2_SEL(val) STM32_CLOCK(val, 3, 2, CCIPR_REG) -#define SPI2_SEL(val) STM32_CLOCK(val, 3, 8, CCIPR_REG) -#define LPUART1_SEL(val) STM32_CLOCK(val, 3, 10, CCIPR_REG) -#define I2C1_SEL(val) STM32_CLOCK(val, 3, 12, CCIPR_REG) -#define I2C2_SEL(val) STM32_CLOCK(val, 3, 14, CCIPR_REG) -#define I2C3_SEL(val) STM32_CLOCK(val, 3, 16, CCIPR_REG) -#define LPTIM1_SEL(val) STM32_CLOCK(val, 3, 18, CCIPR_REG) -#define LPTIM2_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR_REG) -#define LPTIM3_SEL(val) STM32_CLOCK(val, 3, 22, CCIPR_REG) -#define ADC_SEL(val) STM32_CLOCK(val, 3, 28, CCIPR_REG) -#define RNG_SEL(val) STM32_CLOCK(val, 3, 30, CCIPR_REG) +#define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG) +#define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG) +#define SPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG) +#define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) +#define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG) +#define I2C2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG) +#define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG) +#define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG) +#define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG) +#define LPTIM3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG) +#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG) +#define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG) /** BDCR devices */ -#define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/dma_smartbond.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/dma_smartbond.h index 4240801c..abbaad11 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/dma_smartbond.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/dma_smartbond.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef DMA_SMARTBOND_H_ -#define DMA_SMARTBOND_H_ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_DMA_SMARTBOND_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_DMA_SMARTBOND_H_ /** * @brief Vendror-specific DMA peripheral triggering sources. @@ -28,4 +28,4 @@ #define DMA_SMARTBOND_TRIG_MUX_SDADC 0xD #define DMA_SMARTBOND_TRIG_MUX_NONE 0xF -#endif /* DMA_SMARTBOND_H_ */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_DMA_SMARTBOND_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32655_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32655_dma.h new file mode 100644 index 00000000..bedb4b5a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32655_dma.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32655_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32655_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI1_RX 0x01U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_ADC 0x09U +#define MAX32_DMA_SLOT_I2C2_RX 0x0AU +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_SPI0_RX 0x0FU +#define MAX32_DMA_SLOT_UART3_RX 0x1CU +#define MAX32_DMA_SLOT_SPI1_TX 0x21U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_I2C2_TX 0x2AU +#define MAX32_DMA_SLOT_CRC 0x2CU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_SPI0_TX 0x2FU +#define MAX32_DMA_SLOT_UART3_TX 0x3CU +#define MAX32_DMA_SLOT_I2S 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32655_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32662_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32662_dma.h new file mode 100644 index 00000000..4ba582b8 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32662_dma.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI0_RX 0x01U +#define MAX32_DMA_SLOT_SPI1_RX 0x02U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_CAN_RX 0x06U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_ADC 0x09U +#define MAX32_DMA_SLOT_I2S_RX 0x1EU +#define MAX32_DMA_SLOT_SPI0_TX 0x21U +#define MAX32_DMA_SLOT_SPI1_TX 0x22U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_CAN_TX 0x26U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_I2S_TX 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32666_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32666_dma.h new file mode 100644 index 00000000..8296e020 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32666_dma.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2023 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI1_RX 0x01U +#define MAX32_DMA_SLOT_SPI2_RX 0x02U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_ADC 0x09U +#define MAX32_DMA_SLOT_I2C2_RX 0x0AU +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_SPI0_RX 0x0FU +#define MAX32_DMA_SLOT_SPI1_TX 0x21U +#define MAX32_DMA_SLOT_SPI2_TX 0x21U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_I2C2_TX 0x2AU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_SPI0_TX 0x2FU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32666_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32670_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32670_dma.h new file mode 100644 index 00000000..3eaf7182 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32670_dma.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32670_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32670_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI0_RX 0x01U +#define MAX32_DMA_SLOT_SPI1_RX 0x02U +#define MAX32_DMA_SLOT_SPI2_RX 0x03U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_I2C2_RX 0x0AU +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_AES_RX 0x10U +#define MAX32_DMA_SLOT_UART3_RX 0x1CU +#define MAX32_DMA_SLOT_I2S_RX 0x1EU +#define MAX32_DMA_SLOT_SPI0_TX 0x21U +#define MAX32_DMA_SLOT_SPI1_TX 0x22U +#define MAX32_DMA_SLOT_SPI2_TX 0x23U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_I2C2_TX 0x2AU +#define MAX32_DMA_SLOT_CRC 0x2CU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_AES_TX 0x30U +#define MAX32_DMA_SLOT_UART3_TX 0x3CU +#define MAX32_DMA_SLOT_I2S_TX 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32670_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32672_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32672_dma.h new file mode 100644 index 00000000..f6b1a134 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32672_dma.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI0_RX 0x01U +#define MAX32_DMA_SLOT_SPI1_RX 0x02U +#define MAX32_DMA_SLOT_SPI2_RX 0x03U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_ADC 0x09U +#define MAX32_DMA_SLOT_I2C2_RX 0x0AU +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_AES_RX 0x10U +#define MAX32_DMA_SLOT_UART3_RX 0x1CU +#define MAX32_DMA_SLOT_I2S_RX 0x1EU +#define MAX32_DMA_SLOT_SPI0_TX 0x21U +#define MAX32_DMA_SLOT_SPI1_TX 0x22U +#define MAX32_DMA_SLOT_SPI2_TX 0x23U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_I2C2_TX 0x2AU +#define MAX32_DMA_SLOT_CRC 0x2CU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_AES_TX 0x30U +#define MAX32_DMA_SLOT_UART3_TX 0x3CU +#define MAX32_DMA_SLOT_I2S_TX 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32672_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32675_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32675_dma.h new file mode 100644 index 00000000..e627637d --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32675_dma.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI0_RX 0x01U +#define MAX32_DMA_SLOT_SPI1_RX 0x02U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C2_RX 0x0AU +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_AES_RX 0x10U +#define MAX32_DMA_SLOT_I2S_RX 0x1EU +#define MAX32_DMA_SLOT_SPI0_TX 0x21U +#define MAX32_DMA_SLOT_SPI1_TX 0x22U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C2_TX 0x2AU +#define MAX32_DMA_SLOT_CRC 0x2CU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_AES_TX 0x30U +#define MAX32_DMA_SLOT_I2S_TX 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32675_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32680_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32680_dma.h new file mode 100644 index 00000000..dd5451e4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32680_dma.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32680_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32680_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI1_RX 0x01U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_ADC 0x09U +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_SPI0_RX 0x0FU +#define MAX32_DMA_SLOT_UART3_RX 0x1CU +#define MAX32_DMA_SLOT_I2S_RX 0x1EU +#define MAX32_DMA_SLOT_SPI1_TX 0x21U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_CRC 0x2CU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_SPI0_TX 0x2FU +#define MAX32_DMA_SLOT_UART3_TX 0x3CU +#define MAX32_DMA_SLOT_I2S_TX 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32680_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32690_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32690_dma.h new file mode 100644 index 00000000..9e4bb8e5 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max32690_dma.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2023 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32690_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32690_DMA_H_ + +#define MAX32_DMA_SLOT_MEMTOMEM 0x00U +#define MAX32_DMA_SLOT_SPI0_RX 0x01U +#define MAX32_DMA_SLOT_SPI1_RX 0x02U +#define MAX32_DMA_SLOT_SPI2_RX 0x03U +#define MAX32_DMA_SLOT_UART0_RX 0x04U +#define MAX32_DMA_SLOT_UART1_RX 0x05U +#define MAX32_DMA_SLOT_CAN0_RX 0x06U +#define MAX32_DMA_SLOT_I2C0_RX 0x07U +#define MAX32_DMA_SLOT_I2C1_RX 0x08U +#define MAX32_DMA_SLOT_ADC 0x09U +#define MAX32_DMA_SLOT_I2C2_RX 0x0AU +#define MAX32_DMA_SLOT_UART2_RX 0x0EU +#define MAX32_DMA_SLOT_SPI3_RX 0x0FU +#define MAX32_DMA_SLOT_SPI4_RX 0x10U +#define MAX32_DMA_SLOT_USB1_IN 0x11U +#define MAX32_DMA_SLOT_USB2_IN 0x12U +#define MAX32_DMA_SLOT_USB3_IN 0x13U +#define MAX32_DMA_SLOT_USB4_IN 0x14U +#define MAX32_DMA_SLOT_USB5_IN 0x15U +#define MAX32_DMA_SLOT_USB6_IN 0x16U +#define MAX32_DMA_SLOT_USB7_IN 0x17U +#define MAX32_DMA_SLOT_USB8_IN 0x18U +#define MAX32_DMA_SLOT_USB9_IN 0x19U +#define MAX32_DMA_SLOT_USB10_IN 0x1AU +#define MAX32_DMA_SLOT_USB11_IN 0x1BU +#define MAX32_DMA_SLOT_UART3_RX 0x1CU +#define MAX32_DMA_SLOT_I2S_RX 0x1EU +#define MAX32_DMA_SLOT_CAN1_RX 0x1FU +#define MAX32_DMA_SLOT_SPI0_TX 0x21U +#define MAX32_DMA_SLOT_SPI1_TX 0x22U +#define MAX32_DMA_SLOT_SPI2_TX 0x23U +#define MAX32_DMA_SLOT_UART0_TX 0x24U +#define MAX32_DMA_SLOT_UART1_TX 0x25U +#define MAX32_DMA_SLOT_CAN0_TX 0x26U +#define MAX32_DMA_SLOT_I2C0_TX 0x27U +#define MAX32_DMA_SLOT_I2C1_TX 0x28U +#define MAX32_DMA_SLOT_I2C2_TX 0x2AU +#define MAX32_DMA_SLOT_UART2_TX 0x2EU +#define MAX32_DMA_SLOT_SPI3_TX 0x2FU +#define MAX32_DMA_SLOT_SPI4_TX 0x30U +#define MAX32_DMA_SLOT_USB1_OUT 0x31U +#define MAX32_DMA_SLOT_USB2_OUT 0x32U +#define MAX32_DMA_SLOT_USB3_OUT 0x33U +#define MAX32_DMA_SLOT_USB4_OUT 0x34U +#define MAX32_DMA_SLOT_USB5_OUT 0x35U +#define MAX32_DMA_SLOT_USB6_OUT 0x36U +#define MAX32_DMA_SLOT_USB7_OUT 0x37U +#define MAX32_DMA_SLOT_USB8_OUT 0x38U +#define MAX32_DMA_SLOT_USB9_OUT 0x39U +#define MAX32_DMA_SLOT_USB10_OUT 0x3AU +#define MAX32_DMA_SLOT_USB11_OUT 0x3BU +#define MAX32_DMA_SLOT_UART3_TX 0x3CU +#define MAX32_DMA_SLOT_I2S_TX 0x3EU +#define MAX32_DMA_SLOT_CAN1_TX 0x3FU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32690_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max78002_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max78002_dma.h new file mode 100644 index 00000000..cb5592b3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/max78002_dma.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ + +#define MAX78_DMA_SLOT_MEMTOMEM 0x00U +#define MAX78_DMA_SLOT_SPI1_RX 0x01U +#define MAX78_DMA_SLOT_UART0_RX 0x04U +#define MAX78_DMA_SLOT_UART1_RX 0x05U +#define MAX78_DMA_SLOT_I2C0_RX 0x07U +#define MAX78_DMA_SLOT_I2C1_RX 0x08U +#define MAX78_DMA_SLOT_ADC 0x09U +#define MAX78_DMA_SLOT_I2C2_RX 0x0AU +#define MAX78_DMA_SLOT_UART2_RX 0x0EU +#define MAX78_DMA_SLOT_SPI0_RX 0x0FU +#define MAX78_DMA_SLOT_AES_RX 0x10U +#define MAX78_DMA_SLOT_I2S_RX 0x1EU +#define MAX78_DMA_SLOT_SPI1_TX 0x21U +#define MAX78_DMA_SLOT_UART0_TX 0x24U +#define MAX78_DMA_SLOT_UART1_TX 0x25U +#define MAX78_DMA_SLOT_I2C0_TX 0x27U +#define MAX78_DMA_SLOT_I2C1_TX 0x28U +#define MAX78_DMA_SLOT_I2C2_TX 0x2AU +#define MAX78_DMA_SLOT_CRC 0x2CU +#define MAX78_DMA_SLOT_UART2_TX 0x2EU +#define MAX78_DMA_SLOT_SPI0_TX 0x2FU +#define MAX78_DMA_SLOT_AES_TX 0x30U +#define MAX78_DMA_SLOT_I2S_TX 0x3EU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78002_DMA_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/stm32_dma.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/stm32_dma.h index d61f6dfa..a6c1448b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/stm32_dma.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/dma/stm32_dma.h @@ -46,6 +46,8 @@ /** DMA Peripheral increment offset config on bit 15 */ #define STM32_DMA_CH_CFG_PERIPH_INC_FIXED(val) ((val & 0x1) << 15) +#define STM32_DMA_OFFSET_LINKED_BUS STM32_DMA_CH_CFG_PERIPH_INC_FIXED(0) +#define STM32_DMA_OFFSET_FIXED_4 STM32_DMA_CH_CFG_PERIPH_INC_FIXED(1) /** DMA Priority config on bits 16, 17*/ #define STM32_DMA_CH_CFG_PRIORITY(val) ((val & 0x3) << 16) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/espi/npcx_espi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/espi/npcx_espi.h index d73eef41..e4851cc8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/espi/npcx_espi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/espi/npcx_espi.h @@ -6,6 +6,20 @@ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ESPI_NPCX_ESPI_H_ #define ZEPHYR_INCLUDE_DT_BINDINGS_ESPI_NPCX_ESPI_H_ +/* + * Encode virtual wire information into a 16-bit unsigned. + * index = bits[7:0], Replacement index number + * group = bits[11:8], Group number for VWEVMS or VWEVSM + * dir = bits[13:12], Direction for controller to target or target to controller + */ +#define ESPI_NPCX_VW_EX_VAL(dir, group, index) \ + (((dir & 0x1) << 12) + ((group & 0xf) << 8) + (index & 0xff)) + +/* extract specific information from encoded ESPI_NPCX_VW_EX_VAL */ +#define ESPI_NPCX_VW_EX_INDEX(e) ((e) & 0xff) +#define ESPI_NPCX_VW_EX_GROUP_NUM(e) (((e) >> 8) & 0xf) +#define ESPI_NPCX_VW_EX_DIR(e) (((e) >> 12) & 0x1) + /* eSPI VW Master to Slave Register Index */ #define NPCX_VWEVMS0 0 #define NPCX_VWEVMS1 1 @@ -17,6 +31,9 @@ #define NPCX_VWEVMS7 7 #define NPCX_VWEVMS8 8 #define NPCX_VWEVMS9 9 +#define NPCX_VWEVMS10 10 +#define NPCX_VWEVMS11 11 +#define NPCX_VWEVMS_MAX 12 /* eSPI VW Slave to Master Register Index */ #define NPCX_VWEVSM0 0 @@ -29,8 +46,7 @@ #define NPCX_VWEVSM7 7 #define NPCX_VWEVSM8 8 #define NPCX_VWEVSM9 9 -#define NPCX_VWEVSM10 10 -#define NPCX_VWEVSM11 11 +#define NPCX_VWEVSM_MAX 10 /* eSPI VW GPIO Slave to Master Register Index */ #define NPCX_VWGPSM0 0 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gnss/u_blox_m8.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gnss/u_blox_m8.h new file mode 100644 index 00000000..26117e63 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gnss/u_blox_m8.h @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M8_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M8_H_ + +#include + +/* UART Baudrate. */ +#define UBX_M8_UART_BAUDRATE_4800 0x00 +#define UBX_M8_UART_BAUDRATE_9600 0x01 +#define UBX_M8_UART_BAUDRATE_19200 0x02 +#define UBX_M8_UART_BAUDRATE_38400 0x03 +#define UBX_M8_UART_BAUDRATE_57600 0x04 +#define UBX_M8_UART_BAUDRATE_115200 0x05 +#define UBX_M8_UART_BAUDRATE_230400 0x06 +#define UBX_M8_UART_BAUDRATE_460800 0x07 +#define UBX_M8_UART_BAUDRATE_921600 0x08 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M8_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/espressif-esp32-gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/espressif-esp32-gpio.h index 36f824cd..cbea44cd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/espressif-esp32-gpio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/espressif-esp32-gpio.h @@ -32,4 +32,24 @@ /** @} */ +/** + * @name GPIO pin input/output enable flags + * + * These flags allow configuring a pin as input or output while keeping untouched + * its complementary configuration. By instance, if we configure a GPIO pin as an + * input and pass the flag ESP32_GPIO_PIN_OUT_EN, the driver will not disable the + * pin's output buffer. This functionality can be useful to render a pin both an + * input and output, for diagnose or testing purposes. + * + * @{ + */ + +/** Keep GPIO pin enabled as output */ +#define ESP32_GPIO_PIN_OUT_EN (1 << 12) + +/** Keep GPIO pin enabled as input */ +#define ESP32_GPIO_PIN_IN_EN (1 << 13) + +/** @} */ + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ESPRESSIF_ESP32_GPIO_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/nordic-npm2100-gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/nordic-npm2100-gpio.h new file mode 100644 index 00000000..8173c128 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/nordic-npm2100-gpio.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM2100_GPIO_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM2100_GPIO_H_ + +/** + * @brief nPM2100-specific GPIO Flags + * @defgroup gpio_interface_npm2100 nPM2100-specific GPIO Flags + * + * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as + * follows: + * + * - Bit 8: Drive strength (0=1mA, 1=6mA) + * - Bit 9: Debounce (0=OFF, 1=ON) + * + * @ingroup gpio_interface + * @{ + */ + +/** + * @name nPM2100 GPIO drive strength flags + * @brief nPM2100 GPIO drive strength flags + * @{ + */ + +/** @cond INTERNAL_HIDDEN */ +/** Drive mode field mask */ +#define NPM2100_GPIO_DRIVE_MSK 0x0100U +/** @endcond */ + +/** Normal drive */ +#define NPM2100_GPIO_DRIVE_NORMAL (0U << 8U) +/** High drive */ +#define NPM2100_GPIO_DRIVE_HIGH (1U << 8U) + +/** @} */ + +/** + * @name nPM2100 GPIO debounce flags + * @brief nPM2100 GPIO debounce flags + * @{ + */ + +/** @cond INTERNAL_HIDDEN */ +/** Debounce field mask */ +#define NPM2100_GPIO_DEBOUNCE_MSK 0x0200U +/** @endcond */ + +/** Normal drive */ +#define NPM2100_GPIO_DEBOUNCE_OFF (0U << 9U) +/** High drive */ +#define NPM2100_GPIO_DEBOUNCE_ON (1U << 9U) + +/** @} */ + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NORDIC_NPM2100_GPIO_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h new file mode 100644 index 00000000..335f4b1c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/renesas-ra-gpio-ioport.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ + +#define RENESAS_GPIO_DS_POS (8) +#define RENESAS_GPIO_DS_MSK (0x3U << RENESAS_GPIO_DS_POS) +/* GPIO Drive strength */ +#define RENESAS_GPIO_DS_LOW (0x0 << RENESAS_GPIO_DRIVE_POS) +#define RENESAS_GPIO_DS_MIDDLE (0x1 << RENESAS_GPIO_DRIVE_POS) +#define RENESAS_GPIO_DS_HIGH_SPEED_HIGH_DRIVE (0x2 << RENESAS_GPIO_DRIVE_POS) +#define RENESAS_GPIO_DS_HIGH_DRIVE (0x3 << RENESAS_GPIO_DRIVE_POS) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RA_GPIO_IOPORT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h new file mode 100644 index 00000000..30729af9 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ + +/*********************************RZG3S*****************************************/ + +/** + * @brief RZ G3S specific GPIO Flags + * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as + * follows: + * - Bit 9..8: Pin driving ability value + * - Bit 11..10: Digital Noise Filter Clock Selection value + * - Bit 13..12: Digital Noise Filter Number value + * - Bit 14: Digital Noise Filter ON/OFF + * example: + * gpio-consumer { + * out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_FILTER_SET(1, 3, 3))>; + * }; + * gpio-consumer { + * out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_IOLH_SET(2))>; + * }; + */ + +/* GPIO drive IOLH */ +#define RZG3S_GPIO_IOLH_SHIFT 7U +#define RZG3S_GPIO_IOLH_SET(iolh_val) (iolh_val << RZG3S_GPIO_IOLH_SHIFT) + +/* GPIO filter */ +#define RZG3S_GPIO_FILTER_SHIFT 9U +#define RZG3S_GPIO_FILNUM_SHIFT 1U +#define RZG3S_GPIO_FILCLKSEL_SHIFT 3U +#define RZG3S_GPIO_FILTER_SET(fillonoff, filnum, filclksel) \ + (((fillonoff) | ((filnum) << RZG3S_GPIO_FILNUM_SHIFT) | \ + ((filclksel) << RZG3S_GPIO_FILCLKSEL_SHIFT)) \ + << RZG3S_GPIO_FILTER_SHIFT) + +/*******************************************************************************/ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h new file mode 100644 index 00000000..ec96e193 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 Felipe Neves. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_CST816S_GESTURE_CODES_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_CST816S_GESTURE_CODES_H_ + +#define CST816S_GESTURE_CODE_NONE 0x00 +#define CST816S_GESTURE_CODE_SWIPE_UP 0x01 +#define CST816S_GESTURE_CODE_SWIPE_DOWN 0x02 +#define CST816S_GESTURE_CODE_SWIPE_LEFT 0x03 +#define CST816S_GESTURE_CODE_SWIPE_RIGHT 0x04 +#define CST816S_GESTURE_CODE_SINGLE_CLICK 0x05 +#define CST816S_GESTURE_CODE_DOUBLE_CLICK 0x0B +#define CST816S_GESTURE_CODE_LONG_PRESS 0x0C + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h index 629c1628..108691db 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/input/input-event-codes.h @@ -26,6 +26,7 @@ #define INPUT_EV_REL 0x02 /**< Relative coordinate event */ #define INPUT_EV_ABS 0x03 /**< Absolute coordinate event */ #define INPUT_EV_MSC 0x04 /**< Miscellaneous event */ +#define INPUT_EV_DEVICE 0xef /**< Device specific input event */ #define INPUT_EV_VENDOR_START 0xf0 /**< Vendor specific event start */ #define INPUT_EV_VENDOR_STOP 0xff /**< Vendor specific event stop */ /** @} */ @@ -194,8 +195,8 @@ #define INPUT_BTN_7 0x107 /**< 7 button */ #define INPUT_BTN_8 0x108 /**< 8 button */ #define INPUT_BTN_9 0x109 /**< 9 button */ -#define INPUT_BTN_A BTN_SOUTH /**< A button */ -#define INPUT_BTN_B BTN_EAST /**< B button */ +#define INPUT_BTN_A INPUT_BTN_SOUTH /**< A button */ +#define INPUT_BTN_B INPUT_BTN_EAST /**< B button */ #define INPUT_BTN_BACK 0x116 /**< Back button */ #define INPUT_BTN_C 0x132 /**< C button */ #define INPUT_BTN_DPAD_DOWN 0x221 /**< Directional pad Down */ @@ -225,8 +226,8 @@ #define INPUT_BTN_TR 0x137 /**< Right trigger (R1) */ #define INPUT_BTN_TR2 0x139 /**< Right trigger 2 (R2) */ #define INPUT_BTN_WEST 0x134 /**< West button */ -#define INPUT_BTN_X BTN_NORTH /**< X button */ -#define INPUT_BTN_Y BTN_WEST /**< Y button */ +#define INPUT_BTN_X INPUT_BTN_NORTH /**< X button */ +#define INPUT_BTN_Y INPUT_BTN_WEST /**< Y button */ #define INPUT_BTN_Z 0x135 /**< Z button */ /** @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h new file mode 100644 index 00000000..5f4cd793 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_ + +#define WIFI_MAC_INTR_SOURCE 0 +#define WIFI_MAC_NMI_SOURCE 1 +#define WIFI_PWR_INTR_SOURCE 2 +#define WIFI_BB_INTR_SOURCE 3 +#define BT_MAC_INTR_SOURCE 4 +#define BT_BB_INTR_SOURCE 5 +#define BT_BB_NMI_SOURCE 6 +#define LP_TIMER_SOURCE 7 +#define COEX_SOURCE 8 +#define BLE_TIMER_SOURCE 9 +#define BLE_SEC_SOURCE 10 +#define I2C_MASTER_SOURCE 11 +#define APB_CTRL_INTR_SOURCE 12 +#define GPIO_INTR_SOURCE 13 +#define GPIO_NMI_SOURCE 14 +#define SPI1_INTR_SOURCE 15 +#define SPI2_INTR_SOURCE 16 +#define UART0_INTR_SOURCE 17 +#define UART1_INTR_SOURCE 18 +#define LEDC_INTR_SOURCE 19 +#define EFUSE_INTR_SOURCE 20 +#define RTC_CORE_INTR_SOURCE 21 +#define I2C_EXT0_INTR_SOURCE 22 +#define TG0_T0_LEVEL_INTR_SOURCE 23 +#define TG0_WDT_LEVEL_INTR_SOURCE 24 +#define CACHE_IA_INTR_SOURCE 25 +#define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 26 +#define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 27 +#define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 28 +#define SPI_MEM_REJECT_CACHE_INTR_SOURCE 29 +#define ICACHE_PRELOAD0_INTR_SOURCE 30 +#define ICACHE_SYNC0_INTR_SOURCE 31 +#define APB_ADC_INTR_SOURCE 32 +#define DMA_CH0_INTR_SOURCE 33 +#define SHA_INTR_SOURCE 34 +#define ECC_INTR_SOURCE 35 +#define FROM_CPU_INTR0_SOURCE 36 +#define FROM_CPU_INTR1_SOURCE 37 +#define FROM_CPU_INTR2_SOURCE 38 +#define FROM_CPU_INTR3_SOURCE 39 +#define ASSIST_DEBUG_INTR_SOURCE 40 +#define CORE0_PIF_PMS_SIZE_INTR_SOURCE 41 +#define CACHE_CORE0_ACS_INTR_SOURCE 42 + +/* RISC-V supports priority values from 1 (lowest) to 15. + * As interrupt controller for Xtensa and RISC-V is shared, this is + * set to an intermediate and compatible value. + */ +#define IRQ_DEFAULT_PRIORITY 3 + +#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h index f5e2cd61..f6059000 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h @@ -70,4 +70,12 @@ #define BAK_PMS_VIOLATE_INTR_SOURCE 60 #define CACHE_CORE0_ACS_INTR_SOURCE 61 +/* RISC-V supports priority values from 1 (lowest) to 15. + * As interrupt controller for Xtensa and RISC-V is shared, this is + * set to an intermediate and compatible value. + */ +#define IRQ_DEFAULT_PRIORITY 3 + +#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h index 644d8cfb..24b55504 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h @@ -86,4 +86,12 @@ #define ECC_INTR_SOURCE 76 /* interrupt of ECC accelerator, level*/ #define MAX_INTR_SOURCE 77 +/* RISC-V supports priority values from 1 (lowest) to 15. + * As interrupt controller for Xtensa and RISC-V is shared, this is + * set to an intermediate and compatible value. + */ +#define IRQ_DEFAULT_PRIORITY 3 + +#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h index d0657714..32194e69 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h @@ -79,4 +79,11 @@ #define CACHE_IA_INTR_SOURCE 68 /* Cache Invalid Access, LEVEL */ #define MAX_INTR_SOURCE 69 /* total number of interrupt sources */ +/* For Xtensa architecture, zero will allocate low/medium + * levels of priority (ESP_INTR_FLAG_LOWMED) + */ +#define IRQ_DEFAULT_PRIORITY 0 + +#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h index fd63ea50..383f9a62 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h @@ -106,4 +106,11 @@ #define ICACHE_SYNC_INTR_SOURCE 94 /* instruction cache sync done, level */ #define MAX_INTR_SOURCE 95 /* total number of interrupt sources */ +/* For Xtensa architecture, zero will allocate low/medium + * levels of priority (ESP_INTR_FLAG_LOWMED) + */ +#define IRQ_DEFAULT_PRIORITY 0 + +#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h index e2b94e57..87c69060 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h @@ -104,4 +104,11 @@ #define DMA_EXTMEM_REJECT_SOURCE 98 #define MAX_INTR_SOURCE 99 /* number of interrupt sources */ +/* For Xtensa architecture, zero will allocate low/medium + * levels of priority (ESP_INTR_FLAG_LOWMED) + */ +#define IRQ_DEFAULT_PRIORITY 0 + +#define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ + #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mfd/mfd_it8801_altctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mfd/mfd_it8801_altctrl.h new file mode 100644 index 00000000..673cb5d2 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mfd/mfd_it8801_altctrl.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 ITE Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MFD_IT8801_ALTCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MFD_IT8801_ALTCTRL_H_ + +/** + * @brief PIN alternate function. + */ +#define IT8801_ALT_FUNC_1 0U +#define IT8801_ALT_FUNC_2 1U +#define IT8801_ALT_FUNC_3 2U +#define IT8801_ALT_DEFAULT 3U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MFD_IT8801_ALTCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h index 25886635..cb3eae16 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h @@ -20,15 +20,15 @@ * command or data byte * * - * .---. .---. .---. .---. .---. .---. .---. .---. - * SCK -' '---' '---' '---' '---' '---' '---' '---' '--- + * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .- + * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' * - * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---. + * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.- * DOUT |D/C| D7| D6| D5| D4| D3| D2| D1| D0|D/C| D7| D6| D5| D4|...| - * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---' + * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'- * | Word 1 | Word n * - * -. .-- + * -. .- * CS '-----------------------------------------------------------' */ #define MIPI_DBI_MODE_SPI_3WIRE 0x1 @@ -37,15 +37,15 @@ * an additional C/D pin will be use to indicate whether the byte is a * command or data byte * - * .---. .---. .---. .---. .---. .---. .---. .---. - * SCK -' '---' '---' '---' '---' '---' '---' '---' '--- + * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. + * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '--- * - * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---. + * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.- * DOUT | D7| D6| D5| D4| D3| D2| D1| D0| D7| D6| D5| D4| D3| D2| D1| D0| - * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---' + * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'- * | Word 1 | Word n * - * -. .-- + * -. .- * CS '---------------------------------------------------------------' * * -.-------------------------------.-------------------------------.- @@ -110,6 +110,68 @@ #define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7 #define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8 +/** MIPI DBI tearing enable synchronization is disabled. */ +#define MIPI_DBI_TE_NO_EDGE 0x0 + +/** + * MIPI DBI tearing enable synchronization on rising edge of TE signal. + * The controller will only send display write data on a rising edge of TE. + * This should be used when the controller can send a frame worth of data + * data to the display panel faster than the display panel can read a frame + * from its RAM + * + * .------. .------. + * TE -----' '------------------------' '------------- + * -----. .----------------------. + * CS '--------' '-------------------- + */ +#define MIPI_DBI_TE_RISING_EDGE 0x1 + +/** + * MIPI DBI tearing enable synchronization on falling edge of TE signal. + * The controller will only send display write data on a falling edge of TE. + * This should be used when the controller sends a frame worth of data + * data to the display panel slower than the display panel can read a frame + * from its RAM. TE synchronization in this mode will only work if the + * controller can complete the write before the display panel completes 2 + * read cycles, otherwise the read pointer will "catch up" with the write + * pointer. + * + * .------. .------. + * TE -----' '------------------------' '------------- + * ------------. .----- + * CS '---------------------------------------' + */ +#define MIPI_DBI_TE_FALLING_EDGE 0x2 + +/** + * SPI transfer of DBI commands as 8-bit blocks, the default behaviour in + * SPI 4 wire (Type C3) mode. The clocking diagram corresponds exactly to + * the illustration of Type C3. + */ +#define MIPI_DBI_SPI_XFR_8BIT 8 +/** + * SPI transfer of DBI commands as 16-bit blocks, a rare and seldom behaviour + * in SPI 4 wire (Type C3) mode. The corresponding clocking diagram is slightly + * different to the illustration of Type C3. + * + * .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. .-. + * SCK -' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '-' '--- + * + * -.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.---.- + * DOUT |D15|D14|D13|D12|D11|D10| D9| D8| D7| D6| D5| D4| D3| D2| D1| D0| + * -'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'---'- + * | Word 1 (stuffing) : (byte) | + * + * -. .- + * CS '---------------------------------------------------------------' + * + * -.---------------------------------------------------------------.- + * CD | D/C | + * -'---------------------------------------------------------------'- + */ +#define MIPI_DBI_SPI_XFR_16BIT 16 + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h index a5fd23fd..60bd120f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h @@ -4,6 +4,7 @@ */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF54H20_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF54H20_H_ #define NRF_DOMAIN_ID_APPLICATION 2 #define NRF_DOMAIN_ID_RADIOCORE 3 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h new file mode 100644 index 00000000..8e4e1759 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-domain-id-nrf9230.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ + +#define NRF_DOMAIN_ID_APPLICATION 2 +#define NRF_DOMAIN_ID_RADIOCORE 3 +#define NRF_DOMAIN_ID_CELLCORE 4 +#define NRF_DOMAIN_ID_GLOBALFAST 12 +#define NRF_DOMAIN_ID_GLOBALSLOW 13 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_DOMAIN_ID_NRF9280_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h new file mode 100644 index 00000000..aec19500 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf9230-engb.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +/* autogenerated using Nordic HAL utils/gen_offsets.py script */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ + +#define NRF_FICR_BLE_ADDRTYPE 0x00CU +#define NRF_FICR_BLE_ADDR_0 0x010U +#define NRF_FICR_BLE_ADDR_1 0x014U +#define NRF_FICR_BLE_ER_0 0x018U +#define NRF_FICR_BLE_ER_1 0x01CU +#define NRF_FICR_BLE_ER_2 0x020U +#define NRF_FICR_BLE_ER_3 0x024U +#define NRF_FICR_BLE_IR_0 0x028U +#define NRF_FICR_BLE_IR_1 0x02CU +#define NRF_FICR_BLE_IR_2 0x030U +#define NRF_FICR_BLE_IR_3 0x034U +#define NRF_FICR_INFO_CONFIGID 0x050U +#define NRF_FICR_INFO_PART 0x054U +#define NRF_FICR_INFO_VARIANT 0x058U +#define NRF_FICR_INFO_PACKAGE 0x05CU +#define NRF_FICR_INFO_RAM 0x060U +#define NRF_FICR_INFO_MRAM 0x064U +#define NRF_FICR_INFO_CODEPAGESIZE 0x068U +#define NRF_FICR_INFO_CODESIZE 0x06CU +#define NRF_FICR_INFO_DEVICETYPE 0x070U +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_CONFIG 0x0A4U +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCONFIG 0x0A8U +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFXOCAL 0x0ACU +#define NRF_FICR_SIPINFO_OVERRIDE_LFOSC_LFRCAUTOCALCONFIG 0x0B0U +#define NRF_FICR_SIPINFO_OVERRIDE_HFXO64M_CONFIG 0x0B4U +#define NRF_FICR_SIPINFO_PARTNO 0x080U +#define NRF_FICR_SIPINFO_HWREVISION_0 0x084U +#define NRF_FICR_SIPINFO_HWREVISION_1 0x085U +#define NRF_FICR_SIPINFO_HWREVISION_2 0x086U +#define NRF_FICR_SIPINFO_HWREVISION_3 0x087U +#define NRF_FICR_SIPINFO_VARIANT_0 0x088U +#define NRF_FICR_SIPINFO_VARIANT_1 0x089U +#define NRF_FICR_SIPINFO_VARIANT_2 0x08AU +#define NRF_FICR_SIPINFO_VARIANT_3 0x08BU +#define NRF_FICR_SIPINFO_PMICVERSION 0x08CU +#define NRF_FICR_SIPINFO_TESTSITE_0 0x090U +#define NRF_FICR_SIPINFO_TESTSITE_1 0x091U +#define NRF_FICR_SIPINFO_TESTSITE_2 0x092U +#define NRF_FICR_SIPINFO_TESTSITE_3 0x093U +#define NRF_FICR_SIPINFO_LOT 0x094U +#define NRF_FICR_SIPINFO_TESTPROGRAMID_0 0x098U +#define NRF_FICR_SIPINFO_TESTPROGRAMID_1 0x099U +#define NRF_FICR_SIPINFO_TESTPROGRAMID_2 0x09AU +#define NRF_FICR_SIPINFO_TESTPROGRAMID_3 0x09BU +#define NRF_FICR_SIPINFO_OSATPARTNO 0x09CU +#define NRF_FICR_SIPINFO_HWBUILDVERSION_0 0x0A0U +#define NRF_FICR_SIPINFO_HWBUILDVERSION_1 0x0A1U +#define NRF_FICR_SIPINFO_HWBUILDVERSION_2 0x0A2U +#define NRF_FICR_SIPINFO_HWBUILDVERSION_3 0x0A3U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREF 0x344U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_0 0x348U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_1 0x34CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALGAIN_2 0x350U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALOFFSET 0x354U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_0 0x358U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_1 0x35CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_2 0x360U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_3 0x364U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_4 0x368U +#define NRF_FICR_TRIM_GLOBAL_SAADC_LINCALCOEFF_5 0x36CU +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALIREF 0x370U +#define NRF_FICR_TRIM_GLOBAL_SAADC_CALVREFTC 0x374U +#define NRF_FICR_TRIM_GLOBAL_CANPLL_TRIM_CTUNE 0x380U +#define NRF_FICR_TRIM_GLOBAL_COMP_REFTRIM 0x390U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP 0x398U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0 0x39CU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_1 0x3A0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_2 0x3A4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_3 0x3A8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_4 0x3ACU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_5 0x3B0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0 0x3B4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_1 0x3B8U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_2 0x3BCU +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_3 0x3C0U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_4 0x3C4U +#define NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_5 0x3C8U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_0_TRIM 0x3CCU +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_1_TRIM 0x3D0U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_2_TRIM 0x3D4U +#define NRF_FICR_TRIM_APPLICATION_MEMCONF_BLOCKTYPE_3_TRIM 0x3D8U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP 0x3DCU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_0 0x3E0U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1 0x3E4U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_2 0x3E8U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_3 0x3ECU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_4 0x3F0U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_5 0x3F4U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_0 0x3F8U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1 0x3FCU +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_2 0x400U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_3 0x404U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_4 0x408U +#define NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_5 0x40CU +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_0_TRIM 0x410U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_1_TRIM 0x414U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_2_TRIM 0x418U +#define NRF_FICR_TRIM_RADIOCORE_MEMCONF_BLOCKTYPE_3_TRIM 0x41CU + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_NRF_FICR_NRF9230_ENGB_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h index 080b4e04..74761bf0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h @@ -4,6 +4,7 @@ */ #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF54H20_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF54H20_H_ #define NRF_OWNER_ID_NONE 0 #define NRF_OWNER_ID_APPLICATION 2 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h new file mode 100644 index 00000000..6d9a8f28 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-owner-id-nrf9230.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ + +#define NRF_OWNER_ID_NONE 0 +#define NRF_OWNER_ID_APPLICATION 2 +#define NRF_OWNER_ID_RADIOCORE 3 +#define NRF_OWNER_ID_CELL 4 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_OWNER_ID_NRF9280_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-tddconf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-tddconf.h new file mode 100644 index 00000000..44bc74e4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/misc/nordic-tddconf.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ + +#define NRF_TDDCONF_SOURCE_STMMAINCORE BIT(0) +#define NRF_TDDCONF_SOURCE_ETMMAINCORE BIT(1) +#define NRF_TDDCONF_SOURCE_STMHWEVENTS BIT(2) +#define NRF_TDDCONF_SOURCE_STMPPR BIT(3) +#define NRF_TDDCONF_SOURCE_STMFLPR BIT(4) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MISC_NORDIC_TDDCONF_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h new file mode 100644 index 00000000..f8bb545c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2024 Michael Hope + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __CH32V003_PINCTRL_H__ +#define __CH32V003_PINCTRL_H__ + +#define CH32V003_PINMUX_PORT_PA 0 +#define CH32V003_PINMUX_PORT_PC 1 +#define CH32V003_PINMUX_PORT_PD 2 + +/* + * Defines the starting bit for the remap field. Note that the I2C1 and USART1 fields are not + * contigious. + */ +#define CH32V003_PINMUX_SPI1_RM 0 +#define CH32V003_PINMUX_I2C1_RM 1 +#define CH32V003_PINMUX_I2C1_RM1 23 +#define CH32V003_PINMUX_USART1_RM 2 +#define CH32V003_PINMUX_USART1_RM1 21 +#define CH32V003_PINMUX_TIM1_RM 6 +#define CH32V003_PINMUX_TIM2_RM 8 + +/* Port number with 0-2 */ +#define CH32V003_PINCTRL_PORT_SHIFT 0 +/* Pin number 0-15 */ +#define CH32V003_PINCTRL_PIN_SHIFT 2 +/* Base remap bit 0-31 */ +#define CH32V003_PINCTRL_RM_BASE_SHIFT 6 +/* Function remapping ID 0-3 */ +#define CH32V003_PINCTRL_RM_SHIFT 11 + +#define CH32V003_PINMUX_DEFINE(port, pin, rm, remapping) \ + ((CH32V003_PINMUX_PORT_##port << CH32V003_PINCTRL_PORT_SHIFT) | \ + (pin << CH32V003_PINCTRL_PIN_SHIFT) | \ + (CH32V003_PINMUX_##rm##_RM << CH32V003_PINCTRL_RM_BASE_SHIFT) | \ + (remapping << CH32V003_PINCTRL_RM_SHIFT)) + +#define TIM1_ETR_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 0) +#define TIM1_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 1) +#define TIM1_ETR_PD4_2 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 2) +#define TIM1_ETR_PC2_3 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 3) +#define TIM1_CH1_PD2_0 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 0) +#define TIM1_CH1_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 1) +#define TIM1_CH1_PD2_2 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 2) +#define TIM1_CH1_PC4_3 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 3) +#define TIM1_CH2_PA1_0 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 0) +#define TIM1_CH2_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 1) +#define TIM1_CH2_PA1_2 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 2) +#define TIM1_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 3) +#define TIM1_CH3_PC3_0 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 0) +#define TIM1_CH3_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, TIM1, 1) +#define TIM1_CH3_PC3_2 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 2) +#define TIM1_CH3_PC5_3 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 3) +#define TIM1_CH4_PC4_0 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 0) +#define TIM1_CH4_PD3_1 CH32V003_PINMUX_DEFINE(PD, 3, TIM1, 1) +#define TIM1_CH4_PC4_2 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 2) +#define TIM1_CH4_PD4_3 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 3) +#define TIM1_BKIN_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 0) +#define TIM1_BKIN_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 1) +#define TIM1_BKIN_PC2_2 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 2) +#define TIM1_BKIN_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 3) +#define TIM1_CH1N_PD0_0 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 0) +#define TIM1_CH1N_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 1) +#define TIM1_CH1N_PD0_2 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 2) +#define TIM1_CH1N_PC3_3 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 3) +#define TIM1_CH2N_PA2_0 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 0) +#define TIM1_CH2N_PC4_1 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 1) +#define TIM1_CH2N_PA2_2 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 2) +#define TIM1_CH2N_PD2_3 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 3) +#define TIM1_CH3N_PD1_0 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 0) +#define TIM1_CH3N_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 1) +#define TIM1_CH3N_PD1_2 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 2) +#define TIM1_CH3N_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 3) + +#define TIM2_ETR_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0) +#define TIM2_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1) +#define TIM2_ETR_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2) +#define TIM2_ETR_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3) +#define TIM2_CH1_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0) +#define TIM2_CH1_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1) +#define TIM2_CH1_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2) +#define TIM2_CH1_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3) +#define TIM2_CH2_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 0) +#define TIM2_CH2_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, TIM2, 1) +#define TIM2_CH2_PD3_2 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 2) +#define TIM2_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM2, 3) +#define TIM2_CH3_PC0_0 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 0) +#define TIM2_CH3_PD2_1 CH32V003_PINMUX_DEFINE(PD, 2, TIM2, 1) +#define TIM2_CH3_PC0_2 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 2) +#define TIM2_CH3_PD6_3 CH32V003_PINMUX_DEFINE(PD, 6, TIM2, 3) +#define TIM2_CH4_PD7_0 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 0) +#define TIM2_CH4_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 1) +#define TIM2_CH4_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 2) +#define TIM2_CH4_PD5_3 CH32V003_PINMUX_DEFINE(PD, 5, TIM2, 3) + +#define USART1_CK_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, USART1, 0) +#define USART1_CK_PD7_1 CH32V003_PINMUX_DEFINE(PD, 7, USART1, 1) +#define USART1_CK_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, USART1, 2) +#define USART1_CK_PC5_3 CH32V003_PINMUX_DEFINE(PC, 5, USART1, 3) +#define USART1_TX_PD5_0 CH32V003_PINMUX_DEFINE(PD, 5, USART1, 0) +#define USART1_TX_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, USART1, 1) +#define USART1_TX_PD6_2 CH32V003_PINMUX_DEFINE(PD, 6, USART1, 2) +#define USART1_TX_PC0_3 CH32V003_PINMUX_DEFINE(PC, 0, USART1, 3) +#define USART1_RX_PD6_0 CH32V003_PINMUX_DEFINE(PD, 6, USART1, 0) +#define USART1_RX_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, USART1, 1) +#define USART1_RX_PD5_2 CH32V003_PINMUX_DEFINE(PD, 5, USART1, 2) +#define USART1_RX_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, USART1, 3) +#define USART1_CTS_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, USART1, 0) +#define USART1_CTS_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, USART1, 1) +#define USART1_CTS_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 2) +#define USART1_CTS_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 3) +#define USART1_RTS_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 0) +#define USART1_RTS_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 1) +#define USART1_RTS_PC7_2 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 2) +#define USART1_RTS_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 3) + +#define SPI1_NSS_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, SPI1, 0) +#define SPI1_NSS_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, SPI1, 1) +#define SPI1_SCK_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 0) +#define SPI1_SCK_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 1) +#define SPI1_MISO_PC7_0 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 0) +#define SPI1_MISO_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 1) +#define SPI1_MOSI_PC6_0 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 0) +#define SPI1_MOSI_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 1) + +#define I2C1_SCL_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, I2C1, 0) +#define I2C1_SCL_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, I2C1, 1) +#define I2C1_SCL_PC5_2 CH32V003_PINMUX_DEFINE(PC, 5, I2C1, 2) +#define I2C1_SDA_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, I2C1, 0) +#define I2C1_SDA_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, I2C1, 1) +#define I2C1_SDA_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, I2C1, 2) + +#endif /* __CH32V003_PINCTRL_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h new file mode 100644 index 00000000..4f6331fe --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c2-gpio-sigmap.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_ + +#define ESP_NOSIG ESP_SIG_INVAL + +#define ESP_SPICLK_OUT_MUX ESP_SPICLK_OUT +#define ESP_SPIQ_IN 0 +#define ESP_SPIQ_OUT 0 +#define ESP_SPID_IN 1 +#define ESP_SPID_OUT 1 +#define ESP_SPIHD_IN 2 +#define ESP_SPIHD_OUT 2 +#define ESP_SPIWP_IN 3 +#define ESP_SPIWP_OUT 3 +#define ESP_SPICLK_OUT 4 +#define ESP_SPICS0_OUT 5 +#define ESP_U0RXD_IN 6 +#define ESP_U0TXD_OUT 6 +#define ESP_U0CTS_IN 7 +#define ESP_U0RTS_OUT 7 +#define ESP_U0DSR_IN 8 +#define ESP_U0DTR_OUT 8 +#define ESP_U1RXD_IN 9 +#define ESP_U1TXD_OUT 9 +#define ESP_U1CTS_IN 10 +#define ESP_U1RTS_OUT 10 +#define ESP_U1DSR_IN 11 +#define ESP_U1DTR_OUT 11 +#define ESP_SPIQ_MONITOR 15 +#define ESP_SPID_MONITOR 16 +#define ESP_SPIHD_MONITOR 17 +#define ESP_SPIWP_MONITOR 18 +#define ESP_SPICS1_OUT 19 +#define ESP_CPU_TESTBUS0 20 +#define ESP_CPU_TESTBUS1 21 +#define ESP_CPU_TESTBUS2 22 +#define ESP_CPU_TESTBUS3 23 +#define ESP_CPU_TESTBUS4 24 +#define ESP_CPU_TESTBUS5 25 +#define ESP_CPU_TESTBUS6 26 +#define ESP_CPU_TESTBUS7 27 +#define ESP_CPU_GPIO_IN0 28 +#define ESP_CPU_GPIO_OUT0 28 +#define ESP_CPU_GPIO_IN1 29 +#define ESP_CPU_GPIO_OUT1 29 +#define ESP_CPU_GPIO_IN2 30 +#define ESP_CPU_GPIO_OUT2 30 +#define ESP_CPU_GPIO_IN3 31 +#define ESP_CPU_GPIO_OUT3 31 +#define ESP_CPU_GPIO_IN4 32 +#define ESP_CPU_GPIO_OUT4 32 +#define ESP_CPU_GPIO_IN5 33 +#define ESP_CPU_GPIO_OUT5 33 +#define ESP_CPU_GPIO_IN6 34 +#define ESP_CPU_GPIO_OUT6 34 +#define ESP_CPU_GPIO_IN7 35 +#define ESP_CPU_GPIO_OUT7 35 +#define ESP_EXT_ADC_START 45 +#define ESP_LEDC_LS_SIG_OUT0 45 +#define ESP_LEDC_LS_SIG_OUT1 46 +#define ESP_LEDC_LS_SIG_OUT2 47 +#define ESP_LEDC_LS_SIG_OUT3 48 +#define ESP_LEDC_LS_SIG_OUT4 49 +#define ESP_LEDC_LS_SIG_OUT5 50 +#define ESP_RMT_SIG_IN0 51 +#define ESP_RMT_SIG_OUT0 51 +#define ESP_RMT_SIG_IN1 52 +#define ESP_RMT_SIG_OUT1 52 +#define ESP_I2CEXT0_SCL_IN 53 +#define ESP_I2CEXT0_SCL_OUT 53 +#define ESP_I2CEXT0_SDA_IN 54 +#define ESP_I2CEXT0_SDA_OUT 54 +#define ESP_FSPICLK_IN 63 +#define ESP_FSPICLK_OUT 63 +#define ESP_FSPIQ_IN 64 +#define ESP_FSPIQ_OUT 64 +#define ESP_FSPID_IN 65 +#define ESP_FSPID_OUT 65 +#define ESP_FSPIHD_IN 66 +#define ESP_FSPIHD_OUT 66 +#define ESP_FSPIWP_IN 67 +#define ESP_FSPIWP_OUT 67 +#define ESP_FSPICS0_IN 68 +#define ESP_FSPICS0_OUT 68 +#define ESP_FSPICS1_OUT 69 +#define ESP_FSPICS2_OUT 70 +#define ESP_FSPICS3_OUT 71 +#define ESP_FSPICS4_OUT 72 +#define ESP_FSPICS5_OUT 73 +#define ESP_EXTERN_PRIORITY_I 77 +#define ESP_EXTERN_PRIORITY_O 77 +#define ESP_EXTERN_ACTIVE_I 78 +#define ESP_EXTERN_ACTIVE_O 78 +#define ESP_GPIO_EVENT_MATRIX_IN0 79 +#define ESP_GPIO_TASK_MATRIX_OUT0 79 +#define ESP_GPIO_EVENT_MATRIX_IN1 80 +#define ESP_GPIO_TASK_MATRIX_OUT1 80 +#define ESP_GPIO_EVENT_MATRIX_IN2 81 +#define ESP_GPIO_TASK_MATRIX_OUT2 81 +#define ESP_GPIO_EVENT_MATRIX_IN3 82 +#define ESP_GPIO_TASK_MATRIX_OUT3 82 +#define ESP_BB_DIAG8_OUT 83 +#define ESP_BB_DIAG9_OUT 84 +#define ESP_BB_DIAG10_OUT 85 +#define ESP_BB_DIAG11_OUT 86 +#define ESP_BB_DIAG12_OUT 87 +#define ESP_BB_DIAG13_OUT 88 +#define ESP_ANT_SEL0 89 +#define ESP_ANT_SEL1 90 +#define ESP_ANT_SEL2 91 +#define ESP_ANT_SEL3 92 +#define ESP_ANT_SEL4 93 +#define ESP_ANT_SEL5 94 +#define ESP_ANT_SEL6 95 +#define ESP_ANT_SEL7 96 +#define ESP_SIG_IN_FUNC_97 97 +#define ESP_SIG_IN_FUNC97 97 +#define ESP_SIG_IN_FUNC_98 98 +#define ESP_SIG_IN_FUNC98 98 +#define ESP_SIG_IN_FUNC_99 99 +#define ESP_SIG_IN_FUNC99 99 +#define ESP_SIG_IN_FUNC_100 100 +#define ESP_SIG_IN_FUNC100 100 +#define ESP_BLE_DBG_SYNCERR 101 +#define ESP_BLE_DBG_SYNC_FOUND 102 +#define ESP_BLE_DBG_CH_IDX 103 +#define ESP_BLE_DBG_SYNC_WINDOW 104 +#define ESP_BLE_DBG_DATA_EN 105 +#define ESP_BLE_DBG_DATA 106 +#define ESP_BLE_DBG_PKT_TX_ON 107 +#define ESP_BLE_DBG_PKT_RX_ON 108 +#define ESP_BLE_DBG_TXRU_ON 109 +#define ESP_BLE_DBG_RXRU_ON 110 +#define ESP_BLE_DBG_LELC_ST0 111 +#define ESP_BLE_DBG_LELC_ST1 112 +#define ESP_BLE_DBG_LELC_ST2 113 +#define ESP_BLE_DBG_LELC_ST3 114 +#define ESP_BLE_DBG_CRCOK 115 +#define ESP_BLE_DBG_CLK_GPIO 116 +#define ESP_BLE_DBG_RADIO_START 117 +#define ESP_BLE_DBG_SEQUENCE_ON 118 +#define ESP_BLE_DBG_COEX_BT_ON 119 +#define ESP_BLE_DBG_COEX_WIFI_ON 120 +#define ESP_CLK_OUT_OUT1 123 +#define ESP_CLK_OUT_OUT2 124 +#define ESP_CLK_OUT_OUT3 125 +#define ESP_SIG_GPIO_OUT 128 +#define ESP_GPIO_MAP_DATE 0x2106190 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_GPIO_SIGMAP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h new file mode 100644 index 00000000..3b57a76c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h @@ -0,0 +1,796 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * NOTE: Autogenerated file using esp_genpinctrl.py + */ + +#ifndef INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_ +#define INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_ + +/* LEDC_CH0 */ +#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +/* LEDC_CH1 */ +#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +/* LEDC_CH2 */ +#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +/* LEDC_CH3 */ +#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +/* LEDC_CH4 */ +#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +/* LEDC_CH5 */ +#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +/* SPIM2_CSEL */ +#define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT) + +#define SPIM2_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT) + +/* SPIM2_CSEL1 */ +#define SPIM2_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT) + +#define SPIM2_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT) + +/* SPIM2_CSEL2 */ +#define SPIM2_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT) + +#define SPIM2_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT) + +/* SPIM2_CSEL3 */ +#define SPIM2_CSEL3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT) + +#define SPIM2_CSEL3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT) + +/* SPIM2_CSEL4 */ +#define SPIM2_CSEL4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT) + +#define SPIM2_CSEL4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT) + +/* SPIM2_CSEL5 */ +#define SPIM2_CSEL5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT) + +#define SPIM2_CSEL5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT) + +/* SPIM2_MISO */ +#define SPIM2_MISO_GPIO0 ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO1 ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO2 ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO3 ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO4 ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO5 ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO6 ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO7 ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO8 ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO9 ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO10 ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO18 ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO19 ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG) + +#define SPIM2_MISO_GPIO20 ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG) + +/* SPIM2_MOSI */ +#define SPIM2_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT) + +#define SPIM2_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT) + +/* SPIM2_SCLK */ +#define SPIM2_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT) + +#define SPIM2_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT) + +/* UART0_CTS */ +#define UART0_CTS_GPIO0 ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO1 ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO2 ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO3 ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO4 ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO5 ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO6 ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO7 ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO8 ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO9 ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO10 ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO18 ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO19 ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG) + +#define UART0_CTS_GPIO20 ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG) + +/* UART0_DSR */ +#define UART0_DSR_GPIO0 ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO1 ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO2 ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO3 ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO4 ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO5 ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO6 ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO7 ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO8 ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO9 ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO10 ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO18 ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO19 ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG) + +#define UART0_DSR_GPIO20 ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG) + +/* UART0_DTR */ +#define UART0_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT) + +#define UART0_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT) + +/* UART0_RTS */ +#define UART0_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT) + +#define UART0_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT) + +/* UART0_RX */ +#define UART0_RX_GPIO0 ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO1 ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO2 ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO3 ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO4 ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO5 ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO6 ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO7 ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO8 ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO9 ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO10 ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO18 ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO19 ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG) + +#define UART0_RX_GPIO20 ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG) + +/* UART0_TX */ +#define UART0_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT) + +#define UART0_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT) + +/* UART1_CTS */ +#define UART1_CTS_GPIO0 ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO1 ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO2 ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO3 ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO4 ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO5 ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO6 ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO7 ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO8 ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO9 ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO10 ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO18 ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO19 ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG) + +#define UART1_CTS_GPIO20 ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG) + +/* UART1_DSR */ +#define UART1_DSR_GPIO0 ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO1 ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO2 ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO3 ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO4 ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO5 ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO6 ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO7 ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO8 ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO9 ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO10 ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO18 ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO19 ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG) + +#define UART1_DSR_GPIO20 ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG) + +/* UART1_DTR */ +#define UART1_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT) + +#define UART1_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT) + +/* UART1_RTS */ +#define UART1_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT) + +#define UART1_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT) + +/* UART1_RX */ +#define UART1_RX_GPIO0 ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO1 ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO2 ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO3 ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO4 ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO5 ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO6 ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO7 ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO8 ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO9 ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO10 ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO18 ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO19 ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG) + +#define UART1_RX_GPIO20 ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG) + +/* UART1_TX */ +#define UART1_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT) + +#define UART1_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT) + + +#endif /* INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h index 2eda20f9..73a2a04c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h @@ -10,2215 +10,1803 @@ #define INC_DT_BINDS_PINCTRL_ESP32C3_PINCTRL_HAL_H_ /* I2C0_SCL */ -#define I2C0_SCL_GPIO0 \ - ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO1 \ - ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO2 \ - ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO3 \ - ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO4 \ - ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO5 \ - ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO6 \ - ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO7 \ - ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO8 \ - ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO9 \ - ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO10 \ - ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO11 \ - ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO12 \ - ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO13 \ - ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO14 \ - ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO15 \ - ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO16 \ - ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO17 \ - ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO18 \ - ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO19 \ - ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO20 \ - ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO21 \ - ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) /* I2C0_SDA */ -#define I2C0_SDA_GPIO0 \ - ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO1 \ - ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO2 \ - ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO3 \ - ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO4 \ - ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO5 \ - ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO6 \ - ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO7 \ - ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO8 \ - ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO9 \ - ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO10 \ - ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO11 \ - ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO12 \ - ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO13 \ - ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO14 \ - ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO15 \ - ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO16 \ - ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO17 \ - ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO18 \ - ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO19 \ - ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO20 \ - ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO21 \ - ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) + +/* I2S_I_BCK */ +#define I2S_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +#define I2S_I_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2SI_BCK_IN, ESP_I2SI_BCK_OUT) + +/* I2S_I_SD */ +#define I2S_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO6 ESP32_PINMUX(6, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO7 ESP32_PINMUX(7, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO18 ESP32_PINMUX(18, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO19 ESP32_PINMUX(19, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2SI_SD_IN, ESP_NOSIG) + +#define I2S_I_SD_GPIO21 ESP32_PINMUX(21, ESP_I2SI_SD_IN, ESP_NOSIG) + +/* I2S_I_WS */ +#define I2S_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO6 ESP32_PINMUX(6, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO7 ESP32_PINMUX(7, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO17 ESP32_PINMUX(17, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO18 ESP32_PINMUX(18, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO19 ESP32_PINMUX(19, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO20 ESP32_PINMUX(20, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +#define I2S_I_WS_GPIO21 ESP32_PINMUX(21, ESP_I2SI_WS_IN, ESP_I2SI_WS_OUT) + +/* I2S_MCLK */ +#define I2S_MCLK_GPIO0 ESP32_PINMUX(0, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO1 ESP32_PINMUX(1, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO2 ESP32_PINMUX(2, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO3 ESP32_PINMUX(3, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO4 ESP32_PINMUX(4, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO5 ESP32_PINMUX(5, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO6 ESP32_PINMUX(6, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO7 ESP32_PINMUX(7, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO8 ESP32_PINMUX(8, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO9 ESP32_PINMUX(9, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO10 ESP32_PINMUX(10, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO11 ESP32_PINMUX(11, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO12 ESP32_PINMUX(12, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO13 ESP32_PINMUX(13, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO14 ESP32_PINMUX(14, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO15 ESP32_PINMUX(15, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO16 ESP32_PINMUX(16, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO17 ESP32_PINMUX(17, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO18 ESP32_PINMUX(18, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO19 ESP32_PINMUX(19, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO20 ESP32_PINMUX(20, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +#define I2S_MCLK_GPIO21 ESP32_PINMUX(21, ESP_I2S_MCLK_IN, ESP_I2S_MCLK_OUT) + +/* I2S_O_BCK */ +#define I2S_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +#define I2S_O_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2SO_BCK_IN, ESP_I2SO_BCK_OUT) + +/* I2S_O_SD */ +#define I2S_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2SO_SD_OUT) + +#define I2S_O_SD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2SO_SD_OUT) + +/* I2S_O_WS */ +#define I2S_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO6 ESP32_PINMUX(6, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO7 ESP32_PINMUX(7, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO15 ESP32_PINMUX(15, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO16 ESP32_PINMUX(16, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO17 ESP32_PINMUX(17, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO18 ESP32_PINMUX(18, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO19 ESP32_PINMUX(19, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO20 ESP32_PINMUX(20, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) + +#define I2S_O_WS_GPIO21 ESP32_PINMUX(21, ESP_I2SO_WS_IN, ESP_I2SO_WS_OUT) /* LEDC_CH0 */ -#define LEDC_CH0_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define LEDC_CH0_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) /* LEDC_CH1 */ -#define LEDC_CH1_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define LEDC_CH1_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) /* LEDC_CH2 */ -#define LEDC_CH2_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) -#define LEDC_CH2_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) /* LEDC_CH3 */ -#define LEDC_CH3_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) -#define LEDC_CH3_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LEDC_CH3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) /* LEDC_CH4 */ -#define LEDC_CH4_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) -#define LEDC_CH4_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LEDC_CH4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) /* LEDC_CH5 */ -#define LEDC_CH5_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) -#define LEDC_CH5_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LEDC_CH5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) /* SPIM2_CSEL */ -#define SPIM2_CSEL_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT) /* SPIM2_CSEL1 */ -#define SPIM2_CSEL1_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT) /* SPIM2_CSEL2 */ -#define SPIM2_CSEL2_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS2_OUT) /* SPIM2_CSEL3 */ -#define SPIM2_CSEL3_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS3_OUT) /* SPIM2_CSEL4 */ -#define SPIM2_CSEL4_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS4_OUT) /* SPIM2_CSEL5 */ -#define SPIM2_CSEL5_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS5_OUT) /* SPIM2_MISO */ -#define SPIM2_MISO_GPIO0 \ - ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO0 ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO1 \ - ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO1 ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO2 \ - ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO2 ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO3 \ - ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO3 ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO4 \ - ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO4 ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO5 \ - ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO5 ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO6 \ - ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO6 ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO7 \ - ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO7 ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO8 \ - ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO8 ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO9 \ - ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO9 ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO10 \ - ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO10 ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO11 \ - ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO11 ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO12 \ - ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO12 ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO13 \ - ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO13 ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO14 \ - ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO14 ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO15 \ - ESP32_PINMUX(15, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO15 ESP32_PINMUX(15, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO16 \ - ESP32_PINMUX(16, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO16 ESP32_PINMUX(16, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO17 \ - ESP32_PINMUX(17, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO17 ESP32_PINMUX(17, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO18 \ - ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO18 ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO19 \ - ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO19 ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO20 \ - ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO20 ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO21 \ - ESP32_PINMUX(21, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO21 ESP32_PINMUX(21, ESP_FSPIQ_IN, ESP_NOSIG) /* SPIM2_MOSI */ -#define SPIM2_MOSI_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPID_OUT) /* SPIM2_SCLK */ -#define SPIM2_SCLK_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICLK_OUT) /* TWAI_BUS_OFF */ -#define TWAI_BUS_OFF_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) /* TWAI_CLKOUT */ -#define TWAI_CLKOUT_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT) /* TWAI_RX */ -#define TWAI_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO0 ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO1 ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO2 ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO3 ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO4 ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO5 ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO6 ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO7 ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO8 ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO9 ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO10 ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO11 ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO12 ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO13 ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO14 ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO15 ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO16 ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO17 ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO18 ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO19 ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO20 ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO21 ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG) /* TWAI_TX */ -#define TWAI_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX) /* UART0_CTS */ -#define UART0_CTS_GPIO0 \ - ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO0 ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO1 \ - ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO1 ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO2 \ - ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO2 ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO3 \ - ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO3 ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO4 \ - ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO4 ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO5 \ - ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO5 ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO6 \ - ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO6 ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO7 \ - ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO7 ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO8 \ - ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO8 ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO9 \ - ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO9 ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO10 \ - ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO10 ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO11 \ - ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO11 ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO12 \ - ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO12 ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO13 \ - ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO13 ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO14 \ - ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO14 ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO15 \ - ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO15 ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO16 \ - ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO16 ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO17 \ - ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO17 ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO18 \ - ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO18 ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO19 \ - ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO19 ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO20 \ - ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO20 ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO21 \ - ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO21 ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG) /* UART0_DSR */ -#define UART0_DSR_GPIO0 \ - ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO0 ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO1 \ - ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO1 ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO2 \ - ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO2 ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO3 \ - ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO3 ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO4 \ - ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO4 ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO5 \ - ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO5 ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO6 \ - ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO6 ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO7 \ - ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO7 ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO8 \ - ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO8 ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO9 \ - ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO9 ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO10 \ - ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO10 ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO11 \ - ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO11 ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO12 \ - ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO12 ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO13 \ - ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO13 ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO14 \ - ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO14 ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO15 \ - ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO15 ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO16 \ - ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO16 ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO17 \ - ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO17 ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO18 \ - ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO18 ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO19 \ - ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO19 ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO20 \ - ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO20 ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO21 \ - ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO21 ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG) /* UART0_DTR */ -#define UART0_DTR_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT) /* UART0_RTS */ -#define UART0_RTS_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT) /* UART0_RX */ -#define UART0_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO0 ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO1 ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO2 ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO3 ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO4 ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO5 ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO6 ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO7 ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO8 ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO9 ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO10 ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO11 ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO12 ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO13 ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO14 ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO15 ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO16 ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO17 ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO18 ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO19 ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO20 ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO21 ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG) /* UART0_TX */ -#define UART0_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT) /* UART1_CTS */ -#define UART1_CTS_GPIO0 \ - ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO0 ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO1 \ - ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO1 ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO2 \ - ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO2 ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO3 \ - ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO3 ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO4 \ - ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO4 ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO5 \ - ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO5 ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO6 \ - ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO6 ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO7 \ - ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO7 ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO8 \ - ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO8 ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO9 \ - ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO9 ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO10 \ - ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO10 ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO11 \ - ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO11 ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO12 \ - ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO12 ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO13 \ - ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO13 ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO14 \ - ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO14 ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO15 \ - ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO15 ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO16 \ - ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO16 ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO17 \ - ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO17 ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO18 \ - ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO18 ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO19 \ - ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO19 ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO20 \ - ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO20 ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO21 \ - ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO21 ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG) /* UART1_DSR */ -#define UART1_DSR_GPIO0 \ - ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO0 ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO1 \ - ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO1 ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO2 \ - ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO2 ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO3 \ - ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO3 ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO4 \ - ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO4 ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO5 \ - ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO5 ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO6 \ - ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO6 ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO7 \ - ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO7 ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO8 \ - ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO8 ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO9 \ - ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO9 ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO10 \ - ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO10 ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO11 \ - ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO11 ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO12 \ - ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO12 ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO13 \ - ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO13 ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO14 \ - ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO14 ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO15 \ - ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO15 ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO16 \ - ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO16 ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO17 \ - ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO17 ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO18 \ - ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO18 ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO19 \ - ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO19 ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO20 \ - ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO20 ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO21 \ - ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO21 ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG) /* UART1_DTR */ -#define UART1_DTR_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT) /* UART1_RTS */ -#define UART1_RTS_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT) /* UART1_RX */ -#define UART1_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO0 ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO1 ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO2 ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO3 ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO4 ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO5 ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO6 ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO7 ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO8 ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO9 ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO10 ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO11 ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO12 ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO13 ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO14 ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO15 ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO16 ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO17 ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO18 ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO19 ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO20 ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO21 ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG) /* UART1_TX */ -#define UART1_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT) - -#define UART1_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT) #endif /* INC_DT_BINDS_PINCTRL_ESP32C3_PINCTRL_HAL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h index f8713bec..0ea85498 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -10,12652 +10,15019 @@ #define INC_DT_BINDS_PINCTRL_ESP32S3_PINCTRL_HAL_H_ /* I2C0_SCL */ -#define I2C0_SCL_GPIO0 \ - ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO1 \ - ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO2 \ - ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO3 \ - ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO4 \ - ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO5 \ - ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO6 \ - ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO7 \ - ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO8 \ - ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO9 \ - ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO10 \ - ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO11 \ - ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO12 \ - ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO13 \ - ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO14 \ - ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO15 \ - ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO16 \ - ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO17 \ - ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO18 \ - ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO19 \ - ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO20 \ - ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO21 \ - ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO26 \ - ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO27 \ - ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO28 \ - ESP32_PINMUX(28, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO29 \ - ESP32_PINMUX(29, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO30 \ - ESP32_PINMUX(30, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO31 \ - ESP32_PINMUX(31, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO32 \ - ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO33 \ - ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO34 \ - ESP32_PINMUX(34, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO35 \ - ESP32_PINMUX(35, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO36 \ - ESP32_PINMUX(36, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO37 \ - ESP32_PINMUX(37, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO38 \ - ESP32_PINMUX(38, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO39 \ - ESP32_PINMUX(39, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO40 \ - ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO41 \ - ESP32_PINMUX(41, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO42 \ - ESP32_PINMUX(42, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO43 \ - ESP32_PINMUX(43, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO44 \ - ESP32_PINMUX(44, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO45 \ - ESP32_PINMUX(45, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO46 \ - ESP32_PINMUX(46, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO46 ESP32_PINMUX(46, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO47 \ - ESP32_PINMUX(47, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) -#define I2C0_SCL_GPIO48 \ - ESP32_PINMUX(48, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) +#define I2C0_SCL_GPIO48 ESP32_PINMUX(48, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT) /* I2C0_SDA */ -#define I2C0_SDA_GPIO0 \ - ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO1 \ - ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO2 \ - ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO3 \ - ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO4 \ - ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO5 \ - ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO6 \ - ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO7 \ - ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO8 \ - ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO9 \ - ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO10 \ - ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO11 \ - ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO12 \ - ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO13 \ - ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO14 \ - ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO15 \ - ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO16 \ - ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO17 \ - ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO18 \ - ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO19 \ - ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO20 \ - ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO21 \ - ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO26 \ - ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO27 \ - ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO28 \ - ESP32_PINMUX(28, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO29 \ - ESP32_PINMUX(29, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO30 \ - ESP32_PINMUX(30, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO31 \ - ESP32_PINMUX(31, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO32 \ - ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO33 \ - ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO34 \ - ESP32_PINMUX(34, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO35 \ - ESP32_PINMUX(35, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO36 \ - ESP32_PINMUX(36, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO37 \ - ESP32_PINMUX(37, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO38 \ - ESP32_PINMUX(38, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO39 \ - ESP32_PINMUX(39, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO40 \ - ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO41 \ - ESP32_PINMUX(41, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO42 \ - ESP32_PINMUX(42, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO43 \ - ESP32_PINMUX(43, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO44 \ - ESP32_PINMUX(44, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO45 \ - ESP32_PINMUX(45, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO46 \ - ESP32_PINMUX(46, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO46 ESP32_PINMUX(46, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO47 \ - ESP32_PINMUX(47, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) -#define I2C0_SDA_GPIO48 \ - ESP32_PINMUX(48, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) +#define I2C0_SDA_GPIO48 ESP32_PINMUX(48, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT) /* I2C1_SCL */ -#define I2C1_SCL_GPIO0 \ - ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO1 \ - ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO2 \ - ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO3 \ - ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO4 \ - ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO5 \ - ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO6 \ - ESP32_PINMUX(6, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO7 \ - ESP32_PINMUX(7, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO8 \ - ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO9 \ - ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO10 \ - ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO11 \ - ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO12 \ - ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO13 \ - ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO14 \ - ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO15 \ - ESP32_PINMUX(15, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO16 \ - ESP32_PINMUX(16, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO17 \ - ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO18 \ - ESP32_PINMUX(18, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO19 \ - ESP32_PINMUX(19, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO20 \ - ESP32_PINMUX(20, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO21 \ - ESP32_PINMUX(21, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO26 \ - ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO27 \ - ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO28 \ - ESP32_PINMUX(28, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO29 \ - ESP32_PINMUX(29, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO30 \ - ESP32_PINMUX(30, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO31 \ - ESP32_PINMUX(31, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO32 \ - ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO33 \ - ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO34 \ - ESP32_PINMUX(34, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO35 \ - ESP32_PINMUX(35, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO36 \ - ESP32_PINMUX(36, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO37 \ - ESP32_PINMUX(37, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO38 \ - ESP32_PINMUX(38, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO39 \ - ESP32_PINMUX(39, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO40 \ - ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO41 \ - ESP32_PINMUX(41, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO42 \ - ESP32_PINMUX(42, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO43 \ - ESP32_PINMUX(43, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO44 \ - ESP32_PINMUX(44, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO45 \ - ESP32_PINMUX(45, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO46 \ - ESP32_PINMUX(46, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO46 ESP32_PINMUX(46, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO47 \ - ESP32_PINMUX(47, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) -#define I2C1_SCL_GPIO48 \ - ESP32_PINMUX(48, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) +#define I2C1_SCL_GPIO48 ESP32_PINMUX(48, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT) /* I2C1_SDA */ -#define I2C1_SDA_GPIO0 \ - ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO1 \ - ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO2 \ - ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO3 \ - ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO4 \ - ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO5 \ - ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO6 \ - ESP32_PINMUX(6, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO7 \ - ESP32_PINMUX(7, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO8 \ - ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO9 \ - ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO10 \ - ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO11 \ - ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO12 \ - ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO13 \ - ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO14 \ - ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO15 \ - ESP32_PINMUX(15, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO16 \ - ESP32_PINMUX(16, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO17 \ - ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO18 \ - ESP32_PINMUX(18, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO19 \ - ESP32_PINMUX(19, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO20 \ - ESP32_PINMUX(20, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO21 \ - ESP32_PINMUX(21, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO26 \ - ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO27 \ - ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO28 \ - ESP32_PINMUX(28, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO29 \ - ESP32_PINMUX(29, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO30 \ - ESP32_PINMUX(30, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO31 \ - ESP32_PINMUX(31, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO32 \ - ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO33 \ - ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO34 \ - ESP32_PINMUX(34, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO35 \ - ESP32_PINMUX(35, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO36 \ - ESP32_PINMUX(36, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO37 \ - ESP32_PINMUX(37, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO38 \ - ESP32_PINMUX(38, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO39 \ - ESP32_PINMUX(39, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO40 \ - ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO41 \ - ESP32_PINMUX(41, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO42 \ - ESP32_PINMUX(42, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO43 \ - ESP32_PINMUX(43, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO44 \ - ESP32_PINMUX(44, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO45 \ - ESP32_PINMUX(45, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO46 \ - ESP32_PINMUX(46, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO46 ESP32_PINMUX(46, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO47 \ - ESP32_PINMUX(47, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO47 ESP32_PINMUX(47, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) -#define I2C1_SDA_GPIO48 \ - ESP32_PINMUX(48, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) +#define I2C1_SDA_GPIO48 ESP32_PINMUX(48, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT) + +/* I2S0_I_BCK */ +#define I2S0_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO28 ESP32_PINMUX(28, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO29 ESP32_PINMUX(29, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO30 ESP32_PINMUX(30, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO31 ESP32_PINMUX(31, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO40 ESP32_PINMUX(40, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO41 ESP32_PINMUX(41, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO42 ESP32_PINMUX(42, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO43 ESP32_PINMUX(43, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO44 ESP32_PINMUX(44, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO45 ESP32_PINMUX(45, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO46 ESP32_PINMUX(46, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO47 ESP32_PINMUX(47, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +#define I2S0_I_BCK_GPIO48 ESP32_PINMUX(48, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT) + +/* I2S0_I_SD */ +#define I2S0_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO28 ESP32_PINMUX(28, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO29 ESP32_PINMUX(29, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO30 ESP32_PINMUX(30, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO31 ESP32_PINMUX(31, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO40 ESP32_PINMUX(40, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO41 ESP32_PINMUX(41, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO42 ESP32_PINMUX(42, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO43 ESP32_PINMUX(43, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO44 ESP32_PINMUX(44, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO45 ESP32_PINMUX(45, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO46 ESP32_PINMUX(46, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO47 ESP32_PINMUX(47, ESP_I2S0I_SD_IN, ESP_NOSIG) + +#define I2S0_I_SD_GPIO48 ESP32_PINMUX(48, ESP_I2S0I_SD_IN, ESP_NOSIG) + +/* I2S0_I_WS */ +#define I2S0_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO28 ESP32_PINMUX(28, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO29 ESP32_PINMUX(29, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO30 ESP32_PINMUX(30, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO31 ESP32_PINMUX(31, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO40 ESP32_PINMUX(40, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO41 ESP32_PINMUX(41, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO42 ESP32_PINMUX(42, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO43 ESP32_PINMUX(43, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO44 ESP32_PINMUX(44, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO45 ESP32_PINMUX(45, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO46 ESP32_PINMUX(46, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO47 ESP32_PINMUX(47, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +#define I2S0_I_WS_GPIO48 ESP32_PINMUX(48, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT) + +/* I2S0_MCLK */ +#define I2S0_MCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +#define I2S0_MCLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S0_MCLK_OUT) + +/* I2S0_O_BCK */ +#define I2S0_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO28 ESP32_PINMUX(28, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO29 ESP32_PINMUX(29, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO30 ESP32_PINMUX(30, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO31 ESP32_PINMUX(31, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO40 ESP32_PINMUX(40, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO41 ESP32_PINMUX(41, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO42 ESP32_PINMUX(42, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO43 ESP32_PINMUX(43, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO44 ESP32_PINMUX(44, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO45 ESP32_PINMUX(45, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO46 ESP32_PINMUX(46, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO47 ESP32_PINMUX(47, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +#define I2S0_O_BCK_GPIO48 ESP32_PINMUX(48, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT) + +/* I2S0_O_SD */ +#define I2S0_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +#define I2S0_O_SD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S0O_SD_OUT) + +/* I2S0_O_WS */ +#define I2S0_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO28 ESP32_PINMUX(28, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO29 ESP32_PINMUX(29, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO30 ESP32_PINMUX(30, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO31 ESP32_PINMUX(31, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO40 ESP32_PINMUX(40, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO41 ESP32_PINMUX(41, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO42 ESP32_PINMUX(42, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO43 ESP32_PINMUX(43, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO44 ESP32_PINMUX(44, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO45 ESP32_PINMUX(45, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO46 ESP32_PINMUX(46, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO47 ESP32_PINMUX(47, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +#define I2S0_O_WS_GPIO48 ESP32_PINMUX(48, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT) + +/* I2S1_I_BCK */ +#define I2S1_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO28 ESP32_PINMUX(28, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO29 ESP32_PINMUX(29, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO30 ESP32_PINMUX(30, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO31 ESP32_PINMUX(31, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO40 ESP32_PINMUX(40, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO41 ESP32_PINMUX(41, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO42 ESP32_PINMUX(42, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO43 ESP32_PINMUX(43, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO44 ESP32_PINMUX(44, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO45 ESP32_PINMUX(45, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO46 ESP32_PINMUX(46, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO47 ESP32_PINMUX(47, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +#define I2S1_I_BCK_GPIO48 ESP32_PINMUX(48, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT) + +/* I2S1_I_SD */ +#define I2S1_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO6 ESP32_PINMUX(6, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO7 ESP32_PINMUX(7, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO18 ESP32_PINMUX(18, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO19 ESP32_PINMUX(19, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO21 ESP32_PINMUX(21, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO26 ESP32_PINMUX(26, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO27 ESP32_PINMUX(27, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO28 ESP32_PINMUX(28, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO29 ESP32_PINMUX(29, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO30 ESP32_PINMUX(30, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO31 ESP32_PINMUX(31, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO32 ESP32_PINMUX(32, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO33 ESP32_PINMUX(33, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO34 ESP32_PINMUX(34, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO35 ESP32_PINMUX(35, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO36 ESP32_PINMUX(36, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO37 ESP32_PINMUX(37, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO38 ESP32_PINMUX(38, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO39 ESP32_PINMUX(39, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO40 ESP32_PINMUX(40, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO41 ESP32_PINMUX(41, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO42 ESP32_PINMUX(42, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO43 ESP32_PINMUX(43, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO44 ESP32_PINMUX(44, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO45 ESP32_PINMUX(45, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO46 ESP32_PINMUX(46, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO47 ESP32_PINMUX(47, ESP_I2S1I_SD_IN, ESP_NOSIG) + +#define I2S1_I_SD_GPIO48 ESP32_PINMUX(48, ESP_I2S1I_SD_IN, ESP_NOSIG) + +/* I2S1_I_WS */ +#define I2S1_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO28 ESP32_PINMUX(28, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO29 ESP32_PINMUX(29, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO30 ESP32_PINMUX(30, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO31 ESP32_PINMUX(31, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO40 ESP32_PINMUX(40, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO41 ESP32_PINMUX(41, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO42 ESP32_PINMUX(42, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO43 ESP32_PINMUX(43, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO44 ESP32_PINMUX(44, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO45 ESP32_PINMUX(45, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO46 ESP32_PINMUX(46, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO47 ESP32_PINMUX(47, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +#define I2S1_I_WS_GPIO48 ESP32_PINMUX(48, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT) + +/* I2S1_MCLK */ +#define I2S1_MCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +#define I2S1_MCLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S1_MCLK_OUT) + +/* I2S1_O_BCK */ +#define I2S1_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO28 ESP32_PINMUX(28, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO29 ESP32_PINMUX(29, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO30 ESP32_PINMUX(30, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO31 ESP32_PINMUX(31, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO40 ESP32_PINMUX(40, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO41 ESP32_PINMUX(41, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO42 ESP32_PINMUX(42, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO43 ESP32_PINMUX(43, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO44 ESP32_PINMUX(44, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO45 ESP32_PINMUX(45, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO46 ESP32_PINMUX(46, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO47 ESP32_PINMUX(47, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +#define I2S1_O_BCK_GPIO48 ESP32_PINMUX(48, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT) + +/* I2S1_O_SD */ +#define I2S1_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +#define I2S1_O_SD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_I2S1O_SD_OUT) + +/* I2S1_O_WS */ +#define I2S1_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO28 ESP32_PINMUX(28, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO29 ESP32_PINMUX(29, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO30 ESP32_PINMUX(30, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO31 ESP32_PINMUX(31, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO40 ESP32_PINMUX(40, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO41 ESP32_PINMUX(41, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO42 ESP32_PINMUX(42, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO43 ESP32_PINMUX(43, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO44 ESP32_PINMUX(44, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO45 ESP32_PINMUX(45, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO46 ESP32_PINMUX(46, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO47 ESP32_PINMUX(47, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +#define I2S1_O_WS_GPIO48 ESP32_PINMUX(48, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) + +/* LCD_CAM_CAM_CLK */ +#define LCD_CAM_CAM_CLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_CAM_CLK) + +#define LCD_CAM_CAM_CLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_CAM_CLK) + +/* LCD_CAM_CAM_PCLK */ +#define LCD_CAM_CAM_PCLK_GPIO0 ESP32_PINMUX(0, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO1 ESP32_PINMUX(1, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO2 ESP32_PINMUX(2, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO3 ESP32_PINMUX(3, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO4 ESP32_PINMUX(4, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO5 ESP32_PINMUX(5, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO6 ESP32_PINMUX(6, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO7 ESP32_PINMUX(7, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO8 ESP32_PINMUX(8, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO9 ESP32_PINMUX(9, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO10 ESP32_PINMUX(10, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO11 ESP32_PINMUX(11, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO12 ESP32_PINMUX(12, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO13 ESP32_PINMUX(13, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO14 ESP32_PINMUX(14, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO15 ESP32_PINMUX(15, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO16 ESP32_PINMUX(16, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO17 ESP32_PINMUX(17, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO18 ESP32_PINMUX(18, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO19 ESP32_PINMUX(19, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO20 ESP32_PINMUX(20, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO21 ESP32_PINMUX(21, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO26 ESP32_PINMUX(26, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO27 ESP32_PINMUX(27, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO28 ESP32_PINMUX(28, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO29 ESP32_PINMUX(29, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO30 ESP32_PINMUX(30, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO31 ESP32_PINMUX(31, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO32 ESP32_PINMUX(32, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO33 ESP32_PINMUX(33, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO34 ESP32_PINMUX(34, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO35 ESP32_PINMUX(35, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO36 ESP32_PINMUX(36, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO37 ESP32_PINMUX(37, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO38 ESP32_PINMUX(38, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO39 ESP32_PINMUX(39, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO40 ESP32_PINMUX(40, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO41 ESP32_PINMUX(41, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO42 ESP32_PINMUX(42, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO43 ESP32_PINMUX(43, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO44 ESP32_PINMUX(44, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO45 ESP32_PINMUX(45, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO46 ESP32_PINMUX(46, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO47 ESP32_PINMUX(47, ESP_CAM_PCLK, ESP_NOSIG) + +#define LCD_CAM_CAM_PCLK_GPIO48 ESP32_PINMUX(48, ESP_CAM_PCLK, ESP_NOSIG) + +/* LCD_CAM_DATA_IN0 */ +#define LCD_CAM_DATA_IN0_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN0, ESP_NOSIG) + +#define LCD_CAM_DATA_IN0_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN0, ESP_NOSIG) + +/* LCD_CAM_DATA_IN1 */ +#define LCD_CAM_DATA_IN1_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN1, ESP_NOSIG) + +#define LCD_CAM_DATA_IN1_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN1, ESP_NOSIG) + +/* LCD_CAM_DATA_IN10 */ +#define LCD_CAM_DATA_IN10_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN10, ESP_NOSIG) + +#define LCD_CAM_DATA_IN10_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN10, ESP_NOSIG) + +/* LCD_CAM_DATA_IN11 */ +#define LCD_CAM_DATA_IN11_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN11, ESP_NOSIG) + +#define LCD_CAM_DATA_IN11_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN11, ESP_NOSIG) + +/* LCD_CAM_DATA_IN12 */ +#define LCD_CAM_DATA_IN12_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN12, ESP_NOSIG) + +#define LCD_CAM_DATA_IN12_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN12, ESP_NOSIG) + +/* LCD_CAM_DATA_IN13 */ +#define LCD_CAM_DATA_IN13_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN13, ESP_NOSIG) + +#define LCD_CAM_DATA_IN13_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN13, ESP_NOSIG) + +/* LCD_CAM_DATA_IN14 */ +#define LCD_CAM_DATA_IN14_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN14, ESP_NOSIG) + +#define LCD_CAM_DATA_IN14_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN14, ESP_NOSIG) + +/* LCD_CAM_DATA_IN15 */ +#define LCD_CAM_DATA_IN15_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN15, ESP_NOSIG) + +#define LCD_CAM_DATA_IN15_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN15, ESP_NOSIG) + +/* LCD_CAM_DATA_IN2 */ +#define LCD_CAM_DATA_IN2_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN2, ESP_NOSIG) + +#define LCD_CAM_DATA_IN2_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN2, ESP_NOSIG) + +/* LCD_CAM_DATA_IN3 */ +#define LCD_CAM_DATA_IN3_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN3, ESP_NOSIG) + +#define LCD_CAM_DATA_IN3_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN3, ESP_NOSIG) + +/* LCD_CAM_DATA_IN4 */ +#define LCD_CAM_DATA_IN4_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN4, ESP_NOSIG) + +#define LCD_CAM_DATA_IN4_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN4, ESP_NOSIG) + +/* LCD_CAM_DATA_IN5 */ +#define LCD_CAM_DATA_IN5_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN5, ESP_NOSIG) + +#define LCD_CAM_DATA_IN5_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN5, ESP_NOSIG) + +/* LCD_CAM_DATA_IN6 */ +#define LCD_CAM_DATA_IN6_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN6, ESP_NOSIG) + +#define LCD_CAM_DATA_IN6_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN6, ESP_NOSIG) + +/* LCD_CAM_DATA_IN7 */ +#define LCD_CAM_DATA_IN7_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN7, ESP_NOSIG) + +#define LCD_CAM_DATA_IN7_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN7, ESP_NOSIG) + +/* LCD_CAM_DATA_IN8 */ +#define LCD_CAM_DATA_IN8_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN8, ESP_NOSIG) + +#define LCD_CAM_DATA_IN8_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN8, ESP_NOSIG) + +/* LCD_CAM_DATA_IN9 */ +#define LCD_CAM_DATA_IN9_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN9, ESP_NOSIG) + +#define LCD_CAM_DATA_IN9_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN9, ESP_NOSIG) + +/* LCD_CAM_DATA_OUT0 */ +#define LCD_CAM_DATA_OUT0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +#define LCD_CAM_DATA_OUT0_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT0) + +/* LCD_CAM_DATA_OUT1 */ +#define LCD_CAM_DATA_OUT1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +#define LCD_CAM_DATA_OUT1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT1) + +/* LCD_CAM_DATA_OUT10 */ +#define LCD_CAM_DATA_OUT10_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +#define LCD_CAM_DATA_OUT10_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT10) + +/* LCD_CAM_DATA_OUT11 */ +#define LCD_CAM_DATA_OUT11_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +#define LCD_CAM_DATA_OUT11_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT11) + +/* LCD_CAM_DATA_OUT12 */ +#define LCD_CAM_DATA_OUT12_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +#define LCD_CAM_DATA_OUT12_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT12) + +/* LCD_CAM_DATA_OUT13 */ +#define LCD_CAM_DATA_OUT13_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +#define LCD_CAM_DATA_OUT13_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT13) + +/* LCD_CAM_DATA_OUT14 */ +#define LCD_CAM_DATA_OUT14_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +#define LCD_CAM_DATA_OUT14_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT14) + +/* LCD_CAM_DATA_OUT15 */ +#define LCD_CAM_DATA_OUT15_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +#define LCD_CAM_DATA_OUT15_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT15) + +/* LCD_CAM_DATA_OUT2 */ +#define LCD_CAM_DATA_OUT2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +#define LCD_CAM_DATA_OUT2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT2) + +/* LCD_CAM_DATA_OUT3 */ +#define LCD_CAM_DATA_OUT3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +#define LCD_CAM_DATA_OUT3_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT3) + +/* LCD_CAM_DATA_OUT4 */ +#define LCD_CAM_DATA_OUT4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +#define LCD_CAM_DATA_OUT4_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT4) + +/* LCD_CAM_DATA_OUT5 */ +#define LCD_CAM_DATA_OUT5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +#define LCD_CAM_DATA_OUT5_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT5) + +/* LCD_CAM_DATA_OUT6 */ +#define LCD_CAM_DATA_OUT6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +#define LCD_CAM_DATA_OUT6_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT6) + +/* LCD_CAM_DATA_OUT7 */ +#define LCD_CAM_DATA_OUT7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +#define LCD_CAM_DATA_OUT7_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT7) + +/* LCD_CAM_DATA_OUT8 */ +#define LCD_CAM_DATA_OUT8_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +#define LCD_CAM_DATA_OUT8_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT8) + +/* LCD_CAM_DATA_OUT9 */ +#define LCD_CAM_DATA_OUT9_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +#define LCD_CAM_DATA_OUT9_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT9) + +/* LCD_CAM_DC */ +#define LCD_CAM_DC_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DC) + +#define LCD_CAM_DC_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DC) + +/* LCD_CAM_H_ENABLE_CAM */ +#define LCD_CAM_H_ENABLE_CAM_GPIO0 ESP32_PINMUX(0, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO1 ESP32_PINMUX(1, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO2 ESP32_PINMUX(2, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO3 ESP32_PINMUX(3, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO4 ESP32_PINMUX(4, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO5 ESP32_PINMUX(5, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO6 ESP32_PINMUX(6, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO7 ESP32_PINMUX(7, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO8 ESP32_PINMUX(8, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO9 ESP32_PINMUX(9, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO10 ESP32_PINMUX(10, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO11 ESP32_PINMUX(11, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO12 ESP32_PINMUX(12, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO13 ESP32_PINMUX(13, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO14 ESP32_PINMUX(14, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO15 ESP32_PINMUX(15, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO16 ESP32_PINMUX(16, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO17 ESP32_PINMUX(17, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO18 ESP32_PINMUX(18, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO19 ESP32_PINMUX(19, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO20 ESP32_PINMUX(20, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO21 ESP32_PINMUX(21, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO26 ESP32_PINMUX(26, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO27 ESP32_PINMUX(27, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO28 ESP32_PINMUX(28, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO29 ESP32_PINMUX(29, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO30 ESP32_PINMUX(30, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO31 ESP32_PINMUX(31, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO32 ESP32_PINMUX(32, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO33 ESP32_PINMUX(33, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO34 ESP32_PINMUX(34, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO35 ESP32_PINMUX(35, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO36 ESP32_PINMUX(36, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO37 ESP32_PINMUX(37, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO38 ESP32_PINMUX(38, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO39 ESP32_PINMUX(39, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO40 ESP32_PINMUX(40, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO41 ESP32_PINMUX(41, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO42 ESP32_PINMUX(42, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO43 ESP32_PINMUX(43, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO44 ESP32_PINMUX(44, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO45 ESP32_PINMUX(45, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO46 ESP32_PINMUX(46, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO47 ESP32_PINMUX(47, ESP_CAM_H_ENABLE, ESP_NOSIG) + +#define LCD_CAM_H_ENABLE_CAM_GPIO48 ESP32_PINMUX(48, ESP_CAM_H_ENABLE, ESP_NOSIG) + +/* LCD_CAM_H_ENABLE_LCD */ +#define LCD_CAM_H_ENABLE_LCD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_H_ENABLE) + +#define LCD_CAM_H_ENABLE_LCD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_H_ENABLE) + +/* LCD_CAM_H_SYNC_CAM */ +#define LCD_CAM_H_SYNC_CAM_GPIO0 ESP32_PINMUX(0, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO1 ESP32_PINMUX(1, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO2 ESP32_PINMUX(2, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO3 ESP32_PINMUX(3, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO4 ESP32_PINMUX(4, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO5 ESP32_PINMUX(5, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO6 ESP32_PINMUX(6, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO7 ESP32_PINMUX(7, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO8 ESP32_PINMUX(8, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO9 ESP32_PINMUX(9, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO10 ESP32_PINMUX(10, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO11 ESP32_PINMUX(11, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO12 ESP32_PINMUX(12, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO13 ESP32_PINMUX(13, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO14 ESP32_PINMUX(14, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO15 ESP32_PINMUX(15, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO16 ESP32_PINMUX(16, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO17 ESP32_PINMUX(17, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO18 ESP32_PINMUX(18, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO19 ESP32_PINMUX(19, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO20 ESP32_PINMUX(20, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO21 ESP32_PINMUX(21, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO26 ESP32_PINMUX(26, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO27 ESP32_PINMUX(27, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO28 ESP32_PINMUX(28, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO29 ESP32_PINMUX(29, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO30 ESP32_PINMUX(30, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO31 ESP32_PINMUX(31, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO32 ESP32_PINMUX(32, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO33 ESP32_PINMUX(33, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO34 ESP32_PINMUX(34, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO35 ESP32_PINMUX(35, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO36 ESP32_PINMUX(36, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO37 ESP32_PINMUX(37, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO38 ESP32_PINMUX(38, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO39 ESP32_PINMUX(39, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO40 ESP32_PINMUX(40, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO41 ESP32_PINMUX(41, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO42 ESP32_PINMUX(42, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO43 ESP32_PINMUX(43, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO44 ESP32_PINMUX(44, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO45 ESP32_PINMUX(45, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO46 ESP32_PINMUX(46, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO47 ESP32_PINMUX(47, ESP_CAM_H_SYNC, ESP_NOSIG) + +#define LCD_CAM_H_SYNC_CAM_GPIO48 ESP32_PINMUX(48, ESP_CAM_H_SYNC, ESP_NOSIG) + +/* LCD_CAM_H_SYNC_LCD */ +#define LCD_CAM_H_SYNC_LCD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_H_SYNC) + +#define LCD_CAM_H_SYNC_LCD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_H_SYNC) + +/* LCD_CAM_LCD_CLK */ +#define LCD_CAM_LCD_CLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_PCLK) + +#define LCD_CAM_LCD_CLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_PCLK) + +/* LCD_CAM_V_SYNC_CAM */ +#define LCD_CAM_V_SYNC_CAM_GPIO0 ESP32_PINMUX(0, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO1 ESP32_PINMUX(1, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO2 ESP32_PINMUX(2, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO3 ESP32_PINMUX(3, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO4 ESP32_PINMUX(4, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO5 ESP32_PINMUX(5, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO6 ESP32_PINMUX(6, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO7 ESP32_PINMUX(7, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO8 ESP32_PINMUX(8, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO9 ESP32_PINMUX(9, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO10 ESP32_PINMUX(10, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO11 ESP32_PINMUX(11, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO12 ESP32_PINMUX(12, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO13 ESP32_PINMUX(13, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO14 ESP32_PINMUX(14, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO15 ESP32_PINMUX(15, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO16 ESP32_PINMUX(16, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO17 ESP32_PINMUX(17, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO18 ESP32_PINMUX(18, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO19 ESP32_PINMUX(19, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO20 ESP32_PINMUX(20, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO21 ESP32_PINMUX(21, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO26 ESP32_PINMUX(26, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO27 ESP32_PINMUX(27, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO28 ESP32_PINMUX(28, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO29 ESP32_PINMUX(29, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO30 ESP32_PINMUX(30, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO31 ESP32_PINMUX(31, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO32 ESP32_PINMUX(32, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO33 ESP32_PINMUX(33, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO34 ESP32_PINMUX(34, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO35 ESP32_PINMUX(35, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO36 ESP32_PINMUX(36, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO37 ESP32_PINMUX(37, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO38 ESP32_PINMUX(38, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO39 ESP32_PINMUX(39, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO40 ESP32_PINMUX(40, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO41 ESP32_PINMUX(41, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO42 ESP32_PINMUX(42, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO43 ESP32_PINMUX(43, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO44 ESP32_PINMUX(44, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO45 ESP32_PINMUX(45, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO46 ESP32_PINMUX(46, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO47 ESP32_PINMUX(47, ESP_CAM_V_SYNC, ESP_NOSIG) + +#define LCD_CAM_V_SYNC_CAM_GPIO48 ESP32_PINMUX(48, ESP_CAM_V_SYNC, ESP_NOSIG) + +/* LCD_CAM_V_SYNC_LCD */ +#define LCD_CAM_V_SYNC_LCD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_V_SYNC) + +#define LCD_CAM_V_SYNC_LCD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_V_SYNC) /* LEDC_CH0 */ -#define LEDC_CH0_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +#define LEDC_CH0_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) + +/* LEDC_CH1 */ +#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +/* LEDC_CH2 */ +#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +/* LEDC_CH3 */ +#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +/* LEDC_CH4 */ +#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +/* LEDC_CH5 */ +#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +/* LEDC_CH6 */ +#define LEDC_CH6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +/* LEDC_CH7 */ +#define LEDC_CH7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +/* MCPWM0_CAP0 */ +#define MCPWM0_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +/* MCPWM0_CAP1 */ +#define MCPWM0_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +/* MCPWM0_CAP2 */ +#define MCPWM0_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +/* MCPWM0_FAULT0 */ +#define MCPWM0_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F0_IN, ESP_NOSIG) + +/* MCPWM0_FAULT1 */ +#define MCPWM0_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F1_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +/* MCPWM0_FAULT2 */ +#define MCPWM0_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH0_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define MCPWM0_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F2_IN, ESP_NOSIG) -/* LEDC_CH1 */ -#define LEDC_CH1_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_FAULT2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F2_IN, ESP_NOSIG) -#define LEDC_CH1_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +/* MCPWM0_OUT0A */ +#define MCPWM0_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH1_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define MCPWM0_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0A) -/* LEDC_CH2 */ -#define LEDC_CH2_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0A) -#define LEDC_CH2_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +/* MCPWM0_OUT0B */ +#define MCPWM0_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH2_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define MCPWM0_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0B) -/* LEDC_CH3 */ -#define LEDC_CH3_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT0B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0B) -#define LEDC_CH3_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +/* MCPWM0_OUT1A */ +#define MCPWM0_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH3_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define MCPWM0_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1A) -/* LEDC_CH4 */ -#define LEDC_CH4_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1A) -#define LEDC_CH4_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +/* MCPWM0_OUT1B */ +#define MCPWM0_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH4_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define MCPWM0_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1B) -/* LEDC_CH5 */ -#define LEDC_CH5_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT1B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1B) -#define LEDC_CH5_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +/* MCPWM0_OUT2A */ +#define MCPWM0_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH5_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define MCPWM0_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2A) -/* LEDC_CH6 */ -#define LEDC_CH6_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2A) -#define LEDC_CH6_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +/* MCPWM0_OUT2B */ +#define MCPWM0_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH6_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define MCPWM0_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2B) -/* LEDC_CH7 */ -#define LEDC_CH7_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_OUT2B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2B) -#define LEDC_CH7_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +/* MCPWM0_SYNC0 */ +#define MCPWM0_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define LEDC_CH7_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define MCPWM0_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -/* MCPWM0_CAP0 */ -#define MCPWM0_CAP0_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_CAP0_IN, ESP_NOSIG) +/* MCPWM0_SYNC1 */ +#define MCPWM0_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -/* MCPWM0_CAP1 */ -#define MCPWM0_CAP1_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC1_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_CAP1_IN, ESP_NOSIG) +/* MCPWM0_SYNC2 */ +#define MCPWM0_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -/* MCPWM0_CAP2 */ -#define MCPWM0_CAP2_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM0_SYNC2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC2_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_CAP2_IN, ESP_NOSIG) +/* MCPWM1_CAP0 */ +#define MCPWM1_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP0_IN, ESP_NOSIG) -/* MCPWM0_FAULT0 */ -#define MCPWM0_FAULT0_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP0_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_F0_IN, ESP_NOSIG) +/* MCPWM1_CAP1 */ +#define MCPWM1_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_F0_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP1_IN, ESP_NOSIG) -/* MCPWM0_FAULT1 */ -#define MCPWM0_FAULT1_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP1_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_F1_IN, ESP_NOSIG) +/* MCPWM1_CAP2 */ +#define MCPWM1_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_F1_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP2_IN, ESP_NOSIG) -/* MCPWM0_FAULT2 */ -#define MCPWM0_FAULT2_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_F2_IN, ESP_NOSIG) +/* MCPWM1_FAULT0 */ +#define MCPWM1_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_F2_IN, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F0_IN, ESP_NOSIG) -/* MCPWM0_OUT0A */ -#define MCPWM0_OUT0A_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F0_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0A) +/* MCPWM1_FAULT1 */ +#define MCPWM1_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0A) +#define MCPWM1_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F1_IN, ESP_NOSIG) -/* MCPWM0_OUT0B */ -#define MCPWM0_OUT0B_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F1_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0B) +/* MCPWM1_FAULT2 */ +#define MCPWM1_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0B) +#define MCPWM1_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F2_IN, ESP_NOSIG) -/* MCPWM0_OUT1A */ -#define MCPWM0_OUT1A_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_FAULT2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F2_IN, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1A) +/* MCPWM1_OUT0A */ +#define MCPWM1_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1A_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1A) +#define MCPWM1_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0A) -/* MCPWM0_OUT1B */ -#define MCPWM0_OUT1B_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0A) -#define MCPWM0_OUT1B_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1B) +/* MCPWM1_OUT0B */ +#define MCPWM1_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT1B_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1B) +#define MCPWM1_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0B) -/* MCPWM0_OUT2A */ -#define MCPWM0_OUT2A_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT0B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0B) -#define MCPWM0_OUT2A_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2A) +/* MCPWM1_OUT1A */ +#define MCPWM1_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2A_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2A) +#define MCPWM1_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1A) -/* MCPWM0_OUT2B */ -#define MCPWM0_OUT2B_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1A) -#define MCPWM0_OUT2B_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2B) +/* MCPWM1_OUT1B */ +#define MCPWM1_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_OUT2B_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2B) +#define MCPWM1_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1B) -/* MCPWM0_SYNC0 */ -#define MCPWM0_SYNC0_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1B) -#define MCPWM0_SYNC0_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +/* MCPWM1_OUT2A */ +#define MCPWM1_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC0_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2A) -/* MCPWM0_SYNC1 */ -#define MCPWM0_SYNC1_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2A) -#define MCPWM0_SYNC1_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +/* MCPWM1_OUT2B */ +#define MCPWM1_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC1_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2B) -/* MCPWM0_SYNC2 */ -#define MCPWM0_SYNC2_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2B) -#define MCPWM0_SYNC2_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +/* MCPWM1_SYNC0 */ +#define MCPWM1_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM0_SYNC2_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -/* MCPWM1_CAP0 */ -#define MCPWM1_CAP0_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_CAP0_IN, ESP_NOSIG) +/* MCPWM1_SYNC1 */ +#define MCPWM1_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP0_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -/* MCPWM1_CAP1 */ -#define MCPWM1_CAP1_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_CAP1_IN, ESP_NOSIG) +/* MCPWM1_SYNC2 */ +#define MCPWM1_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP1_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -/* MCPWM1_CAP2 */ -#define MCPWM1_CAP2_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_CAP2_IN, ESP_NOSIG) +/* PCNT0_CH0CTRL */ +#define PCNT0_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_CAP2_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -/* MCPWM1_FAULT0 */ -#define MCPWM1_FAULT0_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_F0_IN, ESP_NOSIG) +/* PCNT0_CH0SIG */ +#define PCNT0_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT0_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_F0_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -/* MCPWM1_FAULT1 */ -#define MCPWM1_FAULT1_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_F1_IN, ESP_NOSIG) +/* PCNT0_CH1CTRL */ +#define PCNT0_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT1_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_F1_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -/* MCPWM1_FAULT2 */ -#define MCPWM1_FAULT2_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_F2_IN, ESP_NOSIG) +/* PCNT0_CH1SIG */ +#define PCNT0_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_FAULT2_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_F2_IN, ESP_NOSIG) +#define PCNT0_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -/* MCPWM1_OUT0A */ -#define MCPWM1_OUT0A_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT0_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0A) +/* PCNT1_CH0CTRL */ +#define PCNT1_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0A_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0A) +#define PCNT1_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -/* MCPWM1_OUT0B */ -#define MCPWM1_OUT0B_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0B) +/* PCNT1_CH0SIG */ +#define PCNT1_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT0B_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0B) +#define PCNT1_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -/* MCPWM1_OUT1A */ -#define MCPWM1_OUT1A_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1A) +/* PCNT1_CH1CTRL */ +#define PCNT1_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1A_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1A) +#define PCNT1_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -/* MCPWM1_OUT1B */ -#define MCPWM1_OUT1B_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1B) +/* PCNT1_CH1SIG */ +#define PCNT1_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT1B_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1B) +#define PCNT1_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -/* MCPWM1_OUT2A */ -#define MCPWM1_OUT2A_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT1_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2A) +/* PCNT2_CH0CTRL */ +#define PCNT2_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2A_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2A) +#define PCNT2_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -/* MCPWM1_OUT2B */ -#define MCPWM1_OUT2B_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2B) +/* PCNT2_CH0SIG */ +#define PCNT2_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_OUT2B_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2B) +#define PCNT2_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -/* MCPWM1_SYNC0 */ -#define MCPWM1_SYNC0_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +/* PCNT2_CH1CTRL */ +#define PCNT2_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -/* MCPWM1_SYNC1 */ -#define MCPWM1_SYNC1_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +/* PCNT2_CH1SIG */ +#define PCNT2_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC1_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -/* MCPWM1_SYNC2 */ -#define MCPWM1_SYNC2_GPIO0 \ - ESP32_PINMUX(0, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO1 \ - ESP32_PINMUX(1, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO2 \ - ESP32_PINMUX(2, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO3 \ - ESP32_PINMUX(3, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO4 \ - ESP32_PINMUX(4, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO5 \ - ESP32_PINMUX(5, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO6 \ - ESP32_PINMUX(6, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO7 \ - ESP32_PINMUX(7, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO8 \ - ESP32_PINMUX(8, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO9 \ - ESP32_PINMUX(9, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO10 \ - ESP32_PINMUX(10, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO11 \ - ESP32_PINMUX(11, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO12 \ - ESP32_PINMUX(12, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO13 \ - ESP32_PINMUX(13, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO14 \ - ESP32_PINMUX(14, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO15 \ - ESP32_PINMUX(15, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO16 \ - ESP32_PINMUX(16, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO17 \ - ESP32_PINMUX(17, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO18 \ - ESP32_PINMUX(18, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO19 \ - ESP32_PINMUX(19, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO20 \ - ESP32_PINMUX(20, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO21 \ - ESP32_PINMUX(21, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO26 \ - ESP32_PINMUX(26, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO27 \ - ESP32_PINMUX(27, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO28 \ - ESP32_PINMUX(28, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO29 \ - ESP32_PINMUX(29, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO30 \ - ESP32_PINMUX(30, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT2_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO31 \ - ESP32_PINMUX(31, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +/* PCNT3_CH0CTRL */ +#define PCNT3_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO32 \ - ESP32_PINMUX(32, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO33 \ - ESP32_PINMUX(33, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO34 \ - ESP32_PINMUX(34, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO35 \ - ESP32_PINMUX(35, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO36 \ - ESP32_PINMUX(36, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO37 \ - ESP32_PINMUX(37, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO38 \ - ESP32_PINMUX(38, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO39 \ - ESP32_PINMUX(39, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO40 \ - ESP32_PINMUX(40, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO41 \ - ESP32_PINMUX(41, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO42 \ - ESP32_PINMUX(42, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO43 \ - ESP32_PINMUX(43, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO44 \ - ESP32_PINMUX(44, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO45 \ - ESP32_PINMUX(45, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO46 \ - ESP32_PINMUX(46, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO47 \ - ESP32_PINMUX(47, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO48 \ - ESP32_PINMUX(48, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -/* PCNT0_CH0CTRL */ -#define PCNT0_CH0CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +/* PCNT3_CH0SIG */ +#define PCNT3_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -/* PCNT0_CH0SIG */ -#define PCNT0_CH0SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +/* PCNT3_CH1CTRL */ +#define PCNT3_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH0SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -/* PCNT0_CH1CTRL */ -#define PCNT0_CH1CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +/* PCNT3_CH1SIG */ +#define PCNT3_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -/* PCNT0_CH1SIG */ -#define PCNT0_CH1SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +/* SDHC0_CD */ +#define SDHC0_CD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT0_CH1SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define SDHC0_CD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -/* PCNT1_CH0CTRL */ -#define PCNT1_CH0CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define PCNT1_CH0CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +/* SDHC0_CLKOUT */ +#define SDHC0_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -/* PCNT1_CH0SIG */ -#define PCNT1_CH0SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define PCNT1_CH0SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +/* SDHC0_CMD */ +#define SDHC0_CMD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH0SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -/* PCNT1_CH1CTRL */ -#define PCNT1_CH1CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_CMD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define PCNT1_CH1CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +/* SDHC0_DATA0 */ +#define SDHC0_DATA0_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -/* PCNT1_CH1SIG */ -#define PCNT1_CH1SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA0_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define PCNT1_CH1SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +/* SDHC0_DATA1 */ +#define SDHC0_DATA1_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT1_CH1SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define SDHC0_DATA1_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -/* PCNT2_CH0CTRL */ -#define PCNT2_CH0CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA1_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define PCNT2_CH0CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +/* SDHC0_DATA2 */ +#define SDHC0_DATA2_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define SDHC0_DATA2_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -/* PCNT2_CH0SIG */ -#define PCNT2_CH0SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA2_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define PCNT2_CH0SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +/* SDHC0_DATA3 */ +#define SDHC0_DATA3_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH0SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC0_DATA3_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -/* PCNT2_CH1CTRL */ -#define PCNT2_CH1CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_DATA3_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define PCNT2_CH1CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +/* SDHC0_WP */ +#define SDHC0_WP_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -/* PCNT2_CH1SIG */ -#define PCNT2_CH1SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC0_WP_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +/* SDHC1_CD */ +#define SDHC1_CD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT2_CH1SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define SDHC1_CD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -/* PCNT3_CH0CTRL */ -#define PCNT3_CH0CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define PCNT3_CH0CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +/* SDHC1_CLKOUT */ +#define SDHC1_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -/* PCNT3_CH0SIG */ -#define PCNT3_CH0SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define PCNT3_CH0SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +/* SDHC1_CMD */ +#define SDHC1_CMD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH0SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -/* PCNT3_CH1CTRL */ -#define PCNT3_CH1CTRL_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_CMD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define PCNT3_CH1CTRL_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +/* SDHC1_DATA0 */ +#define SDHC1_DATA0_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define PCNT3_CH1CTRL_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -/* PCNT3_CH1SIG */ -#define PCNT3_CH1SIG_GPIO0 \ - ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_DATA0_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +#define SDHC1_DATA0_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) + +/* SDHC1_DATA1 */ +#define SDHC1_DATA1_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +#define SDHC1_DATA1_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) + +/* SDHC1_DATA2 */ +#define SDHC1_DATA2_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +#define SDHC1_DATA2_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) + +/* SDHC1_DATA3 */ +#define SDHC1_DATA3_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +#define SDHC1_DATA3_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) + +/* SDHC1_WP */ +#define SDHC1_WP_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO1 \ - ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO2 \ - ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO3 \ - ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO4 \ - ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO5 \ - ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO6 \ - ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO7 \ - ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO8 \ - ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO9 \ - ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO10 \ - ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO11 \ - ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO12 \ - ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO13 \ - ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO14 \ - ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO15 \ - ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO16 \ - ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO17 \ - ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO18 \ - ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO19 \ - ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO20 \ - ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO21 \ - ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO26 \ - ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO27 \ - ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO28 \ - ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO29 \ - ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO30 \ - ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO31 \ - ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO32 \ - ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO33 \ - ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO34 \ - ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO35 \ - ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO36 \ - ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO37 \ - ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO38 \ - ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO39 \ - ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO40 \ - ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO41 \ - ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO42 \ - ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO43 \ - ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO44 \ - ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO45 \ - ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO46 \ - ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO47 \ - ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO48 \ - ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define SDHC1_WP_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) /* SPIM2_CSEL */ -#define SPIM2_CSEL_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS0_OUT) -#define SPIM2_CSEL_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS0_OUT) +#define SPIM2_CSEL_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS0_OUT) /* SPIM2_CSEL1 */ -#define SPIM2_CSEL1_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS1_OUT) -#define SPIM2_CSEL1_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS1_OUT) +#define SPIM2_CSEL1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS1_OUT) /* SPIM2_CSEL2 */ -#define SPIM2_CSEL2_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS2_OUT) -#define SPIM2_CSEL2_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS2_OUT) +#define SPIM2_CSEL2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS2_OUT) /* SPIM2_CSEL3 */ -#define SPIM2_CSEL3_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS3_OUT) -#define SPIM2_CSEL3_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS3_OUT) +#define SPIM2_CSEL3_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS3_OUT) /* SPIM2_CSEL4 */ -#define SPIM2_CSEL4_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS4_OUT) -#define SPIM2_CSEL4_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS4_OUT) +#define SPIM2_CSEL4_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS4_OUT) /* SPIM2_CSEL5 */ -#define SPIM2_CSEL5_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICS5_OUT) -#define SPIM2_CSEL5_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS5_OUT) +#define SPIM2_CSEL5_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICS5_OUT) /* SPIM2_MISO */ -#define SPIM2_MISO_GPIO0 \ - ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO0 ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO1 \ - ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO1 ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO2 \ - ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO2 ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO3 \ - ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO3 ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO4 \ - ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO4 ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO5 \ - ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO5 ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO6 \ - ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO6 ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO7 \ - ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO7 ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO8 \ - ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO8 ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO9 \ - ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO9 ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO10 \ - ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO10 ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO11 \ - ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO11 ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO12 \ - ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO12 ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO13 \ - ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO13 ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO14 \ - ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO14 ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO15 \ - ESP32_PINMUX(15, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO15 ESP32_PINMUX(15, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO16 \ - ESP32_PINMUX(16, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO16 ESP32_PINMUX(16, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO17 \ - ESP32_PINMUX(17, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO17 ESP32_PINMUX(17, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO18 \ - ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO18 ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO19 \ - ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO19 ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO20 \ - ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO20 ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO21 \ - ESP32_PINMUX(21, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO21 ESP32_PINMUX(21, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO26 \ - ESP32_PINMUX(26, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO26 ESP32_PINMUX(26, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO27 \ - ESP32_PINMUX(27, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO27 ESP32_PINMUX(27, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO28 \ - ESP32_PINMUX(28, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO28 ESP32_PINMUX(28, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO29 \ - ESP32_PINMUX(29, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO29 ESP32_PINMUX(29, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO30 \ - ESP32_PINMUX(30, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO30 ESP32_PINMUX(30, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO31 \ - ESP32_PINMUX(31, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO31 ESP32_PINMUX(31, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO32 \ - ESP32_PINMUX(32, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO32 ESP32_PINMUX(32, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO33 \ - ESP32_PINMUX(33, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO33 ESP32_PINMUX(33, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO34 \ - ESP32_PINMUX(34, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO34 ESP32_PINMUX(34, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO35 \ - ESP32_PINMUX(35, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO35 ESP32_PINMUX(35, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO36 \ - ESP32_PINMUX(36, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO36 ESP32_PINMUX(36, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO37 \ - ESP32_PINMUX(37, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO37 ESP32_PINMUX(37, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO38 \ - ESP32_PINMUX(38, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO38 ESP32_PINMUX(38, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO39 \ - ESP32_PINMUX(39, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO39 ESP32_PINMUX(39, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO40 \ - ESP32_PINMUX(40, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO40 ESP32_PINMUX(40, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO41 \ - ESP32_PINMUX(41, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO41 ESP32_PINMUX(41, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO42 \ - ESP32_PINMUX(42, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO42 ESP32_PINMUX(42, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO43 \ - ESP32_PINMUX(43, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO43 ESP32_PINMUX(43, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO44 \ - ESP32_PINMUX(44, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO44 ESP32_PINMUX(44, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO45 \ - ESP32_PINMUX(45, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO45 ESP32_PINMUX(45, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO46 \ - ESP32_PINMUX(46, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO46 ESP32_PINMUX(46, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO47 \ - ESP32_PINMUX(47, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO47 ESP32_PINMUX(47, ESP_FSPIQ_IN, ESP_NOSIG) -#define SPIM2_MISO_GPIO48 \ - ESP32_PINMUX(48, ESP_FSPIQ_IN, ESP_NOSIG) +#define SPIM2_MISO_GPIO48 ESP32_PINMUX(48, ESP_FSPIQ_IN, ESP_NOSIG) /* SPIM2_MOSI */ -#define SPIM2_MOSI_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPID_OUT) -#define SPIM2_MOSI_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPID_OUT) +#define SPIM2_MOSI_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPID_OUT) /* SPIM2_SCLK */ -#define SPIM2_SCLK_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_FSPICLK_OUT) -#define SPIM2_SCLK_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICLK_OUT) +#define SPIM2_SCLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_FSPICLK_OUT) /* SPIM3_CSEL */ -#define SPIM3_CSEL_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CS0_OUT) -#define SPIM3_CSEL_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CS0_OUT) +#define SPIM3_CSEL_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CS0_OUT) /* SPIM3_CSEL1 */ -#define SPIM3_CSEL1_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CS1_OUT) -#define SPIM3_CSEL1_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CS1_OUT) +#define SPIM3_CSEL1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CS1_OUT) /* SPIM3_CSEL2 */ -#define SPIM3_CSEL2_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CS2_OUT) -#define SPIM3_CSEL2_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CS2_OUT) +#define SPIM3_CSEL2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CS2_OUT) /* SPIM3_MISO */ -#define SPIM3_MISO_GPIO0 \ - ESP32_PINMUX(0, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO0 ESP32_PINMUX(0, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO1 \ - ESP32_PINMUX(1, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO1 ESP32_PINMUX(1, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO2 \ - ESP32_PINMUX(2, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO2 ESP32_PINMUX(2, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO3 \ - ESP32_PINMUX(3, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO3 ESP32_PINMUX(3, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO4 \ - ESP32_PINMUX(4, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO4 ESP32_PINMUX(4, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO5 \ - ESP32_PINMUX(5, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO5 ESP32_PINMUX(5, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO6 \ - ESP32_PINMUX(6, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO6 ESP32_PINMUX(6, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO7 \ - ESP32_PINMUX(7, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO7 ESP32_PINMUX(7, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO8 \ - ESP32_PINMUX(8, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO8 ESP32_PINMUX(8, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO9 \ - ESP32_PINMUX(9, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO9 ESP32_PINMUX(9, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO10 \ - ESP32_PINMUX(10, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO10 ESP32_PINMUX(10, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO11 \ - ESP32_PINMUX(11, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO11 ESP32_PINMUX(11, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO12 \ - ESP32_PINMUX(12, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO12 ESP32_PINMUX(12, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO13 \ - ESP32_PINMUX(13, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO13 ESP32_PINMUX(13, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO14 \ - ESP32_PINMUX(14, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO14 ESP32_PINMUX(14, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO15 \ - ESP32_PINMUX(15, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO15 ESP32_PINMUX(15, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO16 \ - ESP32_PINMUX(16, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO16 ESP32_PINMUX(16, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO17 \ - ESP32_PINMUX(17, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO17 ESP32_PINMUX(17, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO18 \ - ESP32_PINMUX(18, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO18 ESP32_PINMUX(18, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO19 \ - ESP32_PINMUX(19, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO19 ESP32_PINMUX(19, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO20 \ - ESP32_PINMUX(20, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO20 ESP32_PINMUX(20, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO21 \ - ESP32_PINMUX(21, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO21 ESP32_PINMUX(21, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO26 \ - ESP32_PINMUX(26, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO26 ESP32_PINMUX(26, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO27 \ - ESP32_PINMUX(27, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO27 ESP32_PINMUX(27, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO28 \ - ESP32_PINMUX(28, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO28 ESP32_PINMUX(28, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO29 \ - ESP32_PINMUX(29, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO29 ESP32_PINMUX(29, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO30 \ - ESP32_PINMUX(30, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO30 ESP32_PINMUX(30, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO31 \ - ESP32_PINMUX(31, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO31 ESP32_PINMUX(31, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO32 \ - ESP32_PINMUX(32, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO32 ESP32_PINMUX(32, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO33 \ - ESP32_PINMUX(33, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO33 ESP32_PINMUX(33, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO34 \ - ESP32_PINMUX(34, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO34 ESP32_PINMUX(34, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO35 \ - ESP32_PINMUX(35, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO35 ESP32_PINMUX(35, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO36 \ - ESP32_PINMUX(36, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO36 ESP32_PINMUX(36, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO37 \ - ESP32_PINMUX(37, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO37 ESP32_PINMUX(37, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO38 \ - ESP32_PINMUX(38, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO38 ESP32_PINMUX(38, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO39 \ - ESP32_PINMUX(39, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO39 ESP32_PINMUX(39, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO40 \ - ESP32_PINMUX(40, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO40 ESP32_PINMUX(40, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO41 \ - ESP32_PINMUX(41, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO41 ESP32_PINMUX(41, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO42 \ - ESP32_PINMUX(42, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO42 ESP32_PINMUX(42, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO43 \ - ESP32_PINMUX(43, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO43 ESP32_PINMUX(43, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO44 \ - ESP32_PINMUX(44, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO44 ESP32_PINMUX(44, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO45 \ - ESP32_PINMUX(45, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO45 ESP32_PINMUX(45, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO46 \ - ESP32_PINMUX(46, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO46 ESP32_PINMUX(46, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO47 \ - ESP32_PINMUX(47, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO47 ESP32_PINMUX(47, ESP_SPI3_Q_IN, ESP_NOSIG) -#define SPIM3_MISO_GPIO48 \ - ESP32_PINMUX(48, ESP_SPI3_Q_IN, ESP_NOSIG) +#define SPIM3_MISO_GPIO48 ESP32_PINMUX(48, ESP_SPI3_Q_IN, ESP_NOSIG) /* SPIM3_MOSI */ -#define SPIM3_MOSI_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_D_OUT) -#define SPIM3_MOSI_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_D_OUT) +#define SPIM3_MOSI_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_D_OUT) /* SPIM3_SCLK */ -#define SPIM3_SCLK_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SPI3_CLK_OUT) -#define SPIM3_SCLK_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CLK_OUT) +#define SPIM3_SCLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SPI3_CLK_OUT) /* TWAI_BUS_OFF */ -#define TWAI_BUS_OFF_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) -#define TWAI_BUS_OFF_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) +#define TWAI_BUS_OFF_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON) /* TWAI_CLKOUT */ -#define TWAI_CLKOUT_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_TWAI_CLKOUT) -#define TWAI_CLKOUT_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_TWAI_CLKOUT) +#define TWAI_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_TWAI_CLKOUT) /* TWAI_RX */ -#define TWAI_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO0 ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO1 ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO2 ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO3 ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO4 ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO5 ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO6 ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO7 ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO8 ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO9 ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO10 ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO11 ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO12 ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO13 ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO14 ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO15 ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO16 ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO17 ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO18 ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO19 ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO20 ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO21 ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO26 \ - ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO26 ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO27 \ - ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO27 ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO28 \ - ESP32_PINMUX(28, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO28 ESP32_PINMUX(28, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO29 \ - ESP32_PINMUX(29, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO29 ESP32_PINMUX(29, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO30 \ - ESP32_PINMUX(30, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO30 ESP32_PINMUX(30, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO31 \ - ESP32_PINMUX(31, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO31 ESP32_PINMUX(31, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO32 \ - ESP32_PINMUX(32, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO32 ESP32_PINMUX(32, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO33 \ - ESP32_PINMUX(33, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO33 ESP32_PINMUX(33, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO34 \ - ESP32_PINMUX(34, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO34 ESP32_PINMUX(34, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO35 \ - ESP32_PINMUX(35, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO35 ESP32_PINMUX(35, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO36 \ - ESP32_PINMUX(36, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO36 ESP32_PINMUX(36, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO37 \ - ESP32_PINMUX(37, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO37 ESP32_PINMUX(37, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO38 \ - ESP32_PINMUX(38, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO38 ESP32_PINMUX(38, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO39 \ - ESP32_PINMUX(39, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO39 ESP32_PINMUX(39, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO40 \ - ESP32_PINMUX(40, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO40 ESP32_PINMUX(40, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO41 \ - ESP32_PINMUX(41, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO41 ESP32_PINMUX(41, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO42 \ - ESP32_PINMUX(42, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO42 ESP32_PINMUX(42, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO43 \ - ESP32_PINMUX(43, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO43 ESP32_PINMUX(43, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO44 \ - ESP32_PINMUX(44, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO44 ESP32_PINMUX(44, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO45 \ - ESP32_PINMUX(45, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO45 ESP32_PINMUX(45, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO46 \ - ESP32_PINMUX(46, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO46 ESP32_PINMUX(46, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO47 \ - ESP32_PINMUX(47, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO47 ESP32_PINMUX(47, ESP_TWAI_RX, ESP_NOSIG) -#define TWAI_RX_GPIO48 \ - ESP32_PINMUX(48, ESP_TWAI_RX, ESP_NOSIG) +#define TWAI_RX_GPIO48 ESP32_PINMUX(48, ESP_TWAI_RX, ESP_NOSIG) /* TWAI_TX */ -#define TWAI_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_TWAI_TX) -#define TWAI_TX_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_TWAI_TX) +#define TWAI_TX_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_TWAI_TX) /* UART0_CTS */ -#define UART0_CTS_GPIO0 \ - ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO0 ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO1 \ - ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO1 ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO2 \ - ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO2 ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO3 \ - ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO3 ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO4 \ - ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO4 ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO5 \ - ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO5 ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO6 \ - ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO6 ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO7 \ - ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO7 ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO8 \ - ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO8 ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO9 \ - ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO9 ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO10 \ - ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO10 ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO11 \ - ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO11 ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO12 \ - ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO12 ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO13 \ - ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO13 ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO14 \ - ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO14 ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO15 \ - ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO15 ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO16 \ - ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO16 ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO17 \ - ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO17 ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO18 \ - ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO18 ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO19 \ - ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO19 ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO20 \ - ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO20 ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO21 \ - ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO21 ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO26 \ - ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO26 ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO27 \ - ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO27 ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO28 \ - ESP32_PINMUX(28, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO28 ESP32_PINMUX(28, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO29 \ - ESP32_PINMUX(29, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO29 ESP32_PINMUX(29, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO30 \ - ESP32_PINMUX(30, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO30 ESP32_PINMUX(30, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO31 \ - ESP32_PINMUX(31, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO31 ESP32_PINMUX(31, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO32 \ - ESP32_PINMUX(32, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO32 ESP32_PINMUX(32, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO33 \ - ESP32_PINMUX(33, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO33 ESP32_PINMUX(33, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO34 \ - ESP32_PINMUX(34, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO34 ESP32_PINMUX(34, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO35 \ - ESP32_PINMUX(35, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO35 ESP32_PINMUX(35, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO36 \ - ESP32_PINMUX(36, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO36 ESP32_PINMUX(36, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO37 \ - ESP32_PINMUX(37, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO37 ESP32_PINMUX(37, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO38 \ - ESP32_PINMUX(38, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO38 ESP32_PINMUX(38, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO39 \ - ESP32_PINMUX(39, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO39 ESP32_PINMUX(39, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO40 \ - ESP32_PINMUX(40, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO40 ESP32_PINMUX(40, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO41 \ - ESP32_PINMUX(41, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO41 ESP32_PINMUX(41, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO42 \ - ESP32_PINMUX(42, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO42 ESP32_PINMUX(42, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO43 \ - ESP32_PINMUX(43, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO43 ESP32_PINMUX(43, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO44 \ - ESP32_PINMUX(44, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO44 ESP32_PINMUX(44, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO45 \ - ESP32_PINMUX(45, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO45 ESP32_PINMUX(45, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO46 \ - ESP32_PINMUX(46, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO46 ESP32_PINMUX(46, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO47 \ - ESP32_PINMUX(47, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO47 ESP32_PINMUX(47, ESP_U0CTS_IN, ESP_NOSIG) -#define UART0_CTS_GPIO48 \ - ESP32_PINMUX(48, ESP_U0CTS_IN, ESP_NOSIG) +#define UART0_CTS_GPIO48 ESP32_PINMUX(48, ESP_U0CTS_IN, ESP_NOSIG) /* UART0_DSR */ -#define UART0_DSR_GPIO0 \ - ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO0 ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO1 \ - ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO1 ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO2 \ - ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO2 ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO3 \ - ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO3 ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO4 \ - ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO4 ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO5 \ - ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO5 ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO6 \ - ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO6 ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO7 \ - ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO7 ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO8 \ - ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO8 ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO9 \ - ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO9 ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO10 \ - ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO10 ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO11 \ - ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO11 ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO12 \ - ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO12 ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO13 \ - ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO13 ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO14 \ - ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO14 ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO15 \ - ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO15 ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO16 \ - ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO16 ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO17 \ - ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO17 ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO18 \ - ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO18 ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO19 \ - ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO19 ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO20 \ - ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO20 ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO21 \ - ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO21 ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO26 \ - ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO26 ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO27 \ - ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO27 ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO28 \ - ESP32_PINMUX(28, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO28 ESP32_PINMUX(28, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO29 \ - ESP32_PINMUX(29, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO29 ESP32_PINMUX(29, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO30 \ - ESP32_PINMUX(30, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO30 ESP32_PINMUX(30, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO31 \ - ESP32_PINMUX(31, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO31 ESP32_PINMUX(31, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO32 \ - ESP32_PINMUX(32, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO32 ESP32_PINMUX(32, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO33 \ - ESP32_PINMUX(33, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO33 ESP32_PINMUX(33, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO34 \ - ESP32_PINMUX(34, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO34 ESP32_PINMUX(34, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO35 \ - ESP32_PINMUX(35, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO35 ESP32_PINMUX(35, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO36 \ - ESP32_PINMUX(36, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO36 ESP32_PINMUX(36, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO37 \ - ESP32_PINMUX(37, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO37 ESP32_PINMUX(37, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO38 \ - ESP32_PINMUX(38, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO38 ESP32_PINMUX(38, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO39 \ - ESP32_PINMUX(39, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO39 ESP32_PINMUX(39, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO40 \ - ESP32_PINMUX(40, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO40 ESP32_PINMUX(40, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO41 \ - ESP32_PINMUX(41, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO41 ESP32_PINMUX(41, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO42 \ - ESP32_PINMUX(42, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO42 ESP32_PINMUX(42, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO43 \ - ESP32_PINMUX(43, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO43 ESP32_PINMUX(43, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO44 \ - ESP32_PINMUX(44, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO44 ESP32_PINMUX(44, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO45 \ - ESP32_PINMUX(45, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO45 ESP32_PINMUX(45, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO46 \ - ESP32_PINMUX(46, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO46 ESP32_PINMUX(46, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO47 \ - ESP32_PINMUX(47, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO47 ESP32_PINMUX(47, ESP_U0DSR_IN, ESP_NOSIG) -#define UART0_DSR_GPIO48 \ - ESP32_PINMUX(48, ESP_U0DSR_IN, ESP_NOSIG) +#define UART0_DSR_GPIO48 ESP32_PINMUX(48, ESP_U0DSR_IN, ESP_NOSIG) /* UART0_DTR */ -#define UART0_DTR_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U0DTR_OUT) -#define UART0_DTR_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U0DTR_OUT) +#define UART0_DTR_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U0DTR_OUT) /* UART0_RTS */ -#define UART0_RTS_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U0RTS_OUT) -#define UART0_RTS_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U0RTS_OUT) +#define UART0_RTS_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U0RTS_OUT) /* UART0_RX */ -#define UART0_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO0 ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO1 ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO2 ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO3 ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO4 ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO5 ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO6 ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO7 ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO8 ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO9 ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO10 ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO11 ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO12 ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO13 ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO14 ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO15 ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO16 ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO17 ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO18 ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO19 ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO20 ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO21 ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO26 \ - ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO26 ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO27 \ - ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO27 ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO28 \ - ESP32_PINMUX(28, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO28 ESP32_PINMUX(28, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO29 \ - ESP32_PINMUX(29, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO29 ESP32_PINMUX(29, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO30 \ - ESP32_PINMUX(30, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO30 ESP32_PINMUX(30, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO31 \ - ESP32_PINMUX(31, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO31 ESP32_PINMUX(31, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO32 \ - ESP32_PINMUX(32, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO32 ESP32_PINMUX(32, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO33 \ - ESP32_PINMUX(33, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO33 ESP32_PINMUX(33, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO34 \ - ESP32_PINMUX(34, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO34 ESP32_PINMUX(34, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO35 \ - ESP32_PINMUX(35, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO35 ESP32_PINMUX(35, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO36 \ - ESP32_PINMUX(36, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO36 ESP32_PINMUX(36, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO37 \ - ESP32_PINMUX(37, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO37 ESP32_PINMUX(37, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO38 \ - ESP32_PINMUX(38, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO38 ESP32_PINMUX(38, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO39 \ - ESP32_PINMUX(39, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO39 ESP32_PINMUX(39, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO40 \ - ESP32_PINMUX(40, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO40 ESP32_PINMUX(40, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO41 \ - ESP32_PINMUX(41, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO41 ESP32_PINMUX(41, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO42 \ - ESP32_PINMUX(42, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO42 ESP32_PINMUX(42, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO43 \ - ESP32_PINMUX(43, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO43 ESP32_PINMUX(43, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO44 \ - ESP32_PINMUX(44, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO44 ESP32_PINMUX(44, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO45 \ - ESP32_PINMUX(45, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO45 ESP32_PINMUX(45, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO46 \ - ESP32_PINMUX(46, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO46 ESP32_PINMUX(46, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO47 \ - ESP32_PINMUX(47, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO47 ESP32_PINMUX(47, ESP_U0RXD_IN, ESP_NOSIG) -#define UART0_RX_GPIO48 \ - ESP32_PINMUX(48, ESP_U0RXD_IN, ESP_NOSIG) +#define UART0_RX_GPIO48 ESP32_PINMUX(48, ESP_U0RXD_IN, ESP_NOSIG) /* UART0_TX */ -#define UART0_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U0TXD_OUT) -#define UART0_TX_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U0TXD_OUT) +#define UART0_TX_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U0TXD_OUT) /* UART1_CTS */ -#define UART1_CTS_GPIO0 \ - ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO0 ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO1 \ - ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO1 ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO2 \ - ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO2 ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO3 \ - ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO3 ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO4 \ - ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO4 ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO5 \ - ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO5 ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO6 \ - ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO6 ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO7 \ - ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO7 ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO8 \ - ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO8 ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO9 \ - ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO9 ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO10 \ - ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO10 ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO11 \ - ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO11 ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO12 \ - ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO12 ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO13 \ - ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO13 ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO14 \ - ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO14 ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO15 \ - ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO15 ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO16 \ - ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO16 ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO17 \ - ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO17 ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO18 \ - ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO18 ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO19 \ - ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO19 ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO20 \ - ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO20 ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO21 \ - ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO21 ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO26 \ - ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO26 ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO27 \ - ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO27 ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO28 \ - ESP32_PINMUX(28, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO28 ESP32_PINMUX(28, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO29 \ - ESP32_PINMUX(29, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO29 ESP32_PINMUX(29, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO30 \ - ESP32_PINMUX(30, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO30 ESP32_PINMUX(30, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO31 \ - ESP32_PINMUX(31, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO31 ESP32_PINMUX(31, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO32 \ - ESP32_PINMUX(32, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO32 ESP32_PINMUX(32, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO33 \ - ESP32_PINMUX(33, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO33 ESP32_PINMUX(33, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO34 \ - ESP32_PINMUX(34, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO34 ESP32_PINMUX(34, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO35 \ - ESP32_PINMUX(35, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO35 ESP32_PINMUX(35, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO36 \ - ESP32_PINMUX(36, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO36 ESP32_PINMUX(36, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO37 \ - ESP32_PINMUX(37, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO37 ESP32_PINMUX(37, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO38 \ - ESP32_PINMUX(38, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO38 ESP32_PINMUX(38, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO39 \ - ESP32_PINMUX(39, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO39 ESP32_PINMUX(39, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO40 \ - ESP32_PINMUX(40, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO40 ESP32_PINMUX(40, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO41 \ - ESP32_PINMUX(41, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO41 ESP32_PINMUX(41, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO42 \ - ESP32_PINMUX(42, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO42 ESP32_PINMUX(42, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO43 \ - ESP32_PINMUX(43, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO43 ESP32_PINMUX(43, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO44 \ - ESP32_PINMUX(44, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO44 ESP32_PINMUX(44, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO45 \ - ESP32_PINMUX(45, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO45 ESP32_PINMUX(45, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO46 \ - ESP32_PINMUX(46, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO46 ESP32_PINMUX(46, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO47 \ - ESP32_PINMUX(47, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO47 ESP32_PINMUX(47, ESP_U1CTS_IN, ESP_NOSIG) -#define UART1_CTS_GPIO48 \ - ESP32_PINMUX(48, ESP_U1CTS_IN, ESP_NOSIG) +#define UART1_CTS_GPIO48 ESP32_PINMUX(48, ESP_U1CTS_IN, ESP_NOSIG) /* UART1_DSR */ -#define UART1_DSR_GPIO0 \ - ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO0 ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO1 \ - ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO1 ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO2 \ - ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO2 ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO3 \ - ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO3 ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO4 \ - ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO4 ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO5 \ - ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO5 ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO6 \ - ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO6 ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO7 \ - ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO7 ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO8 \ - ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO8 ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO9 \ - ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO9 ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO10 \ - ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO10 ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO11 \ - ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO11 ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO12 \ - ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO12 ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO13 \ - ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO13 ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO14 \ - ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO14 ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO15 \ - ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO15 ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO16 \ - ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO16 ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO17 \ - ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO17 ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO18 \ - ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO18 ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO19 \ - ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO19 ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO20 \ - ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO20 ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO21 \ - ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO21 ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO26 \ - ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO26 ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO27 \ - ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO27 ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO28 \ - ESP32_PINMUX(28, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO28 ESP32_PINMUX(28, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO29 \ - ESP32_PINMUX(29, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO29 ESP32_PINMUX(29, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO30 \ - ESP32_PINMUX(30, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO30 ESP32_PINMUX(30, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO31 \ - ESP32_PINMUX(31, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO31 ESP32_PINMUX(31, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO32 \ - ESP32_PINMUX(32, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO32 ESP32_PINMUX(32, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO33 \ - ESP32_PINMUX(33, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO33 ESP32_PINMUX(33, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO34 \ - ESP32_PINMUX(34, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO34 ESP32_PINMUX(34, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO35 \ - ESP32_PINMUX(35, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO35 ESP32_PINMUX(35, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO36 \ - ESP32_PINMUX(36, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO36 ESP32_PINMUX(36, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO37 \ - ESP32_PINMUX(37, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO37 ESP32_PINMUX(37, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO38 \ - ESP32_PINMUX(38, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO38 ESP32_PINMUX(38, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO39 \ - ESP32_PINMUX(39, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO39 ESP32_PINMUX(39, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO40 \ - ESP32_PINMUX(40, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO40 ESP32_PINMUX(40, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO41 \ - ESP32_PINMUX(41, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO41 ESP32_PINMUX(41, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO42 \ - ESP32_PINMUX(42, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO42 ESP32_PINMUX(42, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO43 \ - ESP32_PINMUX(43, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO43 ESP32_PINMUX(43, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO44 \ - ESP32_PINMUX(44, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO44 ESP32_PINMUX(44, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO45 \ - ESP32_PINMUX(45, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO45 ESP32_PINMUX(45, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO46 \ - ESP32_PINMUX(46, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO46 ESP32_PINMUX(46, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO47 \ - ESP32_PINMUX(47, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO47 ESP32_PINMUX(47, ESP_U1DSR_IN, ESP_NOSIG) -#define UART1_DSR_GPIO48 \ - ESP32_PINMUX(48, ESP_U1DSR_IN, ESP_NOSIG) +#define UART1_DSR_GPIO48 ESP32_PINMUX(48, ESP_U1DSR_IN, ESP_NOSIG) /* UART1_DTR */ -#define UART1_DTR_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U1DTR_OUT) -#define UART1_DTR_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U1DTR_OUT) +#define UART1_DTR_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U1DTR_OUT) /* UART1_RTS */ -#define UART1_RTS_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U1RTS_OUT) -#define UART1_RTS_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U1RTS_OUT) +#define UART1_RTS_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U1RTS_OUT) /* UART1_RX */ -#define UART1_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO0 ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO1 ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO2 ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO3 ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO4 ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO5 ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO6 ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO7 ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO8 ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO9 ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO10 ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO11 ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO12 ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO13 ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO14 ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO15 ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO16 ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO17 ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO18 ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO19 ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO20 ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO21 ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO26 \ - ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO26 ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO27 \ - ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO27 ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO28 \ - ESP32_PINMUX(28, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO28 ESP32_PINMUX(28, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO29 \ - ESP32_PINMUX(29, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO29 ESP32_PINMUX(29, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO30 \ - ESP32_PINMUX(30, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO30 ESP32_PINMUX(30, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO31 \ - ESP32_PINMUX(31, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO31 ESP32_PINMUX(31, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO32 \ - ESP32_PINMUX(32, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO32 ESP32_PINMUX(32, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO33 \ - ESP32_PINMUX(33, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO33 ESP32_PINMUX(33, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO34 \ - ESP32_PINMUX(34, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO34 ESP32_PINMUX(34, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO35 \ - ESP32_PINMUX(35, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO35 ESP32_PINMUX(35, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO36 \ - ESP32_PINMUX(36, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO36 ESP32_PINMUX(36, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO37 \ - ESP32_PINMUX(37, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO37 ESP32_PINMUX(37, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO38 \ - ESP32_PINMUX(38, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO38 ESP32_PINMUX(38, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO39 \ - ESP32_PINMUX(39, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO39 ESP32_PINMUX(39, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO40 \ - ESP32_PINMUX(40, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO40 ESP32_PINMUX(40, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO41 \ - ESP32_PINMUX(41, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO41 ESP32_PINMUX(41, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO42 \ - ESP32_PINMUX(42, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO42 ESP32_PINMUX(42, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO43 \ - ESP32_PINMUX(43, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO43 ESP32_PINMUX(43, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO44 \ - ESP32_PINMUX(44, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO44 ESP32_PINMUX(44, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO45 \ - ESP32_PINMUX(45, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO45 ESP32_PINMUX(45, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO46 \ - ESP32_PINMUX(46, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO46 ESP32_PINMUX(46, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO47 \ - ESP32_PINMUX(47, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO47 ESP32_PINMUX(47, ESP_U1RXD_IN, ESP_NOSIG) -#define UART1_RX_GPIO48 \ - ESP32_PINMUX(48, ESP_U1RXD_IN, ESP_NOSIG) +#define UART1_RX_GPIO48 ESP32_PINMUX(48, ESP_U1RXD_IN, ESP_NOSIG) /* UART1_TX */ -#define UART1_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U1TXD_OUT) -#define UART1_TX_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U1TXD_OUT) +#define UART1_TX_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U1TXD_OUT) /* UART2_CTS */ -#define UART2_CTS_GPIO0 \ - ESP32_PINMUX(0, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO0 ESP32_PINMUX(0, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO1 \ - ESP32_PINMUX(1, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO1 ESP32_PINMUX(1, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO2 \ - ESP32_PINMUX(2, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO2 ESP32_PINMUX(2, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO3 \ - ESP32_PINMUX(3, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO3 ESP32_PINMUX(3, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO4 \ - ESP32_PINMUX(4, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO4 ESP32_PINMUX(4, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO5 \ - ESP32_PINMUX(5, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO5 ESP32_PINMUX(5, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO6 \ - ESP32_PINMUX(6, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO6 ESP32_PINMUX(6, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO7 \ - ESP32_PINMUX(7, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO7 ESP32_PINMUX(7, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO8 \ - ESP32_PINMUX(8, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO8 ESP32_PINMUX(8, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO9 \ - ESP32_PINMUX(9, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO9 ESP32_PINMUX(9, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO10 \ - ESP32_PINMUX(10, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO10 ESP32_PINMUX(10, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO11 \ - ESP32_PINMUX(11, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO11 ESP32_PINMUX(11, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO12 \ - ESP32_PINMUX(12, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO12 ESP32_PINMUX(12, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO13 \ - ESP32_PINMUX(13, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO13 ESP32_PINMUX(13, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO14 \ - ESP32_PINMUX(14, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO14 ESP32_PINMUX(14, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO15 \ - ESP32_PINMUX(15, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO15 ESP32_PINMUX(15, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO16 \ - ESP32_PINMUX(16, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO16 ESP32_PINMUX(16, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO17 \ - ESP32_PINMUX(17, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO17 ESP32_PINMUX(17, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO18 \ - ESP32_PINMUX(18, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO18 ESP32_PINMUX(18, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO19 \ - ESP32_PINMUX(19, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO19 ESP32_PINMUX(19, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO20 \ - ESP32_PINMUX(20, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO20 ESP32_PINMUX(20, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO21 \ - ESP32_PINMUX(21, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO21 ESP32_PINMUX(21, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO26 \ - ESP32_PINMUX(26, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO26 ESP32_PINMUX(26, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO27 \ - ESP32_PINMUX(27, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO27 ESP32_PINMUX(27, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO28 \ - ESP32_PINMUX(28, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO28 ESP32_PINMUX(28, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO29 \ - ESP32_PINMUX(29, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO29 ESP32_PINMUX(29, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO30 \ - ESP32_PINMUX(30, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO30 ESP32_PINMUX(30, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO31 \ - ESP32_PINMUX(31, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO31 ESP32_PINMUX(31, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO32 \ - ESP32_PINMUX(32, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO32 ESP32_PINMUX(32, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO33 \ - ESP32_PINMUX(33, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO33 ESP32_PINMUX(33, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO34 \ - ESP32_PINMUX(34, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO34 ESP32_PINMUX(34, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO35 \ - ESP32_PINMUX(35, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO35 ESP32_PINMUX(35, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO36 \ - ESP32_PINMUX(36, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO36 ESP32_PINMUX(36, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO37 \ - ESP32_PINMUX(37, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO37 ESP32_PINMUX(37, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO38 \ - ESP32_PINMUX(38, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO38 ESP32_PINMUX(38, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO39 \ - ESP32_PINMUX(39, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO39 ESP32_PINMUX(39, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO40 \ - ESP32_PINMUX(40, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO40 ESP32_PINMUX(40, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO41 \ - ESP32_PINMUX(41, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO41 ESP32_PINMUX(41, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO42 \ - ESP32_PINMUX(42, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO42 ESP32_PINMUX(42, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO43 \ - ESP32_PINMUX(43, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO43 ESP32_PINMUX(43, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO44 \ - ESP32_PINMUX(44, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO44 ESP32_PINMUX(44, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO45 \ - ESP32_PINMUX(45, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO45 ESP32_PINMUX(45, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO46 \ - ESP32_PINMUX(46, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO46 ESP32_PINMUX(46, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO47 \ - ESP32_PINMUX(47, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO47 ESP32_PINMUX(47, ESP_U2CTS_IN, ESP_NOSIG) -#define UART2_CTS_GPIO48 \ - ESP32_PINMUX(48, ESP_U2CTS_IN, ESP_NOSIG) +#define UART2_CTS_GPIO48 ESP32_PINMUX(48, ESP_U2CTS_IN, ESP_NOSIG) /* UART2_RTS */ -#define UART2_RTS_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U2RTS_OUT) -#define UART2_RTS_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U2RTS_OUT) +#define UART2_RTS_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U2RTS_OUT) /* UART2_RX */ -#define UART2_RX_GPIO0 \ - ESP32_PINMUX(0, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO0 ESP32_PINMUX(0, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO1 \ - ESP32_PINMUX(1, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO1 ESP32_PINMUX(1, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO2 \ - ESP32_PINMUX(2, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO2 ESP32_PINMUX(2, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO3 \ - ESP32_PINMUX(3, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO3 ESP32_PINMUX(3, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO4 \ - ESP32_PINMUX(4, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO4 ESP32_PINMUX(4, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO5 \ - ESP32_PINMUX(5, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO5 ESP32_PINMUX(5, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO6 \ - ESP32_PINMUX(6, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO6 ESP32_PINMUX(6, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO7 \ - ESP32_PINMUX(7, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO7 ESP32_PINMUX(7, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO8 \ - ESP32_PINMUX(8, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO8 ESP32_PINMUX(8, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO9 \ - ESP32_PINMUX(9, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO9 ESP32_PINMUX(9, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO10 \ - ESP32_PINMUX(10, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO10 ESP32_PINMUX(10, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO11 \ - ESP32_PINMUX(11, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO11 ESP32_PINMUX(11, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO12 \ - ESP32_PINMUX(12, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO12 ESP32_PINMUX(12, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO13 \ - ESP32_PINMUX(13, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO13 ESP32_PINMUX(13, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO14 \ - ESP32_PINMUX(14, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO14 ESP32_PINMUX(14, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO15 \ - ESP32_PINMUX(15, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO15 ESP32_PINMUX(15, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO16 \ - ESP32_PINMUX(16, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO16 ESP32_PINMUX(16, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO17 \ - ESP32_PINMUX(17, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO17 ESP32_PINMUX(17, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO18 \ - ESP32_PINMUX(18, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO18 ESP32_PINMUX(18, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO19 \ - ESP32_PINMUX(19, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO19 ESP32_PINMUX(19, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO20 \ - ESP32_PINMUX(20, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO20 ESP32_PINMUX(20, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO21 \ - ESP32_PINMUX(21, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO21 ESP32_PINMUX(21, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO26 \ - ESP32_PINMUX(26, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO26 ESP32_PINMUX(26, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO27 \ - ESP32_PINMUX(27, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO27 ESP32_PINMUX(27, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO28 \ - ESP32_PINMUX(28, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO28 ESP32_PINMUX(28, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO29 \ - ESP32_PINMUX(29, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO29 ESP32_PINMUX(29, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO30 \ - ESP32_PINMUX(30, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO30 ESP32_PINMUX(30, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO31 \ - ESP32_PINMUX(31, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO31 ESP32_PINMUX(31, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO32 \ - ESP32_PINMUX(32, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO32 ESP32_PINMUX(32, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO33 \ - ESP32_PINMUX(33, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO33 ESP32_PINMUX(33, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO34 \ - ESP32_PINMUX(34, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO34 ESP32_PINMUX(34, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO35 \ - ESP32_PINMUX(35, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO35 ESP32_PINMUX(35, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO36 \ - ESP32_PINMUX(36, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO36 ESP32_PINMUX(36, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO37 \ - ESP32_PINMUX(37, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO37 ESP32_PINMUX(37, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO38 \ - ESP32_PINMUX(38, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO38 ESP32_PINMUX(38, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO39 \ - ESP32_PINMUX(39, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO39 ESP32_PINMUX(39, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO40 \ - ESP32_PINMUX(40, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO40 ESP32_PINMUX(40, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO41 \ - ESP32_PINMUX(41, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO41 ESP32_PINMUX(41, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO42 \ - ESP32_PINMUX(42, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO42 ESP32_PINMUX(42, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO43 \ - ESP32_PINMUX(43, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO43 ESP32_PINMUX(43, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO44 \ - ESP32_PINMUX(44, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO44 ESP32_PINMUX(44, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO45 \ - ESP32_PINMUX(45, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO45 ESP32_PINMUX(45, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO46 \ - ESP32_PINMUX(46, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO46 ESP32_PINMUX(46, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO47 \ - ESP32_PINMUX(47, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO47 ESP32_PINMUX(47, ESP_U2RXD_IN, ESP_NOSIG) -#define UART2_RX_GPIO48 \ - ESP32_PINMUX(48, ESP_U2RXD_IN, ESP_NOSIG) +#define UART2_RX_GPIO48 ESP32_PINMUX(48, ESP_U2RXD_IN, ESP_NOSIG) /* UART2_TX */ -#define UART2_TX_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_U2TXD_OUT) -#define UART2_TX_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_U2TXD_OUT) +#define UART2_TX_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U2TXD_OUT) #endif /* INC_DT_BINDS_PINCTRL_ESP32S3_PINCTRL_HAL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h index 38b8f6e4..885c8d57 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h @@ -3,8 +3,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_H_ -#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_H_ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_S1_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_S1_H_ /* * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield @@ -115,4 +115,4 @@ (((GECKO_LOCATION(##loc##) & GECKO_LOC_MSK) << GECKO_LOC_POS) | \ ((GECKO_FUN_##fun##_LOC & GECKO_FUN_MSK) << GECKO_FUN_POS)) -#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_H_ */ +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_S1_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h index 97a3ab76..fbfaf777 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h @@ -63,5 +63,6 @@ #define MAX32_POWER_SOURCE_SHIFT 0x04 #define MAX32_OUTPUT_HIGH_SHIFT 0x05 #define MAX32_DRV_STRENGTH_SHIFT 0x06 /* 2 bits */ +#define MAX32_DRV_STRENGTH_MASK 0x03 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h index bdb370d2..4611baef 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h @@ -10,7 +10,10 @@ * The whole nRF pin configuration information is encoded in a 32-bit bitfield * organized as follows: * - * - 31..17: Pin function. + * - 31..24: Pin function. + * - 19-23: Reserved. + * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only) + * - 17: Clockpin enable. * - 16: Pin inversion mode. * - 15: Pin low power mode. * - 14..11: Pin output drive configuration. @@ -24,9 +27,17 @@ */ /** Position of the function field. */ -#define NRF_FUN_POS 17U +#define NRF_FUN_POS 24U /** Mask for the function field. */ -#define NRF_FUN_MSK 0x7FFFU +#define NRF_FUN_MSK 0xFFU +/** Position of the GPD FAST ACTIVE1 */ +#define NRF_GPD_FAST_ACTIVE1_POS 18U +/** Mask for the GPD FAST ACTIVE1 */ +#define NRF_GPD_FAST_ACTIVE1_MSK 0x1U +/** Position of the clockpin enable field. */ +#define NRF_CLOCKPIN_ENABLE_POS 17U +/** Mask for the clockpin enable field. */ +#define NRF_CLOCKPIN_ENABLE_MSK 0x1U /** Position of the invert field. */ #define NRF_INVERT_POS 16U /** Mask for the invert field. */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h index f32f926a..a63cada0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h @@ -1,5 +1,5 @@ /* - * Copyright 2022 NXP + * Copyright 2022, 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,19 +16,22 @@ * - 3..6: Input mux Source Signal Selection (IMCR.SSS) * - 7..15: Input Multiplexed Signal Configuration Register (IMCR) index * - 16..24: Multiplexed Signal Configuration Register (MSCR) index - * - 25..27: SIUL2 instance index (0..7) - * - 28..31: Reserved for future use + * - 25..27: MSCR SIUL2 instance index (0..7) + * - 28..30: IMCR SIUL2 instance index (0..7) + * - 31: Reserved for future use */ -#define NXP_S32_MSCR_SSS_SHIFT 0U -#define NXP_S32_MSCR_SSS_MASK BIT_MASK(3) -#define NXP_S32_IMCR_SSS_SHIFT 3U -#define NXP_S32_IMCR_SSS_MASK BIT_MASK(4) -#define NXP_S32_IMCR_IDX_SHIFT 7U -#define NXP_S32_IMCR_IDX_MASK BIT_MASK(9) -#define NXP_S32_MSCR_IDX_SHIFT 16U -#define NXP_S32_MSCR_IDX_MASK BIT_MASK(9) -#define NXP_S32_SIUL2_IDX_SHIFT 25U -#define NXP_S32_SIUL2_IDX_MASK BIT_MASK(3) +#define NXP_S32_MSCR_SSS_SHIFT 0U +#define NXP_S32_MSCR_SSS_MASK BIT_MASK(3) +#define NXP_S32_IMCR_SSS_SHIFT 3U +#define NXP_S32_IMCR_SSS_MASK BIT_MASK(4) +#define NXP_S32_IMCR_IDX_SHIFT 7U +#define NXP_S32_IMCR_IDX_MASK BIT_MASK(9) +#define NXP_S32_MSCR_IDX_SHIFT 16U +#define NXP_S32_MSCR_IDX_MASK BIT_MASK(9) +#define NXP_S32_MSCR_SIUL2_IDX_SHIFT 25U +#define NXP_S32_MSCR_SIUL2_IDX_MASK BIT_MASK(3) +#define NXP_S32_IMCR_SIUL2_IDX_SHIFT 28U +#define NXP_S32_IMCR_SIUL2_IDX_MASK BIT_MASK(3) #define NXP_S32_PINMUX_MSCR_SSS(cfg) \ (((cfg) & NXP_S32_MSCR_SSS_MASK) << NXP_S32_MSCR_SSS_SHIFT) @@ -42,8 +45,11 @@ #define NXP_S32_PINMUX_MSCR_IDX(cfg) \ (((cfg) & NXP_S32_MSCR_IDX_MASK) << NXP_S32_MSCR_IDX_SHIFT) -#define NXP_S32_PINMUX_SIUL2_IDX(cfg) \ - (((cfg) & NXP_S32_SIUL2_IDX_MASK) << NXP_S32_SIUL2_IDX_SHIFT) +#define NXP_S32_PINMUX_MSCR_SIUL2_IDX(cfg) \ + (((cfg) & NXP_S32_MSCR_SIUL2_IDX_MASK) << NXP_S32_MSCR_SIUL2_IDX_SHIFT) + +#define NXP_S32_PINMUX_IMCR_SIUL2_IDX(cfg) \ + (((cfg) & NXP_S32_IMCR_SIUL2_IDX_MASK) << NXP_S32_IMCR_SIUL2_IDX_SHIFT) #define NXP_S32_PINMUX_GET_MSCR_SSS(cfg) \ (((cfg) >> NXP_S32_MSCR_SSS_SHIFT) & NXP_S32_MSCR_SSS_MASK) @@ -57,21 +63,28 @@ #define NXP_S32_PINMUX_GET_MSCR_IDX(cfg) \ (((cfg) >> NXP_S32_MSCR_IDX_SHIFT) & NXP_S32_MSCR_IDX_MASK) -#define NXP_S32_PINMUX_GET_SIUL2_IDX(cfg) \ - (((cfg) >> NXP_S32_SIUL2_IDX_SHIFT) & NXP_S32_SIUL2_IDX_MASK) +#define NXP_S32_PINMUX_GET_MSCR_SIUL2_IDX(cfg) \ + (((cfg) >> NXP_S32_MSCR_SIUL2_IDX_SHIFT) & NXP_S32_MSCR_SIUL2_IDX_MASK) + +#define NXP_S32_PINMUX_GET_IMCR_SIUL2_IDX(cfg) \ + (((cfg) >> NXP_S32_IMCR_SIUL2_IDX_SHIFT) & NXP_S32_IMCR_SIUL2_IDX_MASK) /** * @brief Utility macro to build NXP S32 pinmux property for pinctrl nodes. * - * @param siul2_idx SIUL2 instance index + * @param mscr_siul2_idx MSCR SIUL2 instance index + * @param imcr_siul2_idx IMCR SIUL2 instance index * @param mscr_idx Multiplexed Signal Configuration Register (MSCR) index * @param mscr_sss Output mux Source Signal Selection (MSCR.SSS) * @param imcr_idx Input Multiplexed Signal Configuration Register (IMCR) index * @param imcr_sss Input mux Source Signal Selection (IMCR.SSS) */ -#define NXP_S32_PINMUX(siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \ - (NXP_S32_PINMUX_SIUL2_IDX(siul2_idx) | NXP_S32_PINMUX_MSCR_IDX(mscr_idx) \ - | NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | NXP_S32_PINMUX_IMCR_IDX(imcr_idx) \ - | NXP_S32_PINMUX_IMCR_SSS(imcr_sss)) +#define NXP_S32_PINMUX(mscr_siul2_idx, imcr_siul2_idx, mscr_idx, mscr_sss, imcr_idx, imcr_sss) \ + (NXP_S32_PINMUX_MSCR_SIUL2_IDX(mscr_siul2_idx) | \ + NXP_S32_PINMUX_IMCR_SIUL2_IDX(imcr_siul2_idx) | \ + NXP_S32_PINMUX_MSCR_IDX(mscr_idx) | \ + NXP_S32_PINMUX_MSCR_SSS(mscr_sss) | \ + NXP_S32_PINMUX_IMCR_IDX(imcr_idx) | \ + NXP_S32_PINMUX_IMCR_SSS(imcr_sss)) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NXP_NXP_S32_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h new file mode 100644 index 00000000..5d88ea6e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ +#define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ + +#define RA_PORT_NUM_POS 0 +#define RA_PORT_NUM_MASK 0xf + +#define RA_PIN_NUM_POS 4 +#define RA_PIN_NUM_MASK 0xf + +#define RA_PSEL_HIZ_JTAG_SWD 0x0 +#define RA_PSEL_AGT 0x1 +#define RA_PSEL_GPT0 0x2 +#define RA_PSEL_GPT1 0x3 +#define RA_PSEL_SCI_0 0x4 +#define RA_PSEL_SCI_2 0x4 +#define RA_PSEL_SCI_4 0x4 +#define RA_PSEL_SCI_6 0x4 +#define RA_PSEL_SCI_8 0x4 +#define RA_PSEL_SCI_1 0x5 +#define RA_PSEL_SCI_3 0x5 +#define RA_PSEL_SCI_5 0x5 +#define RA_PSEL_SCI_7 0x5 +#define RA_PSEL_SCI_9 0x5 +#define RA_PSEL_SPI 0x6 +#define RA_PSEL_I2C 0x7 +#define RA_PSEL_CLKOUT_RTC 0x9 +#define RA_PSEL_CAC_ADC 0xa +#define RA_PSEL_BUS 0xb +#define RA_PSEL_CANFD 0x10 +#define RA_PSEL_QSPI 0x11 +#define RA_PSEL_SSIE 0x12 +#define RA_PSEL_USBFS 0x13 +#define RA_PSEL_USBHS 0x14 +#define RA_PSEL_SDHI 0x15 +#define RA_PSEL_ETH_MII 0x16 +#define RA_PSEL_ETH_RMII 0x17 +#define RA_PSEL_GLCDC 0x19 +#define RA_PSEL_OSPI 0x1c +#define RA_PSEL_ADC 0x00 + +#define RA_PSEL_POS 8 +#define RA_PSEL_MASK 0x1f + +#define RA_MODE_POS 13 +#define RA_MODE_MASK 0x1 + +#define RA_PSEL(psel, port_num, pin_num) \ + (1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS | \ + pin_num << RA_PIN_NUM_POS) + +#endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h new file mode 100644 index 00000000..da9266ac --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_ + +/* Superset list of all possible IO ports. */ +#define PORT_00 0x0000 /* IO port 0 */ +#define PORT_01 0x1000 /* IO port 1 */ +#define PORT_02 0x1100 /* IO port 2 */ +#define PORT_03 0x1200 /* IO port 3 */ +#define PORT_04 0x1300 /* IO port 4 */ +#define PORT_05 0x0100 /* IO port 5 */ +#define PORT_06 0x0200 /* IO port 6 */ +#define PORT_07 0x1400 /* IO port 7 */ +#define PORT_08 0x1500 /* IO port 8 */ +#define PORT_09 0x1600 /* IO port 9 */ +#define PORT_10 0x1700 /* IO port 10 */ +#define PORT_11 0x0300 /* IO port 11 */ +#define PORT_12 0x0400 /* IO port 12 */ +#define PORT_13 0x0500 /* IO port 13 */ +#define PORT_14 0x0600 /* IO port 14 */ +#define PORT_15 0x0700 /* IO port 15 */ +#define PORT_16 0x0800 /* IO port 16 */ +#define PORT_17 0x0900 /* IO port 17 */ +#define PORT_18 0x0A00 /* IO port 18 */ + +/* + * Create the value contain port/pin/function information + * + * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18 + * pin: pin number + * func: pin function + */ +#define RZG_PINMUX(port, pin, func) (port | pin | (func << 4)) + +/* Special purpose port */ +#define BSP_IO_NMI 0xFFFF0000 /* NMI */ + +#define BSP_IO_TMS_SWDIO 0xFFFF0100 /* TMS_SWDIO */ +#define BSP_IO_TDO 0xFFFF0101 /* TDO */ + +#define BSP_IO_AUDIO_CLK1 0xFFFF0200 /* AUDIO_CLK1 */ +#define BSP_IO_AUDIO_CLK2 0xFFFF0201 /* AUDIO_CLK2 */ + +#define BSP_IO_XSPI_SPCLK 0xFFFF0400 /* XSPI_SPCLK */ +#define BSP_IO_XSPI_RESET_N 0xFFFF0401 /* XSPI_RESET_N */ +#define BSP_IO_XSPI_WP_N 0xFFFF0402 /* XSPI_WP_N */ +#define BSP_IO_XSPI_DS 0xFFFF0403 /* XSPI_DS */ +#define BSP_IO_XSPI_CS0_N 0xFFFF0404 /* XSPI_CS0_N */ +#define BSP_IO_XSPI_CS1_N 0xFFFF0405 /* XSPI_CS1_N */ + +#define BSP_IO_XSPI_IO0 0xFFFF0500 /* XSPI_IO0 */ +#define BSP_IO_XSPI_IO1 0xFFFF0501 /* XSPI_IO1 */ +#define BSP_IO_XSPI_IO2 0xFFFF0502 /* XSPI_IO2 */ +#define BSP_IO_XSPI_IO3 0xFFFF0503 /* XSPI_IO3 */ +#define BSP_IO_XSPI_IO4 0xFFFF0504 /* XSPI_IO4 */ +#define BSP_IO_XSPI_IO5 0xFFFF0505 /* XSPI_IO5 */ +#define BSP_IO_XSPI_IO6 0xFFFF0506 /* XSPI_IO6 */ +#define BSP_IO_XSPI_IO7 0xFFFF0507 /* XSPI_IO7 */ + +#define BSP_IO_WDTOVF_PERROUT 0xFFFF0600 /* WDTOVF_PERROUT */ + +#define BSP_IO_I3C_SDA 0xFFFF0900 /* I3C_SDA */ +#define BSP_IO_I3C_SCL 0xFFFF0901 /* I3C_SCL */ + +#define BSP_IO_SD0_CLK 0xFFFF1000 /* CD0_CLK */ +#define BSP_IO_SD0_CMD 0xFFFF1001 /* CD0_CMD */ +#define BSP_IO_SD0_RST_N 0xFFFF1002 /* CD0_RST_N */ + +#define BSP_IO_SD0_DATA0 0xFFFF1100 /* SD0_DATA0 */ +#define BSP_IO_SD0_DATA1 0xFFFF1101 /* SD0_DATA1 */ +#define BSP_IO_SD0_DATA2 0xFFFF1102 /* SD0_DATA2 */ +#define BSP_IO_SD0_DATA3 0xFFFF1103 /* SD0_DATA3 */ +#define BSP_IO_SD0_DATA4 0xFFFF1104 /* SD0_DATA4 */ +#define BSP_IO_SD0_DATA5 0xFFFF1105 /* SD0_DATA5 */ +#define BSP_IO_SD0_DATA6 0xFFFF1106 /* SD0_DATA6 */ +#define BSP_IO_SD0_DATA7 0xFFFF1107 /* SD0_DATA7 */ + +#define BSP_IO_SD1_CLK 0xFFFF1200 /* SD1_CLK */ +#define BSP_IO_SD1_CMD 0xFFFF1201 /* SD1_CMD */ + +#define BSP_IO_SD1_DATA0 0xFFFF1300 /* SD1_DATA0 */ +#define BSP_IO_SD1_DATA1 0xFFFF1301 /* SD1_DATA1 */ +#define BSP_IO_SD1_DATA2 0xFFFF1302 /* SD1_DATA2 */ +#define BSP_IO_SD1_DATA3 0xFFFF1303 /* SD1_DATA3 */ + +/*FILNUM*/ +#define RZG_FILNUM_4_STAGE 0 +#define RZG_FILNUM_8_STAGE 1 +#define RZG_FILNUM_12_STAGE 2 +#define RZG_FILNUM_16_STAGE 3 + +/*FILCLKSEL*/ +#define RZG_FILCLKSEL_NOT_DIV 0 +#define RZG_FILCLKSEL_DIV_9000 1 +#define RZG_FILCLKSEL_DIV_18000 2 +#define RZG_FILCLKSEL_DIV_36000 3 + +#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3) + +#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h index c7870a21..64c3832d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h @@ -25,6 +25,11 @@ #define RP2_PIN_NUM_POS 4 #define RP2_PIN_NUM_MASK 0x1f +#define RP2_GPIO_OVERRIDE_NORMAL 0 +#define RP2_GPIO_OVERRIDE_INVERT 1 +#define RP2_GPIO_OVERRIDE_LOW 2 +#define RP2_GPIO_OVERRIDE_HIGH 3 + #define RP2040_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS | \ alt_func << RP2_ALT_FUNC_POS) @@ -226,4 +231,15 @@ #define GPOUT2_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK) #define GPOUT3_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK) +#define USB_VBUS_DET_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_USB) +#define USB_VBUS_DET_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_USB) + #endif /* __RP2040_PINCTRL_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/si32-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/si32-pinctrl.h new file mode 100644 index 00000000..994480b3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/si32-pinctrl.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2024 GARDENA GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SI32_PINCTRL_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SI32_PINCTRL_ + +#define SI32_SIGNAL_USART0_TX 0 +#define SI32_SIGNAL_USART0_RX 1 +#define SI32_SIGNAL_USART0_RTS 2 +#define SI32_SIGNAL_USART0_CTS 3 +#define SI32_SIGNAL_USART0_UCLK 4 + +#define SI32_SIGNAL_SPI0_SCK 5 +#define SI32_SIGNAL_SPI0_MISO 6 +#define SI32_SIGNAL_SPI0_MOSI 7 +#define SI32_SIGNAL_SPI0_NSS 8 + +#define SI32_SIGNAL_USART1_TX 9 +#define SI32_SIGNAL_USART1_RX 10 +#define SI32_SIGNAL_USART1_RTS 11 +#define SI32_SIGNAL_USART1_CTS 12 +#define SI32_SIGNAL_USART1_UCLK 13 + +#define SI32_SIGNAL_EPCA0_CEX0 14 +#define SI32_SIGNAL_EPCA0_CEX1 15 +#define SI32_SIGNAL_EPCA0_CEX2 16 +#define SI32_SIGNAL_EPCA0_CEX3 17 +#define SI32_SIGNAL_EPCA0_CEX4 18 +#define SI32_SIGNAL_EPCA0_CEX4 19 + +#define SI32_SIGNAL_PCA0_CEX0 20 +#define SI32_SIGNAL_PCA0_CEX1 21 + +#define SI32_SIGNAL_PCA1_CEX0 22 +#define SI32_SIGNAL_PCA1_CEX1 23 + +#define SI32_SIGNAL_EPCA0_ECI 24 + +#define SI32_SIGNAL_PCA0_ECI 25 + +#define SI32_SIGNAL_PCA1_ECI 26 + +#define SI32_SIGNAL_I2S0_TX_WS 27 +#define SI32_SIGNAL_I2S0_TX_SCK 28 +#define SI32_SIGNAL_I2S0_TX_SD 29 + +#define SI32_SIGNAL_I2C0_SDA 30 +#define SI32_SIGNAL_I2C0_SCL 31 + +#define SI32_SIGNAL_CMP0S 32 +#define SI32_SIGNAL_CMP0A 33 + +#define SI32_SIGNAL_CMP1S 34 +#define SI32_SIGNAL_CMP1A 35 + +#define SI32_SIGNAL_TIMER0_CT 36 +#define SI32_SIGNAL_TIMER0_EX 37 + +#define SI32_SIGNAL_TIMER1_CT 38 +#define SI32_SIGNAL_TIMER1_EX 39 + +#define SI32_SIGNAL_UART0_TX 40 +#define SI32_SIGNAL_UART0_RX 41 +#define SI32_SIGNAL_UART0_RTS 42 +#define SI32_SIGNAL_UART0_CTS 43 + +#define SI32_SIGNAL_UART1_TX 44 +#define SI32_SIGNAL_UART1_RX 45 + +#define SI32_SIGNAL_SPI1_SCK 46 +#define SI32_SIGNAL_SPI1_MISO 47 +#define SI32_SIGNAL_SPI1_MOSI 48 +#define SI32_SIGNAL_SPI1_NSS 49 + +#define SI32_SIGNAL_SPI2_SCK 50 +#define SI32_SIGNAL_SPI2_MISO 51 +#define SI32_SIGNAL_SPI2_MOSI 52 +#define SI32_SIGNAL_SPI2_NSS 53 + +#define SI32_SIGNAL_AHB_OUT 54 + +#define SI32_SIGNAL_SSG0_EX0 55 +#define SI32_SIGNAL_SSG0_EX1 56 +#define SI32_SIGNAL_SSG0_EX2 57 +#define SI32_SIGNAL_SSG0_EX3 58 + +#define SI32_SIGNAL_RTC0_OUT 59 + +#define SI32_SIGNAL_I2S0_RX_WS 60 +#define SI32_SIGNAL_I2S0_RX_SCK 61 +#define SI32_SIGNAL_I2S0_RX_SD 62 + +#define SI32_SIGNAL_LPTIMER0_OUT 63 + +#define SI32_SIGNAL_I2C1_SDA 64 +#define SI32_SIGNAL_I2C1_SCL 65 + +#define SI32_SIGNAL_PB_HDKILL 66 + +/** + * @brief Specify MUX field + * + * @param fun Function name + * @param port Port number (0 to 4) + * @param pin Port pin number (0 to 15) + */ +#define SI32_MUX(fun, port, pin) \ + ((((port)&0x7)) | (((pin)&0xF) << 3) | ((SI32_SIGNAL_##fun & 0x7F) << 22)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SI32_PINCTRL_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h new file mode 100644 index 00000000..9ad02a5c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2024 Silicon Labs + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ + +#include + +/* + * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows: + * + * 31..29: Reserved + * 28..24: Route register offset in words from peripheral config (offset of ROUTE + * register in GPIO_ROUTE_TypeDef) + * 23..19: Enable bit (offset into ROUTEEN register for given function) + * 18 : Enable bit presence (some inputs are auto-enabled) + * 17..8 : Peripheral config offset in words from DBUS base within GPIO (offset of ROUTE[n] + * register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440]) + * 7..4 : GPIO pin + * 3..0 : GPIO port + */ + +#define SILABS_PINCTRL_GPIO_PORT_MASK 0x0000000FUL +#define SILABS_PINCTRL_GPIO_PIN_MASK 0x000000F0UL +#define SILABS_PINCTRL_PERIPH_BASE_MASK 0x0003FF00UL +#define SILABS_PINCTRL_HAVE_EN_MASK 0x00040000UL +#define SILABS_PINCTRL_EN_BIT_MASK 0x00F80000UL +#define SILABS_PINCTRL_ROUTE_MASK 0x1F000000UL + +#define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route) \ + (FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) | \ + FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) | \ + FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) | \ + FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) | \ + FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) | \ + FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h new file mode 100644 index 00000000..4ab1c6ab --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h @@ -0,0 +1,1188 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs XG21 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ + +#include + +#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) + +#define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1) + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) + +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 17, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 17, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 17, 1, 2, 3) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 22, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 26, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 26, 1, 1, 2) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 30, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 30, 1, 1, 2) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 34, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 34, 1, 1, 2) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 34, 1, 2, 3) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 34, 1, 3, 5) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 34, 0, 0, 4) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 41, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 41, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 41, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 41, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 41, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 41, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 41, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 41, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 41, 1, 11, 12) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 41, 1, 12, 13) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 41, 1, 13, 14) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 41, 1, 14, 15) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 41, 1, 15, 16) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 59, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 59, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 59, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 59, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 59, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 59, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 67, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 67, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 67, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 67, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 83, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 83, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 83, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 83, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 83, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 83, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 91, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 91, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 91, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 91, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 91, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 91, 0, 0, 2) + +#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 99, 1, 0, 1) +#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 99, 1, 1, 3) +#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 99, 1, 2, 4) +#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 99, 1, 3, 5) +#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 99, 1, 4, 6) +#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 99, 0, 0, 2) + +#define SILABS_DBUS_USART2_CS(port, pin) SILABS_DBUS(port, pin, 107, 1, 0, 1) +#define SILABS_DBUS_USART2_RTS(port, pin) SILABS_DBUS(port, pin, 107, 1, 1, 3) +#define SILABS_DBUS_USART2_RX(port, pin) SILABS_DBUS(port, pin, 107, 1, 2, 4) +#define SILABS_DBUS_USART2_CLK(port, pin) SILABS_DBUS(port, pin, 107, 1, 3, 5) +#define SILABS_DBUS_USART2_TX(port, pin) SILABS_DBUS(port, pin, 107, 1, 4, 6) +#define SILABS_DBUS_USART2_CTS(port, pin) SILABS_DBUS(port, pin, 107, 0, 0, 2) + +#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) +#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) +#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) +#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) +#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) +#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) +#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) +#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) +#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) +#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) +#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) +#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) +#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) +#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) +#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) +#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) +#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) +#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) +#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) +#define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4) + +#define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0) +#define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1) +#define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2) +#define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3) +#define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4) +#define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5) +#define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6) +#define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0) +#define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1) +#define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0) +#define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1) +#define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2) +#define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3) +#define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4) +#define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5) +#define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0) +#define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1) +#define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2) +#define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3) +#define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) +#define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4) + +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) +#define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) +#define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) +#define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) + +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) +#define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) +#define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) +#define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) +#define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) +#define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4) + +#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) +#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) +#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) +#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) +#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) +#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) +#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) +#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) +#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) +#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) +#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) +#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) +#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) +#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) +#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) +#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) +#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) +#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) +#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) +#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) +#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) +#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) +#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) +#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) +#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) +#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) +#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) +#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) +#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) +#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) +#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) +#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) +#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) +#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) +#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) +#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) +#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) +#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) +#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) +#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) +#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) +#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) +#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) +#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) +#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) +#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) +#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) +#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) +#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) +#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) +#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) +#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) +#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) +#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) + +#define USART2_CS_PC0 SILABS_DBUS_USART2_CS(0x2, 0x0) +#define USART2_CS_PC1 SILABS_DBUS_USART2_CS(0x2, 0x1) +#define USART2_CS_PC2 SILABS_DBUS_USART2_CS(0x2, 0x2) +#define USART2_CS_PC3 SILABS_DBUS_USART2_CS(0x2, 0x3) +#define USART2_CS_PC4 SILABS_DBUS_USART2_CS(0x2, 0x4) +#define USART2_CS_PC5 SILABS_DBUS_USART2_CS(0x2, 0x5) +#define USART2_CS_PD0 SILABS_DBUS_USART2_CS(0x3, 0x0) +#define USART2_CS_PD1 SILABS_DBUS_USART2_CS(0x3, 0x1) +#define USART2_CS_PD2 SILABS_DBUS_USART2_CS(0x3, 0x2) +#define USART2_CS_PD3 SILABS_DBUS_USART2_CS(0x3, 0x3) +#define USART2_CS_PD4 SILABS_DBUS_USART2_CS(0x3, 0x4) +#define USART2_RTS_PC0 SILABS_DBUS_USART2_RTS(0x2, 0x0) +#define USART2_RTS_PC1 SILABS_DBUS_USART2_RTS(0x2, 0x1) +#define USART2_RTS_PC2 SILABS_DBUS_USART2_RTS(0x2, 0x2) +#define USART2_RTS_PC3 SILABS_DBUS_USART2_RTS(0x2, 0x3) +#define USART2_RTS_PC4 SILABS_DBUS_USART2_RTS(0x2, 0x4) +#define USART2_RTS_PC5 SILABS_DBUS_USART2_RTS(0x2, 0x5) +#define USART2_RTS_PD0 SILABS_DBUS_USART2_RTS(0x3, 0x0) +#define USART2_RTS_PD1 SILABS_DBUS_USART2_RTS(0x3, 0x1) +#define USART2_RTS_PD2 SILABS_DBUS_USART2_RTS(0x3, 0x2) +#define USART2_RTS_PD3 SILABS_DBUS_USART2_RTS(0x3, 0x3) +#define USART2_RTS_PD4 SILABS_DBUS_USART2_RTS(0x3, 0x4) +#define USART2_RX_PC0 SILABS_DBUS_USART2_RX(0x2, 0x0) +#define USART2_RX_PC1 SILABS_DBUS_USART2_RX(0x2, 0x1) +#define USART2_RX_PC2 SILABS_DBUS_USART2_RX(0x2, 0x2) +#define USART2_RX_PC3 SILABS_DBUS_USART2_RX(0x2, 0x3) +#define USART2_RX_PC4 SILABS_DBUS_USART2_RX(0x2, 0x4) +#define USART2_RX_PC5 SILABS_DBUS_USART2_RX(0x2, 0x5) +#define USART2_RX_PD0 SILABS_DBUS_USART2_RX(0x3, 0x0) +#define USART2_RX_PD1 SILABS_DBUS_USART2_RX(0x3, 0x1) +#define USART2_RX_PD2 SILABS_DBUS_USART2_RX(0x3, 0x2) +#define USART2_RX_PD3 SILABS_DBUS_USART2_RX(0x3, 0x3) +#define USART2_RX_PD4 SILABS_DBUS_USART2_RX(0x3, 0x4) +#define USART2_CLK_PC0 SILABS_DBUS_USART2_CLK(0x2, 0x0) +#define USART2_CLK_PC1 SILABS_DBUS_USART2_CLK(0x2, 0x1) +#define USART2_CLK_PC2 SILABS_DBUS_USART2_CLK(0x2, 0x2) +#define USART2_CLK_PC3 SILABS_DBUS_USART2_CLK(0x2, 0x3) +#define USART2_CLK_PC4 SILABS_DBUS_USART2_CLK(0x2, 0x4) +#define USART2_CLK_PC5 SILABS_DBUS_USART2_CLK(0x2, 0x5) +#define USART2_CLK_PD0 SILABS_DBUS_USART2_CLK(0x3, 0x0) +#define USART2_CLK_PD1 SILABS_DBUS_USART2_CLK(0x3, 0x1) +#define USART2_CLK_PD2 SILABS_DBUS_USART2_CLK(0x3, 0x2) +#define USART2_CLK_PD3 SILABS_DBUS_USART2_CLK(0x3, 0x3) +#define USART2_CLK_PD4 SILABS_DBUS_USART2_CLK(0x3, 0x4) +#define USART2_TX_PC0 SILABS_DBUS_USART2_TX(0x2, 0x0) +#define USART2_TX_PC1 SILABS_DBUS_USART2_TX(0x2, 0x1) +#define USART2_TX_PC2 SILABS_DBUS_USART2_TX(0x2, 0x2) +#define USART2_TX_PC3 SILABS_DBUS_USART2_TX(0x2, 0x3) +#define USART2_TX_PC4 SILABS_DBUS_USART2_TX(0x2, 0x4) +#define USART2_TX_PC5 SILABS_DBUS_USART2_TX(0x2, 0x5) +#define USART2_TX_PD0 SILABS_DBUS_USART2_TX(0x3, 0x0) +#define USART2_TX_PD1 SILABS_DBUS_USART2_TX(0x3, 0x1) +#define USART2_TX_PD2 SILABS_DBUS_USART2_TX(0x3, 0x2) +#define USART2_TX_PD3 SILABS_DBUS_USART2_TX(0x3, 0x3) +#define USART2_TX_PD4 SILABS_DBUS_USART2_TX(0x3, 0x4) +#define USART2_CTS_PC0 SILABS_DBUS_USART2_CTS(0x2, 0x0) +#define USART2_CTS_PC1 SILABS_DBUS_USART2_CTS(0x2, 0x1) +#define USART2_CTS_PC2 SILABS_DBUS_USART2_CTS(0x2, 0x2) +#define USART2_CTS_PC3 SILABS_DBUS_USART2_CTS(0x2, 0x3) +#define USART2_CTS_PC4 SILABS_DBUS_USART2_CTS(0x2, 0x4) +#define USART2_CTS_PC5 SILABS_DBUS_USART2_CTS(0x2, 0x5) +#define USART2_CTS_PD0 SILABS_DBUS_USART2_CTS(0x3, 0x0) +#define USART2_CTS_PD1 SILABS_DBUS_USART2_CTS(0x3, 0x1) +#define USART2_CTS_PD2 SILABS_DBUS_USART2_CTS(0x3, 0x2) +#define USART2_CTS_PD3 SILABS_DBUS_USART2_CTS(0x3, 0x3) +#define USART2_CTS_PD4 SILABS_DBUS_USART2_CTS(0x3, 0x4) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h new file mode 100644 index 00000000..d276d1f5 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h @@ -0,0 +1,1792 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs XG22 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_ + +#include + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 4, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 4, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 4, 0, 0, 1) + +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 15, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 15, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 15, 1, 2, 3) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 20, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 20, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 24, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 24, 1, 1, 2) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 28, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 28, 1, 1, 2) + +#define SILABS_DBUS_EUART0_RTS(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 2) +#define SILABS_DBUS_EUART0_TX(port, pin) SILABS_DBUS(port, pin, 32, 1, 1, 4) +#define SILABS_DBUS_EUART0_CTS(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 1) +#define SILABS_DBUS_EUART0_RX(port, pin) SILABS_DBUS(port, pin, 32, 0, 0, 3) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 38, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 38, 1, 1, 2) +#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 38, 1, 2, 3) +#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 38, 1, 3, 4) +#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 38, 1, 4, 5) +#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 38, 1, 5, 6) +#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 38, 1, 6, 7) +#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 38, 1, 7, 8) +#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 38, 1, 8, 9) +#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 38, 1, 9, 10) +#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 38, 1, 10, 11) +#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 38, 1, 11, 12) +#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 38, 1, 12, 13) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 38, 1, 13, 14) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 38, 1, 14, 16) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 38, 0, 0, 15) + +#define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 56, 1, 0, 1) +#define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 56, 0, 0, 2) +#define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 56, 0, 0, 3) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 61, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 61, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 61, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 61, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 61, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 61, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 61, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 61, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 61, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 61, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 61, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 61, 1, 11, 12) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 61, 1, 12, 13) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 61, 1, 13, 14) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 61, 1, 14, 15) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 61, 1, 15, 16) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 79, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 79, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 79, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 79, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 79, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 79, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 87, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 87, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 87, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 87, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 87, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 87, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 95, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 95, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 95, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 95, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 95, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 95, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 103, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 103, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 103, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 103, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 103, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 103, 1, 5, 6) + +#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 111, 1, 0, 1) +#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 111, 1, 1, 2) +#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 111, 1, 2, 3) +#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 111, 1, 3, 4) +#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 111, 1, 4, 5) +#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 111, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 119, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 119, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 119, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 119, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 119, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 119, 0, 0, 2) + +#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 127, 1, 0, 1) +#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 127, 1, 1, 3) +#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 127, 1, 2, 4) +#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 127, 1, 3, 5) +#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 127, 1, 4, 6) +#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 2) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) +#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) +#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) +#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) +#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) +#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) +#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) + +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) +#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) +#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) +#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) +#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) +#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) +#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) +#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) +#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) +#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) +#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) +#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) +#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) +#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) +#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) +#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) +#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) +#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) +#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) +#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) +#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) + +#define EUART0_RTS_PA0 SILABS_DBUS_EUART0_RTS(0x0, 0x0) +#define EUART0_RTS_PA1 SILABS_DBUS_EUART0_RTS(0x0, 0x1) +#define EUART0_RTS_PA2 SILABS_DBUS_EUART0_RTS(0x0, 0x2) +#define EUART0_RTS_PA3 SILABS_DBUS_EUART0_RTS(0x0, 0x3) +#define EUART0_RTS_PA4 SILABS_DBUS_EUART0_RTS(0x0, 0x4) +#define EUART0_RTS_PA5 SILABS_DBUS_EUART0_RTS(0x0, 0x5) +#define EUART0_RTS_PA6 SILABS_DBUS_EUART0_RTS(0x0, 0x6) +#define EUART0_RTS_PA7 SILABS_DBUS_EUART0_RTS(0x0, 0x7) +#define EUART0_RTS_PA8 SILABS_DBUS_EUART0_RTS(0x0, 0x8) +#define EUART0_RTS_PB0 SILABS_DBUS_EUART0_RTS(0x1, 0x0) +#define EUART0_RTS_PB1 SILABS_DBUS_EUART0_RTS(0x1, 0x1) +#define EUART0_RTS_PB2 SILABS_DBUS_EUART0_RTS(0x1, 0x2) +#define EUART0_RTS_PB3 SILABS_DBUS_EUART0_RTS(0x1, 0x3) +#define EUART0_RTS_PB4 SILABS_DBUS_EUART0_RTS(0x1, 0x4) +#define EUART0_RTS_PC0 SILABS_DBUS_EUART0_RTS(0x2, 0x0) +#define EUART0_RTS_PC1 SILABS_DBUS_EUART0_RTS(0x2, 0x1) +#define EUART0_RTS_PC2 SILABS_DBUS_EUART0_RTS(0x2, 0x2) +#define EUART0_RTS_PC3 SILABS_DBUS_EUART0_RTS(0x2, 0x3) +#define EUART0_RTS_PC4 SILABS_DBUS_EUART0_RTS(0x2, 0x4) +#define EUART0_RTS_PC5 SILABS_DBUS_EUART0_RTS(0x2, 0x5) +#define EUART0_RTS_PC6 SILABS_DBUS_EUART0_RTS(0x2, 0x6) +#define EUART0_RTS_PC7 SILABS_DBUS_EUART0_RTS(0x2, 0x7) +#define EUART0_RTS_PD0 SILABS_DBUS_EUART0_RTS(0x3, 0x0) +#define EUART0_RTS_PD1 SILABS_DBUS_EUART0_RTS(0x3, 0x1) +#define EUART0_RTS_PD2 SILABS_DBUS_EUART0_RTS(0x3, 0x2) +#define EUART0_RTS_PD3 SILABS_DBUS_EUART0_RTS(0x3, 0x3) +#define EUART0_TX_PA0 SILABS_DBUS_EUART0_TX(0x0, 0x0) +#define EUART0_TX_PA1 SILABS_DBUS_EUART0_TX(0x0, 0x1) +#define EUART0_TX_PA2 SILABS_DBUS_EUART0_TX(0x0, 0x2) +#define EUART0_TX_PA3 SILABS_DBUS_EUART0_TX(0x0, 0x3) +#define EUART0_TX_PA4 SILABS_DBUS_EUART0_TX(0x0, 0x4) +#define EUART0_TX_PA5 SILABS_DBUS_EUART0_TX(0x0, 0x5) +#define EUART0_TX_PA6 SILABS_DBUS_EUART0_TX(0x0, 0x6) +#define EUART0_TX_PA7 SILABS_DBUS_EUART0_TX(0x0, 0x7) +#define EUART0_TX_PA8 SILABS_DBUS_EUART0_TX(0x0, 0x8) +#define EUART0_TX_PB0 SILABS_DBUS_EUART0_TX(0x1, 0x0) +#define EUART0_TX_PB1 SILABS_DBUS_EUART0_TX(0x1, 0x1) +#define EUART0_TX_PB2 SILABS_DBUS_EUART0_TX(0x1, 0x2) +#define EUART0_TX_PB3 SILABS_DBUS_EUART0_TX(0x1, 0x3) +#define EUART0_TX_PB4 SILABS_DBUS_EUART0_TX(0x1, 0x4) +#define EUART0_TX_PC0 SILABS_DBUS_EUART0_TX(0x2, 0x0) +#define EUART0_TX_PC1 SILABS_DBUS_EUART0_TX(0x2, 0x1) +#define EUART0_TX_PC2 SILABS_DBUS_EUART0_TX(0x2, 0x2) +#define EUART0_TX_PC3 SILABS_DBUS_EUART0_TX(0x2, 0x3) +#define EUART0_TX_PC4 SILABS_DBUS_EUART0_TX(0x2, 0x4) +#define EUART0_TX_PC5 SILABS_DBUS_EUART0_TX(0x2, 0x5) +#define EUART0_TX_PC6 SILABS_DBUS_EUART0_TX(0x2, 0x6) +#define EUART0_TX_PC7 SILABS_DBUS_EUART0_TX(0x2, 0x7) +#define EUART0_TX_PD0 SILABS_DBUS_EUART0_TX(0x3, 0x0) +#define EUART0_TX_PD1 SILABS_DBUS_EUART0_TX(0x3, 0x1) +#define EUART0_TX_PD2 SILABS_DBUS_EUART0_TX(0x3, 0x2) +#define EUART0_TX_PD3 SILABS_DBUS_EUART0_TX(0x3, 0x3) +#define EUART0_CTS_PA0 SILABS_DBUS_EUART0_CTS(0x0, 0x0) +#define EUART0_CTS_PA1 SILABS_DBUS_EUART0_CTS(0x0, 0x1) +#define EUART0_CTS_PA2 SILABS_DBUS_EUART0_CTS(0x0, 0x2) +#define EUART0_CTS_PA3 SILABS_DBUS_EUART0_CTS(0x0, 0x3) +#define EUART0_CTS_PA4 SILABS_DBUS_EUART0_CTS(0x0, 0x4) +#define EUART0_CTS_PA5 SILABS_DBUS_EUART0_CTS(0x0, 0x5) +#define EUART0_CTS_PA6 SILABS_DBUS_EUART0_CTS(0x0, 0x6) +#define EUART0_CTS_PA7 SILABS_DBUS_EUART0_CTS(0x0, 0x7) +#define EUART0_CTS_PA8 SILABS_DBUS_EUART0_CTS(0x0, 0x8) +#define EUART0_CTS_PB0 SILABS_DBUS_EUART0_CTS(0x1, 0x0) +#define EUART0_CTS_PB1 SILABS_DBUS_EUART0_CTS(0x1, 0x1) +#define EUART0_CTS_PB2 SILABS_DBUS_EUART0_CTS(0x1, 0x2) +#define EUART0_CTS_PB3 SILABS_DBUS_EUART0_CTS(0x1, 0x3) +#define EUART0_CTS_PB4 SILABS_DBUS_EUART0_CTS(0x1, 0x4) +#define EUART0_CTS_PC0 SILABS_DBUS_EUART0_CTS(0x2, 0x0) +#define EUART0_CTS_PC1 SILABS_DBUS_EUART0_CTS(0x2, 0x1) +#define EUART0_CTS_PC2 SILABS_DBUS_EUART0_CTS(0x2, 0x2) +#define EUART0_CTS_PC3 SILABS_DBUS_EUART0_CTS(0x2, 0x3) +#define EUART0_CTS_PC4 SILABS_DBUS_EUART0_CTS(0x2, 0x4) +#define EUART0_CTS_PC5 SILABS_DBUS_EUART0_CTS(0x2, 0x5) +#define EUART0_CTS_PC6 SILABS_DBUS_EUART0_CTS(0x2, 0x6) +#define EUART0_CTS_PC7 SILABS_DBUS_EUART0_CTS(0x2, 0x7) +#define EUART0_CTS_PD0 SILABS_DBUS_EUART0_CTS(0x3, 0x0) +#define EUART0_CTS_PD1 SILABS_DBUS_EUART0_CTS(0x3, 0x1) +#define EUART0_CTS_PD2 SILABS_DBUS_EUART0_CTS(0x3, 0x2) +#define EUART0_CTS_PD3 SILABS_DBUS_EUART0_CTS(0x3, 0x3) +#define EUART0_RX_PA0 SILABS_DBUS_EUART0_RX(0x0, 0x0) +#define EUART0_RX_PA1 SILABS_DBUS_EUART0_RX(0x0, 0x1) +#define EUART0_RX_PA2 SILABS_DBUS_EUART0_RX(0x0, 0x2) +#define EUART0_RX_PA3 SILABS_DBUS_EUART0_RX(0x0, 0x3) +#define EUART0_RX_PA4 SILABS_DBUS_EUART0_RX(0x0, 0x4) +#define EUART0_RX_PA5 SILABS_DBUS_EUART0_RX(0x0, 0x5) +#define EUART0_RX_PA6 SILABS_DBUS_EUART0_RX(0x0, 0x6) +#define EUART0_RX_PA7 SILABS_DBUS_EUART0_RX(0x0, 0x7) +#define EUART0_RX_PA8 SILABS_DBUS_EUART0_RX(0x0, 0x8) +#define EUART0_RX_PB0 SILABS_DBUS_EUART0_RX(0x1, 0x0) +#define EUART0_RX_PB1 SILABS_DBUS_EUART0_RX(0x1, 0x1) +#define EUART0_RX_PB2 SILABS_DBUS_EUART0_RX(0x1, 0x2) +#define EUART0_RX_PB3 SILABS_DBUS_EUART0_RX(0x1, 0x3) +#define EUART0_RX_PB4 SILABS_DBUS_EUART0_RX(0x1, 0x4) +#define EUART0_RX_PC0 SILABS_DBUS_EUART0_RX(0x2, 0x0) +#define EUART0_RX_PC1 SILABS_DBUS_EUART0_RX(0x2, 0x1) +#define EUART0_RX_PC2 SILABS_DBUS_EUART0_RX(0x2, 0x2) +#define EUART0_RX_PC3 SILABS_DBUS_EUART0_RX(0x2, 0x3) +#define EUART0_RX_PC4 SILABS_DBUS_EUART0_RX(0x2, 0x4) +#define EUART0_RX_PC5 SILABS_DBUS_EUART0_RX(0x2, 0x5) +#define EUART0_RX_PC6 SILABS_DBUS_EUART0_RX(0x2, 0x6) +#define EUART0_RX_PC7 SILABS_DBUS_EUART0_RX(0x2, 0x7) +#define EUART0_RX_PD0 SILABS_DBUS_EUART0_RX(0x3, 0x0) +#define EUART0_RX_PD1 SILABS_DBUS_EUART0_RX(0x3, 0x1) +#define EUART0_RX_PD2 SILABS_DBUS_EUART0_RX(0x3, 0x2) +#define EUART0_RX_PD3 SILABS_DBUS_EUART0_RX(0x3, 0x3) + +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) +#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) +#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) +#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) +#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) +#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) +#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) +#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) +#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) +#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) +#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) +#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) +#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) +#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) +#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) +#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) +#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) +#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) +#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) +#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) +#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) +#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) +#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) +#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) +#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) +#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) +#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) +#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) +#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) +#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) +#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) +#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) +#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) +#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) +#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) +#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) +#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) +#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) +#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) +#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) +#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) +#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) +#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) +#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) +#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) +#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) +#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) +#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) +#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) +#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) +#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) +#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) +#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) +#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) +#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) +#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) +#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) +#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) +#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) +#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) +#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) +#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) +#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) +#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) +#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) +#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) +#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) +#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) +#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) +#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) +#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) +#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) +#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) +#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) +#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) +#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) +#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) +#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) +#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) +#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) +#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) +#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) +#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) +#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) +#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) +#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) +#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) +#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) +#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) +#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) +#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) +#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) +#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) +#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) +#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) +#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) +#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) +#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) +#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) +#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) +#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) +#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) +#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) +#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) +#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) +#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) +#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) +#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) +#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) +#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) +#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) +#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) +#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) +#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) +#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) +#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) +#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) +#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) +#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) +#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) +#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) +#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) +#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) +#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) +#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) +#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) +#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) +#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) +#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) +#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) +#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) +#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) +#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) +#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) +#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) +#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) +#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) +#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) +#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) +#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) +#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) +#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) +#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) +#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) +#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) +#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) +#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) +#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) +#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) +#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) + +#define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0) +#define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1) +#define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2) +#define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3) +#define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4) +#define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5) +#define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6) +#define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7) +#define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8) +#define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0) +#define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1) +#define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2) +#define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3) +#define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4) +#define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0) +#define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1) +#define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2) +#define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3) +#define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4) +#define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5) +#define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6) +#define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7) +#define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0) +#define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1) +#define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2) +#define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3) +#define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0) +#define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1) +#define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2) +#define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3) +#define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4) +#define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5) +#define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6) +#define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7) +#define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8) +#define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0) +#define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1) +#define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2) +#define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3) +#define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4) +#define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0) +#define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1) +#define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2) +#define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3) +#define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4) +#define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5) +#define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6) +#define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7) +#define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0) +#define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1) +#define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2) +#define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3) +#define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0) +#define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1) +#define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2) +#define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3) +#define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4) +#define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5) +#define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6) +#define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7) +#define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8) +#define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0) +#define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1) +#define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2) +#define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3) +#define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4) +#define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0) +#define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1) +#define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2) +#define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3) +#define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4) +#define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5) +#define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6) +#define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7) +#define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0) +#define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1) +#define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2) +#define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) +#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) +#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) +#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) +#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) +#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) +#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) +#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) +#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) +#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) +#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) +#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) +#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) +#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) +#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) +#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) +#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) +#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) +#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) +#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) +#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) +#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) +#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) +#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) +#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) +#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) +#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) +#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) +#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) +#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) +#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) +#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) +#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) +#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) +#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) +#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) +#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) +#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) +#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) +#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) +#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) +#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) +#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) +#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) +#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) +#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) +#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) +#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) +#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) +#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) +#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) +#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) +#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) +#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) +#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) +#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) +#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) +#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) +#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) +#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) +#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) +#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) +#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) +#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) +#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) +#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) +#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) +#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) +#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) +#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) +#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) +#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) +#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) +#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) +#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) +#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) +#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) +#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) +#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) +#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) +#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) +#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) +#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) +#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) +#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) +#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) +#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) +#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) +#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) +#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) +#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) +#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) +#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) +#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) +#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) +#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) +#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) +#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) +#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) +#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) +#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) +#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) +#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) +#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) +#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) +#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) +#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) +#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) +#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) +#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) +#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) +#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) +#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) +#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) + +#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) +#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) +#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) +#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) +#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) +#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) +#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) +#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) +#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) +#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) +#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) +#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) +#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) +#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) +#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) +#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) +#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) +#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) +#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) +#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) +#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) +#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) +#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) +#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) +#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) +#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) +#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) +#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) +#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) +#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) +#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) +#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) +#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) +#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) +#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) +#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) +#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) +#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) +#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) +#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) +#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) +#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) +#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) +#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) +#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) +#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) +#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) +#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) +#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) +#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) +#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) +#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) +#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) +#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) +#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) +#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) +#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) +#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) +#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) +#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) +#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) +#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) +#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) +#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) +#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) +#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) +#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) +#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) +#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) +#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) +#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) +#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) +#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) +#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) +#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) +#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) +#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) +#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) +#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) +#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) +#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) +#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) +#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) +#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) +#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) +#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) +#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) +#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) +#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) +#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) +#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) +#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) +#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) +#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) +#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) +#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) +#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) +#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) +#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) +#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) +#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) +#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) +#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) +#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) +#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) +#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) +#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) +#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) + +#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) +#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) +#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) +#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) +#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) +#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) +#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) +#define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7) +#define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8) +#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) +#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) +#define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2) +#define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3) +#define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4) +#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) +#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) +#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) +#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) +#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) +#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) +#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) +#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7) +#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8) +#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) +#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) +#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2) +#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3) +#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4) +#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) +#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) +#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) +#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) +#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) +#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) +#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) +#define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7) +#define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8) +#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) +#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) +#define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2) +#define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3) +#define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4) +#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) +#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) +#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) +#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) +#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) +#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) +#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) +#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7) +#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8) +#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) +#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) +#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2) +#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3) +#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4) +#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) +#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) +#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) +#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) +#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) +#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) +#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) +#define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7) +#define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8) +#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) +#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) +#define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2) +#define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3) +#define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4) +#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) +#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) +#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) +#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) +#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) +#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) +#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) +#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7) +#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8) +#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) +#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) +#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2) +#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3) +#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h new file mode 100644 index 00000000..3bcbd132 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h @@ -0,0 +1,2703 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs XG24 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_ + +#include + +#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) + +#define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 1) + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 10, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 10, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 10, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 10, 0, 0, 1) + +#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 21, 1, 0, 1) +#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 21, 1, 1, 3) +#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 21, 1, 2, 4) +#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 21, 1, 3, 5) +#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 21, 1, 4, 6) +#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 21, 0, 0, 2) + +#define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 29, 1, 0, 1) +#define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 29, 1, 1, 3) +#define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 29, 1, 2, 4) +#define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 29, 1, 3, 5) +#define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 29, 1, 4, 6) +#define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 29, 0, 0, 2) + +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 37, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 37, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 37, 1, 2, 3) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 42, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 42, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 46, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 46, 1, 1, 2) + +#define SILABS_DBUS_KEYSCAN_COLOUT0(port, pin) SILABS_DBUS(port, pin, 50, 1, 0, 1) +#define SILABS_DBUS_KEYSCAN_COLOUT1(port, pin) SILABS_DBUS(port, pin, 50, 1, 1, 2) +#define SILABS_DBUS_KEYSCAN_COLOUT2(port, pin) SILABS_DBUS(port, pin, 50, 1, 2, 3) +#define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 50, 1, 3, 4) +#define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 50, 1, 4, 5) +#define SILABS_DBUS_KEYSCAN_COLOUT5(port, pin) SILABS_DBUS(port, pin, 50, 1, 5, 6) +#define SILABS_DBUS_KEYSCAN_COLOUT6(port, pin) SILABS_DBUS(port, pin, 50, 1, 6, 7) +#define SILABS_DBUS_KEYSCAN_COLOUT7(port, pin) SILABS_DBUS(port, pin, 50, 1, 7, 8) +#define SILABS_DBUS_KEYSCAN_ROWSENSE0(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 9) +#define SILABS_DBUS_KEYSCAN_ROWSENSE1(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 10) +#define SILABS_DBUS_KEYSCAN_ROWSENSE2(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 11) +#define SILABS_DBUS_KEYSCAN_ROWSENSE3(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 12) +#define SILABS_DBUS_KEYSCAN_ROWSENSE4(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 13) +#define SILABS_DBUS_KEYSCAN_ROWSENSE5(port, pin) SILABS_DBUS(port, pin, 50, 0, 0, 14) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 66, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 66, 1, 1, 2) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 70, 1, 1, 2) +#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 70, 1, 2, 3) +#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4) +#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5) +#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 70, 1, 5, 6) +#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 70, 1, 6, 7) +#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 70, 1, 7, 8) +#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 70, 1, 8, 9) +#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 70, 1, 9, 10) +#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 70, 1, 10, 11) +#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 70, 1, 11, 12) +#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 70, 1, 12, 13) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 70, 1, 13, 14) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 70, 1, 14, 16) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 15) + +#define SILABS_DBUS_PCNT0_S0IN(port, pin) SILABS_DBUS(port, pin, 89, 0, 0, 0) +#define SILABS_DBUS_PCNT0_S1IN(port, pin) SILABS_DBUS(port, pin, 89, 0, 0, 1) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 92, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 92, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 92, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 92, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 92, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 92, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 92, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 92, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 92, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 92, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 92, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 92, 1, 11, 12) +#define SILABS_DBUS_PRS0_ASYNCH12(port, pin) SILABS_DBUS(port, pin, 92, 1, 12, 13) +#define SILABS_DBUS_PRS0_ASYNCH13(port, pin) SILABS_DBUS(port, pin, 92, 1, 13, 14) +#define SILABS_DBUS_PRS0_ASYNCH14(port, pin) SILABS_DBUS(port, pin, 92, 1, 14, 15) +#define SILABS_DBUS_PRS0_ASYNCH15(port, pin) SILABS_DBUS(port, pin, 92, 1, 15, 16) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 92, 1, 16, 17) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 92, 1, 17, 18) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 92, 1, 18, 19) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 92, 1, 19, 20) + +#define SILABS_DBUS_RAC_LNAEN(port, pin) SILABS_DBUS(port, pin, 114, 1, 0, 1) +#define SILABS_DBUS_RAC_PAEN(port, pin) SILABS_DBUS(port, pin, 114, 1, 1, 2) + +#define SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(port, pin) SILABS_DBUS(port, pin, 142, 0, 0, 0) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 144, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 144, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 144, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 144, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 144, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 144, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 152, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 152, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 152, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 152, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 152, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 152, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 160, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 160, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 160, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 160, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 160, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 160, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 168, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 168, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 168, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 168, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 168, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 168, 1, 5, 6) + +#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 176, 1, 0, 1) +#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 176, 1, 1, 2) +#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 176, 1, 2, 3) +#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 176, 1, 3, 4) +#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 176, 1, 4, 5) +#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 176, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 184, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 184, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 184, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 184, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 184, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 184, 0, 0, 2) + +#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) +#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) +#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) +#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) +#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) +#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) +#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) +#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7) +#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8) +#define ACMP0_ACMPOUT_PA9 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x9) +#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) +#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) +#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2) +#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3) +#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4) +#define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5) +#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) +#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) +#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) +#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) +#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) +#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) +#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6) +#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7) +#define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8) +#define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9) +#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) +#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) +#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) +#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) +#define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4) +#define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5) + +#define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0) +#define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1) +#define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2) +#define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3) +#define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4) +#define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5) +#define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6) +#define ACMP1_ACMPOUT_PA7 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x7) +#define ACMP1_ACMPOUT_PA8 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x8) +#define ACMP1_ACMPOUT_PA9 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x9) +#define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0) +#define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1) +#define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2) +#define ACMP1_ACMPOUT_PB3 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x3) +#define ACMP1_ACMPOUT_PB4 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x4) +#define ACMP1_ACMPOUT_PB5 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x5) +#define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0) +#define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1) +#define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2) +#define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3) +#define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4) +#define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5) +#define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6) +#define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7) +#define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8) +#define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9) +#define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0) +#define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1) +#define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2) +#define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3) +#define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4) +#define ACMP1_ACMPOUT_PD5 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x5) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) +#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) +#define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8) +#define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4) +#define CMU_CLKOUT0_PD5 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x5) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) +#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) +#define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8) +#define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4) +#define CMU_CLKOUT1_PD5 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x5) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) +#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) +#define CMU_CLKOUT2_PA9 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x9) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) +#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) +#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) +#define CMU_CLKOUT2_PB5 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x5) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) +#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) +#define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8) +#define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) +#define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4) +#define CMU_CLKIN0_PD5 SILABS_DBUS_CMU_CLKIN0(0x3, 0x5) + +#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0) +#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1) +#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2) +#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3) +#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4) +#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5) +#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6) +#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7) +#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8) +#define EUSART0_CS_PA9 SILABS_DBUS_EUSART0_CS(0x0, 0x9) +#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0) +#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1) +#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2) +#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3) +#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4) +#define EUSART0_CS_PB5 SILABS_DBUS_EUSART0_CS(0x1, 0x5) +#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0) +#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1) +#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2) +#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3) +#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4) +#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5) +#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6) +#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7) +#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8) +#define EUSART0_RTS_PA9 SILABS_DBUS_EUSART0_RTS(0x0, 0x9) +#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0) +#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1) +#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2) +#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3) +#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4) +#define EUSART0_RTS_PB5 SILABS_DBUS_EUSART0_RTS(0x1, 0x5) +#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0) +#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1) +#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2) +#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3) +#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4) +#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5) +#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6) +#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7) +#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8) +#define EUSART0_RX_PA9 SILABS_DBUS_EUSART0_RX(0x0, 0x9) +#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0) +#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1) +#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2) +#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3) +#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4) +#define EUSART0_RX_PB5 SILABS_DBUS_EUSART0_RX(0x1, 0x5) +#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0) +#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1) +#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2) +#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3) +#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4) +#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5) +#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6) +#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7) +#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8) +#define EUSART0_SCLK_PA9 SILABS_DBUS_EUSART0_SCLK(0x0, 0x9) +#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0) +#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1) +#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2) +#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3) +#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4) +#define EUSART0_SCLK_PB5 SILABS_DBUS_EUSART0_SCLK(0x1, 0x5) +#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0) +#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1) +#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2) +#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3) +#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4) +#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5) +#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6) +#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7) +#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8) +#define EUSART0_TX_PA9 SILABS_DBUS_EUSART0_TX(0x0, 0x9) +#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0) +#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1) +#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2) +#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3) +#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4) +#define EUSART0_TX_PB5 SILABS_DBUS_EUSART0_TX(0x1, 0x5) +#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0) +#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1) +#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2) +#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3) +#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4) +#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5) +#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6) +#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7) +#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8) +#define EUSART0_CTS_PA9 SILABS_DBUS_EUSART0_CTS(0x0, 0x9) +#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0) +#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1) +#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2) +#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3) +#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4) +#define EUSART0_CTS_PB5 SILABS_DBUS_EUSART0_CTS(0x1, 0x5) + +#define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0) +#define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1) +#define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2) +#define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3) +#define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4) +#define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5) +#define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6) +#define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7) +#define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8) +#define EUSART1_CS_PA9 SILABS_DBUS_EUSART1_CS(0x0, 0x9) +#define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0) +#define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1) +#define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2) +#define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3) +#define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4) +#define EUSART1_CS_PB5 SILABS_DBUS_EUSART1_CS(0x1, 0x5) +#define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0) +#define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1) +#define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2) +#define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3) +#define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4) +#define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5) +#define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6) +#define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7) +#define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8) +#define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9) +#define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0) +#define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1) +#define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2) +#define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3) +#define EUSART1_CS_PD4 SILABS_DBUS_EUSART1_CS(0x3, 0x4) +#define EUSART1_CS_PD5 SILABS_DBUS_EUSART1_CS(0x3, 0x5) +#define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0) +#define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1) +#define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2) +#define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3) +#define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4) +#define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5) +#define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6) +#define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7) +#define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8) +#define EUSART1_RTS_PA9 SILABS_DBUS_EUSART1_RTS(0x0, 0x9) +#define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0) +#define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1) +#define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2) +#define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3) +#define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4) +#define EUSART1_RTS_PB5 SILABS_DBUS_EUSART1_RTS(0x1, 0x5) +#define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0) +#define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1) +#define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2) +#define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3) +#define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4) +#define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5) +#define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6) +#define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7) +#define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8) +#define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9) +#define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0) +#define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1) +#define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2) +#define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3) +#define EUSART1_RTS_PD4 SILABS_DBUS_EUSART1_RTS(0x3, 0x4) +#define EUSART1_RTS_PD5 SILABS_DBUS_EUSART1_RTS(0x3, 0x5) +#define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0) +#define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1) +#define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2) +#define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3) +#define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4) +#define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5) +#define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6) +#define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7) +#define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8) +#define EUSART1_RX_PA9 SILABS_DBUS_EUSART1_RX(0x0, 0x9) +#define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0) +#define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1) +#define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2) +#define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3) +#define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4) +#define EUSART1_RX_PB5 SILABS_DBUS_EUSART1_RX(0x1, 0x5) +#define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0) +#define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1) +#define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2) +#define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3) +#define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4) +#define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5) +#define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6) +#define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7) +#define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8) +#define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9) +#define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0) +#define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1) +#define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2) +#define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3) +#define EUSART1_RX_PD4 SILABS_DBUS_EUSART1_RX(0x3, 0x4) +#define EUSART1_RX_PD5 SILABS_DBUS_EUSART1_RX(0x3, 0x5) +#define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0) +#define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1) +#define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2) +#define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3) +#define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4) +#define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5) +#define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6) +#define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7) +#define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8) +#define EUSART1_SCLK_PA9 SILABS_DBUS_EUSART1_SCLK(0x0, 0x9) +#define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0) +#define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1) +#define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2) +#define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3) +#define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4) +#define EUSART1_SCLK_PB5 SILABS_DBUS_EUSART1_SCLK(0x1, 0x5) +#define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0) +#define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1) +#define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2) +#define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3) +#define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4) +#define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5) +#define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6) +#define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7) +#define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8) +#define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9) +#define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0) +#define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1) +#define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2) +#define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3) +#define EUSART1_SCLK_PD4 SILABS_DBUS_EUSART1_SCLK(0x3, 0x4) +#define EUSART1_SCLK_PD5 SILABS_DBUS_EUSART1_SCLK(0x3, 0x5) +#define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0) +#define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1) +#define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2) +#define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3) +#define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4) +#define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5) +#define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6) +#define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7) +#define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8) +#define EUSART1_TX_PA9 SILABS_DBUS_EUSART1_TX(0x0, 0x9) +#define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0) +#define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1) +#define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2) +#define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3) +#define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4) +#define EUSART1_TX_PB5 SILABS_DBUS_EUSART1_TX(0x1, 0x5) +#define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0) +#define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1) +#define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2) +#define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3) +#define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4) +#define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5) +#define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6) +#define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7) +#define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8) +#define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9) +#define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0) +#define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1) +#define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2) +#define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3) +#define EUSART1_TX_PD4 SILABS_DBUS_EUSART1_TX(0x3, 0x4) +#define EUSART1_TX_PD5 SILABS_DBUS_EUSART1_TX(0x3, 0x5) +#define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0) +#define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1) +#define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2) +#define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3) +#define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4) +#define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5) +#define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6) +#define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7) +#define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8) +#define EUSART1_CTS_PA9 SILABS_DBUS_EUSART1_CTS(0x0, 0x9) +#define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0) +#define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1) +#define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2) +#define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3) +#define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4) +#define EUSART1_CTS_PB5 SILABS_DBUS_EUSART1_CTS(0x1, 0x5) +#define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0) +#define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1) +#define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2) +#define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3) +#define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4) +#define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5) +#define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6) +#define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7) +#define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8) +#define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9) +#define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0) +#define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1) +#define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2) +#define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3) +#define EUSART1_CTS_PD4 SILABS_DBUS_EUSART1_CTS(0x3, 0x4) +#define EUSART1_CTS_PD5 SILABS_DBUS_EUSART1_CTS(0x3, 0x5) + +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) +#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) +#define PTI_DCLK_PC8 SILABS_DBUS_PTI_DCLK(0x2, 0x8) +#define PTI_DCLK_PC9 SILABS_DBUS_PTI_DCLK(0x2, 0x9) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DCLK_PD4 SILABS_DBUS_PTI_DCLK(0x3, 0x4) +#define PTI_DCLK_PD5 SILABS_DBUS_PTI_DCLK(0x3, 0x5) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) +#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) +#define PTI_DFRAME_PC8 SILABS_DBUS_PTI_DFRAME(0x2, 0x8) +#define PTI_DFRAME_PC9 SILABS_DBUS_PTI_DFRAME(0x2, 0x9) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DFRAME_PD4 SILABS_DBUS_PTI_DFRAME(0x3, 0x4) +#define PTI_DFRAME_PD5 SILABS_DBUS_PTI_DFRAME(0x3, 0x5) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) +#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) +#define PTI_DOUT_PC8 SILABS_DBUS_PTI_DOUT(0x2, 0x8) +#define PTI_DOUT_PC9 SILABS_DBUS_PTI_DOUT(0x2, 0x9) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) +#define PTI_DOUT_PD4 SILABS_DBUS_PTI_DOUT(0x3, 0x4) +#define PTI_DOUT_PD5 SILABS_DBUS_PTI_DOUT(0x3, 0x5) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) +#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) +#define I2C0_SCL_PA9 SILABS_DBUS_I2C0_SCL(0x0, 0x9) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) +#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) +#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) +#define I2C0_SCL_PB5 SILABS_DBUS_I2C0_SCL(0x1, 0x5) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) +#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) +#define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8) +#define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4) +#define I2C0_SCL_PD5 SILABS_DBUS_I2C0_SCL(0x3, 0x5) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) +#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) +#define I2C0_SDA_PA9 SILABS_DBUS_I2C0_SDA(0x0, 0x9) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) +#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) +#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) +#define I2C0_SDA_PB5 SILABS_DBUS_I2C0_SDA(0x1, 0x5) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) +#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) +#define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8) +#define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) +#define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4) +#define I2C0_SDA_PD5 SILABS_DBUS_I2C0_SDA(0x3, 0x5) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) +#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) +#define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8) +#define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4) +#define I2C1_SCL_PD5 SILABS_DBUS_I2C1_SCL(0x3, 0x5) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) +#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) +#define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8) +#define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) +#define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4) +#define I2C1_SDA_PD5 SILABS_DBUS_I2C1_SDA(0x3, 0x5) + +#define KEYSCAN_COLOUT0_PA0 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x0) +#define KEYSCAN_COLOUT0_PA1 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x1) +#define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2) +#define KEYSCAN_COLOUT0_PA3 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x3) +#define KEYSCAN_COLOUT0_PA4 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x4) +#define KEYSCAN_COLOUT0_PA5 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x5) +#define KEYSCAN_COLOUT0_PA6 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x6) +#define KEYSCAN_COLOUT0_PA7 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x7) +#define KEYSCAN_COLOUT0_PA8 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x8) +#define KEYSCAN_COLOUT0_PA9 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x9) +#define KEYSCAN_COLOUT0_PB0 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x0) +#define KEYSCAN_COLOUT0_PB1 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x1) +#define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2) +#define KEYSCAN_COLOUT0_PB3 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x3) +#define KEYSCAN_COLOUT0_PB4 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x4) +#define KEYSCAN_COLOUT0_PB5 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x5) +#define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0) +#define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1) +#define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2) +#define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3) +#define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4) +#define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5) +#define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6) +#define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7) +#define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8) +#define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9) +#define KEYSCAN_COLOUT0_PD0 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x0) +#define KEYSCAN_COLOUT0_PD1 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x1) +#define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2) +#define KEYSCAN_COLOUT0_PD3 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x3) +#define KEYSCAN_COLOUT0_PD4 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x4) +#define KEYSCAN_COLOUT0_PD5 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x5) +#define KEYSCAN_COLOUT1_PA0 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x0) +#define KEYSCAN_COLOUT1_PA1 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x1) +#define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2) +#define KEYSCAN_COLOUT1_PA3 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x3) +#define KEYSCAN_COLOUT1_PA4 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x4) +#define KEYSCAN_COLOUT1_PA5 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x5) +#define KEYSCAN_COLOUT1_PA6 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x6) +#define KEYSCAN_COLOUT1_PA7 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x7) +#define KEYSCAN_COLOUT1_PA8 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x8) +#define KEYSCAN_COLOUT1_PA9 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x9) +#define KEYSCAN_COLOUT1_PB0 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x0) +#define KEYSCAN_COLOUT1_PB1 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x1) +#define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2) +#define KEYSCAN_COLOUT1_PB3 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x3) +#define KEYSCAN_COLOUT1_PB4 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x4) +#define KEYSCAN_COLOUT1_PB5 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x5) +#define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0) +#define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1) +#define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2) +#define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3) +#define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4) +#define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5) +#define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6) +#define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7) +#define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8) +#define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9) +#define KEYSCAN_COLOUT1_PD0 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x0) +#define KEYSCAN_COLOUT1_PD1 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x1) +#define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2) +#define KEYSCAN_COLOUT1_PD3 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x3) +#define KEYSCAN_COLOUT1_PD4 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x4) +#define KEYSCAN_COLOUT1_PD5 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x5) +#define KEYSCAN_COLOUT2_PA0 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x0) +#define KEYSCAN_COLOUT2_PA1 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x1) +#define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2) +#define KEYSCAN_COLOUT2_PA3 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x3) +#define KEYSCAN_COLOUT2_PA4 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x4) +#define KEYSCAN_COLOUT2_PA5 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x5) +#define KEYSCAN_COLOUT2_PA6 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x6) +#define KEYSCAN_COLOUT2_PA7 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x7) +#define KEYSCAN_COLOUT2_PA8 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x8) +#define KEYSCAN_COLOUT2_PA9 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x9) +#define KEYSCAN_COLOUT2_PB0 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x0) +#define KEYSCAN_COLOUT2_PB1 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x1) +#define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2) +#define KEYSCAN_COLOUT2_PB3 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x3) +#define KEYSCAN_COLOUT2_PB4 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x4) +#define KEYSCAN_COLOUT2_PB5 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x5) +#define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0) +#define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1) +#define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2) +#define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3) +#define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4) +#define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5) +#define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6) +#define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7) +#define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8) +#define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9) +#define KEYSCAN_COLOUT2_PD0 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x0) +#define KEYSCAN_COLOUT2_PD1 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x1) +#define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2) +#define KEYSCAN_COLOUT2_PD3 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x3) +#define KEYSCAN_COLOUT2_PD4 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x4) +#define KEYSCAN_COLOUT2_PD5 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x5) +#define KEYSCAN_COLOUT3_PA0 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x0) +#define KEYSCAN_COLOUT3_PA1 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x1) +#define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2) +#define KEYSCAN_COLOUT3_PA3 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x3) +#define KEYSCAN_COLOUT3_PA4 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x4) +#define KEYSCAN_COLOUT3_PA5 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x5) +#define KEYSCAN_COLOUT3_PA6 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x6) +#define KEYSCAN_COLOUT3_PA7 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x7) +#define KEYSCAN_COLOUT3_PA8 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x8) +#define KEYSCAN_COLOUT3_PA9 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x9) +#define KEYSCAN_COLOUT3_PB0 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x0) +#define KEYSCAN_COLOUT3_PB1 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x1) +#define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2) +#define KEYSCAN_COLOUT3_PB3 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x3) +#define KEYSCAN_COLOUT3_PB4 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x4) +#define KEYSCAN_COLOUT3_PB5 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x5) +#define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0) +#define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1) +#define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2) +#define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3) +#define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4) +#define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5) +#define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6) +#define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7) +#define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8) +#define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9) +#define KEYSCAN_COLOUT3_PD0 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x0) +#define KEYSCAN_COLOUT3_PD1 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x1) +#define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2) +#define KEYSCAN_COLOUT3_PD3 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x3) +#define KEYSCAN_COLOUT3_PD4 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x4) +#define KEYSCAN_COLOUT3_PD5 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x5) +#define KEYSCAN_COLOUT4_PA0 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x0) +#define KEYSCAN_COLOUT4_PA1 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x1) +#define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2) +#define KEYSCAN_COLOUT4_PA3 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x3) +#define KEYSCAN_COLOUT4_PA4 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x4) +#define KEYSCAN_COLOUT4_PA5 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x5) +#define KEYSCAN_COLOUT4_PA6 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x6) +#define KEYSCAN_COLOUT4_PA7 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x7) +#define KEYSCAN_COLOUT4_PA8 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x8) +#define KEYSCAN_COLOUT4_PA9 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x9) +#define KEYSCAN_COLOUT4_PB0 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x0) +#define KEYSCAN_COLOUT4_PB1 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x1) +#define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2) +#define KEYSCAN_COLOUT4_PB3 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x3) +#define KEYSCAN_COLOUT4_PB4 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x4) +#define KEYSCAN_COLOUT4_PB5 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x5) +#define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0) +#define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1) +#define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2) +#define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3) +#define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4) +#define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5) +#define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6) +#define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7) +#define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8) +#define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9) +#define KEYSCAN_COLOUT4_PD0 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x0) +#define KEYSCAN_COLOUT4_PD1 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x1) +#define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2) +#define KEYSCAN_COLOUT4_PD3 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x3) +#define KEYSCAN_COLOUT4_PD4 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x4) +#define KEYSCAN_COLOUT4_PD5 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x5) +#define KEYSCAN_COLOUT5_PA0 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x0) +#define KEYSCAN_COLOUT5_PA1 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x1) +#define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2) +#define KEYSCAN_COLOUT5_PA3 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x3) +#define KEYSCAN_COLOUT5_PA4 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x4) +#define KEYSCAN_COLOUT5_PA5 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x5) +#define KEYSCAN_COLOUT5_PA6 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x6) +#define KEYSCAN_COLOUT5_PA7 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x7) +#define KEYSCAN_COLOUT5_PA8 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x8) +#define KEYSCAN_COLOUT5_PA9 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x9) +#define KEYSCAN_COLOUT5_PB0 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x0) +#define KEYSCAN_COLOUT5_PB1 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x1) +#define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2) +#define KEYSCAN_COLOUT5_PB3 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x3) +#define KEYSCAN_COLOUT5_PB4 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x4) +#define KEYSCAN_COLOUT5_PB5 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x5) +#define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0) +#define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1) +#define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2) +#define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3) +#define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4) +#define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5) +#define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6) +#define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7) +#define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8) +#define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9) +#define KEYSCAN_COLOUT5_PD0 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x0) +#define KEYSCAN_COLOUT5_PD1 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x1) +#define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2) +#define KEYSCAN_COLOUT5_PD3 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x3) +#define KEYSCAN_COLOUT5_PD4 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x4) +#define KEYSCAN_COLOUT5_PD5 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x5) +#define KEYSCAN_COLOUT6_PA0 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x0) +#define KEYSCAN_COLOUT6_PA1 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x1) +#define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2) +#define KEYSCAN_COLOUT6_PA3 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x3) +#define KEYSCAN_COLOUT6_PA4 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x4) +#define KEYSCAN_COLOUT6_PA5 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x5) +#define KEYSCAN_COLOUT6_PA6 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x6) +#define KEYSCAN_COLOUT6_PA7 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x7) +#define KEYSCAN_COLOUT6_PA8 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x8) +#define KEYSCAN_COLOUT6_PA9 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x9) +#define KEYSCAN_COLOUT6_PB0 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x0) +#define KEYSCAN_COLOUT6_PB1 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x1) +#define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2) +#define KEYSCAN_COLOUT6_PB3 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x3) +#define KEYSCAN_COLOUT6_PB4 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x4) +#define KEYSCAN_COLOUT6_PB5 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x5) +#define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0) +#define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1) +#define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2) +#define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3) +#define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4) +#define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5) +#define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6) +#define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7) +#define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8) +#define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9) +#define KEYSCAN_COLOUT6_PD0 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x0) +#define KEYSCAN_COLOUT6_PD1 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x1) +#define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2) +#define KEYSCAN_COLOUT6_PD3 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x3) +#define KEYSCAN_COLOUT6_PD4 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x4) +#define KEYSCAN_COLOUT6_PD5 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x5) +#define KEYSCAN_COLOUT7_PA0 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x0) +#define KEYSCAN_COLOUT7_PA1 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x1) +#define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2) +#define KEYSCAN_COLOUT7_PA3 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x3) +#define KEYSCAN_COLOUT7_PA4 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x4) +#define KEYSCAN_COLOUT7_PA5 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x5) +#define KEYSCAN_COLOUT7_PA6 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x6) +#define KEYSCAN_COLOUT7_PA7 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x7) +#define KEYSCAN_COLOUT7_PA8 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x8) +#define KEYSCAN_COLOUT7_PA9 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x9) +#define KEYSCAN_COLOUT7_PB0 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x0) +#define KEYSCAN_COLOUT7_PB1 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x1) +#define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2) +#define KEYSCAN_COLOUT7_PB3 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x3) +#define KEYSCAN_COLOUT7_PB4 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x4) +#define KEYSCAN_COLOUT7_PB5 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x5) +#define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0) +#define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1) +#define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2) +#define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3) +#define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4) +#define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5) +#define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6) +#define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7) +#define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8) +#define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9) +#define KEYSCAN_COLOUT7_PD0 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x0) +#define KEYSCAN_COLOUT7_PD1 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x1) +#define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2) +#define KEYSCAN_COLOUT7_PD3 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x3) +#define KEYSCAN_COLOUT7_PD4 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x4) +#define KEYSCAN_COLOUT7_PD5 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x5) +#define KEYSCAN_ROWSENSE0_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x0) +#define KEYSCAN_ROWSENSE0_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x1) +#define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2) +#define KEYSCAN_ROWSENSE0_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x3) +#define KEYSCAN_ROWSENSE0_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x4) +#define KEYSCAN_ROWSENSE0_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x5) +#define KEYSCAN_ROWSENSE0_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x6) +#define KEYSCAN_ROWSENSE0_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x7) +#define KEYSCAN_ROWSENSE0_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x8) +#define KEYSCAN_ROWSENSE0_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x9) +#define KEYSCAN_ROWSENSE0_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x0) +#define KEYSCAN_ROWSENSE0_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x1) +#define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2) +#define KEYSCAN_ROWSENSE0_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x3) +#define KEYSCAN_ROWSENSE0_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x4) +#define KEYSCAN_ROWSENSE0_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x5) +#define KEYSCAN_ROWSENSE1_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x0) +#define KEYSCAN_ROWSENSE1_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x1) +#define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2) +#define KEYSCAN_ROWSENSE1_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x3) +#define KEYSCAN_ROWSENSE1_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x4) +#define KEYSCAN_ROWSENSE1_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x5) +#define KEYSCAN_ROWSENSE1_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x6) +#define KEYSCAN_ROWSENSE1_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x7) +#define KEYSCAN_ROWSENSE1_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x8) +#define KEYSCAN_ROWSENSE1_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x9) +#define KEYSCAN_ROWSENSE1_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x0) +#define KEYSCAN_ROWSENSE1_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x1) +#define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2) +#define KEYSCAN_ROWSENSE1_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x3) +#define KEYSCAN_ROWSENSE1_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x4) +#define KEYSCAN_ROWSENSE1_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x5) +#define KEYSCAN_ROWSENSE2_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x0) +#define KEYSCAN_ROWSENSE2_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x1) +#define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2) +#define KEYSCAN_ROWSENSE2_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x3) +#define KEYSCAN_ROWSENSE2_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x4) +#define KEYSCAN_ROWSENSE2_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x5) +#define KEYSCAN_ROWSENSE2_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x6) +#define KEYSCAN_ROWSENSE2_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x7) +#define KEYSCAN_ROWSENSE2_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x8) +#define KEYSCAN_ROWSENSE2_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x9) +#define KEYSCAN_ROWSENSE2_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x0) +#define KEYSCAN_ROWSENSE2_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x1) +#define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2) +#define KEYSCAN_ROWSENSE2_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x3) +#define KEYSCAN_ROWSENSE2_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x4) +#define KEYSCAN_ROWSENSE2_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x5) +#define KEYSCAN_ROWSENSE3_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x0) +#define KEYSCAN_ROWSENSE3_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x1) +#define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2) +#define KEYSCAN_ROWSENSE3_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x3) +#define KEYSCAN_ROWSENSE3_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x4) +#define KEYSCAN_ROWSENSE3_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x5) +#define KEYSCAN_ROWSENSE3_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x6) +#define KEYSCAN_ROWSENSE3_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x7) +#define KEYSCAN_ROWSENSE3_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x8) +#define KEYSCAN_ROWSENSE3_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x9) +#define KEYSCAN_ROWSENSE3_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x0) +#define KEYSCAN_ROWSENSE3_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x1) +#define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2) +#define KEYSCAN_ROWSENSE3_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x3) +#define KEYSCAN_ROWSENSE3_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x4) +#define KEYSCAN_ROWSENSE3_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x5) +#define KEYSCAN_ROWSENSE4_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x0) +#define KEYSCAN_ROWSENSE4_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x1) +#define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2) +#define KEYSCAN_ROWSENSE4_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x3) +#define KEYSCAN_ROWSENSE4_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x4) +#define KEYSCAN_ROWSENSE4_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x5) +#define KEYSCAN_ROWSENSE4_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x6) +#define KEYSCAN_ROWSENSE4_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x7) +#define KEYSCAN_ROWSENSE4_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x8) +#define KEYSCAN_ROWSENSE4_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x9) +#define KEYSCAN_ROWSENSE4_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x0) +#define KEYSCAN_ROWSENSE4_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x1) +#define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2) +#define KEYSCAN_ROWSENSE4_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x3) +#define KEYSCAN_ROWSENSE4_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x4) +#define KEYSCAN_ROWSENSE4_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x5) +#define KEYSCAN_ROWSENSE5_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x0) +#define KEYSCAN_ROWSENSE5_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x1) +#define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2) +#define KEYSCAN_ROWSENSE5_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x3) +#define KEYSCAN_ROWSENSE5_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x4) +#define KEYSCAN_ROWSENSE5_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x5) +#define KEYSCAN_ROWSENSE5_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x6) +#define KEYSCAN_ROWSENSE5_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x7) +#define KEYSCAN_ROWSENSE5_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x8) +#define KEYSCAN_ROWSENSE5_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x9) +#define KEYSCAN_ROWSENSE5_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x0) +#define KEYSCAN_ROWSENSE5_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x1) +#define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2) +#define KEYSCAN_ROWSENSE5_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x3) +#define KEYSCAN_ROWSENSE5_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x4) +#define KEYSCAN_ROWSENSE5_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x5) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) +#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) +#define LETIMER0_OUT0_PA9 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x9) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) +#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) +#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) +#define LETIMER0_OUT0_PB5 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x5) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) +#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) +#define LETIMER0_OUT1_PA9 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x9) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) +#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) +#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) +#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) +#define LETIMER0_OUT1_PB5 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x5) + +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) +#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) +#define MODEM_ANT0_PA9 SILABS_DBUS_MODEM_ANT0(0x0, 0x9) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) +#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) +#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) +#define MODEM_ANT0_PB5 SILABS_DBUS_MODEM_ANT0(0x1, 0x5) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) +#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) +#define MODEM_ANT0_PC8 SILABS_DBUS_MODEM_ANT0(0x2, 0x8) +#define MODEM_ANT0_PC9 SILABS_DBUS_MODEM_ANT0(0x2, 0x9) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT0_PD4 SILABS_DBUS_MODEM_ANT0(0x3, 0x4) +#define MODEM_ANT0_PD5 SILABS_DBUS_MODEM_ANT0(0x3, 0x5) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) +#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) +#define MODEM_ANT1_PA9 SILABS_DBUS_MODEM_ANT1(0x0, 0x9) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) +#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) +#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) +#define MODEM_ANT1_PB5 SILABS_DBUS_MODEM_ANT1(0x1, 0x5) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) +#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) +#define MODEM_ANT1_PC8 SILABS_DBUS_MODEM_ANT1(0x2, 0x8) +#define MODEM_ANT1_PC9 SILABS_DBUS_MODEM_ANT1(0x2, 0x9) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANT1_PD4 SILABS_DBUS_MODEM_ANT1(0x3, 0x4) +#define MODEM_ANT1_PD5 SILABS_DBUS_MODEM_ANT1(0x3, 0x5) +#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) +#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) +#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) +#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) +#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) +#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) +#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) +#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) +#define MODEM_ANTROLLOVER_PC8 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x8) +#define MODEM_ANTROLLOVER_PC9 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x9) +#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) +#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) +#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) +#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) +#define MODEM_ANTROLLOVER_PD4 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x4) +#define MODEM_ANTROLLOVER_PD5 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x5) +#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) +#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) +#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) +#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) +#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) +#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) +#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) +#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) +#define MODEM_ANTRR0_PC8 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x8) +#define MODEM_ANTRR0_PC9 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x9) +#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) +#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) +#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) +#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) +#define MODEM_ANTRR0_PD4 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x4) +#define MODEM_ANTRR0_PD5 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x5) +#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) +#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) +#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) +#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) +#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) +#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) +#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) +#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) +#define MODEM_ANTRR1_PC8 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x8) +#define MODEM_ANTRR1_PC9 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x9) +#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) +#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) +#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) +#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) +#define MODEM_ANTRR1_PD4 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x4) +#define MODEM_ANTRR1_PD5 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x5) +#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) +#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) +#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) +#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) +#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) +#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) +#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) +#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) +#define MODEM_ANTRR2_PC8 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x8) +#define MODEM_ANTRR2_PC9 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x9) +#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) +#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) +#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) +#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) +#define MODEM_ANTRR2_PD4 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x4) +#define MODEM_ANTRR2_PD5 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x5) +#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) +#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) +#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) +#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) +#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) +#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) +#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) +#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) +#define MODEM_ANTRR3_PC8 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x8) +#define MODEM_ANTRR3_PC9 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x9) +#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) +#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) +#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) +#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) +#define MODEM_ANTRR3_PD4 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x4) +#define MODEM_ANTRR3_PD5 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x5) +#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) +#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) +#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) +#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) +#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) +#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) +#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) +#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) +#define MODEM_ANTRR4_PC8 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x8) +#define MODEM_ANTRR4_PC9 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x9) +#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) +#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) +#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) +#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) +#define MODEM_ANTRR4_PD4 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x4) +#define MODEM_ANTRR4_PD5 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x5) +#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) +#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) +#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) +#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) +#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) +#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) +#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) +#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) +#define MODEM_ANTRR5_PC8 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x8) +#define MODEM_ANTRR5_PC9 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x9) +#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) +#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) +#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) +#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) +#define MODEM_ANTRR5_PD4 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x4) +#define MODEM_ANTRR5_PD5 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x5) +#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) +#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) +#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) +#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) +#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) +#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) +#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) +#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) +#define MODEM_ANTSWEN_PC8 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x8) +#define MODEM_ANTSWEN_PC9 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x9) +#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) +#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) +#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) +#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) +#define MODEM_ANTSWEN_PD4 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x4) +#define MODEM_ANTSWEN_PD5 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x5) +#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) +#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) +#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) +#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) +#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) +#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) +#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) +#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) +#define MODEM_ANTSWUS_PC8 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x8) +#define MODEM_ANTSWUS_PC9 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x9) +#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) +#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) +#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) +#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) +#define MODEM_ANTSWUS_PD4 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x4) +#define MODEM_ANTSWUS_PD5 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x5) +#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) +#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) +#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) +#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) +#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) +#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) +#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) +#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) +#define MODEM_ANTTRIG_PC8 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x8) +#define MODEM_ANTTRIG_PC9 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x9) +#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) +#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) +#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) +#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) +#define MODEM_ANTTRIG_PD4 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x4) +#define MODEM_ANTTRIG_PD5 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x5) +#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) +#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) +#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) +#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) +#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) +#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) +#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) +#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) +#define MODEM_ANTTRIGSTOP_PC8 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x8) +#define MODEM_ANTTRIGSTOP_PC9 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x9) +#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) +#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) +#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) +#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) +#define MODEM_ANTTRIGSTOP_PD4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x4) +#define MODEM_ANTTRIGSTOP_PD5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x5) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) +#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) +#define MODEM_DCLK_PA9 SILABS_DBUS_MODEM_DCLK(0x0, 0x9) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) +#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) +#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) +#define MODEM_DCLK_PB5 SILABS_DBUS_MODEM_DCLK(0x1, 0x5) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) +#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) +#define MODEM_DOUT_PA9 SILABS_DBUS_MODEM_DOUT(0x0, 0x9) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) +#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) +#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) +#define MODEM_DOUT_PB5 SILABS_DBUS_MODEM_DOUT(0x1, 0x5) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) +#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) +#define MODEM_DIN_PA9 SILABS_DBUS_MODEM_DIN(0x0, 0x9) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) +#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) +#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) +#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) +#define MODEM_DIN_PB5 SILABS_DBUS_MODEM_DIN(0x1, 0x5) + +#define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0) +#define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1) +#define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2) +#define PCNT0_S0IN_PA3 SILABS_DBUS_PCNT0_S0IN(0x0, 0x3) +#define PCNT0_S0IN_PA4 SILABS_DBUS_PCNT0_S0IN(0x0, 0x4) +#define PCNT0_S0IN_PA5 SILABS_DBUS_PCNT0_S0IN(0x0, 0x5) +#define PCNT0_S0IN_PA6 SILABS_DBUS_PCNT0_S0IN(0x0, 0x6) +#define PCNT0_S0IN_PA7 SILABS_DBUS_PCNT0_S0IN(0x0, 0x7) +#define PCNT0_S0IN_PA8 SILABS_DBUS_PCNT0_S0IN(0x0, 0x8) +#define PCNT0_S0IN_PA9 SILABS_DBUS_PCNT0_S0IN(0x0, 0x9) +#define PCNT0_S0IN_PB0 SILABS_DBUS_PCNT0_S0IN(0x1, 0x0) +#define PCNT0_S0IN_PB1 SILABS_DBUS_PCNT0_S0IN(0x1, 0x1) +#define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2) +#define PCNT0_S0IN_PB3 SILABS_DBUS_PCNT0_S0IN(0x1, 0x3) +#define PCNT0_S0IN_PB4 SILABS_DBUS_PCNT0_S0IN(0x1, 0x4) +#define PCNT0_S0IN_PB5 SILABS_DBUS_PCNT0_S0IN(0x1, 0x5) +#define PCNT0_S1IN_PA0 SILABS_DBUS_PCNT0_S1IN(0x0, 0x0) +#define PCNT0_S1IN_PA1 SILABS_DBUS_PCNT0_S1IN(0x0, 0x1) +#define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2) +#define PCNT0_S1IN_PA3 SILABS_DBUS_PCNT0_S1IN(0x0, 0x3) +#define PCNT0_S1IN_PA4 SILABS_DBUS_PCNT0_S1IN(0x0, 0x4) +#define PCNT0_S1IN_PA5 SILABS_DBUS_PCNT0_S1IN(0x0, 0x5) +#define PCNT0_S1IN_PA6 SILABS_DBUS_PCNT0_S1IN(0x0, 0x6) +#define PCNT0_S1IN_PA7 SILABS_DBUS_PCNT0_S1IN(0x0, 0x7) +#define PCNT0_S1IN_PA8 SILABS_DBUS_PCNT0_S1IN(0x0, 0x8) +#define PCNT0_S1IN_PA9 SILABS_DBUS_PCNT0_S1IN(0x0, 0x9) +#define PCNT0_S1IN_PB0 SILABS_DBUS_PCNT0_S1IN(0x1, 0x0) +#define PCNT0_S1IN_PB1 SILABS_DBUS_PCNT0_S1IN(0x1, 0x1) +#define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2) +#define PCNT0_S1IN_PB3 SILABS_DBUS_PCNT0_S1IN(0x1, 0x3) +#define PCNT0_S1IN_PB4 SILABS_DBUS_PCNT0_S1IN(0x1, 0x4) +#define PCNT0_S1IN_PB5 SILABS_DBUS_PCNT0_S1IN(0x1, 0x5) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) +#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) +#define PRS0_ASYNCH0_PA9 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x9) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) +#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) +#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) +#define PRS0_ASYNCH0_PB5 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x5) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) +#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) +#define PRS0_ASYNCH1_PA9 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x9) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) +#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) +#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) +#define PRS0_ASYNCH1_PB5 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x5) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) +#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) +#define PRS0_ASYNCH2_PA9 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x9) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) +#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) +#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) +#define PRS0_ASYNCH2_PB5 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x5) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) +#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) +#define PRS0_ASYNCH3_PA9 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x9) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) +#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) +#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) +#define PRS0_ASYNCH3_PB5 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x5) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) +#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) +#define PRS0_ASYNCH4_PA9 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x9) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) +#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) +#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) +#define PRS0_ASYNCH4_PB5 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x5) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) +#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) +#define PRS0_ASYNCH5_PA9 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x9) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) +#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) +#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) +#define PRS0_ASYNCH5_PB5 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x5) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) +#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) +#define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8) +#define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4) +#define PRS0_ASYNCH6_PD5 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x5) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) +#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) +#define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8) +#define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4) +#define PRS0_ASYNCH7_PD5 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x5) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) +#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) +#define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8) +#define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4) +#define PRS0_ASYNCH8_PD5 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x5) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) +#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) +#define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8) +#define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4) +#define PRS0_ASYNCH9_PD5 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x5) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) +#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) +#define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8) +#define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4) +#define PRS0_ASYNCH10_PD5 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x5) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) +#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) +#define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8) +#define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4) +#define PRS0_ASYNCH11_PD5 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x5) +#define PRS0_ASYNCH12_PA0 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x0) +#define PRS0_ASYNCH12_PA1 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x1) +#define PRS0_ASYNCH12_PA2 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x2) +#define PRS0_ASYNCH12_PA3 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x3) +#define PRS0_ASYNCH12_PA4 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x4) +#define PRS0_ASYNCH12_PA5 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x5) +#define PRS0_ASYNCH12_PA6 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x6) +#define PRS0_ASYNCH12_PA7 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x7) +#define PRS0_ASYNCH12_PA8 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x8) +#define PRS0_ASYNCH12_PA9 SILABS_DBUS_PRS0_ASYNCH12(0x0, 0x9) +#define PRS0_ASYNCH12_PB0 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x0) +#define PRS0_ASYNCH12_PB1 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x1) +#define PRS0_ASYNCH12_PB2 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x2) +#define PRS0_ASYNCH12_PB3 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x3) +#define PRS0_ASYNCH12_PB4 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x4) +#define PRS0_ASYNCH12_PB5 SILABS_DBUS_PRS0_ASYNCH12(0x1, 0x5) +#define PRS0_ASYNCH13_PA0 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x0) +#define PRS0_ASYNCH13_PA1 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x1) +#define PRS0_ASYNCH13_PA2 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x2) +#define PRS0_ASYNCH13_PA3 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x3) +#define PRS0_ASYNCH13_PA4 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x4) +#define PRS0_ASYNCH13_PA5 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x5) +#define PRS0_ASYNCH13_PA6 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x6) +#define PRS0_ASYNCH13_PA7 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x7) +#define PRS0_ASYNCH13_PA8 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x8) +#define PRS0_ASYNCH13_PA9 SILABS_DBUS_PRS0_ASYNCH13(0x0, 0x9) +#define PRS0_ASYNCH13_PB0 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x0) +#define PRS0_ASYNCH13_PB1 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x1) +#define PRS0_ASYNCH13_PB2 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x2) +#define PRS0_ASYNCH13_PB3 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x3) +#define PRS0_ASYNCH13_PB4 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x4) +#define PRS0_ASYNCH13_PB5 SILABS_DBUS_PRS0_ASYNCH13(0x1, 0x5) +#define PRS0_ASYNCH14_PA0 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x0) +#define PRS0_ASYNCH14_PA1 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x1) +#define PRS0_ASYNCH14_PA2 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x2) +#define PRS0_ASYNCH14_PA3 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x3) +#define PRS0_ASYNCH14_PA4 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x4) +#define PRS0_ASYNCH14_PA5 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x5) +#define PRS0_ASYNCH14_PA6 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x6) +#define PRS0_ASYNCH14_PA7 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x7) +#define PRS0_ASYNCH14_PA8 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x8) +#define PRS0_ASYNCH14_PA9 SILABS_DBUS_PRS0_ASYNCH14(0x0, 0x9) +#define PRS0_ASYNCH14_PB0 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x0) +#define PRS0_ASYNCH14_PB1 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x1) +#define PRS0_ASYNCH14_PB2 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x2) +#define PRS0_ASYNCH14_PB3 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x3) +#define PRS0_ASYNCH14_PB4 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x4) +#define PRS0_ASYNCH14_PB5 SILABS_DBUS_PRS0_ASYNCH14(0x1, 0x5) +#define PRS0_ASYNCH15_PA0 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x0) +#define PRS0_ASYNCH15_PA1 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x1) +#define PRS0_ASYNCH15_PA2 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x2) +#define PRS0_ASYNCH15_PA3 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x3) +#define PRS0_ASYNCH15_PA4 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x4) +#define PRS0_ASYNCH15_PA5 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x5) +#define PRS0_ASYNCH15_PA6 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x6) +#define PRS0_ASYNCH15_PA7 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x7) +#define PRS0_ASYNCH15_PA8 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x8) +#define PRS0_ASYNCH15_PA9 SILABS_DBUS_PRS0_ASYNCH15(0x0, 0x9) +#define PRS0_ASYNCH15_PB0 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x0) +#define PRS0_ASYNCH15_PB1 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x1) +#define PRS0_ASYNCH15_PB2 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x2) +#define PRS0_ASYNCH15_PB3 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x3) +#define PRS0_ASYNCH15_PB4 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x4) +#define PRS0_ASYNCH15_PB5 SILABS_DBUS_PRS0_ASYNCH15(0x1, 0x5) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) +#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) +#define PRS0_SYNCH0_PA9 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x9) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) +#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) +#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) +#define PRS0_SYNCH0_PB5 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x5) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) +#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) +#define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8) +#define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4) +#define PRS0_SYNCH0_PD5 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x5) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) +#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) +#define PRS0_SYNCH1_PA9 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x9) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) +#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) +#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) +#define PRS0_SYNCH1_PB5 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x5) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) +#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) +#define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8) +#define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4) +#define PRS0_SYNCH1_PD5 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x5) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) +#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) +#define PRS0_SYNCH2_PA9 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x9) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) +#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) +#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) +#define PRS0_SYNCH2_PB5 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x5) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) +#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) +#define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8) +#define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4) +#define PRS0_SYNCH2_PD5 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x5) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) +#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) +#define PRS0_SYNCH3_PA9 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x9) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) +#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) +#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) +#define PRS0_SYNCH3_PB5 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x5) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) +#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) +#define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8) +#define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) +#define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4) +#define PRS0_SYNCH3_PD5 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x5) + +#define HFXO0_BUFOUTREQINASYNC_PA0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x0) +#define HFXO0_BUFOUTREQINASYNC_PA1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x1) +#define HFXO0_BUFOUTREQINASYNC_PA2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x2) +#define HFXO0_BUFOUTREQINASYNC_PA3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x3) +#define HFXO0_BUFOUTREQINASYNC_PA4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x4) +#define HFXO0_BUFOUTREQINASYNC_PA5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x5) +#define HFXO0_BUFOUTREQINASYNC_PA6 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x6) +#define HFXO0_BUFOUTREQINASYNC_PA7 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x7) +#define HFXO0_BUFOUTREQINASYNC_PA8 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x8) +#define HFXO0_BUFOUTREQINASYNC_PA9 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x0, 0x9) +#define HFXO0_BUFOUTREQINASYNC_PB0 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x0) +#define HFXO0_BUFOUTREQINASYNC_PB1 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x1) +#define HFXO0_BUFOUTREQINASYNC_PB2 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x2) +#define HFXO0_BUFOUTREQINASYNC_PB3 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x3) +#define HFXO0_BUFOUTREQINASYNC_PB4 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x4) +#define HFXO0_BUFOUTREQINASYNC_PB5 SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(0x1, 0x5) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) +#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) +#define TIMER0_CC0_PA9 SILABS_DBUS_TIMER0_CC0(0x0, 0x9) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) +#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) +#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) +#define TIMER0_CC0_PB5 SILABS_DBUS_TIMER0_CC0(0x1, 0x5) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) +#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) +#define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8) +#define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4) +#define TIMER0_CC0_PD5 SILABS_DBUS_TIMER0_CC0(0x3, 0x5) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) +#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) +#define TIMER0_CC1_PA9 SILABS_DBUS_TIMER0_CC1(0x0, 0x9) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) +#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) +#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) +#define TIMER0_CC1_PB5 SILABS_DBUS_TIMER0_CC1(0x1, 0x5) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) +#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) +#define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8) +#define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4) +#define TIMER0_CC1_PD5 SILABS_DBUS_TIMER0_CC1(0x3, 0x5) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) +#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) +#define TIMER0_CC2_PA9 SILABS_DBUS_TIMER0_CC2(0x0, 0x9) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) +#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) +#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) +#define TIMER0_CC2_PB5 SILABS_DBUS_TIMER0_CC2(0x1, 0x5) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) +#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) +#define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8) +#define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4) +#define TIMER0_CC2_PD5 SILABS_DBUS_TIMER0_CC2(0x3, 0x5) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) +#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) +#define TIMER0_CDTI0_PA9 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x9) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) +#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) +#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) +#define TIMER0_CDTI0_PB5 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x5) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) +#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) +#define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8) +#define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4) +#define TIMER0_CDTI0_PD5 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x5) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) +#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) +#define TIMER0_CDTI1_PA9 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x9) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) +#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) +#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) +#define TIMER0_CDTI1_PB5 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x5) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) +#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) +#define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8) +#define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4) +#define TIMER0_CDTI1_PD5 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x5) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) +#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) +#define TIMER0_CDTI2_PA9 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x9) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) +#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) +#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) +#define TIMER0_CDTI2_PB5 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x5) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) +#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) +#define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8) +#define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) +#define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4) +#define TIMER0_CDTI2_PD5 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x5) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) +#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) +#define TIMER1_CC0_PA9 SILABS_DBUS_TIMER1_CC0(0x0, 0x9) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) +#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) +#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) +#define TIMER1_CC0_PB5 SILABS_DBUS_TIMER1_CC0(0x1, 0x5) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) +#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) +#define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8) +#define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4) +#define TIMER1_CC0_PD5 SILABS_DBUS_TIMER1_CC0(0x3, 0x5) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) +#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) +#define TIMER1_CC1_PA9 SILABS_DBUS_TIMER1_CC1(0x0, 0x9) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) +#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) +#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) +#define TIMER1_CC1_PB5 SILABS_DBUS_TIMER1_CC1(0x1, 0x5) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) +#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) +#define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8) +#define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4) +#define TIMER1_CC1_PD5 SILABS_DBUS_TIMER1_CC1(0x3, 0x5) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) +#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) +#define TIMER1_CC2_PA9 SILABS_DBUS_TIMER1_CC2(0x0, 0x9) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) +#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) +#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) +#define TIMER1_CC2_PB5 SILABS_DBUS_TIMER1_CC2(0x1, 0x5) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) +#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) +#define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8) +#define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4) +#define TIMER1_CC2_PD5 SILABS_DBUS_TIMER1_CC2(0x3, 0x5) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) +#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) +#define TIMER1_CDTI0_PA9 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x9) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) +#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) +#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) +#define TIMER1_CDTI0_PB5 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x5) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) +#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) +#define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8) +#define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4) +#define TIMER1_CDTI0_PD5 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x5) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) +#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) +#define TIMER1_CDTI1_PA9 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x9) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) +#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) +#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) +#define TIMER1_CDTI1_PB5 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x5) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) +#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) +#define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8) +#define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4) +#define TIMER1_CDTI1_PD5 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x5) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) +#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) +#define TIMER1_CDTI2_PA9 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x9) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) +#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) +#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) +#define TIMER1_CDTI2_PB5 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x5) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) +#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) +#define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8) +#define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) +#define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4) +#define TIMER1_CDTI2_PD5 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x5) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) +#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) +#define TIMER2_CC0_PA9 SILABS_DBUS_TIMER2_CC0(0x0, 0x9) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) +#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) +#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) +#define TIMER2_CC0_PB5 SILABS_DBUS_TIMER2_CC0(0x1, 0x5) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) +#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) +#define TIMER2_CC1_PA9 SILABS_DBUS_TIMER2_CC1(0x0, 0x9) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) +#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) +#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) +#define TIMER2_CC1_PB5 SILABS_DBUS_TIMER2_CC1(0x1, 0x5) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) +#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) +#define TIMER2_CC2_PA9 SILABS_DBUS_TIMER2_CC2(0x0, 0x9) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) +#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) +#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) +#define TIMER2_CC2_PB5 SILABS_DBUS_TIMER2_CC2(0x1, 0x5) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) +#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) +#define TIMER2_CDTI0_PA9 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x9) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) +#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) +#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) +#define TIMER2_CDTI0_PB5 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x5) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) +#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) +#define TIMER2_CDTI1_PA9 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x9) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) +#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) +#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) +#define TIMER2_CDTI1_PB5 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x5) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) +#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) +#define TIMER2_CDTI2_PA9 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x9) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) +#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) +#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) +#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) +#define TIMER2_CDTI2_PB5 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x5) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) +#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) +#define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8) +#define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4) +#define TIMER3_CC0_PD5 SILABS_DBUS_TIMER3_CC0(0x3, 0x5) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) +#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) +#define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8) +#define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4) +#define TIMER3_CC1_PD5 SILABS_DBUS_TIMER3_CC1(0x3, 0x5) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) +#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) +#define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8) +#define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4) +#define TIMER3_CC2_PD5 SILABS_DBUS_TIMER3_CC2(0x3, 0x5) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) +#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) +#define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8) +#define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4) +#define TIMER3_CDTI0_PD5 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x5) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) +#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) +#define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8) +#define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4) +#define TIMER3_CDTI1_PD5 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x5) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) +#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) +#define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8) +#define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) +#define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4) +#define TIMER3_CDTI2_PD5 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x5) + +#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) +#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) +#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) +#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) +#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) +#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) +#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) +#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) +#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) +#define TIMER4_CC0_PA9 SILABS_DBUS_TIMER4_CC0(0x0, 0x9) +#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) +#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) +#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) +#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) +#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) +#define TIMER4_CC0_PB5 SILABS_DBUS_TIMER4_CC0(0x1, 0x5) +#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) +#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) +#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) +#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) +#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) +#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) +#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) +#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) +#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) +#define TIMER4_CC1_PA9 SILABS_DBUS_TIMER4_CC1(0x0, 0x9) +#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) +#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) +#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) +#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) +#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) +#define TIMER4_CC1_PB5 SILABS_DBUS_TIMER4_CC1(0x1, 0x5) +#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) +#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) +#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) +#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) +#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) +#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) +#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) +#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) +#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) +#define TIMER4_CC2_PA9 SILABS_DBUS_TIMER4_CC2(0x0, 0x9) +#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) +#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) +#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) +#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) +#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) +#define TIMER4_CC2_PB5 SILABS_DBUS_TIMER4_CC2(0x1, 0x5) +#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) +#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) +#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) +#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) +#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) +#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) +#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) +#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) +#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) +#define TIMER4_CDTI0_PA9 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x9) +#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) +#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) +#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) +#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) +#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) +#define TIMER4_CDTI0_PB5 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x5) +#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) +#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) +#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) +#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) +#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) +#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) +#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) +#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) +#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) +#define TIMER4_CDTI1_PA9 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x9) +#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) +#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) +#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) +#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) +#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) +#define TIMER4_CDTI1_PB5 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x5) +#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) +#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) +#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) +#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) +#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) +#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) +#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) +#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) +#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) +#define TIMER4_CDTI2_PA9 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x9) +#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) +#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) +#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) +#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) +#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) +#define TIMER4_CDTI2_PB5 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x5) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) +#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) +#define USART0_CS_PA9 SILABS_DBUS_USART0_CS(0x0, 0x9) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) +#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) +#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) +#define USART0_CS_PB5 SILABS_DBUS_USART0_CS(0x1, 0x5) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) +#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) +#define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8) +#define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4) +#define USART0_CS_PD5 SILABS_DBUS_USART0_CS(0x3, 0x5) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) +#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) +#define USART0_RTS_PA9 SILABS_DBUS_USART0_RTS(0x0, 0x9) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) +#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) +#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) +#define USART0_RTS_PB5 SILABS_DBUS_USART0_RTS(0x1, 0x5) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) +#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) +#define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8) +#define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4) +#define USART0_RTS_PD5 SILABS_DBUS_USART0_RTS(0x3, 0x5) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) +#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) +#define USART0_RX_PA9 SILABS_DBUS_USART0_RX(0x0, 0x9) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) +#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) +#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) +#define USART0_RX_PB5 SILABS_DBUS_USART0_RX(0x1, 0x5) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) +#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) +#define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8) +#define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4) +#define USART0_RX_PD5 SILABS_DBUS_USART0_RX(0x3, 0x5) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) +#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) +#define USART0_CLK_PA9 SILABS_DBUS_USART0_CLK(0x0, 0x9) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) +#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) +#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) +#define USART0_CLK_PB5 SILABS_DBUS_USART0_CLK(0x1, 0x5) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) +#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) +#define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8) +#define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4) +#define USART0_CLK_PD5 SILABS_DBUS_USART0_CLK(0x3, 0x5) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) +#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) +#define USART0_TX_PA9 SILABS_DBUS_USART0_TX(0x0, 0x9) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) +#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) +#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) +#define USART0_TX_PB5 SILABS_DBUS_USART0_TX(0x1, 0x5) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) +#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) +#define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8) +#define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4) +#define USART0_TX_PD5 SILABS_DBUS_USART0_TX(0x3, 0x5) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) +#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) +#define USART0_CTS_PA9 SILABS_DBUS_USART0_CTS(0x0, 0x9) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) +#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) +#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) +#define USART0_CTS_PB5 SILABS_DBUS_USART0_CTS(0x1, 0x5) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) +#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) +#define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8) +#define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) +#define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4) +#define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h new file mode 100644 index 00000000..a111ce6c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h @@ -0,0 +1,1875 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs XG27 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_ + +#include + +#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1) + +#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1) +#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3) +#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4) +#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5) +#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6) +#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2) + +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 27, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 27, 1, 2, 3) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 32, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 32, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 36, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 36, 1, 1, 2) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2) +#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 44, 1, 2, 3) +#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 44, 1, 3, 4) +#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 44, 1, 4, 5) +#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 44, 1, 5, 6) +#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 44, 1, 6, 7) +#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 44, 1, 7, 8) +#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 44, 1, 8, 9) +#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 44, 1, 9, 10) +#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 44, 1, 10, 11) +#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 44, 1, 11, 12) +#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 44, 1, 12, 13) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 44, 1, 13, 14) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 44, 1, 14, 16) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 44, 0, 0, 15) + +#define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1) +#define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 62, 0, 0, 2) +#define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 62, 0, 0, 3) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 67, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 67, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 67, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 67, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 67, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 67, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 67, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 67, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 67, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 67, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 67, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 67, 1, 11, 12) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 67, 1, 12, 13) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 67, 1, 13, 14) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 67, 1, 14, 15) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 67, 1, 15, 16) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 85, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 85, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 85, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 85, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 85, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 85, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 93, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 93, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 93, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 101, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 101, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 101, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 109, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 109, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 109, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6) + +#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 117, 1, 0, 1) +#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 117, 1, 1, 2) +#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 117, 1, 2, 3) +#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4) +#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5) +#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 125, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 125, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 125, 0, 0, 2) + +#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 133, 1, 0, 1) +#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3) +#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4) +#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5) +#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6) +#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2) + +#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) +#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) +#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) +#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) +#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) +#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) +#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) +#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7) +#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8) +#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) +#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) +#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2) +#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3) +#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4) +#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) +#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) +#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) +#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) +#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) +#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) +#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6) +#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7) +#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) +#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) +#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) +#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) +#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) +#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) +#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) +#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) +#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) +#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) + +#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0) +#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1) +#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2) +#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3) +#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4) +#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5) +#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6) +#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7) +#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8) +#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0) +#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1) +#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2) +#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3) +#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4) +#define EUSART0_CS_PC0 SILABS_DBUS_EUSART0_CS(0x2, 0x0) +#define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1) +#define EUSART0_CS_PC2 SILABS_DBUS_EUSART0_CS(0x2, 0x2) +#define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3) +#define EUSART0_CS_PC4 SILABS_DBUS_EUSART0_CS(0x2, 0x4) +#define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5) +#define EUSART0_CS_PC6 SILABS_DBUS_EUSART0_CS(0x2, 0x6) +#define EUSART0_CS_PC7 SILABS_DBUS_EUSART0_CS(0x2, 0x7) +#define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0) +#define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1) +#define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2) +#define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3) +#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0) +#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1) +#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2) +#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3) +#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4) +#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5) +#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6) +#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7) +#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8) +#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0) +#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1) +#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2) +#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3) +#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4) +#define EUSART0_RTS_PC0 SILABS_DBUS_EUSART0_RTS(0x2, 0x0) +#define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1) +#define EUSART0_RTS_PC2 SILABS_DBUS_EUSART0_RTS(0x2, 0x2) +#define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3) +#define EUSART0_RTS_PC4 SILABS_DBUS_EUSART0_RTS(0x2, 0x4) +#define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5) +#define EUSART0_RTS_PC6 SILABS_DBUS_EUSART0_RTS(0x2, 0x6) +#define EUSART0_RTS_PC7 SILABS_DBUS_EUSART0_RTS(0x2, 0x7) +#define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0) +#define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1) +#define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2) +#define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3) +#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0) +#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1) +#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2) +#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3) +#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4) +#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5) +#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6) +#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7) +#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8) +#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0) +#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1) +#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2) +#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3) +#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4) +#define EUSART0_RX_PC0 SILABS_DBUS_EUSART0_RX(0x2, 0x0) +#define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1) +#define EUSART0_RX_PC2 SILABS_DBUS_EUSART0_RX(0x2, 0x2) +#define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3) +#define EUSART0_RX_PC4 SILABS_DBUS_EUSART0_RX(0x2, 0x4) +#define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5) +#define EUSART0_RX_PC6 SILABS_DBUS_EUSART0_RX(0x2, 0x6) +#define EUSART0_RX_PC7 SILABS_DBUS_EUSART0_RX(0x2, 0x7) +#define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0) +#define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1) +#define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2) +#define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3) +#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0) +#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1) +#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2) +#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3) +#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4) +#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5) +#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6) +#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7) +#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8) +#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0) +#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1) +#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2) +#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3) +#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4) +#define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0) +#define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1) +#define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2) +#define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3) +#define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4) +#define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5) +#define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6) +#define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7) +#define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0) +#define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1) +#define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2) +#define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3) +#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0) +#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1) +#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2) +#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3) +#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4) +#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5) +#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6) +#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7) +#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8) +#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0) +#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1) +#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2) +#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3) +#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4) +#define EUSART0_TX_PC0 SILABS_DBUS_EUSART0_TX(0x2, 0x0) +#define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1) +#define EUSART0_TX_PC2 SILABS_DBUS_EUSART0_TX(0x2, 0x2) +#define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3) +#define EUSART0_TX_PC4 SILABS_DBUS_EUSART0_TX(0x2, 0x4) +#define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5) +#define EUSART0_TX_PC6 SILABS_DBUS_EUSART0_TX(0x2, 0x6) +#define EUSART0_TX_PC7 SILABS_DBUS_EUSART0_TX(0x2, 0x7) +#define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0) +#define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1) +#define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2) +#define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3) +#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0) +#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1) +#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2) +#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3) +#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4) +#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5) +#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6) +#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7) +#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8) +#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0) +#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1) +#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2) +#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3) +#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4) +#define EUSART0_CTS_PC0 SILABS_DBUS_EUSART0_CTS(0x2, 0x0) +#define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1) +#define EUSART0_CTS_PC2 SILABS_DBUS_EUSART0_CTS(0x2, 0x2) +#define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3) +#define EUSART0_CTS_PC4 SILABS_DBUS_EUSART0_CTS(0x2, 0x4) +#define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5) +#define EUSART0_CTS_PC6 SILABS_DBUS_EUSART0_CTS(0x2, 0x6) +#define EUSART0_CTS_PC7 SILABS_DBUS_EUSART0_CTS(0x2, 0x7) +#define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0) +#define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1) +#define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2) +#define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3) + +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) +#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) +#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) +#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) +#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) +#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) +#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) +#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) +#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) +#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) +#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) +#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) +#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) +#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) +#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) +#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) +#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) +#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) +#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) +#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) +#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) + +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) +#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) +#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) +#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) +#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) +#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) +#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) +#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) +#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) +#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) +#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) +#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) +#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) +#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) +#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) +#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) +#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) +#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) +#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) +#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) +#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) +#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) +#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) +#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) +#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) +#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) +#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) +#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) +#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) +#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) +#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) +#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) +#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) +#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) +#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) +#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) +#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) +#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) +#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) +#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) +#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) +#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) +#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) +#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) +#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) +#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) +#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) +#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) +#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) +#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) +#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) +#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) +#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) +#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) +#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) +#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) +#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) +#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) +#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) +#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) +#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) +#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) +#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) +#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) +#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) +#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) +#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) +#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) +#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) +#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) +#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) +#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) +#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) +#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) +#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) +#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) +#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) +#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) +#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) +#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) +#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) +#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) +#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) +#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) +#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) +#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) +#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) +#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) +#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) +#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) +#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) +#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) +#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) +#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) +#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) +#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) +#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) +#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) +#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) +#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) +#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) +#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) +#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) +#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) +#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) +#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) +#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) +#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) +#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) +#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) +#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) +#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) +#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) +#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) +#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) +#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) +#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) +#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) +#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) +#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) +#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) +#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) +#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) +#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) +#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) +#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) +#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) +#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) +#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) +#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) +#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) +#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) +#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) +#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) +#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) +#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) +#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) +#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) +#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) +#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) +#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) +#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) +#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) +#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) +#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) +#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) +#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) +#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) +#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) +#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) + +#define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0) +#define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1) +#define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2) +#define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3) +#define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4) +#define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5) +#define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6) +#define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7) +#define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8) +#define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0) +#define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1) +#define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2) +#define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3) +#define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4) +#define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0) +#define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1) +#define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2) +#define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3) +#define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4) +#define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5) +#define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6) +#define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7) +#define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0) +#define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1) +#define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2) +#define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3) +#define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0) +#define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1) +#define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2) +#define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3) +#define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4) +#define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5) +#define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6) +#define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7) +#define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8) +#define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0) +#define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1) +#define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2) +#define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3) +#define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4) +#define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0) +#define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1) +#define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2) +#define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3) +#define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4) +#define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5) +#define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6) +#define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7) +#define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0) +#define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1) +#define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2) +#define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3) +#define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0) +#define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1) +#define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2) +#define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3) +#define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4) +#define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5) +#define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6) +#define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7) +#define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8) +#define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0) +#define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1) +#define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2) +#define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3) +#define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4) +#define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0) +#define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1) +#define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2) +#define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3) +#define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4) +#define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5) +#define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6) +#define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7) +#define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0) +#define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1) +#define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2) +#define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) +#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) +#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) +#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) +#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) +#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) +#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) +#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) +#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) +#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) +#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) +#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) +#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) +#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) +#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) +#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) +#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) +#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) +#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) +#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) +#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) +#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) +#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) +#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) +#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) +#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) +#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) +#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) +#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) +#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) +#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) +#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) +#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) +#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) +#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) +#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) +#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) +#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) +#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) +#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) +#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) +#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) +#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) +#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) +#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) +#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) +#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) +#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) +#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) +#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) +#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) +#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) +#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) +#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) +#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) +#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) +#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) +#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) +#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) +#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) +#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) +#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) +#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) +#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) +#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) +#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) +#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) +#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) +#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) +#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) +#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) +#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) +#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) +#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) +#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) +#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) +#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) +#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) +#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) +#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) +#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) +#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) +#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) +#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) +#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) +#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) +#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) +#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) +#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) +#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) +#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) +#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) +#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) +#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) +#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) +#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) +#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) +#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) +#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) +#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) +#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) +#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) +#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) +#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) +#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) +#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) +#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) +#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) +#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) +#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) +#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) +#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) +#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) +#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) + +#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) +#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) +#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) +#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) +#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) +#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) +#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) +#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) +#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) +#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) +#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) +#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) +#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) +#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) +#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) +#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) +#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) +#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) +#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) +#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) +#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) +#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) +#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) +#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) +#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) +#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) +#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) +#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) +#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) +#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) +#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) +#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) +#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) +#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) +#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) +#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) +#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) +#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) +#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) +#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) +#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) +#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) +#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) +#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) +#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) +#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) +#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) +#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) +#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) +#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) +#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) +#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) +#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) +#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) +#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) +#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) +#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) +#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) +#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) +#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) +#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) +#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) +#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) +#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) +#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) +#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) +#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) +#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) +#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) +#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) +#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) +#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) +#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) +#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) +#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) +#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) +#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) +#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) +#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) +#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) +#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) +#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) +#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) +#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) +#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) +#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) +#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) +#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) +#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) +#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) +#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) +#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) +#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) +#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) +#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) +#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) +#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) +#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) +#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) +#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) +#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) +#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) +#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) +#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) +#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) +#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) +#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) +#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) + +#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) +#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) +#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) +#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) +#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) +#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) +#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) +#define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7) +#define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8) +#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) +#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) +#define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2) +#define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3) +#define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4) +#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) +#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) +#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) +#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) +#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) +#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) +#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) +#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7) +#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8) +#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) +#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) +#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2) +#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3) +#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4) +#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) +#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) +#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) +#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) +#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) +#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) +#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) +#define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7) +#define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8) +#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) +#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) +#define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2) +#define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3) +#define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4) +#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) +#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) +#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) +#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) +#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) +#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) +#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) +#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7) +#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8) +#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) +#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) +#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2) +#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3) +#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4) +#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) +#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) +#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) +#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) +#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) +#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) +#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) +#define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7) +#define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8) +#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) +#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) +#define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2) +#define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3) +#define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4) +#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) +#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) +#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) +#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) +#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) +#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) +#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) +#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7) +#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8) +#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) +#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) +#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2) +#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3) +#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h index b50e7846..a830187b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h @@ -39,6 +39,11 @@ #define MUX_MODE_7 7 #define MUX_MODE_8 8 #define MUX_MODE_9 9 +#define MUX_MODE_10 10 +#define MUX_MODE_11 11 +#define MUX_MODE_12 12 +#define MUX_MODE_13 13 +#define MUX_MODE_14 14 #define K3_PINMUX(offset, value, mux_mode) (((offset) & 0x1fff)) ((value) | (mux_mode)) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/imx_scu_rsrc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/imx_scu_rsrc.h new file mode 100644 index 00000000..dc9952ee --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/imx_scu_rsrc.h @@ -0,0 +1,558 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_ + +#define IMX_SC_R_A53 0U +#define IMX_SC_R_A53_0 1U +#define IMX_SC_R_A53_1 2U +#define IMX_SC_R_A53_2 3U +#define IMX_SC_R_A53_3 4U +#define IMX_SC_R_A72 5U +#define IMX_SC_R_A72_0 6U +#define IMX_SC_R_A72_1 7U +#define IMX_SC_R_A72_2 8U +#define IMX_SC_R_A72_3 9U +#define IMX_SC_R_CCI 10U +#define IMX_SC_R_DB 11U +#define IMX_SC_R_DRC_0 12U +#define IMX_SC_R_DRC_1 13U +#define IMX_SC_R_GIC_SMMU 14U +#define IMX_SC_R_IRQSTR_M4_0 15U +#define IMX_SC_R_IRQSTR_M4_1 16U +#define IMX_SC_R_SMMU 17U +#define IMX_SC_R_GIC 18U +#define IMX_SC_R_DC_0_BLIT0 19U +#define IMX_SC_R_DC_0_BLIT1 20U +#define IMX_SC_R_DC_0_BLIT2 21U +#define IMX_SC_R_DC_0_BLIT_OUT 22U +#define IMX_SC_R_PERF 23U +#define IMX_SC_R_USB_1_PHY 24U +#define IMX_SC_R_DC_0_WARP 25U +#define IMX_SC_R_V2X_MU_0 26U +#define IMX_SC_R_V2X_MU_1 27U +#define IMX_SC_R_DC_0_VIDEO0 28U +#define IMX_SC_R_DC_0_VIDEO1 29U +#define IMX_SC_R_DC_0_FRAC0 30U +#define IMX_SC_R_V2X_MU_2 31U +#define IMX_SC_R_DC_0 32U +#define IMX_SC_R_GPU_2_PID0 33U +#define IMX_SC_R_DC_0_PLL_0 34U +#define IMX_SC_R_DC_0_PLL_1 35U +#define IMX_SC_R_DC_1_BLIT0 36U +#define IMX_SC_R_DC_1_BLIT1 37U +#define IMX_SC_R_DC_1_BLIT2 38U +#define IMX_SC_R_DC_1_BLIT_OUT 39U +#define IMX_SC_R_V2X_MU_3 40U +#define IMX_SC_R_V2X_MU_4 41U +#define IMX_SC_R_DC_1_WARP 42U +#define IMX_SC_R_UNUSED1 43U +#define IMX_SC_R_SECVIO 44U +#define IMX_SC_R_DC_1_VIDEO0 45U +#define IMX_SC_R_DC_1_VIDEO1 46U +#define IMX_SC_R_DC_1_FRAC0 47U +#define IMX_SC_R_UNUSED13 48U +#define IMX_SC_R_DC_1 49U +#define IMX_SC_R_UNUSED14 50U +#define IMX_SC_R_DC_1_PLL_0 51U +#define IMX_SC_R_DC_1_PLL_1 52U +#define IMX_SC_R_SPI_0 53U +#define IMX_SC_R_SPI_1 54U +#define IMX_SC_R_SPI_2 55U +#define IMX_SC_R_SPI_3 56U +#define IMX_SC_R_UART_0 57U +#define IMX_SC_R_UART_1 58U +#define IMX_SC_R_UART_2 59U +#define IMX_SC_R_UART_3 60U +#define IMX_SC_R_UART_4 61U +#define IMX_SC_R_EMVSIM_0 62U +#define IMX_SC_R_EMVSIM_1 63U +#define IMX_SC_R_DMA_0_CH0 64U +#define IMX_SC_R_DMA_0_CH1 65U +#define IMX_SC_R_DMA_0_CH2 66U +#define IMX_SC_R_DMA_0_CH3 67U +#define IMX_SC_R_DMA_0_CH4 68U +#define IMX_SC_R_DMA_0_CH5 69U +#define IMX_SC_R_DMA_0_CH6 70U +#define IMX_SC_R_DMA_0_CH7 71U +#define IMX_SC_R_DMA_0_CH8 72U +#define IMX_SC_R_DMA_0_CH9 73U +#define IMX_SC_R_DMA_0_CH10 74U +#define IMX_SC_R_DMA_0_CH11 75U +#define IMX_SC_R_DMA_0_CH12 76U +#define IMX_SC_R_DMA_0_CH13 77U +#define IMX_SC_R_DMA_0_CH14 78U +#define IMX_SC_R_DMA_0_CH15 79U +#define IMX_SC_R_DMA_0_CH16 80U +#define IMX_SC_R_DMA_0_CH17 81U +#define IMX_SC_R_DMA_0_CH18 82U +#define IMX_SC_R_DMA_0_CH19 83U +#define IMX_SC_R_DMA_0_CH20 84U +#define IMX_SC_R_DMA_0_CH21 85U +#define IMX_SC_R_DMA_0_CH22 86U +#define IMX_SC_R_DMA_0_CH23 87U +#define IMX_SC_R_DMA_0_CH24 88U +#define IMX_SC_R_DMA_0_CH25 89U +#define IMX_SC_R_DMA_0_CH26 90U +#define IMX_SC_R_DMA_0_CH27 91U +#define IMX_SC_R_DMA_0_CH28 92U +#define IMX_SC_R_DMA_0_CH29 93U +#define IMX_SC_R_DMA_0_CH30 94U +#define IMX_SC_R_DMA_0_CH31 95U +#define IMX_SC_R_I2C_0 96U +#define IMX_SC_R_I2C_1 97U +#define IMX_SC_R_I2C_2 98U +#define IMX_SC_R_I2C_3 99U +#define IMX_SC_R_I2C_4 100U +#define IMX_SC_R_ADC_0 101U +#define IMX_SC_R_ADC_1 102U +#define IMX_SC_R_FTM_0 103U +#define IMX_SC_R_FTM_1 104U +#define IMX_SC_R_CAN_0 105U +#define IMX_SC_R_CAN_1 106U +#define IMX_SC_R_CAN_2 107U +#define IMX_SC_R_DMA_1_CH0 108U +#define IMX_SC_R_DMA_1_CH1 109U +#define IMX_SC_R_DMA_1_CH2 110U +#define IMX_SC_R_DMA_1_CH3 111U +#define IMX_SC_R_DMA_1_CH4 112U +#define IMX_SC_R_DMA_1_CH5 113U +#define IMX_SC_R_DMA_1_CH6 114U +#define IMX_SC_R_DMA_1_CH7 115U +#define IMX_SC_R_DMA_1_CH8 116U +#define IMX_SC_R_DMA_1_CH9 117U +#define IMX_SC_R_DMA_1_CH10 118U +#define IMX_SC_R_DMA_1_CH11 119U +#define IMX_SC_R_DMA_1_CH12 120U +#define IMX_SC_R_DMA_1_CH13 121U +#define IMX_SC_R_DMA_1_CH14 122U +#define IMX_SC_R_DMA_1_CH15 123U +#define IMX_SC_R_DMA_1_CH16 124U +#define IMX_SC_R_DMA_1_CH17 125U +#define IMX_SC_R_DMA_1_CH18 126U +#define IMX_SC_R_DMA_1_CH19 127U +#define IMX_SC_R_DMA_1_CH20 128U +#define IMX_SC_R_DMA_1_CH21 129U +#define IMX_SC_R_DMA_1_CH22 130U +#define IMX_SC_R_DMA_1_CH23 131U +#define IMX_SC_R_DMA_1_CH24 132U +#define IMX_SC_R_DMA_1_CH25 133U +#define IMX_SC_R_DMA_1_CH26 134U +#define IMX_SC_R_DMA_1_CH27 135U +#define IMX_SC_R_DMA_1_CH28 136U +#define IMX_SC_R_DMA_1_CH29 137U +#define IMX_SC_R_DMA_1_CH30 138U +#define IMX_SC_R_DMA_1_CH31 139U +#define IMX_SC_R_V2X_PID0 140U +#define IMX_SC_R_V2X_PID1 141U +#define IMX_SC_R_V2X_PID2 142U +#define IMX_SC_R_V2X_PID3 143U +#define IMX_SC_R_GPU_0_PID0 144U +#define IMX_SC_R_GPU_0_PID1 145U +#define IMX_SC_R_GPU_0_PID2 146U +#define IMX_SC_R_GPU_0_PID3 147U +#define IMX_SC_R_GPU_1_PID0 148U +#define IMX_SC_R_GPU_1_PID1 149U +#define IMX_SC_R_GPU_1_PID2 150U +#define IMX_SC_R_GPU_1_PID3 151U +#define IMX_SC_R_PCIE_A 152U +#define IMX_SC_R_SERDES_0 153U +#define IMX_SC_R_MATCH_0 154U +#define IMX_SC_R_MATCH_1 155U +#define IMX_SC_R_MATCH_2 156U +#define IMX_SC_R_MATCH_3 157U +#define IMX_SC_R_MATCH_4 158U +#define IMX_SC_R_MATCH_5 159U +#define IMX_SC_R_MATCH_6 160U +#define IMX_SC_R_MATCH_7 161U +#define IMX_SC_R_MATCH_8 162U +#define IMX_SC_R_MATCH_9 163U +#define IMX_SC_R_MATCH_10 164U +#define IMX_SC_R_MATCH_11 165U +#define IMX_SC_R_MATCH_12 166U +#define IMX_SC_R_MATCH_13 167U +#define IMX_SC_R_MATCH_14 168U +#define IMX_SC_R_PCIE_B 169U +#define IMX_SC_R_SATA_0 170U +#define IMX_SC_R_SERDES_1 171U +#define IMX_SC_R_HSIO_GPIO 172U +#define IMX_SC_R_MATCH_15 173U +#define IMX_SC_R_MATCH_16 174U +#define IMX_SC_R_MATCH_17 175U +#define IMX_SC_R_MATCH_18 176U +#define IMX_SC_R_MATCH_19 177U +#define IMX_SC_R_MATCH_20 178U +#define IMX_SC_R_MATCH_21 179U +#define IMX_SC_R_MATCH_22 180U +#define IMX_SC_R_MATCH_23 181U +#define IMX_SC_R_MATCH_24 182U +#define IMX_SC_R_MATCH_25 183U +#define IMX_SC_R_MATCH_26 184U +#define IMX_SC_R_MATCH_27 185U +#define IMX_SC_R_MATCH_28 186U +#define IMX_SC_R_LCD_0 187U +#define IMX_SC_R_LCD_0_PWM_0 188U +#define IMX_SC_R_LCD_0_I2C_0 189U +#define IMX_SC_R_LCD_0_I2C_1 190U +#define IMX_SC_R_PWM_0 191U +#define IMX_SC_R_PWM_1 192U +#define IMX_SC_R_PWM_2 193U +#define IMX_SC_R_PWM_3 194U +#define IMX_SC_R_PWM_4 195U +#define IMX_SC_R_PWM_5 196U +#define IMX_SC_R_PWM_6 197U +#define IMX_SC_R_PWM_7 198U +#define IMX_SC_R_GPIO_0 199U +#define IMX_SC_R_GPIO_1 200U +#define IMX_SC_R_GPIO_2 201U +#define IMX_SC_R_GPIO_3 202U +#define IMX_SC_R_GPIO_4 203U +#define IMX_SC_R_GPIO_5 204U +#define IMX_SC_R_GPIO_6 205U +#define IMX_SC_R_GPIO_7 206U +#define IMX_SC_R_GPT_0 207U +#define IMX_SC_R_GPT_1 208U +#define IMX_SC_R_GPT_2 209U +#define IMX_SC_R_GPT_3 210U +#define IMX_SC_R_GPT_4 211U +#define IMX_SC_R_KPP 212U +#define IMX_SC_R_MU_0A 213U +#define IMX_SC_R_MU_1A 214U +#define IMX_SC_R_MU_2A 215U +#define IMX_SC_R_MU_3A 216U +#define IMX_SC_R_MU_4A 217U +#define IMX_SC_R_MU_5A 218U +#define IMX_SC_R_MU_6A 219U +#define IMX_SC_R_MU_7A 220U +#define IMX_SC_R_MU_8A 221U +#define IMX_SC_R_MU_9A 222U +#define IMX_SC_R_MU_10A 223U +#define IMX_SC_R_MU_11A 224U +#define IMX_SC_R_MU_12A 225U +#define IMX_SC_R_MU_13A 226U +#define IMX_SC_R_MU_5B 227U +#define IMX_SC_R_MU_6B 228U +#define IMX_SC_R_MU_7B 229U +#define IMX_SC_R_MU_8B 230U +#define IMX_SC_R_MU_9B 231U +#define IMX_SC_R_MU_10B 232U +#define IMX_SC_R_MU_11B 233U +#define IMX_SC_R_MU_12B 234U +#define IMX_SC_R_MU_13B 235U +#define IMX_SC_R_ROM_0 236U +#define IMX_SC_R_FSPI_0 237U +#define IMX_SC_R_FSPI_1 238U +#define IMX_SC_R_IEE 239U +#define IMX_SC_R_IEE_R0 240U +#define IMX_SC_R_IEE_R1 241U +#define IMX_SC_R_IEE_R2 242U +#define IMX_SC_R_IEE_R3 243U +#define IMX_SC_R_IEE_R4 244U +#define IMX_SC_R_IEE_R5 245U +#define IMX_SC_R_IEE_R6 246U +#define IMX_SC_R_IEE_R7 247U +#define IMX_SC_R_SDHC_0 248U +#define IMX_SC_R_SDHC_1 249U +#define IMX_SC_R_SDHC_2 250U +#define IMX_SC_R_ENET_0 251U +#define IMX_SC_R_ENET_1 252U +#define IMX_SC_R_MLB_0 253U +#define IMX_SC_R_DMA_2_CH0 254U +#define IMX_SC_R_DMA_2_CH1 255U +#define IMX_SC_R_DMA_2_CH2 256U +#define IMX_SC_R_DMA_2_CH3 257U +#define IMX_SC_R_DMA_2_CH4 258U +#define IMX_SC_R_USB_0 259U +#define IMX_SC_R_USB_1 260U +#define IMX_SC_R_USB_0_PHY 261U +#define IMX_SC_R_USB_2 262U +#define IMX_SC_R_USB_2_PHY 263U +#define IMX_SC_R_DTCP 264U +#define IMX_SC_R_NAND 265U +#define IMX_SC_R_LVDS_0 266U +#define IMX_SC_R_LVDS_0_PWM_0 267U +#define IMX_SC_R_LVDS_0_I2C_0 268U +#define IMX_SC_R_LVDS_0_I2C_1 269U +#define IMX_SC_R_LVDS_1 270U +#define IMX_SC_R_LVDS_1_PWM_0 271U +#define IMX_SC_R_LVDS_1_I2C_0 272U +#define IMX_SC_R_LVDS_1_I2C_1 273U +#define IMX_SC_R_LVDS_2 274U +#define IMX_SC_R_LVDS_2_PWM_0 275U +#define IMX_SC_R_LVDS_2_I2C_0 276U +#define IMX_SC_R_LVDS_2_I2C_1 277U +#define IMX_SC_R_M4_0_PID0 278U +#define IMX_SC_R_M4_0_PID1 279U +#define IMX_SC_R_M4_0_PID2 280U +#define IMX_SC_R_M4_0_PID3 281U +#define IMX_SC_R_M4_0_PID4 282U +#define IMX_SC_R_M4_0_RGPIO 283U +#define IMX_SC_R_M4_0_SEMA42 284U +#define IMX_SC_R_M4_0_TPM 285U +#define IMX_SC_R_M4_0_PIT 286U +#define IMX_SC_R_M4_0_UART 287U +#define IMX_SC_R_M4_0_I2C 288U +#define IMX_SC_R_M4_0_INTMUX 289U +#define IMX_SC_R_ENET_0_A0 290U +#define IMX_SC_R_ENET_0_A1 291U +#define IMX_SC_R_M4_0_MU_0B 292U +#define IMX_SC_R_M4_0_MU_0A0 293U +#define IMX_SC_R_M4_0_MU_0A1 294U +#define IMX_SC_R_M4_0_MU_0A2 295U +#define IMX_SC_R_M4_0_MU_0A3 296U +#define IMX_SC_R_M4_0_MU_1A 297U +#define IMX_SC_R_M4_1_PID0 298U +#define IMX_SC_R_M4_1_PID1 299U +#define IMX_SC_R_M4_1_PID2 300U +#define IMX_SC_R_M4_1_PID3 301U +#define IMX_SC_R_M4_1_PID4 302U +#define IMX_SC_R_M4_1_RGPIO 303U +#define IMX_SC_R_M4_1_SEMA42 304U +#define IMX_SC_R_M4_1_TPM 305U +#define IMX_SC_R_M4_1_PIT 306U +#define IMX_SC_R_M4_1_UART 307U +#define IMX_SC_R_M4_1_I2C 308U +#define IMX_SC_R_M4_1_INTMUX 309U +#define IMX_SC_R_UNUSED17 310U +#define IMX_SC_R_UNUSED18 311U +#define IMX_SC_R_M4_1_MU_0B 312U +#define IMX_SC_R_M4_1_MU_0A0 313U +#define IMX_SC_R_M4_1_MU_0A1 314U +#define IMX_SC_R_M4_1_MU_0A2 315U +#define IMX_SC_R_M4_1_MU_0A3 316U +#define IMX_SC_R_M4_1_MU_1A 317U +#define IMX_SC_R_SAI_0 318U +#define IMX_SC_R_SAI_1 319U +#define IMX_SC_R_SAI_2 320U +#define IMX_SC_R_IRQSTR_SCU2 321U +#define IMX_SC_R_IRQSTR_DSP 322U +#define IMX_SC_R_ELCDIF_PLL 323U +#define IMX_SC_R_OCRAM 324U +#define IMX_SC_R_AUDIO_PLL_0 325U +#define IMX_SC_R_PI_0 326U +#define IMX_SC_R_PI_0_PWM_0 327U +#define IMX_SC_R_PI_0_PWM_1 328U +#define IMX_SC_R_PI_0_I2C_0 329U +#define IMX_SC_R_PI_0_PLL 330U +#define IMX_SC_R_PI_1 331U +#define IMX_SC_R_PI_1_PWM_0 332U +#define IMX_SC_R_PI_1_PWM_1 333U +#define IMX_SC_R_PI_1_I2C_0 334U +#define IMX_SC_R_PI_1_PLL 335U +#define IMX_SC_R_SC_PID0 336U +#define IMX_SC_R_SC_PID1 337U +#define IMX_SC_R_SC_PID2 338U +#define IMX_SC_R_SC_PID3 339U +#define IMX_SC_R_SC_PID4 340U +#define IMX_SC_R_SC_SEMA42 341U +#define IMX_SC_R_SC_TPM 342U +#define IMX_SC_R_SC_PIT 343U +#define IMX_SC_R_SC_UART 344U +#define IMX_SC_R_SC_I2C 345U +#define IMX_SC_R_SC_MU_0B 346U +#define IMX_SC_R_SC_MU_0A0 347U +#define IMX_SC_R_SC_MU_0A1 348U +#define IMX_SC_R_SC_MU_0A2 349U +#define IMX_SC_R_SC_MU_0A3 350U +#define IMX_SC_R_SC_MU_1A 351U +#define IMX_SC_R_SYSCNT_RD 352U +#define IMX_SC_R_SYSCNT_CMP 353U +#define IMX_SC_R_DEBUG 354U +#define IMX_SC_R_SYSTEM 355U +#define IMX_SC_R_SNVS 356U +#define IMX_SC_R_OTP 357U +#define IMX_SC_R_VPU_PID0 358U +#define IMX_SC_R_VPU_PID1 359U +#define IMX_SC_R_VPU_PID2 360U +#define IMX_SC_R_VPU_PID3 361U +#define IMX_SC_R_VPU_PID4 362U +#define IMX_SC_R_VPU_PID5 363U +#define IMX_SC_R_VPU_PID6 364U +#define IMX_SC_R_VPU_PID7 365U +#define IMX_SC_R_ENET_0_A2 366U +#define IMX_SC_R_ENET_1_A0 367U +#define IMX_SC_R_ENET_1_A1 368U +#define IMX_SC_R_ENET_1_A2 369U +#define IMX_SC_R_ENET_1_A3 370U +#define IMX_SC_R_ENET_1_A4 371U +#define IMX_SC_R_DMA_4_CH0 372U +#define IMX_SC_R_DMA_4_CH1 373U +#define IMX_SC_R_DMA_4_CH2 374U +#define IMX_SC_R_DMA_4_CH3 375U +#define IMX_SC_R_DMA_4_CH4 376U +#define IMX_SC_R_ISI_CH0 377U +#define IMX_SC_R_ISI_CH1 378U +#define IMX_SC_R_ISI_CH2 379U +#define IMX_SC_R_ISI_CH3 380U +#define IMX_SC_R_ISI_CH4 381U +#define IMX_SC_R_ISI_CH5 382U +#define IMX_SC_R_ISI_CH6 383U +#define IMX_SC_R_ISI_CH7 384U +#define IMX_SC_R_MJPEG_DEC_S0 385U +#define IMX_SC_R_MJPEG_DEC_S1 386U +#define IMX_SC_R_MJPEG_DEC_S2 387U +#define IMX_SC_R_MJPEG_DEC_S3 388U +#define IMX_SC_R_MJPEG_ENC_S0 389U +#define IMX_SC_R_MJPEG_ENC_S1 390U +#define IMX_SC_R_MJPEG_ENC_S2 391U +#define IMX_SC_R_MJPEG_ENC_S3 392U +#define IMX_SC_R_MIPI_0 393U +#define IMX_SC_R_MIPI_0_PWM_0 394U +#define IMX_SC_R_MIPI_0_I2C_0 395U +#define IMX_SC_R_MIPI_0_I2C_1 396U +#define IMX_SC_R_MIPI_1 397U +#define IMX_SC_R_MIPI_1_PWM_0 398U +#define IMX_SC_R_MIPI_1_I2C_0 399U +#define IMX_SC_R_MIPI_1_I2C_1 400U +#define IMX_SC_R_CSI_0 401U +#define IMX_SC_R_CSI_0_PWM_0 402U +#define IMX_SC_R_CSI_0_I2C_0 403U +#define IMX_SC_R_CSI_1 404U +#define IMX_SC_R_CSI_1_PWM_0 405U +#define IMX_SC_R_CSI_1_I2C_0 406U +#define IMX_SC_R_HDMI 407U +#define IMX_SC_R_HDMI_I2S 408U +#define IMX_SC_R_HDMI_I2C_0 409U +#define IMX_SC_R_HDMI_PLL_0 410U +#define IMX_SC_R_HDMI_RX 411U +#define IMX_SC_R_HDMI_RX_BYPASS 412U +#define IMX_SC_R_HDMI_RX_I2C_0 413U +#define IMX_SC_R_ASRC_0 414U +#define IMX_SC_R_ESAI_0 415U +#define IMX_SC_R_SPDIF_0 416U +#define IMX_SC_R_SPDIF_1 417U +#define IMX_SC_R_SAI_3 418U +#define IMX_SC_R_SAI_4 419U +#define IMX_SC_R_SAI_5 420U +#define IMX_SC_R_GPT_5 421U +#define IMX_SC_R_GPT_6 422U +#define IMX_SC_R_GPT_7 423U +#define IMX_SC_R_GPT_8 424U +#define IMX_SC_R_GPT_9 425U +#define IMX_SC_R_GPT_10 426U +#define IMX_SC_R_DMA_2_CH5 427U +#define IMX_SC_R_DMA_2_CH6 428U +#define IMX_SC_R_DMA_2_CH7 429U +#define IMX_SC_R_DMA_2_CH8 430U +#define IMX_SC_R_DMA_2_CH9 431U +#define IMX_SC_R_DMA_2_CH10 432U +#define IMX_SC_R_DMA_2_CH11 433U +#define IMX_SC_R_DMA_2_CH12 434U +#define IMX_SC_R_DMA_2_CH13 435U +#define IMX_SC_R_DMA_2_CH14 436U +#define IMX_SC_R_DMA_2_CH15 437U +#define IMX_SC_R_DMA_2_CH16 438U +#define IMX_SC_R_DMA_2_CH17 439U +#define IMX_SC_R_DMA_2_CH18 440U +#define IMX_SC_R_DMA_2_CH19 441U +#define IMX_SC_R_DMA_2_CH20 442U +#define IMX_SC_R_DMA_2_CH21 443U +#define IMX_SC_R_DMA_2_CH22 444U +#define IMX_SC_R_DMA_2_CH23 445U +#define IMX_SC_R_DMA_2_CH24 446U +#define IMX_SC_R_DMA_2_CH25 447U +#define IMX_SC_R_DMA_2_CH26 448U +#define IMX_SC_R_DMA_2_CH27 449U +#define IMX_SC_R_DMA_2_CH28 450U +#define IMX_SC_R_DMA_2_CH29 451U +#define IMX_SC_R_DMA_2_CH30 452U +#define IMX_SC_R_DMA_2_CH31 453U +#define IMX_SC_R_ASRC_1 454U +#define IMX_SC_R_ESAI_1 455U +#define IMX_SC_R_SAI_6 456U +#define IMX_SC_R_SAI_7 457U +#define IMX_SC_R_AMIX 458U +#define IMX_SC_R_MQS_0 459U +#define IMX_SC_R_DMA_3_CH0 460U +#define IMX_SC_R_DMA_3_CH1 461U +#define IMX_SC_R_DMA_3_CH2 462U +#define IMX_SC_R_DMA_3_CH3 463U +#define IMX_SC_R_DMA_3_CH4 464U +#define IMX_SC_R_DMA_3_CH5 465U +#define IMX_SC_R_DMA_3_CH6 466U +#define IMX_SC_R_DMA_3_CH7 467U +#define IMX_SC_R_DMA_3_CH8 468U +#define IMX_SC_R_DMA_3_CH9 469U +#define IMX_SC_R_DMA_3_CH10 470U +#define IMX_SC_R_DMA_3_CH11 471U +#define IMX_SC_R_DMA_3_CH12 472U +#define IMX_SC_R_DMA_3_CH13 473U +#define IMX_SC_R_DMA_3_CH14 474U +#define IMX_SC_R_DMA_3_CH15 475U +#define IMX_SC_R_DMA_3_CH16 476U +#define IMX_SC_R_DMA_3_CH17 477U +#define IMX_SC_R_DMA_3_CH18 478U +#define IMX_SC_R_DMA_3_CH19 479U +#define IMX_SC_R_DMA_3_CH20 480U +#define IMX_SC_R_DMA_3_CH21 481U +#define IMX_SC_R_DMA_3_CH22 482U +#define IMX_SC_R_DMA_3_CH23 483U +#define IMX_SC_R_DMA_3_CH24 484U +#define IMX_SC_R_DMA_3_CH25 485U +#define IMX_SC_R_DMA_3_CH26 486U +#define IMX_SC_R_DMA_3_CH27 487U +#define IMX_SC_R_DMA_3_CH28 488U +#define IMX_SC_R_DMA_3_CH29 489U +#define IMX_SC_R_DMA_3_CH30 490U +#define IMX_SC_R_DMA_3_CH31 491U +#define IMX_SC_R_AUDIO_PLL_1 492U +#define IMX_SC_R_AUDIO_CLK_0 493U +#define IMX_SC_R_AUDIO_CLK_1 494U +#define IMX_SC_R_MCLK_OUT_0 495U +#define IMX_SC_R_MCLK_OUT_1 496U +#define IMX_SC_R_PMIC_0 497U +#define IMX_SC_R_PMIC_1 498U +#define IMX_SC_R_SECO 499U +#define IMX_SC_R_CAAM_JR1 500U +#define IMX_SC_R_CAAM_JR2 501U +#define IMX_SC_R_CAAM_JR3 502U +#define IMX_SC_R_SECO_MU_2 503U +#define IMX_SC_R_SECO_MU_3 504U +#define IMX_SC_R_SECO_MU_4 505U +#define IMX_SC_R_HDMI_RX_PWM_0 506U +#define IMX_SC_R_A35 507U +#define IMX_SC_R_A35_0 508U +#define IMX_SC_R_A35_1 509U +#define IMX_SC_R_A35_2 510U +#define IMX_SC_R_A35_3 511U +#define IMX_SC_R_DSP 512U +#define IMX_SC_R_DSP_RAM 513U +#define IMX_SC_R_CAAM_JR1_OUT 514U +#define IMX_SC_R_CAAM_JR2_OUT 515U +#define IMX_SC_R_CAAM_JR3_OUT 516U +#define IMX_SC_R_VPU_DEC_0 517U +#define IMX_SC_R_VPU_ENC_0 518U +#define IMX_SC_R_CAAM_JR0 519U +#define IMX_SC_R_CAAM_JR0_OUT 520U +#define IMX_SC_R_PMIC_2 521U +#define IMX_SC_R_DBLOGIC 522U +#define IMX_SC_R_HDMI_PLL_1 523U +#define IMX_SC_R_BOARD_R0 524U +#define IMX_SC_R_BOARD_R1 525U +#define IMX_SC_R_BOARD_R2 526U +#define IMX_SC_R_BOARD_R3 527U +#define IMX_SC_R_BOARD_R4 528U +#define IMX_SC_R_BOARD_R5 529U +#define IMX_SC_R_BOARD_R6 530U +#define IMX_SC_R_BOARD_R7 531U +#define IMX_SC_R_MJPEG_DEC_MP 532U +#define IMX_SC_R_MJPEG_ENC_MP 533U +#define IMX_SC_R_VPU_TS_0 534U +#define IMX_SC_R_VPU_MU_0 535U +#define IMX_SC_R_VPU_MU_1 536U +#define IMX_SC_R_VPU_MU_2 537U +#define IMX_SC_R_VPU_MU_3 538U +#define IMX_SC_R_VPU_ENC_1 539U +#define IMX_SC_R_VPU 540U +#define IMX_SC_R_DMA_5_CH0 541U +#define IMX_SC_R_DMA_5_CH1 542U +#define IMX_SC_R_DMA_5_CH2 543U +#define IMX_SC_R_DMA_5_CH3 544U +#define IMX_SC_R_ATTESTATION 545U +#define IMX_SC_R_LAST 546U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX_SCU_RSRC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/imx_spc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/imx_spc.h new file mode 100644 index 00000000..68f45e9d --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/imx_spc.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +/* + * Setpoint definitions for IMX Set point controller. The SPC uses a series + * of set points to determine the clock speeds and states of cores, as well + * as which peripherals to gate clocks to. Higher values correspond to more + * power saving. See your SOC's datasheet for specifics of what peripherals + * have their clocks gated at each set point. + * + * Set point control is implemented at the soc level (see pm_state_set()) + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_ + +#define IMX_GPC_RUN 0x0 +#define IMX_GPC_WAIT 0x1 +#define IMX_GPC_STOP 0x2 +#define IMX_GPC_SUSPEND 0x3 + + +#define IMX_SPC_MASK 0xF0 +#define IMX_SPC_SHIFT 4 +#define IMX_GPC_MODE_MASK 0xF + +#define IMX_SPC(x) ((x & IMX_SPC_MASK) >> IMX_SPC_SHIFT) +#define IMX_GPC_MODE(x) (x & IMX_GPC_MODE_MASK) + +#define IMX_SPC_0 0x00 +#define IMX_SPC_1 0x10 +#define IMX_SPC_2 0x20 +#define IMX_SPC_3 0x30 +#define IMX_SPC_4 0x40 +#define IMX_SPC_5 0x50 +#define IMX_SPC_6 0x60 +#define IMX_SPC_7 0x70 +#define IMX_SPC_8 0x80 +#define IMX_SPC_9 0x90 +#define IMX_SPC_10 0xA0 +#define IMX_SPC_11 0xB0 +#define IMX_SPC_12 0xC0 +#define IMX_SPC_13 0xD0 +#define IMX_SPC_14 0xE0 +#define IMX_SPC_15 0xF0 + + +#define IMX_SPC_SET_POINT_0_RUN (IMX_SPC_0 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_0_WAIT (IMX_SPC_0 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_0_STOP (IMX_SPC_0 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_0_SUSPEND (IMX_SPC_0 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_1_RUN (IMX_SPC_1 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_1_WAIT (IMX_SPC_1 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_1_STOP (IMX_SPC_1 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_1_SUSPEND (IMX_SPC_1 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_2_RUN (IMX_SPC_2 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_2_WAIT (IMX_SPC_2 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_2_STOP (IMX_SPC_2 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_2_SUSPEND (IMX_SPC_2 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_3_RUN (IMX_SPC_3 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_3_WAIT (IMX_SPC_3 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_3_STOP (IMX_SPC_3 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_3_SUSPEND (IMX_SPC_3 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_4_RUN (IMX_SPC_4 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_4_WAIT (IMX_SPC_4 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_4_STOP (IMX_SPC_4 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_4_SUSPEND (IMX_SPC_4 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_5_RUN (IMX_SPC_5 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_5_WAIT (IMX_SPC_5 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_5_STOP (IMX_SPC_5 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_5_SUSPEND (IMX_SPC_5 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_6_RUN (IMX_SPC_6 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_6_WAIT (IMX_SPC_6 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_6_STOP (IMX_SPC_6 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_6_SUSPEND (IMX_SPC_6 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_7_RUN (IMX_SPC_7 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_7_WAIT (IMX_SPC_7 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_7_STOP (IMX_SPC_7 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_7_SUSPEND (IMX_SPC_7 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_8_RUN (IMX_SPC_8 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_8_WAIT (IMX_SPC_8 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_8_STOP (IMX_SPC_8 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_8_SUSPEND (IMX_SPC_8 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_9_RUN (IMX_SPC_9 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_9_WAIT (IMX_SPC_9 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_9_STOP (IMX_SPC_9 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_9_SUSPEND (IMX_SPC_9 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_10_RUN (IMX_SPC_10 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_10_WAIT (IMX_SPC_10 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_10_STOP (IMX_SPC_10 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_10_SUSPEND (IMX_SPC_10 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_11_RUN (IMX_SPC_11 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_11_WAIT (IMX_SPC_11 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_11_STOP (IMX_SPC_11 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_11_SUSPEND (IMX_SPC_11 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_12_RUN (IMX_SPC_12 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_12_WAIT (IMX_SPC_12 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_12_STOP (IMX_SPC_12 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_12_SUSPEND (IMX_SPC_12 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_13_RUN (IMX_SPC_13 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_13_WAIT (IMX_SPC_13 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_13_STOP (IMX_SPC_13 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_13_SUSPEND (IMX_SPC_13 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_14_RUN (IMX_SPC_14 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_14_WAIT (IMX_SPC_14 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_14_STOP (IMX_SPC_14 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_14_SUSPEND (IMX_SPC_14 | IMX_GPC_SUSPEND) +#define IMX_SPC_SET_POINT_15_RUN (IMX_SPC_15 | IMX_GPC_RUN) +#define IMX_SPC_SET_POINT_15_WAIT (IMX_SPC_15 | IMX_GPC_WAIT) +#define IMX_SPC_SET_POINT_15_STOP (IMX_SPC_15 | IMX_GPC_STOP) +#define IMX_SPC_SET_POINT_15_SUSPEND (IMX_SPC_15 | IMX_GPC_SUSPEND) + + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PM_IMX_SPC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/nordic-nrf-gpd.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/nordic-nrf-gpd.h new file mode 100644 index 00000000..7f6952f6 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/power/nordic-nrf-gpd.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD +#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD + +/* numbers aligned to nrfs service identifiers */ +#define NRF_GPD_SLOW_MAIN 2U +#define NRF_GPD_SLOW_ACTIVE 1U +#define NRF_GPD_FAST_MAIN 3U +#define NRF_GPD_FAST_ACTIVE1 0U +#define NRF_GPD_FAST_ACTIVE0 4U + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_NORDIC_NRF_GLOBAL_PD */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h new file mode 100644 index 00000000..82256c70 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h @@ -0,0 +1,11 @@ +/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or + * an affiliate of Cypress Semiconductor Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * Divider Type + */ +#define CY_SYSCLK_DIV_8_BIT 0 +#define CY_SYSCLK_DIV_16_BIT 1 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pwm/ra_pwm.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pwm/ra_pwm.h new file mode 100644 index 00000000..e2f8a45e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/pwm/ra_pwm.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_RA_PWM_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_RA_PWM_H_ + +/* PWM SOURCE DIVIDER */ +#define RA_PWM_SOURCE_DIV_1 0 +#define RA_PWM_SOURCE_DIV_2 1 +#define RA_PWM_SOURCE_DIV_4 2 +#define RA_PWM_SOURCE_DIV_8 3 +#define RA_PWM_SOURCE_DIV_16 4 +#define RA_PWM_SOURCE_DIV_32 5 +#define RA_PWM_SOURCE_DIV_64 6 +#define RA_PWM_SOURCE_DIV_128 7 +#define RA_PWM_SOURCE_DIV_256 8 +#define RA_PWM_SOURCE_DIV_512 9 +#define RA_PWM_SOURCE_DIV_1024 10 + +/* PWM SOURCE DIVIDER */ +#define RA_PWM_CHANNEL_0 0 +#define RA_PWM_CHANNEL_1 1 +#define RA_PWM_CHANNEL_2 2 +#define RA_PWM_CHANNEL_3 3 +#define RA_PWM_CHANNEL_4 4 +#define RA_PWM_CHANNEL_5 5 +#define RA_PWM_CHANNEL_6 6 +#define RA_PWM_CHANNEL_7 7 +#define RA_PWM_CHANNEL_8 8 +#define RA_PWM_CHANNEL_9 9 +#define RA_PWM_CHANNEL_10 10 +#define RA_PWM_CHANNEL_11 11 +#define RA_PWM_CHANNEL_12 12 +#define RA_PWM_CHANNEL_13 13 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_RA_PWM_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/npm2100.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/npm2100.h new file mode 100644 index 00000000..2ec703bb --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/npm2100.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM2100_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM2100_H_ + +/** + * @defgroup regulator_npm2100 NPM2100 Devicetree helpers. + * @ingroup regulator_interface + * @{ + */ + +/** + * @name NPM2100 Regulator modes + * @{ + */ +/* Load switch selection, applies to LDOSW only */ +#define NPM2100_REG_LDSW_EN 0x01U + +/* DPS modes applies to BOOST only */ +#define NPM2100_REG_DPS_MASK 0x03U +#define NPM2100_REG_DPS_ALLOW 0x01U +#define NPM2100_REG_DPS_ALLOWLP 0x02U + +/* Operating mode */ +#define NPM2100_REG_OPER_MASK 0x1CU +#define NPM2100_REG_OPER_AUTO 0x00U +#define NPM2100_REG_OPER_HP 0x04U +#define NPM2100_REG_OPER_LP 0x08U +#define NPM2100_REG_OPER_ULP 0x0CU +#define NPM2100_REG_OPER_PASS 0x10U +#define NPM2100_REG_OPER_NOHP 0x14U +#define NPM2100_REG_OPER_OFF 0x18U + +/* Forced mode when GPIO active */ +#define NPM2100_REG_FORCE_MASK 0xE0U +#define NPM2100_REG_FORCE_HP 0x20U +#define NPM2100_REG_FORCE_LP 0x40U +#define NPM2100_REG_FORCE_ULP 0x60U +#define NPM2100_REG_FORCE_PASS 0x80U +#define NPM2100_REG_FORCE_NOHP 0xA0U + +/** @} */ + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NPM2100_H_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/nrf5x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/nrf5x.h new file mode 100644 index 00000000..1f4e048e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/nrf5x.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF5X_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF5X_H_ + +/** + * @defgroup regulator_nrf5x nRF5X regulator devicetree helpers. + * @ingroup regulator_interface + * @{ + */ + +/** + * @name nRF5X regulator modes + * @{ + */ +/** LDO mode */ +#define NRF5X_REG_MODE_LDO 0 +/** DC/DC mode */ +#define NRF5X_REG_MODE_DCDC 1 +/** @} */ + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_NRF5X_H_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/silabs_dcdc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/silabs_dcdc.h new file mode 100644 index 00000000..f2547346 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/regulator/silabs_dcdc.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_SILABS_DCDC_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_SILABS_DCDC_H_ + +/** + * @defgroup regulator_silabs_dcdc Silabs DCDC devicetree helpers. + * @ingroup regulator_interface + * @{ + */ + +/** + * @name Silabs DCDC modes + * @{ + */ +/** Buck mode */ +#define SILABS_DCDC_MODE_BUCK 0 +/** Boost mode */ +#define SILABS_DCDC_MODE_BOOST 1 +/** @} */ + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_REGULATOR_SILABS_DCDC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h new file mode 100644 index 00000000..90f43379 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESERVED_MEMORY_NORDIC_OWNED_MEMORY_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESERVED_MEMORY_NORDIC_OWNED_MEMORY_H_ + +#include + +/** + * @name Basic memory permission flags. + * @{ + */ + +/** Readable. */ +#define NRF_PERM_R BIT(0) +/** Writable. */ +#define NRF_PERM_W BIT(1) +/** Executable. */ +#define NRF_PERM_X BIT(2) +/** Secure-only. */ +#define NRF_PERM_S BIT(3) +/** Non-secure-callable. */ +#define NRF_PERM_NSC BIT(4) + +/** + * @} + */ + +/** + * @name Memory permission flag combinations. + * @note NRF_PERM_NSC overrides all other flags, so it is not included here. + * @{ + */ + +#define NRF_PERM_RW (NRF_PERM_R | NRF_PERM_W) +#define NRF_PERM_RX (NRF_PERM_R | NRF_PERM_X) +#define NRF_PERM_RS (NRF_PERM_R | NRF_PERM_S) +#define NRF_PERM_WX (NRF_PERM_W | NRF_PERM_X) +#define NRF_PERM_WS (NRF_PERM_W | NRF_PERM_S) +#define NRF_PERM_XS (NRF_PERM_X | NRF_PERM_S) +#define NRF_PERM_RWX (NRF_PERM_R | NRF_PERM_W | NRF_PERM_X) +#define NRF_PERM_RWS (NRF_PERM_R | NRF_PERM_W | NRF_PERM_S) +#define NRF_PERM_RXS (NRF_PERM_R | NRF_PERM_X | NRF_PERM_S) +#define NRF_PERM_WXS (NRF_PERM_W | NRF_PERM_X | NRF_PERM_S) +#define NRF_PERM_RWXS (NRF_PERM_R | NRF_PERM_W | NRF_PERM_X | NRF_PERM_S) + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESERVED_MEMORY_NORDIC_OWNED_MEMORY_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/rp2040_reset.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/rp2040_reset.h new file mode 100644 index 00000000..eeb253c3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/rp2040_reset.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2021 Yonatan Schachter + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ + +#define RPI_PICO_RESETS_RESET_ADC 0 +#define RPI_PICO_RESETS_RESET_BUSCTRL 1 +#define RPI_PICO_RESETS_RESET_DMA 2 +#define RPI_PICO_RESETS_RESET_I2C0 3 +#define RPI_PICO_RESETS_RESET_I2C1 4 +#define RPI_PICO_RESETS_RESET_IO_BANK0 5 +#define RPI_PICO_RESETS_RESET_IO_QSPI 6 +#define RPI_PICO_RESETS_RESET_JTAG 7 +#define RPI_PICO_RESETS_RESET_PADS_BANK0 8 +#define RPI_PICO_RESETS_RESET_PADS_QSPI 9 +#define RPI_PICO_RESETS_RESET_PIO0 10 +#define RPI_PICO_RESETS_RESET_PIO1 11 +#define RPI_PICO_RESETS_RESET_PLL_SYS 12 +#define RPI_PICO_RESETS_RESET_PLL_USB 13 +#define RPI_PICO_RESETS_RESET_PWM 14 +#define RPI_PICO_RESETS_RESET_RTC 15 +#define RPI_PICO_RESETS_RESET_SPI0 16 +#define RPI_PICO_RESETS_RESET_SPI1 17 +#define RPI_PICO_RESETS_RESET_SYSCFG 18 +#define RPI_PICO_RESETS_RESET_SYSINFO 19 +#define RPI_PICO_RESETS_RESET_TBMAN 20 +#define RPI_PICO_RESETS_RESET_TIMER 21 +#define RPI_PICO_RESETS_RESET_UART0 22 +#define RPI_PICO_RESETS_RESET_UART1 23 +#define RPI_PICO_RESETS_RESET_USBCTRL 24 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/stm32u0_reset.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/stm32u0_reset.h new file mode 100644 index 00000000..424f836a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/stm32u0_reset.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U0_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U0_RESET_H_ + +#include "stm32-common.h" + +/* RCC bus reset register offset */ +#define STM32_RESET_BUS_IOP 0x2C +#define STM32_RESET_BUS_AHB1 0x28 +#define STM32_RESET_BUS_APB1L 0x38 +#define STM32_RESET_BUS_APB1H 0x40 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32U0_RESET_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/stm32wb0_reset.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/stm32wb0_reset.h new file mode 100644 index 00000000..8fe2a84a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/reset/stm32wb0_reset.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB0_RESET_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB0_RESET_H_ + +#include "stm32-common.h" + +/* RCC bus reset register offset */ +#define STM32_RESET_BUS_AHB0 0x30 +#define STM32_RESET_BUS_APB0 0x34 +#define STM32_RESET_BUS_APB1 0x38 +#define STM32_RESET_BUS_APB2 0x3C + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32WB0_RESET_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/apds9253.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/apds9253.h new file mode 100644 index 00000000..0768ec4f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/apds9253.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2018 PHYTEC Messtechnik GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_APDS9253_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_APDS9253_H_ + +#include + +/** + * @name apds9253 resolution channel references + * @{ + */ + +#define APDS9253_RESOLUTION_20BIT_400MS 0 +#define APDS9253_RESOLUTION_19BIT_200MS BIT(4) +#define APDS9253_RESOLUTION_18BIT_100MS BIT(5) /* default */ +#define APDS9253_RESOLUTION_17BIT_50MS (BIT(5) | BIT(4)) +#define APDS9253_RESOLUTION_16BIT_25MS BIT(6) +#define APDS9253_RESOLUTION_13BIT_3MS (BIT(6) | BIT(4)) + +/** @} */ + +/** + * @name apds9253 measurement rate + * @{ + */ + +#define APDS9253_MEASUREMENT_RATE_2000MS (BIT(2) | BIT(1) | BIT(0)) +#define APDS9253_MEASUREMENT_RATE_1000MS (BIT(2) | BIT(0)) +#define APDS9253_MEASUREMENT_RATE_500MS BIT(2) +#define APDS9253_MEASUREMENT_RATE_200MS (BIT(1) | BIT(0)) +#define APDS9253_MEASUREMENT_RATE_100MS BIT(1) /* default */ +#define APDS9253_MEASUREMENT_RATE_50MS BIT(0) +#define APDS9253_MEASUREMENT_RATE_25MS 0 + +/** @} */ + +/** + * @name apds9253 gain range + * @{ + */ + +#define APDS9253_GAIN_RANGE_18 BIT(2) +#define APDS9253_GAIN_RANGE_9 (BIT(1) | BIT(0)) +#define APDS9253_GAIN_RANGE_6 BIT(1) +#define APDS9253_GAIN_RANGE_3 BIT(0) /* default */ +#define APDS9253_GAIN_RANGE_1 0 + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_APDS9253_H_*/ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lis2dw12.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lis2dw12.h index 9e5892ec..e5d2e048 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lis2dw12.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lis2dw12.h @@ -39,4 +39,22 @@ #define LIS2DW12_DT_WAKEUP_3_ODR 2 #define LIS2DW12_DT_WAKEUP_4_ODR 3 +/* sleep duration */ +#define LIS2DW12_DT_SLEEP_0_ODR 0 +#define LIS2DW12_DT_SLEEP_1_ODR 1 +#define LIS2DW12_DT_SLEEP_2_ODR 2 +#define LIS2DW12_DT_SLEEP_3_ODR 3 +#define LIS2DW12_DT_SLEEP_4_ODR 4 +#define LIS2DW12_DT_SLEEP_5_ODR 5 +#define LIS2DW12_DT_SLEEP_6_ODR 6 +#define LIS2DW12_DT_SLEEP_7_ODR 7 +#define LIS2DW12_DT_SLEEP_8_ODR 8 +#define LIS2DW12_DT_SLEEP_9_ODR 9 +#define LIS2DW12_DT_SLEEP_10_ODR 10 +#define LIS2DW12_DT_SLEEP_11_ODR 11 +#define LIS2DW12_DT_SLEEP_12_ODR 12 +#define LIS2DW12_DT_SLEEP_13_ODR 13 +#define LIS2DW12_DT_SLEEP_14_ODR 14 +#define LIS2DW12_DT_SLEEP_15_ODR 15 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LIS2DW12_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lps2xdf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lps2xdf.h index bcbb831b..b1dffa81 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lps2xdf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lps2xdf.h @@ -37,4 +37,8 @@ #define LPS28DFW_DT_FS_MODE_1_1260 0 #define LPS28DFW_DT_FS_MODE_2_4060 1 +/* Full Scale Pressure Mode */ +#define ILPS22QS_DT_FS_MODE_1_1260 0 +#define ILPS22QS_DT_FS_MODE_2_4060 1 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LPS22DF_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h index 533dd5e3..76caabbd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h @@ -55,4 +55,40 @@ #define LSM6DSV16X_DT_ODR_HA02_AT_3200Hz 0x2B #define LSM6DSV16X_DT_ODR_HA02_AT_6400Hz 0x2C +/* Accelerometer batching rates */ +#define LSM6DSV16X_DT_XL_NOT_BATCHED 0x0 +#define LSM6DSV16X_DT_XL_BATCHED_AT_1Hz875 0x1 +#define LSM6DSV16X_DT_XL_BATCHED_AT_7Hz5 0x2 +#define LSM6DSV16X_DT_XL_BATCHED_AT_15Hz 0x3 +#define LSM6DSV16X_DT_XL_BATCHED_AT_30Hz 0x4 +#define LSM6DSV16X_DT_XL_BATCHED_AT_60Hz 0x5 +#define LSM6DSV16X_DT_XL_BATCHED_AT_120Hz 0x6 +#define LSM6DSV16X_DT_XL_BATCHED_AT_240Hz 0x7 +#define LSM6DSV16X_DT_XL_BATCHED_AT_480Hz 0x8 +#define LSM6DSV16X_DT_XL_BATCHED_AT_960Hz 0x9 +#define LSM6DSV16X_DT_XL_BATCHED_AT_1920Hz 0xa +#define LSM6DSV16X_DT_XL_BATCHED_AT_3840Hz 0xb +#define LSM6DSV16X_DT_XL_BATCHED_AT_7680Hz 0xc + +/* Gyroscope batching rates */ +#define LSM6DSV16X_DT_GY_NOT_BATCHED 0x0 +#define LSM6DSV16X_DT_GY_BATCHED_AT_1Hz875 0x1 +#define LSM6DSV16X_DT_GY_BATCHED_AT_7Hz5 0x2 +#define LSM6DSV16X_DT_GY_BATCHED_AT_15Hz 0x3 +#define LSM6DSV16X_DT_GY_BATCHED_AT_30Hz 0x4 +#define LSM6DSV16X_DT_GY_BATCHED_AT_60Hz 0x5 +#define LSM6DSV16X_DT_GY_BATCHED_AT_120Hz 0x6 +#define LSM6DSV16X_DT_GY_BATCHED_AT_240Hz 0x7 +#define LSM6DSV16X_DT_GY_BATCHED_AT_480Hz 0x8 +#define LSM6DSV16X_DT_GY_BATCHED_AT_960Hz 0x9 +#define LSM6DSV16X_DT_GY_BATCHED_AT_1920Hz 0xa +#define LSM6DSV16X_DT_GY_BATCHED_AT_3840Hz 0xb +#define LSM6DSV16X_DT_GY_BATCHED_AT_7680Hz 0xc + +/* Temperature sensor batching rates */ +#define LSM6DSV16X_DT_TEMP_NOT_BATCHED 0x0 +#define LSM6DSV16X_DT_TEMP_BATCHED_AT_1Hz875 0x1 +#define LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz 0x2 +#define LSM6DSV16X_DT_TEMP_BATCHED_AT_60Hz 0x3 + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSV16X_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm9ds1.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm9ds1.h new file mode 100644 index 00000000..747d145e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/lsm9ds1.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2024 Bootlin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM9DS1_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM9DS1_H_ + +/* Accel range */ +#define LSM9DS1_DT_FS_2G 0 +#define LSM9DS1_DT_FS_16G 1 +#define LSM9DS1_DT_FS_4G 2 +#define LSM9DS1_DT_FS_8G 3 + +#define LSM9DS1_DT_FS_245DPS 0 +#define LSM9DS1_DT_FS_500DPS 1 +#define LSM9DS1_DT_FS_2000DPS 3 + +#define LSM9DS1_IMU_OFF 0x00 +#define LSM9DS1_GY_OFF_XL_10Hz 0x10 +#define LSM9DS1_GY_OFF_XL_50Hz 0x20 +#define LSM9DS1_GY_OFF_XL_119Hz 0x30 +#define LSM9DS1_GY_OFF_XL_238Hz 0x40 +#define LSM9DS1_GY_OFF_XL_476Hz 0x50 +#define LSM9DS1_GY_OFF_XL_952Hz 0x60 +#define LSM9DS1_XL_OFF_GY_14Hz9 0x01 +#define LSM9DS1_XL_OFF_GY_59Hz5 0x02 +#define LSM9DS1_XL_OFF_GY_119Hz 0x03 +#define LSM9DS1_XL_OFF_GY_238Hz 0x04 +#define LSM9DS1_XL_OFF_GY_476Hz 0x05 +#define LSM9DS1_XL_OFF_GY_952Hz 0x06 +#define LSM9DS1_IMU_14Hz9 0x11 +#define LSM9DS1_IMU_59Hz5 0x22 +#define LSM9DS1_IMU_119Hz 0x33 +#define LSM9DS1_IMU_238Hz 0x44 +#define LSM9DS1_IMU_476Hz 0x55 +#define LSM9DS1_IMU_952Hz 0x66 +#define LSM9DS1_XL_OFF_GY_14Hz9_LP 0x81 +#define LSM9DS1_XL_OFF_GY_59Hz5_LP 0x82 +#define LSM9DS1_XL_OFF_GY_119Hz_LP 0x83 +#define LSM9DS1_IMU_14Hz9_LP 0x91 +#define LSM9DS1_IMU_59Hz5_LP 0xA2 +#define LSM9DS1_IMU_119Hz_LP 0xB3 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM9DS1_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/mc3419.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/mc3419.h new file mode 100644 index 00000000..9219f5c9 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/mc3419.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2024 Croxel Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_MEMSIC_MC3419_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_MEMSIC_MC3419_H_ + +/** + * @defgroup MC3419 Memsic DT Options + * @ingroup sensor_interface + * @{ + */ + +/** + * @defgroup MC3419_LPF_CONFIGS Lowe pass filter configurations + * @{ + */ +#define MC3419_LPF_DISABLE 0 +#define MC3419_LPF_EN_WITH_IDR_BY_4p255_FC 9 +#define MC3419_LPF_EN_WITH_IDR_BY_6_FC 10 +#define MC3419_LPF_EN_WITH_IDR_BY_12_FC 11 +#define MC3419_LPF_EN_WITH_IDR_BY_16_FC 13 +/** @} */ + +/** + * @defgroup MC3419_DECIMATION_RATES decimate sampling rate by provided rate + * @{ + */ +#define MC3419_DECIMATE_IDR_BY_1 0 +#define MC3419_DECIMATE_IDR_BY_2 1 +#define MC3419_DECIMATE_IDR_BY_4 2 +#define MC3419_DECIMATE_IDR_BY_5 3 +#define MC3419_DECIMATE_IDR_BY_8 4 +#define MC3419_DECIMATE_IDR_BY_10 5 +#define MC3419_DECIMATE_IDR_BY_16 6 +#define MC3419_DECIMATE_IDR_BY_20 7 +#define MC3419_DECIMATE_IDR_BY_40 8 +#define MC3419_DECIMATE_IDR_BY_67 9 +#define MC3419_DECIMATE_IDR_BY_80 10 +#define MC3419_DECIMATE_IDR_BY_100 11 +#define MC3419_DECIMATE_IDR_BY_200 12 +#define MC3419_DECIMATE_IDR_BY_250 13 +#define MC3419_DECIMATE_IDR_BY_500 14 +#define MC3419_DECIMATE_IDR_BY_1000 15 +/** @} */ + +/** @} */ + +#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_MEMSIC_MC3419_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/tmp116.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/tmp116.h new file mode 100644 index 00000000..fa7c1363 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/sensor/tmp116.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Vitrolife A/S + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP116_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP116_H_ + +/** + * @defgroup TMP116 Texas Instruments (TI) TMP116 DT Options + * @ingroup sensor_interface + * @{ + */ + +/** + * @defgroup TMP116_ODR Temperature output data rate + * @{ + */ +#define TMP116_DT_ODR_15_5_MS 0 +#define TMP116_DT_ODR_125_MS 0x80 +#define TMP116_DT_ODR_250_MS 0x100 +#define TMP116_DT_ODR_500_MS 0x180 +#define TMP116_DT_ODR_1000_MS 0x200 +#define TMP116_DT_ODR_4000_MS 0x280 +#define TMP116_DT_ODR_8000_MS 0x300 +#define TMP116_DT_ODR_16000_MS 0x380 +/** @} */ + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP116_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/video/video-interfaces.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/video/video-interfaces.h new file mode 100644 index 00000000..062c1b5b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/dt-bindings/video/video-interfaces.h @@ -0,0 +1,17 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_VIDEO_INTERFACES_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_VIDEO_INTERFACES_H_ + +#define VIDEO_BUS_TYPE_CSI2_CPHY 1 +#define VIDEO_BUS_TYPE_CSI1 2 +#define VIDEO_BUS_TYPE_CCP2 3 +#define VIDEO_BUS_TYPE_CSI2_DPHY 4 +#define VIDEO_BUS_TYPE_PARALLEL 5 +#define VIDEO_BUS_TYPE_BT656 6 + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_VIDEO_INTERFACES_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/nvs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/nvs.h index 313e9016..df70b64f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/nvs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/nvs.h @@ -164,6 +164,30 @@ ssize_t nvs_read_hist(struct nvs_fs *fs, uint16_t id, void *data, size_t len, ui */ ssize_t nvs_calc_free_space(struct nvs_fs *fs); +/** + * @brief Tell how many contiguous free space remains in the currently active NVS sector. + * + * @param fs Pointer to the file system. + * + * @return Number of free bytes. + */ +size_t nvs_sector_max_data_size(struct nvs_fs *fs); + +/** + * @brief Close the currently active sector and switch to the next one. + * + * @note The garbage collector is called on the new sector. + * + * @warning This routine is made available for specific use cases. + * It breaks the aim of the NVS to avoid any unnecessary flash erases. + * Using this routine extensively can result in premature failure of the flash device. + * + * @param fs Pointer to the file system. + * + * @return 0 on success. On error, returns negative value of errno.h defined error codes. + */ +int nvs_sector_use_next(struct nvs_fs *fs); + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/zms.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/zms.h new file mode 100644 index 00000000..0f0fbb82 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/fs/zms.h @@ -0,0 +1,211 @@ +/* Copyright (c) 2024 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + * + * ZMS: Zephyr Memory Storage + */ +#ifndef ZEPHYR_INCLUDE_FS_ZMS_H_ +#define ZEPHYR_INCLUDE_FS_ZMS_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup zms Zephyr Memory Storage (ZMS) + * @ingroup file_system_storage + * @{ + * @} + */ + +/** + * @defgroup zms_data_structures ZMS data structures + * @ingroup zms + * @{ + */ + +/** Zephyr Memory Storage file system structure */ +struct zms_fs { + /** File system offset in flash */ + off_t offset; + /** Allocation Table Entry (ATE) write address. + * Addresses are stored as `uint64_t`: + * - high 4 bytes correspond to the sector + * - low 4 bytes are the offset in the sector + */ + uint64_t ate_wra; + /** Data write address */ + uint64_t data_wra; + /** Storage system is split into sectors. The sector size must be a multiple of + * `erase-block-size` if the device has erase capabilities + */ + uint32_t sector_size; + /** Number of sectors in the file system */ + uint32_t sector_count; + /** Current cycle counter of the active sector (pointed to by `ate_wra`) */ + uint8_t sector_cycle; + /** Flag indicating if the file system is initialized */ + bool ready; + /** Mutex used to lock flash writes */ + struct k_mutex zms_lock; + /** Flash device runtime structure */ + const struct device *flash_device; + /** Flash memory parameters structure */ + const struct flash_parameters *flash_parameters; + /** Size of an Allocation Table Entry */ + size_t ate_size; +#if CONFIG_ZMS_LOOKUP_CACHE + /** Lookup table used to cache ATE addresses of written IDs */ + uint64_t lookup_cache[CONFIG_ZMS_LOOKUP_CACHE_SIZE]; +#endif +}; + +/** + * @} + */ + +/** + * @defgroup zms_high_level_api ZMS API + * @ingroup zms + * @{ + */ + +/** + * @brief Mount a ZMS file system onto the device specified in `fs`. + * + * @param fs Pointer to the file system. + * @retval 0 Success + * @retval -ERRNO Negative errno code on error + */ +int zms_mount(struct zms_fs *fs); + +/** + * @brief Clear the ZMS file system from device. + * + * @param fs Pointer to the file system. + * @retval 0 Success + * @retval -ERRNO Negative errno code on error + */ +int zms_clear(struct zms_fs *fs); + +/** + * @brief Write an entry to the file system. + * + * @note When the `len` parameter is equal to `0` the entry is effectively removed (it is + * equivalent to calling @ref zms_delete()). It is not possible to distinguish between a deleted + * entry and an entry with data of length 0. + * + * @param fs Pointer to the file system. + * @param id ID of the entry to be written + * @param data Pointer to the data to be written + * @param len Number of bytes to be written (maximum 64 KiB) + * + * @return Number of bytes written. On success, it will be equal to the number of bytes requested + * to be written or 0. + * When a rewrite of the same data already stored is attempted, nothing is written to flash, + * thus 0 is returned. On error, returns negative value of error codes defined in `errno.h`. + */ +ssize_t zms_write(struct zms_fs *fs, uint32_t id, const void *data, size_t len); + +/** + * @brief Delete an entry from the file system + * + * @param fs Pointer to the file system. + * @param id ID of the entry to be deleted + * @retval 0 Success + * @retval -ERRNO Negative errno code on error + */ +int zms_delete(struct zms_fs *fs, uint32_t id); + +/** + * @brief Read an entry from the file system. + * + * @param fs Pointer to the file system. + * @param id ID of the entry to be read + * @param data Pointer to data buffer + * @param len Number of bytes to read at most + * + * @return Number of bytes read. On success, it will be equal to the number of bytes requested + * to be read or less than that if the stored data has a smaller size than the requested one. + * On error, returns negative value of error codes defined in `errno.h`. + */ +ssize_t zms_read(struct zms_fs *fs, uint32_t id, void *data, size_t len); + +/** + * @brief Read a history entry from the file system. + * + * @param fs Pointer to the file system. + * @param id ID of the entry to be read + * @param data Pointer to data buffer + * @param len Number of bytes to be read + * @param cnt History counter: 0: latest entry, 1: one before latest ... + * + * @return Number of bytes read. On success, it will be equal to the number of bytes requested + * to be read. When the return value is larger than the number of bytes requested to read this + * indicates not all bytes were read, and more data is available. On error, returns negative + * value of error codes defined in `errno.h`. + */ +ssize_t zms_read_hist(struct zms_fs *fs, uint32_t id, void *data, size_t len, uint32_t cnt); + +/** + * @brief Gets the length of the data that is stored in an entry with a given ID + * + * @param fs Pointer to the file system. + * @param id ID of the entry whose data length to retrieve. + * + * @return Data length contained in the ATE. On success, it will be equal to the number of bytes + * in the ATE. On error, returns negative value of error codes defined in `errno.h`. + */ +ssize_t zms_get_data_length(struct zms_fs *fs, uint32_t id); + +/** + * @brief Calculate the available free space in the file system. + * + * @param fs Pointer to the file system. + * + * @return Number of free bytes. On success, it will be equal to the number of bytes that can + * still be written to the file system. + * Calculating the free space is a time-consuming operation, especially on SPI flash. + * On error, returns negative value of error codes defined in `errno.h`. + */ +ssize_t zms_calc_free_space(struct zms_fs *fs); + +/** + * @brief Tell how much contiguous free space remains in the currently active ZMS sector. + * + * @param fs Pointer to the file system. + * + * @return Number of free bytes. + */ +size_t zms_active_sector_free_space(struct zms_fs *fs); + +/** + * @brief Close the currently active sector and switch to the next one. + * + * @note The garbage collector is called on the new sector. + * + * @warning This routine is made available for specific use cases. + * It collides with ZMS's goal of avoiding any unnecessary flash erase operations. + * Using this routine extensively can result in premature failure of the flash device. + * + * @param fs Pointer to the file system. + * + * @return 0 on success. On error, returns negative value of error codes defined in `errno.h`. + */ +int zms_sector_use_next(struct zms_fs *fs); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_FS_ZMS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input.h index 32e9bf9f..e43f14c6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input.h @@ -124,9 +124,26 @@ struct input_callback { /** @ref device pointer or NULL. */ const struct device *dev; /** The callback function. */ - void (*callback)(struct input_event *evt); + void (*callback)(struct input_event *evt, void *user_data); + /** User data pointer. */ + void *user_data; }; +/** + * @brief Register a callback structure for input events with a custom name. + * + * Same as @ref INPUT_CALLBACK_DEFINE but allows specifying a custom name + * for the callback structure. Useful if multiple callbacks are used for the + * same callback function. + */ +#define INPUT_CALLBACK_DEFINE_NAMED(_dev, _callback, _user_data, name) \ + static const STRUCT_SECTION_ITERABLE(input_callback, \ + _input_callback__##name) = { \ + .dev = _dev, \ + .callback = _callback, \ + .user_data = _user_data, \ + } + /** * @brief Register a callback structure for input events. * @@ -136,13 +153,10 @@ struct input_callback { * * @param _dev @ref device pointer or NULL. * @param _callback The callback function. + * @param _user_data Pointer to user specified data. */ -#define INPUT_CALLBACK_DEFINE(_dev, _callback) \ - static const STRUCT_SECTION_ITERABLE(input_callback, \ - _input_callback__##_callback) = { \ - .dev = _dev, \ - .callback = _callback, \ - } +#define INPUT_CALLBACK_DEFINE(_dev, _callback, _user_data) \ + INPUT_CALLBACK_DEFINE_NAMED(_dev, _callback, _user_data, _callback) #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_kbd_matrix.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_kbd_matrix.h index bb164e6f..16391d8f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_kbd_matrix.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_kbd_matrix.h @@ -16,6 +16,8 @@ #include #include +#include +#include #include #include #include @@ -111,6 +113,7 @@ struct input_kbd_matrix_common_config { uint8_t row_size; uint8_t col_size; uint32_t poll_period_us; + uint32_t stable_poll_period_us; uint32_t poll_timeout_ms; uint32_t debounce_down_us; uint32_t debounce_up_us; @@ -190,6 +193,9 @@ struct input_kbd_matrix_common_config { .row_size = _row_size, \ .col_size = _col_size, \ .poll_period_us = DT_PROP(node_id, poll_period_ms) * USEC_PER_MSEC, \ + .stable_poll_period_us = DT_PROP_OR(node_id, stable_poll_period_ms, \ + DT_PROP(node_id, poll_period_ms)) * \ + USEC_PER_MSEC, \ .poll_timeout_ms = DT_PROP(node_id, poll_timeout_ms), \ .debounce_down_us = DT_PROP(node_id, debounce_down_ms) * USEC_PER_MSEC, \ .debounce_up_us = DT_PROP(node_id, debounce_up_ms) * USEC_PER_MSEC, \ @@ -248,6 +254,9 @@ struct input_kbd_matrix_common_data { uint8_t scan_cycles_idx; struct k_sem poll_lock; +#ifdef CONFIG_PM_DEVICE + atomic_t suspended; +#endif struct k_thread thread; @@ -305,6 +314,20 @@ void input_kbd_matrix_drive_column_hook(const struct device *dev, int col); */ int input_kbd_matrix_common_init(const struct device *dev); +#ifdef CONFIG_PM_DEVICE +/** + * @brief Common power management action handler. + * + * This handles PM actions for a keyboard matrix device, meant to be used as + * argument of @ref PM_DEVICE_DT_INST_DEFINE. + * + * @param dev Keyboard matrix device instance. + * @param action The power management action to handle. + */ +int input_kbd_matrix_pm_action(const struct device *dev, + enum pm_device_action action); +#endif + /** @} */ #endif /* ZEPHYR_INCLUDE_INPUT_KBD_MATRIX_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_touch.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_touch.h new file mode 100644 index 00000000..45010741 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/input/input_touch.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_INPUT_TOUCH_H_ +#define ZEPHYR_INCLUDE_INPUT_TOUCH_H_ + +/** + * @brief Touch Events API + * @defgroup touch_events Touchscreen Event Report API + * @since 3.7 + * @version 0.1.0 + * @ingroup io_interfaces + * @{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Common touchscreen config. + * + * This structure **must** be placed first in the driver's config structure. + * + * @param screen_width Horizontal resolution of touchscreen + * @param screen_height Vertical resolution of touchscreen + * @param inverted_x X axis is inverted + * @param inverted_y Y axis is inverted + * @param swapped_x_y X and Y axes are swapped + * + * see touchscreem-common.yaml for more details + */ +struct input_touchscreen_common_config { + uint32_t screen_width; + uint32_t screen_height; + bool inverted_x; + bool inverted_y; + bool swapped_x_y; +}; + +/** + * @brief Initialize common touchscreen config from devicetree + * + * @param node_id The devicetree node identifier. + */ +#define INPUT_TOUCH_DT_COMMON_CONFIG_INIT(node_id) \ + { \ + .screen_width = DT_PROP(node_id, screen_width), \ + .screen_height = DT_PROP(node_id, screen_height), \ + .inverted_x = DT_PROP(node_id, inverted_x), \ + .inverted_y = DT_PROP(node_id, inverted_y), \ + .swapped_x_y = DT_PROP(node_id, swapped_x_y) \ + } + +/** + * @brief Initialize common touchscreen config from devicetree instance. + * + * @param inst Instance. + */ +#define INPUT_TOUCH_DT_INST_COMMON_CONFIG_INIT(inst) \ + INPUT_TOUCH_DT_COMMON_CONFIG_INIT(DT_DRV_INST(inst)) + +/** + * @brief Validate the offset of the common config structure. + * + * @param config Name of the config structure. + */ +#define INPUT_TOUCH_STRUCT_CHECK(config) \ + BUILD_ASSERT(offsetof(config, common) == 0, \ + "struct input_touchscreen_common_config must be placed first"); + +/** + * @brief Common utility for reporting touchscreen position events. + * + * @param dev Touchscreen controller + * @param x X coordinate as reported by the controller + * @param y Y coordinate as reported by the controller + * @param timeout Timeout for reporting the event + */ +void input_touchscreen_report_pos(const struct device *dev, + uint32_t x, uint32_t y, + k_timeout_t timeout); + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* ZEPHYR_INCLUDE_INPUT_TOUCH_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/internal/syscall_handler.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/internal/syscall_handler.h index b48070fa..a1264d6c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/internal/syscall_handler.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/internal/syscall_handler.h @@ -62,7 +62,7 @@ static inline bool k_is_in_user_syscall(void) * calls from supervisor mode bypass everything directly to * the implementation function. */ - return !k_is_in_isr() && (_current->syscall_frame != NULL); + return !k_is_in_isr() && (arch_current_thread()->syscall_frame != NULL); } /** @@ -350,7 +350,7 @@ int k_usermode_string_copy(char *dst, const char *src, size_t maxlen); #define K_OOPS(expr) \ do { \ if (expr) { \ - arch_syscall_oops(_current->syscall_frame); \ + arch_syscall_oops(arch_current_thread()->syscall_frame); \ } \ } while (false) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/icmsg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/icmsg.h index 80e34120..6e4cbaea 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/icmsg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/icmsg.h @@ -51,8 +51,10 @@ struct icmsg_data_t { /* General */ const struct icmsg_config_t *cfg; +#ifdef CONFIG_MULTITHREADING struct k_work_delayable notify_work; struct k_work mbox_work; +#endif atomic_t state; }; @@ -64,7 +66,7 @@ struct icmsg_data_t { * completed. * This function is intended to be called late in the initialization process, * possibly from a thread which can be safely blocked while handshake with the - * remote instance is being pefromed. + * remote instance is being performed. * * @param[in] conf Structure containing configuration parameters for the icmsg * instance. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/ipc_static_vrings.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/ipc_static_vrings.h index d82144f4..2450e85d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/ipc_static_vrings.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/ipc_static_vrings.h @@ -9,7 +9,6 @@ #include #include -#include #ifdef __cplusplus extern "C" { @@ -55,9 +54,6 @@ struct ipc_static_vrings { /** SHM physmap. */ metal_phys_addr_t shm_physmap[1]; - /** SHM device. */ - struct metal_device shm_device; - /** SHM and addresses. */ uintptr_t status_reg_addr; @@ -77,7 +73,7 @@ struct ipc_static_vrings { size_t shm_size; /** SHM IO region. */ - struct metal_io_region *shm_io; + struct metal_io_region shm_io; /** VRINGs */ struct virtio_vring_info rvrings[VRING_COUNT]; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/pbuf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/pbuf.h index 0be5bd51..8783cdbb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/pbuf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/ipc/pbuf.h @@ -35,6 +35,13 @@ extern "C" { */ #define _PBUF_MIN_DATA_LEN ROUND_UP(PBUF_PACKET_LEN_SZ + 1 + _PBUF_IDX_SIZE, _PBUF_IDX_SIZE) +#if defined(CONFIG_ARCH_POSIX) +/* For the native simulated boards we need to modify some pointers at init */ +#define PBUF_MAYBE_CONST +#else +#define PBUF_MAYBE_CONST const +#endif + /** @brief Control block of packet buffer. * * The structure contains configuration data. @@ -87,9 +94,9 @@ struct pbuf_data { * written in a way to protect the data from being corrupted. */ struct pbuf { - const struct pbuf_cfg *const cfg; /* Configuration of the - * buffer. - */ + PBUF_MAYBE_CONST struct pbuf_cfg *const cfg; /* Configuration of the + * buffer. + */ struct pbuf_data data; /* Data used to read and write * to the buffer */ @@ -144,17 +151,32 @@ struct pbuf { "Misaligned memory."); \ BUILD_ASSERT(size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE + \ _PBUF_MIN_DATA_LEN), "Insufficient size."); \ - \ - static const struct pbuf_cfg cfg_##name = \ + static PBUF_MAYBE_CONST struct pbuf_cfg cfg_##name = \ PBUF_CFG_INIT(mem_addr, size, dcache_align); \ static struct pbuf name = { \ .cfg = &cfg_##name, \ } /** - * @brief Initialize the packet buffer. + * @brief Initialize the Tx packet buffer. + * + * This function initializes the Tx packet buffer based on provided configuration. + * If the configuration is incorrect, the function will return error. + * + * It is recommended to use PBUF_DEFINE macro for build time initialization. + * + * @param pb Pointer to the packed buffer containing + * configuration and data. Configuration has to be + * fixed before the initialization. + * @retval 0 on success. + * @retval -EINVAL when the input parameter is incorrect. + */ +int pbuf_tx_init(struct pbuf *pb); + +/** + * @brief Initialize the Rx packet buffer. * - * This function initializes the packet buffer based on provided configuration. + * This function initializes the Rx packet buffer. * If the configuration is incorrect, the function will return error. * * It is recommended to use PBUF_DEFINE macro for build time initialization. @@ -165,7 +187,7 @@ struct pbuf { * @retval 0 on success. * @retval -EINVAL when the input parameter is incorrect. */ -int pbuf_init(struct pbuf *pb); +int pbuf_rx_init(struct pbuf *pb); /** * @brief Write specified amount of data to the packet buffer. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/irq_multilevel.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/irq_multilevel.h index 3dbb58f3..dc18c304 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/irq_multilevel.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/irq_multilevel.h @@ -21,6 +21,64 @@ extern "C" { #endif #if defined(CONFIG_MULTI_LEVEL_INTERRUPTS) || defined(__DOXYGEN__) + +typedef union _z_irq { + /* Zephyr multilevel-encoded IRQ */ + uint32_t irq; + + /* Interrupt bits */ + struct { + /* First level interrupt bits */ + uint32_t l1: CONFIG_1ST_LEVEL_INTERRUPT_BITS; + /* Second level interrupt bits */ + uint32_t l2: CONFIG_2ND_LEVEL_INTERRUPT_BITS; + /* Third level interrupt bits */ + uint32_t l3: CONFIG_3RD_LEVEL_INTERRUPT_BITS; + } bits; + + /* Third level IRQ's interrupt controller */ + struct { + /* IRQ of the third level interrupt aggregator */ + uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS; + } l3_intc; + + /* Second level IRQ's interrupt controller */ + struct { + /* IRQ of the second level interrupt aggregator */ + uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS; + } l2_intc; +} _z_irq_t; + +BUILD_ASSERT(sizeof(_z_irq_t) == sizeof(uint32_t), "Size of `_z_irq_t` must equal to `uint32_t`"); + +static inline uint32_t _z_l1_irq(_z_irq_t irq) +{ + return irq.bits.l1; +} + +static inline uint32_t _z_l2_irq(_z_irq_t irq) +{ + return irq.bits.l2 - 1; +} + +static inline uint32_t _z_l3_irq(_z_irq_t irq) +{ + return irq.bits.l3 - 1; +} + +static inline unsigned int _z_irq_get_level(_z_irq_t z_irq) +{ + if (z_irq.bits.l3 != 0) { + return 3; + } + + if (z_irq.bits.l2 != 0) { + return 2; + } + + return 1; +} + /** * @brief Return IRQ level * This routine returns the interrupt level number of the provided interrupt. @@ -31,20 +89,11 @@ extern "C" { */ static inline unsigned int irq_get_level(unsigned int irq) { - const uint32_t mask2 = BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS) << - CONFIG_1ST_LEVEL_INTERRUPT_BITS; - const uint32_t mask3 = BIT_MASK(CONFIG_3RD_LEVEL_INTERRUPT_BITS) << - (CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS); - - if (IS_ENABLED(CONFIG_3RD_LEVEL_INTERRUPTS) && (irq & mask3) != 0) { - return 3; - } + _z_irq_t z_irq = { + .irq = irq, + }; - if (IS_ENABLED(CONFIG_2ND_LEVEL_INTERRUPTS) && (irq & mask2) != 0) { - return 2; - } - - return 1; + return _z_irq_get_level(z_irq); } /** @@ -59,12 +108,11 @@ static inline unsigned int irq_get_level(unsigned int irq) */ static inline unsigned int irq_from_level_2(unsigned int irq) { - if (IS_ENABLED(CONFIG_3RD_LEVEL_INTERRUPTS)) { - return ((irq >> CONFIG_1ST_LEVEL_INTERRUPT_BITS) & - BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS)) - 1; - } else { - return (irq >> CONFIG_1ST_LEVEL_INTERRUPT_BITS) - 1; - } + _z_irq_t z_irq = { + .irq = irq, + }; + + return _z_l2_irq(z_irq); } /** @@ -90,7 +138,15 @@ static inline unsigned int irq_from_level_2(unsigned int irq) */ static inline unsigned int irq_to_level_2(unsigned int irq) { - return IRQ_TO_L2(irq); + _z_irq_t z_irq = { + .bits = { + .l1 = 0, + .l2 = irq + 1, + .l3 = 0, + }, + }; + + return z_irq.irq; } /** @@ -105,7 +161,11 @@ static inline unsigned int irq_to_level_2(unsigned int irq) */ static inline unsigned int irq_parent_level_2(unsigned int irq) { - return irq & BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS); + _z_irq_t z_irq = { + .irq = irq, + }; + + return _z_l1_irq(z_irq); } /** @@ -121,7 +181,11 @@ static inline unsigned int irq_parent_level_2(unsigned int irq) */ static inline unsigned int irq_from_level_3(unsigned int irq) { - return (irq >> (CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS)) - 1; + _z_irq_t z_irq = { + .irq = irq, + }; + + return _z_l3_irq(z_irq); } /** @@ -148,7 +212,15 @@ static inline unsigned int irq_from_level_3(unsigned int irq) */ static inline unsigned int irq_to_level_3(unsigned int irq) { - return IRQ_TO_L3(irq); + _z_irq_t z_irq = { + .bits = { + .l1 = 0, + .l2 = 0, + .l3 = irq + 1, + }, + }; + + return z_irq.irq; } /** @@ -163,8 +235,11 @@ static inline unsigned int irq_to_level_3(unsigned int irq) */ static inline unsigned int irq_parent_level_3(unsigned int irq) { - return (irq >> CONFIG_1ST_LEVEL_INTERRUPT_BITS) & - BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS); + _z_irq_t z_irq = { + .irq = irq, + }; + + return _z_l2_irq(z_irq); } /** @@ -248,10 +323,43 @@ static inline unsigned int irq_get_intc_irq(unsigned int irq) { const unsigned int level = irq_get_level(irq); - __ASSERT_NO_MSG(level > 1 && level <= 3); + __ASSERT_NO_MSG(level <= 3); + _z_irq_t z_irq = { + .irq = irq, + }; + + if (level == 3) { + return z_irq.l3_intc.irq; + } else if (level == 2) { + return z_irq.l2_intc.irq; + } else { + return irq; + } +} + +/** + * @brief Increments the multilevel-encoded @a irq by @a val + * + * @param irq IRQ number in its zephyr format + * @param val Amount to increment + * + * @return @a irq incremented by @a val + */ +static inline unsigned int irq_increment(unsigned int irq, unsigned int val) +{ + _z_irq_t z_irq = { + .irq = irq, + }; + + if (z_irq.bits.l3 != 0) { + z_irq.bits.l3 += val; + } else if (z_irq.bits.l2 != 0) { + z_irq.bits.l2 += val; + } else { + z_irq.bits.l1 += val; + } - return irq & BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS + - (level == 3 ? CONFIG_2ND_LEVEL_INTERRUPT_BITS : 0)); + return z_irq.irq; } #endif /* CONFIG_MULTI_LEVEL_INTERRUPTS */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel.h index 5f4ee3ae..82d4b3a6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel.h @@ -122,6 +122,38 @@ typedef void (*k_thread_user_cb_t)(const struct k_thread *thread, */ void k_thread_foreach(k_thread_user_cb_t user_cb, void *user_data); +/** + * @brief Iterate over all the threads in running on specified cpu. + * + * This function is does otherwise the same thing as k_thread_foreach(), + * but it only loops through the threads running on specified cpu only. + * If CONFIG_SMP is not defined the implementation this is the same as + * k_thread_foreach(), with an assert cpu == 0. + * + * @param cpu The filtered cpu number + * @param user_cb Pointer to the user callback function. + * @param user_data Pointer to user data. + * + * @note @kconfig{CONFIG_THREAD_MONITOR} must be set for this function + * to be effective. + * @note This API uses @ref k_spin_lock to protect the _kernel.threads + * list which means creation of new threads and terminations of existing + * threads are blocked until this API returns. + */ +#ifdef CONFIG_SMP +void k_thread_foreach_filter_by_cpu(unsigned int cpu, + k_thread_user_cb_t user_cb, void *user_data); +#else +static inline +void k_thread_foreach_filter_by_cpu(unsigned int cpu, + k_thread_user_cb_t user_cb, void *user_data) +{ + __ASSERT(cpu == 0, "cpu filter out of bounds"); + ARG_UNUSED(cpu); + k_thread_foreach(user_cb, user_data); +} +#endif + /** * @brief Iterate over all the threads in the system without locking. * @@ -152,6 +184,51 @@ void k_thread_foreach(k_thread_user_cb_t user_cb, void *user_data); void k_thread_foreach_unlocked( k_thread_user_cb_t user_cb, void *user_data); +/** + * @brief Iterate over the threads in running on current cpu without locking. + * + * This function does otherwise the same thing as + * k_thread_foreach_unlocked(), but it only loops through the threads + * running on specified cpu. If CONFIG_SMP is not defined the + * implementation this is the same as k_thread_foreach_unlocked(), with an + * assert requiring cpu == 0. + * + * @param cpu The filtered cpu number + * @param user_cb Pointer to the user callback function. + * @param user_data Pointer to user data. + * + * @note @kconfig{CONFIG_THREAD_MONITOR} must be set for this function + * to be effective. + * @note This API uses @ref k_spin_lock only when accessing the _kernel.threads + * queue elements. It unlocks it during user callback function processing. + * If a new task is created when this @c foreach function is in progress, + * the added new task would not be included in the enumeration. + * If a task is aborted during this enumeration, there would be a race here + * and there is a possibility that this aborted task would be included in the + * enumeration. + * @note If the task is aborted and the memory occupied by its @c k_thread + * structure is reused when this @c k_thread_foreach_unlocked is in progress + * it might even lead to the system behave unstable. + * This function may never return, as it would follow some @c next task + * pointers treating given pointer as a pointer to the k_thread structure + * while it is something different right now. + * Do not reuse the memory that was occupied by k_thread structure of aborted + * task if it was aborted after this function was called in any context. + */ +#ifdef CONFIG_SMP +void k_thread_foreach_unlocked_filter_by_cpu(unsigned int cpu, + k_thread_user_cb_t user_cb, void *user_data); +#else +static inline +void k_thread_foreach_unlocked_filter_by_cpu(unsigned int cpu, + k_thread_user_cb_t user_cb, void *user_data) +{ + __ASSERT(cpu == 0, "cpu filter out of bounds"); + ARG_UNUSED(cpu); + k_thread_foreach_unlocked(user_cb, user_data); +} +#endif + /** @} */ /** @@ -173,6 +250,7 @@ void k_thread_foreach_unlocked( * */ #define K_ESSENTIAL (BIT(0)) +#define K_FP_IDX 1 /** * @brief FPU registers are managed by context switch * @@ -182,7 +260,6 @@ void k_thread_foreach_unlocked( * and restore the contents of these registers when scheduling the thread. * No effect if @kconfig{CONFIG_FPU_SHARING} is not enabled. */ -#define K_FP_IDX 1 #define K_FP_REGS (BIT(K_FP_IDX)) /** @@ -588,7 +665,7 @@ static inline k_tid_t k_current_get(void) #ifdef CONFIG_CURRENT_THREAD_USE_TLS /* Thread-local cache of current thread ID, set in z_thread_entry() */ - extern __thread k_tid_t z_tls_current; + extern Z_THREAD_LOCAL k_tid_t z_tls_current; return z_tls_current; #else @@ -617,18 +694,6 @@ static inline k_tid_t k_current_get(void) */ __syscall void k_thread_abort(k_tid_t thread); - -/** - * @brief Start an inactive thread - * - * If a thread was created with K_FOREVER in the delay parameter, it will - * not be added to the scheduling queue until this function is called - * on it. - * - * @param thread thread to start - */ -__syscall void k_thread_start(k_tid_t thread); - k_ticks_t z_timeout_expires(const struct _timeout *timeout); k_ticks_t z_timeout_remaining(const struct _timeout *timeout); @@ -827,12 +892,12 @@ __syscall int k_thread_priority_get(k_tid_t thread); * Rescheduling can occur immediately depending on the priority @a thread is * set to: * - * - If its priority is raised above the priority of the caller of this - * function, and the caller is preemptible, @a thread will be scheduled in. + * - If its priority is raised above the priority of a currently scheduled + * preemptible thread, @a thread will be scheduled in. * - * - If the caller operates on itself, it lowers its priority below that of - * other threads in the system, and the caller is preemptible, the thread of - * highest priority will be scheduled in. + * - If the caller lowers the priority of a currently scheduled preemptible + * thread below that of other threads in the system, the thread of the highest + * priority will be scheduled in. * * Priority can be assigned in the range of -CONFIG_NUM_COOP_PRIORITIES to * CONFIG_NUM_PREEMPT_PRIORITIES-1, where -CONFIG_NUM_COOP_PRIORITIES is the @@ -987,6 +1052,24 @@ __syscall void k_thread_suspend(k_tid_t thread); */ __syscall void k_thread_resume(k_tid_t thread); +/** + * @brief Start an inactive thread + * + * If a thread was created with K_FOREVER in the delay parameter, it will + * not be added to the scheduling queue until this function is called + * on it. + * + * @note This is a legacy API for compatibility. Modern Zephyr + * threads are initialized in the "suspended" state and no not need + * special handling for "start". + * + * @param thread thread to start + */ +static inline void k_thread_start(k_tid_t thread) +{ + k_thread_resume(thread); +} + /** * @brief Set time-slicing period and scope. * @@ -3244,12 +3327,12 @@ static inline unsigned int z_impl_k_sem_count_get(struct k_sem *sem) * @param initial_count Initial semaphore count. * @param count_limit Maximum permitted semaphore count. */ -#define K_SEM_DEFINE(name, initial_count, count_limit) \ - STRUCT_SECTION_ITERABLE(k_sem, name) = \ - Z_SEM_INITIALIZER(name, initial_count, count_limit); \ - BUILD_ASSERT(((count_limit) != 0) && \ - ((initial_count) <= (count_limit)) && \ - ((count_limit) <= K_SEM_MAX_LIMIT)); +#define K_SEM_DEFINE(name, initial_count, count_limit) \ + STRUCT_SECTION_ITERABLE(k_sem, name) = \ + Z_SEM_INITIALIZER(name, initial_count, count_limit); \ + BUILD_ASSERT(((count_limit) != 0) && \ + (((initial_count) < (count_limit)) || ((initial_count) == (count_limit))) && \ + ((count_limit) <= K_SEM_MAX_LIMIT)); /** @} */ @@ -3523,6 +3606,22 @@ int k_work_queue_drain(struct k_work_q *queue, bool plug); */ int k_work_queue_unplug(struct k_work_q *queue); +/** @brief Stop a work queue. + * + * Stops the work queue thread and ensures that no further work will be processed. + * This call is blocking and guarantees that the work queue thread has terminated + * cleanly if successful, no work will be processed past this point. + * + * @param queue Pointer to the queue structure. + * @param timeout Maximum time to wait for the work queue to stop. + * + * @retval 0 if the work queue was stopped + * @retval -EALREADY if the work queue was not started (or already stopped) + * @retval -EBUSY if the work queue is actively processing work items + * @retval -ETIMEDOUT if the work queue did not stop within the stipulated timeout + */ +int k_work_queue_stop(struct k_work_q *queue, k_timeout_t timeout); + /** @brief Initialize a delayable work structure. * * This must be invoked before scheduling a delayable work structure for the @@ -3832,6 +3931,8 @@ enum { K_WORK_QUEUE_DRAIN = BIT(K_WORK_QUEUE_DRAIN_BIT), K_WORK_QUEUE_PLUGGED_BIT = 3, K_WORK_QUEUE_PLUGGED = BIT(K_WORK_QUEUE_PLUGGED_BIT), + K_WORK_QUEUE_STOP_BIT = 4, + K_WORK_QUEUE_STOP = BIT(K_WORK_QUEUE_STOP_BIT), /* Static work queue flags */ K_WORK_QUEUE_NO_YIELD_BIT = 8, @@ -4607,7 +4708,7 @@ __syscall int k_msgq_put(struct k_msgq *msgq, const void *data, k_timeout_t time * K_FOREVER. * * @retval 0 Message received. - * @retval -ENOMSG Returned without waiting. + * @retval -ENOMSG Returned without waiting or queue purged. * @retval -EAGAIN Waiting period timed out. */ __syscall int k_msgq_get(struct k_msgq *msgq, void *data, k_timeout_t timeout); @@ -6116,6 +6217,15 @@ int k_thread_runtime_stats_get(k_tid_t thread, */ int k_thread_runtime_stats_all_get(k_thread_runtime_stats_t *stats); +/** + * @brief Get the runtime statistics of all threads on specified cpu + * + * @param cpu The cpu number + * @param stats Pointer to struct to copy statistics into. + * @return -EINVAL if null pointers, otherwise 0 + */ +int k_thread_runtime_stats_cpu_get(int cpu, k_thread_runtime_stats_t *stats); + /** * @brief Enable gathering of runtime statistics for specified thread * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm.h index 88ad40af..79c3dc48 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm.h @@ -114,6 +114,25 @@ extern "C" { */ #define K_MEM_MAP_LOCK BIT(17) +/** + * Region will be unpaged i.e. not mapped into memory + * + * This is meant to be used by kernel code and not by application code. + * + * Corresponding memory address range will be set so no actual memory will + * be allocated initially. Allocation will happen through demand paging when + * addresses in that range are accessed. This is incompatible with + * K_MEM_MAP_LOCK. + * + * When this flag is specified, the phys argument to arch_mem_map() + * is interpreted as a backing store location value not a physical address. + * This is very similar to arch_mem_page_out() in that regard. + * Two special location values are defined: ARCH_UNPAGED_ANON_ZERO and + * ARCH_UNPAGED_ANON_UNINIT. Those are to be used with anonymous memory + * mappings for zeroed and uninitialized pages respectively. + */ +#define K_MEM_MAP_UNPAGED BIT(18) + /** @} */ /** @@ -173,6 +192,54 @@ static inline void *k_mem_map(size_t size, uint32_t flags) return k_mem_map_phys_guard((uintptr_t)NULL, size, flags, true); } +#ifdef CONFIG_DEMAND_MAPPING +/** + * Create an unpaged mapping + * + * This maps backing-store "location" tokens into Zephyr's address space. + * Corresponding memory address range will be set so no actual memory will + * be allocated initially. Allocation will happen through demand paging when + * addresses in the mapped range are accessed. + * + * The kernel will choose a base virtual address and return it to the caller. + * The memory access permissions for all contexts will be set per the + * provided flags argument. + * + * If user thread access control needs to be managed in any way, do not enable + * K_MEM_PERM_USER flags here; instead manage the region's permissions + * with memory domain APIs after the mapping has been established. Setting + * K_MEM_PERM_USER here will allow all user threads to access this memory + * which is usually undesirable. + * + * This is incompatible with K_MEM_MAP_LOCK. + * + * The provided backing-store "location" token must be linearly incrementable + * by a page size across the entire mapping. + * + * Allocated pages will have write-back cache settings. + * + * The returned virtual memory pointer will be page-aligned. The size + * parameter, and any base address for re-mapping purposes must be page- + * aligned. + * + * Note that the allocation includes two guard pages immediately before + * and after the requested region. The total size of the allocation will be + * the requested size plus the size of these two guard pages. + * + * @param location Backing store initial location token + * @param size Size of the memory mapping. This must be page-aligned. + * @param flags K_MEM_PERM_*, K_MEM_MAP_* control flags. + * @return The mapping location, or NULL if insufficient virtual address + * space to establish the mapping, or insufficient memory for paging + * structures. + */ +static inline void *k_mem_map_unpaged(uintptr_t location, size_t size, uint32_t flags) +{ + flags |= K_MEM_MAP_UNPAGED; + return k_mem_map_phys_guard(location, size, flags, false); +} +#endif + /** * Un-map mapped memory * @@ -191,6 +258,23 @@ static inline void k_mem_unmap(void *addr, size_t size) k_mem_unmap_phys_guard(addr, size, true); } +/** + * Modify memory mapping attribute flags + * + * This updates caching, access and control flags for the provided + * page-aligned memory region. + * + * Calling this function on a region which was not mapped to begin with is + * undefined behavior. However system memory implicitly mapped at boot time + * is supported. + * + * @param addr Page-aligned memory region base virtual address + * @param size Page-aligned memory region size + * @param flags K_MEM_PERM_*, K_MEM_MAP_* control flags. + * @return 0 for success, negative error code otherwise. + */ +int k_mem_update_flags(void *addr, size_t size, uint32_t flags); + /** * Given an arbitrary region, provide a aligned region that covers it * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm/demand_paging.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm/demand_paging.h index ab2ca7d0..10a2e791 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm/demand_paging.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/mm/demand_paging.h @@ -217,6 +217,8 @@ __syscall void k_mem_paging_histogram_backing_store_page_out_get( * @{ */ +#if defined(CONFIG_EVICTION_TRACKING) || defined(__DOXYGEN__) + /** * Submit a page frame for eviction candidate tracking * @@ -261,6 +263,25 @@ void k_mem_paging_eviction_remove(struct k_mem_page_frame *pf); */ void k_mem_paging_eviction_accessed(uintptr_t phys); +#else /* CONFIG_EVICTION_TRACKING || __DOXYGEN__ */ + +static inline void k_mem_paging_eviction_add(struct k_mem_page_frame *pf) +{ + ARG_UNUSED(pf); +} + +static inline void k_mem_paging_eviction_remove(struct k_mem_page_frame *pf) +{ + ARG_UNUSED(pf); +} + +static inline void k_mem_paging_eviction_accessed(uintptr_t phys) +{ + ARG_UNUSED(phys); +} + +#endif /* CONFIG_EVICTION_TRACKING || __DOXYGEN__ */ + /** * Select a page frame for eviction * @@ -349,6 +370,22 @@ int k_mem_paging_backing_store_location_get(struct k_mem_page_frame *pf, */ void k_mem_paging_backing_store_location_free(uintptr_t location); +/** + * Obtain persistent location token for on-demand content + * + * Unlike k_mem_paging_backing_store_location_get() this does not allocate + * any backing store space. Instead, it returns a location token corresponding + * to some fixed storage content to be paged in on demand. This is expected + * to be used in conjonction with CONFIG_LINKER_USE_ONDEMAND_SECTION and the + * K_MEM_MAP_UNPAGED flag to create demand mappings at boot time. This may + * also be used e.g. to implement file-based mmap(). + * + * @param addr Virtual address to obtain a location token for + * @param [out] location storage location token + * @return 0 for success or negative error code + */ +int k_mem_paging_backing_store_location_query(void *addr, uintptr_t *location); + /** * Copy a data page from K_MEM_SCRATCH_PAGE to the specified location * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/thread_stack.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/thread_stack.h index a8151cce..2989624e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/thread_stack.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel/thread_stack.h @@ -293,7 +293,6 @@ static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) #define K_THREAD_STACK_LEN K_KERNEL_STACK_LEN #define K_THREAD_STACK_DEFINE K_KERNEL_STACK_DEFINE #define K_THREAD_STACK_ARRAY_DEFINE K_KERNEL_STACK_ARRAY_DEFINE -#define K_THREAD_STACK_MEMBER K_KERNEL_STACK_MEMBER #define K_THREAD_STACK_BUFFER K_KERNEL_STACK_BUFFER #define K_THREAD_STACK_DECLARE K_KERNEL_STACK_DECLARE #define K_THREAD_STACK_ARRAY_DECLARE K_KERNEL_STACK_ARRAY_DECLARE @@ -613,27 +612,6 @@ static inline char *K_KERNEL_STACK_BUFFER(k_thread_stack_t *sym) K_THREAD_STACK_ARRAY_DEFINE(sym, nmemb, size) #endif /* CONFIG_LINKER_USE_PINNED_SECTION */ -/** - * @brief Define an embedded stack memory region - * - * Used for stacks embedded within other data structures. Use is highly - * discouraged but in some cases necessary. For memory protection scenarios, - * it is very important that any RAM preceding this member not be writable - * by threads else a stack overflow will lead to silent corruption. In other - * words, the containing data structure should live in RAM owned by the kernel. - * - * A user thread can only be started with a stack defined in this way if - * the thread starting it is in supervisor mode. - * - * @deprecated This is now deprecated, as stacks defined in this way are not - * usable from user mode. Use K_KERNEL_STACK_MEMBER. - * - * @param sym Thread stack symbol name - * @param size Size of the stack memory region - */ -#define K_THREAD_STACK_MEMBER(sym, size) __DEPRECATED_MACRO \ - Z_THREAD_STACK_DEFINE_IN(sym, size,) - /** @} */ /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel_structs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel_structs.h index cf7daff9..3c1df990 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel_structs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/kernel_structs.h @@ -54,9 +54,6 @@ extern "C" { /* Thread is waiting on an object */ #define _THREAD_PENDING (BIT(1)) -/* Thread has not yet started */ -#define _THREAD_PRESTART (BIT(2)) - /* Thread has terminated */ #define _THREAD_DEAD (BIT(3)) @@ -171,7 +168,7 @@ struct _cpu { #endif #ifdef CONFIG_SMP - /* True when _current is allowed to context switch */ + /* True when arch_current_thread() is allowed to context switch */ uint8_t swap_ok; #endif @@ -260,12 +257,12 @@ bool z_smp_cpu_mobile(void); #define _current_cpu ({ __ASSERT_NO_MSG(!z_smp_cpu_mobile()); \ arch_curr_cpu(); }) -#define _current k_sched_current_thread_query() #else #define _current_cpu (&_kernel.cpus[0]) -#define _current _kernel.cpus[0].current -#endif +#endif /* CONFIG_SMP */ + +#define _current arch_current_thread() __DEPRECATED_MACRO /* kernel wait queue record */ #ifdef CONFIG_WAITQ_SCALABLE diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/devicetree_regions.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/devicetree_regions.h index e1d91627..9a0139df 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/devicetree_regions.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/devicetree_regions.h @@ -82,6 +82,66 @@ #define LINKER_DT_NODE_REGION_NAME(node_id) \ STRINGIFY(LINKER_DT_NODE_REGION_NAME_TOKEN(node_id)) +#define _DT_MEMORY_REGION_FLAGS_TOKEN(n) DT_STRING_TOKEN(n, zephyr_memory_region_flags) +#define _DT_MEMORY_REGION_FLAGS_UNQUOTED(n) DT_STRING_UNQUOTED(n, zephyr_memory_region_flags) + +#define _LINKER_L_PAREN ( +#define _LINKER_R_PAREN ) +#define _LINKER_ENCLOSE_PAREN(x) _LINKER_L_PAREN x _LINKER_R_PAREN + +#define _LINKER_IS_EMPTY_TOKEN_ 1 +#define _LINKER_IS_EMPTY_TOKEN_EXPAND(x) _LINKER_IS_EMPTY_TOKEN_##x +#define _LINKER_IS_EMPTY_TOKEN(x) _LINKER_IS_EMPTY_TOKEN_EXPAND(x) + +/** + * @brief Get the linker memory-region flags with parentheses. + * + * This attempts to return the zephyr,memory-region-flags property + * with parentheses. + * Return empty string if not set the property. + * + * Example devicetree fragment: + * + * @code{.dts} + * / { + * soc { + * rx: memory@2000000 { + * zephyr,memory-region = "READ_EXEC"; + * zephyr,memory-region-flags = "rx"; + * }; + * rx_not_w: memory@2001000 { + * zephyr,memory-region = "READ_EXEC_NOT_WRITE"; + * zephyr,memory-region-flags = "rx!w"; + * }; + * no_flags: memory@2001000 { + * zephyr,memory-region = "NO_FLAGS"; + * }; + * }; + * }; + * @endcode + * + * Example usage: + * + * @code{.c} + * LINKER_DT_NODE_REGION_FLAGS(DT_NODELABEL(rx)) // (rx) + * LINKER_DT_NODE_REGION_FLAGS(DT_NODELABEL(rx_not_w)) // (rx!w) + * LINKER_DT_NODE_REGION_FLAGS(DT_NODELABEL(no_flags)) // [flags will not be specified] + * @endcode + * + * @param node_id node identifier + * @return the value of the memory region flag specified in the device tree + * enclosed in parentheses. + */ + +#define LINKER_DT_NODE_REGION_FLAGS(node_id) \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_region_flags), \ + (COND_CODE_1(_LINKER_IS_EMPTY_TOKEN(_DT_MEMORY_REGION_FLAGS_TOKEN(node_id)), \ + (), \ + (_LINKER_ENCLOSE_PAREN( \ + _DT_MEMORY_REGION_FLAGS_UNQUOTED(node_id)) \ + ))), \ + (_LINKER_ENCLOSE_PAREN(rw))) + /** @cond INTERNAL_HIDDEN */ #define _DT_COMPATIBLE zephyr_memory_region @@ -102,6 +162,7 @@ * compatible = "zephyr,memory-region", "mmio-sram"; * reg = < 0x20010000 0x1000 >; * zephyr,memory-region = "FOOBAR"; + * zephyr,memory-region-flags = "rw"; * }; * @endcode * @@ -114,10 +175,11 @@ * @param node_id devicetree node identifier * @param attr region attributes */ -#define _REGION_DECLARE(node_id) \ - LINKER_DT_NODE_REGION_NAME_TOKEN(node_id) : \ - ORIGIN = DT_REG_ADDR(node_id), \ - LENGTH = DT_REG_SIZE(node_id) +#define _REGION_DECLARE(node_id) \ + LINKER_DT_NODE_REGION_NAME_TOKEN(node_id) \ + LINKER_DT_NODE_REGION_FLAGS(node_id) \ + : ORIGIN = DT_REG_ADDR(node_id), \ + LENGTH = DT_REG_SIZE(node_id) /** * @brief Declare a memory section from the device tree nodes with diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-defs.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-defs.h index d860222f..9c795ae7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-defs.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-defs.h @@ -32,6 +32,7 @@ */ #ifdef ZTEST_UNITTEST #define DT_NODE_HAS_STATUS(node, status) 0 +#define DT_NODE_HAS_STATUS_OKAY(node) 0 #else #include #endif @@ -159,7 +160,7 @@ extern char __gcov_bss_size[]; /* end address of image, used by newlib for the heap */ extern char _end[]; -#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ccm), okay)) +#if (DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm))) extern char __ccm_data_rom_start[]; extern char __ccm_start[]; extern char __ccm_data_start[]; @@ -171,14 +172,14 @@ extern char __ccm_noinit_end[]; extern char __ccm_end[]; #endif -#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)) +#if (DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm))) extern char __itcm_start[]; extern char __itcm_end[]; extern char __itcm_size[]; extern char __itcm_load_start[]; #endif -#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)) +#if (DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm))) extern char __dtcm_data_start[]; extern char __dtcm_data_end[]; extern char __dtcm_bss_start[]; @@ -190,7 +191,7 @@ extern char __dtcm_start[]; extern char __dtcm_end[]; #endif -#if (DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_ocm), okay)) +#if (DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ocm))) extern char __ocm_data_start[]; extern char __ocm_data_end[]; extern char __ocm_bss_start[]; @@ -230,6 +231,7 @@ extern char _nocache_ram_size[]; * section, stored in RAM instead of FLASH. */ #ifdef CONFIG_ARCH_HAS_RAMFUNC_SUPPORT +extern char __ramfunc_region_start[]; extern char __ramfunc_start[]; extern char __ramfunc_end[]; extern char __ramfunc_size[]; @@ -337,6 +339,24 @@ static inline bool lnkr_is_region_pinned(uint8_t *addr, size_t sz) #endif /* CONFIG_LINKER_USE_PINNED_SECTION */ +#ifdef CONFIG_LINKER_USE_ONDEMAND_SECTION +/* lnkr_ondemand_start[] and lnkr_ondemand_end[] must encapsulate + * all the on-demand sections as these are used by + * the MMU code to mark the virtual pages with the appropriate backing store + * location token to have them be paged in on demand. + */ +extern char lnkr_ondemand_start[]; +extern char lnkr_ondemand_end[]; +extern char lnkr_ondemand_load_start[]; + +extern char lnkr_ondemand_text_start[]; +extern char lnkr_ondemand_text_end[]; +extern char lnkr_ondemand_text_size[]; +extern char lnkr_ondemand_rodata_start[]; +extern char lnkr_ondemand_rodata_end[]; +extern char lnkr_ondemand_rodata_size[]; + +#endif /* CONFIG_LINKER_USE_ONDEMAND_SECTION */ #endif /* ! _ASMLANGUAGE */ #endif /* ZEPHYR_INCLUDE_LINKER_LINKER_DEFS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-devnull.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-devnull.h index d5455dd6..12dd7b7b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-devnull.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/linker-devnull.h @@ -11,6 +11,7 @@ */ #ifndef ZEPHYR_INCLUDE_LINKER_LINKER_DEVNULL_H_ +#define ZEPHYR_INCLUDE_LINKER_LINKER_DEVNULL_H_ #if defined(CONFIG_LINKER_DEVNULL_MEMORY) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/section_tags.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/section_tags.h index 6c7c1bdd..560d7611 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/section_tags.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/section_tags.h @@ -13,6 +13,8 @@ #if !defined(_ASMLANGUAGE) +#include + #define __noinit __in_section_unique(_NOINIT_SECTION_NAME) #define __noinit_named(name) __in_section_unique_named(_NOINIT_SECTION_NAME, name) #define __irq_vector_table Z_GENERIC_SECTION(_IRQ_VECTOR_TABLE_SECTION_NAME) @@ -42,6 +44,7 @@ #define __imx_boot_data_section Z_GENERIC_SECTION(_IMX_BOOT_DATA_SECTION_NAME) #define __imx_boot_ivt_section Z_GENERIC_SECTION(_IMX_BOOT_IVT_SECTION_NAME) #define __imx_boot_dcd_section Z_GENERIC_SECTION(_IMX_BOOT_DCD_SECTION_NAME) +#define __imx_boot_container_section Z_GENERIC_SECTION(_IMX_BOOT_CONTAINER_SECTION_NAME) #define __stm32_sdram1_section Z_GENERIC_SECTION(_STM32_SDRAM1_SECTION_NAME) #define __stm32_sdram2_section Z_GENERIC_SECTION(_STM32_SDRAM2_SECTION_NAME) #define __stm32_backup_sram_section Z_GENERIC_SECTION(_STM32_BACKUP_SRAM_SECTION_NAME) @@ -97,6 +100,14 @@ #define __pinned_noinit __noinit #endif /* CONFIG_LINKER_USE_PINNED_SECTION */ +#if defined(CONFIG_LINKER_USE_ONDEMAND_SECTION) +#define __ondemand_func Z_GENERIC_DOT_SECTION(ONDEMAND_TEXT_SECTION_NAME) +#define __ondemand_rodata Z_GENERIC_DOT_SECTION(ONDEMAND_RODATA_SECTION_NAME) +#else +#define __ondemand_func +#define __ondemand_rodata +#endif /* CONFIG_LINKER_USE_ONDEMAND_SECTION */ + #if defined(CONFIG_LINKER_USE_PINNED_SECTION) #define __isr __pinned_func #else diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/sections.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/sections.h index 14aa4c29..36159427 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/sections.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/linker/sections.h @@ -67,6 +67,7 @@ #define _IMX_BOOT_DATA_SECTION_NAME .boot_hdr.data #define _IMX_BOOT_IVT_SECTION_NAME .boot_hdr.ivt #define _IMX_BOOT_DCD_SECTION_NAME .boot_hdr.dcd_data +#define _IMX_BOOT_CONTAINER_SECTION_NAME .boot_hdr.container #define _STM32_SDRAM1_SECTION_NAME .stm32_sdram1 #define _STM32_SDRAM2_SECTION_NAME .stm32_sdram2 @@ -100,6 +101,11 @@ #define PINNED_NOINIT_SECTION_NAME pinned_noinit #endif +#if defined(CONFIG_LINKER_USE_ONDEMAND_SECTION) +#define ONDEMAND_TEXT_SECTION_NAME ondemand_text +#define ONDEMAND_RODATA_SECTION_NAME ondemand_rodata +#endif + /* Short section references for use in ASM files */ #if defined(_ASMLANGUAGE) /* Various text section names */ @@ -139,6 +145,14 @@ #define PINNED_NOINIT NOINIT #endif /* CONFIG_LINKER_USE_PINNED_SECTION */ +#if defined(CONFIG_LINKER_USE_ONDEMAND_SECTION) +#define ONDEMAND_TEXT ONDEMAND_TEXT_SECTION_NAME +#define ONDEMAND_RODATA ONDEMAND_RODATA_SECTION_NAME +#else +#define ONDEMAND_TEXT TEXT +#define ONDEMAND_RODATA RODATA +#endif /* CONFIG_LINKER_USE_ONDEMAND_SECTION */ + #endif /* _ASMLANGUAGE */ #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/buf_loader.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/buf_loader.h index 5079c011..9d5dd1c9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/buf_loader.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/buf_loader.h @@ -47,16 +47,19 @@ void *llext_buf_peek(struct llext_loader *ldr, size_t pos); * @param _buf Buffer containing the ELF binary * @param _buf_len Buffer length in bytes */ -#define LLEXT_BUF_LOADER(_buf, _buf_len) \ - { \ - .loader = { \ - .read = llext_buf_read, \ - .seek = llext_buf_seek, \ - .peek = llext_buf_peek, \ - }, \ - .buf = (_buf), \ - .len = (_buf_len), \ - .pos = 0 \ +#define LLEXT_BUF_LOADER(_buf, _buf_len) \ + { \ + .loader = \ + { \ + .prepare = NULL, \ + .read = llext_buf_read, \ + .seek = llext_buf_seek, \ + .peek = llext_buf_peek, \ + .finalize = NULL, \ + }, \ + .buf = (_buf), \ + .len = (_buf_len), \ + .pos = 0, \ } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/elf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/elf.h index 7230d131..48a611a3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/elf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/elf.h @@ -393,54 +393,6 @@ struct elf64_rela { */ #define ELF64_R_TYPE(i) ((i) & 0xffffffff) -/** - * Relocation names (should be moved to arch-specific files) - * @cond ignore - */ -#define R_386_NONE 0 -#define R_386_32 1 -#define R_386_PC32 2 -#define R_386_GOT32 3 -#define R_386_PLT32 4 -#define R_386_COPY 5 -#define R_386_GLOB_DAT 6 -#define R_386_JMP_SLOT 7 -#define R_386_RELATIVE 8 -#define R_386_GOTOFF 9 - -#define R_ARM_NONE 0 -#define R_ARM_PC24 1 -#define R_ARM_ABS32 2 -#define R_ARM_REL32 3 -#define R_ARM_COPY 20 -#define R_ARM_GLOB_DAT 21 -#define R_ARM_JUMP_SLOT 22 -#define R_ARM_RELATIVE 23 -#define R_ARM_CALL 28 -#define R_ARM_JUMP24 29 -#define R_ARM_TARGET1 38 -#define R_ARM_V4BX 40 -#define R_ARM_PREL31 42 -#define R_ARM_MOVW_ABS_NC 43 -#define R_ARM_MOVT_ABS 44 -#define R_ARM_MOVW_PREL_NC 45 -#define R_ARM_MOVT_PREL 46 -#define R_ARM_ALU_PC_G0_NC 57 -#define R_ARM_ALU_PC_G1_NC 59 -#define R_ARM_LDR_PC_G2 63 - -#define R_ARM_THM_CALL 10 -#define R_ARM_THM_JUMP24 30 -#define R_ARM_THM_MOVW_ABS_NC 47 -#define R_ARM_THM_MOVT_ABS 48 -#define R_ARM_THM_MOVW_PREL_NC 49 -#define R_ARM_THM_MOVT_PREL 50 - -#define R_XTENSA_NONE 0 -#define R_XTENSA_32 1 -#define R_XTENSA_SLOT0_OP 20 -/** @endcond */ - /** * Dynamic features currently not used by LLEXT * @cond ignore diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/fs_loader.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/fs_loader.h new file mode 100644 index 00000000..9cb41851 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/fs_loader.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 BayLibre SAS + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_LLEXT_FS_LOADER_H +#define ZEPHYR_LLEXT_FS_LOADER_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * @brief LLEXT filesystem loader implementation. + * + * @addtogroup llext_loader_apis + * @{ + */ + +/** + * @brief Implementation of @ref llext_loader that reads from a filesystem. + */ +struct llext_fs_loader { + /** Extension loader */ + struct llext_loader loader; + + /** @cond ignore */ + bool is_open; + const char *name; + struct fs_file_t file; + /** @endcond */ +}; + +/** @cond ignore */ +int llext_fs_prepare(struct llext_loader *ldr); +int llext_fs_read(struct llext_loader *ldr, void *buf, size_t len); +int llext_fs_seek(struct llext_loader *ldr, size_t pos); +void llext_fs_finalize(struct llext_loader *ldr); +/** @endcond */ + +/** + * @brief Initializer for an llext_fs_loader structure + * + * @param _filename Absolute path to the extension file. + */ +#define LLEXT_FS_LOADER(_filename) \ + { \ + .loader = \ + { \ + .prepare = llext_fs_prepare, \ + .read = llext_fs_read, \ + .seek = llext_fs_seek, \ + .peek = NULL, \ + .finalize = llext_fs_finalize, \ + }, \ + .is_open = false, \ + .name = (_filename), \ + } + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_LLEXT_FS_LOADER_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext.h index 441aab0e..5bd16ea3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext.h @@ -65,6 +65,9 @@ enum llext_mem { struct llext_loader; /** @endcond */ +/* Maximim number of dependency LLEXTs */ +#define LLEXT_MAX_DEPENDENCIES 8 + /** * @brief Structure describing a linkable loadable extension * @@ -114,8 +117,27 @@ struct llext { /** Extension use counter, prevents unloading while in use */ unsigned int use_count; + + /** Array of extensions, whose symbols this extension accesses */ + struct llext *dependency[LLEXT_MAX_DEPENDENCIES]; + + /** @cond ignore */ + unsigned int sect_cnt; + elf_shdr_t *sect_hdrs; + bool sect_hdrs_on_heap; + /** @endcond */ }; +static inline const elf_shdr_t *llext_section_headers(const struct llext *ext) +{ + return ext->sect_hdrs; +} + +static inline unsigned int llext_section_count(const struct llext *ext) +{ + return ext->sect_cnt; +} + /** * @brief Advanced llext_load parameters * @@ -126,9 +148,18 @@ struct llext_load_param { bool relocate_local; /** * Use the virtual symbol addresses from the ELF, not addresses within - * the memory buffer, when calculating relocation targets. + * the memory buffer, when calculating relocation targets. It also + * means, that the application will take care to place the extension at + * those pre-defined addresses, so the LLEXT core doesn't have to do any + * allocation and copying internally. */ bool pre_located; + /** + * Extensions can implement custom ELF sections to be loaded in specific + * memory regions, detached from other sections of compatible types. + * This optional callback checks whether a section should be detached. + */ + bool (*section_detached)(const elf_shdr_t *shdr); }; /** Default initializer for @ref llext_load_param */ @@ -171,7 +202,7 @@ int llext_iterate(int (*fn)(struct llext *ext, void *arg), void *arg); * @retval -ENOTSUP Unsupported ELF features */ int llext_load(struct llext_loader *loader, const char *name, struct llext **ext, - struct llext_load_param *ldr_parm); + const struct llext_load_param *ldr_parm); /** * @brief Unload an extension @@ -287,7 +318,7 @@ int llext_call_fn(struct llext *ext, const char *sym_name); * @param[in] domain Memory domain to add partitions to * * @returns 0 on success, or a negative error code. - * @retval -ENOSYS @kconfig{CONFIG_USERSPACE} is not enabled or supported + * @retval -ENOSYS Option @kconfig{CONFIG_USERSPACE} is not enabled or supported */ int llext_add_domain(struct llext *ext, struct k_mem_domain *domain); @@ -324,16 +355,47 @@ int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, ssize_t llext_find_section(struct llext_loader *loader, const char *search_name); /** - * @brief Architecture specific function for updating addresses via relocation table + * @brief Extract ELF section header by name. + * + * Searches for a section by name in the ELF file and retrieves its full header. + * + * @param[in] loader Extension loader data and context + * @param[in] ext Extension to be searched + * @param[in] search_name Section name to search for + * @param[out] shdr Buffer for the section header + * @retval 0 Success + * @retval -ENOTSUP "peek" method not supported + * @retval -ENOENT section not found + */ +int llext_get_section_header(struct llext_loader *loader, struct llext *ext, + const char *search_name, elf_shdr_t *shdr); + +/** + * @brief Architecture specific function for local binding relocations + * + * @param[in] loader Extension loader data and context + * @param[in] ext Extension to call function in + * @param[in] rel Relocation data provided by elf + * @param[in] sym Corresponding symbol table entry + * @param[in] got_offset Offset within a relocation table or in the code + * @param[in] ldr_parm Loader parameters + */ +void arch_elf_relocate_local(struct llext_loader *loader, struct llext *ext, const elf_rela_t *rel, + const elf_sym_t *sym, size_t got_offset, + const struct llext_load_param *ldr_parm); + +/** + * @brief Architecture specific function for global binding relocations * * @param[in] loader Extension loader data and context * @param[in] ext Extension to call function in * @param[in] rel Relocation data provided by elf * @param[in] sym Corresponding symbol table entry - * @param[in] got_offset Offset within a relocation table + * @param[in] got_offset Offset within a relocation table or in the code + * @param[in] link_addr target address for table-based relocations */ -void arch_elf_relocate_local(struct llext_loader *loader, struct llext *ext, - const elf_rela_t *rel, const elf_sym_t *sym, size_t got_offset); +void arch_elf_relocate_global(struct llext_loader *loader, struct llext *ext, const elf_rela_t *rel, + const elf_sym_t *sym, size_t got_offset, const void *link_addr); /** * @} diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext_internal.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext_internal.h new file mode 100644 index 00000000..f07dd5ef --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/llext_internal.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_LLEXT_INTERNAL_H +#define ZEPHYR_LLEXT_INTERNAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * @brief Private header for linkable loadable extensions + */ + +/** @cond ignore */ + +struct llext_loader; +struct llext; + +const void *llext_loaded_sect_ptr(struct llext_loader *ldr, struct llext *ext, unsigned int sh_ndx); + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_LLEXT_INTERNAL_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/loader.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/loader.h index ffc0d504..3d043806 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/loader.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/loader.h @@ -40,6 +40,15 @@ struct llext_elf_sect_map; /* defined in llext_priv.h */ * extension is loaded, this object is no longer needed. */ struct llext_loader { + /** + * @brief Optional function to prepare the loader for loading extension. + * + * @param[in] ldr Loader + * + * @returns 0 on success, or a negative error. + */ + int (*prepare)(struct llext_loader *ldr); + /** * @brief Function to read (copy) from the loader * @@ -79,17 +88,30 @@ struct llext_loader { */ void *(*peek)(struct llext_loader *ldr, size_t pos); + /** + * @brief Optional function to clean after the extension has been loaded or error occurred. + * + * @param[in] ldr Loader + */ + void (*finalize)(struct llext_loader *ldr); + /** @cond ignore */ elf_ehdr_t hdr; elf_shdr_t sects[LLEXT_MEM_COUNT]; - elf_shdr_t *sect_hdrs; - bool sect_hdrs_on_heap; struct llext_elf_sect_map *sect_map; - uint32_t sect_cnt; /** @endcond */ }; /** @cond ignore */ +static inline int llext_prepare(struct llext_loader *l) +{ + if (l->prepare) { + return l->prepare(l); + } + + return 0; +} + static inline int llext_read(struct llext_loader *l, void *buf, size_t len) { return l->read(l, buf, len); @@ -108,6 +130,13 @@ static inline void *llext_peek(struct llext_loader *l, size_t pos) return NULL; } + +static inline void llext_finalize(struct llext_loader *l) +{ + if (l->finalize) { + l->finalize(l); + } +} /* @endcond */ /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/symbol.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/symbol.h index 880cb4f8..9eb847b9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/symbol.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/llext/symbol.h @@ -93,7 +93,7 @@ struct llext_symtable { #define Z_LL_EXTENSION_SYMBOL(x) \ static const struct llext_const_symbol \ Z_GENERIC_SECTION(".exported_sym") __used \ - x ## _sym = { \ + __llext_sym_ ## x = { \ .name = STRINGIFY(x), .addr = (const void *)&x, \ } #else @@ -123,14 +123,16 @@ struct llext_symtable { /* SLID-enabled LLEXT application: export symbols, names in separate section */ #define Z_EXPORT_SYMBOL(x) \ static const char Z_GENERIC_SECTION("llext_exports_strtab") __used \ - x ## _sym_name[] = STRINGIFY(x); \ - static const STRUCT_SECTION_ITERABLE(llext_const_symbol, x ## _sym) = { \ - .name = x ## _sym_name, .addr = (const void *)&x, \ + __llext_sym_name_ ## x[] = STRINGIFY(x); \ + static const STRUCT_SECTION_ITERABLE(llext_const_symbol, \ + __llext_sym_ ## x) = { \ + .name = __llext_sym_name_ ## x, .addr = (const void *)&x, \ } #elif defined(CONFIG_LLEXT) /* LLEXT application: export symbols */ #define Z_EXPORT_SYMBOL(x) \ - static const STRUCT_SECTION_ITERABLE(llext_const_symbol, x ## _sym) = { \ + static const STRUCT_SECTION_ITERABLE(llext_const_symbol, \ + __llext_sym_ ## x) = { \ .name = STRINGIFY(x), .addr = (const void *)&x, \ } #else diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log.h index f92be9bc..7edfca9a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log.h @@ -328,8 +328,7 @@ void z_log_vprintk(const char *fmt, va_list ap); log_source_const_data, \ Z_LOG_ITEM_CONST_DATA(_name)) = \ { \ - .name = IS_ENABLED(CONFIG_LOG_FMT_SECTION_STRIP) ? NULL : \ - COND_CODE_1(CONFIG_LOG_FMT_SECTION, \ + .name = COND_CODE_1(CONFIG_LOG_FMT_SECTION, \ (UTIL_CAT(_name, _str)), (STRINGIFY(_name))), \ .level = (_level) \ } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_backend_ws.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_backend_ws.h new file mode 100644 index 00000000..0894d2ca --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_backend_ws.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_LOG_BACKEND_WS_H_ +#define ZEPHYR_LOG_BACKEND_WS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Register websocket socket where the logging output is sent. + * + * @param fd Websocket socket value. + * + * @return 0 if ok, <0 if error + */ +int log_backend_ws_register(int fd); + +/** + * @brief Unregister websocket socket where the logging output was sent. + * + * @details After this the websocket output is disabled. + * + * @param fd Websocket socket value. + * + * @return 0 if ok, <0 if error + */ +int log_backend_ws_unregister(int fd); + +/** + * @brief Get the websocket logger backend + * + * @details This function returns the websocket logger backend. + * + * @return Pointer to the websocket logger backend. + */ +const struct log_backend *log_backend_ws_get(void); + +/** + * @brief Start the websocket logger backend + * + * @details This function starts the websocket logger backend. + */ +void log_backend_ws_start(void); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_LOG_BACKEND_WS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_core.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_core.h index 42ef6e99..64cd2a6c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_core.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_core.h @@ -16,19 +16,19 @@ /* This header file keeps all macros and functions needed for creating logging * messages (macros like @ref LOG_ERR). */ -#define LOG_LEVEL_NONE 0U -#define LOG_LEVEL_ERR 1U -#define LOG_LEVEL_WRN 2U -#define LOG_LEVEL_INF 3U -#define LOG_LEVEL_DBG 4U +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERR 1 +#define LOG_LEVEL_WRN 2 +#define LOG_LEVEL_INF 3 +#define LOG_LEVEL_DBG 4 #ifdef __cplusplus extern "C" { #endif #ifndef CONFIG_LOG -#define CONFIG_LOG_DEFAULT_LEVEL 0U -#define CONFIG_LOG_MAX_LEVEL 0U +#define CONFIG_LOG_DEFAULT_LEVEL 0 +#define CONFIG_LOG_MAX_LEVEL 0 #endif /* Id of local domain. */ @@ -54,15 +54,10 @@ extern "C" { __COND_CODE(_LOG_XXXX##_level, (_level), (_default)) #define _LOG_XXXX0 _LOG_YYYY, -#define _LOG_XXXX0U _LOG_YYYY, #define _LOG_XXXX1 _LOG_YYYY, -#define _LOG_XXXX1U _LOG_YYYY, #define _LOG_XXXX2 _LOG_YYYY, -#define _LOG_XXXX2U _LOG_YYYY, #define _LOG_XXXX3 _LOG_YYYY, -#define _LOG_XXXX3U _LOG_YYYY, #define _LOG_XXXX4 _LOG_YYYY, -#define _LOG_XXXX4U _LOG_YYYY, /** * @brief Macro for conditional code generation if provided log level allows. @@ -85,13 +80,9 @@ extern "C" { __COND_CODE(_LOG_ZZZZ##_eval_level, _iftrue, _iffalse) #define _LOG_ZZZZ1 _LOG_YYYY, -#define _LOG_ZZZZ1U _LOG_YYYY, #define _LOG_ZZZZ2 _LOG_YYYY, -#define _LOG_ZZZZ2U _LOG_YYYY, #define _LOG_ZZZZ3 _LOG_YYYY, -#define _LOG_ZZZZ3U _LOG_YYYY, #define _LOG_ZZZZ4 _LOG_YYYY, -#define _LOG_ZZZZ4U _LOG_YYYY, /** * @@ -101,11 +92,11 @@ extern "C" { log_const_source_id(__log_current_const_data) : 0U) /* Set of defines that are set to 1 if function name prefix is enabled for given level. */ -#define Z_LOG_FUNC_PREFIX_0U 0 -#define Z_LOG_FUNC_PREFIX_1U COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_ERR, (1), (0)) -#define Z_LOG_FUNC_PREFIX_2U COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_WRN, (1), (0)) -#define Z_LOG_FUNC_PREFIX_3U COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_INF, (1), (0)) -#define Z_LOG_FUNC_PREFIX_4U COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_DBG, (1), (0)) +#define Z_LOG_FUNC_PREFIX_0 0 +#define Z_LOG_FUNC_PREFIX_1 COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_ERR, (1), (0)) +#define Z_LOG_FUNC_PREFIX_2 COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_WRN, (1), (0)) +#define Z_LOG_FUNC_PREFIX_3 COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_INF, (1), (0)) +#define Z_LOG_FUNC_PREFIX_4 COND_CODE_1(CONFIG_LOG_FUNC_NAME_PREFIX_DBG, (1), (0)) /** * @brief Macro for optional injection of function name as first argument of @@ -143,6 +134,15 @@ extern "C" { #define Z_LOG_LEVEL_CHECK(_level, _check_level, _default_level) \ ((_level) <= Z_LOG_RESOLVED_LEVEL(_check_level, _default_level)) +/** @brief Compile time level checking. + * + * This check is resolved at compile time and logging message is removed if check fails. + * + * @param _level Log level. + * + * @retval true Message shall be compiled in. + * @retval false Message shall removed during the compilation. + */ #define Z_LOG_CONST_LEVEL_CHECK(_level) \ (IS_ENABLED(CONFIG_LOG) && \ (Z_LOG_LEVEL_CHECK(_level, CONFIG_LOG_OVERRIDE_LEVEL, LOG_LEVEL_NONE) \ @@ -153,6 +153,63 @@ extern "C" { ) \ )) +/** @brief Static level checking for instance logging. + * + * This check applies only to instance logging and only if runtime filtering + * is disabled. It is performed in runtime but because level comes from the + * structure which is constant it is not exact runtime filtering because it + * cannot be changed in runtime. + * + * @param _level Log level. + * @param _inst 1 is source is the instance of a module. + * @param _source Data associated with the instance. + * + * @retval true Continue with log message creation. + * @retval false Drop that message. + */ +#define Z_LOG_STATIC_INST_LEVEL_CHECK(_level, _inst, _source) \ + (IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) || !_inst || \ + (_level <= ((const struct log_source_const_data *)_source)->level)) + +/** @brief Dynamic level checking. + * + * It uses the level from the dynamic structure. + * + * @param _level Log level. + * @param _source Data associated with the source. + * + * @retval true Continue with log message creation. + * @retval false Drop that message. + */ +#define Z_LOG_DYNAMIC_LEVEL_CHECK(_level, _source) \ + (!IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) || k_is_user_context() || \ + ((_level) <= Z_LOG_RUNTIME_FILTER(((struct log_source_dynamic_data *)_source)->filters))) + +/** @brief Check if message shall be created. + * + * Aggregate all checks into a single one. + * + * @param _level Log level. + * @param _inst 1 is source is the instance of a module. + * @param _source Data associated with the source. + * + * @retval true Continue with log message creation. + * @retval false Drop that message. + */ +#define Z_LOG_LEVEL_ALL_CHECK(_level, _inst, _source) \ + (Z_LOG_CONST_LEVEL_CHECK(_level) && \ + Z_LOG_STATIC_INST_LEVEL_CHECK(_level, _inst, _source) && \ + Z_LOG_DYNAMIC_LEVEL_CHECK(_level, _source)) + +/** @brief Get current module data that is used for source id retrieving. + * + * If runtime filtering is used then pointer to dynamic data is returned and else constant + * data is used. + */ +#define Z_LOG_CURRENT_DATA() \ + COND_CODE_1(CONFIG_LOG_RUNTIME_FILTERING, \ + (__log_current_dynamic_data), (__log_current_const_data)) + /*****************************************************************************/ /****************** Definitions used by minimal logging *********************/ /*****************************************************************************/ @@ -226,68 +283,41 @@ static inline char z_log_minimal_level_to_char(int level) * @param _level Log message severity level. * * @param _inst Set to 1 for instance specific log message. 0 otherwise. - * - * @param _source Pointer to static source descriptor object. NULL when runtime filtering - * is enabled. - * - * @param _dsource Pointer to dynamic source descriptor. NULL when runtime filtering - * is disabled. + * @param _source Pointer to a structure associated with the module or instance. + * If it is a module then it is used only when runtime filtering is + * enabled. If it is instance then it is used in both cases. * * @param ... String with arguments. */ -#define Z_LOG2(_level, _inst, _source, _dsource, ...) do { \ - if (!Z_LOG_CONST_LEVEL_CHECK(_level)) { \ - break; \ - } \ - if (IS_ENABLED(CONFIG_LOG_MODE_MINIMAL)) { \ - Z_LOG_TO_PRINTK(_level, __VA_ARGS__); \ - break; \ - } \ - /* For instance logging check instance specific static level */ \ - if (_inst != 0 && !IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING)) { \ - if (_level > ((struct log_source_const_data *)_source)->level) { \ - break; \ - } \ - } \ - \ - bool is_user_context = k_is_user_context(); \ - if (IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) && \ - !is_user_context && _level > Z_LOG_RUNTIME_FILTER((_dsource)->filters)) { \ - break; \ - } \ - int _mode; \ - void *_src = IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) ? \ - (void *)(_dsource) : (void *)(_source); \ - bool string_ok; \ - LOG_POINTERS_VALIDATE(string_ok, __VA_ARGS__); \ - if (!string_ok) { \ - LOG_STRING_WARNING(_mode, _src, __VA_ARGS__); \ - break; \ - } \ - Z_LOG_MSG_CREATE(UTIL_NOT(IS_ENABLED(CONFIG_USERSPACE)), _mode, \ - Z_LOG_LOCAL_DOMAIN_ID, _src, _level, NULL,\ - 0, __VA_ARGS__); \ - (void)_mode; \ - if (false) { \ - /* Arguments checker present but never evaluated.*/ \ - /* Placed here to ensure that __VA_ARGS__ are*/ \ - /* evaluated once when log is enabled.*/ \ - z_log_printf_arg_checker(__VA_ARGS__); \ - } \ -} while (false) +#define Z_LOG2(_level, _inst, _source, ...) \ + do { \ + if (!Z_LOG_LEVEL_ALL_CHECK(_level, _inst, _source)) { \ + break; \ + } \ + if (IS_ENABLED(CONFIG_LOG_MODE_MINIMAL)) { \ + Z_LOG_TO_PRINTK(_level, __VA_ARGS__); \ + break; \ + } \ + int _mode; \ + bool string_ok; \ + LOG_POINTERS_VALIDATE(string_ok, __VA_ARGS__); \ + if (!string_ok) { \ + LOG_STRING_WARNING(_mode, _source, __VA_ARGS__); \ + break; \ + } \ + Z_LOG_MSG_CREATE(UTIL_NOT(IS_ENABLED(CONFIG_USERSPACE)), _mode, \ + Z_LOG_LOCAL_DOMAIN_ID, _source, _level, NULL, 0, __VA_ARGS__); \ + (void)_mode; \ + if (false) { \ + /* Arguments checker present but never evaluated.*/ \ + /* Placed here to ensure that __VA_ARGS__ are*/ \ + /* evaluated once when log is enabled.*/ \ + z_log_printf_arg_checker(__VA_ARGS__); \ + } \ + } while (false) -#define Z_LOG(_level, ...) \ - Z_LOG2(_level, 0, __log_current_const_data, __log_current_dynamic_data, __VA_ARGS__) - -#define Z_LOG_INSTANCE(_level, _inst, ...) do { \ - (void)_inst; \ - Z_LOG2(_level, 1, \ - COND_CODE_1(CONFIG_LOG_RUNTIME_FILTERING, (NULL), (Z_LOG_INST(_inst))), \ - (struct log_source_dynamic_data *)COND_CODE_1( \ - CONFIG_LOG_RUNTIME_FILTERING, \ - (Z_LOG_INST(_inst)), (NULL)), \ - __VA_ARGS__); \ -} while (0) +#define Z_LOG(_level, ...) Z_LOG2(_level, 0, Z_LOG_CURRENT_DATA(), __VA_ARGS__) +#define Z_LOG_INSTANCE(_level, _inst, ...) Z_LOG2(_level, 1, Z_LOG_INST(_inst), __VA_ARGS__) /*****************************************************************************/ /****************** Macros for hexdump logging *******************************/ @@ -302,11 +332,9 @@ static inline char z_log_minimal_level_to_char(int level) * * @param _inst Set to 1 for instance specific log message. 0 otherwise. * - * @param _source Pointer to static source descriptor object. NULL when runtime filtering - * is enabled. - * - * @param _dsource Pointer to dynamic source descriptor. NULL when runtime filtering - * is disabled. + * @param _source Pointer to a structure associated with the module or instance. + * If it is a module then it is used only when runtime filtering is + * enabled. If it is instance then it is used in both cases. * * @param _data Hexdump data; * @@ -314,56 +342,31 @@ static inline char z_log_minimal_level_to_char(int level) * * @param ... String. */ -#define Z_LOG_HEXDUMP2(_level, _inst, _source, _dsource, _data, _len, ...) do { \ - const char *_str = GET_ARG_N(1, __VA_ARGS__); \ - if (!Z_LOG_CONST_LEVEL_CHECK(_level)) { \ - break; \ - } \ - /* For instance logging check instance specific static level */ \ - if (_inst && !IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING)) { \ - if (_level > ((struct log_source_const_data *)_source)->level) { \ - break; \ - } \ - } \ - bool is_user_context = k_is_user_context(); \ - uint32_t filters = IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) ? \ - (_dsource)->filters : 0;\ - \ - if (IS_ENABLED(CONFIG_LOG_MODE_MINIMAL)) { \ - Z_LOG_TO_PRINTK(_level, "%s", _str); \ - z_log_minimal_hexdump_print((_level), \ - (const char *)(_data), (_len));\ - break; \ - } \ - if (IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) && \ - !is_user_context && (_level) > Z_LOG_RUNTIME_FILTER(filters)) { \ - break; \ - } \ - int mode; \ - void *_src = IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) ? \ - (void *)(_dsource) : (void *)(_source); \ - Z_LOG_MSG_CREATE(UTIL_NOT(IS_ENABLED(CONFIG_USERSPACE)), mode, \ - Z_LOG_LOCAL_DOMAIN_ID, _src, _level, \ - _data, _len, \ - COND_CODE_0(NUM_VA_ARGS_LESS_1(_, ##__VA_ARGS__), \ +#define Z_LOG_HEXDUMP2(_level, _inst, _source, _data, _len, ...) \ + do { \ + if (!Z_LOG_LEVEL_ALL_CHECK(_level, _inst, _source)) { \ + break; \ + } \ + const char *_str = GET_ARG_N(1, __VA_ARGS__); \ + if (IS_ENABLED(CONFIG_LOG_MODE_MINIMAL)) { \ + Z_LOG_TO_PRINTK(_level, "%s", _str); \ + z_log_minimal_hexdump_print((_level), (const char *)(_data), (_len)); \ + break; \ + } \ + int mode; \ + Z_LOG_MSG_CREATE(UTIL_NOT(IS_ENABLED(CONFIG_USERSPACE)), mode, \ + Z_LOG_LOCAL_DOMAIN_ID, _source, _level, _data, _len, \ + COND_CODE_0(NUM_VA_ARGS_LESS_1(_, ##__VA_ARGS__), \ (), \ (COND_CODE_0(NUM_VA_ARGS_LESS_1(__VA_ARGS__), \ - ("%s", __VA_ARGS__), (__VA_ARGS__)))));\ -} while (false) + ("%s", __VA_ARGS__), (__VA_ARGS__))))); \ + } while (false) -#define Z_LOG_HEXDUMP(_level, _data, _length, ...) \ - Z_LOG_HEXDUMP2(_level, 0, \ - __log_current_const_data, \ - __log_current_dynamic_data, \ - _data, _length, __VA_ARGS__) +#define Z_LOG_HEXDUMP(_level, _data, _length, ...) \ + Z_LOG_HEXDUMP2(_level, 0, Z_LOG_CURRENT_DATA(), _data, _length, __VA_ARGS__) -#define Z_LOG_HEXDUMP_INSTANCE(_level, _inst, _data, _length, _str) \ - Z_LOG_HEXDUMP2(_level, 1, \ - COND_CODE_1(CONFIG_LOG_RUNTIME_FILTERING, (NULL), (Z_LOG_INST(_inst))), \ - (struct log_source_dynamic_data *)COND_CODE_1( \ - CONFIG_LOG_RUNTIME_FILTERING, \ - (Z_LOG_INST(_inst)), (NULL)), \ - _data, _length, _str) +#define Z_LOG_HEXDUMP_INSTANCE(_level, _inst, _data, _length, ...) \ + Z_LOG_HEXDUMP2(_level, 1, Z_LOG_INST(_inst), _data, _length, __VA_ARGS__) /*****************************************************************************/ /****************** Filtering macros *****************************************/ @@ -493,6 +496,20 @@ static inline uint32_t log_dynamic_source_id(struct log_source_dynamic_data *dat sizeof(struct log_source_dynamic_data); } +/** @brief Get index of the log source based on the address of the associated data. + * + * @param source Address of the data structure (dynamic if runtime filtering is + * enabled and static otherwise). + * + * @return Source ID. + */ +static inline uint32_t log_source_id(const void *source) +{ + return IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING) ? + log_dynamic_source_id((struct log_source_dynamic_data *)source) : + log_const_source_id((const struct log_source_const_data *)source); +} + /** @brief Dummy function to trigger log messages arguments type checking. */ static inline __printf_like(1, 2) void z_log_printf_arg_checker(const char *fmt, ...) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_frontend_stmesp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_frontend_stmesp.h new file mode 100644 index 00000000..e2b7a215 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_frontend_stmesp.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_LOGGING_LOG_FRONTEND_STMESP_H_ +#define ZEPHYR_INCLUDE_LOGGING_LOG_FRONTEND_STMESP_H_ + +#include +#include +#ifdef CONFIG_LOG_FRONTEND_STMESP +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Notify frontend that ETR/STM is ready. + * + * Log frontend optionally dumps buffered data and start to write to the STM + * stimulus port. + * + * @note Function is applicable only for the domain that performs initial ETR/STM setup. + * + * @retval 0 on success. + * @retval -EIO if there was an internal failure. + */ +int log_frontend_stmesp_etr_ready(void); + +/** @brief Hook to be called before going to sleep. + * + * Hook writes dummy data to the STM Stimulus Port to ensure that all logging + * data is flushed. + */ +void log_frontend_stmesp_pre_sleep(void); + +/** @brief Perform a dummy write to STMESP. + * + * It can be used to force flushing STM data. + */ +void log_frontend_stmesp_dummy_write(void); + +/** @brief Trace point + * + * Write a trace point information using STM. Number of unique trace points is limited + * to 32768 - CONFIG_LOG_FRONTEND_STMESP_TP_CHAN_BASE per core. + * + * @param x Trace point ID. + */ +static inline void log_frontend_stmesp_tp(uint16_t x) +{ +#ifdef CONFIG_LOG_FRONTEND_STMESP + STMESP_Type *port; + int err = stmesp_get_port((uint32_t)x + CONFIG_LOG_FRONTEND_STMESP_TP_CHAN_BASE, &port); + + __ASSERT_NO_MSG(err == 0); + if (err == 0) { + stmesp_flag(port, 1, true, + IS_ENABLED(CONFIG_LOG_FRONTEND_STMESP_GUARANTEED_ACCESS)); + } +#endif +} + +/** @brief Trace point with 32 bit data. + * + * Write a trace point information using STM. Number of unique trace points is limited + * to 32768 - CONFIG_LOG_FRONTEND_STMESP_TP_CHAN_BASE per core. + * + * @param x Trace point ID. + * @param d Data. 32 bit word. + */ +static inline void log_frontend_stmesp_tp_d32(uint16_t x, uint32_t d) +{ +#ifdef CONFIG_LOG_FRONTEND_STMESP + STMESP_Type *port; + int err = stmesp_get_port((uint32_t)x + CONFIG_LOG_FRONTEND_STMESP_TP_CHAN_BASE, &port); + + __ASSERT_NO_MSG(err == 0); + if (err == 0) { + stmesp_data32(port, d, true, true, + IS_ENABLED(CONFIG_LOG_FRONTEND_STMESP_GUARANTEED_ACCESS)); + } +#endif +} + +/** @brief Function called for log message with no arguments when turbo logging is enabled. + * + * @param source Pointer to the source structure. + * @param x Index of the string used for the log message. + */ +void log_frontend_stmesp_log0(const void *source, uint32_t x); + +/** @brief Function called for log message with one argument when turbo logging is enabled. + * + * @param source Pointer to the source structure. + * @param x Index of the string used for the log message. + * @param arg Argument. + */ +void log_frontend_stmesp_log1(const void *source, uint32_t x, uint32_t arg); + +TYPE_SECTION_START_EXTERN(const char *, log_stmesp_ptr); + +/** @brief Macro for handling a turbo log message with no arguments. + * + * @param _source Pointer to the source structure. + * @param ... String. + */ +#define LOG_FRONTEND_STMESP_LOG0(_source, ...) \ + do { \ + static const char _str[] __in_section(_log_stmesp_str, static, _) \ + __used __noasan __aligned(sizeof(uint32_t)) = GET_ARG_N(1, __VA_ARGS__); \ + static const char *_str_ptr __in_section(_log_stmesp_ptr, static, _) \ + __used __noasan = _str; \ + uint32_t idx = \ + ((uintptr_t)&_str_ptr - (uintptr_t)TYPE_SECTION_START(log_stmesp_ptr)) / \ + sizeof(void *); \ + log_frontend_stmesp_log0(_source, idx); \ + } while (0) + +/** @brief Macro for handling a turbo log message with one argument. + * + * @param _source Pointer to the source structure. + * @param ... String with one numeric argument. + */ +#define LOG_FRONTEND_STMESP_LOG1(_source, ...) \ + do { \ + static const char _str[] __in_section(_log_stmesp_str, static, _) \ + __used __noasan __aligned(sizeof(uint32_t)) = GET_ARG_N(1, __VA_ARGS__); \ + static const char *_str_ptr __in_section(_log_stmesp_ptr, static, _) \ + __used __noasan = _str; \ + uint32_t idx = \ + ((uintptr_t)&_str_ptr - (uintptr_t)TYPE_SECTION_START(log_stmesp_ptr)) / \ + sizeof(void *); \ + log_frontend_stmesp_log1(_source, idx, (uintptr_t)(GET_ARG_N(2, __VA_ARGS__))); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_LOGGING_LOG_FRONTEND_STMESP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_frontend_stmesp_demux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_frontend_stmesp_demux.h new file mode 100644 index 00000000..728ce401 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_frontend_stmesp_demux.h @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_LOGGING_LOG_FRONTEND_STMESP_DEMUX_H_ +#define ZEPHYR_INCLUDE_LOGGING_LOG_FRONTEND_STMESP_DEMUX_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup log_frontend_stmesp_apis Trace and Debug Domain APIs + * @{ + * @} + * @defgroup log_frontend_stpesp_demux_apis Logging frontend STMESP Demultiplexer API + * @ingroup log_frontend_stmesp_apis + * @{ + */ + +/** @brief Bits used to store major index. */ +#define LOG_FRONTEND_STMESP_DEMUX_MAJOR_BITS 3 + +/** @brief Bits used to store severity level. */ +#define LOG_FRONTEND_STMESP_DEMUX_LEVEL_BITS 3 + +/** @brief Bits used to store total length. */ +#define LOG_FRONTEND_STMESP_DEMUX_TLENGTH_BITS 16 + +/** @brief Bits used to store package length. */ +#define LOG_FRONTEND_STMESP_DEMUX_PLENGTH_BITS 10 + +/** @brief Maximum number of supported majors. */ +#define LOG_FRONTEND_STMESP_DEMUX_MAJOR_MAX BIT(LOG_FRONTEND_STMESP_DEMUX_MAJOR_BITS) + +/** @brief Log message type. */ +#define LOG_FRONTEND_STMESP_DEMUX_TYPE_LOG 0 + +/** @brief Trace point message type. */ +#define LOG_FRONTEND_STMESP_DEMUX_TYPE_TRACE_POINT 1 + +/** @brief HW event message type. */ +#define LOG_FRONTEND_STMESP_DEMUX_TYPE_HW_EVENT 2 + +/** @brief Logging message header. */ +struct log_frontend_stmesp_demux_log_header { + /** Major index. */ + uint32_t major : LOG_FRONTEND_STMESP_DEMUX_MAJOR_BITS; + + /** Severity level. */ + uint32_t level : LOG_FRONTEND_STMESP_DEMUX_LEVEL_BITS; + + /** Total length excluding this header. */ + uint32_t total_len : LOG_FRONTEND_STMESP_DEMUX_TLENGTH_BITS; + + /** Hexdump data length. */ + uint32_t package_len : LOG_FRONTEND_STMESP_DEMUX_PLENGTH_BITS; +}; + +/** @brief Union for writing raw data to the logging message header. */ +union log_frontend_stmesp_demux_header { + /** Log header structure. */ + struct log_frontend_stmesp_demux_log_header log; + + /** Raw word. */ + uint32_t raw; +}; + +/** @brief Generic STP demux packet. */ +struct log_frontend_stmesp_demux_packet_generic { + /** Data for MPSC packet handling. */ + MPSC_PBUF_HDR; + + /** Type. */ + uint64_t type: 2; + + /** Flag indicating if packet is valid. */ + uint64_t content_invalid: 1; +}; + +/** @brief Packet with logging message. */ +struct log_frontend_stmesp_demux_log { + /** Data for MPSC packet handling. */ + MPSC_PBUF_HDR; + + /** Type. */ + uint64_t type: 2; + + /** Flag indicating if packet is valid. */ + uint64_t content_invalid: 1; + + /** Timestamp. */ + uint64_t timestamp: 59; + + /** Logging header. */ + struct log_frontend_stmesp_demux_log_header hdr; + + /** Padding so that data is 8 bytes aligned. */ + uint32_t padding; + + /** Content. */ + uint8_t data[]; +}; + +/** @brief Packet with trace point. */ +struct log_frontend_stmesp_demux_trace_point { + /** Data for MPSC packet handling. */ + MPSC_PBUF_HDR; + + /** Type. */ + uint64_t type: 2; + + /** Flag indicating if packet is valid. */ + uint64_t content_invalid: 1; + + /** Flag indicating if trace point includes data. */ + uint64_t has_data: 1; + + /** Timestamp. 54 bits at 40MHz is >14 years. */ + uint64_t timestamp: 54; + + /** Major ID. */ + uint64_t major: 4; + + /** Source ID - used for compressed logging. */ + uint16_t source_id; + + /** ID */ + uint16_t id; + + /** Content. */ + uint32_t data; +}; + +/** @brief Packet with HW event. */ +struct log_frontend_stmesp_demux_hw_event { + /** Data for MPSC packet handling. */ + MPSC_PBUF_HDR; + + /** Type. */ + uint64_t type: 2; + + /** Flag indicating if packet is valid. */ + uint64_t content_invalid: 1; + + /** Timestamp. */ + uint64_t timestamp: 59; + + /** HW event ID. */ + uint8_t evt; +}; + +/** @brief Union of all packet types. */ +union log_frontend_stmesp_demux_packet { + /** Pointer to generic mpsc_pbuf const packet. */ + const union mpsc_pbuf_generic *rgeneric; + + /** Pointer to generic mpsc_pbuf packet. */ + union mpsc_pbuf_generic *generic; + + /** Pointer to the log message. */ + struct log_frontend_stmesp_demux_log *log; + + /** Pointer to the trace point message. */ + struct log_frontend_stmesp_demux_trace_point *trace_point; + + /** Pointer to the HW event message. */ + struct log_frontend_stmesp_demux_hw_event *hw_event; + + /** Pointer to the generic log_frontend_stmesp_demux packet. */ + struct log_frontend_stmesp_demux_packet_generic *generic_packet; +}; + +/** @brief Demultiplexer configuration. */ +struct log_frontend_stmesp_demux_config { + /** Array with expected major ID's. */ + const uint16_t *m_ids; + + /** Array length. Must be not bigger than @ref LOG_FRONTEND_STMESP_DEMUX_MAJOR_MAX. */ + uint32_t m_ids_cnt; + + /** Buffer for storing source ID's. Used for turbo logging. */ + uint32_t *source_id_buf; + + /** It must be multiple of number of major ID's count. */ + size_t source_id_buf_len; +}; + +/** @brief Initialize the demultiplexer. + * + * @param config Configuration. + * + * @retval 0 on success. + * @retval -EINVAL on invalid configuration. + */ +int log_frontend_stmesp_demux_init(const struct log_frontend_stmesp_demux_config *config); + +/** @brief Indicate major opcode in the STPv2 stream. + * + * @param id Master ID. + */ +void log_frontend_stmesp_demux_major(uint16_t id); + +/** @brief Indicate channel opcode in the STPv2 stream. + * + * @param id Channel ID. + */ +void log_frontend_stmesp_demux_channel(uint16_t id); + +/** @brief Indicate detected packet start (DMTS). + * + * @param data Data. Can be NULL which indicates trace point without data. + * @param ts Timestamp. Can be NULL. + */ +int log_frontend_stmesp_demux_packet_start(uint32_t *data, uint64_t *ts); + +/** @brief Indicate optimized log message with no arguments. + * + * @param source_id Source ID. + * @param ts Timestamp. Can be NULL. + */ +int log_frontend_stmesp_demux_log0(uint16_t source_id, uint64_t *ts); + +/** @brief Indicate source ID. + * + * @param source_id Source ID. + */ +void log_frontend_stmesp_demux_source_id(uint16_t source_id); + +/** @brief Indicate timestamp. + * + * Timestamp is separated from packet start because according to STM spec (3.2.2) + * it is possible that timestamp is assigned to a later packet. + * + * @param ts Timestamp. + */ +void log_frontend_stmesp_demux_timestamp(uint64_t ts); + +/** @brief Indicate data. + * + * @param data Data buffer. + * @param len Length. + */ +void log_frontend_stmesp_demux_data(uint8_t *data, size_t len); + +/** @brief Indicate packet end (Flag). */ +void log_frontend_stmesp_demux_packet_end(void); + +/** @brief Get number of dropped messages and reset the counter. + * + * Message can be dropped if there is no room in the packet buffer. + * + * @return Number of dropped messages. + */ +uint32_t log_frontend_stmesp_demux_get_dropped(void); + +/** @brief Claim packet. + * + * Get pointer to the pending packet with logging message. Packet must be freed + * using @ref log_frontend_stmesp_demux_free. + * + * @return Pointer to the packet or NULL. + */ +union log_frontend_stmesp_demux_packet log_frontend_stmesp_demux_claim(void); + +/** @brief Free previously claimed packet. + * + * See @ref log_frontend_stmesp_demux_claim. + * + * @param packet Packet. + */ +void log_frontend_stmesp_demux_free(union log_frontend_stmesp_demux_packet packet); + +/** @brief Get source name for a turbo log message. + * + * During a boot cooprocessors (FLPR and PPR) are sending location in memory where + * their source data is stored. If application core is an owner of those cores + * it has access to that memory and based on chip ID and source ID it can retrieve + * the source name. + * + * @param m_id Major ID. + * @param s_id Source ID. + * + * @return Pointer to a string which is a source name or unknown name if source name + * cannot be retrieved. + */ +const char *log_frontend_stmesp_demux_sname_get(uint32_t m_id, uint16_t s_id); + +/** @brief Check if there are any started but not completed log messages. + * + * @retval True There is no pending started log message. + * @retval False There is pending message. + */ +bool log_frontend_stmesp_demux_is_idle(void); + +/** @brief Close any opened messages and mark them as invalid. */ +void log_frontend_stmesp_demux_reset(void); + +/** @brief Get maximum buffer utilization. + * + * @retval Non-negative Maximum buffer utilization. + * @retval -ENOTSUP Feature not enabled. + */ +int log_frontend_stmesp_demux_max_utilization(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_LOGGING_LOG_FRONTEND_STMESP_DEMUX_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_output.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_output.h index 0ef3fe9a..46b59520 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_output.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/logging/log_output.h @@ -190,11 +190,34 @@ void log_output_msg_syst_process(const struct log_output *log_output, */ void log_output_dropped_process(const struct log_output *output, uint32_t cnt); +/** @brief Write to the output buffer. + * + * @param outf Output function. + * @param buf Buffer. + * @param len Buffer length. + * @param ctx Context passed to the %p outf. + */ +static inline void log_output_write(log_output_func_t outf, uint8_t *buf, size_t len, void *ctx) +{ + int processed; + + while (len != 0) { + processed = outf(buf, len, ctx); + len -= processed; + buf += processed; + } +} + /** @brief Flush output buffer. * * @param output Pointer to the log output instance. */ -void log_output_flush(const struct log_output *output); +static inline void log_output_flush(const struct log_output *output) +{ + log_output_write(output->func, output->buf, output->control_block->offset, + output->control_block->ctx); + output->control_block->offset = 0; +} /** @brief Function for setting user context passed to the output function. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/lorawan/lorawan.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/lorawan/lorawan.h index 058c4cba..91499724 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/lorawan/lorawan.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/lorawan/lorawan.h @@ -103,6 +103,14 @@ enum lorawan_message_type { LORAWAN_MSG_CONFIRMED, /**< Confirmed message */ }; +/** + * @brief LoRaWAN downlink flags. + */ +enum lorawan_dl_flags { + LORAWAN_DATA_PENDING = BIT(0), + LORAWAN_TIME_UPDATED = BIT(1), +}; + /** * @brief LoRaWAN join parameters for over-the-Air activation (OTAA) * @@ -181,15 +189,14 @@ struct lorawan_downlink_cb { * and should therefore be as short as possible. * * @param port Port message was sent on - * @param data_pending Network server has more downlink packets pending + * @param flags Downlink data flags (see @ref lorawan_dl_flags) * @param rssi Received signal strength in dBm * @param snr Signal to Noise ratio in dBm * @param len Length of data received, will be 0 for ACKs * @param data Data received, will be NULL for ACKs */ - void (*cb)(uint8_t port, bool data_pending, - int16_t rssi, int8_t snr, - uint8_t len, const uint8_t *data); + void (*cb)(uint8_t port, uint8_t flags, int16_t rssi, int8_t snr, uint8_t len, + const uint8_t *data); /** Node for callback list */ sys_snode_t node; }; @@ -372,6 +379,32 @@ void lorawan_get_payload_sizes(uint8_t *max_next_payload_size, */ int lorawan_set_region(enum lorawan_region region); +/** + * @brief Request for time according to DeviceTimeReq MAC cmd + * + * Append MAC DevTimeReq command. It will be processed on next send + * message or force sending empty message to request time immediately. + * + * @param force_request Immediately send an empty message to execute the request + * @return 0 if successful, negative errno otherwise + */ +int lorawan_request_device_time(bool force_request); + +/** + * @brief Retrieve the current time from LoRaWAN stack updated by + * DeviceTimeAns on MAC layer. + * + * This function uses the GPS epoch format, as used in all LoRaWAN services. + * + * The GPS epoch started on 1980-01-06T00:00:00Z, but has since diverged + * from UTC, as it does not consider corrections like leap seconds. + * + * @param gps_time Synchronized time in GPS epoch format truncated to 32-bit. + * + * @return 0 if successful, -EAGAIN if the clock is not yet synchronized. + */ +int lorawan_device_time_get(uint32_t *gps_time); + #ifdef CONFIG_LORAWAN_APP_CLOCK_SYNC /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/math/interpolation.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/math/interpolation.h new file mode 100644 index 00000000..044c8506 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/math/interpolation.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2024 Embeint Inc + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ZEPHYR_MATH_INTERPOLATION_H_ +#define ZEPHYR_INCLUDE_ZEPHYR_MATH_INTERPOLATION_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file + * @brief Provide linear interpolation functions + */ + +/** + * @brief Perform a linear interpolation across an arbitrary curve + * + * @note Result rounding occurs away from 0, e.g: + * 1.5 -> 2, -5.5 -> -6 + * + * @param x_axis Ascending list of X co-ordinates for @a y_axis data points + * @param y_axis Y co-ordinates for each X data point + * @param len Length of the @a x_axis and @a y_axis arrays + * @param x X co-ordinate to lookup + * + * @retval y_axis[0] if x < x_axis[0] + * @retval y_axis[len - 1] if x > x_axis[len - 1] + * @retval int32_t Linear interpolation between the two nearest @a y_axis values. + */ +static inline int32_t linear_interpolate(const int32_t *x_axis, const int32_t *y_axis, uint8_t len, + int32_t x) +{ + float rise, run, slope; + int32_t x_shifted; + uint8_t idx_low = 0; + + /* Handle out of bounds values */ + if (x <= x_axis[0]) { + return y_axis[0]; + } else if (x >= x_axis[len - 1]) { + return y_axis[len - 1]; + } + + /* Find the lower x axis bucket */ + while (x >= x_axis[idx_low + 1]) { + idx_low++; + } + + /* Shift input to origin */ + x_shifted = x - x_axis[idx_low]; + if (x_shifted == 0) { + return y_axis[idx_low]; + } + + /* Local slope */ + rise = y_axis[idx_low + 1] - y_axis[idx_low]; + run = x_axis[idx_low + 1] - x_axis[idx_low]; + slope = rise / run; + + /* Apply slope, undo origin shift and round */ + return roundf(y_axis[idx_low] + (slope * x_shifted)); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_ZEPHYR_MATH_INTERPOLATION_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit.h index 08da3df1..0d1e05f5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit.h @@ -1,280 +1,22 @@ /* - * Copyright (c) 2020 Linumiz + * Copyright (c) 2024 Vogl Electronic GmbH * * SPDX-License-Identifier: Apache-2.0 */ /** - * @brief hawkBit Firmware Over-the-Air for Zephyr Project. - * @defgroup hawkbit hawkBit Firmware Over-the-Air - * @ingroup third_party - * @{ + * @file + * @brief hawkBit legacy header file */ + #ifndef ZEPHYR_INCLUDE_MGMT_HAWKBIT_H_ #define ZEPHYR_INCLUDE_MGMT_HAWKBIT_H_ -#include - -#define HAWKBIT_JSON_URL "/default/controller/v1" - -/** - * @brief Response message from hawkBit. - * - * @details These messages are used to inform the server and the - * user about the process status of the hawkBit and also - * used to standardize the errors that may occur. - * - */ -enum hawkbit_response { - HAWKBIT_NETWORKING_ERROR, - HAWKBIT_UNCONFIRMED_IMAGE, - HAWKBIT_PERMISSION_ERROR, - HAWKBIT_METADATA_ERROR, - HAWKBIT_DOWNLOAD_ERROR, - HAWKBIT_OK, - HAWKBIT_UPDATE_INSTALLED, - HAWKBIT_NO_UPDATE, - HAWKBIT_CANCEL_UPDATE, - HAWKBIT_NOT_INITIALIZED, - HAWKBIT_PROBE_IN_PROGRESS, -}; - -/** - * @brief hawkBit configuration structure. - * - * @details This structure is used to store the hawkBit configuration - * settings. - */ -struct hawkbit_runtime_config { - char *server_addr; - uint16_t server_port; - char *auth_token; - sec_tag_t tls_tag; -}; - -/** - * @brief Callback to provide the custom data to the hawkBit server. - * - * @details This callback is used to provide the custom data to the hawkBit server. - * The custom data is used to provide the hawkBit server with the device specific - * data. - * - * @param device_id The device ID. - * @param buffer The buffer to store the json. - * @param buffer_size The size of the buffer. - */ -typedef int (*hawkbit_config_device_data_cb_handler_t)(const char *device_id, uint8_t *buffer, - const size_t buffer_size); - -/** - * @brief Set the custom data callback. - * - * @details This function is used to set the custom data callback. - * The callback is used to provide the custom data to the hawkBit server. - * - * @param cb The callback function. - * - * @retval 0 on success. - * @retval -EINVAL if the callback is NULL. - */ -int hawkbit_set_custom_data_cb(hawkbit_config_device_data_cb_handler_t cb); - -/** - * @brief Init the flash partition - * - * @retval 0 on success. - * @retval -errno if init fails. - */ -int hawkbit_init(void); - -/** - * @brief Runs hawkBit probe and hawkBit update automatically - * - * @details The hawkbit_autohandler handles the whole process - * in pre-determined time intervals. - */ -void hawkbit_autohandler(void); - -/** - * @brief The hawkBit probe verify if there is some update to be performed. - * - * @retval HAWKBIT_NETWORKING_ERROR fail to connect to the hawkBit server. - * @retval HAWKBIT_UNCONFIRMED_IMAGE image is unconfirmed. - * @retval HAWKBIT_PERMISSION_ERROR fail to get the permission to access the hawkBit server. - * @retval HAWKBIT_METADATA_ERROR fail to parse or to encode the metadata. - * @retval HAWKBIT_DOWNLOAD_ERROR fail while downloading the update package. - * @retval HAWKBIT_OK if the image was already updated. - * @retval HAWKBIT_UPDATE_INSTALLED if an update was installed. Reboot is required to apply it. - * @retval HAWKBIT_NO_UPDATE if no update was available. - * @retval HAWKBIT_CANCEL_UPDATE if the update was cancelled by the server. - * @retval HAWKBIT_NOT_INITIALIZED if hawkBit is not initialized. - * @retval HAWKBIT_PROBE_IN_PROGRESS if probe is currently running. - */ -enum hawkbit_response hawkbit_probe(void); - -/** - * @brief Request system to reboot. - */ -void hawkbit_reboot(void); - -/** - * @brief Callback to get the device identity. - * - * @param id Pointer to the buffer to store the device identity - * @param id_max_len The maximum length of the buffer - */ -typedef bool (*hawkbit_get_device_identity_cb_handler_t)(char *id, int id_max_len); - -/** - * @brief Set the device identity callback. - * - * @details This function is used to set a custom device identity callback. - * - * @param cb The callback function. - * - * @retval 0 on success. - * @retval -EINVAL if the callback is NULL. - */ -int hawkbit_set_device_identity_cb(hawkbit_get_device_identity_cb_handler_t cb); - -/** - * @brief Set the hawkBit server configuration settings. - * - * @param config Configuration settings to set. - * @retval 0 on success. - * @retval -EAGAIN if probe is currently running. - */ -int hawkbit_set_config(struct hawkbit_runtime_config *config); +#warning " is deprecated, include , \ + and instead." -/** - * @brief Get the hawkBit server configuration settings. - * - * @return Configuration settings. - */ -struct hawkbit_runtime_config hawkbit_get_config(void); - -/** - * @brief Set the hawkBit server address. - * - * @param addr_str Server address to set. - * @retval 0 on success. - * @retval -EAGAIN if probe is currently running. - */ -static inline int hawkbit_set_server_addr(char *addr_str) -{ - struct hawkbit_runtime_config set_config = { - .server_addr = addr_str, .server_port = 0, .auth_token = NULL, .tls_tag = 0}; - - return hawkbit_set_config(&set_config); -} - -/** - * @brief Set the hawkBit server port. - * - * @param port Server port to set. - * @retval 0 on success. - * @retval -EAGAIN if probe is currently running. - */ -static inline int hawkbit_set_server_port(uint16_t port) -{ - struct hawkbit_runtime_config set_config = { - .server_addr = NULL, .server_port = port, .auth_token = NULL, .tls_tag = 0}; - - return hawkbit_set_config(&set_config); -} - -/** - * @brief Set the hawkBit security token. - * - * @param token Security token to set. - * @retval 0 on success. - * @retval -EAGAIN if probe is currently running. - */ -static inline int hawkbit_set_ddi_security_token(char *token) -{ - struct hawkbit_runtime_config set_config = { - .server_addr = NULL, .server_port = 0, .auth_token = token, .tls_tag = 0}; - - return hawkbit_set_config(&set_config); -} - -/** - * @brief Set the hawkBit TLS tag - * - * @param tag TLS tag to set. - * @retval 0 on success. - * @retval -EAGAIN if probe is currently running. - */ -static inline int hawkbit_set_tls_tag(sec_tag_t tag) -{ - struct hawkbit_runtime_config set_config = { - .server_addr = NULL, .server_port = 0, .auth_token = NULL, .tls_tag = tag}; - - return hawkbit_set_config(&set_config); -} - -/** - * @brief Get the hawkBit server address. - * - * @return Server address. - */ -static inline char *hawkbit_get_server_addr(void) -{ - return hawkbit_get_config().server_addr; -} - -/** - * @brief Get the hawkBit server port. - * - * @return Server port. - */ -static inline uint16_t hawkbit_get_server_port(void) -{ - return hawkbit_get_config().server_port; -} - -/** - * @brief Get the hawkBit security token. - * - * @return Security token. - */ -static inline char *hawkbit_get_ddi_security_token(void) -{ - return hawkbit_get_config().auth_token; -} - -/** - * @brief Get the hawkBit TLS tag. - * - * @return TLS tag. - */ -static inline sec_tag_t hawkbit_get_tls_tag(void) -{ - return hawkbit_get_config().tls_tag; -} - -/** - * @brief Get the hawkBit action id. - * - * @return Action id. - -*/ -int32_t hawkbit_get_action_id(void); - -/** - * @brief Resets the hawkBit action id, that is saved in settings. - * - * @details This should be done after changing the hawkBit server. - * - * @retval 0 on success. - * @retval -EAGAIN if probe is currently running. - * @retval -EIO if the action id could not be reset. - * - */ -int hawkbit_reset_action_id(void); - -/** - * @} - */ +#include +#include +#include -#endif /* _HAWKBIT_H_ */ +#endif /* ZEPHYR_INCLUDE_MGMT_HAWKBIT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/autohandler.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/autohandler.h new file mode 100644 index 00000000..3fbe7f15 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/autohandler.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024 Vogl Electronic GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief hawkBit autohandler header file + */ + +/** + * @brief hawkBit autohandler API. + * @defgroup hawkbit_autohandler hawkBit autohandler API + * @ingroup hawkbit + * @{ + */ + +#ifndef ZEPHYR_INCLUDE_MGMT_HAWKBIT_AUTOHANDLER_H_ +#define ZEPHYR_INCLUDE_MGMT_HAWKBIT_AUTOHANDLER_H_ + +#include + +/** + * @brief Runs hawkBit probe and hawkBit update automatically + * + * @details The hawkbit_autohandler handles the whole process + * in pre-determined time intervals. + * + * @param auto_reschedule If true, the handler will reschedule itself + */ +void hawkbit_autohandler(bool auto_reschedule); + +/** + * @brief Wait for the autohandler to finish. + * + * @param events Set of desired events on which to wait. Set to ::UINT32_MAX to wait for the + * autohandler to finish one run, or BIT() together with a value from + * ::hawkbit_response to wait for a specific event. + * @param timeout Waiting period for the desired set of events or one of the + * special values ::K_NO_WAIT and ::K_FOREVER. + * + * @return A value from ::hawkbit_response. + */ +enum hawkbit_response hawkbit_autohandler_wait(uint32_t events, k_timeout_t timeout); + +/** + * @brief Cancel the run of the hawkBit autohandler. + * + * @return a value from k_work_cancel_delayable(). + */ +int hawkbit_autohandler_cancel(void); + +/** + * @brief Set the delay for the next run of the autohandler. + * + * @details This function will only delay the next run of the autohandler. The delay will not + * persist after the autohandler runs. + * + * @param timeout The delay to set. + * @param if_bigger If true, the delay will be set only if the new delay is bigger than the current + * one. + * + * @retval 0 if @a if_bigger was true and the current delay was bigger than the new one. + * @retval otherwise, a value from k_work_reschedule(). + */ +int hawkbit_autohandler_set_delay(k_timeout_t timeout, bool if_bigger); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_MGMT_HAWKBIT_AUTOHANDLER_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/config.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/config.h new file mode 100644 index 00000000..c02212bf --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/config.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2024 Vogl Electronic GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief hawkBit configuration header file + */ + +/** + * @brief hawkBit configuration API. + * @defgroup hawkbit_config hawkBit configuration API + * @ingroup hawkbit + * @{ + */ + +#ifndef ZEPHYR_INCLUDE_MGMT_HAWKBIT_CONFIG_H_ +#define ZEPHYR_INCLUDE_MGMT_HAWKBIT_CONFIG_H_ + +#include +#include + +/** + * @brief hawkBit configuration structure. + * + * @details This structure is used to store the hawkBit configuration + * settings. + */ +struct hawkbit_runtime_config { + /** Server address */ + char *server_addr; + /** Server port */ + uint16_t server_port; + /** Security token */ + char *auth_token; + /** TLS tag */ + sec_tag_t tls_tag; +}; + +/** + * @brief Set the hawkBit server configuration settings. + * + * @param config Configuration settings to set. + * @retval 0 on success. + * @retval -EAGAIN if probe is currently running. + */ +int hawkbit_set_config(struct hawkbit_runtime_config *config); + +/** + * @brief Get the hawkBit server configuration settings. + * + * @return Configuration settings. + */ +struct hawkbit_runtime_config hawkbit_get_config(void); + +/** + * @brief Set the hawkBit server address. + * + * @param addr_str Server address to set. + * @retval 0 on success. + * @retval -EAGAIN if probe is currently running. + */ +static inline int hawkbit_set_server_addr(char *addr_str) +{ + struct hawkbit_runtime_config set_config = { + .server_addr = addr_str, + .server_port = 0, + .auth_token = NULL, + .tls_tag = 0, + }; + + return hawkbit_set_config(&set_config); +} + +/** + * @brief Set the hawkBit server port. + * + * @param port Server port to set. + * @retval 0 on success. + * @retval -EAGAIN if probe is currently running. + */ +static inline int hawkbit_set_server_port(uint16_t port) +{ + struct hawkbit_runtime_config set_config = { + .server_addr = NULL, + .server_port = port, + .auth_token = NULL, + .tls_tag = 0, + }; + + return hawkbit_set_config(&set_config); +} + +/** + * @brief Set the hawkBit security token. + * + * @param token Security token to set. + * @retval 0 on success. + * @retval -EAGAIN if probe is currently running. + */ +static inline int hawkbit_set_ddi_security_token(char *token) +{ + struct hawkbit_runtime_config set_config = { + .server_addr = NULL, + .server_port = 0, + .auth_token = token, + .tls_tag = 0, + }; + + return hawkbit_set_config(&set_config); +} + +/** + * @brief Set the hawkBit TLS tag + * + * @param tag TLS tag to set. + * @retval 0 on success. + * @retval -EAGAIN if probe is currently running. + */ +static inline int hawkbit_set_tls_tag(sec_tag_t tag) +{ + struct hawkbit_runtime_config set_config = { + .server_addr = NULL, + .server_port = 0, + .auth_token = NULL, + .tls_tag = tag, + }; + + return hawkbit_set_config(&set_config); +} + +/** + * @brief Get the hawkBit server address. + * + * @return Server address. + */ +static inline char *hawkbit_get_server_addr(void) +{ + return hawkbit_get_config().server_addr; +} + +/** + * @brief Get the hawkBit server port. + * + * @return Server port. + */ +static inline uint16_t hawkbit_get_server_port(void) +{ + return hawkbit_get_config().server_port; +} + +/** + * @brief Get the hawkBit security token. + * + * @return Security token. + */ +static inline char *hawkbit_get_ddi_security_token(void) +{ + return hawkbit_get_config().auth_token; +} + +/** + * @brief Get the hawkBit TLS tag. + * + * @return TLS tag. + */ +static inline sec_tag_t hawkbit_get_tls_tag(void) +{ + return hawkbit_get_config().tls_tag; +} + +/** + * @brief Get the hawkBit action id. + * + * @return Action id. + */ +int32_t hawkbit_get_action_id(void); + +/** + * @brief Get the hawkBit poll interval. + * + * @return Poll interval. + */ +uint32_t hawkbit_get_poll_interval(void); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_MGMT_HAWKBIT_CONFIG_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/hawkbit.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/hawkbit.h new file mode 100644 index 00000000..6ef59521 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/hawkbit/hawkbit.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2020 Linumiz + * Copyright (c) 2024 Vogl Electronic GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief hawkBit main header file + */ + +/** + * @brief hawkBit Firmware Over-the-Air for Zephyr Project. + * @defgroup hawkbit hawkBit Firmware Over-the-Air + * @ingroup third_party + * @{ + */ + +#ifndef ZEPHYR_INCLUDE_MGMT_HAWKBIT_HAWKBIT_H_ +#define ZEPHYR_INCLUDE_MGMT_HAWKBIT_HAWKBIT_H_ + +#include + +/** + * @brief Response message from hawkBit. + * + * @details These messages are used to inform the server and the + * user about the process status of the hawkBit and also + * used to standardize the errors that may occur. + * + */ +enum hawkbit_response { + /** matching events were not received within the specified time */ + HAWKBIT_NO_RESPONSE, + /** fail to connect to the hawkBit server */ + HAWKBIT_NETWORKING_ERROR, + /** image is unconfirmed */ + HAWKBIT_UNCONFIRMED_IMAGE, + /** fail to get the permission to access the hawkBit server */ + HAWKBIT_PERMISSION_ERROR, + /** fail to parse or to encode the metadata */ + HAWKBIT_METADATA_ERROR, + /** fail while downloading the update package */ + HAWKBIT_DOWNLOAD_ERROR, + /** image was already updated */ + HAWKBIT_OK, + /** an update was installed. Reboot is required to apply it */ + HAWKBIT_UPDATE_INSTALLED, + /** no update was available */ + HAWKBIT_NO_UPDATE, + /** update was cancelled by the server */ + HAWKBIT_CANCEL_UPDATE, + /** hawkBit is not initialized */ + HAWKBIT_NOT_INITIALIZED, + /** probe is currently running */ + HAWKBIT_PROBE_IN_PROGRESS, +}; + +/** + * @brief Callback to provide the custom data to the hawkBit server. + * + * @details This callback is used to provide the custom data to the hawkBit server. + * The custom data is used to provide the hawkBit server with the device specific + * data. + * + * @param device_id The device ID. + * @param buffer The buffer to store the json. + * @param buffer_size The size of the buffer. + */ +typedef int (*hawkbit_config_device_data_cb_handler_t)(const char *device_id, uint8_t *buffer, + const size_t buffer_size); + +/** + * @brief Set the custom data callback. + * + * @details This function is used to set the custom data callback. + * The callback is used to provide the custom data to the hawkBit server. + * + * @param cb The callback function. + * + * @retval 0 on success. + * @retval -EINVAL if the callback is NULL. + */ +int hawkbit_set_custom_data_cb(hawkbit_config_device_data_cb_handler_t cb); + +/** + * @brief Init the flash partition + * + * @retval 0 on success. + * @retval -errno if init fails. + */ +int hawkbit_init(void); + +/** + * @brief The hawkBit probe verify if there is some update to be performed. + * + * @return A value from ::hawkbit_response. + */ +enum hawkbit_response hawkbit_probe(void); + +/** + * @brief Request system to reboot. + */ +void hawkbit_reboot(void); + +/** + * @brief Callback to get the device identity. + * + * @param id Pointer to the buffer to store the device identity + * @param id_max_len The maximum length of the buffer + */ +typedef bool (*hawkbit_get_device_identity_cb_handler_t)(char *id, int id_max_len); + +/** + * @brief Set the device identity callback. + * + * @details This function is used to set a custom device identity callback. + * + * @param cb The callback function. + * + * @retval 0 on success. + * @retval -EINVAL if the callback is NULL. + */ +int hawkbit_set_device_identity_cb(hawkbit_get_device_identity_cb_handler_t cb); + +/** + * @brief Resets the hawkBit action id, that is saved in settings. + * + * @details This should be done after changing the hawkBit server. + * + * @retval 0 on success. + * @retval -EAGAIN if probe is currently running. + * @retval -EIO if the action id could not be reset. + * + */ +int hawkbit_reset_action_id(void); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_MGMT_HAWKBIT_HAWKBIT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/enum_mgmt/enum_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/enum_mgmt/enum_mgmt.h new file mode 100644 index 00000000..2eea2ee2 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/enum_mgmt/enum_mgmt.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef H_ENUM_MGMT_ +#define H_ENUM_MGMT_ + +/** + * @brief MCUmgr enum_mgmt API + * @defgroup mcumgr_enum_mgmt MCUmgr enum_mgmt API + * @ingroup mcumgr + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Command IDs for enumeration management group. + */ +#define ENUM_MGMT_ID_COUNT 0 +#define ENUM_MGMT_ID_LIST 1 +#define ENUM_MGMT_ID_SINGLE 2 +#define ENUM_MGMT_ID_DETAILS 3 + +/** + * Command result codes for enumeration management group. + */ +enum enum_mgmt_err_code_t { + /** No error, this is implied if there is no ret value in the response */ + ENUM_MGMT_ERR_OK = 0, + + /** Unknown error occurred. */ + ENUM_MGMT_ERR_UNKNOWN, + + /** Too many entries were provided. */ + ENUM_MGMT_ERR_TOO_MANY_GROUP_ENTRIES, + + /** Insufficient heap memory to store entry data. */ + ENUM_MGMT_ERR_INSUFFICIENT_HEAP_FOR_ENTRIES, + + /** Provided index is larger than the number of supported grouped. */ + ENUM_MGMT_ERR_INDEX_TOO_LARGE, +}; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* H_ENUM_MGMT_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/enum_mgmt/enum_mgmt_callbacks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/enum_mgmt/enum_mgmt_callbacks.h new file mode 100644 index 00000000..638a69e9 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/enum_mgmt/enum_mgmt_callbacks.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef H_MCUMGR_ENUM_MGMT_CALLBACKS_ +#define H_MCUMGR_ENUM_MGMT_CALLBACKS_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief MCUmgr enum_mgmt callback API + * @defgroup mcumgr_callback_api_enum_mgmt MCUmgr enum_mgmt callback API + * @ingroup mcumgr_callback_api + * @{ + */ + +/** + * Structure provided in the #MGMT_EVT_OP_ENUM_MGMT_DETAILS notification callback: This callback + * function is called once per command group when the detail command is used, it can be used to + * return additional information/fields in the response. + */ +struct enum_mgmt_detail_output { + /** The group that is currently being enumerated. */ + const struct mgmt_group *group; + + /** + * The zcbor encoder which is currently being used to output group information, additional + * fields to the group can be added using this. + */ + zcbor_state_t *zse; +}; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h index 82e642c7..49dffc6b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018-2021 mcumgr authors - * Copyright (c) 2022-2023 Nordic Semiconductor ASA + * Copyright (c) 2022-2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -56,6 +56,7 @@ extern "C" { #define IMG_MGMT_ID_CORELIST 3 #define IMG_MGMT_ID_CORELOAD 4 #define IMG_MGMT_ID_ERASE 5 +#define IMG_MGMT_ID_SLOT_INFO 6 /** * Command result codes for image management group. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h index a9e05b5d..5c479fd9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h @@ -8,6 +8,10 @@ #ifndef H_MCUMGR_IMG_MGMT_CALLBACKS_ #define H_MCUMGR_IMG_MGMT_CALLBACKS_ +#include +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -37,6 +41,58 @@ struct img_mgmt_upload_check { struct img_mgmt_upload_req *req; }; +/** + * Structure provided in the #MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE notification callback: This + * callback function is used to allow applications or modules append custom fields to the image + * slot state response. + */ +struct img_mgmt_state_slot_encode { + bool *ok; + zcbor_state_t *zse; + const uint32_t slot; + const char *version; + const uint8_t *hash; + const int flags; +}; + +/** + * Structure provided in the #MGMT_EVT_OP_IMG_MGMT_SLOT_INFO_IMAGE notification callback: This + * callback function is called once per image when the slot info command is used, it can be used + * to return additional information/fields in the response. + */ +struct img_mgmt_slot_info_image { + /** The image that is currently being enumerated. */ + const uint8_t image; + + /** + * The zcbor encoder which is currently being used to output information, additional fields + * can be added using this. + */ + zcbor_state_t *zse; +}; + +/** + * Structure provided in the #MGMT_EVT_OP_IMG_MGMT_SLOT_INFO_SLOT notification callback: This + * callback function is called once per slot per image when the slot info command is used, it can + * be used to return additional information/fields in the response. + */ +struct img_mgmt_slot_info_slot { + /** The image that is currently being enumerated. */ + const uint8_t image; + + /** The slot that is currently being enumerated. */ + const uint8_t slot; + + /** Flash area of the slot that is current being enumerated. */ + const struct flash_area *fa; + + /** + * The zcbor encoder which is currently being used to output information, additional fields + * can be added using this. + */ + zcbor_state_t *zse; +}; + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h index 07ff7039..c9f7259f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h @@ -28,6 +28,30 @@ struct os_mgmt_reset_data { bool force; }; +/** + * Structure provided in the #MGMT_EVT_OP_OS_MGMT_BOOTLOADER_INFO notification callback: This + * callback function is used to add new fields to the bootloader info response. + */ +struct os_mgmt_bootloader_info_data { + /** + * The zcbor encoder which is currently being used to output group information, additional + * fields to the group can be added using this. + */ + zcbor_state_t *zse; + + /** Contains the number of decoded parameters. */ + const size_t *decoded; + + /** Contains the value of the query parameter. */ + struct zcbor_string *query; + + /** + * Must be set to true to indicate a response has been added, otherwise will return the + * #OS_MGMT_ERR_QUERY_YIELDS_NO_ANSWER error. + */ + bool *has_output; +}; + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h index 194c3846..e3cd408e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h @@ -27,6 +27,10 @@ #include #endif +#ifdef CONFIG_MCUMGR_GRP_ENUM +#include +#endif + #ifdef __cplusplus extern "C" { #endif @@ -118,6 +122,7 @@ enum mgmt_cb_groups { MGMT_EVT_GRP_IMG, MGMT_EVT_GRP_FS, MGMT_EVT_GRP_SETTINGS, + MGMT_EVT_GRP_ENUM, MGMT_EVT_GRP_USER_CUSTOM_START = MGMT_GROUP_ID_PERUSER, }; @@ -180,6 +185,15 @@ enum img_mgmt_group_events { /** Callback when an image write command has finished writing to flash. */ MGMT_EVT_OP_IMG_MGMT_DFU_CHUNK_WRITE_COMPLETE = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 5), + /** Callback when an image slot's state is encoded for a response. */ + MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 6), + + /** Callback when an slot list command outputs fields for an image. */ + MGMT_EVT_OP_IMG_MGMT_SLOT_INFO_IMAGE = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 7), + + /** Callback when an slot list command outputs fields for a slot of an image. */ + MGMT_EVT_OP_IMG_MGMT_SLOT_INFO_SLOT = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 8), + /** Used to enable all img_mgmt_group events. */ MGMT_EVT_OP_IMG_MGMT_ALL = MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_IMG), }; @@ -198,10 +212,16 @@ enum os_mgmt_group_events { MGMT_EVT_OP_OS_MGMT_INFO_APPEND = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 2), /** Callback when a datetime get command has been received. */ - MGMT_EVT_OP_OS_MGMT_DATETIME_GET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 3), + MGMT_EVT_OP_OS_MGMT_DATETIME_GET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 3), /** Callback when a datetime set command has been received, data is struct rtc_time(). */ - MGMT_EVT_OP_OS_MGMT_DATETIME_SET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 4), + MGMT_EVT_OP_OS_MGMT_DATETIME_SET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 4), + + /** + * Callback when a bootloader info command has been received, data is + * os_mgmt_bootloader_info_data. + */ + MGMT_EVT_OP_OS_MGMT_BOOTLOADER_INFO = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 5), /** Used to enable all os_mgmt_group events. */ MGMT_EVT_OP_OS_MGMT_ALL = MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_OS), @@ -218,6 +238,17 @@ enum settings_mgmt_group_events { MGMT_EVT_OP_SETTINGS_MGMT_ALL = MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_SETTINGS), }; +/** + * MGMT event opcodes for enumeration management group. + */ +enum enum_mgmt_group_events { + /** Callback when fetching details on supported command groups. */ + MGMT_EVT_OP_ENUM_MGMT_DETAILS = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_ENUM, 0), + + /** Used to enable all enum_mgmt_group events. */ + MGMT_EVT_OP_ENUM_MGMT_ALL = MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_ENUM), +}; + /** * MGMT callback struct */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h index a247a1c2..23960154 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018-2021 mcumgr authors - * Copyright (c) 2022-2023 Nordic Semiconductor ASA + * Copyright (c) 2022-2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,6 +104,11 @@ struct mgmt_group { /** Should be true when using user defined payload */ bool custom_payload; #endif + +#if IS_ENABLED(CONFIG_MCUMGR_GRP_ENUM_DETAILS_NAME) + /** NULL-terminated name of group */ + const char *mg_group_name; +#endif }; /** @@ -120,6 +125,24 @@ void mgmt_register_group(struct mgmt_group *group); */ void mgmt_unregister_group(struct mgmt_group *group); +/** + * @brief Group iteration callback + * + * @param group Group + * @param user_data User-supplied data + * + * @return true to continue with the foreach callback, false to abort + */ +typedef bool (*mgmt_groups_cb_t)(const struct mgmt_group *group, void *user_data); + +/** + * @brief Iterate over groups + * + * @param user_cb User callback + * @param user_data User-supplied data + */ +void mgmt_groups_foreach(mgmt_groups_cb_t user_cb, void *user_data); + /** * @brief Finds a registered command handler. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt_defines.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt_defines.h index 5dafc8f8..f1bb7178 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt_defines.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/mgmt/mgmt_defines.h @@ -77,6 +77,9 @@ enum mcumgr_group_t { /** Shell management group, used for executing shell commands */ MGMT_GROUP_ID_SHELL, + /** Enumeration management group, used for listing supported command groups */ + MGMT_GROUP_ID_ENUM, + /** User groups defined from 64 onwards */ MGMT_GROUP_ID_PERUSER = 64, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp.h index c72461a9..16d7ada8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp.h @@ -26,7 +26,7 @@ #ifndef H_SMP_ #define H_SMP_ -#include +#include #include #include @@ -121,12 +121,6 @@ int smp_process_request_packet(struct smp_streamer *streamer, void *req); */ bool smp_add_cmd_err(zcbor_state_t *zse, uint16_t group, uint16_t ret); -/** @deprecated Deprecated after Zephyr 3.4, use smp_add_cmd_err() instead */ -__deprecated inline bool smp_add_cmd_ret(zcbor_state_t *zse, uint16_t group, uint16_t ret) -{ - return smp_add_cmd_err(zse, group, ret); -} - #if defined(CONFIG_MCUMGR_SMP_SUPPORT_ORIGINAL_PROTOCOL) /** @typedef smp_translate_error_fn * @brief Translates a SMP version 2 error response to a legacy SMP version 1 error code. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp_client.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp_client.h index 2e0eee2c..35685fd9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp_client.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/smp/smp_client.h @@ -8,7 +8,7 @@ #define H_SMP_CLIENT_ #include -#include +#include #include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp.h index d8cec687..38aa1b0e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp.h @@ -148,6 +148,8 @@ enum smp_transport_type { SMP_UDP_IPV4_TRANSPORT, /** SMP UDP IPv6 */ SMP_UDP_IPV6_TRANSPORT, + /** SMP LoRaWAN */ + SMP_LORAWAN_TRANSPORT, /** SMP user defined type */ SMP_USER_DEFINED_TRANSPORT }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_bt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_bt.h index 0aff0510..501cd658 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_bt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_bt.h @@ -11,6 +11,7 @@ #ifndef ZEPHYR_INCLUDE_MGMT_SMP_BT_H_ #define ZEPHYR_INCLUDE_MGMT_SMP_BT_H_ +#include #include struct bt_conn; @@ -18,6 +19,24 @@ struct bt_conn; extern "C" { #endif +/** SMP service UUID value. */ +#define SMP_BT_SVC_UUID_VAL \ + BT_UUID_128_ENCODE(0x8d53dc1d, 0x1db7, 0x4cd3, 0x868b, 0x8a527460aa84) + +/** SMP service UUID. */ +#define SMP_BT_SVC_UUID \ + BT_UUID_DECLARE_128(SMP_BT_SVC_UUID_VAL) + +/** SMP characteristic UUID value. */ +#define SMP_BT_CHR_UUID_VAL \ + BT_UUID_128_ENCODE(0xda2e7828, 0xfbce, 0x4e01, 0xae9e, 0x261174997c48) + +/** SMP characteristic UUID + * Used for both requests and responses. + */ +#define SMP_BT_CHR_UUID \ + BT_UUID_DECLARE_128(SMP_BT_CHR_UUID_VAL) + /** * @brief Registers the SMP Bluetooth service. Should only be called if the Bluetooth * transport has been unregistered by calling smp_bt_unregister(). diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_dummy.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_dummy.h index 02e974ea..5247b8e7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_dummy.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/mcumgr/transport/smp_dummy.h @@ -12,7 +12,7 @@ #define ZEPHYR_INCLUDE_MGMT_MCUMGR_TRANSPORT_DUMMY_H_ #include -#include +#include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/osdp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/osdp.h index b73314ae..29940ff0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/osdp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/mgmt/osdp.h @@ -9,8 +9,8 @@ * @brief Open Supervised Device Protocol (OSDP) public API header file. */ -#ifndef _OSDP_H_ -#define _OSDP_H_ +#ifndef ZEPHYR_INCLUDE_MGMT_OSDP_H_ +#define ZEPHYR_INCLUDE_MGMT_OSDP_H_ #include #include @@ -480,4 +480,4 @@ uint32_t osdp_get_sc_status_mask(void); } #endif -#endif /* _OSDP_H_ */ +#endif /* ZEPHYR_INCLUDE_MGMT_OSDP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/misc/lorem_ipsum.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/misc/lorem_ipsum.h new file mode 100644 index 00000000..b85e0527 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/misc/lorem_ipsum.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015 Intel Corporation. + * Copyright (c) 2024 Tenstorrent AI ULC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_MISC_LOREM_IPSUM_H_ +#define ZEPHYR_MISC_LOREM_IPSUM_H_ + +#include + +/* + * N.B. These strings are generally only used for tests and samples. They are not part of any + * official Zephyr API, but were moved to reduce duplication. + */ + +/* Generated by http://www.lipsum.com/ + * 1 paragraph, 69 words, 445 bytes of Lorem Ipsum + */ +#define LOREM_IPSUM_SHORT \ + "Lorem ipsum dolor sit amet, consectetur adipiscing elit, " \ + "sed do eiusmod tempor incididunt ut labore et dolore magna " \ + "aliqua. Ut enim ad minim veniam, quis nostrud exercitation " \ + "ullamco laboris nisi ut aliquip ex ea commodo consequat. Duis " \ + "aute irure dolor in reprehenderit in voluptate velit esse " \ + "cillum dolore eu fugiat nulla pariatur. Excepteur sint " \ + "occaecat cupidatat non proident, sunt in culpa qui officia " \ + "deserunt mollit anim id est laborum." + +#define LOREM_IPSUM_SHORT_STRLEN 445 +BUILD_ASSERT(sizeof(LOREM_IPSUM_SHORT) == LOREM_IPSUM_SHORT_STRLEN + 1); + +/* Generated by http://www.lipsum.com/ + * 2 paragraphs, 173 words, 1160 bytes of Lorem Ipsum + */ +#define LOREM_IPSUM \ + "Lorem ipsum dolor sit amet, consectetur adipiscing elit. Vivamus a varius sapien. " \ + "Suspendisse interdum nulla et enim elementum faucibus. Vestibulum nec est libero. Duis " \ + "leo orci, tincidunt a interdum ut, porttitor ac arcu. Etiam porttitor pretium nibh, non " \ + "laoreet nisl vulputate vitae. Vestibulum sit amet odio sit amet nibh faucibus mattis " \ + "eget at ex. Nam non arcu vitae nisi congue eleifend. Suspendisse sagittis, leo at " \ + "blandit semper, arcu neque tristique dolor, eu consequat urna quam non tortor. " \ + "Suspendisse ut ullamcorper lectus. Nullam ut accumsan lacus, sed iaculis leo. " \ + "Suspendisse potenti. Duis ullamcorper velit tellus, ac dictum tellus ultricies quis." \ + "\n" \ + "Curabitur tellus eros, congue a sem et, mattis fermentum velit. Donec sollicitudin " \ + "faucibus enim eu vehicula. Aliquam pulvinar lectus et finibus laoreet. Praesent at " \ + "tempor ex. Aenean blandit nunc viverra enim vulputate, et dictum turpis elementum. " \ + "Donec porttitor in dolor a ultricies. Cras neque ipsum, blandit sed varius at, semper " \ + "quis justo. Meanness ac metus ex. Pellentesque eu tortor eget nisl tempor pretium. " \ + "Donec elit enim, ultrices sit amet est vitae, sollicitudin bibendum egestas." + +#define LOREM_IPSUM_STRLEN 1160 +BUILD_ASSERT(sizeof(LOREM_IPSUM) == LOREM_IPSUM_STRLEN + 1); + +#endif /* ZEPHYR_MISC_LOREM_IPSUM_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/cmux.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/cmux.h index 3d655db0..f1fa0bee 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/cmux.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/cmux.h @@ -111,7 +111,7 @@ struct modem_cmux_dlci { }; struct modem_cmux_frame { - uint16_t dlci_address; + uint8_t dlci_address; bool cr; bool pf; uint8_t type; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/pipe.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/pipe.h index 9b195692..b91dfb50 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/pipe.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/modem/pipe.h @@ -63,7 +63,7 @@ struct modem_pipe_api { struct modem_pipe { void *data; - struct modem_pipe_api *api; + const struct modem_pipe_api *api; modem_pipe_api_callback callback; void *user_data; struct k_spinlock spinlock; @@ -77,7 +77,7 @@ struct modem_pipe { * @param data Pipe data to bind to pipe instance * @param api Pipe API implementation to bind to pipe instance */ -void modem_pipe_init(struct modem_pipe *pipe, void *data, struct modem_pipe_api *api); +void modem_pipe_init(struct modem_pipe *pipe, void *data, const struct modem_pipe_api *api); /** * @endcond @@ -87,6 +87,7 @@ void modem_pipe_init(struct modem_pipe *pipe, void *data, struct modem_pipe_api * @brief Open pipe * * @param pipe Pipe instance + * @param timeout Timeout waiting for pipe to open * * @retval 0 if pipe was successfully opened or was already open * @retval -errno code otherwise @@ -95,7 +96,7 @@ void modem_pipe_init(struct modem_pipe *pipe, void *data, struct modem_pipe_api * It may block the calling thread, which in the case of the system workqueue * can result in a deadlock until this call times out waiting for the pipe to be open. */ -int modem_pipe_open(struct modem_pipe *pipe); +int modem_pipe_open(struct modem_pipe *pipe, k_timeout_t timeout); /** * @brief Open pipe asynchronously @@ -163,6 +164,7 @@ void modem_pipe_release(struct modem_pipe *pipe); * @brief Close pipe * * @param pipe Pipe instance + * @param timeout Timeout waiting for pipe to close * * @retval 0 if pipe open was called closed or pipe was already closed * @retval -errno code otherwise @@ -171,7 +173,7 @@ void modem_pipe_release(struct modem_pipe *pipe); * It may block the calling thread, which in the case of the system workqueue * can result in a deadlock until this call times out waiting for the pipe to be closed. */ -int modem_pipe_close(struct modem_pipe *pipe); +int modem_pipe_close(struct modem_pipe *pipe, k_timeout_t timeout); /** * @brief Close pipe asynchronously diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/multi_heap/shared_multi_heap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/multi_heap/shared_multi_heap.h index a9cdf120..652ecb5e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/multi_heap/shared_multi_heap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/multi_heap/shared_multi_heap.h @@ -73,6 +73,9 @@ enum shared_multi_heap_attr { /** non-cacheable */ SMH_REG_ATTR_NON_CACHEABLE, + /** external Memory */ + SMH_REG_ATTR_EXTERNAL, + /** must be the last item */ SMH_REG_ATTR_NUM, }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/buf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/buf.h index 3a472d32..c537c030 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/buf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/buf.h @@ -1,2737 +1,14 @@ -/** @file - * @brief Buffer management. - */ - /* * Copyright (c) 2015 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_NET_BUF_H_ -#define ZEPHYR_INCLUDE_NET_BUF_H_ - -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Network buffer library - * @defgroup net_buf Network Buffer Library - * @ingroup networking - * @{ - */ - -/* Alignment needed for various parts of the buffer definition */ -#if CONFIG_NET_BUF_ALIGNMENT == 0 -#define __net_buf_align __aligned(sizeof(void *)) -#else -#define __net_buf_align __aligned(CONFIG_NET_BUF_ALIGNMENT) -#endif - -/** - * @brief Define a net_buf_simple stack variable. - * - * This is a helper macro which is used to define a net_buf_simple object - * on the stack. - * - * @param _name Name of the net_buf_simple object. - * @param _size Maximum data storage for the buffer. - */ -#define NET_BUF_SIMPLE_DEFINE(_name, _size) \ - uint8_t net_buf_data_##_name[_size]; \ - struct net_buf_simple _name = { \ - .data = net_buf_data_##_name, \ - .len = 0, \ - .size = _size, \ - .__buf = net_buf_data_##_name, \ - } - -/** - * - * @brief Define a static net_buf_simple variable. - * - * This is a helper macro which is used to define a static net_buf_simple - * object. - * - * @param _name Name of the net_buf_simple object. - * @param _size Maximum data storage for the buffer. - */ -#define NET_BUF_SIMPLE_DEFINE_STATIC(_name, _size) \ - static __noinit uint8_t net_buf_data_##_name[_size]; \ - static struct net_buf_simple _name = { \ - .data = net_buf_data_##_name, \ - .len = 0, \ - .size = _size, \ - .__buf = net_buf_data_##_name, \ - } - -/** - * @brief Simple network buffer representation. - * - * This is a simpler variant of the net_buf object (in fact net_buf uses - * net_buf_simple internally). It doesn't provide any kind of reference - * counting, user data, dynamic allocation, or in general the ability to - * pass through kernel objects such as FIFOs. - * - * The main use of this is for scenarios where the meta-data of the normal - * net_buf isn't needed and causes too much overhead. This could be e.g. - * when the buffer only needs to be allocated on the stack or when the - * access to and lifetime of the buffer is well controlled and constrained. - */ -struct net_buf_simple { - /** Pointer to the start of data in the buffer. */ - uint8_t *data; - - /** - * Length of the data behind the data pointer. - * - * To determine the max length, use net_buf_simple_max_len(), not #size! - */ - uint16_t len; - - /** Amount of data that net_buf_simple#__buf can store. */ - uint16_t size; - - /** Start of the data storage. Not to be accessed directly - * (the data pointer should be used instead). - */ - uint8_t *__buf; -}; - -/** - * - * @brief Define a net_buf_simple stack variable and get a pointer to it. - * - * This is a helper macro which is used to define a net_buf_simple object on - * the stack and the get a pointer to it as follows: - * - * struct net_buf_simple *my_buf = NET_BUF_SIMPLE(10); - * - * After creating the object it needs to be initialized by calling - * net_buf_simple_init(). - * - * @param _size Maximum data storage for the buffer. - * - * @return Pointer to stack-allocated net_buf_simple object. - */ -#define NET_BUF_SIMPLE(_size) \ - ((struct net_buf_simple *)(&(struct { \ - struct net_buf_simple buf; \ - uint8_t data[_size]; \ - }) { \ - .buf.size = _size, \ - })) - -/** - * @brief Initialize a net_buf_simple object. - * - * This needs to be called after creating a net_buf_simple object using - * the NET_BUF_SIMPLE macro. - * - * @param buf Buffer to initialize. - * @param reserve_head Headroom to reserve. - */ -static inline void net_buf_simple_init(struct net_buf_simple *buf, - size_t reserve_head) -{ - if (!buf->__buf) { - buf->__buf = (uint8_t *)buf + sizeof(*buf); - } - - buf->data = buf->__buf + reserve_head; - buf->len = 0U; -} - -/** - * @brief Initialize a net_buf_simple object with data. - * - * Initialized buffer object with external data. - * - * @param buf Buffer to initialize. - * @param data External data pointer - * @param size Amount of data the pointed data buffer if able to fit. - */ -void net_buf_simple_init_with_data(struct net_buf_simple *buf, - void *data, size_t size); - -/** - * @brief Reset buffer - * - * Reset buffer data so it can be reused for other purposes. - * - * @param buf Buffer to reset. - */ -static inline void net_buf_simple_reset(struct net_buf_simple *buf) -{ - buf->len = 0U; - buf->data = buf->__buf; -} - -/** - * Clone buffer state, using the same data buffer. - * - * Initializes a buffer to point to the same data as an existing buffer. - * Allows operations on the same data without altering the length and - * offset of the original. - * - * @param original Buffer to clone. - * @param clone The new clone. - */ -void net_buf_simple_clone(const struct net_buf_simple *original, - struct net_buf_simple *clone); - -/** - * @brief Prepare data to be added at the end of the buffer - * - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param len Number of bytes to increment the length with. - * - * @return The original tail of the buffer. - */ -void *net_buf_simple_add(struct net_buf_simple *buf, size_t len); - -/** - * @brief Copy given number of bytes from memory to the end of the buffer - * - * Increments the data length of the buffer to account for more data at the - * end. - * - * @param buf Buffer to update. - * @param mem Location of data to be added. - * @param len Length of data to be added - * - * @return The original tail of the buffer. - */ -void *net_buf_simple_add_mem(struct net_buf_simple *buf, const void *mem, - size_t len); - -/** - * @brief Add (8-bit) byte at the end of the buffer - * - * Increments the data length of the buffer to account for more data at the - * end. - * - * @param buf Buffer to update. - * @param val byte value to be added. - * - * @return Pointer to the value added - */ -uint8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, uint8_t val); - -/** - * @brief Add 16-bit value at the end of the buffer - * - * Adds 16-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 16-bit value to be added. - */ -void net_buf_simple_add_le16(struct net_buf_simple *buf, uint16_t val); - -/** - * @brief Add 16-bit value at the end of the buffer - * - * Adds 16-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 16-bit value to be added. - */ -void net_buf_simple_add_be16(struct net_buf_simple *buf, uint16_t val); - -/** - * @brief Add 24-bit value at the end of the buffer - * - * Adds 24-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 24-bit value to be added. - */ -void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Add 24-bit value at the end of the buffer - * - * Adds 24-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 24-bit value to be added. - */ -void net_buf_simple_add_be24(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Add 32-bit value at the end of the buffer - * - * Adds 32-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 32-bit value to be added. - */ -void net_buf_simple_add_le32(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Add 32-bit value at the end of the buffer - * - * Adds 32-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 32-bit value to be added. - */ -void net_buf_simple_add_be32(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Add 40-bit value at the end of the buffer - * - * Adds 40-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 40-bit value to be added. - */ -void net_buf_simple_add_le40(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Add 40-bit value at the end of the buffer - * - * Adds 40-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 40-bit value to be added. - */ -void net_buf_simple_add_be40(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Add 48-bit value at the end of the buffer - * - * Adds 48-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 48-bit value to be added. - */ -void net_buf_simple_add_le48(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Add 48-bit value at the end of the buffer - * - * Adds 48-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 48-bit value to be added. - */ -void net_buf_simple_add_be48(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Add 64-bit value at the end of the buffer - * - * Adds 64-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 64-bit value to be added. - */ -void net_buf_simple_add_le64(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Add 64-bit value at the end of the buffer - * - * Adds 64-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 64-bit value to be added. - */ -void net_buf_simple_add_be64(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Remove data from the end of the buffer. - * - * Removes data from the end of the buffer by modifying the buffer length. - * - * @param buf Buffer to update. - * @param len Number of bytes to remove. - * - * @return New end of the buffer data. - */ -void *net_buf_simple_remove_mem(struct net_buf_simple *buf, size_t len); - -/** - * @brief Remove a 8-bit value from the end of the buffer - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 8-bit values. - * - * @param buf A valid pointer on a buffer. - * - * @return The 8-bit removed value - */ -uint8_t net_buf_simple_remove_u8(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 16 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 16-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from little endian to host endian. - */ -uint16_t net_buf_simple_remove_le16(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 16 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 16-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from big endian to host endian. - */ -uint16_t net_buf_simple_remove_be16(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 24 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 24-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from little endian to host endian. - */ -uint32_t net_buf_simple_remove_le24(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 24 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 24-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from big endian to host endian. - */ -uint32_t net_buf_simple_remove_be24(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 32 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 32-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 32-bit value converted from little endian to host endian. - */ -uint32_t net_buf_simple_remove_le32(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 32 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 32-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 32-bit value converted from big endian to host endian. - */ -uint32_t net_buf_simple_remove_be32(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 40 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 40-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 40-bit value converted from little endian to host endian. - */ -uint64_t net_buf_simple_remove_le40(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 40 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 40-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 40-bit value converted from big endian to host endian. - */ -uint64_t net_buf_simple_remove_be40(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 48 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 48-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 48-bit value converted from little endian to host endian. - */ -uint64_t net_buf_simple_remove_le48(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 48 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 48-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 48-bit value converted from big endian to host endian. - */ -uint64_t net_buf_simple_remove_be48(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 64 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 64-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 64-bit value converted from little endian to host endian. - */ -uint64_t net_buf_simple_remove_le64(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 64 bits from the end of the buffer. - * - * Same idea as with net_buf_simple_remove_mem(), but a helper for operating - * on 64-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 64-bit value converted from big endian to host endian. - */ -uint64_t net_buf_simple_remove_be64(struct net_buf_simple *buf); - -/** - * @brief Prepare data to be added to the start of the buffer - * - * Modifies the data pointer and buffer length to account for more data - * in the beginning of the buffer. - * - * @param buf Buffer to update. - * @param len Number of bytes to add to the beginning. - * - * @return The new beginning of the buffer data. - */ -void *net_buf_simple_push(struct net_buf_simple *buf, size_t len); - -/** - * @brief Copy given number of bytes from memory to the start of the buffer. - * - * Modifies the data pointer and buffer length to account for more data - * in the beginning of the buffer. - * - * @param buf Buffer to update. - * @param mem Location of data to be added. - * @param len Length of data to be added. - * - * @return The new beginning of the buffer data. - */ -void *net_buf_simple_push_mem(struct net_buf_simple *buf, const void *mem, - size_t len); - -/** - * @brief Push 16-bit value to the beginning of the buffer - * - * Adds 16-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 16-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_le16(struct net_buf_simple *buf, uint16_t val); - -/** - * @brief Push 16-bit value to the beginning of the buffer - * - * Adds 16-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 16-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_be16(struct net_buf_simple *buf, uint16_t val); - -/** - * @brief Push 8-bit value to the beginning of the buffer - * - * Adds 8-bit value the beginning of the buffer. - * - * @param buf Buffer to update. - * @param val 8-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_u8(struct net_buf_simple *buf, uint8_t val); - -/** - * @brief Push 24-bit value to the beginning of the buffer - * - * Adds 24-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 24-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_le24(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Push 24-bit value to the beginning of the buffer - * - * Adds 24-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 24-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_be24(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Push 32-bit value to the beginning of the buffer - * - * Adds 32-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 32-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_le32(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Push 32-bit value to the beginning of the buffer - * - * Adds 32-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 32-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_be32(struct net_buf_simple *buf, uint32_t val); - -/** - * @brief Push 40-bit value to the beginning of the buffer - * - * Adds 40-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 40-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_le40(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Push 40-bit value to the beginning of the buffer - * - * Adds 40-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 40-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_be40(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Push 48-bit value to the beginning of the buffer - * - * Adds 48-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 48-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_le48(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Push 48-bit value to the beginning of the buffer - * - * Adds 48-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 48-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_be48(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Push 64-bit value to the beginning of the buffer - * - * Adds 64-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 64-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_le64(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Push 64-bit value to the beginning of the buffer - * - * Adds 64-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 64-bit value to be pushed to the buffer. - */ -void net_buf_simple_push_be64(struct net_buf_simple *buf, uint64_t val); - -/** - * @brief Remove data from the beginning of the buffer. - * - * Removes data from the beginning of the buffer by modifying the data - * pointer and buffer length. - * - * @param buf Buffer to update. - * @param len Number of bytes to remove. - * - * @return New beginning of the buffer data. - */ -void *net_buf_simple_pull(struct net_buf_simple *buf, size_t len); -/** - * @brief Remove data from the beginning of the buffer. - * - * Removes data from the beginning of the buffer by modifying the data - * pointer and buffer length. - * - * @param buf Buffer to update. - * @param len Number of bytes to remove. - * - * @return Pointer to the old location of the buffer data. - */ -void *net_buf_simple_pull_mem(struct net_buf_simple *buf, size_t len); +#ifndef ZEPHYR_INCLUDE_NET_BUF_DEPRECATED_H_ +#define ZEPHYR_INCLUDE_NET_BUF_DEPRECATED_H_ -/** - * @brief Remove a 8-bit value from the beginning of the buffer - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 8-bit values. - * - * @param buf A valid pointer on a buffer. - * - * @return The 8-bit removed value - */ -uint8_t net_buf_simple_pull_u8(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 16 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 16-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from little endian to host endian. - */ -uint16_t net_buf_simple_pull_le16(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 16 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 16-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from big endian to host endian. - */ -uint16_t net_buf_simple_pull_be16(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 24 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 24-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from little endian to host endian. - */ -uint32_t net_buf_simple_pull_le24(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 24 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 24-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from big endian to host endian. - */ -uint32_t net_buf_simple_pull_be24(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 32 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 32-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 32-bit value converted from little endian to host endian. - */ -uint32_t net_buf_simple_pull_le32(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 32 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 32-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 32-bit value converted from big endian to host endian. - */ -uint32_t net_buf_simple_pull_be32(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 40 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 40-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 40-bit value converted from little endian to host endian. - */ -uint64_t net_buf_simple_pull_le40(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 40 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 40-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 40-bit value converted from big endian to host endian. - */ -uint64_t net_buf_simple_pull_be40(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 48 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 48-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 48-bit value converted from little endian to host endian. - */ -uint64_t net_buf_simple_pull_le48(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 48 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 48-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 48-bit value converted from big endian to host endian. - */ -uint64_t net_buf_simple_pull_be48(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 64 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 64-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 64-bit value converted from little endian to host endian. - */ -uint64_t net_buf_simple_pull_le64(struct net_buf_simple *buf); - -/** - * @brief Remove and convert 64 bits from the beginning of the buffer. - * - * Same idea as with net_buf_simple_pull(), but a helper for operating - * on 64-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 64-bit value converted from big endian to host endian. - */ -uint64_t net_buf_simple_pull_be64(struct net_buf_simple *buf); - -/** - * @brief Get the tail pointer for a buffer. - * - * Get a pointer to the end of the data in a buffer. - * - * @param buf Buffer. - * - * @return Tail pointer for the buffer. - */ -static inline uint8_t *net_buf_simple_tail(const struct net_buf_simple *buf) -{ - return buf->data + buf->len; -} - -/** - * @brief Check buffer headroom. - * - * Check how much free space there is in the beginning of the buffer. - * - * buf A valid pointer on a buffer - * - * @return Number of bytes available in the beginning of the buffer. - */ -size_t net_buf_simple_headroom(const struct net_buf_simple *buf); - -/** - * @brief Check buffer tailroom. - * - * Check how much free space there is at the end of the buffer. - * - * @param buf A valid pointer on a buffer - * - * @return Number of bytes available at the end of the buffer. - */ -size_t net_buf_simple_tailroom(const struct net_buf_simple *buf); - -/** - * @brief Check maximum net_buf_simple::len value. - * - * This value is depending on the number of bytes being reserved as headroom. - * - * @param buf A valid pointer on a buffer - * - * @return Number of bytes usable behind the net_buf_simple::data pointer. - */ -uint16_t net_buf_simple_max_len(const struct net_buf_simple *buf); - -/** - * @brief Parsing state of a buffer. - * - * This is used for temporarily storing the parsing state of a buffer - * while giving control of the parsing to a routine which we don't - * control. - */ -struct net_buf_simple_state { - /** Offset of the data pointer from the beginning of the storage */ - uint16_t offset; - /** Length of data */ - uint16_t len; -}; - -/** - * @brief Save the parsing state of a buffer. - * - * Saves the parsing state of a buffer so it can be restored later. - * - * @param buf Buffer from which the state should be saved. - * @param state Storage for the state. - */ -static inline void net_buf_simple_save(const struct net_buf_simple *buf, - struct net_buf_simple_state *state) -{ - state->offset = (uint16_t)net_buf_simple_headroom(buf); - state->len = buf->len; -} - -/** - * @brief Restore the parsing state of a buffer. - * - * Restores the parsing state of a buffer from a state previously stored - * by net_buf_simple_save(). - * - * @param buf Buffer to which the state should be restored. - * @param state Stored state. - */ -static inline void net_buf_simple_restore(struct net_buf_simple *buf, - struct net_buf_simple_state *state) -{ - buf->data = buf->__buf + state->offset; - buf->len = state->len; -} - -/** - * Flag indicating that the buffer's associated data pointer, points to - * externally allocated memory. Therefore once ref goes down to zero, the - * pointed data will not need to be deallocated. This never needs to be - * explicitly set or unset by the net_buf API user. Such net_buf is - * exclusively instantiated via net_buf_alloc_with_data() function. - * Reference count mechanism however will behave the same way, and ref - * count going to 0 will free the net_buf but no the data pointer in it. - */ -#define NET_BUF_EXTERNAL_DATA BIT(0) - -/** - * @brief Network buffer representation. - * - * This struct is used to represent network buffers. Such buffers are - * normally defined through the NET_BUF_POOL_*_DEFINE() APIs and allocated - * using the net_buf_alloc() API. - */ -struct net_buf { - /** Allow placing the buffer into sys_slist_t */ - sys_snode_t node; - - /** Fragments associated with this buffer. */ - struct net_buf *frags; - - /** Reference count. */ - uint8_t ref; - - /** Bit-field of buffer flags. */ - uint8_t flags; - - /** Where the buffer should go when freed up. */ - uint8_t pool_id; - - /** Size of user data on this buffer */ - uint8_t user_data_size; - - /** Union for convenience access to the net_buf_simple members, also - * preserving the old API. - */ - union { - /* The ABI of this struct must match net_buf_simple */ - struct { - /** Pointer to the start of data in the buffer. */ - uint8_t *data; - - /** Length of the data behind the data pointer. */ - uint16_t len; - - /** Amount of data that this buffer can store. */ - uint16_t size; - - /** Start of the data storage. Not to be accessed - * directly (the data pointer should be used - * instead). - */ - uint8_t *__buf; - }; - - /** @cond INTERNAL_HIDDEN */ - struct net_buf_simple b; - /** @endcond */ - }; - - /** System metadata for this buffer. */ - uint8_t user_data[] __net_buf_align; -}; - -/** @cond INTERNAL_HIDDEN */ - -struct net_buf_data_cb { - uint8_t * __must_check (*alloc)(struct net_buf *buf, size_t *size, - k_timeout_t timeout); - uint8_t * __must_check (*ref)(struct net_buf *buf, uint8_t *data); - void (*unref)(struct net_buf *buf, uint8_t *data); -}; - -struct net_buf_data_alloc { - const struct net_buf_data_cb *cb; - void *alloc_data; - size_t max_alloc_size; -}; - -/** @endcond */ - -/** - * @brief Network buffer pool representation. - * - * This struct is used to represent a pool of network buffers. - */ -struct net_buf_pool { - /** LIFO to place the buffer into when free */ - struct k_lifo free; - - /** To prevent concurrent access/modifications */ - struct k_spinlock lock; - - /** Number of buffers in pool */ - const uint16_t buf_count; - - /** Number of uninitialized buffers */ - uint16_t uninit_count; - - /** Size of user data allocated to this pool */ - uint8_t user_data_size; - -#if defined(CONFIG_NET_BUF_POOL_USAGE) - /** Amount of available buffers in the pool. */ - atomic_t avail_count; - - /** Total size of the pool. */ - const uint16_t pool_size; - - /** Name of the pool. Used when printing pool information. */ - const char *name; -#endif /* CONFIG_NET_BUF_POOL_USAGE */ - - /** Optional destroy callback when buffer is freed. */ - void (*const destroy)(struct net_buf *buf); - - /** Data allocation handlers. */ - const struct net_buf_data_alloc *alloc; - - /** Start of buffer storage array */ - struct net_buf * const __bufs; -}; - -/** @cond INTERNAL_HIDDEN */ -#define NET_BUF_POOL_USAGE_INIT(_pool, _count) \ - IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.avail_count = ATOMIC_INIT(_count),)) \ - IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.name = STRINGIFY(_pool),)) - -#define NET_BUF_POOL_INITIALIZER(_pool, _alloc, _bufs, _count, _ud_size, _destroy) \ - { \ - .free = Z_LIFO_INITIALIZER(_pool.free), \ - .lock = { }, \ - .buf_count = _count, \ - .uninit_count = _count, \ - .user_data_size = _ud_size, \ - NET_BUF_POOL_USAGE_INIT(_pool, _count) \ - .destroy = _destroy, \ - .alloc = _alloc, \ - .__bufs = (struct net_buf *)_bufs, \ - } - -#define _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size) \ - struct _net_buf_##_name { uint8_t b[sizeof(struct net_buf)]; \ - uint8_t ud[_ud_size]; } __net_buf_align; \ - BUILD_ASSERT(_ud_size <= UINT8_MAX); \ - BUILD_ASSERT(offsetof(struct net_buf, user_data) == \ - offsetof(struct _net_buf_##_name, ud), "Invalid offset"); \ - BUILD_ASSERT(__alignof__(struct net_buf) == \ - __alignof__(struct _net_buf_##_name), "Invalid alignment"); \ - BUILD_ASSERT(sizeof(struct _net_buf_##_name) == \ - ROUND_UP(sizeof(struct net_buf) + _ud_size, __alignof__(struct net_buf)), \ - "Size cannot be determined"); \ - static struct _net_buf_##_name _net_buf_##_name[_count] __noinit - -extern const struct net_buf_data_alloc net_buf_heap_alloc; -/** @endcond */ - -/** - * - * @brief Define a new pool for buffers using the heap for the data. - * - * Defines a net_buf_pool struct and the necessary memory storage (array of - * structs) for the needed amount of buffers. After this, the buffers can be - * accessed from the pool through net_buf_alloc. The pool is defined as a - * static variable, so if it needs to be exported outside the current module - * this needs to happen with the help of a separate pointer rather than an - * extern declaration. - * - * The data payload of the buffers will be allocated from the heap using - * k_malloc, so CONFIG_HEAP_MEM_POOL_SIZE must be set to a positive value. - * This kind of pool does not support blocking on the data allocation, so - * the timeout passed to net_buf_alloc will be always treated as K_NO_WAIT - * when trying to allocate the data. This means that allocation failures, - * i.e. NULL returns, must always be handled cleanly. - * - * If provided with a custom destroy callback, this callback is - * responsible for eventually calling net_buf_destroy() to complete the - * process of returning the buffer to the pool. - * - * @param _name Name of the pool variable. - * @param _count Number of buffers in the pool. - * @param _ud_size User data space to reserve per buffer. - * @param _destroy Optional destroy callback when buffer is freed. - */ -#define NET_BUF_POOL_HEAP_DEFINE(_name, _count, _ud_size, _destroy) \ - _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size); \ - static STRUCT_SECTION_ITERABLE(net_buf_pool, _name) = \ - NET_BUF_POOL_INITIALIZER(_name, &net_buf_heap_alloc, \ - _net_buf_##_name, _count, _ud_size, \ - _destroy) - -/** @cond INTERNAL_HIDDEN */ - -struct net_buf_pool_fixed { - uint8_t *data_pool; -}; - -extern const struct net_buf_data_cb net_buf_fixed_cb; - -/** @endcond */ - -/** - * - * @brief Define a new pool for buffers based on fixed-size data - * - * Defines a net_buf_pool struct and the necessary memory storage (array of - * structs) for the needed amount of buffers. After this, the buffers can be - * accessed from the pool through net_buf_alloc. The pool is defined as a - * static variable, so if it needs to be exported outside the current module - * this needs to happen with the help of a separate pointer rather than an - * extern declaration. - * - * The data payload of the buffers will be allocated from a byte array - * of fixed sized chunks. This kind of pool does not support blocking on - * the data allocation, so the timeout passed to net_buf_alloc will be - * always treated as K_NO_WAIT when trying to allocate the data. This means - * that allocation failures, i.e. NULL returns, must always be handled - * cleanly. - * - * If provided with a custom destroy callback, this callback is - * responsible for eventually calling net_buf_destroy() to complete the - * process of returning the buffer to the pool. - * - * @param _name Name of the pool variable. - * @param _count Number of buffers in the pool. - * @param _data_size Maximum data payload per buffer. - * @param _ud_size User data space to reserve per buffer. - * @param _destroy Optional destroy callback when buffer is freed. - */ -#define NET_BUF_POOL_FIXED_DEFINE(_name, _count, _data_size, _ud_size, _destroy) \ - _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size); \ - static uint8_t __noinit net_buf_data_##_name[_count][_data_size] __net_buf_align; \ - static const struct net_buf_pool_fixed net_buf_fixed_##_name = { \ - .data_pool = (uint8_t *)net_buf_data_##_name, \ - }; \ - static const struct net_buf_data_alloc net_buf_fixed_alloc_##_name = { \ - .cb = &net_buf_fixed_cb, \ - .alloc_data = (void *)&net_buf_fixed_##_name, \ - .max_alloc_size = _data_size, \ - }; \ - static STRUCT_SECTION_ITERABLE(net_buf_pool, _name) = \ - NET_BUF_POOL_INITIALIZER(_name, &net_buf_fixed_alloc_##_name, \ - _net_buf_##_name, _count, _ud_size, \ - _destroy) - -/** @cond INTERNAL_HIDDEN */ -extern const struct net_buf_data_cb net_buf_var_cb; -/** @endcond */ - -/** - * - * @brief Define a new pool for buffers with variable size payloads - * - * Defines a net_buf_pool struct and the necessary memory storage (array of - * structs) for the needed amount of buffers. After this, the buffers can be - * accessed from the pool through net_buf_alloc. The pool is defined as a - * static variable, so if it needs to be exported outside the current module - * this needs to happen with the help of a separate pointer rather than an - * extern declaration. - * - * The data payload of the buffers will be based on a memory pool from which - * variable size payloads may be allocated. - * - * If provided with a custom destroy callback, this callback is - * responsible for eventually calling net_buf_destroy() to complete the - * process of returning the buffer to the pool. - * - * @param _name Name of the pool variable. - * @param _count Number of buffers in the pool. - * @param _data_size Total amount of memory available for data payloads. - * @param _ud_size User data space to reserve per buffer. - * @param _destroy Optional destroy callback when buffer is freed. - */ -#define NET_BUF_POOL_VAR_DEFINE(_name, _count, _data_size, _ud_size, _destroy) \ - _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size); \ - K_HEAP_DEFINE(net_buf_mem_pool_##_name, _data_size); \ - static const struct net_buf_data_alloc net_buf_data_alloc_##_name = { \ - .cb = &net_buf_var_cb, \ - .alloc_data = &net_buf_mem_pool_##_name, \ - .max_alloc_size = 0, \ - }; \ - static STRUCT_SECTION_ITERABLE(net_buf_pool, _name) = \ - NET_BUF_POOL_INITIALIZER(_name, &net_buf_data_alloc_##_name, \ - _net_buf_##_name, _count, _ud_size, \ - _destroy) - -/** - * - * @brief Define a new pool for buffers - * - * Defines a net_buf_pool struct and the necessary memory storage (array of - * structs) for the needed amount of buffers. After this,the buffers can be - * accessed from the pool through net_buf_alloc. The pool is defined as a - * static variable, so if it needs to be exported outside the current module - * this needs to happen with the help of a separate pointer rather than an - * extern declaration. - * - * If provided with a custom destroy callback this callback is - * responsible for eventually calling net_buf_destroy() to complete the - * process of returning the buffer to the pool. - * - * @param _name Name of the pool variable. - * @param _count Number of buffers in the pool. - * @param _size Maximum data size for each buffer. - * @param _ud_size Amount of user data space to reserve. - * @param _destroy Optional destroy callback when buffer is freed. - */ -#define NET_BUF_POOL_DEFINE(_name, _count, _size, _ud_size, _destroy) \ - NET_BUF_POOL_FIXED_DEFINE(_name, _count, _size, _ud_size, _destroy) - -/** - * @brief Looks up a pool based on its ID. - * - * @param id Pool ID (e.g. from buf->pool_id). - * - * @return Pointer to pool. - */ -struct net_buf_pool *net_buf_pool_get(int id); - -/** - * @brief Get a zero-based index for a buffer. - * - * This function will translate a buffer into a zero-based index, - * based on its placement in its buffer pool. This can be useful if you - * want to associate an external array of meta-data contexts with the - * buffers of a pool. - * - * @param buf Network buffer. - * - * @return Zero-based index for the buffer. - */ -int net_buf_id(const struct net_buf *buf); - -/** - * @brief Allocate a new fixed buffer from a pool. - * - * @note Some types of data allocators do not support - * blocking (such as the HEAP type). In this case it's still possible - * for net_buf_alloc() to fail (return NULL) even if it was given - * K_FOREVER. - * - * @note The timeout value will be overridden to K_NO_WAIT if called from the - * system workqueue. - * - * @param pool Which pool to allocate the buffer from. - * @param timeout Affects the action taken should the pool be empty. - * If K_NO_WAIT, then return immediately. If K_FOREVER, then - * wait as long as necessary. Otherwise, wait until the specified - * timeout. - * - * @return New buffer or NULL if out of buffers. - */ -#if defined(CONFIG_NET_BUF_LOG) -struct net_buf * __must_check net_buf_alloc_fixed_debug(struct net_buf_pool *pool, - k_timeout_t timeout, - const char *func, - int line); -#define net_buf_alloc_fixed(_pool, _timeout) \ - net_buf_alloc_fixed_debug(_pool, _timeout, __func__, __LINE__) -#else -struct net_buf * __must_check net_buf_alloc_fixed(struct net_buf_pool *pool, - k_timeout_t timeout); -#endif - -/** - * @copydetails net_buf_alloc_fixed - */ -static inline struct net_buf * __must_check net_buf_alloc(struct net_buf_pool *pool, - k_timeout_t timeout) -{ - return net_buf_alloc_fixed(pool, timeout); -} - -/** - * @brief Allocate a new variable length buffer from a pool. - * - * @note Some types of data allocators do not support - * blocking (such as the HEAP type). In this case it's still possible - * for net_buf_alloc() to fail (return NULL) even if it was given - * K_FOREVER. - * - * @note The timeout value will be overridden to K_NO_WAIT if called from the - * system workqueue. - * - * @param pool Which pool to allocate the buffer from. - * @param size Amount of data the buffer must be able to fit. - * @param timeout Affects the action taken should the pool be empty. - * If K_NO_WAIT, then return immediately. If K_FOREVER, then - * wait as long as necessary. Otherwise, wait until the specified - * timeout. - * - * @return New buffer or NULL if out of buffers. - */ -#if defined(CONFIG_NET_BUF_LOG) -struct net_buf * __must_check net_buf_alloc_len_debug(struct net_buf_pool *pool, - size_t size, - k_timeout_t timeout, - const char *func, - int line); -#define net_buf_alloc_len(_pool, _size, _timeout) \ - net_buf_alloc_len_debug(_pool, _size, _timeout, __func__, __LINE__) -#else -struct net_buf * __must_check net_buf_alloc_len(struct net_buf_pool *pool, - size_t size, - k_timeout_t timeout); -#endif - -/** - * @brief Allocate a new buffer from a pool but with external data pointer. - * - * Allocate a new buffer from a pool, where the data pointer comes from the - * user and not from the pool. - * - * @note Some types of data allocators do not support - * blocking (such as the HEAP type). In this case it's still possible - * for net_buf_alloc() to fail (return NULL) even if it was given - * K_FOREVER. - * - * @note The timeout value will be overridden to K_NO_WAIT if called from the - * system workqueue. - * - * @param pool Which pool to allocate the buffer from. - * @param data External data pointer - * @param size Amount of data the pointed data buffer if able to fit. - * @param timeout Affects the action taken should the pool be empty. - * If K_NO_WAIT, then return immediately. If K_FOREVER, then - * wait as long as necessary. Otherwise, wait until the specified - * timeout. - * - * @return New buffer or NULL if out of buffers. - */ -#if defined(CONFIG_NET_BUF_LOG) -struct net_buf * __must_check net_buf_alloc_with_data_debug(struct net_buf_pool *pool, - void *data, size_t size, - k_timeout_t timeout, - const char *func, int line); -#define net_buf_alloc_with_data(_pool, _data_, _size, _timeout) \ - net_buf_alloc_with_data_debug(_pool, _data_, _size, _timeout, \ - __func__, __LINE__) -#else -struct net_buf * __must_check net_buf_alloc_with_data(struct net_buf_pool *pool, - void *data, size_t size, - k_timeout_t timeout); -#endif - -/** - * @brief Get a buffer from a FIFO. - * - * This function is NOT thread-safe if the buffers in the FIFO contain - * fragments. - * - * @param fifo Which FIFO to take the buffer from. - * @param timeout Affects the action taken should the FIFO be empty. - * If K_NO_WAIT, then return immediately. If K_FOREVER, then wait as - * long as necessary. Otherwise, wait until the specified timeout. - * - * @return New buffer or NULL if the FIFO is empty. - */ -#if defined(CONFIG_NET_BUF_LOG) -struct net_buf * __must_check net_buf_get_debug(struct k_fifo *fifo, - k_timeout_t timeout, - const char *func, int line); -#define net_buf_get(_fifo, _timeout) \ - net_buf_get_debug(_fifo, _timeout, __func__, __LINE__) -#else -struct net_buf * __must_check net_buf_get(struct k_fifo *fifo, - k_timeout_t timeout); -#endif - -/** - * @brief Destroy buffer from custom destroy callback - * - * This helper is only intended to be used from custom destroy callbacks. - * If no custom destroy callback is given to NET_BUF_POOL_*_DEFINE() then - * there is no need to use this API. - * - * @param buf Buffer to destroy. - */ -static inline void net_buf_destroy(struct net_buf *buf) -{ - struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); - - if (buf->__buf) { - if (!(buf->flags & NET_BUF_EXTERNAL_DATA)) { - pool->alloc->cb->unref(buf, buf->__buf); - } - buf->__buf = NULL; - } - - k_lifo_put(&pool->free, buf); -} - -/** - * @brief Reset buffer - * - * Reset buffer data and flags so it can be reused for other purposes. - * - * @param buf Buffer to reset. - */ -void net_buf_reset(struct net_buf *buf); - -/** - * @brief Initialize buffer with the given headroom. - * - * The buffer is not expected to contain any data when this API is called. - * - * @param buf Buffer to initialize. - * @param reserve How much headroom to reserve. - */ -void net_buf_simple_reserve(struct net_buf_simple *buf, size_t reserve); - -/** - * @brief Put a buffer into a list - * - * If the buffer contains follow-up fragments this function will take care of - * inserting them as well into the list. - * - * @param list Which list to append the buffer to. - * @param buf Buffer. - */ -void net_buf_slist_put(sys_slist_t *list, struct net_buf *buf); - -/** - * @brief Get a buffer from a list. - * - * If the buffer had any fragments, these will automatically be recovered from - * the list as well and be placed to the buffer's fragment list. - * - * @param list Which list to take the buffer from. - * - * @return New buffer or NULL if the FIFO is empty. - */ -struct net_buf * __must_check net_buf_slist_get(sys_slist_t *list); - -/** - * @brief Put a buffer to the end of a FIFO. - * - * If the buffer contains follow-up fragments this function will take care of - * inserting them as well into the FIFO. - * - * @param fifo Which FIFO to put the buffer to. - * @param buf Buffer. - */ -void net_buf_put(struct k_fifo *fifo, struct net_buf *buf); - -/** - * @brief Decrements the reference count of a buffer. - * - * The buffer is put back into the pool if the reference count reaches zero. - * - * @param buf A valid pointer on a buffer - */ -#if defined(CONFIG_NET_BUF_LOG) -void net_buf_unref_debug(struct net_buf *buf, const char *func, int line); -#define net_buf_unref(_buf) \ - net_buf_unref_debug(_buf, __func__, __LINE__) -#else -void net_buf_unref(struct net_buf *buf); -#endif - -/** - * @brief Increment the reference count of a buffer. - * - * @param buf A valid pointer on a buffer - * - * @return the buffer newly referenced - */ -struct net_buf * __must_check net_buf_ref(struct net_buf *buf); - -/** - * @brief Clone buffer - * - * Duplicate given buffer including any (user) data and headers currently stored. - * - * @param buf A valid pointer on a buffer - * @param timeout Affects the action taken should the pool be empty. - * If K_NO_WAIT, then return immediately. If K_FOREVER, then - * wait as long as necessary. Otherwise, wait until the specified - * timeout. - * - * @return Cloned buffer or NULL if out of buffers. - */ -struct net_buf * __must_check net_buf_clone(struct net_buf *buf, - k_timeout_t timeout); - -/** - * @brief Get a pointer to the user data of a buffer. - * - * @param buf A valid pointer on a buffer - * - * @return Pointer to the user data of the buffer. - */ -static inline void * __must_check net_buf_user_data(const struct net_buf *buf) -{ - return (void *)buf->user_data; -} - -/** - * @brief Copy user data from one to another buffer. - * - * @param dst A valid pointer to a buffer gettings its user data overwritten. - * @param src A valid pointer to a buffer gettings its user data copied. User data size must be - * equal to or exceed @a dst. - * - * @return 0 on success or negative error number on failure. - */ -int net_buf_user_data_copy(struct net_buf *dst, const struct net_buf *src); - -/** - * @brief Initialize buffer with the given headroom. - * - * The buffer is not expected to contain any data when this API is called. - * - * @param buf Buffer to initialize. - * @param reserve How much headroom to reserve. - */ -static inline void net_buf_reserve(struct net_buf *buf, size_t reserve) -{ - net_buf_simple_reserve(&buf->b, reserve); -} - -/** - * @brief Prepare data to be added at the end of the buffer - * - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param len Number of bytes to increment the length with. - * - * @return The original tail of the buffer. - */ -static inline void *net_buf_add(struct net_buf *buf, size_t len) -{ - return net_buf_simple_add(&buf->b, len); -} - -/** - * @brief Copies the given number of bytes to the end of the buffer - * - * Increments the data length of the buffer to account for more data at - * the end. - * - * @param buf Buffer to update. - * @param mem Location of data to be added. - * @param len Length of data to be added - * - * @return The original tail of the buffer. - */ -static inline void *net_buf_add_mem(struct net_buf *buf, const void *mem, - size_t len) -{ - return net_buf_simple_add_mem(&buf->b, mem, len); -} - -/** - * @brief Add (8-bit) byte at the end of the buffer - * - * Increments the data length of the buffer to account for more data at - * the end. - * - * @param buf Buffer to update. - * @param val byte value to be added. - * - * @return Pointer to the value added - */ -static inline uint8_t *net_buf_add_u8(struct net_buf *buf, uint8_t val) -{ - return net_buf_simple_add_u8(&buf->b, val); -} - -/** - * @brief Add 16-bit value at the end of the buffer - * - * Adds 16-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 16-bit value to be added. - */ -static inline void net_buf_add_le16(struct net_buf *buf, uint16_t val) -{ - net_buf_simple_add_le16(&buf->b, val); -} - -/** - * @brief Add 16-bit value at the end of the buffer - * - * Adds 16-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 16-bit value to be added. - */ -static inline void net_buf_add_be16(struct net_buf *buf, uint16_t val) -{ - net_buf_simple_add_be16(&buf->b, val); -} - -/** - * @brief Add 24-bit value at the end of the buffer - * - * Adds 24-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 24-bit value to be added. - */ -static inline void net_buf_add_le24(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_add_le24(&buf->b, val); -} - -/** - * @brief Add 24-bit value at the end of the buffer - * - * Adds 24-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 24-bit value to be added. - */ -static inline void net_buf_add_be24(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_add_be24(&buf->b, val); -} - -/** - * @brief Add 32-bit value at the end of the buffer - * - * Adds 32-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 32-bit value to be added. - */ -static inline void net_buf_add_le32(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_add_le32(&buf->b, val); -} - -/** - * @brief Add 32-bit value at the end of the buffer - * - * Adds 32-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 32-bit value to be added. - */ -static inline void net_buf_add_be32(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_add_be32(&buf->b, val); -} - -/** - * @brief Add 40-bit value at the end of the buffer - * - * Adds 40-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 40-bit value to be added. - */ -static inline void net_buf_add_le40(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_add_le40(&buf->b, val); -} - -/** - * @brief Add 40-bit value at the end of the buffer - * - * Adds 40-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 40-bit value to be added. - */ -static inline void net_buf_add_be40(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_add_be40(&buf->b, val); -} - -/** - * @brief Add 48-bit value at the end of the buffer - * - * Adds 48-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 48-bit value to be added. - */ -static inline void net_buf_add_le48(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_add_le48(&buf->b, val); -} - -/** - * @brief Add 48-bit value at the end of the buffer - * - * Adds 48-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 48-bit value to be added. - */ -static inline void net_buf_add_be48(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_add_be48(&buf->b, val); -} - -/** - * @brief Add 64-bit value at the end of the buffer - * - * Adds 64-bit value in little endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 64-bit value to be added. - */ -static inline void net_buf_add_le64(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_add_le64(&buf->b, val); -} - -/** - * @brief Add 64-bit value at the end of the buffer - * - * Adds 64-bit value in big endian format at the end of buffer. - * Increments the data length of a buffer to account for more data - * at the end. - * - * @param buf Buffer to update. - * @param val 64-bit value to be added. - */ -static inline void net_buf_add_be64(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_add_be64(&buf->b, val); -} - -/** - * @brief Remove data from the end of the buffer. - * - * Removes data from the end of the buffer by modifying the buffer length. - * - * @param buf Buffer to update. - * @param len Number of bytes to remove. - * - * @return New end of the buffer data. - */ -static inline void *net_buf_remove_mem(struct net_buf *buf, size_t len) -{ - return net_buf_simple_remove_mem(&buf->b, len); -} - -/** - * @brief Remove a 8-bit value from the end of the buffer - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 8-bit values. - * - * @param buf A valid pointer on a buffer. - * - * @return The 8-bit removed value - */ -static inline uint8_t net_buf_remove_u8(struct net_buf *buf) -{ - return net_buf_simple_remove_u8(&buf->b); -} - -/** - * @brief Remove and convert 16 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 16-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from little endian to host endian. - */ -static inline uint16_t net_buf_remove_le16(struct net_buf *buf) -{ - return net_buf_simple_remove_le16(&buf->b); -} - -/** - * @brief Remove and convert 16 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 16-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from big endian to host endian. - */ -static inline uint16_t net_buf_remove_be16(struct net_buf *buf) -{ - return net_buf_simple_remove_be16(&buf->b); -} - -/** - * @brief Remove and convert 24 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 24-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from big endian to host endian. - */ -static inline uint32_t net_buf_remove_be24(struct net_buf *buf) -{ - return net_buf_simple_remove_be24(&buf->b); -} - -/** - * @brief Remove and convert 24 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 24-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from little endian to host endian. - */ -static inline uint32_t net_buf_remove_le24(struct net_buf *buf) -{ - return net_buf_simple_remove_le24(&buf->b); -} - -/** - * @brief Remove and convert 32 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 32-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 32-bit value converted from little endian to host endian. - */ -static inline uint32_t net_buf_remove_le32(struct net_buf *buf) -{ - return net_buf_simple_remove_le32(&buf->b); -} - -/** - * @brief Remove and convert 32 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 32-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 32-bit value converted from big endian to host endian. - */ -static inline uint32_t net_buf_remove_be32(struct net_buf *buf) -{ - return net_buf_simple_remove_be32(&buf->b); -} - -/** - * @brief Remove and convert 40 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 40-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 40-bit value converted from little endian to host endian. - */ -static inline uint64_t net_buf_remove_le40(struct net_buf *buf) -{ - return net_buf_simple_remove_le40(&buf->b); -} - -/** - * @brief Remove and convert 40 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 40-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 40-bit value converted from big endian to host endian. - */ -static inline uint64_t net_buf_remove_be40(struct net_buf *buf) -{ - return net_buf_simple_remove_be40(&buf->b); -} - -/** - * @brief Remove and convert 48 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 48-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 48-bit value converted from little endian to host endian. - */ -static inline uint64_t net_buf_remove_le48(struct net_buf *buf) -{ - return net_buf_simple_remove_le48(&buf->b); -} - -/** - * @brief Remove and convert 48 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 48-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 48-bit value converted from big endian to host endian. - */ -static inline uint64_t net_buf_remove_be48(struct net_buf *buf) -{ - return net_buf_simple_remove_be48(&buf->b); -} - -/** - * @brief Remove and convert 64 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 64-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 64-bit value converted from little endian to host endian. - */ -static inline uint64_t net_buf_remove_le64(struct net_buf *buf) -{ - return net_buf_simple_remove_le64(&buf->b); -} - -/** - * @brief Remove and convert 64 bits from the end of the buffer. - * - * Same idea as with net_buf_remove_mem(), but a helper for operating on - * 64-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 64-bit value converted from big endian to host endian. - */ -static inline uint64_t net_buf_remove_be64(struct net_buf *buf) -{ - return net_buf_simple_remove_be64(&buf->b); -} - -/** - * @brief Prepare data to be added at the start of the buffer - * - * Modifies the data pointer and buffer length to account for more data - * in the beginning of the buffer. - * - * @param buf Buffer to update. - * @param len Number of bytes to add to the beginning. - * - * @return The new beginning of the buffer data. - */ -static inline void *net_buf_push(struct net_buf *buf, size_t len) -{ - return net_buf_simple_push(&buf->b, len); -} - -/** - * @brief Copies the given number of bytes to the start of the buffer - * - * Modifies the data pointer and buffer length to account for more data - * in the beginning of the buffer. - * - * @param buf Buffer to update. - * @param mem Location of data to be added. - * @param len Length of data to be added. - * - * @return The new beginning of the buffer data. - */ -static inline void *net_buf_push_mem(struct net_buf *buf, const void *mem, - size_t len) -{ - return net_buf_simple_push_mem(&buf->b, mem, len); -} - -/** - * @brief Push 8-bit value to the beginning of the buffer - * - * Adds 8-bit value the beginning of the buffer. - * - * @param buf Buffer to update. - * @param val 8-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_u8(struct net_buf *buf, uint8_t val) -{ - net_buf_simple_push_u8(&buf->b, val); -} - -/** - * @brief Push 16-bit value to the beginning of the buffer - * - * Adds 16-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 16-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_le16(struct net_buf *buf, uint16_t val) -{ - net_buf_simple_push_le16(&buf->b, val); -} - -/** - * @brief Push 16-bit value to the beginning of the buffer - * - * Adds 16-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 16-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_be16(struct net_buf *buf, uint16_t val) -{ - net_buf_simple_push_be16(&buf->b, val); -} - -/** - * @brief Push 24-bit value to the beginning of the buffer - * - * Adds 24-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 24-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_le24(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_push_le24(&buf->b, val); -} - -/** - * @brief Push 24-bit value to the beginning of the buffer - * - * Adds 24-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 24-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_be24(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_push_be24(&buf->b, val); -} - -/** - * @brief Push 32-bit value to the beginning of the buffer - * - * Adds 32-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 32-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_le32(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_push_le32(&buf->b, val); -} - -/** - * @brief Push 32-bit value to the beginning of the buffer - * - * Adds 32-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 32-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_be32(struct net_buf *buf, uint32_t val) -{ - net_buf_simple_push_be32(&buf->b, val); -} - -/** - * @brief Push 40-bit value to the beginning of the buffer - * - * Adds 40-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 40-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_le40(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_push_le40(&buf->b, val); -} - -/** - * @brief Push 40-bit value to the beginning of the buffer - * - * Adds 40-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 40-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_be40(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_push_be40(&buf->b, val); -} - -/** - * @brief Push 48-bit value to the beginning of the buffer - * - * Adds 48-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 48-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_le48(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_push_le48(&buf->b, val); -} - -/** - * @brief Push 48-bit value to the beginning of the buffer - * - * Adds 48-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 48-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_be48(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_push_be48(&buf->b, val); -} - -/** - * @brief Push 64-bit value to the beginning of the buffer - * - * Adds 64-bit value in little endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 64-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_le64(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_push_le64(&buf->b, val); -} - -/** - * @brief Push 64-bit value to the beginning of the buffer - * - * Adds 64-bit value in big endian format to the beginning of the - * buffer. - * - * @param buf Buffer to update. - * @param val 64-bit value to be pushed to the buffer. - */ -static inline void net_buf_push_be64(struct net_buf *buf, uint64_t val) -{ - net_buf_simple_push_be64(&buf->b, val); -} - -/** - * @brief Remove data from the beginning of the buffer. - * - * Removes data from the beginning of the buffer by modifying the data - * pointer and buffer length. - * - * @param buf Buffer to update. - * @param len Number of bytes to remove. - * - * @return New beginning of the buffer data. - */ -static inline void *net_buf_pull(struct net_buf *buf, size_t len) -{ - return net_buf_simple_pull(&buf->b, len); -} - -/** - * @brief Remove data from the beginning of the buffer. - * - * Removes data from the beginning of the buffer by modifying the data - * pointer and buffer length. - * - * @param buf Buffer to update. - * @param len Number of bytes to remove. - * - * @return Pointer to the old beginning of the buffer data. - */ -static inline void *net_buf_pull_mem(struct net_buf *buf, size_t len) -{ - return net_buf_simple_pull_mem(&buf->b, len); -} - -/** - * @brief Remove a 8-bit value from the beginning of the buffer - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 8-bit values. - * - * @param buf A valid pointer on a buffer. - * - * @return The 8-bit removed value - */ -static inline uint8_t net_buf_pull_u8(struct net_buf *buf) -{ - return net_buf_simple_pull_u8(&buf->b); -} - -/** - * @brief Remove and convert 16 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 16-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from little endian to host endian. - */ -static inline uint16_t net_buf_pull_le16(struct net_buf *buf) -{ - return net_buf_simple_pull_le16(&buf->b); -} - -/** - * @brief Remove and convert 16 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 16-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 16-bit value converted from big endian to host endian. - */ -static inline uint16_t net_buf_pull_be16(struct net_buf *buf) -{ - return net_buf_simple_pull_be16(&buf->b); -} - -/** - * @brief Remove and convert 24 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 24-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from little endian to host endian. - */ -static inline uint32_t net_buf_pull_le24(struct net_buf *buf) -{ - return net_buf_simple_pull_le24(&buf->b); -} - -/** - * @brief Remove and convert 24 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 24-bit big endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 24-bit value converted from big endian to host endian. - */ -static inline uint32_t net_buf_pull_be24(struct net_buf *buf) -{ - return net_buf_simple_pull_be24(&buf->b); -} - -/** - * @brief Remove and convert 32 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 32-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 32-bit value converted from little endian to host endian. - */ -static inline uint32_t net_buf_pull_le32(struct net_buf *buf) -{ - return net_buf_simple_pull_le32(&buf->b); -} - -/** - * @brief Remove and convert 32 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 32-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 32-bit value converted from big endian to host endian. - */ -static inline uint32_t net_buf_pull_be32(struct net_buf *buf) -{ - return net_buf_simple_pull_be32(&buf->b); -} - -/** - * @brief Remove and convert 40 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 40-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 40-bit value converted from little endian to host endian. - */ -static inline uint64_t net_buf_pull_le40(struct net_buf *buf) -{ - return net_buf_simple_pull_le40(&buf->b); -} - -/** - * @brief Remove and convert 40 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 40-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 40-bit value converted from big endian to host endian. - */ -static inline uint64_t net_buf_pull_be40(struct net_buf *buf) -{ - return net_buf_simple_pull_be40(&buf->b); -} - -/** - * @brief Remove and convert 48 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 48-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 48-bit value converted from little endian to host endian. - */ -static inline uint64_t net_buf_pull_le48(struct net_buf *buf) -{ - return net_buf_simple_pull_le48(&buf->b); -} - -/** - * @brief Remove and convert 48 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 48-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 48-bit value converted from big endian to host endian. - */ -static inline uint64_t net_buf_pull_be48(struct net_buf *buf) -{ - return net_buf_simple_pull_be48(&buf->b); -} - -/** - * @brief Remove and convert 64 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 64-bit little endian data. - * - * @param buf A valid pointer on a buffer. - * - * @return 64-bit value converted from little endian to host endian. - */ -static inline uint64_t net_buf_pull_le64(struct net_buf *buf) -{ - return net_buf_simple_pull_le64(&buf->b); -} - -/** - * @brief Remove and convert 64 bits from the beginning of the buffer. - * - * Same idea as with net_buf_pull(), but a helper for operating on - * 64-bit big endian data. - * - * @param buf A valid pointer on a buffer - * - * @return 64-bit value converted from big endian to host endian. - */ -static inline uint64_t net_buf_pull_be64(struct net_buf *buf) -{ - return net_buf_simple_pull_be64(&buf->b); -} - -/** - * @brief Check buffer tailroom. - * - * Check how much free space there is at the end of the buffer. - * - * @param buf A valid pointer on a buffer - * - * @return Number of bytes available at the end of the buffer. - */ -static inline size_t net_buf_tailroom(const struct net_buf *buf) -{ - return net_buf_simple_tailroom(&buf->b); -} - -/** - * @brief Check buffer headroom. - * - * Check how much free space there is in the beginning of the buffer. - * - * buf A valid pointer on a buffer - * - * @return Number of bytes available in the beginning of the buffer. - */ -static inline size_t net_buf_headroom(const struct net_buf *buf) -{ - return net_buf_simple_headroom(&buf->b); -} - -/** - * @brief Check maximum net_buf::len value. - * - * This value is depending on the number of bytes being reserved as headroom. - * - * @param buf A valid pointer on a buffer - * - * @return Number of bytes usable behind the net_buf::data pointer. - */ -static inline uint16_t net_buf_max_len(const struct net_buf *buf) -{ - return net_buf_simple_max_len(&buf->b); -} - -/** - * @brief Get the tail pointer for a buffer. - * - * Get a pointer to the end of the data in a buffer. - * - * @param buf Buffer. - * - * @return Tail pointer for the buffer. - */ -static inline uint8_t *net_buf_tail(const struct net_buf *buf) -{ - return net_buf_simple_tail(&buf->b); -} - -/** - * @brief Find the last fragment in the fragment list. - * - * @return Pointer to last fragment in the list. - */ -struct net_buf *net_buf_frag_last(struct net_buf *frags); - -/** - * @brief Insert a new fragment to a chain of bufs. - * - * Insert a new fragment into the buffer fragments list after the parent. - * - * Note: This function takes ownership of the fragment reference so the - * caller is not required to unref. - * - * @param parent Parent buffer/fragment. - * @param frag Fragment to insert. - */ -void net_buf_frag_insert(struct net_buf *parent, struct net_buf *frag); - -/** - * @brief Add a new fragment to the end of a chain of bufs. - * - * Append a new fragment into the buffer fragments list. - * - * Note: This function takes ownership of the fragment reference so the - * caller is not required to unref. - * - * @param head Head of the fragment chain. - * @param frag Fragment to add. - * - * @return New head of the fragment chain. Either head (if head - * was non-NULL) or frag (if head was NULL). - */ -struct net_buf *net_buf_frag_add(struct net_buf *head, struct net_buf *frag); - -/** - * @brief Delete existing fragment from a chain of bufs. - * - * @param parent Parent buffer/fragment, or NULL if there is no parent. - * @param frag Fragment to delete. - * - * @return Pointer to the buffer following the fragment, or NULL if it - * had no further fragments. - */ -#if defined(CONFIG_NET_BUF_LOG) -struct net_buf *net_buf_frag_del_debug(struct net_buf *parent, - struct net_buf *frag, - const char *func, int line); -#define net_buf_frag_del(_parent, _frag) \ - net_buf_frag_del_debug(_parent, _frag, __func__, __LINE__) -#else -struct net_buf *net_buf_frag_del(struct net_buf *parent, struct net_buf *frag); -#endif - -/** - * @brief Copy bytes from net_buf chain starting at offset to linear buffer - * - * Copy (extract) @a len bytes from @a src net_buf chain, starting from @a - * offset in it, to a linear buffer @a dst. Return number of bytes actually - * copied, which may be less than requested, if net_buf chain doesn't have - * enough data, or destination buffer is too small. - * - * @param dst Destination buffer - * @param dst_len Destination buffer length - * @param src Source net_buf chain - * @param offset Starting offset to copy from - * @param len Number of bytes to copy - * @return number of bytes actually copied - */ -size_t net_buf_linearize(void *dst, size_t dst_len, - const struct net_buf *src, size_t offset, size_t len); - -/** - * @typedef net_buf_allocator_cb - * @brief Network buffer allocator callback. - * - * @details The allocator callback is called when net_buf_append_bytes - * needs to allocate a new net_buf. - * - * @param timeout Affects the action taken should the net buf pool be empty. - * If K_NO_WAIT, then return immediately. If K_FOREVER, then - * wait as long as necessary. Otherwise, wait until the specified - * timeout. - * @param user_data The user data given in net_buf_append_bytes call. - * @return pointer to allocated net_buf or NULL on error. - */ -typedef struct net_buf * __must_check (*net_buf_allocator_cb)(k_timeout_t timeout, - void *user_data); - -/** - * @brief Append data to a list of net_buf - * - * @details Append data to a net_buf. If there is not enough space in the - * net_buf then more net_buf will be added, unless there are no free net_buf - * and timeout occurs. If not allocator is provided it attempts to allocate from - * the same pool as the original buffer. - * - * @param buf Network buffer. - * @param len Total length of input data - * @param value Data to be added - * @param timeout Timeout is passed to the net_buf allocator callback. - * @param allocate_cb When a new net_buf is required, use this callback. - * @param user_data A user data pointer to be supplied to the allocate_cb. - * This pointer is can be anything from a mem_pool or a net_pkt, the - * logic is left up to the allocate_cb function. - * - * @return Length of data actually added. This may be less than input - * length if other timeout than K_FOREVER was used, and there - * were no free fragments in a pool to accommodate all data. - */ -size_t net_buf_append_bytes(struct net_buf *buf, size_t len, - const void *value, k_timeout_t timeout, - net_buf_allocator_cb allocate_cb, void *user_data); - -/** - * @brief Match data with a net_buf's content - * - * @details Compare data with a content of a net_buf. Provide information about - * the number of bytes matching between both. If needed, traverse - * through multiple buffer fragments. - * - * @param buf Network buffer - * @param offset Starting offset to compare from - * @param data Data buffer for comparison - * @param len Number of bytes to compare - * - * @return The number of bytes compared before the first difference. - */ -size_t net_buf_data_match(const struct net_buf *buf, size_t offset, const void *data, size_t len); - -/** - * @brief Skip N number of bytes in a net_buf - * - * @details Skip N number of bytes starting from fragment's offset. If the total - * length of data is placed in multiple fragments, this function will skip from - * all fragments until it reaches N number of bytes. Any fully skipped buffers - * are removed from the net_buf list. - * - * @param buf Network buffer. - * @param len Total length of data to be skipped. - * - * @return Pointer to the fragment or - * NULL and pos is 0 after successful skip, - * NULL and pos is 0xffff otherwise. - */ -static inline struct net_buf *net_buf_skip(struct net_buf *buf, size_t len) -{ - while (buf && len--) { - net_buf_pull_u8(buf); - if (!buf->len) { - buf = net_buf_frag_del(NULL, buf); - } - } - - return buf; -} - -/** - * @brief Calculate amount of bytes stored in fragments. - * - * Calculates the total amount of data stored in the given buffer and the - * fragments linked to it. - * - * @param buf Buffer to start off with. - * - * @return Number of bytes in the buffer and its fragments. - */ -static inline size_t net_buf_frags_len(const struct net_buf *buf) -{ - size_t bytes = 0; - - while (buf) { - bytes += buf->len; - buf = buf->frags; - } - - return bytes; -} - -/** - * @} - */ +#include -#ifdef __cplusplus -} -#endif +#warning This header is deprecated, include instead -#endif /* ZEPHYR_INCLUDE_NET_BUF_H_ */ +#endif /* ZEPHYR_INCLUDE_NET_BUF_DEPRECATED_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/capture.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/capture.h index 0a90e444..1ebb3da4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/capture.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/capture.h @@ -23,6 +23,8 @@ extern "C" { /** * @brief Network packet capture support functions * @defgroup net_capture Network packet capture + * @since 2.6 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap.h index 44ffed7a..09df1e98 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap.h @@ -64,6 +64,7 @@ enum coap_option_num { COAP_OPTION_PROXY_SCHEME = 39, /**< Proxy-Scheme */ COAP_OPTION_SIZE1 = 60, /**< Size1 */ COAP_OPTION_ECHO = 252, /**< Echo (RFC 9175) */ + COAP_OPTION_NO_RESPONSE = 258, /**< No-Response (RFC 7967) */ COAP_OPTION_REQUEST_TAG = 292 /**< Request-Tag (RFC 9175) */ }; @@ -222,6 +223,22 @@ enum coap_content_format { COAP_CONTENT_FORMAT_APP_CBOR = 60 /**< application/cbor */ }; +/** + * @brief Set of No-Response option values for CoAP. + * + * To be used when encoding or decoding a No-Response option defined + * in RFC 7967. + */ +enum coap_no_response { + COAP_NO_RESPONSE_SUPPRESS_2_XX = 0x02, + COAP_NO_RESPONSE_SUPPRESS_4_XX = 0x08, + COAP_NO_RESPONSE_SUPPRESS_5_XX = 0x10, + + COAP_NO_RESPONSE_SUPPRESS_ALL = COAP_NO_RESPONSE_SUPPRESS_2_XX | + COAP_NO_RESPONSE_SUPPRESS_4_XX | + COAP_NO_RESPONSE_SUPPRESS_5_XX, +}; + /** @cond INTERNAL_HIDDEN */ /* block option helper */ @@ -338,8 +355,15 @@ typedef int (*coap_reply_t)(const struct coap_packet *response, * @brief CoAP transmission parameters. */ struct coap_transmission_parameters { - /** Initial ACK timeout. Value is used as a base value to retry pending CoAP packets. */ + /** Initial ACK timeout. Value is used as a base value to retry pending CoAP packets. */ uint32_t ack_timeout; +#if defined(CONFIG_COAP_RANDOMIZE_ACK_TIMEOUT) || defined(__DOXYGEN__) + /** + * Set CoAP ack random factor. A value of 150 means a factor of 1.5. A value of 0 defaults + * to @kconfig{CONFIG_COAP_ACK_RANDOM_PERCENT}. The value must be >= 100. + */ + uint16_t ack_random_percent; +#endif /* defined(CONFIG_COAP_RANDOMIZE_ACK_TIMEOUT) */ /** Set CoAP retry backoff factor. A value of 200 means a factor of 2.0. */ uint16_t coap_backoff_percent; /** Maximum number of retransmissions. */ @@ -528,6 +552,21 @@ int coap_packet_init(struct coap_packet *cpkt, uint8_t *data, uint16_t max_len, int coap_ack_init(struct coap_packet *cpkt, const struct coap_packet *req, uint8_t *data, uint16_t max_len, uint8_t code); +/** + * @brief Create a new CoAP Reset message for given request. + * + * This function works like @ref coap_packet_init, filling CoAP header type, + * and CoAP header message id fields. + * + * @param cpkt New packet to be initialized using the storage from @a data. + * @param req CoAP request packet that is being acknowledged + * @param data Data that will contain a CoAP packet information + * @param max_len Maximum allowable length of data + * + * @return 0 in case of success or negative in case of error. + */ +int coap_rst_init(struct coap_packet *cpkt, const struct coap_packet *req, + uint8_t *data, uint16_t max_len); /** * @brief Returns a randomly generated array of 8 bytes, that can be * used as a message's token. @@ -887,21 +926,22 @@ int coap_get_option_int(const struct coap_packet *cpkt, uint16_t code); * @return Integer value of the block size in case of success * or negative in case of error. */ -int coap_get_block1_option(const struct coap_packet *cpkt, bool *has_more, uint8_t *block_number); +int coap_get_block1_option(const struct coap_packet *cpkt, bool *has_more, uint32_t *block_number); /** * @brief Get values from CoAP block2 option. * - * Decode block number and block size from option. Ignore the has_more flag - * as it should always be zero on queries. + * Decode block number, more flag and block size from option. * * @param cpkt Packet to be inspected + * @param has_more Is set to the value of the more flag * @param block_number Is set to the number of the block * * @return Integer value of the block size in case of success * or negative in case of error. */ -int coap_get_block2_option(const struct coap_packet *cpkt, uint8_t *block_number); +int coap_get_block2_option(const struct coap_packet *cpkt, bool *has_more, + uint32_t *block_number); /** * @brief Retrieves BLOCK{1,2} and SIZE{1,2} from @a cpkt and updates diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_client.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_client.h index a3576a24..ce09c56d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_client.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_client.h @@ -15,6 +15,8 @@ /** * @brief CoAP client API * @defgroup coap_client CoAP client API + * @since 3.4 + * @version 0.1.0 * @ingroup networking * @{ */ @@ -51,16 +53,16 @@ typedef void (*coap_client_response_cb_t)(int16_t result_code, * @brief Representation of a CoAP client request. */ struct coap_client_request { - enum coap_method method; /**< Method of the request */ - bool confirmable; /**< CoAP Confirmable/Non-confirmable message */ - const char *path; /**< Path of the requested resource */ - enum coap_content_format fmt; /**< Content format to be used */ - uint8_t *payload; /**< User allocated buffer for send request */ - size_t len; /**< Length of the payload */ - coap_client_response_cb_t cb; /**< Callback when response received */ - struct coap_client_option *options; /**< Extra options to be added to request */ - uint8_t num_options; /**< Number of extra options */ - void *user_data; /**< User provided context */ + enum coap_method method; /**< Method of the request */ + bool confirmable; /**< CoAP Confirmable/Non-confirmable message */ + const char *path; /**< Path of the requested resource */ + enum coap_content_format fmt; /**< Content format to be used */ + const uint8_t *payload; /**< User allocated buffer for send request */ + size_t len; /**< Length of the payload */ + coap_client_response_cb_t cb; /**< Callback when response received */ + const struct coap_client_option *options; /**< Extra options to be added to request */ + uint8_t num_options; /**< Number of extra options */ + void *user_data; /**< User provided context */ }; /** @@ -86,7 +88,7 @@ struct coap_client_option { struct coap_client_internal_request { uint8_t request_token[COAP_TOKEN_MAX_LEN]; uint32_t offset; - uint32_t last_id; + uint16_t last_id; uint8_t request_tkl; bool request_ongoing; atomic_t in_callback; @@ -106,8 +108,7 @@ struct coap_client { int fd; struct sockaddr address; socklen_t socklen; - bool response_ready; - struct k_mutex send_mutex; + struct k_mutex lock; uint8_t send_buf[MAX_COAP_MSG_LEN]; uint8_t recv_buf[MAX_COAP_MSG_LEN]; struct coap_client_internal_request requests[CONFIG_COAP_CLIENT_MAX_REQUESTS]; @@ -157,6 +158,43 @@ int coap_client_req(struct coap_client *client, int sock, const struct sockaddr */ void coap_client_cancel_requests(struct coap_client *client); +/** + * @brief Cancel matching requests. + * + * This function cancels all CoAP client request that matches the given request. + * The request is matched based on the method, path, callback and user_data, if provided. + * Any field set to NULL is considered a wildcard. + * + * (struct coap_client_request){0} cancels all requests. + * (struct coap_client_request){.method = COAP_METHOD_GET} cancels all GET requests. + * + * @param client Pointer to the CoAP client instance. + * @param req Pointer to the CoAP client request to be canceled. + */ +void coap_client_cancel_request(struct coap_client *client, struct coap_client_request *req); + +/** + * @brief Initialise a Block2 option to be added to a request + * + * If the application expects a request to require a blockwise transfer, it may pre-emptively + * suggest a maximum block size to the server - see RFC7959 Figure 3: Block-Wise GET with Early + * Negotiation. + * + * This helper function returns a Block2 option to send with the initial request. + * + * @return CoAP client initial Block2 option structure + */ +static inline struct coap_client_option coap_client_option_initial_block2(void) +{ + struct coap_client_option block2 = { + .code = COAP_OPTION_BLOCK2, + .len = 1, + .value[0] = coap_bytes_to_block_size(CONFIG_COAP_CLIENT_BLOCK_SIZE), + }; + + return block2; +} + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_mgmt.h index a52293a9..7997d1e9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_mgmt.h @@ -21,6 +21,8 @@ extern "C" { /** * @brief CoAP Manager Events * @defgroup coap_mgmt CoAP Manager Events + * @since 3.6 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_service.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_service.h index b894fecf..f5bf3f84 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_service.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/coap_service.h @@ -23,6 +23,8 @@ extern "C" { /** * @brief CoAP Service API * @defgroup coap_service CoAP service API + * @since 3.6 + * @version 0.1.0 * @ingroup networking * @{ */ @@ -57,7 +59,7 @@ struct coap_service { }; #define __z_coap_service_define(_name, _host, _port, _flags, _res_begin, _res_end) \ - static struct coap_service_data coap_service_data_##_name = { \ + static struct coap_service_data _CONCAT(coap_service_data_, _name) = { \ .sock_fd = -1, \ }; \ const STRUCT_SECTION_ITERABLE(coap_service, _name) = { \ @@ -67,7 +69,7 @@ struct coap_service { .flags = _flags, \ .res_begin = (_res_begin), \ .res_end = (_res_end), \ - .data = &coap_service_data_##_name, \ + .data = &_CONCAT(coap_service_data_, _name), \ } /** @endcond */ @@ -109,8 +111,8 @@ struct coap_service { * @param _service Name of the associated service. */ #define COAP_RESOURCE_DEFINE(_name, _service, ...) \ - STRUCT_SECTION_ITERABLE_ALTERNATE(coap_resource_##_service, coap_resource, _name) \ - = __VA_ARGS__ + STRUCT_SECTION_ITERABLE_ALTERNATE(_CONCAT(coap_resource_, _service), coap_resource, \ + _name) = __VA_ARGS__ /** * @brief Define a CoAP service with static resources. @@ -130,11 +132,11 @@ struct coap_service { * @param _flags Configuration flags @see @ref COAP_SERVICE_FLAGS. */ #define COAP_SERVICE_DEFINE(_name, _host, _port, _flags) \ - extern struct coap_resource _CONCAT(_coap_resource_##_name, _list_start)[]; \ - extern struct coap_resource _CONCAT(_coap_resource_##_name, _list_end)[]; \ + extern struct coap_resource _CONCAT(_CONCAT(_coap_resource_, _name), _list_start)[]; \ + extern struct coap_resource _CONCAT(_CONCAT(_coap_resource_, _name), _list_end)[]; \ __z_coap_service_define(_name, _host, _port, _flags, \ - &_CONCAT(_coap_resource_##_name, _list_start)[0], \ - &_CONCAT(_coap_resource_##_name, _list_end)[0]) + &_CONCAT(_CONCAT(_coap_resource_, _name), _list_start)[0], \ + &_CONCAT(_CONCAT(_coap_resource_, _name), _list_end)[0]) /** * @brief Count the number of CoAP services. @@ -175,7 +177,7 @@ struct coap_service { * @param _it Name of iterator (of type @ref coap_resource) */ #define COAP_RESOURCE_FOREACH(_service, _it) \ - STRUCT_SECTION_FOREACH_ALTERNATE(coap_resource_##_service, coap_resource, _it) + STRUCT_SECTION_FOREACH_ALTERNATE(_CONCAT(coap_resource_, _service), coap_resource, _it) /** * @brief Iterate over all static resources associated with @p _service . diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity.h index 7e8ab1ea..4f3da6b4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity.h @@ -255,7 +255,9 @@ int conn_mgr_if_set_timeout(struct net_if *iface, int timeout); /** * @brief Connection Manager Bulk API * @defgroup conn_mgr_connectivity_bulk Connection Manager Connectivity Bulk API - * @ingroup networking + * @since 3.4 + * @version 0.1.0 + * @ingroup conn_mgr_connectivity * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity_impl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity_impl.h index 49070685..644a0b89 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity_impl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_connectivity_impl.h @@ -26,7 +26,9 @@ extern "C" { /** * @brief Connection Manager Connectivity Implementation API * @defgroup conn_mgr_connectivity_impl Connection Manager Connectivity Implementation API - * @ingroup networking + * @since 3.4 + * @version 0.1.0 + * @ingroup conn_mgr_connectivity * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_monitor.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_monitor.h index 16a873b7..5cf3efa4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_monitor.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/conn_mgr_monitor.h @@ -21,6 +21,8 @@ extern "C" { /** * @brief Connection Manager API * @defgroup conn_mgr Connection Manager API + * @since 2.0 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4.h index 925c4e13..fee4a169 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4.h @@ -21,6 +21,8 @@ extern "C" { /** * @brief DHCPv4 * @defgroup dhcpv4 DHCPv4 + * @since 1.7 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4_server.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4_server.h index 18c4af11..1cd0bbdb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4_server.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv4_server.h @@ -21,6 +21,8 @@ extern "C" { /** * @brief DHCPv4 server * @defgroup dhcpv4_server DHCPv4 server + * @since 3.6 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -107,6 +109,34 @@ int net_dhcpv4_server_foreach_lease(struct net_if *iface, net_dhcpv4_lease_cb_t cb, void *user_data); +/** + * @typedef net_dhcpv4_server_provider_cb_t + * @brief Callback used to let application provide an address for a given + * client ID + * @details This function is called before assigning an address to a client, + * and lets the application override the address for a given client. If the + * callback returns 0, addr needs to be a valid address and will be assigned + * to the client. If the callback returns anything non-zero, the client will + * be assigned an address from the pool. + * + * @param iface Pointer to the network interface + * @param client_id Pointer to client requesting an address + * @param addr Address to be assigned to client + * @param user_data A valid pointer to user data or NULL + */ +typedef int (*net_dhcpv4_server_provider_cb_t)(struct net_if *iface, + const struct dhcpv4_client_id *client_id, + struct in_addr *addr, + void *user_data); +/** + * @brief Set the callback used to provide addresses to the DHCP server. + * + * @param cb User-supplied callback function to call + * @param user_data A valid pointer to user data or NULL + */ +void net_dhcpv4_server_set_provider_cb(net_dhcpv4_server_provider_cb_t cb, + void *user_data); + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv6.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv6.h index 715b8cae..ad3c586c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv6.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dhcpv6.h @@ -18,6 +18,8 @@ extern "C" { /** * @brief DHCPv6 * @defgroup dhcpv6 DHCPv6 + * @since 3.5 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_resolve.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_resolve.h index 36983f0b..33398dab 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_resolve.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_resolve.h @@ -25,6 +25,8 @@ extern "C" { /** * @brief DNS resolving library * @defgroup dns_resolve DNS Resolve Library + * @since 1.8 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -139,9 +141,9 @@ enum dns_query_type { /** How many sockets the dispatcher is able to poll. */ #define DNS_DISPATCHER_MAX_POLL (DNS_RESOLVER_MAX_POLL + MDNS_MAX_POLL + LLMNR_MAX_POLL) -#if defined(CONFIG_NET_SOCKETS_POLL_MAX) -BUILD_ASSERT(CONFIG_NET_SOCKETS_POLL_MAX >= DNS_DISPATCHER_MAX_POLL, - "CONFIG_NET_SOCKETS_POLL_MAX must be larger than " STRINGIFY(DNS_DISPATCHER_MAX_POLL)); +#if defined(CONFIG_ZVFS_POLL_MAX) +BUILD_ASSERT(CONFIG_ZVFS_POLL_MAX >= DNS_DISPATCHER_MAX_POLL, + "CONFIG_ZVFS_POLL_MAX must be larger than " STRINGIFY(DNS_DISPATCHER_MAX_POLL)); #endif /** @brief What is the type of the socket given to DNS socket dispatcher, @@ -200,6 +202,8 @@ struct dns_socket_dispatcher { int fds_len; /** Local socket to dispatch */ int sock; + /** Interface we are bound to */ + int ifindex; /** There can be two contexts to dispatch. This points to the other * context if sharing the socket between resolver / responder. */ @@ -340,6 +344,11 @@ struct dns_resolve_context { /** Connection to the DNS server */ int sock; + /** Network interface index if the DNS resolving should be done + * via this interface. Value 0 indicates any interface can be used. + */ + int if_index; + /** Is this server mDNS one */ uint8_t is_mdns : 1; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_sd.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_sd.h index 6e4f9fcb..97548199 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_sd.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dns_sd.h @@ -13,6 +13,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -29,6 +30,8 @@ extern "C" { * @see RFC 6763 * * @defgroup dns_sd DNS Service Discovery + * @since 2.5 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -128,18 +131,15 @@ extern "C" { * Example (with TXT): * @code{.c} * #include - * static const bar_txt[] = { + * static const char bar_txt[] = { * "\x06" "path=/" * "\x0f" "this=is the way" * "\x0e" "foo or=foo not" * "\x17" "this=has\0embedded\0nulls" * "\x04" "true" * }; - * // Possibly use an ephemeral port - * // Possibly only assign bar_port when the service is running - * static uint16_t bar_port; * DNS_SD_REGISTER_TCP_SERVICE(bar, CONFIG_NET_HOSTNAME, - * "_bar", "local", bar_txt, &bar_port); + * "_bar", "local", bar_txt, 4242); * @endcode * * TXT records begin with a single length byte (hex-encoded) @@ -174,10 +174,8 @@ extern "C" { * Example (no TXT): * @code{.c} * #include - * #include - * static const foo_port = sys_cpu_to_be16(4242); * DNS_SD_REGISTER_UDP_SERVICE(foo, CONFIG_NET_HOSTNAME, - * "_foo", DNS_SD_EMPTY_TXT, &foo_port); + * "_foo", "local", DNS_SD_EMPTY_TXT, 4242); * @endcode * * @param id variable name for the DNS-SD service record diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dsa.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dsa.h index 1aed17e1..db81a5e3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dsa.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dsa.h @@ -17,6 +17,8 @@ /** * @brief DSA definitions and helpers * @defgroup DSA Distributed Switch Architecture definitions and helpers + * @since 2.5 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dummy.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dummy.h index 4c5fe031..926f9edc 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dummy.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/dummy.h @@ -23,6 +23,8 @@ extern "C" { /** * @brief Dummy L2/driver support functions * @defgroup dummy Dummy L2/driver Support Functions + * @since 1.14 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet.h index be9ed7ce..c870525c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet.h @@ -41,6 +41,8 @@ extern "C" { /** * @brief Ethernet support functions * @defgroup ethernet Ethernet Support Functions + * @since 1.0 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -202,6 +204,12 @@ enum ethernet_hw_caps { /** TX-Injection supported */ ETHERNET_TXINJECTION_MODE = BIT(20), + + /** 2.5 Gbits link supported */ + ETHERNET_LINK_2500BASE_T = BIT(21), + + /** 5 Gbits link supported */ + ETHERNET_LINK_5000BASE_T = BIT(22), }; /** @cond INTERNAL_HIDDEN */ @@ -572,6 +580,9 @@ struct ethernet_api { const struct device *(*get_ptp_clock)(const struct device *dev); #endif /* CONFIG_PTP_CLOCK */ + /** Return PHY device that is tied to this ethernet device */ + const struct device *(*get_phy)(const struct device *dev); + /** Send a network packet */ int (*send)(const struct device *dev, struct net_pkt *pkt); }; @@ -648,7 +659,7 @@ struct ethernet_context { atomic_t flags; #if defined(CONFIG_NET_ETHERNET_BRIDGE) - struct eth_bridge_iface_context bridge; + struct net_if *bridge; #endif /** Carrier ON/OFF handler worker. This is used to create @@ -928,14 +939,14 @@ void net_eth_ipv6_mcast_to_mac_addr(const struct in6_addr *ipv6_addr, static inline enum ethernet_hw_caps net_eth_get_hw_capabilities(struct net_if *iface) { - const struct ethernet_api *eth = - (struct ethernet_api *)net_if_get_device(iface)->api; + const struct device *dev = net_if_get_device(iface); + const struct ethernet_api *api = (struct ethernet_api *)dev->api; - if (!eth->get_capabilities) { + if (!api || !api->get_capabilities) { return (enum ethernet_hw_caps)0; } - return eth->get_capabilities(net_if_get_device(iface)); + return api->get_capabilities(dev); } /** @@ -1296,6 +1307,16 @@ int net_eth_txinjection_mode(struct net_if *iface, bool enable); */ int net_eth_mac_filter(struct net_if *iface, struct net_eth_addr *mac, enum ethernet_filter_type type, bool enable); + +/** + * @brief Return the PHY device that is tied to this ethernet network interface. + * + * @param iface Network interface + * + * @return Pointer to PHY device if found, NULL if not found. + */ +const struct device *net_eth_get_phy(struct net_if *iface); + /** * @brief Return PTP clock that is tied to this ethernet network interface. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_bridge.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_bridge.h index fa2ca546..329e218d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_bridge.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_bridge.h @@ -8,6 +8,7 @@ /* * Copyright (c) 2021 BayLibre SAS + * Copyright (c) 2024 Nordic Semiconductor * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,48 +26,44 @@ extern "C" { /** * @brief Ethernet Bridging API * @defgroup eth_bridge Ethernet Bridging API + * @since 2.7 + * @version 0.8.0 * @ingroup networking * @{ */ /** @cond INTERNAL_HIDDEN */ -struct eth_bridge { +#if defined(CONFIG_NET_ETHERNET_BRIDGE) +#define NET_ETHERNET_BRIDGE_ETH_INTERFACE_COUNT CONFIG_NET_ETHERNET_BRIDGE_ETH_INTERFACE_COUNT +#else +#define NET_ETHERNET_BRIDGE_ETH_INTERFACE_COUNT 1 +#endif + +struct eth_bridge_iface_context { + /* Lock to protect access to interface array below */ struct k_mutex lock; - sys_slist_t interfaces; - sys_slist_t listeners; - bool initialized; -}; -#define ETH_BRIDGE_INITIALIZER(obj) \ - { \ - .lock = { }, \ - .interfaces = SYS_SLIST_STATIC_INIT(&obj.interfaces), \ - .listeners = SYS_SLIST_STATIC_INIT(&obj.listeners), \ - } + /* The actual bridge virtual interface */ + struct net_if *iface; -/** @endcond */ + /* What Ethernet interfaces are bridged together */ + struct net_if *eth_iface[NET_ETHERNET_BRIDGE_ETH_INTERFACE_COUNT]; -/** - * @brief Statically define and initialize a bridge instance. - * - * @param name Name of the bridge object - */ -#define ETH_BRIDGE_INIT(name) \ - STRUCT_SECTION_ITERABLE(eth_bridge, name) = \ - ETH_BRIDGE_INITIALIZER(name) + /* How many interfaces are bridged atm */ + size_t count; -/** @cond INTERNAL_HIDDEN */ + /* Bridge instance id */ + int id; -struct eth_bridge_iface_context { - sys_snode_t node; - struct eth_bridge *instance; - bool allow_tx; -}; + /* Is the bridge interface initialized */ + bool is_init : 1; + + /* Has user configured the bridge */ + bool is_setup : 1; -struct eth_bridge_listener { - sys_snode_t node; - struct k_fifo pkt_queue; + /* Is the interface enabled or not */ + bool status : 1; }; /** @endcond */ @@ -75,77 +72,32 @@ struct eth_bridge_listener { * @brief Add an Ethernet network interface to a bridge * * This adds a network interface to a bridge. The interface is then put - * into promiscuous mode, all packets received by this interface are sent - * to the bridge, and any other packets sent to the bridge (with some - * exceptions) are transmitted via this interface. - * - * For transmission from the bridge to occur via this interface, it is - * necessary to enable TX mode with eth_bridge_iface_tx(). TX mode is - * initially disabled. + * into promiscuous mode. After more than one Ethernet interfaces are + * added to the bridge interface, the bridge interface is setup. + * After the setup is done, the bridge interface can be brought up so + * that it can start bridging L2 traffic. * - * Once an interface is added to a bridge, all its incoming traffic is - * diverted to the bridge. However, packets sent out with net_if_queue_tx() - * via this interface are not subjected to the bridge. - * - * @param br A pointer to an initialized bridge object + * @param br A pointer to a bridge interface * @param iface Interface to add * * @return 0 if OK, negative error code otherwise. */ -int eth_bridge_iface_add(struct eth_bridge *br, struct net_if *iface); +int eth_bridge_iface_add(struct net_if *br, struct net_if *iface); /** - * @brief Remove an Ethernet network interface from a bridge + * @brief Remove an Ethernet network interface from a bridge. * - * @param br A pointer to an initialized bridge object - * @param iface Interface to remove + * If the bridge interface setup has only one Ethernet interface left + * after this function call, the bridge is disabled as it cannot bridge + * the L2 traffic any more. The bridge interface is left in UP state + * if this case. * - * @return 0 if OK, negative error code otherwise. - */ -int eth_bridge_iface_remove(struct eth_bridge *br, struct net_if *iface); - -/** - * @brief Enable/disable transmission mode for a bridged interface - * - * When TX mode is off, the interface may receive packets and send them to - * the bridge but no packets coming from the bridge will be sent through this - * interface. When TX mode is on, both incoming and outgoing packets are - * allowed. - * - * @param iface Interface to configure - * @param allow true to activate TX mode, false otherwise - * - * @return 0 if OK, negative error code otherwise. - */ -int eth_bridge_iface_allow_tx(struct net_if *iface, bool allow); - -/** - * @brief Add (register) a listener to the bridge - * - * This lets a software listener register a pointer to a provided FIFO for - * receiving packets sent to the bridge. The listener is responsible for - * emptying the FIFO with k_fifo_get() which will return a struct net_pkt - * pointer, and releasing the packet with net_pkt_unref() when done with it. - * - * The listener wishing not to receive any more packets should simply - * unregister itself with eth_bridge_listener_remove(). - * - * @param br A pointer to an initialized bridge object - * @param l A pointer to an initialized listener instance. - * - * @return 0 if OK, negative error code otherwise. - */ -int eth_bridge_listener_add(struct eth_bridge *br, struct eth_bridge_listener *l); - -/** - * @brief Remove (unregister) a listener from the bridge - * - * @param br A pointer to an initialized bridge object - * @param l A pointer to the listener instance to be removed. + * @param br A pointer to a bridge interface + * @param iface Interface to remove * * @return 0 if OK, negative error code otherwise. */ -int eth_bridge_listener_remove(struct eth_bridge *br, struct eth_bridge_listener *l); +int eth_bridge_iface_remove(struct net_if *br, struct net_if *iface); /** * @brief Get bridge index according to pointer @@ -154,28 +106,28 @@ int eth_bridge_listener_remove(struct eth_bridge *br, struct eth_bridge_listener * * @return Bridge index */ -int eth_bridge_get_index(struct eth_bridge *br); +int eth_bridge_get_index(struct net_if *br); /** * @brief Get bridge instance according to index * * @param index Bridge instance index * - * @return Pointer to bridge instance or NULL if not found. + * @return Pointer to bridge interface or NULL if not found. */ -struct eth_bridge *eth_bridge_get_by_index(int index); +struct net_if *eth_bridge_get_by_index(int index); /** * @typedef eth_bridge_cb_t * @brief Callback used while iterating over bridge instances * - * @param br Pointer to bridge instance + * @param br Pointer to bridge context instance * @param user_data User supplied data */ -typedef void (*eth_bridge_cb_t)(struct eth_bridge *br, void *user_data); +typedef void (*eth_bridge_cb_t)(struct eth_bridge_iface_context *br, void *user_data); /** - * @brief Go through all the bridge instances in order to get + * @brief Go through all the bridge context instances in order to get * information about them. This is mainly useful in * net-shell to print data about currently active bridges. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_mgmt.h index ae339b68..d92f39bc 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_mgmt.h @@ -22,6 +22,8 @@ extern "C" { /** * @brief Ethernet library * @defgroup ethernet_mgmt Ethernet Library + * @since 1.12 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_vlan.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_vlan.h index 3a8a2f5c..ba969954 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_vlan.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ethernet_vlan.h @@ -16,6 +16,8 @@ /** * @brief VLAN definitions and helpers * @defgroup vlan_api Virtual LAN definitions and helpers + * @since 1.12 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/gptp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/gptp.h index 488583e4..87533e8b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/gptp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/gptp.h @@ -16,6 +16,8 @@ /** * @brief generic Precision Time Protocol (gPTP) support * @defgroup gptp gPTP support + * @since 1.13 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hdlc_rcp_if/hdlc_rcp_if.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hdlc_rcp_if/hdlc_rcp_if.h new file mode 100644 index 00000000..d26bf12b --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hdlc_rcp_if/hdlc_rcp_if.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Public APIs of HDLC RCP communication Interface + * + * This file provide the HDLC APIs to be used by an RCP host + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief OT RCP HDLC RX callback function. + * + * @note This function is called in the radio spinel HDLC level + */ +typedef void (*hdlc_rx_callback_t)(uint8_t *data, uint16_t len, void *param); + +/** HDLC interface configuration data. */ +struct hdlc_api { + /** + * @brief HDLC interface API + */ + struct net_if_api iface_api; + + /** + * @brief Register the Spinel HDLC RX callback. + * + * @param hdlc_rx_callback pointer to the spinel HDLC RX callback + * @param param pointer to the spinel HDLC interface + * + * @retval 0 The callback was successfully registered. + * @retval -EIO The callback could not be registered. + */ + int (*register_rx_cb)(hdlc_rx_callback_t hdlc_rx_callback, void *param); + + /** + * @brief Transmit a HDLC frame + * + * + * @param frame pointer to the HDLC frame to be transmitted. + * @param length length of the HDLC frame to be transmitted. + + * @retval 0 The frame was successfully sent. + * @retval -EIO The frame could not be sent due to some unspecified + * interface error (e.g. the interface being busy). + */ + int (*send)(const uint8_t *frame, uint16_t length); + + /** + * @brief Deinitialize the device. + * + * @param none + * + * @retval 0 The interface was successfully stopped. + * @retval -EIO The interface could not be stopped. + */ + int (*deinit)(void); +}; + +/* Make sure that the interface API is properly setup inside + * HDLC interface API struct (it is the first one). + */ +BUILD_ASSERT(offsetof(struct hdlc_api, iface_api) == 0); + +#ifdef __cplusplus +} +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hostname.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hostname.h index 4e801ffb..f187427a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hostname.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/hostname.h @@ -18,6 +18,8 @@ extern "C" { /** * @brief Network hostname configuration library * @defgroup net_hostname Network Hostname Library + * @since 1.10 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -92,11 +94,12 @@ static inline void net_hostname_init(void) /** * @brief Set the device hostname postfix * - * @details Set the device hostname to some value. This is only used if + * @details Convert the hostname postfix to hexadecimal value and set the + * device hostname with the converted value. This is only used if * CONFIG_NET_HOSTNAME_UNIQUE is set. * * @param hostname_postfix Usually link address. The function will convert this - * to a string. + * to a hexadecimal string. * @param postfix_len Length of the hostname_postfix array. * * @return 0 if ok, <0 if error @@ -114,6 +117,33 @@ static inline int net_hostname_set_postfix(const uint8_t *hostname_postfix, } #endif /* CONFIG_NET_HOSTNAME_UNIQUE */ +/** + * @brief Set the postfix string for the network hostname. + * + * @details Set the hostname postfix string for the network hostname as is, without any conversion. + * This is only used if CONFIG_NET_HOSTNAME_UNIQUE is set. The function checks if the combined + * length of the default hostname (defined by CONFIG_NET_HOSTNAME) and the postfix does not exceed + * NET_HOSTNAME_MAX_LEN. If the postfix is too long, the function returns an + * error. + * + * @param hostname_postfix Pointer to the postfix string to be appended to the network hostname. + * @param postfix_len Length of the hostname_postfix array. + * + * @return 0 if ok, <0 if error + */ +#if defined(CONFIG_NET_HOSTNAME_UNIQUE) +int net_hostname_set_postfix_str(const uint8_t *hostname_postfix, + int postfix_len); +#else +static inline int net_hostname_set_postfix_str(const uint8_t *hostname_postfix, + int postfix_len) +{ + ARG_UNUSED(hostname_postfix); + ARG_UNUSED(postfix_len); + return -EMSGSIZE; +} +#endif /* CONFIG_NET_HOSTNAME_UNIQUE */ + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/hpack.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/hpack.h index 0a85cf7c..e9d75ce9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/hpack.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/hpack.h @@ -18,6 +18,8 @@ /** * @brief HTTP HPACK * @defgroup http_hpack HTTP HPACK + * @since 3.7 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/method.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/method.h index 30f4aaee..9bcad986 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/method.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/method.h @@ -14,6 +14,8 @@ /** * @brief HTTP request methods * @defgroup http_methods HTTP request methods + * @since 3.3 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/server.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/server.h index 88ca9d27..4cb40e52 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/server.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/server.h @@ -14,6 +14,8 @@ * @brief HTTP server API * * @defgroup http_server HTTP server API + * @since 3.7 + * @version 0.1.0 * @ingroup networking * @{ */ @@ -23,7 +25,9 @@ #include #include #include +#include #include +#include #ifdef __cplusplus extern "C" { @@ -36,17 +40,22 @@ extern "C" { #define HTTP_SERVER_MAX_STREAMS CONFIG_HTTP_SERVER_MAX_STREAMS #define HTTP_SERVER_MAX_CONTENT_TYPE_LEN CONFIG_HTTP_SERVER_MAX_CONTENT_TYPE_LENGTH #define HTTP_SERVER_MAX_URL_LENGTH CONFIG_HTTP_SERVER_MAX_URL_LENGTH +#define HTTP_SERVER_MAX_HEADER_LEN CONFIG_HTTP_SERVER_MAX_HEADER_LEN #else #define HTTP_SERVER_CLIENT_BUFFER_SIZE 0 #define HTTP_SERVER_MAX_STREAMS 0 #define HTTP_SERVER_MAX_CONTENT_TYPE_LEN 0 #define HTTP_SERVER_MAX_URL_LENGTH 0 +#define HTTP_SERVER_MAX_HEADER_LEN 0 #endif -/* Maximum header field name / value length. This is only used to detect Upgrade and - * websocket header fields and values in the http1 server so the value is quite short. - */ -#define HTTP_SERVER_MAX_HEADER_LEN 32 +#if defined(CONFIG_HTTP_SERVER_CAPTURE_HEADERS) +#define HTTP_SERVER_CAPTURE_HEADER_BUFFER_SIZE CONFIG_HTTP_SERVER_CAPTURE_HEADER_BUFFER_SIZE +#define HTTP_SERVER_CAPTURE_HEADER_COUNT CONFIG_HTTP_SERVER_CAPTURE_HEADER_COUNT +#else +#define HTTP_SERVER_CAPTURE_HEADER_BUFFER_SIZE 0 +#define HTTP_SERVER_CAPTURE_HEADER_COUNT 0 +#endif #define HTTP2_PREFACE "PRI * HTTP/2.0\r\n\r\nSM\r\n\r\n" @@ -59,6 +68,9 @@ enum http_resource_type { /** Static resource, cannot be modified on runtime. */ HTTP_RESOURCE_TYPE_STATIC, + /** serves static gzipped files from a filesystem */ + HTTP_RESOURCE_TYPE_STATIC_FS, + /** Dynamic resource, server interacts with the application via registered * @ref http_resource_dynamic_cb_t. */ @@ -115,6 +127,37 @@ struct http_resource_detail_static { BUILD_ASSERT(offsetof(struct http_resource_detail_static, common) == 0); /** @endcond */ +/** + * @brief Representation of a static filesystem server resource. + */ +struct http_resource_detail_static_fs { + /** Common resource details. */ + struct http_resource_detail common; + + /** Path in the local filesystem */ + const char *fs_path; +}; + +/** @cond INTERNAL_HIDDEN */ +/* Make sure that the common is the first in the struct. */ +BUILD_ASSERT(offsetof(struct http_resource_detail_static_fs, common) == 0); +/** @endcond */ + +struct http_content_type { + const char *extension; + size_t extension_len; + const char *content_type; +}; + +#define HTTP_SERVER_CONTENT_TYPE(_extension, _content_type) \ + const STRUCT_SECTION_ITERABLE(http_content_type, _extension) = { \ + .extension = STRINGIFY(_extension), \ + .extension_len = sizeof(STRINGIFY(_extension)) - 1, \ + .content_type = _content_type, \ + }; + +#define HTTP_SERVER_CONTENT_TYPE_FOREACH(_it) STRUCT_SECTION_FOREACH(http_content_type, _it) + struct http_client_ctx; /** Indicates the status of the currently processed piece of data. */ @@ -127,6 +170,38 @@ enum http_data_status { HTTP_SERVER_DATA_FINAL = 1, }; +/** @brief Status of captured request headers */ +enum http_header_status { + HTTP_HEADER_STATUS_OK, /**< All available headers were successfully captured. */ + HTTP_HEADER_STATUS_DROPPED, /**< One or more headers were dropped due to lack of space. */ + HTTP_HEADER_STATUS_NONE, /**< No header status is available. */ +}; + +/** @brief HTTP header representation */ +struct http_header { + const char *name; /**< Pointer to header name NULL-terminated string. */ + const char *value; /**< Pointer to header value NULL-terminated string. */ +}; + +/** @brief HTTP request context */ +struct http_request_ctx { + uint8_t *data; /**< HTTP request data */ + size_t data_len; /**< Length of HTTP request data */ + struct http_header *headers; /**< Array of HTTP request headers */ + size_t header_count; /**< Array length of HTTP request headers */ + enum http_header_status headers_status; /**< Status of HTTP request headers */ +}; + +/** @brief HTTP response context */ +struct http_response_ctx { + enum http_status status; /**< HTTP status code to include in response */ + const struct http_header *headers; /**< Array of HTTP headers */ + size_t header_count; /**< Length of headers array */ + const uint8_t *body; /**< Pointer to body data */ + size_t body_len; /**< Length of body data */ + bool final_chunk; /**< Flag set to true when the application has no more data to send */ +}; + /** * @typedef http_resource_dynamic_cb_t * @brief Callback used when data is received. Data to be sent to client @@ -134,19 +209,17 @@ enum http_data_status { * * @param client HTTP context information for this client connection. * @param status HTTP data status, indicate whether more data is expected or not. - * @param data_buffer Data received. - * @param data_len Amount of data received. + * @param request_ctx Request context structure containing HTTP request data that was received. + * @param response_ctx Response context structure for application to populate with response data. * @param user_data User specified data. * - * @return >0 amount of data to be sent to client, let server to call this - * function again when new data is received. - * 0 nothing to sent to client, close the connection + * @return 0 success, server can send any response data provided in the response_ctx. * <0 error, close the connection. */ typedef int (*http_resource_dynamic_cb_t)(struct http_client_ctx *client, enum http_data_status status, - uint8_t *data_buffer, - size_t data_len, + const struct http_request_ctx *request_ctx, + struct http_response_ctx *response_ctx, void *user_data); /** @@ -161,14 +234,6 @@ struct http_resource_detail_dynamic { */ http_resource_dynamic_cb_t cb; - /** Data buffer used to exchanged data between server and the, - * application. - */ - uint8_t *data_buffer; - - /** Length of the data in the data buffer. */ - size_t data_buffer_len; - /** A pointer to the client currently processing resource, used to * prevent concurrent access to the resource from multiple clients. */ @@ -277,6 +342,9 @@ struct http2_stream_ctx { enum http2_stream_state stream_state; /**< Stream state. */ int window_size; /**< Stream-level window size. */ + /** Currently processed resource detail. */ + struct http_resource_detail *current_detail; + /** Flag indicating that headers were sent in the reply. */ bool headers_sent : 1; @@ -293,6 +361,37 @@ struct http2_frame { uint8_t padding_len; /**< Frame padding length. */ }; +/** @cond INTERNAL_HIDDEN */ +/** @brief Context for capturing HTTP headers */ +struct http_header_capture_ctx { + /** Buffer for HTTP headers captured for application use */ + unsigned char buffer[HTTP_SERVER_CAPTURE_HEADER_BUFFER_SIZE]; + + /** Descriptor of each captured HTTP header */ + struct http_header headers[HTTP_SERVER_CAPTURE_HEADER_COUNT]; + + /** Status of captured headers */ + enum http_header_status status; + + /** Number of headers captured */ + size_t count; + + /** Current position in buffer */ + size_t cursor; + + /** The HTTP2 stream associated with the current headers */ + struct http2_stream_ctx *current_stream; + + /** The next HTTP header value should be stored */ + bool store_next_value; +}; +/** @endcond */ + +/** @brief HTTP header name representation */ +struct http_header_name { + const char *name; /**< Pointer to header name NULL-terminated string. */ +}; + /** * @brief Representation of an HTTP client connected to the server. */ @@ -336,6 +435,9 @@ struct http_client_ctx { /** HTTP/1 parser context. */ struct http_parser parser; + /** Header capture context */ + struct http_header_capture_ctx header_capture_ctx; + /** Request URL. */ unsigned char url_buffer[HTTP_SERVER_MAX_URL_LENGTH]; @@ -391,6 +493,21 @@ struct http_client_ctx { bool expect_continuation : 1; }; +/** + * @brief Register an HTTP request header to be captured by the server + * + * @param _id variable name for the header capture instance + * @param _header header to be captured, as literal string + */ +#define HTTP_SERVER_REGISTER_HEADER_CAPTURE(_id, _header) \ + BUILD_ASSERT(sizeof(_header) <= CONFIG_HTTP_SERVER_MAX_HEADER_LEN, \ + "Header is too long to be captured, try increasing " \ + "CONFIG_HTTP_SERVER_MAX_HEADER_LEN"); \ + static const char *const _id##_str = _header; \ + static const STRUCT_SECTION_ITERABLE(http_header_name, _id) = { \ + .name = _id##_str, \ + } + /** @brief Start the HTTP2 server. * * The server runs in a background thread. Once started, the server will create diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/service.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/service.h index e541c768..6a836b73 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/service.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/service.h @@ -13,6 +13,8 @@ * @brief HTTP service API * * @defgroup http_service HTTP service API + * @since 3.4 + * @version 0.1.0 * @ingroup networking * @{ */ @@ -78,7 +80,7 @@ struct http_service_desc { #define __z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail, _res_begin, \ _res_end, ...) \ - static const STRUCT_SECTION_ITERABLE(http_service_desc, _name) = { \ + const STRUCT_SECTION_ITERABLE(http_service_desc, _name) = { \ .host = _host, \ .port = (uint16_t *)(_port), \ .detail = (void *)(_detail), \ @@ -99,8 +101,9 @@ struct http_service_desc { /** * @brief Define an HTTP service without static resources. * - * @note The @p _host parameter must be non-`NULL`. It is used to specify an IP address either in - * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. + * @note The @p _host parameter is used to specify an IP address either in + * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. If left NULL, the listening + * port will listen on all addresses. * * @note The @p _port parameter must be non-`NULL`. It points to a location that specifies the port * number to use for the service. If the specified port number is zero, then an ephemeral port @@ -120,8 +123,9 @@ struct http_service_desc { /** * @brief Define an HTTPS service without static resources. * - * @note The @p _host parameter must be non-`NULL`. It is used to specify an IP address either in - * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. + * @note The @p _host parameter is used to specify an IP address either in + * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. If left NULL, the listening + * port will listen on all addresses. * * @note The @p _port parameter must be non-`NULL`. It points to a location that specifies the port * number to use for the service. If the specified port number is zero, then an ephemeral port @@ -147,8 +151,9 @@ struct http_service_desc { /** * @brief Define an HTTP service with static resources. * - * @note The @p _host parameter must be non-`NULL`. It is used to specify an IP address either in - * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. + * @note The @p _host parameter is used to specify an IP address either in + * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. If left NULL, the listening + * port will listen on all addresses. * * @note The @p _port parameter must be non-`NULL`. It points to a location that specifies the port * number to use for the service. If the specified port number is zero, then an ephemeral port @@ -172,8 +177,9 @@ struct http_service_desc { /** * @brief Define an HTTPS service with static resources. * - * @note The @p _host parameter must be non-`NULL`. It is used to specify an IP address either in - * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. + * @note The @p _host parameter is used to specify an IP address either in + * IPv4 or IPv6 format a fully-qualified hostname or a virtual host. If left NULL, the listening + * port will listen on all addresses. * * @note The @p _port parameter must be non-`NULL`. It points to a location that specifies the port * number to use for the service. If the specified port number is zero, then an ephemeral port diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/status.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/status.h index 17b3394a..6a136a17 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/status.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/http/status.h @@ -14,6 +14,8 @@ /** * @brief HTTP response status codes * @defgroup http_status_codes HTTP response status codes + * @since 3.3 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/icmp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/icmp.h index 6d6a6b2c..9ada9880 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/icmp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/icmp.h @@ -9,6 +9,8 @@ * @brief ICMP sending and receiving. * * @defgroup icmp Send and receive IPv4 or IPv6 ICMP Echo Request messages. + * @since 3.5 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_ie.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_ie.h index a2378a38..ac520e65 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_ie.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_ie.h @@ -23,7 +23,7 @@ #ifndef ZEPHYR_INCLUDE_NET_IEEE802154_IE_H_ #define ZEPHYR_INCLUDE_NET_IEEE802154_IE_H_ -#include +#include #include /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_mgmt.h index 59372423..8996014d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_mgmt.h @@ -330,6 +330,13 @@ struct ieee802154_req_params { uint8_t len; /** Link quality information, between 0 and 255 */ uint8_t lqi; + /** Flag if association is permitted by the coordinator */ + bool association_permitted; + + /** Additional payload of the beacon if any.*/ + uint8_t *beacon_payload; + /** Length of the additional payload. */ + size_t beacon_payload_len; }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_pkt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_pkt.h index 3270f994..b51db139 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_pkt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_pkt.h @@ -59,6 +59,16 @@ struct net_pkt_cb_ieee802154 { */ uint8_t rssi; }; + struct { +#if defined(CONFIG_IEEE802154_SELECTIVE_TXCHANNEL) + /* The channel used for timed transmissions. + * + * Please refer to `ieee802154_radio_api::tx` documentation for + * details. + */ + uint8_t txchannel; +#endif /* CONFIG_IEEE802154_SELECTIVE_TXCHANNEL */ + }; }; /* Flags */ @@ -179,6 +189,18 @@ static inline void net_pkt_set_ieee802154_rssi_dbm(struct net_pkt *pkt, int16_t CODE_UNREACHABLE; } +#if defined(CONFIG_IEEE802154_SELECTIVE_TXCHANNEL) +static inline uint8_t net_pkt_ieee802154_txchannel(struct net_pkt *pkt) +{ + return net_pkt_cb_ieee802154(pkt)->txchannel; +} + +static inline void net_pkt_set_ieee802154_txchannel(struct net_pkt *pkt, uint8_t channel) +{ + net_pkt_cb_ieee802154(pkt)->txchannel = channel; +} +#endif /* CONFIG_IEEE802154_SELECTIVE_TXCHANNEL */ + static inline bool net_pkt_ieee802154_ack_fpb(struct net_pkt *pkt) { return net_pkt_cb_ieee802154(pkt)->ack_fpb; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio.h index 10a1922f..e2ab96ff 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio.h @@ -520,13 +520,26 @@ enum ieee802154_hw_caps { /** RxOnWhenIdle handling supported */ IEEE802154_RX_ON_WHEN_IDLE = BIT(12), + /** Support for timed transmissions on selective channel. + * + * This capability informs that transmissions with modes + * @ref IEEE802154_TX_MODE_TXTIME and @ref IEEE802154_TX_MODE_TXTIME_CCA support + * scheduling of timed transmissions on selective tx channel. + * The driver MAY have this capability only if the Kconfig option + * `CONFIG_IEEE802154_SELECTIVE_TXCHANNEL` is set, otherwise the driver MUST + * NOT have this capability. + * + * Please refer to the `ieee802154_radio_api::tx` documentation for details. + */ + IEEE802154_HW_SELECTIVE_TXCHANNEL = BIT(13), + /* Note: Update also IEEE802154_HW_CAPS_BITS_COMMON_COUNT when changing * the ieee802154_hw_caps type. */ }; /** @brief Number of bits used by ieee802154_hw_caps type. */ -#define IEEE802154_HW_CAPS_BITS_COMMON_COUNT (13) +#define IEEE802154_HW_CAPS_BITS_COMMON_COUNT (14) /** @brief This and higher values are specific to the protocol- or driver-specific extensions. */ #define IEEE802154_HW_CAPS_BITS_PRIV_START IEEE802154_HW_CAPS_BITS_COMMON_COUNT @@ -625,6 +638,8 @@ enum ieee802154_tx_mode { * Transmit packet in the future, at the specified time, no CCA. * * @note requires IEEE802154_HW_TXTIME capability. + * + * @note capability IEEE802154_HW_SELECTIVE_TXCHANNEL may apply. */ IEEE802154_TX_MODE_TXTIME, @@ -635,6 +650,8 @@ enum ieee802154_tx_mode { * * @note Required for Thread 1.2 Coordinated Sampled Listening feature * (see Thread specification 1.2.0, ch. 3.2.6.3). + * + * @note capability IEEE802154_HW_SELECTIVE_TXCHANNEL may apply. */ IEEE802154_TX_MODE_TXTIME_CCA, @@ -1657,6 +1674,23 @@ struct ieee802154_radio_api { * considerable idle waiting time. SHALL return `-ENETDOWN` unless the * interface is "UP". * + * @note The transmission occurs on the radio channel set by the call to + * `set_channel()`. However, if the `CONFIG_IEEE802154_SELECTIVE_TXCHANNEL` + * is set and the driver has the capability `IEEE802154_HW_SELECTIVE_TXCHANNEL` + * then the transmissions requested with `mode` IEEE802154_TX_MODE_TXTIME + * or `IEEE802154_TX_MODE_TXTIME_CCA` SHALL use the radio channel + * returned by `net_pkt_ieee802154_txchannel()` to transmit the packet + * and receive an ACK on that channel if the frame requested it. After + * the operation the driver should return to the channel set previously by + * `set_channel()` call. + * It is responsibility of an upper layer to set the required radio channel + * for the packet by a call to `net_pkt_set_ieee802154_txchannel()`. + * This feature allows CSL transmissions as stated in IEEE 802.15.4-2020 + * chapter 6.12.2.7 CSL over multiple channels. This feature allows to perform + * a switch of the radio channel as late as possible before transmission without + * interrupting possible reception that could occur if separate `set_channel()` + * was called. + * * @param dev pointer to IEEE 802.15.4 driver device * @param mode the transmission mode, some of which require specific * offloading capabilities. @@ -1731,6 +1765,7 @@ struct ieee802154_radio_api { */ int (*stop)(const struct device *dev); +#if defined(CONFIG_IEEE802154_CARRIER_FUNCTIONS) /** * @brief Start continuous carrier wave transmission. * @@ -1752,6 +1787,30 @@ struct ieee802154_radio_api { */ int (*continuous_carrier)(const struct device *dev); + /** + * @brief Start modulated carrier wave transmission. + * + * @details When the radio is emitting modulated carrier signals, it + * blocks all transmissions on the selected channel. + * This function is to be called only during radio + * tests. Do not use it during normal device operation. + * + * @note Implementations MAY **sleep** and will usually NOT be + * **isr-ok**. MAY be called in any interface state once the driver is + * fully initialized ("ready"). + * + * @param dev pointer to IEEE 802.15.4 driver device + * @param data Pointer to a buffer to modulate the carrier with. + * The first byte is the data length. + * + * @retval 0 modulated carrier wave transmission started + * @retval -EALREADY The driver was already in "TESTING" state and + * emitting a modulated carrier. + * @retval -EIO not started + */ + int (*modulated_carrier)(const struct device *dev, const uint8_t *data); +#endif /* CONFIG_IEEE802154_CARRIER_FUNCTIONS */ + /** * @brief Set or update driver configuration. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio_openthread.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio_openthread.h index e45bbc6b..0890d100 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio_openthread.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ieee802154_radio_openthread.h @@ -14,6 +14,9 @@ #include +/** Bit number starting the OpenThread specific capabilities of ieee802154 driver. */ +#define IEEE802154_OPENTHREAD_HW_CAPS_BITS_START IEEE802154_HW_CAPS_BITS_PRIV_START + /** * OpenThread specific capabilities of ieee802154 driver. * This type extends @ref ieee802154_hw_caps. @@ -22,7 +25,26 @@ enum ieee802154_openthread_hw_caps { /** Capability to transmit with @ref IEEE802154_OPENTHREAD_TX_MODE_TXTIME_MULTIPLE_CCA * mode. */ - IEEE802154_OPENTHREAD_HW_MULTIPLE_CCA = BIT(IEEE802154_HW_CAPS_BITS_PRIV_START), + IEEE802154_OPENTHREAD_HW_MULTIPLE_CCA = BIT(IEEE802154_OPENTHREAD_HW_CAPS_BITS_START), + + /** Capability to support CST-related features. + * + * The CST-related features are described by "Specification changes for Thread-in-Mobile" + * Draft version 1, July 11, 2024. The CST allows to transmit a frame with CST Phase and + * CST Period IEs as described by chapter 4.6.6.1 of the Thread-in-Mobile specification + * change. The upper layer implementation (OpenThread) is responsible for preparing + * a frame to be transmitted that contains placeholders where the CST Phase and CST Period + * are to be placed. The implementation of a driver is responsible for injecting + * correct value for CST Phase IE and CST Period IE based on configuration parameters + * @ref IEEE802154_OPENTHREAD_CONFIG_CST_PERIOD and + * @ref IEEE802154_OPENTHREAD_CONFIG_EXPECTED_TX_TIME. + * + * @note The CST transmission in its design is very similar to CSL reception. + * In the CSL reception the receiver side informs its peer about the moment in time + * when it will be able to receive. In the CST transmission the transmitter side informs + * its peer about the moment in time when the next transmission will occur. + */ + IEEE802154_OPENTHREAD_HW_CST = BIT(IEEE802154_OPENTHREAD_HW_CAPS_BITS_START + 1), }; /** @brief TX mode */ @@ -64,6 +86,9 @@ enum ieee802154_openthread_tx_mode { * section 11.3, table 11-2). * * Requires IEEE802154_OPENTHREAD_HW_MULTIPLE_CCA capability. + * + * @note Capability @ref IEEE802154_HW_SELECTIVE_TXCHANNEL applies as for + * @ref IEEE802154_TX_MODE_TXTIME_CCA. */ IEEE802154_OPENTHREAD_TX_MODE_TXTIME_MULTIPLE_CCA = IEEE802154_TX_MODE_PRIV_START }; @@ -77,7 +102,33 @@ enum ieee802154_openthread_config_type { * @ref IEEE802154_OPENTHREAD_TX_MODE_TXTIME_MULTIPLE_CCA. * Requires IEEE802154_OPENTHREAD_HW_MULTIPLE_CCA capability. */ - IEEE802154_OPENTHREAD_CONFIG_MAX_EXTRA_CCA_ATTEMPTS = IEEE802154_CONFIG_PRIV_START + IEEE802154_OPENTHREAD_CONFIG_MAX_EXTRA_CCA_ATTEMPTS = IEEE802154_CONFIG_PRIV_START, + + /** Configures the CST period of a device. + * + * When a frame containing CST Period IE is about to be transmitted by a driver, + * the driver SHALL inject the CST Period value to the CST Period IE based on + * the value of this configuration parameter. + * + * Requires IEEE802154_OPENTHREAD_HW_CST capability. + */ + IEEE802154_OPENTHREAD_CONFIG_CST_PERIOD, + + /** Configure a point in time at which a TX frame is expected to be transmitted. + * + * When a frame containing CST Phase IE is about to be transmitted by a driver, + * the driver SHALL inject the CST Phase IE value to the CST Phase IE based on + * the value of this configuration parameter parameter, the time of transmission + * and the CST Period value. + * + * This parameter configures the nanosecond resolution timepoint relative to + * the network subsystem's local clock at which a TX frame's end of SFD + * (i.e. equivalently its end of SHR, start of PHR) is expected to be transmitted + * at the local antenna. + * + * Requires IEEE802154_OPENTHREAD_HW_CST capability. + */ + IEEE802154_OPENTHREAD_CONFIG_EXPECTED_TX_TIME, }; /** @@ -103,6 +154,18 @@ struct ieee802154_openthread_config { * requested with mode @ref IEEE802154_OPENTHREAD_TX_MODE_TXTIME_MULTIPLE_CCA. */ uint8_t max_extra_cca_attempts; + + /** ``IEEE802154_OPENTHREAD_CONFIG_CST_PERIOD`` + * + * The CST period (in CPU byte order). + */ + uint32_t cst_period; + + /** ``IEEE802154_OPENTHREAD_CONFIG_EXPECTED_TX_TIME`` + * + * A point in time at which a TX frame is expected to be transmitted. + */ + net_time_t expected_tx_time; }; }; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/igmp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/igmp.h index 7dbfd78e..099bbda3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/igmp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/igmp.h @@ -14,6 +14,8 @@ /** * @brief IGMP (Internet Group Management Protocol) * @defgroup igmp IGMP API + * @since 2.6 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lldp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lldp.h index 9f91a0c7..0d638f27 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lldp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lldp.h @@ -16,6 +16,8 @@ /** * @brief LLDP definitions and helpers * @defgroup lldp Link Layer Discovery Protocol definitions and helpers + * @since 1.13 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m.h index 9dcdb142..4aa81a8b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m.h @@ -33,6 +33,10 @@ #include #include +#ifdef __cplusplus +extern "C" { +#endif + /** * @name LwM2M Objects managed by OMA for LwM2M tech specification. * Objects in this range have IDs from 0 to 1023. @@ -126,7 +130,49 @@ typedef void (*lwm2m_observe_cb_t)(enum lwm2m_observe_event event, struct lwm2m_ struct lwm2m_ctx; -enum lwm2m_rd_client_event; + +/** + * @brief LwM2M RD client events + * + * LwM2M client events are passed back to the event_cb function in + * lwm2m_rd_client_start() + */ +enum lwm2m_rd_client_event { + /** Invalid event */ + LWM2M_RD_CLIENT_EVENT_NONE, + /** Bootstrap registration failure */ + LWM2M_RD_CLIENT_EVENT_BOOTSTRAP_REG_FAILURE, + /** Bootstrap registration complete */ + LWM2M_RD_CLIENT_EVENT_BOOTSTRAP_REG_COMPLETE, + /** Bootstrap transfer complete */ + LWM2M_RD_CLIENT_EVENT_BOOTSTRAP_TRANSFER_COMPLETE, + /** Registration failure */ + LWM2M_RD_CLIENT_EVENT_REGISTRATION_FAILURE, + /** Registration complete */ + LWM2M_RD_CLIENT_EVENT_REGISTRATION_COMPLETE, + /** Registration timeout */ + LWM2M_RD_CLIENT_EVENT_REG_TIMEOUT, + /** Registration update complete */ + LWM2M_RD_CLIENT_EVENT_REG_UPDATE_COMPLETE, + /** De-registration failure */ + LWM2M_RD_CLIENT_EVENT_DEREGISTER_FAILURE, + /** Disconnected */ + LWM2M_RD_CLIENT_EVENT_DISCONNECT, + /** Queue mode RX off */ + LWM2M_RD_CLIENT_EVENT_QUEUE_MODE_RX_OFF, + /** Engine suspended */ + LWM2M_RD_CLIENT_EVENT_ENGINE_SUSPENDED, + /** Network error */ + LWM2M_RD_CLIENT_EVENT_NETWORK_ERROR, + /** Registration update */ + LWM2M_RD_CLIENT_EVENT_REG_UPDATE, + /** De-register */ + LWM2M_RD_CLIENT_EVENT_DEREGISTER, + /** Server disabled */ + LWM2M_RD_CLIENT_EVENT_SERVER_DISABLED, +}; + + /** * @brief Asynchronous RD client event callback * @@ -136,6 +182,7 @@ enum lwm2m_rd_client_event; typedef void (*lwm2m_ctx_event_cb_t)(struct lwm2m_ctx *ctx, enum lwm2m_rd_client_event event); +typedef int (*lwm2m_set_sockopt_cb_t)(struct lwm2m_ctx *client_ctx); /** * @brief Different traffic states of the LwM2M socket. @@ -171,6 +218,7 @@ struct lwm2m_ctx { sys_slist_t queued_messages; #endif sys_slist_t observer; + struct k_mutex lock; /** @endcond */ /** A pointer to currently processed request, for internal LwM2M engine @@ -199,8 +247,6 @@ struct lwm2m_ctx { char *desthostname; /** Destination hostname length */ uint16_t desthostnamelen; - /** Flag to indicate if hostname verification is enabled */ - bool hostname_verify; /** Custom load_credentials function. * Client can set load_credentials function as a way of overriding @@ -214,7 +260,7 @@ struct lwm2m_ctx { * a callback that is called after a socket is created and before * connect. */ - int (*set_socketoptions)(struct lwm2m_ctx *client_ctx); + lwm2m_set_sockopt_cb_t set_socketoptions; /** Flag to indicate if context should use DTLS. * Enabled via the use of coaps:// protocol prefix in connection @@ -868,21 +914,6 @@ int lwm2m_set_u16(const struct lwm2m_obj_path *path, uint16_t value); */ int lwm2m_set_u32(const struct lwm2m_obj_path *path, uint32_t value); -/** - * @brief Set resource (instance) value (u64) - * - * @deprecated Unsigned 64bit value type does not exits. - * This is internally handled as a int64_t. - * Use lwm2m_set_s64() instead. - * - * @param[in] path LwM2M path as a struct - * @param[in] value u64 value - * - * @return 0 for success or negative in case of error. - */ -__deprecated -int lwm2m_set_u64(const struct lwm2m_obj_path *path, uint64_t value); - /** * @brief Set resource (instance) value (s8) * @@ -1061,21 +1092,6 @@ int lwm2m_get_u16(const struct lwm2m_obj_path *path, uint16_t *value); */ int lwm2m_get_u32(const struct lwm2m_obj_path *path, uint32_t *value); -/** - * @brief Get resource (instance) value (u64) - * - * @deprecated Unsigned 64bit value type does not exits. - * This is internally handled as a int64_t. - * Use lwm2m_get_s64() instead. - - * @param[in] path LwM2M path as a struct - * @param[out] value u64 buffer to copy data into - * - * @return 0 for success or negative in case of error. - */ -__deprecated -int lwm2m_get_u64(const struct lwm2m_obj_path *path, uint64_t *value); - /** * @brief Get resource (instance) value (s8) * @@ -1423,47 +1439,6 @@ int lwm2m_engine_start(struct lwm2m_ctx *client_ctx); */ void lwm2m_acknowledge(struct lwm2m_ctx *client_ctx); -/** - * @brief LwM2M RD client events - * - * LwM2M client events are passed back to the event_cb function in - * lwm2m_rd_client_start() - */ -enum lwm2m_rd_client_event { - /** Invalid event */ - LWM2M_RD_CLIENT_EVENT_NONE, - /** Bootstrap registration failure */ - LWM2M_RD_CLIENT_EVENT_BOOTSTRAP_REG_FAILURE, - /** Bootstrap registration complete */ - LWM2M_RD_CLIENT_EVENT_BOOTSTRAP_REG_COMPLETE, - /** Bootstrap transfer complete */ - LWM2M_RD_CLIENT_EVENT_BOOTSTRAP_TRANSFER_COMPLETE, - /** Registration failure */ - LWM2M_RD_CLIENT_EVENT_REGISTRATION_FAILURE, - /** Registration complete */ - LWM2M_RD_CLIENT_EVENT_REGISTRATION_COMPLETE, - /** Registration timeout */ - LWM2M_RD_CLIENT_EVENT_REG_TIMEOUT, - /** Registration update complete */ - LWM2M_RD_CLIENT_EVENT_REG_UPDATE_COMPLETE, - /** De-registration failure */ - LWM2M_RD_CLIENT_EVENT_DEREGISTER_FAILURE, - /** Disconnected */ - LWM2M_RD_CLIENT_EVENT_DISCONNECT, - /** Queue mode RX off */ - LWM2M_RD_CLIENT_EVENT_QUEUE_MODE_RX_OFF, - /** Engine suspended */ - LWM2M_RD_CLIENT_EVENT_ENGINE_SUSPENDED, - /** Network error */ - LWM2M_RD_CLIENT_EVENT_NETWORK_ERROR, - /** Registration update */ - LWM2M_RD_CLIENT_EVENT_REG_UPDATE, - /** De-register */ - LWM2M_RD_CLIENT_EVENT_DEREGISTER, - /** Server disabled */ - LWM2M_RD_CLIENT_EVENT_SERVER_DISABLED, -}; - /* * LwM2M RD client flags, used to configure LwM2M session. */ @@ -1648,5 +1623,20 @@ int lwm2m_security_mode(struct lwm2m_ctx *ctx); */ int lwm2m_set_default_sockopt(struct lwm2m_ctx *ctx); +/** + * @brief Set the @ref lwm2m_ctx::set_socketoptions callback for the pull context's client. + * + * This allows setting specific socket options on the socket that is used to pull + * firmware updates. The callback will be called after the pull context socket has been + * created and before it will connect. + * + * @param[in] set_sockopt_cb A callback function to set sockopts for the pull context client. + */ +void lwm2m_pull_context_set_sockopt_callback(lwm2m_set_sockopt_cb_t set_sockopt_cb); + +#ifdef __cplusplus +} +#endif + #endif /* ZEPHYR_INCLUDE_NET_LWM2M_H_ */ /**@} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m_path.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m_path.h index ad012c8a..568c2af0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m_path.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/lwm2m_path.h @@ -13,6 +13,8 @@ * @brief LwM2M path helper macros * * @defgroup lwm2m_path_helpers LwM2M path helper macros + * @since 2.5 + * @version 0.8.0 * @ingroup lwm2m_api * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mdio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mdio.h index 6ed13c1a..07c4c6b9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mdio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mdio.h @@ -15,6 +15,8 @@ /** * @brief Definitions for IEEE 802.3 management interface * @defgroup ethernet_mdio IEEE 802.3 management interface + * @since 3.5 + * @version 0.8.0 * @ingroup ethernet * @{ */ @@ -97,6 +99,10 @@ enum mdio_opcode { #define MDIO_PKGID1 0x000EU /** Package identifier (2) */ #define MDIO_PKGID2 0x000FU +/* PCS Register: EEE capability Register */ +#define MDIO_PCS_EEE_CAP 0x0014U +/* Auto-negotiation Register: EEE advertisement Register */ +#define MDIO_AN_EEE_ADV 0x003CU /* BASE-T1 registers */ @@ -228,6 +234,12 @@ enum mdio_opcode { /** 10BASE-T1L PCS Descrambler Status */ #define MDIO_PCS_B10L_STAT_DSCR_STAT_OK_LL BIT(2) +/* Auto-negotiation Register: EEE advertisement Register */ +/** Advertise 1000T capability */ +#define MDIO_AN_EEE_ADV_1000T BIT(2) +/** Advertise 100TX capability */ +#define MDIO_AN_EEE_ADV_100TX BIT(1) + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mii.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mii.h index 371f1966..b57ef862 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mii.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mii.h @@ -15,6 +15,8 @@ /** * @brief Ethernet MII (media independent interface) functions * @defgroup ethernet_mii Ethernet MII Support Functions + * @since 1.7 + * @version 0.8.0 * @ingroup ethernet * @{ */ @@ -157,6 +159,15 @@ /** 1000BASE-T half-duplex capable */ #define MII_ESTAT_1000BASE_T_HALF (1 << 12) +/* MMD Access Control Register (MII_MMD_ACR) Register bit definitions */ +/** DEVAD Mask */ +#define MII_MMD_ACR_DEVAD_MASK (0x1F << 0) +/** Address Data bits */ +#define MII_MMD_ACR_ADDR (0x00 << 14) +#define MII_MMD_ACR_DATA_NO_POS_INC (0x01 << 14) +#define MII_MMD_ACR_DATA_RW_POS_INC (0x10 << 14) +#define MII_MMD_ACR_DATA_W_POS_INC (0x11 << 14) + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mld.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mld.h new file mode 100644 index 00000000..031eb03c --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mld.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2016 Intel Corporation + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Multicast Listener Discovery API + */ + +#ifndef ZEPHYR_INCLUDE_NET_MLD_H_ +#define ZEPHYR_INCLUDE_NET_MLD_H_ + +/** + * @brief MLD (Multicast Listener Discovery) + * @defgroup mld Multicast Listener Discovery API + * @since 1.8 + * @version 0.8.0 + * @ingroup networking + * @{ + */ + +#include + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Join a given multicast group. + * + * @param iface Network interface where join message is sent + * @param addr Multicast group to join + * + * @return 0 if joining was done, <0 otherwise. + */ +#if defined(CONFIG_NET_IPV6_MLD) +int net_ipv6_mld_join(struct net_if *iface, const struct in6_addr *addr); +#else +static inline int +net_ipv6_mld_join(struct net_if *iface, const struct in6_addr *addr) +{ + ARG_UNUSED(addr); + ARG_UNUSED(iface); + + return -ENOTSUP; +} +#endif /* CONFIG_NET_IPV6_MLD */ + +/** + * @brief Leave a given multicast group. + * + * @param iface Network interface where leave message is sent + * @param addr Multicast group to leave + * + * @return 0 if leaving is done, <0 otherwise. + */ +#if defined(CONFIG_NET_IPV6_MLD) +int net_ipv6_mld_leave(struct net_if *iface, const struct in6_addr *addr); +#else +static inline int +net_ipv6_mld_leave(struct net_if *iface, const struct in6_addr *addr) +{ + ARG_UNUSED(iface); + ARG_UNUSED(addr); + + return -ENOTSUP; +} +#endif /* CONFIG_NET_IPV6_MLD */ + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_NET_MLD_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mqtt_sn.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mqtt_sn.h index 102cb5e6..cc4b042a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mqtt_sn.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/mqtt_sn.h @@ -13,6 +13,8 @@ * Targets protocol version 1.2. * * @defgroup mqtt_sn_socket MQTT-SN Client library + * @since 3.3 + * @version 0.1.0 * @ingroup networking * @{ */ @@ -22,7 +24,7 @@ #include -#include +#include #include #include @@ -73,16 +75,16 @@ enum mqtt_sn_topic_type { * MQTT-SN return codes. */ enum mqtt_sn_return_code { - MQTT_SN_CODE_ACCEPTED = 0x00, /**< Accepted */ + MQTT_SN_CODE_ACCEPTED = 0x00, /**< Accepted */ MQTT_SN_CODE_REJECTED_CONGESTION = 0x01, /**< Rejected: congestion */ - MQTT_SN_CODE_REJECTED_TOPIC_ID = 0x02, /**< Rejected: Invalid Topic ID */ - MQTT_SN_CODE_REJECTED_NOTSUP = 0x03, /**< Rejected: Not Supported */ + MQTT_SN_CODE_REJECTED_TOPIC_ID = 0x02, /**< Rejected: Invalid Topic ID */ + MQTT_SN_CODE_REJECTED_NOTSUP = 0x03, /**< Rejected: Not Supported */ }; /** @brief Abstracts memory buffers. */ struct mqtt_sn_data { const uint8_t *data; /**< Pointer to data. */ - uint16_t size; /**< Size of data, in bytes. */ + size_t size; /**< Size of data, in bytes. */ }; /** @@ -103,19 +105,22 @@ struct mqtt_sn_data { * * struct mqtt_sn_data data = MQTT_SN_DATA_BYTES(0x13, 0x37); */ -#define MQTT_SN_DATA_BYTES(...) \ - ((struct mqtt_sn_data) { (uint8_t[]){ __VA_ARGS__ }, sizeof((uint8_t[]){ __VA_ARGS__ })}) +#define MQTT_SN_DATA_BYTES(...) \ + ((struct mqtt_sn_data){(uint8_t[]){__VA_ARGS__}, sizeof((uint8_t[]){__VA_ARGS__})}) /** * Event types that can be emitted by the library. */ enum mqtt_sn_evt_type { - MQTT_SN_EVT_CONNECTED, /**< Connected to a gateway */ + MQTT_SN_EVT_CONNECTED, /**< Connected to a gateway */ MQTT_SN_EVT_DISCONNECTED, /**< Disconnected */ - MQTT_SN_EVT_ASLEEP, /**< Entered ASLEEP state */ - MQTT_SN_EVT_AWAKE, /**< Entered AWAKE state */ - MQTT_SN_EVT_PUBLISH, /**< Received a PUBLISH message */ - MQTT_SN_EVT_PINGRESP /**< Received a PINGRESP */ + MQTT_SN_EVT_ASLEEP, /**< Entered ASLEEP state */ + MQTT_SN_EVT_AWAKE, /**< Entered AWAKE state */ + MQTT_SN_EVT_PUBLISH, /**< Received a PUBLISH message */ + MQTT_SN_EVT_PINGRESP, /**< Received a PINGRESP */ + MQTT_SN_EVT_ADVERTISE, /**< Received a ADVERTISE */ + MQTT_SN_EVT_GWINFO, /**< Received a GWINFO */ + MQTT_SN_EVT_SEARCHGW /**< Received a SEARCHGW */ }; /** @@ -178,16 +183,27 @@ struct mqtt_sn_transport { void (*deinit)(struct mqtt_sn_transport *transport); /** - * Will be called by the library when it wants to send a message. + * @brief Will be called by the library when it wants to send a message. + * + * Implementations should follow sendto conventions with exceptions. + * When dest_addr == NULL, message should be broadcast with addrlen being + * the broadcast radius. This should also handle setting up/destroying + * connections as required when the address changes. + * + * @return ENOERR on connection+transmission success, Negative values + * signal errors. */ - int (*msg_send)(struct mqtt_sn_client *client, void *buf, size_t sz); + int (*sendto)(struct mqtt_sn_client *client, void *buf, size_t sz, const void *dest_addr, + size_t addrlen); /** * @brief Will be called by the library when it wants to receive a message. * - * Implementations should follow recv conventions. + * Implementations should follow recvfrom conventions with the exception + * of a NULL src_addr being a broadcast message. */ - ssize_t (*recv)(struct mqtt_sn_client *client, void *buffer, size_t length); + ssize_t (*recvfrom)(struct mqtt_sn_client *client, void *rx_buf, size_t rx_len, + void *src_addr, size_t *addrlen); /** * @brief Check if incoming data is available. @@ -213,9 +229,9 @@ struct mqtt_sn_transport_udp { /** Socket FD */ int sock; - /** Address of the gateway */ - struct sockaddr gwaddr; - socklen_t gwaddrlen; + /** Address of broadcasts */ + struct sockaddr bcaddr; + socklen_t bcaddrlen; }; #define UDP_TRANSPORT(transport) CONTAINER_OF(transport, struct mqtt_sn_transport_udp, tp) @@ -263,6 +279,9 @@ struct mqtt_sn_client { /** Buffer for incoming data */ struct net_buf_simple rx; + /** Buffer for incoming data sender address */ + struct net_buf_simple rx_addr; + /** Event callback */ mqtt_sn_evt_cb_t evt_cb; @@ -275,6 +294,9 @@ struct mqtt_sn_client { /** List of registered topics */ sys_slist_t topic; + /** List of found gateways */ + sys_slist_t gateway; + /** Current state of the MQTT-SN client */ int state; @@ -284,6 +306,15 @@ struct mqtt_sn_client { /** Number of retries for failed ping attempts */ uint8_t ping_retries; + /** Timestamp of the next SEARCHGW transmission */ + int64_t ts_searchgw; + + /** Timestamp of the next GWINFO transmission */ + int64_t ts_gwinfo; + + /** Radius of the next GWINFO transmission */ + int64_t radius_gwinfo; + /** Delayable work structure for processing MQTT-SN events */ struct k_work_delayable process_work; }; @@ -315,6 +346,29 @@ int mqtt_sn_client_init(struct mqtt_sn_client *client, const struct mqtt_sn_data */ void mqtt_sn_client_deinit(struct mqtt_sn_client *client); +/** + * @brief Manually add a Gateway, bypasing the normal search process. + * + * This function manually creates a gateway that is stored internal to the library. + * + * @param client The MQTT-SN client to connect. + * @param gw_id Single byte Gateway Identifier + * @param gw_addr Address data structure to be used by the transport layer. + * + * @return 0 or a negative error code (errno.h) indicating reason of failure. + */ +int mqtt_sn_add_gw(struct mqtt_sn_client *client, uint8_t gw_id, struct mqtt_sn_data gw_addr); + +/** + * @brief Initiate the MQTT-SN GW Search process. + * + * @param client The MQTT-SN client to connect. + * @param radius Broadcast radius for the search message. + * + * @return 0 or a negative error code (errno.h) indicating reason of failure. + */ +int mqtt_sn_search(struct mqtt_sn_client *client, uint8_t radius); + /** * @brief Connect the client. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_config.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_config.h index 3a04bedb..088ae5b5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_config.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_config.h @@ -22,6 +22,8 @@ extern "C" { /** * @brief Network configuration library * @defgroup net_config Network Configuration Library + * @since 1.8 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_context.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_context.h index 86d48fa1..80d84426 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_context.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_context.h @@ -17,6 +17,8 @@ /** * @brief Application network context * @defgroup net_context Application network context + * @since 1.0 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -198,7 +200,7 @@ struct net_conn_handle; /** * Note that we do not store the actual source IP address in the context - * because the address is already be set in the network interface struct. + * because the address is already set in the network interface struct. * If there is no such source address there, the packet cannot be sent * anyway. This saves 12 bytes / context in IPv6. */ @@ -314,6 +316,20 @@ __net_socket struct net_context { socklen_t addrlen; } proxy; #endif +#if defined(CONFIG_NET_CONTEXT_CLAMP_PORT_RANGE) + /** Restrict local port range between these values. + * The option takes an uint32_t value with the high 16 bits + * set to the upper range bound, and the low 16 bits set to + * the lower range bound. Range bounds are inclusive. The + * 16-bit values should be in host byte order. + * The lower bound has to be less than the upper bound when + * both bounds are not zero. Otherwise, setting the option + * fails with EINVAL. + * If either bound is outside of the global local port range, + * or is zero, then that bound has no effect. + */ + uint32_t port_range; +#endif #if defined(CONFIG_NET_CONTEXT_RCVTIMEO) /** Receive timeout */ k_timeout_t rcvtimeo; @@ -360,6 +376,22 @@ __net_socket struct net_context { */ uint16_t addr_preferences; #endif +#if defined(CONFIG_NET_IPV6) || defined(CONFIG_NET_IPV4) + union { + /** + * IPv6 multicast output network interface for this context/socket. + * Only allowed for SOCK_DGRAM or SOCK_RAW type sockets. + */ + uint8_t ipv6_mcast_ifindex; + + /** + * IPv4 multicast output network interface for this context/socket. + * Only allowed for SOCK_DGRAM type sockets. + */ + uint8_t ipv4_mcast_ifindex; + }; +#endif /* CONFIG_NET_IPV6 || CONFIG_NET_IPV4 */ + #if defined(CONFIG_NET_CONTEXT_TIMESTAMPING) /** Enable RX, TX or both timestamps of packets send through sockets. */ uint8_t timestamping; @@ -1290,6 +1322,9 @@ enum net_context_option { NET_OPT_TTL = 16, /**< IPv4 unicast TTL */ NET_OPT_ADDR_PREFERENCES = 17, /**< IPv6 address preference */ NET_OPT_TIMESTAMPING = 18, /**< Packet timestamping */ + NET_OPT_MCAST_IFINDEX = 19, /**< IPv6 multicast output network interface index */ + NET_OPT_MTU = 20, /**< IPv4 socket path MTU */ + NET_OPT_LOCAL_PORT_RANGE = 21, /**< Clamp local port range */ }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_core.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_core.h index 0ec70fd6..4b07aaa3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_core.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_core.h @@ -39,6 +39,8 @@ extern "C" { /** * @brief Network core library * @defgroup net_core Network Core Library + * @since 1.0 + * @version 1.0.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_event.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_event.h index 9bcba06b..f0f8545a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_event.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_event.h @@ -74,6 +74,7 @@ enum net_event_ipv6_cmd { NET_EVENT_IPV6_CMD_PE_DISABLED, NET_EVENT_IPV6_CMD_PE_FILTER_ADD, NET_EVENT_IPV6_CMD_PE_FILTER_DEL, + NET_EVENT_IPV6_CMD_PMTU_CHANGED, }; /* IPv4 Events*/ @@ -99,6 +100,7 @@ enum net_event_ipv4_cmd { NET_EVENT_IPV4_CMD_ACD_SUCCEED, NET_EVENT_IPV4_CMD_ACD_FAILED, NET_EVENT_IPV4_CMD_ACD_CONFLICT, + NET_EVENT_IPV4_CMD_PMTU_CHANGED, }; /* L4 network events */ @@ -237,6 +239,10 @@ enum net_event_l4_cmd { #define NET_EVENT_IPV6_PE_FILTER_DEL \ (_NET_EVENT_IPV6_BASE | NET_EVENT_IPV6_CMD_PE_FILTER_DEL) +/** IPv6 Path MTU is changed. */ +#define NET_EVENT_IPV6_PMTU_CHANGED \ + (_NET_EVENT_IPV6_BASE | NET_EVENT_IPV6_CMD_PMTU_CHANGED) + /** Event emitted when an IPv4 address is added to the system. */ #define NET_EVENT_IPV4_ADDR_ADD \ (_NET_EVENT_IPV4_BASE | NET_EVENT_IPV4_CMD_ADDR_ADD) @@ -296,6 +302,10 @@ enum net_event_l4_cmd { #define NET_EVENT_IPV4_ACD_CONFLICT \ (_NET_EVENT_IPV4_BASE | NET_EVENT_IPV4_CMD_ACD_CONFLICT) +/** IPv4 Path MTU is changed. */ +#define NET_EVENT_IPV4_PMTU_CHANGED \ + (_NET_EVENT_IPV4_BASE | NET_EVENT_IPV4_CMD_PMTU_CHANGED) + /** Event emitted when the system is considered to be connected. * The connected in this context means that the network interface is up, * and the interface has either IPv4 or IPv6 address assigned to it. @@ -441,6 +451,34 @@ struct net_event_ipv6_pe_filter { bool is_deny_list; }; +/** + * @brief Network Management event information structure + * Used to pass information on network event + * NET_EVENT_IPV4_PMTU_CHANGED + * when CONFIG_NET_MGMT_EVENT_INFO enabled and event generator pass the + * information. + */ +struct net_event_ipv4_pmtu_info { + /** IPv4 address */ + struct in_addr dst; + /** New MTU */ + uint16_t mtu; +}; + +/** + * @brief Network Management event information structure + * Used to pass information on network event + * NET_EVENT_IPV6_PMTU_CHANGED + * when CONFIG_NET_MGMT_EVENT_INFO enabled and event generator pass the + * information. + */ +struct net_event_ipv6_pmtu_info { + /** IPv6 address */ + struct in6_addr dst; + /** New MTU */ + uint32_t mtu; +}; + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_if.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_if.h index 67501f43..14981e92 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_if.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_if.h @@ -15,6 +15,8 @@ /** * @brief Network Interface abstraction layer * @defgroup net_if Network Interface abstraction layer + * @since 1.5 + * @version 1.0.0 * @ingroup networking * @{ */ @@ -40,6 +42,8 @@ #include #endif +#include + #ifdef __cplusplus extern "C" { #endif @@ -298,7 +302,7 @@ struct net_offload; #endif /* CONFIG_NET_OFFLOAD */ /** @cond INTERNAL_HIDDEN */ -#if defined(CONFIG_NET_NATIVE_IPV6) +#if defined(CONFIG_NET_IPV6) #define NET_IF_MAX_IPV6_ADDR CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT #define NET_IF_MAX_IPV6_MADDR CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT #define NET_IF_MAX_IPV6_PREFIX CONFIG_NET_IF_IPV6_PREFIX_COUNT @@ -329,6 +333,16 @@ struct net_if_ipv6 { /** Retransmit timer (RFC 4861, page 52) */ uint32_t retrans_timer; +#if defined(CONFIG_NET_IPV6_IID_STABLE) + /** IID (Interface Identifier) pointer used for link local address */ + struct net_if_addr *iid; + + /** Incremented when network interface goes down so that we can + * generate new stable addresses when interface comes back up. + */ + uint32_t network_counter; +#endif /* CONFIG_NET_IPV6_IID_STABLE */ + #if defined(CONFIG_NET_IPV6_PE) /** Privacy extension DESYNC_FACTOR value from RFC 8981 ch 3.4. * "DESYNC_FACTOR is a random value within the range 0 - MAX_DESYNC_FACTOR. @@ -420,7 +434,7 @@ struct net_if_dhcpv6 { #endif /* defined(CONFIG_NET_DHCPV6) && defined(CONFIG_NET_NATIVE_IPV6) */ /** @cond INTERNAL_HIDDEN */ -#if defined(CONFIG_NET_NATIVE_IPV4) +#if defined(CONFIG_NET_IPV4) #define NET_IF_MAX_IPV4_ADDR CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT #define NET_IF_MAX_IPV4_MADDR CONFIG_NET_IF_MCAST_IPV4_ADDR_COUNT #else @@ -540,11 +554,11 @@ struct net_if_ipv4_autoconf { * @brief Network interface IP address configuration. */ struct net_if_ip { -#if defined(CONFIG_NET_NATIVE_IPV6) +#if defined(CONFIG_NET_IPV6) struct net_if_ipv6 *ipv6; #endif /* CONFIG_NET_IPV6 */ -#if defined(CONFIG_NET_NATIVE_IPV4) +#if defined(CONFIG_NET_IPV4) struct net_if_ipv4 *ipv4; #endif /* CONFIG_NET_IPV4 */ }; @@ -682,6 +696,10 @@ struct net_if { #if defined(CONFIG_NET_STATISTICS_PER_INTERFACE) /** Network statistics related to this network interface */ struct net_stats stats; + + /** Promethus collector for this network interface */ + IF_ENABLED(CONFIG_NET_STATISTICS_VIA_PROMETHEUS, + (struct prometheus_collector *collector);) #endif /* CONFIG_NET_STATISTICS_PER_INTERFACE */ /** Network interface instance configuration */ @@ -768,8 +786,9 @@ static inline void net_if_tx_unlock(struct net_if *iface) static inline void net_if_flag_set(struct net_if *iface, enum net_if_flag value) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return; + } atomic_set_bit(iface->if_dev->flags, value); } @@ -785,8 +804,9 @@ static inline void net_if_flag_set(struct net_if *iface, static inline bool net_if_flag_test_and_set(struct net_if *iface, enum net_if_flag value) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return false; + } return atomic_test_and_set_bit(iface->if_dev->flags, value); } @@ -800,8 +820,9 @@ static inline bool net_if_flag_test_and_set(struct net_if *iface, static inline void net_if_flag_clear(struct net_if *iface, enum net_if_flag value) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return; + } atomic_clear_bit(iface->if_dev->flags, value); } @@ -817,8 +838,9 @@ static inline void net_if_flag_clear(struct net_if *iface, static inline bool net_if_flag_test_and_clear(struct net_if *iface, enum net_if_flag value) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return false; + } return atomic_test_and_clear_bit(iface->if_dev->flags, value); } @@ -834,10 +856,7 @@ static inline bool net_if_flag_test_and_clear(struct net_if *iface, static inline bool net_if_flag_is_set(struct net_if *iface, enum net_if_flag value) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); - - if (iface == NULL) { + if (iface == NULL || iface->if_dev == NULL) { return false; } @@ -855,10 +874,12 @@ static inline bool net_if_flag_is_set(struct net_if *iface, static inline enum net_if_oper_state net_if_oper_state_set( struct net_if *iface, enum net_if_oper_state oper_state) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NET_IF_OPER_UNKNOWN; + } - if (oper_state >= NET_IF_OPER_UNKNOWN && oper_state <= NET_IF_OPER_UP) { + BUILD_ASSERT((enum net_if_oper_state)(-1) > 0 && NET_IF_OPER_UNKNOWN == 0); + if (oper_state <= NET_IF_OPER_UP) { iface->if_dev->oper_state = oper_state; } @@ -874,8 +895,9 @@ static inline enum net_if_oper_state net_if_oper_state_set( */ static inline enum net_if_oper_state net_if_oper_state(struct net_if *iface) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NET_IF_OPER_UNKNOWN; + } return iface->if_dev->oper_state; } @@ -899,7 +921,7 @@ enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt); */ static inline const struct net_l2 *net_if_l2(struct net_if *iface) { - if (!iface || !iface->if_dev) { + if (iface == NULL || iface->if_dev == NULL) { return NULL; } @@ -925,8 +947,9 @@ enum net_verdict net_if_recv_data(struct net_if *iface, struct net_pkt *pkt); */ static inline void *net_if_l2_data(struct net_if *iface) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NULL; + } return iface->if_dev->l2_data; } @@ -940,8 +963,9 @@ static inline void *net_if_l2_data(struct net_if *iface) */ static inline const struct device *net_if_get_device(struct net_if *iface) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NULL; + } return iface->if_dev->dev; } @@ -992,8 +1016,9 @@ bool net_if_is_offloaded(struct net_if *iface); static inline struct net_offload *net_if_offload(struct net_if *iface) { #if defined(CONFIG_NET_OFFLOAD) - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NULL; + } return iface->if_dev->offload; #else @@ -1013,8 +1038,9 @@ static inline struct net_offload *net_if_offload(struct net_if *iface) static inline bool net_if_is_socket_offloaded(struct net_if *iface) { #if defined(CONFIG_NET_SOCKETS_OFFLOAD) - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return false; + } return (iface->if_dev->socket_offload != NULL); #else @@ -1034,8 +1060,9 @@ static inline void net_if_socket_offload_set( struct net_if *iface, net_socket_create_t socket_offload) { #if defined(CONFIG_NET_SOCKETS_OFFLOAD) - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return; + } iface->if_dev->socket_offload = socket_offload; #else @@ -1054,8 +1081,9 @@ static inline void net_if_socket_offload_set( static inline net_socket_create_t net_if_socket_offload(struct net_if *iface) { #if defined(CONFIG_NET_SOCKETS_OFFLOAD) - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NULL; + } return iface->if_dev->socket_offload; #else @@ -1074,8 +1102,9 @@ static inline net_socket_create_t net_if_socket_offload(struct net_if *iface) */ static inline struct net_linkaddr *net_if_get_link_addr(struct net_if *iface) { - NET_ASSERT(iface); - NET_ASSERT(iface->if_dev); + if (iface == NULL || iface->if_dev == NULL) { + return NULL; + } return &iface->if_dev->link_addr; } @@ -1089,7 +1118,9 @@ static inline struct net_linkaddr *net_if_get_link_addr(struct net_if *iface) */ static inline struct net_if_config *net_if_get_config(struct net_if *iface) { - NET_ASSERT(iface); + if (iface == NULL) { + return NULL; + } return &iface->config; } @@ -1233,12 +1264,10 @@ static inline int net_if_set_link_addr(struct net_if *iface, */ static inline uint16_t net_if_get_mtu(struct net_if *iface) { - if (iface == NULL) { + if (iface == NULL || iface->if_dev == NULL) { return 0U; } - NET_ASSERT(iface->if_dev); - return iface->if_dev->mtu; } @@ -1251,12 +1280,10 @@ static inline uint16_t net_if_get_mtu(struct net_if *iface) static inline void net_if_set_mtu(struct net_if *iface, uint16_t mtu) { - if (iface == NULL) { + if (iface == NULL || iface->if_dev == NULL) { return; } - NET_ASSERT(iface->if_dev); - iface->if_dev->mtu = mtu; } @@ -1269,7 +1296,9 @@ static inline void net_if_set_mtu(struct net_if *iface, static inline void net_if_addr_set_lf(struct net_if_addr *ifaddr, bool is_infinite) { - NET_ASSERT(ifaddr); + if (ifaddr == NULL) { + return; + } ifaddr->is_infinite = is_infinite; } @@ -1301,7 +1330,9 @@ struct net_if *net_if_lookup_by_dev(const struct device *dev); */ static inline struct net_if_config *net_if_config_get(struct net_if *iface) { - NET_ASSERT(iface); + if (iface == NULL) { + return NULL; + } return &iface->config; } @@ -1632,7 +1663,9 @@ void net_if_ipv6_maddr_join(struct net_if *iface, */ static inline bool net_if_ipv6_maddr_is_joined(struct net_if_mcast_addr *addr) { - NET_ASSERT(addr); + if (addr == NULL) { + return false; + } return addr->is_joined; } @@ -1746,7 +1779,9 @@ bool net_if_ipv6_addr_onlink(struct net_if **iface, struct in6_addr *addr); #if defined(CONFIG_NET_NATIVE_IPV6) static inline struct in6_addr *net_if_router_ipv6(struct net_if_router *router) { - NET_ASSERT(router); + if (router == NULL) { + return NULL; + } return &router->address.in6_addr; } @@ -1824,7 +1859,16 @@ bool net_if_ipv6_router_rm(struct net_if_router *router); * * @return Hop limit */ +#if defined(CONFIG_NET_NATIVE_IPV6) uint8_t net_if_ipv6_get_hop_limit(struct net_if *iface); +#else +static inline uint8_t net_if_ipv6_get_hop_limit(struct net_if *iface) +{ + ARG_UNUSED(iface); + + return 0; +} +#endif /* CONFIG_NET_NATIVE_IPV6 */ /** * @brief Set the default IPv6 hop limit of a given interface. @@ -1832,7 +1876,16 @@ uint8_t net_if_ipv6_get_hop_limit(struct net_if *iface); * @param iface Network interface * @param hop_limit New hop limit */ +#if defined(CONFIG_NET_NATIVE_IPV6) void net_if_ipv6_set_hop_limit(struct net_if *iface, uint8_t hop_limit); +#else +static inline void net_if_ipv6_set_hop_limit(struct net_if *iface, + uint8_t hop_limit) +{ + ARG_UNUSED(iface); + ARG_UNUSED(hop_limit); +} +#endif /* CONFIG_NET_NATIVE_IPV6 */ /** @cond INTERNAL_HIDDEN */ @@ -1857,7 +1910,16 @@ static inline void net_ipv6_set_hop_limit(struct net_if *iface, * * @return Hop limit */ +#if defined(CONFIG_NET_NATIVE_IPV6) uint8_t net_if_ipv6_get_mcast_hop_limit(struct net_if *iface); +#else +static inline uint8_t net_if_ipv6_get_mcast_hop_limit(struct net_if *iface) +{ + ARG_UNUSED(iface); + + return 0; +} +#endif /* CONFIG_NET_NATIVE_IPV6 */ /** * @brief Set the default IPv6 multicast hop limit of a given interface. @@ -1865,7 +1927,16 @@ uint8_t net_if_ipv6_get_mcast_hop_limit(struct net_if *iface); * @param iface Network interface * @param hop_limit New hop limit */ +#if defined(CONFIG_NET_NATIVE_IPV6) void net_if_ipv6_set_mcast_hop_limit(struct net_if *iface, uint8_t hop_limit); +#else +static inline void net_if_ipv6_set_mcast_hop_limit(struct net_if *iface, + uint8_t hop_limit) +{ + ARG_UNUSED(iface); + ARG_UNUSED(hop_limit); +} +#endif /* CONFIG_NET_NATIVE_IPV6 */ /** * @brief Set IPv6 reachable time for a given interface @@ -1877,7 +1948,9 @@ static inline void net_if_ipv6_set_base_reachable_time(struct net_if *iface, uint32_t reachable_time) { #if defined(CONFIG_NET_NATIVE_IPV6) - NET_ASSERT(iface); + if (iface == NULL) { + return; + } if (!iface->config.ip.ipv6) { return; @@ -1901,7 +1974,9 @@ static inline void net_if_ipv6_set_base_reachable_time(struct net_if *iface, static inline uint32_t net_if_ipv6_get_reachable_time(struct net_if *iface) { #if defined(CONFIG_NET_NATIVE_IPV6) - NET_ASSERT(iface); + if (iface == NULL) { + return 0; + } if (!iface->config.ip.ipv6) { return 0; @@ -1952,7 +2027,9 @@ static inline void net_if_ipv6_set_retrans_timer(struct net_if *iface, uint32_t retrans_timer) { #if defined(CONFIG_NET_NATIVE_IPV6) - NET_ASSERT(iface); + if (iface == NULL) { + return; + } if (!iface->config.ip.ipv6) { return; @@ -1975,7 +2052,9 @@ static inline void net_if_ipv6_set_retrans_timer(struct net_if *iface, static inline uint32_t net_if_ipv6_get_retrans_timer(struct net_if *iface) { #if defined(CONFIG_NET_NATIVE_IPV6) - NET_ASSERT(iface); + if (iface == NULL) { + return 0; + } if (!iface->config.ip.ipv6) { return 0; @@ -1999,7 +2078,7 @@ static inline uint32_t net_if_ipv6_get_retrans_timer(struct net_if *iface) * @return Pointer to IPv6 address to use, NULL if no IPv6 address * could be found. */ -#if defined(CONFIG_NET_NATIVE_IPV6) +#if defined(CONFIG_NET_IPV6) const struct in6_addr *net_if_ipv6_select_src_addr(struct net_if *iface, const struct in6_addr *dst); #else @@ -2026,7 +2105,7 @@ static inline const struct in6_addr *net_if_ipv6_select_src_addr( * @return Pointer to IPv6 address to use, NULL if no IPv6 address * could be found. */ -#if defined(CONFIG_NET_NATIVE_IPV6) +#if defined(CONFIG_NET_IPV6) const struct in6_addr *net_if_ipv6_select_src_addr_hint(struct net_if *iface, const struct in6_addr *dst, int flags); @@ -2051,7 +2130,7 @@ static inline const struct in6_addr *net_if_ipv6_select_src_addr_hint( * @return Pointer to network interface to use, NULL if no suitable interface * could be found. */ -#if defined(CONFIG_NET_NATIVE_IPV6) +#if defined(CONFIG_NET_IPV6) struct net_if *net_if_ipv6_select_src_iface(const struct in6_addr *dst); #else static inline struct net_if *net_if_ipv6_select_src_iface( @@ -2312,7 +2391,9 @@ void net_if_ipv4_maddr_join(struct net_if *iface, */ static inline bool net_if_ipv4_maddr_is_joined(struct net_if_mcast_addr *addr) { - NET_ASSERT(addr); + if (addr == NULL) { + return false; + } return addr->is_joined; } @@ -2335,7 +2416,9 @@ void net_if_ipv4_maddr_leave(struct net_if *iface, #if defined(CONFIG_NET_NATIVE_IPV4) static inline struct in_addr *net_if_router_ipv4(struct net_if_router *router) { - NET_ASSERT(router); + if (router == NULL) { + return NULL; + } return &router->address.in_addr; } @@ -2428,7 +2511,7 @@ bool net_if_ipv4_is_addr_bcast(struct net_if *iface, * @return Pointer to network interface to use, NULL if no suitable interface * could be found. */ -#if defined(CONFIG_NET_NATIVE_IPV4) +#if defined(CONFIG_NET_IPV4) struct net_if *net_if_ipv4_select_src_iface(const struct in_addr *dst); #else static inline struct net_if *net_if_ipv4_select_src_iface( @@ -2451,7 +2534,7 @@ static inline struct net_if *net_if_ipv4_select_src_iface( * @return Pointer to IPv4 address to use, NULL if no IPv4 address * could be found. */ -#if defined(CONFIG_NET_NATIVE_IPV4) +#if defined(CONFIG_NET_IPV4) const struct in_addr *net_if_ipv4_select_src_addr(struct net_if *iface, const struct in_addr *dst); #else @@ -2562,6 +2645,15 @@ bool net_if_ipv4_set_netmask_by_addr(struct net_if *iface, const struct in_addr *addr, const struct in_addr *netmask); +/** + * @brief Get IPv4 gateway of an interface. + * + * @param iface Interface to use. + * + * @return The gateway set on the interface, unspecified address if not found. + */ +struct in_addr net_if_ipv4_get_gw(struct net_if *iface); + /** * @brief Set IPv4 gateway for an interface. * @@ -2773,7 +2865,9 @@ int net_if_up(struct net_if *iface); */ static inline bool net_if_is_up(struct net_if *iface) { - NET_ASSERT(iface); + if (iface == NULL) { + return false; + } return net_if_flag_is_set(iface, NET_IF_UP) && net_if_flag_is_set(iface, NET_IF_RUNNING); @@ -2797,7 +2891,9 @@ int net_if_down(struct net_if *iface); */ static inline bool net_if_is_admin_up(struct net_if *iface) { - NET_ASSERT(iface); + if (iface == NULL) { + return false; + } return net_if_flag_is_set(iface, NET_IF_UP); } @@ -2831,7 +2927,9 @@ void net_if_carrier_off(struct net_if *iface); */ static inline bool net_if_is_carrier_ok(struct net_if *iface) { - NET_ASSERT(iface); + if (iface == NULL) { + return false; + } return net_if_flag_is_set(iface, NET_IF_LOWER_UP); } @@ -2867,7 +2965,9 @@ void net_if_dormant_off(struct net_if *iface); */ static inline bool net_if_is_dormant(struct net_if *iface) { - NET_ASSERT(iface); + if (iface == NULL) { + return false; + } return net_if_flag_is_set(iface, NET_IF_DORMANT); } @@ -3140,12 +3240,24 @@ struct net_if_api { NET_IF_DHCPV6_INIT \ } +#define NET_PROMETHEUS_GET_COLLECTOR_NAME(dev_id, sfx) \ + net_stats_##dev_id##_##sfx##_collector +#define NET_PROMETHEUS_INIT(dev_id, sfx) \ + IF_ENABLED(CONFIG_NET_STATISTICS_VIA_PROMETHEUS, \ + (.collector = &NET_PROMETHEUS_GET_COLLECTOR_NAME(dev_id, sfx),)) + #define NET_IF_GET_NAME(dev_id, sfx) __net_if_##dev_id##_##sfx #define NET_IF_DEV_GET_NAME(dev_id, sfx) __net_if_dev_##dev_id##_##sfx #define NET_IF_GET(dev_id, sfx) \ ((struct net_if *)&NET_IF_GET_NAME(dev_id, sfx)) +#if defined(CONFIG_NET_STATISTICS_VIA_PROMETHEUS) +extern int net_stats_prometheus_scrape(struct prometheus_collector *collector, + struct prometheus_metric *metric, + void *user_data); +#endif /* CONFIG_NET_STATISTICS_VIA_PROMETHEUS */ + #define NET_IF_INIT(dev_id, sfx, _l2, _mtu, _num_configs) \ static STRUCT_SECTION_ITERABLE(net_if_dev, \ NET_IF_DEV_GET_NAME(dev_id, sfx)) = { \ @@ -3163,7 +3275,15 @@ struct net_if_api { .if_dev = &(NET_IF_DEV_GET_NAME(dev_id, sfx)), \ NET_IF_CONFIG_INIT \ } \ - } + }; \ + IF_ENABLED(CONFIG_NET_STATISTICS_VIA_PROMETHEUS, \ + (static PROMETHEUS_COLLECTOR_DEFINE( \ + NET_PROMETHEUS_GET_COLLECTOR_NAME(dev_id, \ + sfx), \ + net_stats_prometheus_scrape, \ + NET_IF_GET(dev_id, sfx)); \ + NET_STATS_PROMETHEUS(NET_IF_GET(dev_id, sfx), \ + dev_id, sfx);)) #define NET_IF_OFFLOAD_INIT(dev_id, sfx, _mtu) \ static STRUCT_SECTION_ITERABLE(net_if_dev, \ @@ -3181,7 +3301,16 @@ struct net_if_api { .if_dev = &(NET_IF_DEV_GET_NAME(dev_id, sfx)), \ NET_IF_CONFIG_INIT \ } \ - } + }; \ + IF_ENABLED(CONFIG_NET_STATISTICS_VIA_PROMETHEUS, \ + (static PROMETHEUS_COLLECTOR_DEFINE( \ + NET_PROMETHEUS_GET_COLLECTOR_NAME(dev_id, \ + sfx), \ + net_stats_prometheus_scrape, \ + NET_IF_GET(dev_id, sfx)); \ + NET_STATS_PROMETHEUS(NET_IF_GET(dev_id, sfx), \ + dev_id, sfx);)) + /** @endcond */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_ip.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_ip.h index 86fb06ee..214b90cd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_ip.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_ip.h @@ -16,6 +16,8 @@ /** * @brief IPv4/IPv6 primitives and helpers * @defgroup ip_4_6 IPv4/IPv6 primitives and helpers + * @since 1.0 + * @version 1.0.0 * @ingroup networking * @{ */ @@ -63,6 +65,7 @@ enum net_ip_protocol { IPPROTO_IP = 0, /**< IP protocol (pseudo-val for setsockopt() */ IPPROTO_ICMP = 1, /**< ICMP protocol */ IPPROTO_IGMP = 2, /**< IGMP protocol */ + IPPROTO_ETH_P_ALL = 3, /**< Every packet. from linux if_ether.h */ IPPROTO_IPIP = 4, /**< IPIP tunnels */ IPPROTO_TCP = 6, /**< TCP protocol */ IPPROTO_UDP = 17, /**< UDP protocol */ @@ -76,6 +79,7 @@ enum net_ip_protocol_secure { IPPROTO_TLS_1_0 = 256, /**< TLS 1.0 protocol */ IPPROTO_TLS_1_1 = 257, /**< TLS 1.1 protocol */ IPPROTO_TLS_1_2 = 258, /**< TLS 1.2 protocol */ + IPPROTO_TLS_1_3 = 259, /**< TLS 1.3 protocol */ IPPROTO_DTLS_1_0 = 272, /**< DTLS 1.0 protocol */ IPPROTO_DTLS_1_2 = 273, /**< DTLS 1.2 protocol */ }; @@ -228,6 +232,12 @@ struct sockaddr_ll_ptr { uint8_t *sll_addr; /**< Physical-layer address, big endian */ }; +/** Socket address struct for unix socket where address is a pointer */ +struct sockaddr_un_ptr { + sa_family_t sun_family; /**< Always AF_UNIX */ + char *sun_path; /**< pathname */ +}; + struct sockaddr_can_ptr { sa_family_t can_family; int can_ifindex; @@ -370,14 +380,27 @@ struct cmsghdr { #endif #endif +#if defined(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS) +#define UNIX_PATH_MAX 108 +#undef NET_SOCKADDR_MAX_SIZE +/* Define NET_SOCKADDR_MAX_SIZE to be struct of sa_family_t + char[UNIX_PATH_MAX] */ +#define NET_SOCKADDR_MAX_SIZE (UNIX_PATH_MAX+sizeof(sa_family_t)) +#if !defined(CONFIG_NET_SOCKETS_PACKET) +#undef NET_SOCKADDR_PTR_MAX_SIZE +#define NET_SOCKADDR_PTR_MAX_SIZE (sizeof(struct sockaddr_un_ptr)) +#endif +#endif + #if !defined(CONFIG_NET_IPV4) #if !defined(CONFIG_NET_IPV6) #if !defined(CONFIG_NET_SOCKETS_PACKET) +#if !defined(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS) #define NET_SOCKADDR_MAX_SIZE (sizeof(struct sockaddr_in6)) #define NET_SOCKADDR_PTR_MAX_SIZE (sizeof(struct sockaddr_in6_ptr)) #endif #endif #endif +#endif /** @endcond */ @@ -435,6 +458,9 @@ extern const struct in6_addr in6addr_loopback; /** IPv4 any address */ #define INADDR_ANY 0 +/** IPv4 broadcast address */ +#define INADDR_BROADCAST 0xffffffff + /** IPv4 address initializer */ #define INADDR_ANY_INIT { { { INADDR_ANY } } } @@ -743,6 +769,38 @@ static inline bool net_ipv6_is_prefix(const uint8_t *addr1, return (addr1[bytes] & mask) == (addr2[bytes] & mask); } + +/** + * @brief Get the IPv6 network address via the unicast address and the prefix mask. + * + * @param inaddr Unicast IPv6 address. + * @param outaddr Prefix masked IPv6 address (network address). + * @param prefix_len Prefix length (max length is 128). + */ +static inline void net_ipv6_addr_prefix_mask(const uint8_t *inaddr, + uint8_t *outaddr, + uint8_t prefix_len) +{ + uint8_t bits = 128 - prefix_len; + uint8_t bytes = prefix_len / 8U; + uint8_t remain = bits % 8; + uint8_t mask; + + memset(outaddr, 0, 16U); + memcpy(outaddr, inaddr, bytes); + + if (!remain) { + /* No remaining bits, the prefixes are the same as first + * bytes are the same. + */ + return; + } + + /* Create a mask that has remaining most significant bits set */ + mask = (uint8_t)((0xff << (8 - remain)) ^ 0xff) << remain; + outaddr[bytes] = inaddr[bytes] & mask; +} + /** * @brief Check if the IPv4 address is a loopback address (127.0.0.0/8). * @@ -1401,7 +1459,32 @@ static inline bool net_ipv6_addr_is_v4_mapped(const struct in6_addr *addr) } /** - * @brief Create IPv6 address interface identifier + * @brief Generate IPv6 address using a prefix and interface identifier. + * Interface identifier is either generated from EUI-64 (MAC) defined + * in RFC 4291 or from randomized value defined in RFC 7217. + * + * @param iface Network interface + * @param prefix IPv6 prefix, can be left out in which case fe80::/64 is used + * @param network_id Network identifier (for example SSID in WLAN), this is + * optional can be set to NULL + * @param network_id_len Network identifier length, if set to 0 then the + * network id is ignored. + * @param dad_counter Duplicate Address Detection counter value, can be set to 0 + * if it is not known. + * @param addr IPv6 address + * @param lladdr Link local address + * + * @return 0 if ok, < 0 if error + */ +int net_ipv6_addr_generate_iid(struct net_if *iface, + const struct in6_addr *prefix, + uint8_t *network_id, size_t network_id_len, + uint8_t dad_counter, + struct in6_addr *addr, + struct net_linkaddr *lladdr); + +/** + * @brief Create IPv6 address interface identifier. * * @param addr IPv6 address * @param lladdr Link local address @@ -1409,43 +1492,7 @@ static inline bool net_ipv6_addr_is_v4_mapped(const struct in6_addr *addr) static inline void net_ipv6_addr_create_iid(struct in6_addr *addr, struct net_linkaddr *lladdr) { - UNALIGNED_PUT(htonl(0xfe800000), &addr->s6_addr32[0]); - UNALIGNED_PUT(0, &addr->s6_addr32[1]); - - switch (lladdr->len) { - case 2: - /* The generated IPv6 shall not toggle the - * Universal/Local bit. RFC 6282 ch 3.2.2 - */ - if (lladdr->type == NET_LINK_IEEE802154) { - UNALIGNED_PUT(0, &addr->s6_addr32[2]); - addr->s6_addr[11] = 0xff; - addr->s6_addr[12] = 0xfe; - addr->s6_addr[13] = 0U; - addr->s6_addr[14] = lladdr->addr[0]; - addr->s6_addr[15] = lladdr->addr[1]; - } - - break; - case 6: - /* We do not toggle the Universal/Local bit - * in Bluetooth. See RFC 7668 ch 3.2.2 - */ - memcpy(&addr->s6_addr[8], lladdr->addr, 3); - addr->s6_addr[11] = 0xff; - addr->s6_addr[12] = 0xfe; - memcpy(&addr->s6_addr[13], lladdr->addr + 3, 3); - - if (lladdr->type == NET_LINK_ETHERNET) { - addr->s6_addr[8] ^= 0x02; - } - - break; - case 8: - memcpy(&addr->s6_addr[8], lladdr->addr, lladdr->len); - addr->s6_addr[8] ^= 0x02; - break; - } + (void)net_ipv6_addr_generate_iid(NULL, NULL, NULL, 0, 0, addr, lladdr); } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_l2.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_l2.h index 30085728..37c9b083 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_l2.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_l2.h @@ -13,7 +13,7 @@ #define ZEPHYR_INCLUDE_NET_NET_L2_H_ #include -#include +#include #include #include @@ -24,6 +24,8 @@ extern "C" { /** * @brief Network Layer 2 abstraction layer * @defgroup net_l2 Network L2 Abstraction Layer + * @since 1.5 + * @version 1.0.0 * @ingroup networking * @{ */ @@ -85,47 +87,31 @@ struct net_l2 { extern const struct net_l2 NET_L2_GET_NAME(_name) #define NET_L2_GET_CTX_TYPE(_name) _name##_CTX_TYPE -#ifdef CONFIG_NET_L2_VIRTUAL #define VIRTUAL_L2 VIRTUAL NET_L2_DECLARE_PUBLIC(VIRTUAL_L2); -#endif /* CONFIG_NET_L2_DUMMY */ -#ifdef CONFIG_NET_L2_DUMMY #define DUMMY_L2 DUMMY #define DUMMY_L2_CTX_TYPE void* NET_L2_DECLARE_PUBLIC(DUMMY_L2); -#endif /* CONFIG_NET_L2_DUMMY */ -#if defined(CONFIG_NET_OFFLOAD) || defined(CONFIG_NET_SOCKETS_OFFLOAD) #define OFFLOADED_NETDEV_L2 OFFLOADED_NETDEV NET_L2_DECLARE_PUBLIC(OFFLOADED_NETDEV_L2); -#endif /* CONFIG_NET_OFFLOAD || CONFIG_NET_SOCKETS_OFFLOAD */ -#ifdef CONFIG_NET_L2_ETHERNET #define ETHERNET_L2 ETHERNET NET_L2_DECLARE_PUBLIC(ETHERNET_L2); -#endif /* CONFIG_NET_L2_ETHERNET */ -#ifdef CONFIG_NET_L2_PPP #define PPP_L2 PPP NET_L2_DECLARE_PUBLIC(PPP_L2); -#endif /* CONFIG_NET_L2_PPP */ -#ifdef CONFIG_NET_L2_IEEE802154 #define IEEE802154_L2 IEEE802154 NET_L2_DECLARE_PUBLIC(IEEE802154_L2); -#endif /* CONFIG_NET_L2_IEEE802154 */ -#ifdef CONFIG_NET_L2_OPENTHREAD #define OPENTHREAD_L2 OPENTHREAD NET_L2_DECLARE_PUBLIC(OPENTHREAD_L2); -#endif /* CONFIG_NET_L2_OPENTHREAD */ -#ifdef CONFIG_NET_L2_CANBUS_RAW #define CANBUS_RAW_L2 CANBUS_RAW #define CANBUS_RAW_L2_CTX_TYPE void* NET_L2_DECLARE_PUBLIC(CANBUS_RAW_L2); -#endif /* CONFIG_NET_L2_CANBUS_RAW */ #ifdef CONFIG_NET_L2_CUSTOM_IEEE802154 #ifndef CUSTOM_IEEE802154_L2 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_linkaddr.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_linkaddr.h index 9e21e7dc..e5f0d5f2 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_linkaddr.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_linkaddr.h @@ -23,6 +23,8 @@ extern "C" { /** * @brief Network link address library * @defgroup net_linkaddr Network Link Address Library + * @since 1.0 + * @version 1.0.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_mgmt.h index 46c5e6aa..fe3ee7f9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_mgmt.h @@ -24,6 +24,8 @@ extern "C" { /** * @brief Network Management * @defgroup net_mgmt Network Management + * @since 1.7 + * @version 1.0.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_offload.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_offload.h index 30435127..f1752672 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_offload.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_offload.h @@ -15,11 +15,13 @@ /** * @brief Network offloading interface * @defgroup net_offload Network Offloading Interface + * @since 1.7 + * @version 0.8.0 * @ingroup networking * @{ */ -#include +#include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt.h index 3f7df54e..1a3b4a04 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt.h @@ -19,7 +19,7 @@ #include #include -#include +#include #if defined(CONFIG_IEEE802154) #include @@ -40,6 +40,8 @@ extern "C" { /** * @brief Network packet management library * @defgroup net_pkt Network Packet Library + * @since 1.5 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -48,6 +50,28 @@ struct net_context; /** @cond INTERNAL_HIDDEN */ +#if defined(CONFIG_NET_PKT_ALLOC_STATS) +struct net_pkt_alloc_stats { + uint64_t alloc_sum; + uint64_t time_sum; + uint32_t count; +}; + +struct net_pkt_alloc_stats_slab { + struct net_pkt_alloc_stats ok; + struct net_pkt_alloc_stats fail; + struct k_mem_slab *slab; +}; + +#define NET_PKT_ALLOC_STATS_DEFINE(alloc_name, slab_name) \ + STRUCT_SECTION_ITERABLE(net_pkt_alloc_stats_slab, alloc_name) = { \ + .slab = &slab_name, \ + } + +#else +#define NET_PKT_ALLOC_STATS_DEFINE(name, slab) +#endif /* CONFIG_NET_PKT_ALLOC_STATS */ + /* buffer cursor used in net_pkt */ struct net_pkt_cursor { /** Current net_buf pointer by the cursor */ @@ -121,7 +145,8 @@ struct net_pkt { struct net_ptp_time timestamp; #endif -#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS) +#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS) || \ + defined(CONFIG_TRACING_NET_CORE) struct { /** Create time in cycles */ uint32_t create_time; @@ -142,6 +167,10 @@ struct net_pkt { }; #endif /* CONFIG_NET_PKT_RXTIME_STATS || CONFIG_NET_PKT_TXTIME_STATS */ +#if defined(CONFIG_NET_PKT_ALLOC_STATS) + struct net_pkt_alloc_stats_slab *alloc_stats; +#endif /* CONFIG_NET_PKT_ALLOC_STATS */ + /** Reference counter */ atomic_t atomic_ref; @@ -313,6 +342,11 @@ struct net_pkt { uint8_t cooked_mode_pkt : 1; #endif /* CONFIG_NET_CAPTURE_COOKED_MODE */ +#if defined(CONFIG_NET_IPV4_PMTU) + /* Path MTU needed for this destination address */ + uint8_t ipv4_pmtu : 1; +#endif /* CONFIG_NET_IPV4_PMTU */ + /* @endcond */ }; @@ -754,6 +788,31 @@ static inline uint16_t net_pkt_ip_opts_len(struct net_pkt *pkt) #endif } +#if defined(CONFIG_NET_IPV4_PMTU) +static inline bool net_pkt_ipv4_pmtu(struct net_pkt *pkt) +{ + return !!pkt->ipv4_pmtu; +} + +static inline void net_pkt_set_ipv4_pmtu(struct net_pkt *pkt, bool value) +{ + pkt->ipv4_pmtu = value; +} +#else +static inline bool net_pkt_ipv4_pmtu(struct net_pkt *pkt) +{ + ARG_UNUSED(pkt); + + return false; +} + +static inline void net_pkt_set_ipv4_pmtu(struct net_pkt *pkt, bool value) +{ + ARG_UNUSED(pkt); + ARG_UNUSED(value); +} +#endif /* CONFIG_NET_IPV4_PMTU */ + #if defined(CONFIG_NET_IPV4_FRAGMENT) static inline uint16_t net_pkt_ipv4_fragment_offset(struct net_pkt *pkt) { @@ -1105,7 +1164,9 @@ static inline void net_pkt_set_timestamp_ns(struct net_pkt *pkt, net_time_t time } #endif /* CONFIG_NET_PKT_TIMESTAMP || CONFIG_NET_PKT_TXTIME */ -#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS) +#if defined(CONFIG_NET_PKT_RXTIME_STATS) || defined(CONFIG_NET_PKT_TXTIME_STATS) || \ + defined(CONFIG_TRACING_NET_CORE) + static inline uint32_t net_pkt_create_time(struct net_pkt *pkt) { return pkt->create_time; @@ -1130,36 +1191,9 @@ static inline void net_pkt_set_create_time(struct net_pkt *pkt, ARG_UNUSED(pkt); ARG_UNUSED(create_time); } -#endif /* CONFIG_NET_PKT_RXTIME_STATS || CONFIG_NET_PKT_TXTIME_STATS */ - -/** - * @deprecated Use @ref net_pkt_timestamp or @ref net_pkt_timestamp_ns instead. - */ -static inline uint64_t net_pkt_txtime(struct net_pkt *pkt) -{ -#if defined(CONFIG_NET_PKT_TXTIME) - return pkt->timestamp.second * NSEC_PER_SEC + pkt->timestamp.nanosecond; -#else - ARG_UNUSED(pkt); - - return 0; -#endif /* CONFIG_NET_PKT_TXTIME */ -} - -/** - * @deprecated Use @ref net_pkt_set_timestamp or @ref net_pkt_set_timestamp_ns - * instead. - */ -static inline void net_pkt_set_txtime(struct net_pkt *pkt, uint64_t txtime) -{ -#if defined(CONFIG_NET_PKT_TXTIME) - pkt->timestamp.second = txtime / NSEC_PER_SEC; - pkt->timestamp.nanosecond = txtime % NSEC_PER_SEC; -#else - ARG_UNUSED(pkt); - ARG_UNUSED(txtime); -#endif /* CONFIG_NET_PKT_TXTIME */ -} +#endif /* CONFIG_NET_PKT_RXTIME_STATS || CONFIG_NET_PKT_TXTIME_STATS || + * CONFIG_TRACING_NET_CORE + */ #if defined(CONFIG_NET_PKT_TXTIME_STATS_DETAIL) || \ defined(CONFIG_NET_PKT_RXTIME_STATS_DETAIL) @@ -1474,7 +1508,8 @@ static inline void net_pkt_set_remote_address(struct net_pkt *pkt, * @param count Number of net_pkt in this slab. */ #define NET_PKT_SLAB_DEFINE(name, count) \ - K_MEM_SLAB_DEFINE(name, sizeof(struct net_pkt), count, 4) + K_MEM_SLAB_DEFINE(name, sizeof(struct net_pkt), count, 4); \ + NET_PKT_ALLOC_STATS_DEFINE(pkt_alloc_stats_##name, name) /** @cond INTERNAL_HIDDEN */ @@ -1579,6 +1614,7 @@ void net_pkt_frag_insert_debug(struct net_pkt *pkt, struct net_buf *frag, */ /** @endcond */ +#if defined(NET_PKT_DEBUG_ENABLED) /** * @brief Print fragment list and the fragment sizes * @@ -1586,12 +1622,12 @@ void net_pkt_frag_insert_debug(struct net_pkt *pkt, struct net_buf *frag, * * @param pkt Network pkt. */ -#if defined(NET_PKT_DEBUG_ENABLED) void net_pkt_print_frags(struct net_pkt *pkt); #else #define net_pkt_print_frags(pkt) #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Get a data buffer from a given pool. * @@ -1606,11 +1642,11 @@ void net_pkt_print_frags(struct net_pkt *pkt); * * @return Network buffer if successful, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_buf *net_pkt_get_reserve_data(struct net_buf_pool *pool, size_t min_len, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Get RX DATA buffer from pool. * Normally you should use net_pkt_get_frag() instead. @@ -1625,10 +1661,10 @@ struct net_buf *net_pkt_get_reserve_data(struct net_buf_pool *pool, * * @return Network buffer if successful, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_buf *net_pkt_get_reserve_rx_data(size_t min_len, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Get TX DATA buffer from pool. * Normally you should use net_pkt_get_frag() instead. @@ -1643,10 +1679,10 @@ struct net_buf *net_pkt_get_reserve_rx_data(size_t min_len, k_timeout_t timeout) * * @return Network buffer if successful, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_buf *net_pkt_get_reserve_tx_data(size_t min_len, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Get a data fragment that might be from user specific * buffer pool or from global DATA pool. @@ -1659,11 +1695,11 @@ struct net_buf *net_pkt_get_reserve_tx_data(size_t min_len, k_timeout_t timeout) * * @return Network buffer if successful, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_buf *net_pkt_get_frag(struct net_pkt *pkt, size_t min_len, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Place packet back into the available packets slab * @@ -1673,10 +1709,10 @@ struct net_buf *net_pkt_get_frag(struct net_pkt *pkt, size_t min_len, * @param pkt Network packet to release. * */ -#if !defined(NET_PKT_DEBUG_ENABLED) void net_pkt_unref(struct net_pkt *pkt); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Increase the packet ref count * @@ -1686,10 +1722,10 @@ void net_pkt_unref(struct net_pkt *pkt); * * @return Network packet if successful, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_pkt *net_pkt_ref(struct net_pkt *pkt); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Increase the packet fragment ref count * @@ -1699,19 +1735,19 @@ struct net_pkt *net_pkt_ref(struct net_pkt *pkt); * * @return a pointer on the referenced Network fragment. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_buf *net_pkt_frag_ref(struct net_buf *frag); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Decrease the packet fragment ref count * * @param frag Network fragment to unref. */ -#if !defined(NET_PKT_DEBUG_ENABLED) void net_pkt_frag_unref(struct net_buf *frag); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Delete existing fragment from a packet * @@ -1722,29 +1758,28 @@ void net_pkt_frag_unref(struct net_buf *frag); * @return Pointer to the following fragment, or NULL if it had no * further fragments. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_buf *net_pkt_frag_del(struct net_pkt *pkt, struct net_buf *parent, struct net_buf *frag); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Add a fragment to a packet at the end of its fragment list * * @param pkt pkt Network packet where to add the fragment * @param frag Fragment to add */ -#if !defined(NET_PKT_DEBUG_ENABLED) void net_pkt_frag_add(struct net_pkt *pkt, struct net_buf *frag); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Insert a fragment to a packet at the beginning of its fragment list * * @param pkt pkt Network packet where to insert the fragment * @param frag Fragment to insert */ -#if !defined(NET_PKT_DEBUG_ENABLED) void net_pkt_frag_insert(struct net_pkt *pkt, struct net_buf *frag); #endif @@ -1875,6 +1910,7 @@ struct net_pkt *net_pkt_rx_alloc_with_buffer_debug(struct net_if *iface, #endif /* NET_PKT_DEBUG_ENABLED */ /** @endcond */ +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate an initialized net_pkt * @@ -1885,10 +1921,10 @@ struct net_pkt *net_pkt_rx_alloc_with_buffer_debug(struct net_if *iface, * * @return a pointer to a newly allocated net_pkt on success, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_pkt *net_pkt_alloc(k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate an initialized net_pkt from a specific slab * @@ -1903,11 +1939,11 @@ struct net_pkt *net_pkt_alloc(k_timeout_t timeout); * * @return a pointer to a newly allocated net_pkt on success, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_pkt *net_pkt_alloc_from_slab(struct k_mem_slab *slab, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate an initialized net_pkt for RX * @@ -1918,10 +1954,10 @@ struct net_pkt *net_pkt_alloc_from_slab(struct k_mem_slab *slab, * * @return a pointer to a newly allocated net_pkt on success, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_pkt *net_pkt_rx_alloc(k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate a network packet for a specific network interface. * @@ -1930,7 +1966,6 @@ struct net_pkt *net_pkt_rx_alloc(k_timeout_t timeout); * * @return a pointer to a newly allocated net_pkt on success, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_pkt *net_pkt_alloc_on_iface(struct net_if *iface, k_timeout_t timeout); @@ -1943,6 +1978,7 @@ struct net_pkt *net_pkt_rx_alloc_on_iface(struct net_if *iface, #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate buffer for a net_pkt * @@ -1958,13 +1994,13 @@ struct net_pkt *net_pkt_rx_alloc_on_iface(struct net_if *iface, * * @return 0 on success, negative errno code otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) int net_pkt_alloc_buffer(struct net_pkt *pkt, size_t size, enum net_ip_protocol proto, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate buffer for a net_pkt, of specified size, w/o any additional * preconditions @@ -1978,11 +2014,11 @@ int net_pkt_alloc_buffer(struct net_pkt *pkt, * * @return 0 on success, negative errno code otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) int net_pkt_alloc_buffer_raw(struct net_pkt *pkt, size_t size, k_timeout_t timeout); #endif +#if !defined(NET_PKT_DEBUG_ENABLED) /** * @brief Allocate a network packet and buffer at once * @@ -1994,7 +2030,6 @@ int net_pkt_alloc_buffer_raw(struct net_pkt *pkt, size_t size, * * @return a pointer to a newly allocated net_pkt on success, NULL otherwise. */ -#if !defined(NET_PKT_DEBUG_ENABLED) struct net_pkt *net_pkt_alloc_with_buffer(struct net_if *iface, size_t size, sa_family_t family, diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt_filter.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt_filter.h index 753ca347..15406b6e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt_filter.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_pkt_filter.h @@ -27,6 +27,8 @@ extern "C" { /** * @brief Network Packet Filter API * @defgroup net_pkt_filter Network Packet Filter API + * @since 3.0 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -209,6 +211,8 @@ bool npf_remove_all_rules(struct npf_rule_list *rules); /** * @defgroup npf_basic_cond Basic Filter Conditions + * @since 3.0 + * @version 0.8.0 * @ingroup net_pkt_filter * @{ */ @@ -386,6 +390,8 @@ extern npf_test_fn_t npf_ip_src_addr_unmatch; /** * @defgroup npf_eth_cond Ethernet Filter Conditions * @ingroup net_pkt_filter + * @since 3.0 + * @version 0.8.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_stats.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_stats.h index 5a2ac84e..5b28d994 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_stats.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_stats.h @@ -18,6 +18,13 @@ #include #include +#include +#include +#include +#include +#include +#include + #ifdef __cplusplus extern "C" { #endif @@ -25,6 +32,8 @@ extern "C" { /** * @brief Network statistics library * @defgroup net_stats Network Statistics Library + * @since 1.5 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -196,6 +205,34 @@ struct net_stats_ipv6_nd { net_stats_t sent; }; +/** + * @brief IPv6 Path MTU Discovery statistics + */ +struct net_stats_ipv6_pmtu { + /** Number of dropped IPv6 PMTU packets. */ + net_stats_t drop; + + /** Number of received IPv6 PMTU packets. */ + net_stats_t recv; + + /** Number of sent IPv6 PMTU packets. */ + net_stats_t sent; +}; + +/** + * @brief IPv4 Path MTU Discovery statistics + */ +struct net_stats_ipv4_pmtu { + /** Number of dropped IPv4 PMTU packets. */ + net_stats_t drop; + + /** Number of received IPv4 PMTU packets. */ + net_stats_t recv; + + /** Number of sent IPv4 PMTU packets. */ + net_stats_t sent; +}; + /** * @brief IPv6 multicast listener daemon statistics */ @@ -224,6 +261,20 @@ struct net_stats_ipv4_igmp { net_stats_t drop; }; +/** + * @brief DNS statistics + */ +struct net_stats_dns { + /** Number of received DNS queries */ + net_stats_t recv; + + /** Number of sent DNS responses */ + net_stats_t sent; + + /** Number of dropped DNS packets */ + net_stats_t drop; +}; + /** * @brief Network packet transfer times for calculating average TX time */ @@ -363,6 +414,16 @@ struct net_stats { struct net_stats_ipv6_nd ipv6_nd; #endif +#if defined(CONFIG_NET_STATISTICS_IPV6_PMTU) + /** IPv6 Path MTU Discovery statistics */ + struct net_stats_ipv6_pmtu ipv6_pmtu; +#endif + +#if defined(CONFIG_NET_STATISTICS_IPV4_PMTU) + /** IPv4 Path MTU Discovery statistics */ + struct net_stats_ipv4_pmtu ipv4_pmtu; +#endif + #if defined(CONFIG_NET_STATISTICS_MLD) /** IPv6 MLD statistics */ struct net_stats_ipv6_mld ipv6_mld; @@ -373,6 +434,11 @@ struct net_stats { struct net_stats_ipv4_igmp ipv4_igmp; #endif +#if defined(CONFIG_NET_STATISTICS_DNS) + /** DNS statistics */ + struct net_stats_dns dns; +#endif + #if NET_TC_COUNT > 1 /** Traffic class statistics */ struct net_stats_tc tc; @@ -621,6 +687,9 @@ struct net_stats_wifi { /** Total number of unicast packets received and sent */ struct net_stats_pkts unicast; + + /** Total number of dropped packets at received and sent*/ + net_stats_t overrun_count; }; #if defined(CONFIG_NET_STATISTICS_USER_API) @@ -641,6 +710,8 @@ enum net_request_stats_cmd { NET_REQUEST_STATS_CMD_GET_IPV4, NET_REQUEST_STATS_CMD_GET_IPV6, NET_REQUEST_STATS_CMD_GET_IPV6_ND, + NET_REQUEST_STATS_CMD_GET_IPV6_PMTU, + NET_REQUEST_STATS_CMD_GET_IPV4_PMTU, NET_REQUEST_STATS_CMD_GET_ICMP, NET_REQUEST_STATS_CMD_GET_UDP, NET_REQUEST_STATS_CMD_GET_TCP, @@ -648,6 +719,7 @@ enum net_request_stats_cmd { NET_REQUEST_STATS_CMD_GET_PPP, NET_REQUEST_STATS_CMD_GET_PM, NET_REQUEST_STATS_CMD_GET_WIFI, + NET_REQUEST_STATS_CMD_RESET_WIFI, }; /** @endcond */ @@ -707,6 +779,26 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_IPV6_ND); /** @endcond */ #endif /* CONFIG_NET_STATISTICS_IPV6_ND */ +#if defined(CONFIG_NET_STATISTICS_IPV6_PMTU) +/** Request IPv6 Path MTU Discovery statistics */ +#define NET_REQUEST_STATS_GET_IPV6_PMTU \ + (_NET_STATS_BASE | NET_REQUEST_STATS_CMD_GET_IPV6_PMTU) + +/** @cond INTERNAL_HIDDEN */ +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_IPV6_PMTU); +/** @endcond */ +#endif /* CONFIG_NET_STATISTICS_IPV6_PMTU */ + +#if defined(CONFIG_NET_STATISTICS_IPV4_PMTU) +/** Request IPv4 Path MTU Discovery statistics */ +#define NET_REQUEST_STATS_GET_IPV4_PMTU \ + (_NET_STATS_BASE | NET_REQUEST_STATS_CMD_GET_IPV4_PMTU) + +/** @cond INTERNAL_HIDDEN */ +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_IPV4_PMTU); +/** @endcond */ +#endif /* CONFIG_NET_STATISTICS_IPV4_PMTU */ + #if defined(CONFIG_NET_STATISTICS_ICMP) /** Request ICMPv4 and ICMPv6 statistics */ #define NET_REQUEST_STATS_GET_ICMP \ @@ -777,8 +869,576 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_PM); /** @cond INTERNAL_HIDDEN */ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_WIFI); /** @endcond */ + +/** Reset Wi-Fi statistics*/ +#define NET_REQUEST_STATS_RESET_WIFI \ + (_NET_STATS_BASE | NET_REQUEST_STATS_CMD_RESET_WIFI) + +/** @cond INTERNAL_HIDDEN */ +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_RESET_WIFI); +/** @endcond */ #endif /* CONFIG_NET_STATISTICS_WIFI */ +#define NET_STATS_GET_METRIC_NAME(_name) _name +#define NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx) net_stats_##dev_id##_##sfx##_collector +#define NET_STATS_GET_VAR(dev_id, sfx, var) zephyr_net_##var +#define NET_STATS_GET_INSTANCE(dev_id, sfx, _not_used) STRINGIFY(_##dev_id##_##sfx) + +/* The label value is set to be the network interface name. Note that we skip + * the first character (_) when setting the label value. This can be changed + * if there is a way to token paste the instance name without the prefix character. + * Note also that the below macros have some parameters that are not used atm. + */ +#define NET_STATS_PROMETHEUS_COUNTER_DEFINE(_desc, _labelval, _not_used, \ + _collector, _name, _stat_var_ptr) \ + static PROMETHEUS_COUNTER_DEFINE( \ + NET_STATS_GET_METRIC_NAME(_name), \ + _desc, ({ .key = "nic", .value = &_labelval[1] }), \ + &(_collector), _stat_var_ptr) + +#define NET_STATS_PROMETHEUS_GAUGE_DEFINE(_desc, _labelval, _not_used, \ + _collector, _name, _stat_var_ptr) \ + static PROMETHEUS_GAUGE_DEFINE( \ + NET_STATS_GET_METRIC_NAME(_name), \ + _desc, ({ .key = "nic", .value = &_labelval[1] }), \ + &(_collector), _stat_var_ptr) + +#define NET_STATS_PROMETHEUS_SUMMARY_DEFINE(_desc, _labelval, _not_used, \ + _collector, _name, _stat_var_ptr) \ + static PROMETHEUS_SUMMARY_DEFINE( \ + NET_STATS_GET_METRIC_NAME(_name), \ + _desc, ({ .key = "nic", .value = &_labelval[1] }), \ + &(_collector), _stat_var_ptr) + +#define NET_STATS_PROMETHEUS_HISTOGRAM_DEFINE(_desc, _labelval, _not_used, \ + _collector, _name, _stat_var_ptr) \ + static PROMETHEUS_HISTOGRAM_DEFINE( \ + NET_STATS_GET_METRIC_NAME(_name), \ + _desc, ({ .key = "nic", .value = &_labelval[1] }), \ + &(_collector), _stat_var_ptr) + +/* IPv6 layer statistics */ +#if defined(CONFIG_NET_STATISTICS_IPV6) +#define NET_STATS_PROMETHEUS_IPV6(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_sent), \ + &(iface)->stats.ipv6.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_recv), \ + &(iface)->stats.ipv6.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_drop), \ + &(iface)->stats.ipv6.drop); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 packets forwarded", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_forward), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_forwarded), \ + &(iface)->stats.ipv6.forwarded) +#else +#define NET_STATS_PROMETHEUS_IPV6(iface, dev_id, sfx) +#endif + +/* IPv4 layer statistics */ +#if defined(CONFIG_NET_STATISTICS_IPV4) +#define NET_STATS_PROMETHEUS_IPV4(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_sent), \ + &(iface)->stats.ipv4.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_recv), \ + &(iface)->stats.ipv4.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_drop), \ + &(iface)->stats.ipv4.drop); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 packets forwarded", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_forwarded), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_forwarded), \ + &(iface)->stats.ipv4.forwarded) +#else +#define NET_STATS_PROMETHEUS_IPV4(iface, dev_id, sfx) +#endif + +/* ICMP layer statistics */ +#if defined(CONFIG_NET_STATISTICS_ICMP) +#define NET_STATS_PROMETHEUS_ICMP(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "ICMP packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, icmp_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, icmp_sent), \ + &(iface)->stats.icmp.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "ICMP packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, icmp_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, icmp_recv), \ + &(iface)->stats.icmp.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "ICMP packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, icmp_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, icmp_drop), \ + &(iface)->stats.icmp.drop); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "ICMP packets checksum error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, icmp_chkerr), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, icmp_chkerr), \ + &(iface)->stats.icmp.chkerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "ICMP packets type error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, icmp_typeerr), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, icmp_typeerr), \ + &(iface)->stats.icmp.typeerr) +#else +#define NET_STATS_PROMETHEUS_ICMP(iface, dev_id, sfx) +#endif + +/* UDP layer statistics */ +#if defined(CONFIG_NET_STATISTICS_UDP) +#define NET_STATS_PROMETHEUS_UDP(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "UDP packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, udp_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, udp_sent), \ + &(iface)->stats.udp.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "UDP packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, udp_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, udp_recv), \ + &(iface)->stats.udp.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "UDP packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, udp_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, udp_drop), \ + &(iface)->stats.udp.drop); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "UDP packets checksum error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, udp_chkerr), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, udp_chkerr), \ + &(iface)->stats.udp.chkerr) +#else +#define NET_STATS_PROMETHEUS_UDP(iface, dev_id, sfx) +#endif + +/* TCP layer statistics */ +#if defined(CONFIG_NET_STATISTICS_TCP) +#define NET_STATS_PROMETHEUS_TCP(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP bytes sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_bytes_sent), \ + "byte_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_bytes_sent), \ + &(iface)->stats.tcp.bytes.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP bytes received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_bytes_recv), \ + "byte_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_bytes_recv), \ + &(iface)->stats.tcp.bytes.received); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP bytes resent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_bytes_resent), \ + "byte_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_bytes_resent), \ + &(iface)->stats.tcp.resent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_sent), \ + &(iface)->stats.tcp.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_recv), \ + &(iface)->stats.tcp.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_drop), \ + &(iface)->stats.tcp.drop); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets checksum error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_chkerr), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_chkerr), \ + &(iface)->stats.tcp.chkerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets ack error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_ackerr), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_ackerr), \ + &(iface)->stats.tcp.ackerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets reset error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_rsterr), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_rsterr), \ + &(iface)->stats.tcp.rsterr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP packets retransmitted", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_rexmit), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_rexmit), \ + &(iface)->stats.tcp.rexmit); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP reset received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_rst_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_rst), \ + &(iface)->stats.tcp.rst); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP connection drop", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_conndrop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_conndrop), \ + &(iface)->stats.tcp.conndrop); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "TCP connection reset", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tcp_connrst), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tcp_connrst), \ + &(iface)->stats.tcp.connrst) +#else +#define NET_STATS_PROMETHEUS_TCP(iface, dev_id, sfx) +#endif + +/* IPv6 Neighbor Discovery statistics */ +#if defined(CONFIG_NET_STATISTICS_IPV6_ND) +#define NET_STATS_PROMETHEUS_IPV6_ND(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 ND packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_nd_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_nd_sent), \ + &(iface)->stats.ipv6_nd.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 ND packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_nd_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_nd_recv), \ + &(iface)->stats.ipv6_nd.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 ND packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_nd_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_nd_drop), \ + &(iface)->stats.ipv6_nd.drop) +#else +#define NET_STATS_PROMETHEUS_IPV6_ND(iface, dev_id, sfx) +#endif + +/* IPv6 Path MTU Discovery statistics */ +#if defined(CONFIG_NET_STATISTICS_IPV6_PMTU) +#define NET_STATS_PROMETHEUS_IPV6_PMTU(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 PMTU packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_pmtu_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_pmtu_sent), \ + &(iface)->stats.ipv6_pmtu.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 PMTU packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_pmtu_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_pmtu_recv), \ + &(iface)->stats.ipv6_pmtu.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 PMTU packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_pmtu_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_pmtu_drop), \ + &(iface)->stats.ipv6_pmtu.drop) +#else +#define NET_STATS_PROMETHEUS_IPV6_PMTU(iface, dev_id, sfx) +#endif + +/* IPv4 Path MTU Discovery statistics */ +#if defined(CONFIG_NET_STATISTICS_IPV4_PMTU) +#define NET_STATS_PROMETHEUS_IPV4_PMTU(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 PMTU packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_pmtu_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_pmtu_sent), \ + &(iface)->stats.ipv4_pmtu.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 PMTU packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_pmtu_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_pmtu_recv), \ + &(iface)->stats.ipv4_pmtu.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 PMTU packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_pmtu_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_pmtu_drop), \ + &(iface)->stats.ipv4_pmtu.drop) +#else +#define NET_STATS_PROMETHEUS_IPV4_PMTU(iface, dev_id, sfx) +#endif + +/* IPv6 Multicast Listener Discovery statistics */ +#if defined(CONFIG_NET_STATISTICS_MLD) +#define NET_STATS_PROMETHEUS_MLD(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 MLD packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_mld_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_mld_sent), \ + &(iface)->stats.ipv6_mld.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 MLD packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_mld_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_mld_recv), \ + &(iface)->stats.ipv6_mld.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv6 MLD packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv6_mld_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv6_mld_drop), \ + &(iface)->stats.ipv6_mld.drop) +#else +#define NET_STATS_PROMETHEUS_MLD(iface, dev_id, sfx) +#endif + +/* IPv4 IGMP statistics */ +#if defined(CONFIG_NET_STATISTICS_IGMP) +#define NET_STATS_PROMETHEUS_IGMP(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 IGMP packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_igmp_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_igmp_sent), \ + &(iface)->stats.ipv4_igmp.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 IGMP packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_igmp_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_igmp_recv), \ + &(iface)->stats.ipv4_igmp.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IPv4 IGMP packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ipv4_igmp_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ipv4_igmp_drop), \ + &(iface)->stats.ipv4_igmp.drop) +#else +#define NET_STATS_PROMETHEUS_IGMP(iface, dev_id, sfx) +#endif + +/* DNS statistics */ +#if defined(CONFIG_NET_STATISTICS_DNS) +#define NET_STATS_PROMETHEUS_DNS(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "DNS packets sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, dns_sent), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, dns_sent), \ + &(iface)->stats.dns.sent); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "DNS packets received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, dns_recv), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, dns_recv), \ + &(iface)->stats.dns.recv); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "DNS packets dropped", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, dns_drop), \ + "packet_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, dns_drop), \ + &(iface)->stats.dns.drop) +#else +#define NET_STATS_PROMETHEUS_DNS(iface, dev_id, sfx) +#endif + +/* TX time statistics */ +#if defined(CONFIG_NET_PKT_TXTIME_STATS) +#define NET_STATS_PROMETHEUS_TX_TIME(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_SUMMARY_DEFINE( \ + "TX time in microseconds", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, tx_time), \ + "time", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, tx_time), \ + &(iface)->stats.tx_time) +#else +#define NET_STATS_PROMETHEUS_TX_TIME(iface, dev_id, sfx) +#endif + +/* RX time statistics */ +#if defined(CONFIG_NET_PKT_RXTIME_STATS) +#define NET_STATS_PROMETHEUS_RX_TIME(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_SUMMARY_DEFINE( \ + "RX time in microseconds", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, rx_time), \ + "time", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, rx_time), \ + &(iface)->stats.rx_time) +#else +#define NET_STATS_PROMETHEUS_RX_TIME(iface, dev_id, sfx) +#endif + +/* Per network interface statistics via Prometheus */ +#define NET_STATS_PROMETHEUS(iface, dev_id, sfx) \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "Processing error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, process_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, processing_error), \ + &(iface)->stats.processing_error); \ + /* IP layer error statistics */ \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IP proto error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ip_proto_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ip_errors_protoerr), \ + &(iface)->stats.ip_errors.protoerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IP version/header len error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ip_vhl_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ip_errors_vhlerr), \ + &(iface)->stats.ip_errors.vhlerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IP header len error (high byte)", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ip_hblen_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ip_errors_hblenerr), \ + &(iface)->stats.ip_errors.hblenerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IP header len error (low byte)", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ip_lblen_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ip_errors_lblenerr), \ + &(iface)->stats.ip_errors.lblenerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IP fragment error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ip_frag_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ip_errors_fragerr), \ + &(iface)->stats.ip_errors.fragerr); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "IP checksum error", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, ip_chk_error), \ + "error_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, ip_errors_chkerr), \ + &(iface)->stats.ip_errors.chkerr); \ + /* General network statistics */ \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "Bytes received", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, bytes_recv), \ + "byte_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, bytes_recv), \ + &(iface)->stats.bytes.received); \ + NET_STATS_PROMETHEUS_COUNTER_DEFINE( \ + "Bytes sent", \ + NET_STATS_GET_INSTANCE(dev_id, sfx, bytes_sent), \ + "byte_count", \ + NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx), \ + NET_STATS_GET_VAR(dev_id, sfx, bytes_sent), \ + &(iface)->stats.bytes.sent); \ + NET_STATS_PROMETHEUS_IPV6(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_IPV4(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_ICMP(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_UDP(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_TCP(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_IPV6_ND(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_IPV6_PMTU(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_IPV4_PMTU(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_MLD(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_IGMP(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_DNS(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_TX_TIME(iface, dev_id, sfx); \ + NET_STATS_PROMETHEUS_RX_TIME(iface, dev_id, sfx) + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_time.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_time.h index 57a36517..def9ab01 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_time.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_time.h @@ -14,6 +14,8 @@ * https://github.com/torvalds/linux/blob/master/[tools/]include/linux/time64.h * * @defgroup net_time Network time representation. + * @since 3.5 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_timeout.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_timeout.h index 87d31264..5e4f89fb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_timeout.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/net_timeout.h @@ -17,6 +17,8 @@ /** * @brief Network long timeout primitives and helpers * @defgroup net_timeout Network long timeout primitives and helpers + * @since 1.14 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/offloaded_netdev.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/offloaded_netdev.h index 009a0666..fedfae74 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/offloaded_netdev.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/offloaded_netdev.h @@ -25,6 +25,8 @@ extern "C" { /** * @brief Offloaded Net Devices * @defgroup offloaded_netdev Offloaded Net Devices + * @since 3.4 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/openthread.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/openthread.h index 1e3619e5..0d83109e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/openthread.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/openthread.h @@ -14,6 +14,8 @@ /** * @brief OpenThread Layer 2 abstraction layer * @defgroup openthread OpenThread L2 abstraction layer + * @since 1.11 + * @version 0.8.0 * @ingroup ieee802154 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/phy.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/phy.h index 160b31df..0cffda13 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/phy.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/phy.h @@ -16,6 +16,8 @@ /** * @brief Ethernet PHY Interface * @defgroup ethernet_phy Ethernet PHY Interface + * @since 2.7 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -40,6 +42,10 @@ enum phy_link_speed { LINK_HALF_1000BASE_T = BIT(4), /** 1000Base-T Full-Duplex */ LINK_FULL_1000BASE_T = BIT(5), + /** 2.5GBase-T Full-Duplex */ + LINK_FULL_2500BASE_T = BIT(6), + /** 5GBase-T Full-Duplex */ + LINK_FULL_5000BASE_T = BIT(7), }; /** @@ -49,7 +55,7 @@ enum phy_link_speed { * * @return True if link is full duplex, false if not. */ -#define PHY_LINK_IS_FULL_DUPLEX(x) (x & (BIT(1) | BIT(3) | BIT(5))) +#define PHY_LINK_IS_FULL_DUPLEX(x) (x & (BIT(1) | BIT(3) | BIT(5) | BIT(6) | BIT(7))) /** * @brief Check if phy link speed is 1 Gbit/sec. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ppp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ppp.h index da31eca0..fc31f347 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ppp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ppp.h @@ -24,6 +24,8 @@ extern "C" { /** * @brief Point-to-point (PPP) L2/driver support functions * @defgroup ppp PPP L2/driver Support Functions + * @since 2.0 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/collector.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/collector.h new file mode 100644 index 00000000..08d93cf4 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/collector.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_COLLECTOR_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_COLLECTOR_H_ + +/** + * @file + * + * @brief Prometheus collector APIs. + * + * @defgroup prometheus Prometheus API + * @since 4.0 + * @version 0.1.0 + * @ingroup networking + * @{ + */ + +#include +#include +#include + +#include + +struct prometheus_collector; + +/** + * @typedef prometheus_scrape_cb_t + * @brief Callback used to scrape a collector for a specific metric. + * + * @param collector A valid pointer on the collector to scrape + * @param metric A valid pointer on the metric to scrape + * @param user_data A valid pointer to a user data or NULL + * + * @return 0 if successful, otherwise a negative error code. + */ +typedef int (*prometheus_scrape_cb_t)(struct prometheus_collector *collector, + struct prometheus_metric *metric, + void *user_data); + +/** + * @brief Prometheus collector definition + * + * This structure defines a Prometheus collector. + */ +struct prometheus_collector { + /** Name of the collector */ + const char *name; + /** Array of metrics associated with the collector */ + sys_slist_t metrics; + /** Mutex to protect the metrics list manipulation */ + struct k_mutex lock; + /** User callback function. If set, then the metric data is fetched + * via the function callback. + */ + prometheus_scrape_cb_t user_cb; + /** User data */ + void *user_data; +}; + +/** + * @brief Prometheus Collector definition. + * + * This macro defines a Collector. + * + * @param _name The collector's name. + * @param ... Optional user callback function. If set, this function is called + * when the collector is scraped. The function should be of type + * prometheus_scrape_cb_t. + * Optional user data to pass to the user callback function. + */ +#define PROMETHEUS_COLLECTOR_DEFINE(_name, ...) \ + STRUCT_SECTION_ITERABLE(prometheus_collector, _name) = { \ + .name = STRINGIFY(_name), \ + .metrics = SYS_SLIST_STATIC_INIT(&_name.metrics), \ + .lock = Z_MUTEX_INITIALIZER(_name.lock), \ + .user_cb = COND_CODE_0( \ + NUM_VA_ARGS_LESS_1( \ + LIST_DROP_EMPTY(__VA_ARGS__, _)), \ + (NULL), \ + (GET_ARG_N(1, __VA_ARGS__))), \ + .user_data = COND_CODE_0( \ + NUM_VA_ARGS_LESS_1(__VA_ARGS__), (NULL), \ + (GET_ARG_N(1, \ + GET_ARGS_LESS_N(1, __VA_ARGS__)))), \ + } + +/** + * @brief Register a metric with a Prometheus collector + * + * Registers the specified metric with the given collector. + * + * @param collector Pointer to the collector to register the metric with. + * @param metric Pointer to the metric to register. + * + * @return 0 if successful, otherwise a negative error code. + * @retval -EINVAL Invalid arguments. + * @retval -ENOMEM Not enough memory to register the metric. + */ +int prometheus_collector_register_metric(struct prometheus_collector *collector, + struct prometheus_metric *metric); + +/** + * @brief Get a metric from a Prometheus collector + * + * Retrieves the metric with the specified name from the given collector. + * + * @param collector Pointer to the collector to retrieve the metric from. + * @param name Name of the metric to retrieve. + * @return Pointer to the retrieved metric, or NULL if not found. + */ +const void *prometheus_collector_get_metric(struct prometheus_collector *collector, + const char *name); + +/** @cond INTERNAL_HIDDEN */ + +enum prometheus_walk_state { + PROMETHEUS_WALK_START, + PROMETHEUS_WALK_CONTINUE, + PROMETHEUS_WALK_STOP, +}; + +struct prometheus_collector_walk_context { + struct prometheus_collector *collector; + struct prometheus_metric *metric; + struct prometheus_metric *tmp; + enum prometheus_walk_state state; +}; + +/** @endcond */ + +/** + * @brief Walk through all metrics in a Prometheus collector and format them + * into a buffer. + * + * @param ctx Pointer to the walker context. + * @param buffer Pointer to the buffer to store the formatted metrics. + * @param buffer_size Size of the buffer. + * @return 0 if successful and we went through all metrics, -EAGAIN if we + * need to call this function again, any other negative error code + * means an error occurred. + */ +int prometheus_collector_walk_metrics(struct prometheus_collector_walk_context *ctx, + uint8_t *buffer, size_t buffer_size); + +/** + * @brief Initialize the walker context to walk through all metrics. + * + * @param ctx Pointer to the walker context. + * @param collector Pointer to the collector to walk through. + * + * @return 0 if successful, otherwise a negative error code. + */ +static inline int prometheus_collector_walk_init(struct prometheus_collector_walk_context *ctx, + struct prometheus_collector *collector) +{ + if (collector == NULL) { + return -EINVAL; + } + + ctx->collector = collector; + ctx->state = PROMETHEUS_WALK_START; + ctx->metric = NULL; + ctx->tmp = NULL; + + return 0; +} + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_COLLECTOR_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/counter.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/counter.h new file mode 100644 index 00000000..591e7ec2 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/counter.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_COUNTER_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_COUNTER_H_ + +/** + * @file + * + * @brief Prometheus counter APIs. + * + * @addtogroup prometheus + * @{ + */ + +#include + +#include +#include + +/** + * @brief Type used to represent a Prometheus counter metric. + * + * * References + * * See https://prometheus.io/docs/concepts/metric_types/#counter + */ +struct prometheus_counter { + /** Base of the Prometheus counter metric */ + struct prometheus_metric base; + /** Value of the Prometheus counter metric */ + uint64_t value; + /** User data */ + void *user_data; +}; + +/** + * @brief Prometheus Counter definition. + * + * This macro defines a Counter metric. If you want to make the counter static, + * then add "static" keyword before the PROMETHEUS_COUNTER_DEFINE. + * + * @param _name The counter metric name + * @param _desc Counter description + * @param _label Label for the metric. Additional labels can be added at runtime. + * @param _collector Collector to map this metric. Can be set to NULL if it not yet known. + * @param ... Optional user data specific to this metric instance. + * + * Example usage: + * @code{.c} + * + * PROMETHEUS_COUNTER_DEFINE(http_request_counter, "HTTP request counter", + * ({ .key = "http_request", .value = "request_count" }), + * NULL); + * @endcode + */ +#define PROMETHEUS_COUNTER_DEFINE(_name, _desc, _label, _collector, ...) \ + STRUCT_SECTION_ITERABLE(prometheus_counter, _name) = { \ + .base.name = STRINGIFY(_name), \ + .base.type = PROMETHEUS_COUNTER, \ + .base.description = _desc, \ + .base.labels[0] = __DEBRACKET _label, \ + .base.num_labels = 1, \ + .base.collector = _collector, \ + .value = 0ULL, \ + .user_data = COND_CODE_0( \ + NUM_VA_ARGS_LESS_1(LIST_DROP_EMPTY(__VA_ARGS__, _)), \ + (NULL), \ + (GET_ARG_N(1, __VA_ARGS__))), \ + } + +/** + * @brief Increment the value of a Prometheus counter metric + * Increments the value of the specified counter metric by arbitrary amount. + * @param counter Pointer to the counter metric to increment. + * @param value Amount to increment the counter by. + * @return 0 on success, negative errno on error. + */ +int prometheus_counter_add(struct prometheus_counter *counter, uint64_t value); + +/** + * @brief Increment the value of a Prometheus counter metric + * Increments the value of the specified counter metric by one. + * @param counter Pointer to the counter metric to increment. + * @return 0 on success, negative errno on error. + */ +static inline int prometheus_counter_inc(struct prometheus_counter *counter) +{ + return prometheus_counter_add(counter, 1ULL); +} + +/** + * @brief Set the counter value to specific value. + * The new value must be higher than the current value. This function can be used + * if we cannot add individual increments to the counter but need to periodically + * update the counter value. This function will add the difference between the + * new value and the old value to the counter. + * @param counter Pointer to the counter metric to increment. + * @param value New value of the counter. + * @return 0 on success, negative errno on error. + */ +int prometheus_counter_set(struct prometheus_counter *counter, uint64_t value); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_COUNTER_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/formatter.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/formatter.h new file mode 100644 index 00000000..393fe4c6 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/formatter.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_FORMATTER_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_FORMATTER_H_ + +/** + * @file + * + * @brief Prometheus formatter APIs. + * + * @addtogroup prometheus + * @{ + */ + +#include + +/** + * @brief Format exposition data for Prometheus + * + * Formats the exposition data collected by the specified collector into the provided buffer. + * Function will format metric data according to Prometheus text-based format + * + * @param collector Pointer to the collector containing the data to format. + * @param buffer Pointer to the buffer where the formatted exposition data will be stored. + * @param buffer_size Size of the buffer. + * + * @return 0 on success, negative errno on error. + */ +int prometheus_format_exposition(struct prometheus_collector *collector, char *buffer, + size_t buffer_size); + +/** + * @brief Format exposition data for one metric for Prometheus + * + * Formats the exposition data of one specific metric into the provided buffer. + * Function will format metric data according to Prometheus text-based format. + * + * @param metric Pointer to the metric containing the data to format. + * @param buffer Pointer to the buffer where the formatted exposition data will be stored. + * @param buffer_size Size of the buffer. + * @param written How many bytes have been written to the buffer. + * + * @return 0 on success, negative errno on error. + */ +int prometheus_format_one_metric(struct prometheus_metric *metric, char *buffer, + size_t buffer_size, int *written); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_FORMATTER_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/gauge.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/gauge.h new file mode 100644 index 00000000..0703e381 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/gauge.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_GAUGE_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_GAUGE_H_ + +/** + * @file + * + * @brief Prometheus gauge APIs. + * + * @addtogroup prometheus + * @{ + */ + +#include +#include + +/** + * @brief Type used to represent a Prometheus gauge metric. + * + * * References + * * See https://prometheus.io/docs/concepts/metric_types/#gauge + */ +struct prometheus_gauge { + /** Base of the Prometheus gauge metric */ + struct prometheus_metric base; + /** Value of the Prometheus gauge metric */ + double value; + /** User data */ + void *user_data; +}; + +/** + * @brief Prometheus Gauge definition. + * + * This macro defines a Gauge metric. If you want to make the gauge static, + * then add "static" keyword before the PROMETHEUS_GAUGE_DEFINE. + * + * @param _name The gauge metric name. + * @param _desc Gauge description + * @param _label Label for the metric. Additional labels can be added at runtime. + * @param _collector Collector to map this metric. Can be set to NULL if it not yet known. + * @param ... Optional user data specific to this metric instance. + * + * Example usage: + * @code{.c} + * + * PROMETHEUS_GAUGE_DEFINE(http_request_gauge, "HTTP request gauge", + * ({ .key = "http_request", .value = "request_count" }), + * NULL); + * + * @endcode + */ +#define PROMETHEUS_GAUGE_DEFINE(_name, _desc, _label, _collector, ...) \ + STRUCT_SECTION_ITERABLE(prometheus_gauge, _name) = { \ + .base.name = STRINGIFY(_name), \ + .base.type = PROMETHEUS_GAUGE, \ + .base.description = _desc, \ + .base.labels[0] = __DEBRACKET _label, \ + .base.num_labels = 1, \ + .base.collector = _collector, \ + .value = 0.0, \ + .user_data = COND_CODE_0( \ + NUM_VA_ARGS_LESS_1(LIST_DROP_EMPTY(__VA_ARGS__, _)), \ + (NULL), \ + (GET_ARG_N(1, __VA_ARGS__))), \ + } + +/** + * @brief Set the value of a Prometheus gauge metric + * + * Sets the value of the specified gauge metric to the given value. + * + * @param gauge Pointer to the gauge metric to set. + * @param value Value to set the gauge metric to. + * + * @return 0 on success, -EINVAL if the value is negative. + */ +int prometheus_gauge_set(struct prometheus_gauge *gauge, double value); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_GAUGE_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/histogram.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/histogram.h new file mode 100644 index 00000000..dbf5538f --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/histogram.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_HISTOGRAM_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_HISTOGRAM_H_ + +/** + * @file + * + * @brief Prometheus histogram APIs. + * + * @addtogroup prometheus + * @{ + */ + +#include +#include + +#include + +/** + * @brief Prometheus histogram bucket definition. + * + * This structure defines a Prometheus histogram bucket. + */ +struct prometheus_histogram_bucket { + /** Upper bound value of bucket */ + double upper_bound; + /** Cumulative count of observations in the bucket */ + unsigned long count; +}; + +/** + * @brief Type used to represent a Prometheus histogram metric. + * + * * References + * * See https://prometheus.io/docs/concepts/metric_types/#histogram + */ +struct prometheus_histogram { + /** Base of the Prometheus histogram metric */ + struct prometheus_metric base; + /** Array of buckets in the histogram */ + struct prometheus_histogram_bucket *buckets; + /** Number of buckets in the histogram */ + size_t num_buckets; + /** Sum of all observed values in the histogram */ + double sum; + /** Total count of observations in the histogram */ + unsigned long count; + /** User data */ + void *user_data; +}; + +/** + * @brief Prometheus Histogram definition. + * + * This macro defines a Histogram metric. If you want to make the histogram static, + * then add "static" keyword before the PROMETHEUS_HISTOGRAM_DEFINE. + * + * @param _name The histogram metric name. + * @param _desc Histogram description + * @param _label Label for the metric. Additional labels can be added at runtime. + * @param _collector Collector to map this metric. Can be set to NULL if it not yet known. + * @param ... Optional user data specific to this metric instance. + * + * Example usage: + * @code{.c} + * + * PROMETHEUS_HISTOGRAM_DEFINE(http_request_histogram, "HTTP request histogram", + * ({ .key = "request_latency", .value = "request_latency_seconds" }), + * NULL); + * + * @endcode + */ +#define PROMETHEUS_HISTOGRAM_DEFINE(_name, _desc, _label, _collector, ...) \ + STRUCT_SECTION_ITERABLE(prometheus_histogram, _name) = { \ + .base.name = STRINGIFY(_name), \ + .base.type = PROMETHEUS_HISTOGRAM, \ + .base.description = _desc, \ + .base.labels[0] = __DEBRACKET _label, \ + .base.num_labels = 1, \ + .base.collector = _collector, \ + .buckets = NULL, \ + .num_buckets = 0, \ + .sum = 0.0, \ + .count = 0U, \ + .user_data = COND_CODE_0( \ + NUM_VA_ARGS_LESS_1(LIST_DROP_EMPTY(__VA_ARGS__, _)), \ + (NULL), \ + (GET_ARG_N(1, __VA_ARGS__))), \ + } + +/** + * @brief Observe a value in a Prometheus histogram metric + * + * Observes the specified value in the given histogram metric. + * + * @param histogram Pointer to the histogram metric to observe. + * @param value Value to observe in the histogram metric. + * @return 0 on success, -EINVAL if the value is negative. + */ +int prometheus_histogram_observe(struct prometheus_histogram *histogram, double value); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_HISTOGRAM_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/label.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/label.h new file mode 100644 index 00000000..7d348d43 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/label.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_LABEL_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_LABEL_H_ + +/** + * @file + * + * @brief Prometheus label interface. + * + * @addtogroup prometheus + * @{ + */ + +#if defined(CONFIG_PROMETHEUS) +/** Maximum number of labels per metric */ +#define MAX_PROMETHEUS_LABELS_PER_METRIC CONFIG_PROMETHEUS_LABEL_MAX_COUNT +#else +#define MAX_PROMETHEUS_LABELS_PER_METRIC 1 +#endif /* CONFIG_PROMETHEUS */ + +/** + * @brief Prometheus label definition. + * + * This structure defines a Prometheus label. + */ +struct prometheus_label { + /** Prometheus metric label key */ + const char *key; + /** Prometheus metric label value */ + const char *value; +}; + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_LABEL_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/metric.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/metric.h new file mode 100644 index 00000000..bbe3a0e3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/metric.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_METRIC_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_METRIC_H_ + +/** + * @file + * + * @brief Prometheus metric interface. + * + * @addtogroup prometheus + * @{ + */ + +#include +#include +#include + +/** + * @brief Prometheus metric types. + * + * * References + * * See https://prometheus.io/docs/concepts/metric_types + */ +enum prometheus_metric_type { + /** Prometheus Counter */ + PROMETHEUS_COUNTER = 0, + /** Prometheus Gauge */ + PROMETHEUS_GAUGE, + /** Prometheus Summary */ + PROMETHEUS_SUMMARY, + /** Prometheus Histogram */ + PROMETHEUS_HISTOGRAM, +}; + +/** + * @brief Type used to represent a Prometheus metric base. + * + * Every metric has a prometheus_metric structure associated used + * to control the metric access and usage. + */ +struct prometheus_metric { + /** Slist metric list node */ + sys_snode_t node; + /** Back pointer to the collector that this metric belongs to */ + struct prometheus_collector *collector; + /** Back pointer to the actual metric (counter, gauge, etc.). + * This is just a temporary solution, ultimate goal is to place + * this generic metrict struct into the actual metric struct. + */ + void *metric; + /** Type of the Prometheus metric. */ + enum prometheus_metric_type type; + /** Name of the Prometheus metric. */ + const char *name; + /** Description of the Prometheus metric. */ + const char *description; + /** Labels associated with the Prometheus metric. */ + struct prometheus_label labels[MAX_PROMETHEUS_LABELS_PER_METRIC]; + /** Number of labels associated with the Prometheus metric. */ + int num_labels; + /** User defined data */ + void *user_data; + /* Add any other necessary fields */ +}; + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_METRIC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/summary.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/summary.h new file mode 100644 index 00000000..d36b34c6 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/prometheus/summary.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2024 Mustafa Abdullah Kus, Sparse Technology + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_PROMETHEUS_SUMMARY_H_ +#define ZEPHYR_INCLUDE_PROMETHEUS_SUMMARY_H_ + +/** + * @file + * + * @brief Prometheus summary APIs. + * + * @addtogroup prometheus + * @{ + */ + +#include +#include + +#include + +/** + * @brief Prometheus summary quantile definition. + * + * This structure defines a Prometheus summary quantile. + */ +struct prometheus_summary_quantile { + /** Quantile of the summary */ + double quantile; + /** Value of the quantile */ + double value; + /** User data */ + void *user_data; +}; + +/** + * @brief Type used to represent a Prometheus summary metric. + * + * * References + * * See https://prometheus.io/docs/concepts/metric_types/#summary + */ +struct prometheus_summary { + /** Base of the Prometheus summary metric */ + struct prometheus_metric base; + /** Array of quantiles associated with the Prometheus summary metric */ + struct prometheus_summary_quantile *quantiles; + /** Number of quantiles associated with the Prometheus summary metric */ + size_t num_quantiles; + /** Sum of all observed values in the summary metric */ + double sum; + /** Total count of observations in the summary metric */ + unsigned long count; + /** User data */ + void *user_data; +}; + +/** + * @brief Prometheus Summary definition. + * + * This macro defines a Summary metric. If you want to make the summary static, + * then add "static" keyword before the PROMETHEUS_SUMMARY_DEFINE. + * + * @param _name The summary metric name. + * @param _desc Summary description + * @param _label Label for the metric. Additional labels can be added at runtime. + * @param _collector Collector to map this metric. Can be set to NULL if it not yet known. + * @param ... Optional user data specific to this metric instance. + * + * + * Example usage: + * @code{.c} + * + * PROMETHEUS_SUMMARY_DEFINE(http_request_summary, "HTTP request summary", + * ({ .key = "request_latency", + * .value = "request_latency_seconds" }), NULL); + * + * @endcode + */ + +#define PROMETHEUS_SUMMARY_DEFINE(_name, _desc, _label, _collector, ...) \ + STRUCT_SECTION_ITERABLE(prometheus_summary, _name) = { \ + .base.name = STRINGIFY(_name), \ + .base.type = PROMETHEUS_SUMMARY, \ + .base.description = _desc, \ + .base.labels[0] = __DEBRACKET _label, \ + .base.num_labels = 1, \ + .base.collector = _collector, \ + .quantiles = NULL, \ + .num_quantiles = 0, \ + .sum = 0.0, \ + .count = 0U, \ + .user_data = COND_CODE_0( \ + NUM_VA_ARGS_LESS_1(LIST_DROP_EMPTY(__VA_ARGS__, _)), \ + (NULL), \ + (GET_ARG_N(1, __VA_ARGS__))), \ + } + +/** + * @brief Observes a value in a Prometheus summary metric + * + * Observes the specified value in the given summary metric. + * + * @param summary Pointer to the summary metric to observe. + * @param value Value to observe in the summary metric. + * @return 0 on success, -EINVAL if the value is negative. + */ +int prometheus_summary_observe(struct prometheus_summary *summary, double value); + +/** + * @brief Set the summary value to specific value. + * The new value must be higher than the current value. This function can be used + * if we cannot add individual increments to the summary but need to periodically + * update the counter value. This function will add the difference between the + * new value and the old value to the summary fields. + * @param summary Pointer to the summary metric to increment. + * @param value New value of the summary. + * @param count New counter value of the summary. + * @return 0 on success, negative errno on error. + */ +int prometheus_summary_observe_set(struct prometheus_summary *summary, + double value, unsigned long count); + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_PROMETHEUS_SUMMARY_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/promiscuous.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/promiscuous.h index 30d47b2c..431715c5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/promiscuous.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/promiscuous.h @@ -17,6 +17,8 @@ /** * @brief Promiscuous mode support. * @defgroup promiscuous Promiscuous mode + * @since 1.13 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp.h index d57c47e7..f61f32d9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp.h @@ -17,6 +17,8 @@ /** * @brief Precision Time Protocol (PTP) support * @defgroup ptp PTP support + * @since 3.7 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp_time.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp_time.h index 269325cd..f2e5409d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp_time.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/ptp_time.h @@ -18,6 +18,8 @@ /** * @brief Precision Time Protocol time specification * @defgroup ptp_time PTP time + * @since 1.13 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/sntp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/sntp.h index 68a733d3..66128f76 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/sntp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/sntp.h @@ -22,6 +22,8 @@ extern "C" { /** * @brief Simple Network Time Protocol API * @defgroup sntp SNTP + * @since 1.10 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -71,13 +73,24 @@ int sntp_init(struct sntp_ctx *ctx, struct sockaddr *addr, * * @param ctx Address of sntp context. * @param timeout Timeout of waiting for sntp response (in milliseconds). - * @param time Timestamp including integer and fractional seconds since + * @param ts Timestamp including integer and fractional seconds since + * 1 Jan 1970 (output). + * + * @return 0 if ok, <0 if error (-ETIMEDOUT if timeout). + */ +int sntp_query(struct sntp_ctx *ctx, uint32_t timeout, struct sntp_time *ts); + +/** + * @brief Attempt to receive an SNTP response after issuing a query + * + * @param ctx Address of sntp context. + * @param timeout Timeout of waiting for sntp response (in milliseconds). + * @param ts Timestamp including integer and fractional seconds since * 1 Jan 1970 (output). * * @return 0 if ok, <0 if error (-ETIMEDOUT if timeout). */ -int sntp_query(struct sntp_ctx *ctx, uint32_t timeout, - struct sntp_time *time); +int sntp_recv_response(struct sntp_ctx *ctx, uint32_t timeout, struct sntp_time *ts); /** * @brief Release SNTP context diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket.h index 62f1387e..58c3fb03 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket.h @@ -18,6 +18,8 @@ /** * @brief BSD Sockets compatible API * @defgroup bsd_sockets BSD Sockets compatible API + * @since 1.9 + * @version 1.0.0 * @ingroup networking * @{ */ @@ -93,8 +95,10 @@ extern "C" { /** @} */ /** - * @defgroup secure_sockets_options Socket options for TLS - * @{ + * @defgroup secure_sockets_options Socket options for TLS + * @since 1.13 + * @version 0.8.0 + * @{ */ /** * @name Socket options for TLS @@ -328,13 +332,11 @@ __syscall void *zsock_get_context_object(int sock); * @brief Create a network socket * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/socket.html * for normative description. - * This function is also exposed as ``socket()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `socket()` + * if @kconfig{CONFIG_POSIX_API} is defined. * * If CONFIG_USERSPACE is enabled, the caller will be granted access to the * context object associated with the returned file descriptor. @@ -347,13 +349,11 @@ __syscall int zsock_socket(int family, int type, int proto); * @brief Create an unnamed pair of connected sockets * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * https://pubs.opengroup.org/onlinepubs/009695399/functions/socketpair.html * for normative description. - * This function is also exposed as ``socketpair()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `socketpair()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_socketpair(int family, int type, int proto, int *sv); @@ -361,12 +361,10 @@ __syscall int zsock_socketpair(int family, int type, int proto, int *sv); * @brief Close a network socket * * @details - * @rst * Close a network socket. - * This function is also exposed as ``close()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case it - * may conflict with generic POSIX ``close()`` function). - * @endrst + * This function is also exposed as `close()` + * if @kconfig{CONFIG_POSIX_API} is defined (in which case it + * may conflict with generic POSIX `close()` function). */ __syscall int zsock_close(int sock); @@ -374,14 +372,12 @@ __syscall int zsock_close(int sock); * @brief Shutdown socket send/receive operations * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/shutdown.html * for normative description, but currently this function has no effect in * Zephyr and provided solely for compatibility with existing code. - * This function is also exposed as ``shutdown()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `shutdown()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_shutdown(int sock, int how); @@ -389,13 +385,11 @@ __syscall int zsock_shutdown(int sock, int how); * @brief Bind a socket to a local network address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/bind.html * for normative description. - * This function is also exposed as ``bind()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `bind()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_bind(int sock, const struct sockaddr *addr, socklen_t addrlen); @@ -404,13 +398,11 @@ __syscall int zsock_bind(int sock, const struct sockaddr *addr, * @brief Connect a socket to a peer network address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/connect.html * for normative description. - * This function is also exposed as ``connect()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `connect()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_connect(int sock, const struct sockaddr *addr, socklen_t addrlen); @@ -419,13 +411,11 @@ __syscall int zsock_connect(int sock, const struct sockaddr *addr, * @brief Set up a STREAM socket to accept peer connections * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/listen.html * for normative description. - * This function is also exposed as ``listen()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `listen()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_listen(int sock, int backlog); @@ -433,13 +423,11 @@ __syscall int zsock_listen(int sock, int backlog); * @brief Accept a connection on listening socket * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/accept.html * for normative description. - * This function is also exposed as ``accept()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `accept()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_accept(int sock, struct sockaddr *addr, socklen_t *addrlen); @@ -447,13 +435,11 @@ __syscall int zsock_accept(int sock, struct sockaddr *addr, socklen_t *addrlen); * @brief Send data to an arbitrary network address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/sendto.html * for normative description. - * This function is also exposed as ``sendto()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `sendto()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall ssize_t zsock_sendto(int sock, const void *buf, size_t len, int flags, const struct sockaddr *dest_addr, @@ -463,13 +449,11 @@ __syscall ssize_t zsock_sendto(int sock, const void *buf, size_t len, * @brief Send data to a connected peer * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/send.html * for normative description. - * This function is also exposed as ``send()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `send()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ static inline ssize_t zsock_send(int sock, const void *buf, size_t len, int flags) @@ -481,13 +465,11 @@ static inline ssize_t zsock_send(int sock, const void *buf, size_t len, * @brief Send data to an arbitrary network address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/sendmsg.html * for normative description. - * This function is also exposed as ``sendmsg()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `sendmsg()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall ssize_t zsock_sendmsg(int sock, const struct msghdr *msg, int flags); @@ -496,13 +478,11 @@ __syscall ssize_t zsock_sendmsg(int sock, const struct msghdr *msg, * @brief Receive data from an arbitrary network address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/recvfrom.html * for normative description. - * This function is also exposed as ``recvfrom()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `recvfrom()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall ssize_t zsock_recvfrom(int sock, void *buf, size_t max_len, int flags, struct sockaddr *src_addr, @@ -512,13 +492,11 @@ __syscall ssize_t zsock_recvfrom(int sock, void *buf, size_t max_len, * @brief Receive a message from an arbitrary network address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/recvmsg.html * for normative description. - * This function is also exposed as ``recvmsg()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `recvmsg()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall ssize_t zsock_recvmsg(int sock, struct msghdr *msg, int flags); @@ -526,13 +504,11 @@ __syscall ssize_t zsock_recvmsg(int sock, struct msghdr *msg, int flags); * @brief Receive data from a connected peer * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/recv.html * for normative description. - * This function is also exposed as ``recv()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `recv()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ static inline ssize_t zsock_recv(int sock, void *buf, size_t max_len, int flags) @@ -544,13 +520,11 @@ static inline ssize_t zsock_recv(int sock, void *buf, size_t max_len, * @brief Control blocking/non-blocking mode of a socket * * @details - * @rst * This functions allow to (only) configure a socket for blocking or * non-blocking operation (O_NONBLOCK). - * This function is also exposed as ``fcntl()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case - * it may conflict with generic POSIX ``fcntl()`` function). - * @endrst + * This function is also exposed as `fcntl()` + * if @kconfig{CONFIG_POSIX_API} is defined (in which case + * it may conflict with generic POSIX `fcntl()` function). */ __syscall int zsock_fcntl_impl(int sock, int cmd, int flags); @@ -579,18 +553,16 @@ static inline int zsock_fcntl_wrapper(int sock, int cmd, ...) * @brief Control underlying socket parameters * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * https://pubs.opengroup.org/onlinepubs/9699919799/functions/ioctl.html * for normative description. * This function enables querying or manipulating underlying socket parameters. - * Currently supported @p request values include ``ZFD_IOCTL_FIONBIO``, and - * ``ZFD_IOCTL_FIONREAD``, to set non-blocking mode, and query the number of + * Currently supported @p request values include `ZFD_IOCTL_FIONBIO`, and + * `ZFD_IOCTL_FIONREAD`, to set non-blocking mode, and query the number of * bytes available to read, respectively. - * This function is also exposed as ``ioctl()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case - * it may conflict with generic POSIX ``ioctl()`` function). - * @endrst + * This function is also exposed as `ioctl()` + * if @kconfig{CONFIG_POSIX_API} is defined (in which case + * it may conflict with generic POSIX `ioctl()` function). */ __syscall int zsock_ioctl_impl(int sock, unsigned long request, va_list ap); @@ -616,31 +588,30 @@ static inline int zsock_ioctl_wrapper(int sock, unsigned long request, ...) * @brief Efficiently poll multiple sockets for events * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/poll.html * for normative description. - * This function is also exposed as ``poll()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case - * it may conflict with generic POSIX ``poll()`` function). - * @endrst + * This function is also exposed as `poll()` + * if @kconfig{CONFIG_POSIX_API} is defined (in which case + * it may conflict with generic POSIX `poll()` function). */ -__syscall int zsock_poll(struct zsock_pollfd *fds, int nfds, int timeout); +static inline int zsock_poll(struct zsock_pollfd *fds, int nfds, int timeout) +{ + return zvfs_poll(fds, nfds, timeout); +} /** * @brief Get various socket options * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/getsockopt.html * for normative description. In Zephyr this function supports a subset of * socket options described by POSIX, but also some additional options * available in Linux (some options are dummy and provided to ease porting * of existing code). - * This function is also exposed as ``getsockopt()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `getsockopt()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_getsockopt(int sock, int level, int optname, void *optval, socklen_t *optlen); @@ -649,16 +620,14 @@ __syscall int zsock_getsockopt(int sock, int level, int optname, * @brief Set various socket options * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/setsockopt.html * for normative description. In Zephyr this function supports a subset of * socket options described by POSIX, but also some additional options * available in Linux (some options are dummy and provided to ease porting * of existing code). - * This function is also exposed as ``setsockopt()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `setsockopt()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_setsockopt(int sock, int level, int optname, const void *optval, socklen_t optlen); @@ -667,13 +636,11 @@ __syscall int zsock_setsockopt(int sock, int level, int optname, * @brief Get peer name * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/getpeername.html * for normative description. - * This function is also exposed as ``getpeername()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `getpeername()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_getpeername(int sock, struct sockaddr *addr, socklen_t *addrlen); @@ -682,13 +649,11 @@ __syscall int zsock_getpeername(int sock, struct sockaddr *addr, * @brief Get socket name * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/getsockname.html * for normative description. - * This function is also exposed as ``getsockname()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `getsockname()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_getsockname(int sock, struct sockaddr *addr, socklen_t *addrlen); @@ -697,13 +662,11 @@ __syscall int zsock_getsockname(int sock, struct sockaddr *addr, * @brief Get local host name * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/gethostname.html * for normative description. - * This function is also exposed as ``gethostname()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `gethostname()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_gethostname(char *buf, size_t len); @@ -711,13 +674,11 @@ __syscall int zsock_gethostname(char *buf, size_t len); * @brief Convert network address from internal to numeric ASCII form * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/inet_ntop.html * for normative description. - * This function is also exposed as ``inet_ntop()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `inet_ntop()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ static inline char *zsock_inet_ntop(sa_family_t family, const void *src, char *dst, size_t size) @@ -729,13 +690,11 @@ static inline char *zsock_inet_ntop(sa_family_t family, const void *src, * @brief Convert network address from numeric ASCII form to internal representation * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/inet_pton.html * for normative description. - * This function is also exposed as ``inet_pton()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `inet_pton()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ __syscall int zsock_inet_pton(sa_family_t family, const char *src, void *dst); @@ -774,13 +733,11 @@ __syscall int z_zsock_getaddrinfo_internal(const char *host, * @brief Resolve a domain name to one or more network addresses * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/getaddrinfo.html * for normative description. - * This function is also exposed as ``getaddrinfo()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `getaddrinfo()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ int zsock_getaddrinfo(const char *host, const char *service, const struct zsock_addrinfo *hints, @@ -790,13 +747,11 @@ int zsock_getaddrinfo(const char *host, const char *service, * @brief Free results returned by zsock_getaddrinfo() * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/freeaddrinfo.html * for normative description. - * This function is also exposed as ``freeaddrinfo()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `freeaddrinfo()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ void zsock_freeaddrinfo(struct zsock_addrinfo *ai); @@ -804,13 +759,11 @@ void zsock_freeaddrinfo(struct zsock_addrinfo *ai); * @brief Convert zsock_getaddrinfo() error code to textual message * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/gai_strerror.html * for normative description. - * This function is also exposed as ``gai_strerror()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `gai_strerror()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ const char *zsock_gai_strerror(int errcode); @@ -841,254 +794,16 @@ const char *zsock_gai_strerror(int errcode); * @brief Resolve a network address to a domain name or ASCII address * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/getnameinfo.html * for normative description. - * This function is also exposed as ``getnameinfo()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `getnameinfo()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ int zsock_getnameinfo(const struct sockaddr *addr, socklen_t addrlen, char *host, socklen_t hostlen, char *serv, socklen_t servlen, int flags); -#if defined(CONFIG_NET_SOCKETS_POSIX_NAMES) - -/** - * @name Socket APIs available if CONFIG_NET_SOCKETS_POSIX_NAMES is enabled - * @{ - */ - -/** POSIX wrapper for @ref zsock_pollfd */ -#define pollfd zsock_pollfd - -/** POSIX wrapper for @ref zsock_socket */ -static inline int socket(int family, int type, int proto) -{ - return zsock_socket(family, type, proto); -} - -/** POSIX wrapper for @ref zsock_socketpair */ -static inline int socketpair(int family, int type, int proto, int sv[2]) -{ - return zsock_socketpair(family, type, proto, sv); -} - -/** POSIX wrapper for @ref zsock_close */ -static inline int close(int sock) -{ - return zsock_close(sock); -} - -/** POSIX wrapper for @ref zsock_shutdown */ -static inline int shutdown(int sock, int how) -{ - return zsock_shutdown(sock, how); -} - -/** POSIX wrapper for @ref zsock_bind */ -static inline int bind(int sock, const struct sockaddr *addr, socklen_t addrlen) -{ - return zsock_bind(sock, addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_connect */ -static inline int connect(int sock, const struct sockaddr *addr, - socklen_t addrlen) -{ - return zsock_connect(sock, addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_listen */ -static inline int listen(int sock, int backlog) -{ - return zsock_listen(sock, backlog); -} - -/** POSIX wrapper for @ref zsock_accept */ -static inline int accept(int sock, struct sockaddr *addr, socklen_t *addrlen) -{ - return zsock_accept(sock, addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_send */ -static inline ssize_t send(int sock, const void *buf, size_t len, int flags) -{ - return zsock_send(sock, buf, len, flags); -} - -/** POSIX wrapper for @ref zsock_recv */ -static inline ssize_t recv(int sock, void *buf, size_t max_len, int flags) -{ - return zsock_recv(sock, buf, max_len, flags); -} - -/** POSIX wrapper for @ref zsock_sendto */ -static inline ssize_t sendto(int sock, const void *buf, size_t len, int flags, - const struct sockaddr *dest_addr, - socklen_t addrlen) -{ - return zsock_sendto(sock, buf, len, flags, dest_addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_sendmsg */ -static inline ssize_t sendmsg(int sock, const struct msghdr *message, - int flags) -{ - return zsock_sendmsg(sock, message, flags); -} - -/** POSIX wrapper for @ref zsock_recvfrom */ -static inline ssize_t recvfrom(int sock, void *buf, size_t max_len, int flags, - struct sockaddr *src_addr, socklen_t *addrlen) -{ - return zsock_recvfrom(sock, buf, max_len, flags, src_addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_recvmsg */ -static inline ssize_t recvmsg(int sock, struct msghdr *msg, int flags) -{ - return zsock_recvmsg(sock, msg, flags); -} - -/** POSIX wrapper for @ref zsock_poll */ -static inline int poll(struct zsock_pollfd *fds, int nfds, int timeout) -{ - return zsock_poll(fds, nfds, timeout); -} - -/** POSIX wrapper for @ref zsock_getsockopt */ -static inline int getsockopt(int sock, int level, int optname, - void *optval, socklen_t *optlen) -{ - return zsock_getsockopt(sock, level, optname, optval, optlen); -} - -/** POSIX wrapper for @ref zsock_setsockopt */ -static inline int setsockopt(int sock, int level, int optname, - const void *optval, socklen_t optlen) -{ - return zsock_setsockopt(sock, level, optname, optval, optlen); -} - -/** POSIX wrapper for @ref zsock_getpeername */ -static inline int getpeername(int sock, struct sockaddr *addr, - socklen_t *addrlen) -{ - return zsock_getpeername(sock, addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_getsockname */ -static inline int getsockname(int sock, struct sockaddr *addr, - socklen_t *addrlen) -{ - return zsock_getsockname(sock, addr, addrlen); -} - -/** POSIX wrapper for @ref zsock_getaddrinfo */ -static inline int getaddrinfo(const char *host, const char *service, - const struct zsock_addrinfo *hints, - struct zsock_addrinfo **res) -{ - return zsock_getaddrinfo(host, service, hints, res); -} - -/** POSIX wrapper for @ref zsock_freeaddrinfo */ -static inline void freeaddrinfo(struct zsock_addrinfo *ai) -{ - zsock_freeaddrinfo(ai); -} - -/** POSIX wrapper for @ref zsock_gai_strerror */ -static inline const char *gai_strerror(int errcode) -{ - return zsock_gai_strerror(errcode); -} - -/** POSIX wrapper for @ref zsock_getnameinfo */ -static inline int getnameinfo(const struct sockaddr *addr, socklen_t addrlen, - char *host, socklen_t hostlen, - char *serv, socklen_t servlen, int flags) -{ - return zsock_getnameinfo(addr, addrlen, host, hostlen, - serv, servlen, flags); -} - -/** POSIX wrapper for @ref zsock_addrinfo */ -#define addrinfo zsock_addrinfo - -/** POSIX wrapper for @ref zsock_gethostname */ -static inline int gethostname(char *buf, size_t len) -{ - return zsock_gethostname(buf, len); -} - -/** POSIX wrapper for @ref zsock_inet_pton */ -static inline int inet_pton(sa_family_t family, const char *src, void *dst) -{ - return zsock_inet_pton(family, src, dst); -} - -/** POSIX wrapper for @ref zsock_inet_ntop */ -static inline char *inet_ntop(sa_family_t family, const void *src, char *dst, - size_t size) -{ - return zsock_inet_ntop(family, src, dst, size); -} - -/** POSIX wrapper for @ref ZSOCK_POLLIN */ -#define POLLIN ZSOCK_POLLIN -/** POSIX wrapper for @ref ZSOCK_POLLOUT */ -#define POLLOUT ZSOCK_POLLOUT -/** POSIX wrapper for @ref ZSOCK_POLLERR */ -#define POLLERR ZSOCK_POLLERR -/** POSIX wrapper for @ref ZSOCK_POLLHUP */ -#define POLLHUP ZSOCK_POLLHUP -/** POSIX wrapper for @ref ZSOCK_POLLNVAL */ -#define POLLNVAL ZSOCK_POLLNVAL - -/** POSIX wrapper for @ref ZSOCK_MSG_PEEK */ -#define MSG_PEEK ZSOCK_MSG_PEEK -/** POSIX wrapper for @ref ZSOCK_MSG_CTRUNC */ -#define MSG_CTRUNC ZSOCK_MSG_CTRUNC -/** POSIX wrapper for @ref ZSOCK_MSG_TRUNC */ -#define MSG_TRUNC ZSOCK_MSG_TRUNC -/** POSIX wrapper for @ref ZSOCK_MSG_DONTWAIT */ -#define MSG_DONTWAIT ZSOCK_MSG_DONTWAIT -/** POSIX wrapper for @ref ZSOCK_MSG_WAITALL */ -#define MSG_WAITALL ZSOCK_MSG_WAITALL - -/** POSIX wrapper for @ref ZSOCK_SHUT_RD */ -#define SHUT_RD ZSOCK_SHUT_RD -/** POSIX wrapper for @ref ZSOCK_SHUT_WR */ -#define SHUT_WR ZSOCK_SHUT_WR -/** POSIX wrapper for @ref ZSOCK_SHUT_RDWR */ -#define SHUT_RDWR ZSOCK_SHUT_RDWR - -/** POSIX wrapper for @ref DNS_EAI_BADFLAGS */ -#define EAI_BADFLAGS DNS_EAI_BADFLAGS -/** POSIX wrapper for @ref DNS_EAI_NONAME */ -#define EAI_NONAME DNS_EAI_NONAME -/** POSIX wrapper for @ref DNS_EAI_AGAIN */ -#define EAI_AGAIN DNS_EAI_AGAIN -/** POSIX wrapper for @ref DNS_EAI_FAIL */ -#define EAI_FAIL DNS_EAI_FAIL -/** POSIX wrapper for @ref DNS_EAI_NODATA */ -#define EAI_NODATA DNS_EAI_NODATA -/** POSIX wrapper for @ref DNS_EAI_MEMORY */ -#define EAI_MEMORY DNS_EAI_MEMORY -/** POSIX wrapper for @ref DNS_EAI_SYSTEM */ -#define EAI_SYSTEM DNS_EAI_SYSTEM -/** POSIX wrapper for @ref DNS_EAI_SERVICE */ -#define EAI_SERVICE DNS_EAI_SERVICE -/** POSIX wrapper for @ref DNS_EAI_SOCKTYPE */ -#define EAI_SOCKTYPE DNS_EAI_SOCKTYPE -/** POSIX wrapper for @ref DNS_EAI_FAMILY */ -#define EAI_FAMILY DNS_EAI_FAMILY -/** @} */ -#endif /* defined(CONFIG_NET_SOCKETS_POSIX_NAMES) */ - /** * @name Network interface name description * @{ @@ -1239,6 +954,14 @@ struct in_pktinfo { struct in_addr ipi_addr; /**< Header Destination address */ }; +/** Retrieve the current known path MTU of the current socket. Returns an + * integer. IP_MTU is valid only for getsockopt and can be employed only when + * the socket has been connected. + */ +#define IP_MTU 14 + +/** Set IPv4 multicast datagram network interface. */ +#define IP_MULTICAST_IF 32 /** Set IPv4 multicast TTL value. */ #define IP_MULTICAST_TTL 33 /** Join IPv4 multicast group. */ @@ -1255,6 +978,17 @@ struct ip_mreqn { int imr_ifindex; /**< Network interface index */ }; +/** + * @brief Struct used when setting a IPv4 multicast network interface. + */ +struct ip_mreq { + struct in_addr imr_multiaddr; /**< IP multicast group address */ + struct in_addr imr_interface; /**< IP address of local interface */ +}; + +/** Clamp down the global port range for a given socket */ +#define IP_LOCAL_PORT_RANGE 51 + /** @} */ /** @@ -1265,6 +999,9 @@ struct ip_mreqn { /** Set the unicast hop limit for the socket. */ #define IPV6_UNICAST_HOPS 16 +/** Set multicast output network interface index for the socket. */ +#define IPV6_MULTICAST_IF 17 + /** Set the multicast hop limit for the socket. */ #define IPV6_MULTICAST_HOPS 18 @@ -1274,6 +1011,12 @@ struct ip_mreqn { /** Leave IPv6 multicast group. */ #define IPV6_DROP_MEMBERSHIP 21 +/** Join IPv6 multicast group. */ +#define IPV6_JOIN_GROUP IPV6_ADD_MEMBERSHIP + +/** Leave IPv6 multicast group. */ +#define IPV6_LEAVE_GROUP IPV6_DROP_MEMBERSHIP + /** * @brief Struct used when joining or leaving a IPv6 multicast group. */ @@ -1285,6 +1028,13 @@ struct ipv6_mreq { int ipv6mr_ifindex; }; +/** For getsockopt(), retrieve the current known IPv6 path MTU of the given socket. + * Valid only when the socket has been connected. + * For setsockopt(), set the MTU to be used for the socket. The MTU is limited by + * the device MTU or the path MTU when path MTU discovery is enabled. + */ +#define IPV6_MTU 24 + /** Don't support IPv4 access */ #define IPV6_V6ONLY 26 @@ -1338,6 +1088,46 @@ struct in6_pktinfo { #define SOMAXCONN 128 /** @} */ +/** + * @name Macros for checking special IPv6 addresses. + * @{ + */ +/** Check unspecified IPv6 address. */ +#define IN6_IS_ADDR_UNSPECIFIED(addr) \ + net_ipv6_addr_cmp(net_ipv6_unspecified_address(), addr) + +/** Check loopback IPv6 address. */ +#define IN6_IS_ADDR_LOOPBACK(addr) net_ipv6_is_addr_loopback(addr) + +/** Check IPv6 multicast address */ +#define IN6_IS_ADDR_MULTICAST(addr) net_ipv6_is_addr_mcast(addr) + +/** Check IPv6 link local address */ +#define IN6_IS_ADDR_LINKLOCAL(addr) net_ipv6_is_ll_addr(addr) + +/** Check IPv6 site local address */ +#define IN6_IS_ADDR_SITELOCAL(addr) net_ipv6_is_sl_addr(addr) + +/** Check IPv6 v4 mapped address */ +#define IN6_IS_ADDR_V4MAPPED(addr) net_ipv6_addr_is_v4_mapped(addr) + +/** Check IPv6 multicast global address */ +#define IN6_IS_ADDR_MC_GLOBAL(addr) net_ipv6_is_addr_mcast_global(addr) + +/** Check IPv6 multicast node local address */ +#define IN6_IS_ADDR_MC_NODELOCAL(addr) net_ipv6_is_addr_mcast_iface(addr) + +/** Check IPv6 multicast link local address */ +#define IN6_IS_ADDR_MC_LINKLOCAL(addr) net_ipv6_is_addr_mcast_link(addr) + +/** Check IPv6 multicast site local address */ +#define IN6_IS_ADDR_MC_SITELOCAL(addr) net_ipv6_is_addr_mcast_site(addr) + +/** Check IPv6 multicast organization local address */ +#define IN6_IS_ADDR_MC_ORGLOCAL(addr) net_ipv6_is_addr_mcast_org(addr) + +/** @} */ + /** @cond INTERNAL_HIDDEN */ /** * @brief Registration information for a given BSD socket family. @@ -1401,13 +1191,26 @@ struct net_socket_register { * We have these includes here so that we do not need * to change the applications that were only including * zephyr/net/socket.h header file. + * + * Additionally, if non-zephyr-prefixed headers are used here, + * native_sim pulls in those from the host rather than Zephyr's. */ #if defined(CONFIG_POSIX_API) -#include -#include -#include -#include -#include +#if !defined(ZEPHYR_INCLUDE_POSIX_ARPA_INET_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_NETDB_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_UNISTD_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_POLL_H_) +#include +#endif +#if !defined(ZEPHYR_INCLUDE_POSIX_SYS_SOCKET_H_) +#include +#endif #endif /* CONFIG_POSIX_API */ #endif /* ZEPHYR_INCLUDE_NET_SOCKET_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_net_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_net_mgmt.h index 3c173f96..8f3c5829 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_net_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_net_mgmt.h @@ -24,7 +24,9 @@ extern "C" { /** * @brief Socket NET_MGMT library - * @defgroup socket_net_mgmt Network Core Library + * @defgroup socket_net_mgmt Socket NET_MGMT library + * @since 2.0 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_poll.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_poll.h index 97e03804..d794f103 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_poll.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_poll.h @@ -7,6 +7,8 @@ #ifndef ZEPHYR_INCLUDE_NET_SOCKET_POLL_H_ #define ZEPHYR_INCLUDE_NET_SOCKET_POLL_H_ +#include + /* Setting for pollfd to avoid circular inclusion */ /** @@ -20,6 +22,7 @@ extern "C" { #endif +#ifdef __DOXYGEN__ /** * @brief Definition of the monitored socket/file descriptor. * @@ -30,6 +33,9 @@ struct zsock_pollfd { short events; /**< Requested events */ short revents; /**< Returned events */ }; +#else +#define zsock_pollfd zvfs_pollfd +#endif #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_select.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_select.h index 5fca2950..10f3d9d4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_select.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_select.h @@ -19,142 +19,111 @@ * @{ */ +#include + #include #include +#include #ifdef __cplusplus extern "C" { #endif /** Socket file descriptor set. */ -typedef struct zsock_fd_set { - uint32_t bitset[(CONFIG_ZVFS_OPEN_MAX + 31) / 32]; -} zsock_fd_set; +typedef struct zvfs_fd_set zsock_fd_set; /** * @brief Legacy function to poll multiple sockets for events * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/select.html * for normative description. This function is provided to ease porting of * existing code and not recommended for usage due to its inefficiency, * use zsock_poll() instead. In Zephyr this function works only with * sockets, not arbitrary file descriptors. - * This function is also exposed as ``select()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined (in which case - * it may conflict with generic POSIX ``select()`` function). - * @endrst + * This function is also exposed as `select()` + * if @kconfig{CONFIG_POSIX_API} is defined (in which case + * it may conflict with generic POSIX `select()` function). */ -__syscall int zsock_select(int nfds, zsock_fd_set *readfds, - zsock_fd_set *writefds, - zsock_fd_set *exceptfds, - struct zsock_timeval *timeout); +static inline int zsock_select(int nfds, zsock_fd_set *readfds, zsock_fd_set *writefds, + zsock_fd_set *exceptfds, struct zsock_timeval *timeout) +{ + struct timespec to = { + .tv_sec = (timeout == NULL) ? 0 : timeout->tv_sec, + .tv_nsec = (long)((timeout == NULL) ? 0 : timeout->tv_usec * NSEC_PER_USEC)}; + + return zvfs_select(nfds, readfds, writefds, exceptfds, (timeout == NULL) ? NULL : &to, + NULL); +} /** Number of file descriptors which can be added to zsock_fd_set */ -#define ZSOCK_FD_SETSIZE (sizeof(((zsock_fd_set *)0)->bitset) * 8) +#define ZSOCK_FD_SETSIZE ZVFS_FD_SETSIZE /** * @brief Initialize (clear) fd_set * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/select.html * for normative description. - * This function is also exposed as ``FD_ZERO()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `FD_ZERO()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ -void ZSOCK_FD_ZERO(zsock_fd_set *set); +static inline void ZSOCK_FD_ZERO(zsock_fd_set *set) +{ + ZVFS_FD_ZERO(set); +} /** * @brief Check whether socket is a member of fd_set * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/select.html * for normative description. - * This function is also exposed as ``FD_ISSET()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `FD_ISSET()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ -int ZSOCK_FD_ISSET(int fd, zsock_fd_set *set); +static inline int ZSOCK_FD_ISSET(int fd, zsock_fd_set *set) +{ + return ZVFS_FD_ISSET(fd, set); +} /** * @brief Remove socket from fd_set * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/select.html * for normative description. - * This function is also exposed as ``FD_CLR()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `FD_CLR()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ -void ZSOCK_FD_CLR(int fd, zsock_fd_set *set); +static inline void ZSOCK_FD_CLR(int fd, zsock_fd_set *set) +{ + ZVFS_FD_CLR(fd, set); +} /** * @brief Add socket to fd_set * * @details - * @rst - * See `POSIX.1-2017 article - * `__ + * See POSIX.1-2017 article + * http://pubs.opengroup.org/onlinepubs/9699919799/functions/select.html * for normative description. - * This function is also exposed as ``FD_SET()`` - * if :kconfig:option:`CONFIG_POSIX_API` is defined. - * @endrst + * This function is also exposed as `FD_SET()` + * if @kconfig{CONFIG_POSIX_API} is defined. */ -void ZSOCK_FD_SET(int fd, zsock_fd_set *set); - -/** @cond INTERNAL_HIDDEN */ - -#ifdef CONFIG_NET_SOCKETS_POSIX_NAMES - -#define fd_set zsock_fd_set -#define FD_SETSIZE ZSOCK_FD_SETSIZE - -static inline int select(int nfds, zsock_fd_set *readfds, - zsock_fd_set *writefds, zsock_fd_set *exceptfds, - struct timeval *timeout) +static inline void ZSOCK_FD_SET(int fd, zsock_fd_set *set) { - return zsock_select(nfds, readfds, writefds, exceptfds, timeout); + ZVFS_FD_SET(fd, set); } -static inline void FD_ZERO(zsock_fd_set *set) -{ - ZSOCK_FD_ZERO(set); -} - -static inline int FD_ISSET(int fd, zsock_fd_set *set) -{ - return ZSOCK_FD_ISSET(fd, set); -} - -static inline void FD_CLR(int fd, zsock_fd_set *set) -{ - ZSOCK_FD_CLR(fd, set); -} - -static inline void FD_SET(int fd, zsock_fd_set *set) -{ - ZSOCK_FD_SET(fd, set); -} - -#endif /* CONFIG_NET_SOCKETS_POSIX_NAMES */ - -/** @endcond */ - #ifdef __cplusplus } #endif -#include - /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_service.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_service.h index f7c04fad..045d98dd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_service.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socket_service.h @@ -18,6 +18,8 @@ /** * @brief BSD socket service API * @defgroup bsd_socket_service BSD socket service API + * @since 3.6 + * @version 0.2.0 * @ingroup networking * @{ */ @@ -30,15 +32,23 @@ extern "C" { #endif +struct net_socket_service_event; + +/** @brief The signature for a net socket service handler function. + * + * The function will be invoked by the socket service. + * + * @param pev the socket service event that provided the handler. + */ +typedef void (*net_socket_service_handler_t)(struct net_socket_service_event *pev); + /** * This struct contains information which socket triggered * calls to the callback function. */ struct net_socket_service_event { - /** k_work that is done when there is desired activity in file descriptor. */ - struct k_work work; /** Callback to be called for desired socket activity */ - k_work_handler_t callback; + net_socket_service_handler_t callback; /** Socket information that triggered this event. */ struct zsock_pollfd event; /** User data */ @@ -65,8 +75,6 @@ struct net_socket_service_desc { */ const char *owner; #endif - /** Workqueue where the work is submitted. */ - struct k_work_q *work_q; /** Pointer to the list of services that we are listening */ struct net_socket_service_event *pev; /** Length of the pollable socket array for this service. */ @@ -81,15 +89,13 @@ struct net_socket_service_desc { #define __z_net_socket_svc_get_idx(_svc_id) __z_net_socket_service_idx_##_svc_id #define __z_net_socket_svc_get_owner __FILE__ ":" STRINGIFY(__LINE__) -extern void net_socket_service_callback(struct k_work *work); - #if CONFIG_NET_SOCKETS_LOG_LEVEL >= LOG_LEVEL_DBG #define NET_SOCKET_SERVICE_OWNER .owner = __z_net_socket_svc_get_owner, #else #define NET_SOCKET_SERVICE_OWNER #endif -#define __z_net_socket_service_define(_name, _work_q, _cb, _count, ...) \ +#define __z_net_socket_service_define(_name, _cb, _count, ...) \ static int __z_net_socket_svc_get_idx(_name); \ static struct net_socket_service_event \ __z_net_socket_svc_get_name(_name)[_count] = { \ @@ -101,7 +107,6 @@ extern void net_socket_service_callback(struct k_work *work); COND_CODE_0(NUM_VA_ARGS_LESS_1(__VA_ARGS__), (), __VA_ARGS__) \ const STRUCT_SECTION_ITERABLE(net_socket_service_desc, _name) = { \ NET_SOCKET_SERVICE_OWNER \ - .work_q = (_work_q), \ .pev = __z_net_socket_svc_get_name(_name), \ .pev_len = (_count), \ .idx = &__z_net_socket_svc_get_idx(_name), \ @@ -124,13 +129,11 @@ extern void net_socket_service_callback(struct k_work *work); * instead. * * @param name Name of the service. - * @param work_q Pointer to workqueue where the work is done. Can be null in which case - * system workqueue is used. * @param cb Callback function that is called for socket activity. * @param count How many pollable sockets is needed for this service. */ -#define NET_SOCKET_SERVICE_SYNC_DEFINE(name, work_q, cb, count) \ - __z_net_socket_service_define(name, work_q, cb, count) +#define NET_SOCKET_SERVICE_SYNC_DEFINE(name, cb, count) \ + __z_net_socket_service_define(name, cb, count) /** * @brief Statically define a network socket service in a private (static) scope. @@ -139,13 +142,11 @@ extern void net_socket_service_callback(struct k_work *work); * with next socket service. * * @param name Name of the service. - * @param work_q Pointer to workqueue where the work is done. Can be null in which case - * system workqueue is used. * @param cb Callback function that is called for socket activity. * @param count How many pollable sockets is needed for this service. */ -#define NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(name, work_q, cb, count) \ - __z_net_socket_service_define(name, work_q, cb, count, static) +#define NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(name, cb, count) \ + __z_net_socket_service_define(name, cb, count, static) /** * @brief Register pollable sockets. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan.h index dd2a7049..ca88d376 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan.h @@ -23,7 +23,9 @@ extern "C" { /** * @brief SocketCAN library - * @defgroup socket_can Network Core Library + * @defgroup socket_can SocketCAN library + * @since 1.14 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan_utils.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan_utils.h index 7db287ff..4c4d2118 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan_utils.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/socketcan_utils.h @@ -22,8 +22,7 @@ extern "C" { /** * @brief SocketCAN utilities - * @defgroup socket_can Network Core Library - * @ingroup networking + * @addtogroup socket_can * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tftp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tftp.h index eb3df0cc..5839987b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tftp.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tftp.h @@ -9,6 +9,8 @@ * @brief TFTP Client Implementation * * @defgroup tftp_client TFTP Client library + * @since 2.3 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tls_credentials.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tls_credentials.h index 77e2a230..6477543f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tls_credentials.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/tls_credentials.h @@ -16,6 +16,8 @@ /** * @brief TLS credentials management * @defgroup tls_credentials TLS credentials management + * @since 1.13 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/trickle.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/trickle.h index 9d46ffa0..9bd3e09f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/trickle.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/trickle.h @@ -26,6 +26,8 @@ extern "C" { /** * @brief Trickle algorithm library * @defgroup trickle Trickle Algorithm Library + * @since 1.7 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -134,7 +136,9 @@ void net_trickle_inconsistency(struct net_trickle *trickle); */ static inline bool net_trickle_is_running(struct net_trickle *trickle) { - NET_ASSERT(trickle); + if (trickle == NULL) { + return false; + } return trickle->I != 0U; } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual.h index 80666529..d229a214 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual.h @@ -29,6 +29,8 @@ extern "C" { /** * @brief Virtual network interface support functions * @defgroup virtual Virtual Network Interface Support Functions + * @since 2.6 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -41,6 +43,9 @@ enum virtual_interface_caps { /** Virtual LAN interface (VLAN) */ VIRTUAL_INTERFACE_VLAN = BIT(2), + /** Virtual Ethernet bridge interface. */ + VIRTUAL_INTERFACE_BRIDGE = BIT(3), + /** @cond INTERNAL_HIDDEN */ /* Marker for capabilities - must be at the end of the enum. * It is here because the capability list cannot be empty. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual_mgmt.h index 467a1fef..04ca6ae9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/virtual_mgmt.h @@ -22,6 +22,8 @@ extern "C" { /** * @brief Virtual interface library * @defgroup virtual_mgmt Virtual Interface Library + * @since 2.6 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/websocket.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/websocket.h index 067fa599..790a2e93 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/websocket.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/websocket.h @@ -26,6 +26,8 @@ extern "C" { /** * @brief Websocket API * @defgroup websocket Websocket API + * @since 1.12 + * @version 0.1.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi.h index 6f8bfc0c..e74a44ca 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi.h @@ -11,8 +11,10 @@ */ /** - * @defgroup wifi_mgmt Wi-Fi Management * @brief Wi-Fi Management API. + * @defgroup wifi_mgmt Wi-Fi Management + * @since 1.12 + * @version 0.8.0 * @ingroup networking * @{ */ @@ -46,22 +48,144 @@ enum wifi_security_type { WIFI_SECURITY_TYPE_PSK_SHA256, /** WPA3-SAE security. */ WIFI_SECURITY_TYPE_SAE, + /** WPA3-SAE security with hunting-and-pecking loop. */ + WIFI_SECURITY_TYPE_SAE_HNP = WIFI_SECURITY_TYPE_SAE, + /** WPA3-SAE security with hash-to-element. */ + WIFI_SECURITY_TYPE_SAE_H2E, + /** WPA3-SAE security with both hunting-and-pecking loop and hash-to-element enabled. */ + WIFI_SECURITY_TYPE_SAE_AUTO, /** GB 15629.11-2003 WAPI security. */ WIFI_SECURITY_TYPE_WAPI, /** EAP security - Enterprise. */ WIFI_SECURITY_TYPE_EAP, + /** EAP TLS security - Enterprise. */ + WIFI_SECURITY_TYPE_EAP_TLS = WIFI_SECURITY_TYPE_EAP, /** WEP security. */ WIFI_SECURITY_TYPE_WEP, /** WPA-PSK security. */ WIFI_SECURITY_TYPE_WPA_PSK, /** WPA/WPA2/WPA3 PSK security. */ WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL, - -/** @cond INTERNAL_HIDDEN */ + /** DPP security */ + WIFI_SECURITY_TYPE_DPP, + /** EAP PEAP MSCHAPV2 security - Enterprise. */ + WIFI_SECURITY_TYPE_EAP_PEAP_MSCHAPV2, + /** EAP PEAP GTC security - Enterprise. */ + WIFI_SECURITY_TYPE_EAP_PEAP_GTC, + /** EAP TTLS MSCHAPV2 security - Enterprise. */ + WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2, + /** EAP PEAP security - Enterprise. */ + WIFI_SECURITY_TYPE_EAP_PEAP_TLS, + /** EAP TLS SHA256 security - Enterprise. */ + WIFI_SECURITY_TYPE_EAP_TLS_SHA256, + /** FT-PSK security */ + WIFI_SECURITY_TYPE_FT_PSK, + /** FT-SAE security */ + WIFI_SECURITY_TYPE_FT_SAE, + /** FT-EAP security */ + WIFI_SECURITY_TYPE_FT_EAP, + /** FT-EAP-SHA384 security */ + WIFI_SECURITY_TYPE_FT_EAP_SHA384, + + /** @cond INTERNAL_HIDDEN */ __WIFI_SECURITY_TYPE_AFTER_LAST, WIFI_SECURITY_TYPE_MAX = __WIFI_SECURITY_TYPE_AFTER_LAST - 1, WIFI_SECURITY_TYPE_UNKNOWN -/** @endcond */ + /** @endcond */ +}; + +/** @brief EPA method Types. */ +enum wifi_eap_type { + /** No EPA security. */ + WIFI_EAP_TYPE_NONE = 0, + /** EPA GTC security, refer to rfc3748 chapter 5. */ + WIFI_EAP_TYPE_GTC = 6, + /** EPA TLS security, refer to rfc5216. */ + WIFI_EAP_TYPE_TLS = 13, + /** EPA TTLS security, refer to rfc5281. */ + WIFI_EAP_TYPE_TTLS = 21, + /** EPA PEAP security, refer to draft-josefsson-pppext-eap-tls-eap-06.txt. */ + WIFI_EAP_TYPE_PEAP = 25, + /** EPA MSCHAPV2 security, refer to draft-kamath-pppext-eap-mschapv2-00.txt. */ + WIFI_EAP_TYPE_MSCHAPV2 = 26, +}; + +/** @brief Enterprise security WPA3 suiteb types. */ +enum wifi_suiteb_type { + /** suiteb. */ + WIFI_SUITEB = 1, + /** suiteb-192. */ + WIFI_SUITEB_192, +}; + +enum wifi_eap_tls_cipher_type { + /** EAP TLS with NONE */ + WIFI_EAP_TLS_NONE, + /** EAP TLS with ECDH & ECDSA with p384 */ + WIFI_EAP_TLS_ECC_P384, + /** EAP TLS with ECDH & RSA with > 3K */ + WIFI_EAP_TLS_RSA_3K, +}; + +/** @brief Group cipher and pairwise cipher types. */ +enum wifi_cipher_type { + /** AES in counter mode with CBC-MAC (CCMP-128). */ + WPA_CAPA_ENC_CCMP, + /** 128-bit Galois/Counter Mode Protocol. */ + WPA_CAPA_ENC_GCMP, + /** 256-bit Galois/Counter Mode Protocol. */ + WPA_CAPA_ENC_GCMP_256, +}; + +/** @brief group mgmt cipher types. */ +enum wifi_group_mgmt_cipher_type { + /** 128-bit Broadcast/Multicast Integrity Protocol + * Cipher-based Message Authentication Code . + */ + WPA_CAPA_ENC_BIP, + /** 128-bit Broadcast/Multicast Integrity Protocol + * Galois Message Authentication Code . + */ + WPA_CAPA_ENC_BIP_GMAC_128, + /** 256-bit Broadcast/Multicast Integrity Protocol + * Galois Message Authentication Code . + */ + WPA_CAPA_ENC_BIP_GMAC_256, +}; + +struct wifi_cipher_desc { + /** Cipher capability. */ + unsigned int capa; + /** Cipher name string. */ + char *name; +}; + +struct wifi_eap_cipher_config { + /** Key management type string. */ + char *key_mgmt; + /** OpenSSL cipher string. */ + char *openssl_ciphers; + /** Group cipher cipher string. */ + char *group_cipher; + /** Pairwise_cipher cipher string. */ + char *pairwise_cipher; + /** Group management cipher string. */ + char *group_mgmt_cipher; + /** Used to confiure TLS features. */ + char *tls_flags; +}; + +struct wifi_eap_config { + /** Security type. */ + unsigned int type; + /** EPA method type of phase1. */ + enum wifi_eap_type eap_type_phase1; + /** EPA method type of phase2. */ + enum wifi_eap_type eap_type_phase2; + /** EPA method string. */ + char *method; + /** Phase2 setting string. */ + char *phase2; }; /** Helper function to get user-friendly security type name. */ @@ -108,6 +232,27 @@ enum wifi_frequency_bands { /** Helper function to get user-friendly frequency band name. */ const char *wifi_band_txt(enum wifi_frequency_bands band); +/** + * @brief IEEE 802.11 operational frequency bandwidths (not exhaustive). + */ +enum wifi_frequency_bandwidths { + /** 20 MHz. */ + WIFI_FREQ_BANDWIDTH_20MHZ = 1, + /** 40 MHz. */ + WIFI_FREQ_BANDWIDTH_40MHZ, + /** 80 MHz. */ + WIFI_FREQ_BANDWIDTH_80MHZ, + + /** Number of frequency bandwidths available. */ + __WIFI_FREQ_BANDWIDTH_AFTER_LAST, + /** Highest frequency bandwidth available. */ + WIFI_FREQ_BANDWIDTH_MAX = __WIFI_FREQ_BANDWIDTH_AFTER_LAST - 1, + /** Invalid frequency bandwidth */ + WIFI_FREQ_BANDWIDTH_UNKNOWN +}; + +const char *const wifi_bandwidth_txt(enum wifi_frequency_bandwidths bandwidth); + /** Max SSID length */ #define WIFI_SSID_MAX_LEN 32 /** Minimum PSK length */ @@ -118,6 +263,10 @@ const char *wifi_band_txt(enum wifi_frequency_bands band); #define WIFI_SAE_PSWD_MAX_LEN 128 /** MAC address length */ #define WIFI_MAC_ADDR_LEN 6 +/** Max enterprise identity length */ +#define WIFI_ENT_IDENTITY_MAX_LEN 64 +/** Max enterprise password length */ +#define WIFI_ENT_PSWD_MAX_LEN 128 /** Minimum channel number */ #define WIFI_CHANNEL_MIN 1 @@ -428,12 +577,14 @@ static inline const char *wifi_twt_get_err_code_str(int16_t err_no) enum wifi_ps_param_type { /** Power save state. */ WIFI_PS_PARAM_STATE, - /** Power save listen interval. */ + /** Power save listen interval (units: (short) beacon intervals). */ WIFI_PS_PARAM_LISTEN_INTERVAL, /** Power save wakeup mode. */ WIFI_PS_PARAM_WAKEUP_MODE, /** Power save mode. */ WIFI_PS_PARAM_MODE, + /** Power save exit strategy. */ + WIFI_PS_PARAM_EXIT_STRATEGY, /** Power save timeout. */ WIFI_PS_PARAM_TIMEOUT, }; @@ -449,6 +600,24 @@ enum wifi_ps_wakeup_mode { /** Helper function to get user-friendly ps wakeup mode name. */ const char *wifi_ps_wakeup_mode_txt(enum wifi_ps_wakeup_mode ps_wakeup_mode); +/** + * @brief Wi-Fi power save exit strategy + */ +enum wifi_ps_exit_strategy { + /** PS-Poll frame based */ + WIFI_PS_EXIT_CUSTOM_ALGO = 0, + /** QoS NULL frame based */ + WIFI_PS_EXIT_EVERY_TIM, + +/** @cond INTERNAL_HIDDEN */ + WIFI_PS_EXIT_LAST, + WIFI_PS_EXIT_MAX = WIFI_PS_EXIT_LAST - 1, +/** @endcond */ +}; + +/** Helper function to get user-friendly ps exit strategy name. */ +const char *wifi_ps_exit_strategy_txt(enum wifi_ps_exit_strategy ps_exit_strategy); + /** @brief Wi-Fi power save error codes. */ enum wifi_config_ps_param_fail_reason { /** Unspecified error */ @@ -465,6 +634,8 @@ enum wifi_config_ps_param_fail_reason { WIFI_PS_PARAM_FAIL_DEVICE_CONNECTED, /** Listen interval out of range */ WIFI_PS_PARAM_LISTEN_INTERVAL_RANGE_INVALID, + /** Invalid exit strategy */ + WIFI_PS_PARAM_FAIL_INVALID_EXIT_STRATEGY, }; /** @cond INTERNAL_HIDDEN */ @@ -484,6 +655,20 @@ static const char * const wifi_ps_param_config_err_code_tbl[] = { }; /** @endcond */ +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM +/** IEEE 802.11v BTM (BSS transition management) Query reasons. + * Refer to IEEE Std 802.11v-2011 - Table 7-43x-Transition and Transition Query reasons table. + */ +enum wifi_btm_query_reason { + /** Unspecified. */ + WIFI_BTM_QUERY_REASON_UNSPECIFIED = 0, + /** Low RSSI. */ + WIFI_BTM_QUERY_REASON_LOW_RSSI = 16, + /** Leaving ESS. */ + WIFI_BTM_QUERY_REASON_LEAVING_ESS = 20, +}; +#endif + /** Helper function to get user-friendly power save error code name. */ static inline const char *wifi_ps_get_config_err_code_str(int16_t err_no) { @@ -500,6 +685,12 @@ enum wifi_ap_config_param { WIFI_AP_CONFIG_PARAM_MAX_INACTIVITY = BIT(0), /** Used for AP mode configuration parameter max_num_sta */ WIFI_AP_CONFIG_PARAM_MAX_NUM_STA = BIT(1), + /** Used for AP mode configuration parameter bandwidth */ + WIFI_AP_CONFIG_PARAM_BANDWIDTH = BIT(2), + /** Used for AP mode configuration parameter ht_capab */ + WIFI_AP_CONFIG_PARAM_HT_CAPAB = BIT(3), + /** Used for AP mode configuration parameter vht_capab */ + WIFI_AP_CONFIG_PARAM_VHT_CAPAB = BIT(4), }; #ifdef __cplusplus diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_credentials.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_credentials.h new file mode 100644 index 00000000..0241930e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_credentials.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef WIFI_CREDENTIALS_H__ +#define WIFI_CREDENTIALS_H__ + +#include +#include +#include + +/** + * @defgroup wifi_credentials Wi-Fi credentials library + * @ingroup networking + * @since 4.0 + * @version 0.1.0 + * @{ + * @brief Library that provides a way to store and load Wi-Fi credentials. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* this entry contains a BSSID */ +#define WIFI_CREDENTIALS_FLAG_BSSID BIT(0) +/* this entry is to be preferred over others */ +#define WIFI_CREDENTIALS_FLAG_FAVORITE BIT(1) +/* this entry can use the 2.4 GHz band */ +#define WIFI_CREDENTIALS_FLAG_2_4GHz BIT(2) +/* this entry can use the 5 GHz band */ +#define WIFI_CREDENTIALS_FLAG_5GHz BIT(3) +/* this entry requires management frame protection */ +#define WIFI_CREDENTIALS_FLAG_MFP_REQUIRED BIT(4) +/* this entry disables management frame protection */ +#define WIFI_CREDENTIALS_FLAG_MFP_DISABLED BIT(5) + +#define WIFI_CREDENTIALS_MAX_PASSWORD_LEN \ + MAX(WIFI_PSK_MAX_LEN, CONFIG_WIFI_CREDENTIALS_SAE_PASSWORD_LENGTH) + +/** + * @brief Wi-Fi credentials entry header + * @note Every settings entry starts with this header. + * Depending on the `type` field, the header can be casted to a larger type. + * In addition to SSID (usually a string) and BSSID (a MAC address), + * a `flags` field can be used to control some detail settings. + * + */ +struct wifi_credentials_header { + enum wifi_security_type type; /**< Wi-Fi security type */ + char ssid[WIFI_SSID_MAX_LEN]; /**< SSID (Service Set Identifier) */ + size_t ssid_len; /**< Length of the SSID */ + uint32_t flags; /**< Flags for controlling detail settings */ + uint32_t timeout; /**< Timeout for connecting to the network */ + uint8_t bssid[WIFI_MAC_ADDR_LEN]; /**< BSSID (Basic Service Set Identifier) */ + uint8_t channel; /**< Channel on which the network operates */ +}; + +/** + * @brief Wi-Fi Personal credentials entry + * @note Contains only the header and a password. + * For PSK security, passwords can be up to `WIFI_PSK_MAX_LEN` bytes long + * including NULL termination. For SAE security it can range up to + * `CONFIG_WIFI_CREDENTIALS_SAE_PASSWORD_LENGTH`. + * + */ +struct wifi_credentials_personal { + struct wifi_credentials_header header; /**< Header */ + char password[WIFI_CREDENTIALS_MAX_PASSWORD_LEN]; /**< Password/PSK */ + size_t password_len; /**< Length of the password */ +}; + +/** + * @brief Wi-Fi Enterprise credentials entry + * @note This functionality is not yet implemented. + */ +struct wifi_credentials_enterprise { + struct wifi_credentials_header header; /**< Header */ + size_t identity_len; /**< Length of the identity */ + size_t anonymous_identity_len; /**< Length of the anonymous identity */ + size_t password_len; /**< Length of the password */ + size_t ca_cert_len; /**< Length of the CA certificate */ + size_t client_cert_len; /**< Length of the client certificate */ + size_t private_key_len; /**< Length of the private key */ + size_t private_key_pw_len; /**< Length of the private key password */ +}; + +/** + * @brief Get credentials for given SSID. + * + * @param[in] ssid SSID to look for + * @param[in] ssid_len length of SSID + * @param[out] type Wi-Fi security type + * @param[out] bssid_buf buffer to store BSSID if it was fixed + * @param[in] bssid_buf_len length of bssid_buf + * @param[out] password_buf buffer to store password + * @param[in] password_buf_len length of password_buf + * @param[out] password_len length of password + * @param[out] flags flags + * @param[out] channel channel + * @param[out] timeout timeout + * + * @return 0 Success. + * @return -ENOENT No network with this SSID was found. + * @return -EINVAL A required buffer was NULL or invalid SSID length. + * @return -EPROTO The network with this SSID is not a personal network. + */ +int wifi_credentials_get_by_ssid_personal(const char *ssid, size_t ssid_len, + enum wifi_security_type *type, uint8_t *bssid_buf, + size_t bssid_buf_len, char *password_buf, + size_t password_buf_len, size_t *password_len, + uint32_t *flags, uint8_t *channel, uint32_t *timeout); + +/** + * @brief Set credentials for given SSID. + * + * @param[in] ssid SSID to look for + * @param[in] ssid_len length of SSID + * @param[in] type Wi-Fi security type + * @param[in] bssid BSSID (may be NULL) + * @param[in] bssid_len length of BSSID buffer (either 0 or WIFI_MAC_ADDR_LEN) + * @param[in] password password + * @param[in] password_len length of password + * @param[in] flags flags + * @param[in] channel Channel + * @param[in] timeout Timeout + * + * @return 0 Success. Credentials are stored in persistent storage. + * @return -EINVAL A required buffer was NULL or security type is not supported. + * @return -ENOTSUP Security type is not supported. + * @return -ENOBUFS All slots are already taken. + */ +int wifi_credentials_set_personal(const char *ssid, size_t ssid_len, enum wifi_security_type type, + const uint8_t *bssid, size_t bssid_len, const char *password, + size_t password_len, uint32_t flags, uint8_t channel, + uint32_t timeout); + +/** + * @brief Get credentials for given SSID by struct. + * + * @param[in] ssid SSID to look for + * @param[in] ssid_len length of SSID + * @param[out] buf credentials Pointer to struct where credentials are stored + * + * @return 0 Success. + * @return -ENOENT No network with this SSID was found. + * @return -EINVAL A required buffer was NULL or too small. + * @return -EPROTO The network with this SSID is not a personal network. + */ +int wifi_credentials_get_by_ssid_personal_struct(const char *ssid, size_t ssid_len, + struct wifi_credentials_personal *buf); + +/** + * @brief Set credentials for given SSID by struct. + * + * @param[in] creds credentials Pointer to struct from which credentials are loaded + * + * @return 0 Success. + * @return -ENOENT No network with this SSID was found. + * @return -EINVAL A required buffer was NULL or incorrect size. + * @return -ENOBUFS All slots are already taken. + */ +int wifi_credentials_set_personal_struct(const struct wifi_credentials_personal *creds); + +/** + * @brief Delete credentials for given SSID. + * + * @param[in] ssid SSID to look for + * @param[in] ssid_len length of SSID + * + * @return -ENOENT if No network with this SSID was found. + * @return 0 on success, otherwise a negative error code + */ +int wifi_credentials_delete_by_ssid(const char *ssid, size_t ssid_len); + +/** + * @brief Check if credentials storage is empty. + * + * @return true if credential storage is empty, otherwise false + */ +bool wifi_credentials_is_empty(void); + +/** + * @brief Deletes all stored Wi-Fi credentials. + * + * This function deletes all Wi-Fi credentials that have been stored in the system. + * It is typically used when you want to clear all saved networks. + * + * @return 0 on successful, otherwise a negative error code + */ +int wifi_credentials_delete_all(void); + +/** + * @brief Callback type for wifi_credentials_for_each_ssid. + * @param[in] cb_arg arguments for the callback function. Appropriate cb_arg is + * transferred by wifi_credentials_for_each_ssid. + * @param[in] ssid SSID + * @param[in] ssid_len length of SSID + */ +typedef void (*wifi_credentials_ssid_cb)(void *cb_arg, const char *ssid, size_t ssid_len); + +/** + * @brief Call callback for each registered SSID. + * + * @param cb callback + * @param cb_arg argument for callback function + */ +void wifi_credentials_for_each_ssid(wifi_credentials_ssid_cb cb, void *cb_arg); + +#ifdef __cplusplus +} +#endif + +/** @} */ + +#endif /* WIFI_CREDENTIALS_H__ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_mgmt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_mgmt.h index 3c385994..d9d84303 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_mgmt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_mgmt.h @@ -1,5 +1,7 @@ /* * Copyright (c) 2017 Intel Corporation. + * Copyright 2024 NXP + * Copyright (c) 2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -49,6 +51,12 @@ extern "C" { #define WIFI_MGMT_SCAN_CHAN_MAX_MANUAL 1 #endif /* CONFIG_WIFI_MGMT_SCAN_CHAN_MAX_MANUAL */ +#ifdef CONFIG_WIFI_ENT_IDENTITY_MAX_USERS +#define WIFI_ENT_IDENTITY_MAX_USERS CONFIG_WIFI_ENT_IDENTITY_MAX_USERS +#else +#define WIFI_ENT_IDENTITY_MAX_USERS 1 +#endif /* CONFIG_WIFI_ENT_IDENTITY_MAX_USERS */ + #define WIFI_MGMT_BAND_STR_SIZE_MAX 8 #define WIFI_MGMT_SCAN_MAX_BSS_CNT 65535 @@ -69,6 +77,10 @@ enum net_request_wifi_cmd { NET_REQUEST_WIFI_CMD_AP_DISABLE, /** Get interface status */ NET_REQUEST_WIFI_CMD_IFACE_STATUS, + /** Set or get 11k status */ + NET_REQUEST_WIFI_CMD_11K_CONFIG, + /** Send 11k neighbor request */ + NET_REQUEST_WIFI_CMD_11K_NEIGHBOR_REQUEST, /** Set power save status */ NET_REQUEST_WIFI_CMD_PS, /** Setup or teardown TWT flow */ @@ -87,13 +99,41 @@ enum net_request_wifi_cmd { NET_REQUEST_WIFI_CMD_AP_STA_DISCONNECT, /** Get Wi-Fi driver and Firmware versions */ NET_REQUEST_WIFI_CMD_VERSION, + /** Get Wi-Fi latest connection parameters */ + NET_REQUEST_WIFI_CMD_CONN_PARAMS, /** Set RTS threshold */ NET_REQUEST_WIFI_CMD_RTS_THRESHOLD, /** Configure AP parameter */ NET_REQUEST_WIFI_CMD_AP_CONFIG_PARAM, -/** @cond INTERNAL_HIDDEN */ + /** DPP actions */ + NET_REQUEST_WIFI_CMD_DPP, +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM + /** BSS transition management query */ + NET_REQUEST_WIFI_CMD_BTM_QUERY, +#endif + /** Flush PMKSA cache entries */ + NET_REQUEST_WIFI_CMD_PMKSA_FLUSH, + /** Set enterprise mode credential */ + NET_REQUEST_WIFI_CMD_ENTERPRISE_CREDS, + /** Get RTS threshold */ + NET_REQUEST_WIFI_CMD_RTS_THRESHOLD_CONFIG, + /** WPS config */ + NET_REQUEST_WIFI_CMD_WPS_CONFIG, +#ifdef CONFIG_WIFI_CREDENTIALS_CONNECT_STORED + /** Connect to APs stored using wifi_credentials library. */ + NET_REQUEST_WIFI_CMD_CONNECT_STORED, +#endif + /** Start roaming */ + NET_REQUEST_WIFI_CMD_START_ROAMING, + /** Neighbor report complete */ + NET_REQUEST_WIFI_CMD_NEIGHBOR_REP_COMPLETE, + /** Specific scan */ + NET_REQUEST_WIFI_CMD_CANDIDATE_SCAN, + /** AP WPS config */ + NET_REQUEST_WIFI_CMD_AP_WPS_CONFIG, + /** @cond INTERNAL_HIDDEN */ NET_REQUEST_WIFI_CMD_MAX -/** @endcond */ + /** @endcond */ }; /** Request a Wi-Fi scan */ @@ -132,6 +172,16 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_AP_DISABLE); NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_IFACE_STATUS); +#define NET_REQUEST_WIFI_11K_CONFIG \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_11K_CONFIG) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_11K_CONFIG); + +#define NET_REQUEST_WIFI_11K_NEIGHBOR_REQUEST \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_11K_NEIGHBOR_REQUEST) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_11K_NEIGHBOR_REQUEST); + /** Request a Wi-Fi power save */ #define NET_REQUEST_WIFI_PS \ (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_PS) @@ -186,6 +236,12 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_AP_STA_DISCONNECT); NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_VERSION); +/** Request a Wi-Fi connection parameters */ +#define NET_REQUEST_WIFI_CONN_PARAMS \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_CONN_PARAMS) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_CONN_PARAMS); + /** Request a Wi-Fi RTS threshold */ #define NET_REQUEST_WIFI_RTS_THRESHOLD \ (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_RTS_THRESHOLD) @@ -198,6 +254,58 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_RTS_THRESHOLD); NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_AP_CONFIG_PARAM); +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP +/** Request a Wi-Fi DPP operation */ +#define NET_REQUEST_WIFI_DPP \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_DPP) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_DPP); +#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */ + +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM +/** Request a Wi-Fi BTM query */ +#define NET_REQUEST_WIFI_BTM_QUERY (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_BTM_QUERY) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_BTM_QUERY); +#endif + +/** Request a Wi-Fi PMKSA cache entries flush */ +#define NET_REQUEST_WIFI_PMKSA_FLUSH \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_PMKSA_FLUSH) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_PMKSA_FLUSH); + +/** Set Wi-Fi enterprise mode CA/client Cert and key */ +#define NET_REQUEST_WIFI_ENTERPRISE_CREDS \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_ENTERPRISE_CREDS) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_ENTERPRISE_CREDS); + +/** Request a Wi-Fi RTS threshold configuration */ +#define NET_REQUEST_WIFI_RTS_THRESHOLD_CONFIG \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_RTS_THRESHOLD_CONFIG) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_RTS_THRESHOLD_CONFIG); + +#define NET_REQUEST_WIFI_WPS_CONFIG (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_WPS_CONFIG) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_WPS_CONFIG); +#ifdef CONFIG_WIFI_CREDENTIALS_CONNECT_STORED +#define NET_REQUEST_WIFI_CONNECT_STORED (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_CONNECT_STORED) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_CONNECT_STORED); +#endif + +#define NET_REQUEST_WIFI_START_ROAMING \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_START_ROAMING) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_START_ROAMING); + +#define NET_REQUEST_WIFI_NEIGHBOR_REP_COMPLETE \ + (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_NEIGHBOR_REP_COMPLETE) + +NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_NEIGHBOR_REP_COMPLETE); + /** @brief Wi-Fi management events */ enum net_event_wifi_cmd { /** Scan results available */ @@ -220,6 +328,12 @@ enum net_event_wifi_cmd { NET_EVENT_WIFI_CMD_RAW_SCAN_RESULT, /** Disconnect complete */ NET_EVENT_WIFI_CMD_DISCONNECT_COMPLETE, + /** Signal change event */ + NET_EVENT_WIFI_CMD_SIGNAL_CHANGE, + /** Neighbor Report */ + NET_EVENT_WIFI_CMD_NEIGHBOR_REP_RECEIVED, + /** Neighbor Report complete */ + NET_EVENT_WIFI_CMD_NEIGHBOR_REP_COMPLETE, /** AP mode enable result */ NET_EVENT_WIFI_CMD_AP_ENABLE_RESULT, /** AP mode disable result */ @@ -228,6 +342,8 @@ enum net_event_wifi_cmd { NET_EVENT_WIFI_CMD_AP_STA_CONNECTED, /** STA disconnected from AP */ NET_EVENT_WIFI_CMD_AP_STA_DISCONNECTED, + /** Supplicant specific event */ + NET_EVENT_WIFI_CMD_SUPPLICANT, }; /** Event emitted for Wi-Fi scan result */ @@ -266,6 +382,14 @@ enum net_event_wifi_cmd { #define NET_EVENT_WIFI_DISCONNECT_COMPLETE \ (_NET_WIFI_EVENT | NET_EVENT_WIFI_CMD_DISCONNECT_COMPLETE) +/** Event signal change of connected AP */ +#define NET_EVENT_WIFI_SIGNAL_CHANGE \ + (_NET_WIFI_EVENT | NET_EVENT_WIFI_CMD_SIGNAL_CHANGE) + +/** Event Neighbor Report Completed */ +#define NET_EVENT_WIFI_NEIGHBOR_REP_COMP \ + (_NET_WIFI_EVENT | NET_EVENT_WIFI_CMD_NEIGHBOR_REP_COMPLETE) + /** Event emitted for Wi-Fi access point enable result */ #define NET_EVENT_WIFI_AP_ENABLE_RESULT \ (_NET_WIFI_EVENT | NET_EVENT_WIFI_CMD_AP_ENABLE_RESULT) @@ -357,7 +481,7 @@ struct wifi_scan_params { */ struct wifi_scan_result { /** SSID */ - uint8_t ssid[WIFI_SSID_MAX_LEN]; + uint8_t ssid[WIFI_SSID_MAX_LEN + 1]; /** SSID length */ uint8_t ssid_length; /** Frequency band */ @@ -402,6 +526,50 @@ struct wifi_connect_req_params { uint8_t bssid[WIFI_MAC_ADDR_LEN]; /** Connect timeout in seconds, SYS_FOREVER_MS for no timeout */ int timeout; + /** anonymous identity */ + const uint8_t *anon_id; + /** anon_id length, max 64 */ + uint8_t aid_length; + /** Private key passwd for enterprise mode */ + const uint8_t *key_passwd; + /** Private key passwd length, max 128 */ + uint8_t key_passwd_length; + /** private key2 passwd */ + const uint8_t *key2_passwd; + /** key2 passwd length, max 128 */ + uint8_t key2_passwd_length; + /** suiteb or suiteb-192 */ + uint8_t suiteb_type; + /** TLS cipher */ + uint8_t TLS_cipher; + /** eap version */ + int eap_ver; + /** Identity for EAP */ + const uint8_t *eap_identity; + /** eap identity length, max 64 */ + uint8_t eap_id_length; + /** Password string for EAP. */ + const uint8_t *eap_password; + /** eap passwd length, max 128 */ + uint8_t eap_passwd_length; + /** Fast BSS Transition used */ + bool ft_used; + /** Number of EAP users */ + int nusers; + /** Number of EAP passwds */ + uint8_t passwds; + /** User Identities */ + const uint8_t *identities[WIFI_ENT_IDENTITY_MAX_USERS]; + /** User Passwords */ + const uint8_t *passwords[WIFI_ENT_IDENTITY_MAX_USERS]; + /** Hidden SSID configure + * 0: disabled (default) + * 1: send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID + * 2: clear SSID, but keep the original length and ignore probe request for broadcast SSID + */ + uint8_t ignore_broadcast_ssid; + /** Parameter used for frequency band */ + enum wifi_frequency_bandwidths bandwidth; }; /** @brief Wi-Fi connect result codes. To be overlaid on top of \ref wifi_status @@ -490,7 +658,7 @@ struct wifi_iface_status { /** SSID length */ unsigned int ssid_len; /** SSID */ - char ssid[WIFI_SSID_MAX_LEN]; + char ssid[WIFI_SSID_MAX_LEN + 1]; /** BSSID */ char bssid[WIFI_MAC_ADDR_LEN]; /** Frequency band */ @@ -513,6 +681,8 @@ struct wifi_iface_status { unsigned short beacon_interval; /** is TWT capable? */ bool twt_capable; + /** The current 802.11 PHY TX data rate (in Kbps) */ + int current_phy_tx_rate; }; /** @brief Wi-Fi power save parameters */ @@ -538,6 +708,8 @@ struct wifi_ps_params { enum wifi_ps_param_type type; /** Wi-Fi power save fail reason */ enum wifi_config_ps_param_fail_reason fail_reason; + /** Wi-Fi power save exit strategy */ + enum wifi_ps_exit_strategy exit_strategy; }; /** @brief Wi-Fi TWT parameters */ @@ -623,6 +795,46 @@ struct wifi_twt_flow_info { uint32_t twt_wake_ahead_duration; }; +/** Wi-Fi enterprise mode credentials */ +struct wifi_enterprise_creds_params { + /** CA certification */ + uint8_t *ca_cert; + /** CA certification length */ + uint32_t ca_cert_len; + /** Client certification */ + uint8_t *client_cert; + /** Client certification length */ + uint32_t client_cert_len; + /** Client key */ + uint8_t *client_key; + /** Client key length */ + uint32_t client_key_len; + /** CA certification of phase2*/ + uint8_t *ca_cert2; + /** Phase2 CA certification length */ + uint32_t ca_cert2_len; + /** Client certification of phase2*/ + uint8_t *client_cert2; + /** Phase2 Client certification length */ + uint32_t client_cert2_len; + /** Client key of phase2*/ + uint8_t *client_key2; + /** Phase2 Client key length */ + uint32_t client_key2_len; + /** Server certification */ + uint8_t *server_cert; + /** Server certification length */ + uint32_t server_cert_len; + /** Server key */ + uint8_t *server_key; + /** Server key length */ + uint32_t server_key_len; + /** Diffie–Hellman parameter */ + uint8_t *dh_param; + /** Diffie–Hellman parameter length */ + uint32_t dh_param_len; +}; + /** @brief Wi-Fi power save configuration */ struct wifi_ps_config { /** Number of TWT flows */ @@ -641,6 +853,16 @@ enum wifi_mgmt_op { WIFI_MGMT_SET = 1, }; +/** Wi-Fi 11k parameters */ +struct wifi_11k_params { + /** 11k command operation */ + enum wifi_mgmt_op oper; + /** 11k enable/disable */ + bool enable_11k; + /** SSID */ + uint8_t ssid[WIFI_SSID_MAX_LEN + 1]; +}; + /** Max regulatory channel number */ #define MAX_REG_CHAN_NUM 42 @@ -662,7 +884,9 @@ struct wifi_reg_chan_info { struct wifi_reg_domain { /** Regulatory domain operation */ enum wifi_mgmt_op oper; - /** Ignore all other regulatory hints over this one */ + /** Ignore all other regulatory hints over this one, the behavior is + * implementation specific. + */ bool force; /** Country code: ISO/IEC 3166-1 alpha-2 */ uint8_t country_code[WIFI_COUNTRY_CODE_LEN]; @@ -756,6 +980,7 @@ struct wifi_channel_info { /** @cond INTERNAL_HIDDEN */ #define WIFI_AP_STA_MAX_INACTIVITY (LONG_MAX - 1) +#define WIFI_AP_IEEE_80211_CAPAB_MAX_LEN 64 /** @endcond */ /** @brief Wi-Fi AP configuration parameter */ @@ -766,6 +991,242 @@ struct wifi_ap_config_params { uint32_t max_inactivity; /** Parameter used for setting maximum number of stations */ uint32_t max_num_sta; + /** Parameter used for frequency band */ + enum wifi_frequency_bandwidths bandwidth; +#if defined(CONFIG_WIFI_NM_HOSTAPD_AP) + /** Parameter used for setting HT capabilities */ + char ht_capab[WIFI_AP_IEEE_80211_CAPAB_MAX_LEN + 1]; + /** Parameter used for setting VHT capabilities */ + char vht_capab[WIFI_AP_IEEE_80211_CAPAB_MAX_LEN + 1]; +#endif +}; + +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP +/** @brief Wi-Fi DPP configuration parameter */ +/** Wi-Fi DPP QR-CODE in string max len for SHA512 */ +#define WIFI_DPP_QRCODE_MAX_LEN 255 + +/** Wi-Fi DPP operations */ +enum wifi_dpp_op { + /** Unset invalid operation */ + WIFI_DPP_OP_INVALID = 0, + /** Add configurator */ + WIFI_DPP_CONFIGURATOR_ADD, + /** Start DPP auth as configurator or enrollee */ + WIFI_DPP_AUTH_INIT, + /** Scan qr_code as parameter */ + WIFI_DPP_QR_CODE, + /** Start DPP chirp to send DPP announcement */ + WIFI_DPP_CHIRP, + /** Listen on specific frequency */ + WIFI_DPP_LISTEN, + /** Generate a bootstrap like qrcode */ + WIFI_DPP_BOOTSTRAP_GEN, + /** Get a bootstrap uri for external device to scan */ + WIFI_DPP_BOOTSTRAP_GET_URI, + /** Set configurator parameters */ + WIFI_DPP_SET_CONF_PARAM, + /** Set DPP rx response wait timeout */ + WIFI_DPP_SET_WAIT_RESP_TIME, + /** Reconfigure DPP network */ + WIFI_DPP_RECONFIG +}; + +/** Wi-Fi DPP crypto Elliptic Curves */ +enum wifi_dpp_curves { + /** Unset default use P-256 */ + WIFI_DPP_CURVES_DEFAULT = 0, + /** prime256v1 */ + WIFI_DPP_CURVES_P_256, + /** secp384r1 */ + WIFI_DPP_CURVES_P_384, + /** secp521r1 */ + WIFI_DPP_CURVES_P_512, + /** brainpoolP256r1 */ + WIFI_DPP_CURVES_BP_256, + /** brainpoolP384r1 */ + WIFI_DPP_CURVES_BP_384, + /** brainpoolP512r1 */ + WIFI_DPP_CURVES_BP_512 +}; + +/** Wi-Fi DPP role */ +enum wifi_dpp_role { + /** Unset role */ + WIFI_DPP_ROLE_UNSET = 0, + /** Configurator passes AP config to enrollee */ + WIFI_DPP_ROLE_CONFIGURATOR, + /** Enrollee gets AP config and connect to AP */ + WIFI_DPP_ROLE_ENROLLEE, + /** Both configurator and enrollee might be chosen */ + WIFI_DPP_ROLE_EITHER +}; + +/** Wi-Fi DPP security type + * + * current only support DPP only AKM + */ +enum wifi_dpp_conf { + /** Unset conf */ + WIFI_DPP_CONF_UNSET = 0, + /** conf=sta-dpp, AKM DPP only for sta */ + WIFI_DPP_CONF_STA, + /** conf=ap-dpp, AKM DPP only for ap */ + WIFI_DPP_CONF_AP, + /** conf=query, query for AKM */ + WIFI_DPP_CONF_QUERY +}; + +/** Wi-Fi DPP bootstrap type + * + * current default and only support QR-CODE + */ +enum wifi_dpp_bootstrap_type { + /** Unset type */ + WIFI_DPP_BOOTSTRAP_TYPE_UNSET = 0, + /** qrcode */ + WIFI_DPP_BOOTSTRAP_TYPE_QRCODE, + /** pkex */ + WIFI_DPP_BOOTSTRAP_TYPE_PKEX, + /** nfc */ + WIFI_DPP_BOOTSTRAP_TYPE_NFC_URI +}; + +/** Params to add DPP configurator */ +struct wifi_dpp_configurator_add_params { + /** ECP curves for private key */ + int curve; + /** ECP curves for net access key */ + int net_access_key_curve; +}; + +/** Params to initiate a DPP auth procedure */ +struct wifi_dpp_auth_init_params { + /** Peer bootstrap id */ + int peer; + /** Configuration parameter id */ + int configurator; + /** Role configurator or enrollee */ + int role; + /** Security type */ + int conf; + /** SSID in string */ + char ssid[WIFI_SSID_MAX_LEN + 1]; +}; + +/** Params to do DPP chirp */ +struct wifi_dpp_chirp_params { + /** Own bootstrap id */ + int id; + /** Chirp on frequency */ + int freq; +}; + +/** Params to do DPP listen */ +struct wifi_dpp_listen_params { + /** Listen on frequency */ + int freq; + /** Role configurator or enrollee */ + int role; +}; + +/** Params to generate a DPP bootstrap */ +struct wifi_dpp_bootstrap_gen_params { + /** Bootstrap type */ + int type; + /** Own operating class */ + int op_class; + /** Own working channel */ + int chan; + /** ECP curves */ + int curve; + /** Own mac address */ + uint8_t mac[WIFI_MAC_ADDR_LEN]; +}; + +/** Params to set specific DPP configurator */ +struct wifi_dpp_configurator_set_params { + /** Peer bootstrap id */ + int peer; + /** Configuration parameter id */ + int configurator; + /** Role configurator or enrollee */ + int role; + /** Security type */ + int conf; + /** ECP curves for private key */ + int curve; + /** ECP curves for net access key */ + int net_access_key_curve; + /** Own mac address */ + char ssid[WIFI_SSID_MAX_LEN + 1]; +}; + +/** Wi-Fi DPP params for various operations + */ +struct wifi_dpp_params { + /** Operation enum */ + int action; + union { + /** Params to add DPP configurator */ + struct wifi_dpp_configurator_add_params configurator_add; + /** Params to initiate a DPP auth procedure */ + struct wifi_dpp_auth_init_params auth_init; + /** Params to do DPP chirp */ + struct wifi_dpp_chirp_params chirp; + /** Params to do DPP listen */ + struct wifi_dpp_listen_params listen; + /** Params to generate a DPP bootstrap */ + struct wifi_dpp_bootstrap_gen_params bootstrap_gen; + /** Params to set specific DPP configurator */ + struct wifi_dpp_configurator_set_params configurator_set; + /** Bootstrap get uri id */ + int id; + /** Timeout for DPP frame response rx */ + int dpp_resp_wait_time; + /** network id for reconfig */ + int network_id; + /** DPP QR-CODE, max for SHA512 */ + uint8_t dpp_qr_code[WIFI_DPP_QRCODE_MAX_LEN + 1]; + /** Request response reusing request buffer. + * So once a request is sent, buffer will be + * fulfilled by response + */ + char resp[WIFI_DPP_QRCODE_MAX_LEN + 1]; + }; +}; +#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */ + +#define WIFI_WPS_PIN_MAX_LEN 8 + +/** Operation for WPS */ +enum wifi_wps_op { + /** WPS pbc */ + WIFI_WPS_PBC = 0, + /** Get WPS pin number */ + WIFI_WPS_PIN_GET = 1, + /** Set WPS pin number */ + WIFI_WPS_PIN_SET = 2, +}; + +/** Wi-Fi wps setup */ +struct wifi_wps_config_params { + /** wps operation */ + enum wifi_wps_op oper; + /** pin value*/ + char pin[WIFI_WPS_PIN_MAX_LEN + 1]; +}; + +/** Wi-Fi AP status + */ +enum wifi_hostapd_iface_state { + WIFI_HAPD_IFACE_UNINITIALIZED, + WIFI_HAPD_IFACE_DISABLED, + WIFI_HAPD_IFACE_COUNTRY_UPDATE, + WIFI_HAPD_IFACE_ACS, + WIFI_HAPD_IFACE_HT_SCAN, + WIFI_HAPD_IFACE_DFS, + WIFI_HAPD_IFACE_ENABLED }; #include @@ -863,7 +1324,30 @@ struct wifi_mgmt_ops { * @return 0 if ok, < 0 if error */ int (*get_stats)(const struct device *dev, struct net_stats_wifi *stats); + /** Reset Wi-Fi statistics + * + * @param dev Pointer to the device structure for the driver instance. + * + * @return 0 if ok, < 0 if error + */ + int (*reset_stats)(const struct device *dev); #endif /* CONFIG_NET_STATISTICS_WIFI */ + /** Set or get 11K status + * + * @param dev Pointer to the device structure for the driver instance. + * @param params 11k parameters + * + * @return 0 if ok, < 0 if error + */ + int (*cfg_11k)(const struct device *dev, struct wifi_11k_params *params); + /** Send 11k neighbor request + * + * @param dev Pointer to the device structure for the driver instance. + * @param params 11k parameters + * + * @return 0 if ok, < 0 if error + */ + int (*send_11k_neighbor_request)(const struct device *dev, struct wifi_11k_params *params); /** Set power save status * * @param dev Pointer to the device structure for the driver instance. @@ -920,6 +1404,16 @@ struct wifi_mgmt_ops { * @return 0 if ok, < 0 if error */ int (*channel)(const struct device *dev, struct wifi_channel_info *channel); +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM + /** Send BTM query + * + * @param dev Pointer to the device structure for the driver instance. + * @param reason query reason + * + * @return 0 if ok, < 0 if error + */ + int (*btm_query)(const struct device *dev, uint8_t reason); +#endif /** Get Version of WiFi driver and Firmware * * The driver that implements the get_version function must not use stack to allocate the @@ -933,6 +1427,14 @@ struct wifi_mgmt_ops { * @return 0 if ok, < 0 if error */ int (*get_version)(const struct device *dev, struct wifi_version *params); + /** Get Wi-Fi connection parameters recently used + * + * @param dev Pointer to the device structure for the driver instance + * @param params the Wi-Fi connection parameters recently used + * + * @return 0 if ok, < 0 if error + */ + int (*get_conn_params)(const struct device *dev, struct wifi_connect_req_params *params); /** Set RTS threshold value * * @param dev Pointer to the device structure for the driver instance. @@ -949,6 +1451,66 @@ struct wifi_mgmt_ops { * @return 0 if ok, < 0 if error */ int (*ap_config_params)(const struct device *dev, struct wifi_ap_config_params *params); + +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP + /** Dispatch DPP operations by action enum, with or without arguments in string format + * + * @param dev Pointer to the device structure for the driver instance + * @param params DPP action enum and parameters in string + * + * @return 0 if ok, < 0 if error + */ + int (*dpp_dispatch)(const struct device *dev, struct wifi_dpp_params *params); +#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */ + /** Flush PMKSA cache entries + * + * @param dev Pointer to the device structure for the driver instance. + * + * @return 0 if ok, < 0 if error + */ + int (*pmksa_flush)(const struct device *dev); + /** Set Wi-Fi enterprise mode CA/client Cert and key + * + * @param dev Pointer to the device structure for the driver instance. + * @param creds Pointer to the CA/client Cert and key. + * + * @return 0 if ok, < 0 if error + */ +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE + int (*enterprise_creds)(const struct device *dev, + struct wifi_enterprise_creds_params *creds); +#endif + /** Get RTS threshold value + * + * @param dev Pointer to the device structure for the driver instance. + * @param rts_threshold Pointer to the RTS threshold value. + * + * @return 0 if ok, < 0 if error + */ + int (*get_rts_threshold)(const struct device *dev, unsigned int *rts_threshold); + /** Start a WPS PBC/PIN connection + * + * @param dev Pointer to the device structure for the driver instance + * @param params wps operarion parameters + * + * @return 0 if ok, < 0 if error + */ + int (*wps_config)(const struct device *dev, struct wifi_wps_config_params *params); + /** Trigger candidate scan + * + * @param dev Pointer to the device structure for the driver instance + * @param params Scan parameters + * + * @return 0 if ok, < 0 if error + */ + int (*candidate_scan)(const struct device *dev, struct wifi_scan_params *params); + /** Start 11r roaming + * + * @param dev Pointer to the device structure for the driver instance + * + * @return 0 if ok, < 0 if error + */ + int (*start_11r_roaming)(const struct device *dev); }; /** Wi-Fi management offload API */ @@ -1040,6 +1602,17 @@ void wifi_mgmt_raise_raw_scan_result_event(struct net_if *iface, */ void wifi_mgmt_raise_disconnect_complete_event(struct net_if *iface, int status); +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_ROAMING +/** Wi-Fi management neighbor reports event + * + * @param iface Network interface + * @param inbuf Input buffer of neighbor reports + * @param buf_len Lenghth of input buffer + */ +void wifi_mgmt_raise_neighbor_rep_recv_event(struct net_if *iface, + char *inbuf, size_t buf_len); +#endif + /** Wi-Fi management AP mode enable result event * * @param iface Network interface diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_nm.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_nm.h index 5965513d..4c94b478 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_nm.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/wifi_nm.h @@ -22,6 +22,8 @@ /** * @brief Wi-Fi Network manager API * @defgroup wifi_nm Wi-Fi Network Manager API + * @since 3.5 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/zperf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/zperf.h index c97c9d01..4b6c50f4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/zperf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net/zperf.h @@ -10,6 +10,8 @@ * * @brief Zperf API * @defgroup zperf Zperf API + * @since 3.3 + * @version 0.8.0 * @ingroup networking * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net_buf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net_buf.h new file mode 100644 index 00000000..02c041e9 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/net_buf.h @@ -0,0 +1,2731 @@ +/** @file + * @brief Buffer management. + */ + +/* + * Copyright (c) 2015 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_NET_BUF_H_ +#define ZEPHYR_INCLUDE_NET_BUF_H_ + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Network buffer library + * @defgroup net_buf Network Buffer Library + * @since 1.0 + * @version 1.0.0 + * @ingroup os_services + * @{ + */ + +/* Alignment needed for various parts of the buffer definition */ +#if CONFIG_NET_BUF_ALIGNMENT == 0 +#define __net_buf_align __aligned(sizeof(void *)) +#else +#define __net_buf_align __aligned(CONFIG_NET_BUF_ALIGNMENT) +#endif + +/** + * @brief Define a net_buf_simple stack variable. + * + * This is a helper macro which is used to define a net_buf_simple object + * on the stack. + * + * @param _name Name of the net_buf_simple object. + * @param _size Maximum data storage for the buffer. + */ +#define NET_BUF_SIMPLE_DEFINE(_name, _size) \ + uint8_t net_buf_data_##_name[_size]; \ + struct net_buf_simple _name = { \ + .data = net_buf_data_##_name, \ + .len = 0, \ + .size = _size, \ + .__buf = net_buf_data_##_name, \ + } + +/** + * + * @brief Define a static net_buf_simple variable. + * + * This is a helper macro which is used to define a static net_buf_simple + * object. + * + * @param _name Name of the net_buf_simple object. + * @param _size Maximum data storage for the buffer. + */ +#define NET_BUF_SIMPLE_DEFINE_STATIC(_name, _size) \ + static __noinit uint8_t net_buf_data_##_name[_size]; \ + static struct net_buf_simple _name = { \ + .data = net_buf_data_##_name, \ + .len = 0, \ + .size = _size, \ + .__buf = net_buf_data_##_name, \ + } + +/** + * @brief Simple network buffer representation. + * + * This is a simpler variant of the net_buf object (in fact net_buf uses + * net_buf_simple internally). It doesn't provide any kind of reference + * counting, user data, dynamic allocation, or in general the ability to + * pass through kernel objects such as FIFOs. + * + * The main use of this is for scenarios where the meta-data of the normal + * net_buf isn't needed and causes too much overhead. This could be e.g. + * when the buffer only needs to be allocated on the stack or when the + * access to and lifetime of the buffer is well controlled and constrained. + */ +struct net_buf_simple { + /** Pointer to the start of data in the buffer. */ + uint8_t *data; + + /** + * Length of the data behind the data pointer. + * + * To determine the max length, use net_buf_simple_max_len(), not #size! + */ + uint16_t len; + + /** Amount of data that net_buf_simple#__buf can store. */ + uint16_t size; + + /** Start of the data storage. Not to be accessed directly + * (the data pointer should be used instead). + */ + uint8_t *__buf; +}; + +/** + * + * @brief Define a net_buf_simple stack variable and get a pointer to it. + * + * This is a helper macro which is used to define a net_buf_simple object on + * the stack and the get a pointer to it as follows: + * + * struct net_buf_simple *my_buf = NET_BUF_SIMPLE(10); + * + * After creating the object it needs to be initialized by calling + * net_buf_simple_init(). + * + * @param _size Maximum data storage for the buffer. + * + * @return Pointer to stack-allocated net_buf_simple object. + */ +#define NET_BUF_SIMPLE(_size) \ + ((struct net_buf_simple *)(&(struct { \ + struct net_buf_simple buf; \ + uint8_t data[_size]; \ + }) { \ + .buf.size = _size, \ + })) + +/** + * @brief Initialize a net_buf_simple object. + * + * This needs to be called after creating a net_buf_simple object using + * the NET_BUF_SIMPLE macro. + * + * @param buf Buffer to initialize. + * @param reserve_head Headroom to reserve. + */ +static inline void net_buf_simple_init(struct net_buf_simple *buf, + size_t reserve_head) +{ + if (!buf->__buf) { + buf->__buf = (uint8_t *)buf + sizeof(*buf); + } + + buf->data = buf->__buf + reserve_head; + buf->len = 0U; +} + +/** + * @brief Initialize a net_buf_simple object with data. + * + * Initialized buffer object with external data. + * + * @param buf Buffer to initialize. + * @param data External data pointer + * @param size Amount of data the pointed data buffer if able to fit. + */ +void net_buf_simple_init_with_data(struct net_buf_simple *buf, + void *data, size_t size); + +/** + * @brief Reset buffer + * + * Reset buffer data so it can be reused for other purposes. + * + * @param buf Buffer to reset. + */ +static inline void net_buf_simple_reset(struct net_buf_simple *buf) +{ + buf->len = 0U; + buf->data = buf->__buf; +} + +/** + * Clone buffer state, using the same data buffer. + * + * Initializes a buffer to point to the same data as an existing buffer. + * Allows operations on the same data without altering the length and + * offset of the original. + * + * @param original Buffer to clone. + * @param clone The new clone. + */ +void net_buf_simple_clone(const struct net_buf_simple *original, + struct net_buf_simple *clone); + +/** + * @brief Prepare data to be added at the end of the buffer + * + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param len Number of bytes to increment the length with. + * + * @return The original tail of the buffer. + */ +void *net_buf_simple_add(struct net_buf_simple *buf, size_t len); + +/** + * @brief Copy given number of bytes from memory to the end of the buffer + * + * Increments the data length of the buffer to account for more data at the + * end. + * + * @param buf Buffer to update. + * @param mem Location of data to be added. + * @param len Length of data to be added + * + * @return The original tail of the buffer. + */ +void *net_buf_simple_add_mem(struct net_buf_simple *buf, const void *mem, + size_t len); + +/** + * @brief Add (8-bit) byte at the end of the buffer + * + * Increments the data length of the buffer to account for more data at the + * end. + * + * @param buf Buffer to update. + * @param val byte value to be added. + * + * @return Pointer to the value added + */ +uint8_t *net_buf_simple_add_u8(struct net_buf_simple *buf, uint8_t val); + +/** + * @brief Add 16-bit value at the end of the buffer + * + * Adds 16-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 16-bit value to be added. + */ +void net_buf_simple_add_le16(struct net_buf_simple *buf, uint16_t val); + +/** + * @brief Add 16-bit value at the end of the buffer + * + * Adds 16-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 16-bit value to be added. + */ +void net_buf_simple_add_be16(struct net_buf_simple *buf, uint16_t val); + +/** + * @brief Add 24-bit value at the end of the buffer + * + * Adds 24-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 24-bit value to be added. + */ +void net_buf_simple_add_le24(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Add 24-bit value at the end of the buffer + * + * Adds 24-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 24-bit value to be added. + */ +void net_buf_simple_add_be24(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Add 32-bit value at the end of the buffer + * + * Adds 32-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 32-bit value to be added. + */ +void net_buf_simple_add_le32(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Add 32-bit value at the end of the buffer + * + * Adds 32-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 32-bit value to be added. + */ +void net_buf_simple_add_be32(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +void net_buf_simple_add_le40(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +void net_buf_simple_add_be40(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Add 48-bit value at the end of the buffer + * + * Adds 48-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 48-bit value to be added. + */ +void net_buf_simple_add_le48(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Add 48-bit value at the end of the buffer + * + * Adds 48-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 48-bit value to be added. + */ +void net_buf_simple_add_be48(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Add 64-bit value at the end of the buffer + * + * Adds 64-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 64-bit value to be added. + */ +void net_buf_simple_add_le64(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Add 64-bit value at the end of the buffer + * + * Adds 64-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 64-bit value to be added. + */ +void net_buf_simple_add_be64(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Remove data from the end of the buffer. + * + * Removes data from the end of the buffer by modifying the buffer length. + * + * @param buf Buffer to update. + * @param len Number of bytes to remove. + * + * @return New end of the buffer data. + */ +void *net_buf_simple_remove_mem(struct net_buf_simple *buf, size_t len); + +/** + * @brief Remove a 8-bit value from the end of the buffer + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 8-bit values. + * + * @param buf A valid pointer on a buffer. + * + * @return The 8-bit removed value + */ +uint8_t net_buf_simple_remove_u8(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 16 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 16-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from little endian to host endian. + */ +uint16_t net_buf_simple_remove_le16(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 16 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 16-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from big endian to host endian. + */ +uint16_t net_buf_simple_remove_be16(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 24 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 24-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from little endian to host endian. + */ +uint32_t net_buf_simple_remove_le24(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 24 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 24-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from big endian to host endian. + */ +uint32_t net_buf_simple_remove_be24(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 32 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 32-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 32-bit value converted from little endian to host endian. + */ +uint32_t net_buf_simple_remove_le32(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 32 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 32-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 32-bit value converted from big endian to host endian. + */ +uint32_t net_buf_simple_remove_be32(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_remove_le40(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 40-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_remove_be40(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 48 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 48-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 48-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_remove_le48(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 48 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 48-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 48-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_remove_be48(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 64 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 64-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 64-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_remove_le64(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 64 bits from the end of the buffer. + * + * Same idea as with net_buf_simple_remove_mem(), but a helper for operating + * on 64-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 64-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_remove_be64(struct net_buf_simple *buf); + +/** + * @brief Prepare data to be added to the start of the buffer + * + * Modifies the data pointer and buffer length to account for more data + * in the beginning of the buffer. + * + * @param buf Buffer to update. + * @param len Number of bytes to add to the beginning. + * + * @return The new beginning of the buffer data. + */ +void *net_buf_simple_push(struct net_buf_simple *buf, size_t len); + +/** + * @brief Copy given number of bytes from memory to the start of the buffer. + * + * Modifies the data pointer and buffer length to account for more data + * in the beginning of the buffer. + * + * @param buf Buffer to update. + * @param mem Location of data to be added. + * @param len Length of data to be added. + * + * @return The new beginning of the buffer data. + */ +void *net_buf_simple_push_mem(struct net_buf_simple *buf, const void *mem, + size_t len); + +/** + * @brief Push 16-bit value to the beginning of the buffer + * + * Adds 16-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 16-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le16(struct net_buf_simple *buf, uint16_t val); + +/** + * @brief Push 16-bit value to the beginning of the buffer + * + * Adds 16-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 16-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be16(struct net_buf_simple *buf, uint16_t val); + +/** + * @brief Push 8-bit value to the beginning of the buffer + * + * Adds 8-bit value the beginning of the buffer. + * + * @param buf Buffer to update. + * @param val 8-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_u8(struct net_buf_simple *buf, uint8_t val); + +/** + * @brief Push 24-bit value to the beginning of the buffer + * + * Adds 24-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 24-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le24(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Push 24-bit value to the beginning of the buffer + * + * Adds 24-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 24-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be24(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Push 32-bit value to the beginning of the buffer + * + * Adds 32-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 32-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le32(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Push 32-bit value to the beginning of the buffer + * + * Adds 32-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 32-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be32(struct net_buf_simple *buf, uint32_t val); + +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le40(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be40(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Push 48-bit value to the beginning of the buffer + * + * Adds 48-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 48-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le48(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Push 48-bit value to the beginning of the buffer + * + * Adds 48-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 48-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be48(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Push 64-bit value to the beginning of the buffer + * + * Adds 64-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 64-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_le64(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Push 64-bit value to the beginning of the buffer + * + * Adds 64-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 64-bit value to be pushed to the buffer. + */ +void net_buf_simple_push_be64(struct net_buf_simple *buf, uint64_t val); + +/** + * @brief Remove data from the beginning of the buffer. + * + * Removes data from the beginning of the buffer by modifying the data + * pointer and buffer length. + * + * @param buf Buffer to update. + * @param len Number of bytes to remove. + * + * @return New beginning of the buffer data. + */ +void *net_buf_simple_pull(struct net_buf_simple *buf, size_t len); + +/** + * @brief Remove data from the beginning of the buffer. + * + * Removes data from the beginning of the buffer by modifying the data + * pointer and buffer length. + * + * @param buf Buffer to update. + * @param len Number of bytes to remove. + * + * @return Pointer to the old location of the buffer data. + */ +void *net_buf_simple_pull_mem(struct net_buf_simple *buf, size_t len); + +/** + * @brief Remove a 8-bit value from the beginning of the buffer + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 8-bit values. + * + * @param buf A valid pointer on a buffer. + * + * @return The 8-bit removed value + */ +uint8_t net_buf_simple_pull_u8(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 16 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 16-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from little endian to host endian. + */ +uint16_t net_buf_simple_pull_le16(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 16 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 16-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from big endian to host endian. + */ +uint16_t net_buf_simple_pull_be16(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 24 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 24-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from little endian to host endian. + */ +uint32_t net_buf_simple_pull_le24(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 24 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 24-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from big endian to host endian. + */ +uint32_t net_buf_simple_pull_be24(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 32 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 32-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 32-bit value converted from little endian to host endian. + */ +uint32_t net_buf_simple_pull_le32(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 32 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 32-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 32-bit value converted from big endian to host endian. + */ +uint32_t net_buf_simple_pull_be32(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_pull_le40(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 40-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_pull_be40(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 48 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 48-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 48-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_pull_le48(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 48 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 48-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 48-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_pull_be48(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 64 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 64-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 64-bit value converted from little endian to host endian. + */ +uint64_t net_buf_simple_pull_le64(struct net_buf_simple *buf); + +/** + * @brief Remove and convert 64 bits from the beginning of the buffer. + * + * Same idea as with net_buf_simple_pull(), but a helper for operating + * on 64-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 64-bit value converted from big endian to host endian. + */ +uint64_t net_buf_simple_pull_be64(struct net_buf_simple *buf); + +/** + * @brief Get the tail pointer for a buffer. + * + * Get a pointer to the end of the data in a buffer. + * + * @param buf Buffer. + * + * @return Tail pointer for the buffer. + */ +static inline uint8_t *net_buf_simple_tail(const struct net_buf_simple *buf) +{ + return buf->data + buf->len; +} + +/** + * @brief Check buffer headroom. + * + * Check how much free space there is in the beginning of the buffer. + * + * buf A valid pointer on a buffer + * + * @return Number of bytes available in the beginning of the buffer. + */ +size_t net_buf_simple_headroom(const struct net_buf_simple *buf); + +/** + * @brief Check buffer tailroom. + * + * Check how much free space there is at the end of the buffer. + * + * @param buf A valid pointer on a buffer + * + * @return Number of bytes available at the end of the buffer. + */ +size_t net_buf_simple_tailroom(const struct net_buf_simple *buf); + +/** + * @brief Check maximum net_buf_simple::len value. + * + * This value is depending on the number of bytes being reserved as headroom. + * + * @param buf A valid pointer on a buffer + * + * @return Number of bytes usable behind the net_buf_simple::data pointer. + */ +uint16_t net_buf_simple_max_len(const struct net_buf_simple *buf); + +/** + * @brief Parsing state of a buffer. + * + * This is used for temporarily storing the parsing state of a buffer + * while giving control of the parsing to a routine which we don't + * control. + */ +struct net_buf_simple_state { + /** Offset of the data pointer from the beginning of the storage */ + uint16_t offset; + /** Length of data */ + uint16_t len; +}; + +/** + * @brief Save the parsing state of a buffer. + * + * Saves the parsing state of a buffer so it can be restored later. + * + * @param buf Buffer from which the state should be saved. + * @param state Storage for the state. + */ +static inline void net_buf_simple_save(const struct net_buf_simple *buf, + struct net_buf_simple_state *state) +{ + state->offset = (uint16_t)net_buf_simple_headroom(buf); + state->len = buf->len; +} + +/** + * @brief Restore the parsing state of a buffer. + * + * Restores the parsing state of a buffer from a state previously stored + * by net_buf_simple_save(). + * + * @param buf Buffer to which the state should be restored. + * @param state Stored state. + */ +static inline void net_buf_simple_restore(struct net_buf_simple *buf, + struct net_buf_simple_state *state) +{ + buf->data = buf->__buf + state->offset; + buf->len = state->len; +} + +/** + * Flag indicating that the buffer's associated data pointer, points to + * externally allocated memory. Therefore once ref goes down to zero, the + * pointed data will not need to be deallocated. This never needs to be + * explicitly set or unset by the net_buf API user. Such net_buf is + * exclusively instantiated via net_buf_alloc_with_data() function. + * Reference count mechanism however will behave the same way, and ref + * count going to 0 will free the net_buf but no the data pointer in it. + */ +#define NET_BUF_EXTERNAL_DATA BIT(0) + +/** + * @brief Network buffer representation. + * + * This struct is used to represent network buffers. Such buffers are + * normally defined through the NET_BUF_POOL_*_DEFINE() APIs and allocated + * using the net_buf_alloc() API. + */ +struct net_buf { + /** Allow placing the buffer into sys_slist_t */ + sys_snode_t node; + + /** Fragments associated with this buffer. */ + struct net_buf *frags; + + /** Reference count. */ + uint8_t ref; + + /** Bit-field of buffer flags. */ + uint8_t flags; + + /** Where the buffer should go when freed up. */ + uint8_t pool_id; + + /** Size of user data on this buffer */ + uint8_t user_data_size; + + /** Union for convenience access to the net_buf_simple members, also + * preserving the old API. + */ + union { + /* The ABI of this struct must match net_buf_simple */ + struct { + /** Pointer to the start of data in the buffer. */ + uint8_t *data; + + /** Length of the data behind the data pointer. */ + uint16_t len; + + /** Amount of data that this buffer can store. */ + uint16_t size; + + /** Start of the data storage. Not to be accessed + * directly (the data pointer should be used + * instead). + */ + uint8_t *__buf; + }; + + /** @cond INTERNAL_HIDDEN */ + struct net_buf_simple b; + /** @endcond */ + }; + + /** System metadata for this buffer. Cleared on allocation. */ + uint8_t user_data[] __net_buf_align; +}; + +/** @cond INTERNAL_HIDDEN */ + +struct net_buf_data_cb { + uint8_t * __must_check (*alloc)(struct net_buf *buf, size_t *size, + k_timeout_t timeout); + uint8_t * __must_check (*ref)(struct net_buf *buf, uint8_t *data); + void (*unref)(struct net_buf *buf, uint8_t *data); +}; + +struct net_buf_data_alloc { + const struct net_buf_data_cb *cb; + void *alloc_data; + size_t max_alloc_size; +}; + +/** @endcond */ + +/** + * @brief Network buffer pool representation. + * + * This struct is used to represent a pool of network buffers. + */ +struct net_buf_pool { + /** LIFO to place the buffer into when free */ + struct k_lifo free; + + /** To prevent concurrent access/modifications */ + struct k_spinlock lock; + + /** Number of buffers in pool */ + const uint16_t buf_count; + + /** Number of uninitialized buffers */ + uint16_t uninit_count; + + /** Size of user data allocated to this pool */ + uint8_t user_data_size; + +#if defined(CONFIG_NET_BUF_POOL_USAGE) + /** Amount of available buffers in the pool. */ + atomic_t avail_count; + + /** Total size of the pool. */ + const uint16_t pool_size; + + /** Name of the pool. Used when printing pool information. */ + const char *name; +#endif /* CONFIG_NET_BUF_POOL_USAGE */ + + /** Optional destroy callback when buffer is freed. */ + void (*const destroy)(struct net_buf *buf); + + /** Data allocation handlers. */ + const struct net_buf_data_alloc *alloc; + + /** Start of buffer storage array */ + struct net_buf * const __bufs; +}; + +/** @cond INTERNAL_HIDDEN */ +#define NET_BUF_POOL_USAGE_INIT(_pool, _count) \ + IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.avail_count = ATOMIC_INIT(_count),)) \ + IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.name = STRINGIFY(_pool),)) + +#define NET_BUF_POOL_INITIALIZER(_pool, _alloc, _bufs, _count, _ud_size, _destroy) \ + { \ + .free = Z_LIFO_INITIALIZER(_pool.free), \ + .lock = { }, \ + .buf_count = _count, \ + .uninit_count = _count, \ + .user_data_size = _ud_size, \ + NET_BUF_POOL_USAGE_INIT(_pool, _count) \ + .destroy = _destroy, \ + .alloc = _alloc, \ + .__bufs = (struct net_buf *)_bufs, \ + } + +#define _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size) \ + struct _net_buf_##_name { uint8_t b[sizeof(struct net_buf)]; \ + uint8_t ud[_ud_size]; } __net_buf_align; \ + BUILD_ASSERT(_ud_size <= UINT8_MAX); \ + BUILD_ASSERT(offsetof(struct net_buf, user_data) == \ + offsetof(struct _net_buf_##_name, ud), "Invalid offset"); \ + BUILD_ASSERT(__alignof__(struct net_buf) == \ + __alignof__(struct _net_buf_##_name), "Invalid alignment"); \ + BUILD_ASSERT(sizeof(struct _net_buf_##_name) == \ + ROUND_UP(sizeof(struct net_buf) + _ud_size, __alignof__(struct net_buf)), \ + "Size cannot be determined"); \ + static struct _net_buf_##_name _net_buf_##_name[_count] __noinit + +extern const struct net_buf_data_alloc net_buf_heap_alloc; +/** @endcond */ + +/** + * + * @brief Define a new pool for buffers using the heap for the data. + * + * Defines a net_buf_pool struct and the necessary memory storage (array of + * structs) for the needed amount of buffers. After this, the buffers can be + * accessed from the pool through net_buf_alloc. The pool is defined as a + * static variable, so if it needs to be exported outside the current module + * this needs to happen with the help of a separate pointer rather than an + * extern declaration. + * + * The data payload of the buffers will be allocated from the heap using + * k_malloc, so CONFIG_HEAP_MEM_POOL_SIZE must be set to a positive value. + * This kind of pool does not support blocking on the data allocation, so + * the timeout passed to net_buf_alloc will be always treated as K_NO_WAIT + * when trying to allocate the data. This means that allocation failures, + * i.e. NULL returns, must always be handled cleanly. + * + * If provided with a custom destroy callback, this callback is + * responsible for eventually calling net_buf_destroy() to complete the + * process of returning the buffer to the pool. + * + * @param _name Name of the pool variable. + * @param _count Number of buffers in the pool. + * @param _ud_size User data space to reserve per buffer. + * @param _destroy Optional destroy callback when buffer is freed. + */ +#define NET_BUF_POOL_HEAP_DEFINE(_name, _count, _ud_size, _destroy) \ + _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size); \ + static STRUCT_SECTION_ITERABLE(net_buf_pool, _name) = \ + NET_BUF_POOL_INITIALIZER(_name, &net_buf_heap_alloc, \ + _net_buf_##_name, _count, _ud_size, \ + _destroy) + +/** @cond INTERNAL_HIDDEN */ + +struct net_buf_pool_fixed { + uint8_t *data_pool; +}; + +extern const struct net_buf_data_cb net_buf_fixed_cb; + +/** @endcond */ + +/** + * + * @brief Define a new pool for buffers based on fixed-size data + * + * Defines a net_buf_pool struct and the necessary memory storage (array of + * structs) for the needed amount of buffers. After this, the buffers can be + * accessed from the pool through net_buf_alloc. The pool is defined as a + * static variable, so if it needs to be exported outside the current module + * this needs to happen with the help of a separate pointer rather than an + * extern declaration. + * + * The data payload of the buffers will be allocated from a byte array + * of fixed sized chunks. This kind of pool does not support blocking on + * the data allocation, so the timeout passed to net_buf_alloc will be + * always treated as K_NO_WAIT when trying to allocate the data. This means + * that allocation failures, i.e. NULL returns, must always be handled + * cleanly. + * + * If provided with a custom destroy callback, this callback is + * responsible for eventually calling net_buf_destroy() to complete the + * process of returning the buffer to the pool. + * + * @param _name Name of the pool variable. + * @param _count Number of buffers in the pool. + * @param _data_size Maximum data payload per buffer. + * @param _ud_size User data space to reserve per buffer. + * @param _destroy Optional destroy callback when buffer is freed. + */ +#define NET_BUF_POOL_FIXED_DEFINE(_name, _count, _data_size, _ud_size, _destroy) \ + _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size); \ + static uint8_t __noinit net_buf_data_##_name[_count][_data_size] __net_buf_align; \ + static const struct net_buf_pool_fixed net_buf_fixed_##_name = { \ + .data_pool = (uint8_t *)net_buf_data_##_name, \ + }; \ + static const struct net_buf_data_alloc net_buf_fixed_alloc_##_name = { \ + .cb = &net_buf_fixed_cb, \ + .alloc_data = (void *)&net_buf_fixed_##_name, \ + .max_alloc_size = _data_size, \ + }; \ + static STRUCT_SECTION_ITERABLE(net_buf_pool, _name) = \ + NET_BUF_POOL_INITIALIZER(_name, &net_buf_fixed_alloc_##_name, \ + _net_buf_##_name, _count, _ud_size, \ + _destroy) + +/** @cond INTERNAL_HIDDEN */ +extern const struct net_buf_data_cb net_buf_var_cb; +/** @endcond */ + +/** + * + * @brief Define a new pool for buffers with variable size payloads + * + * Defines a net_buf_pool struct and the necessary memory storage (array of + * structs) for the needed amount of buffers. After this, the buffers can be + * accessed from the pool through net_buf_alloc. The pool is defined as a + * static variable, so if it needs to be exported outside the current module + * this needs to happen with the help of a separate pointer rather than an + * extern declaration. + * + * The data payload of the buffers will be based on a memory pool from which + * variable size payloads may be allocated. + * + * If provided with a custom destroy callback, this callback is + * responsible for eventually calling net_buf_destroy() to complete the + * process of returning the buffer to the pool. + * + * @param _name Name of the pool variable. + * @param _count Number of buffers in the pool. + * @param _data_size Total amount of memory available for data payloads. + * @param _ud_size User data space to reserve per buffer. + * @param _destroy Optional destroy callback when buffer is freed. + */ +#define NET_BUF_POOL_VAR_DEFINE(_name, _count, _data_size, _ud_size, _destroy) \ + _NET_BUF_ARRAY_DEFINE(_name, _count, _ud_size); \ + K_HEAP_DEFINE(net_buf_mem_pool_##_name, _data_size); \ + static const struct net_buf_data_alloc net_buf_data_alloc_##_name = { \ + .cb = &net_buf_var_cb, \ + .alloc_data = &net_buf_mem_pool_##_name, \ + .max_alloc_size = 0, \ + }; \ + static STRUCT_SECTION_ITERABLE(net_buf_pool, _name) = \ + NET_BUF_POOL_INITIALIZER(_name, &net_buf_data_alloc_##_name, \ + _net_buf_##_name, _count, _ud_size, \ + _destroy) + +/** + * + * @brief Define a new pool for buffers + * + * Defines a net_buf_pool struct and the necessary memory storage (array of + * structs) for the needed amount of buffers. After this,the buffers can be + * accessed from the pool through net_buf_alloc. The pool is defined as a + * static variable, so if it needs to be exported outside the current module + * this needs to happen with the help of a separate pointer rather than an + * extern declaration. + * + * If provided with a custom destroy callback this callback is + * responsible for eventually calling net_buf_destroy() to complete the + * process of returning the buffer to the pool. + * + * @param _name Name of the pool variable. + * @param _count Number of buffers in the pool. + * @param _size Maximum data size for each buffer. + * @param _ud_size Amount of user data space to reserve. + * @param _destroy Optional destroy callback when buffer is freed. + */ +#define NET_BUF_POOL_DEFINE(_name, _count, _size, _ud_size, _destroy) \ + NET_BUF_POOL_FIXED_DEFINE(_name, _count, _size, _ud_size, _destroy) + +/** + * @brief Looks up a pool based on its ID. + * + * @param id Pool ID (e.g. from buf->pool_id). + * + * @return Pointer to pool. + */ +struct net_buf_pool *net_buf_pool_get(int id); + +/** + * @brief Get a zero-based index for a buffer. + * + * This function will translate a buffer into a zero-based index, + * based on its placement in its buffer pool. This can be useful if you + * want to associate an external array of meta-data contexts with the + * buffers of a pool. + * + * @param buf Network buffer. + * + * @return Zero-based index for the buffer. + */ +int net_buf_id(const struct net_buf *buf); + +/** + * @brief Allocate a new fixed buffer from a pool. + * + * @note Some types of data allocators do not support + * blocking (such as the HEAP type). In this case it's still possible + * for net_buf_alloc() to fail (return NULL) even if it was given + * K_FOREVER. + * + * @note The timeout value will be overridden to K_NO_WAIT if called from the + * system workqueue. + * + * @param pool Which pool to allocate the buffer from. + * @param timeout Affects the action taken should the pool be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then + * wait as long as necessary. Otherwise, wait until the specified + * timeout. + * + * @return New buffer or NULL if out of buffers. + */ +#if defined(CONFIG_NET_BUF_LOG) +struct net_buf * __must_check net_buf_alloc_fixed_debug(struct net_buf_pool *pool, + k_timeout_t timeout, + const char *func, + int line); +#define net_buf_alloc_fixed(_pool, _timeout) \ + net_buf_alloc_fixed_debug(_pool, _timeout, __func__, __LINE__) +#else +struct net_buf * __must_check net_buf_alloc_fixed(struct net_buf_pool *pool, + k_timeout_t timeout); +#endif + +/** + * @copydetails net_buf_alloc_fixed + */ +static inline struct net_buf * __must_check net_buf_alloc(struct net_buf_pool *pool, + k_timeout_t timeout) +{ + return net_buf_alloc_fixed(pool, timeout); +} + +/** + * @brief Allocate a new variable length buffer from a pool. + * + * @note Some types of data allocators do not support + * blocking (such as the HEAP type). In this case it's still possible + * for net_buf_alloc() to fail (return NULL) even if it was given + * K_FOREVER. + * + * @note The timeout value will be overridden to K_NO_WAIT if called from the + * system workqueue. + * + * @param pool Which pool to allocate the buffer from. + * @param size Amount of data the buffer must be able to fit. + * @param timeout Affects the action taken should the pool be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then + * wait as long as necessary. Otherwise, wait until the specified + * timeout. + * + * @return New buffer or NULL if out of buffers. + */ +#if defined(CONFIG_NET_BUF_LOG) +struct net_buf * __must_check net_buf_alloc_len_debug(struct net_buf_pool *pool, + size_t size, + k_timeout_t timeout, + const char *func, + int line); +#define net_buf_alloc_len(_pool, _size, _timeout) \ + net_buf_alloc_len_debug(_pool, _size, _timeout, __func__, __LINE__) +#else +struct net_buf * __must_check net_buf_alloc_len(struct net_buf_pool *pool, + size_t size, + k_timeout_t timeout); +#endif + +/** + * @brief Allocate a new buffer from a pool but with external data pointer. + * + * Allocate a new buffer from a pool, where the data pointer comes from the + * user and not from the pool. + * + * @note Some types of data allocators do not support + * blocking (such as the HEAP type). In this case it's still possible + * for net_buf_alloc() to fail (return NULL) even if it was given + * K_FOREVER. + * + * @note The timeout value will be overridden to K_NO_WAIT if called from the + * system workqueue. + * + * @param pool Which pool to allocate the buffer from. + * @param data External data pointer + * @param size Amount of data the pointed data buffer if able to fit. + * @param timeout Affects the action taken should the pool be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then + * wait as long as necessary. Otherwise, wait until the specified + * timeout. + * + * @return New buffer or NULL if out of buffers. + */ +#if defined(CONFIG_NET_BUF_LOG) +struct net_buf * __must_check net_buf_alloc_with_data_debug(struct net_buf_pool *pool, + void *data, size_t size, + k_timeout_t timeout, + const char *func, int line); +#define net_buf_alloc_with_data(_pool, _data_, _size, _timeout) \ + net_buf_alloc_with_data_debug(_pool, _data_, _size, _timeout, \ + __func__, __LINE__) +#else +struct net_buf * __must_check net_buf_alloc_with_data(struct net_buf_pool *pool, + void *data, size_t size, + k_timeout_t timeout); +#endif + +/** + * @brief Get a buffer from a FIFO. + * + * @deprecated Use @a k_fifo_get() instead. + * + * @param fifo Which FIFO to take the buffer from. + * @param timeout Affects the action taken should the FIFO be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then wait as + * long as necessary. Otherwise, wait until the specified timeout. + * + * @return New buffer or NULL if the FIFO is empty. + */ +#if defined(CONFIG_NET_BUF_LOG) +__deprecated struct net_buf * __must_check net_buf_get_debug(struct k_fifo *fifo, + k_timeout_t timeout, + const char *func, int line); +#define net_buf_get(_fifo, _timeout) \ + net_buf_get_debug(_fifo, _timeout, __func__, __LINE__) +#else +__deprecated struct net_buf * __must_check net_buf_get(struct k_fifo *fifo, + k_timeout_t timeout); +#endif + +/** + * @brief Destroy buffer from custom destroy callback + * + * This helper is only intended to be used from custom destroy callbacks. + * If no custom destroy callback is given to NET_BUF_POOL_*_DEFINE() then + * there is no need to use this API. + * + * @param buf Buffer to destroy. + */ +static inline void net_buf_destroy(struct net_buf *buf) +{ + struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); + + if (buf->__buf) { + if (!(buf->flags & NET_BUF_EXTERNAL_DATA)) { + pool->alloc->cb->unref(buf, buf->__buf); + } + buf->__buf = NULL; + } + + k_lifo_put(&pool->free, buf); +} + +/** + * @brief Reset buffer + * + * Reset buffer data and flags so it can be reused for other purposes. + * + * @param buf Buffer to reset. + */ +void net_buf_reset(struct net_buf *buf); + +/** + * @brief Initialize buffer with the given headroom. + * + * The buffer is not expected to contain any data when this API is called. + * + * @param buf Buffer to initialize. + * @param reserve How much headroom to reserve. + */ +void net_buf_simple_reserve(struct net_buf_simple *buf, size_t reserve); + +/** + * @brief Put a buffer into a list + * + * @param list Which list to append the buffer to. + * @param buf Buffer. + */ +void net_buf_slist_put(sys_slist_t *list, struct net_buf *buf); + +/** + * @brief Get a buffer from a list. + * + * @param list Which list to take the buffer from. + * + * @return New buffer or NULL if the FIFO is empty. + */ +struct net_buf * __must_check net_buf_slist_get(sys_slist_t *list); + +/** + * @brief Put a buffer to the end of a FIFO. + * + * @deprecated Use @a k_fifo_put() instead. + * + * @param fifo Which FIFO to put the buffer to. + * @param buf Buffer. + */ +__deprecated void net_buf_put(struct k_fifo *fifo, struct net_buf *buf); + +/** + * @brief Decrements the reference count of a buffer. + * + * The buffer is put back into the pool if the reference count reaches zero. + * + * @param buf A valid pointer on a buffer + */ +#if defined(CONFIG_NET_BUF_LOG) +void net_buf_unref_debug(struct net_buf *buf, const char *func, int line); +#define net_buf_unref(_buf) \ + net_buf_unref_debug(_buf, __func__, __LINE__) +#else +void net_buf_unref(struct net_buf *buf); +#endif + +/** + * @brief Increment the reference count of a buffer. + * + * @param buf A valid pointer on a buffer + * + * @return the buffer newly referenced + */ +struct net_buf * __must_check net_buf_ref(struct net_buf *buf); + +/** + * @brief Clone buffer + * + * Duplicate given buffer including any (user) data and headers currently stored. + * + * @param buf A valid pointer on a buffer + * @param timeout Affects the action taken should the pool be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then + * wait as long as necessary. Otherwise, wait until the specified + * timeout. + * + * @return Cloned buffer or NULL if out of buffers. + */ +struct net_buf * __must_check net_buf_clone(struct net_buf *buf, + k_timeout_t timeout); + +/** + * @brief Get a pointer to the user data of a buffer. + * + * @param buf A valid pointer on a buffer + * + * @return Pointer to the user data of the buffer. + */ +static inline void * __must_check net_buf_user_data(const struct net_buf *buf) +{ + return (void *)buf->user_data; +} + +/** + * @brief Copy user data from one to another buffer. + * + * @param dst A valid pointer to a buffer gettings its user data overwritten. + * @param src A valid pointer to a buffer gettings its user data copied. User data size must be + * equal to or exceed @a dst. + * + * @return 0 on success or negative error number on failure. + */ +int net_buf_user_data_copy(struct net_buf *dst, const struct net_buf *src); + +/** + * @brief Initialize buffer with the given headroom. + * + * The buffer is not expected to contain any data when this API is called. + * + * @param buf Buffer to initialize. + * @param reserve How much headroom to reserve. + */ +static inline void net_buf_reserve(struct net_buf *buf, size_t reserve) +{ + net_buf_simple_reserve(&buf->b, reserve); +} + +/** + * @brief Prepare data to be added at the end of the buffer + * + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param len Number of bytes to increment the length with. + * + * @return The original tail of the buffer. + */ +static inline void *net_buf_add(struct net_buf *buf, size_t len) +{ + return net_buf_simple_add(&buf->b, len); +} + +/** + * @brief Copies the given number of bytes to the end of the buffer + * + * Increments the data length of the buffer to account for more data at + * the end. + * + * @param buf Buffer to update. + * @param mem Location of data to be added. + * @param len Length of data to be added + * + * @return The original tail of the buffer. + */ +static inline void *net_buf_add_mem(struct net_buf *buf, const void *mem, + size_t len) +{ + return net_buf_simple_add_mem(&buf->b, mem, len); +} + +/** + * @brief Add (8-bit) byte at the end of the buffer + * + * Increments the data length of the buffer to account for more data at + * the end. + * + * @param buf Buffer to update. + * @param val byte value to be added. + * + * @return Pointer to the value added + */ +static inline uint8_t *net_buf_add_u8(struct net_buf *buf, uint8_t val) +{ + return net_buf_simple_add_u8(&buf->b, val); +} + +/** + * @brief Add 16-bit value at the end of the buffer + * + * Adds 16-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 16-bit value to be added. + */ +static inline void net_buf_add_le16(struct net_buf *buf, uint16_t val) +{ + net_buf_simple_add_le16(&buf->b, val); +} + +/** + * @brief Add 16-bit value at the end of the buffer + * + * Adds 16-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 16-bit value to be added. + */ +static inline void net_buf_add_be16(struct net_buf *buf, uint16_t val) +{ + net_buf_simple_add_be16(&buf->b, val); +} + +/** + * @brief Add 24-bit value at the end of the buffer + * + * Adds 24-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 24-bit value to be added. + */ +static inline void net_buf_add_le24(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_add_le24(&buf->b, val); +} + +/** + * @brief Add 24-bit value at the end of the buffer + * + * Adds 24-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 24-bit value to be added. + */ +static inline void net_buf_add_be24(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_add_be24(&buf->b, val); +} + +/** + * @brief Add 32-bit value at the end of the buffer + * + * Adds 32-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 32-bit value to be added. + */ +static inline void net_buf_add_le32(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_add_le32(&buf->b, val); +} + +/** + * @brief Add 32-bit value at the end of the buffer + * + * Adds 32-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 32-bit value to be added. + */ +static inline void net_buf_add_be32(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_add_be32(&buf->b, val); +} + +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +static inline void net_buf_add_le40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_le40(&buf->b, val); +} + +/** + * @brief Add 40-bit value at the end of the buffer + * + * Adds 40-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 40-bit value to be added. + */ +static inline void net_buf_add_be40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_be40(&buf->b, val); +} + +/** + * @brief Add 48-bit value at the end of the buffer + * + * Adds 48-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 48-bit value to be added. + */ +static inline void net_buf_add_le48(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_le48(&buf->b, val); +} + +/** + * @brief Add 48-bit value at the end of the buffer + * + * Adds 48-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 48-bit value to be added. + */ +static inline void net_buf_add_be48(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_be48(&buf->b, val); +} + +/** + * @brief Add 64-bit value at the end of the buffer + * + * Adds 64-bit value in little endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 64-bit value to be added. + */ +static inline void net_buf_add_le64(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_le64(&buf->b, val); +} + +/** + * @brief Add 64-bit value at the end of the buffer + * + * Adds 64-bit value in big endian format at the end of buffer. + * Increments the data length of a buffer to account for more data + * at the end. + * + * @param buf Buffer to update. + * @param val 64-bit value to be added. + */ +static inline void net_buf_add_be64(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_add_be64(&buf->b, val); +} + +/** + * @brief Remove data from the end of the buffer. + * + * Removes data from the end of the buffer by modifying the buffer length. + * + * @param buf Buffer to update. + * @param len Number of bytes to remove. + * + * @return New end of the buffer data. + */ +static inline void *net_buf_remove_mem(struct net_buf *buf, size_t len) +{ + return net_buf_simple_remove_mem(&buf->b, len); +} + +/** + * @brief Remove a 8-bit value from the end of the buffer + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 8-bit values. + * + * @param buf A valid pointer on a buffer. + * + * @return The 8-bit removed value + */ +static inline uint8_t net_buf_remove_u8(struct net_buf *buf) +{ + return net_buf_simple_remove_u8(&buf->b); +} + +/** + * @brief Remove and convert 16 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 16-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from little endian to host endian. + */ +static inline uint16_t net_buf_remove_le16(struct net_buf *buf) +{ + return net_buf_simple_remove_le16(&buf->b); +} + +/** + * @brief Remove and convert 16 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 16-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from big endian to host endian. + */ +static inline uint16_t net_buf_remove_be16(struct net_buf *buf) +{ + return net_buf_simple_remove_be16(&buf->b); +} + +/** + * @brief Remove and convert 24 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 24-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from big endian to host endian. + */ +static inline uint32_t net_buf_remove_be24(struct net_buf *buf) +{ + return net_buf_simple_remove_be24(&buf->b); +} + +/** + * @brief Remove and convert 24 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 24-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from little endian to host endian. + */ +static inline uint32_t net_buf_remove_le24(struct net_buf *buf) +{ + return net_buf_simple_remove_le24(&buf->b); +} + +/** + * @brief Remove and convert 32 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 32-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 32-bit value converted from little endian to host endian. + */ +static inline uint32_t net_buf_remove_le32(struct net_buf *buf) +{ + return net_buf_simple_remove_le32(&buf->b); +} + +/** + * @brief Remove and convert 32 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 32-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 32-bit value converted from big endian to host endian. + */ +static inline uint32_t net_buf_remove_be32(struct net_buf *buf) +{ + return net_buf_simple_remove_be32(&buf->b); +} + +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_remove_le40(struct net_buf *buf) +{ + return net_buf_simple_remove_le40(&buf->b); +} + +/** + * @brief Remove and convert 40 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 40-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 40-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_remove_be40(struct net_buf *buf) +{ + return net_buf_simple_remove_be40(&buf->b); +} + +/** + * @brief Remove and convert 48 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 48-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 48-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_remove_le48(struct net_buf *buf) +{ + return net_buf_simple_remove_le48(&buf->b); +} + +/** + * @brief Remove and convert 48 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 48-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 48-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_remove_be48(struct net_buf *buf) +{ + return net_buf_simple_remove_be48(&buf->b); +} + +/** + * @brief Remove and convert 64 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 64-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 64-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_remove_le64(struct net_buf *buf) +{ + return net_buf_simple_remove_le64(&buf->b); +} + +/** + * @brief Remove and convert 64 bits from the end of the buffer. + * + * Same idea as with net_buf_remove_mem(), but a helper for operating on + * 64-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 64-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_remove_be64(struct net_buf *buf) +{ + return net_buf_simple_remove_be64(&buf->b); +} + +/** + * @brief Prepare data to be added at the start of the buffer + * + * Modifies the data pointer and buffer length to account for more data + * in the beginning of the buffer. + * + * @param buf Buffer to update. + * @param len Number of bytes to add to the beginning. + * + * @return The new beginning of the buffer data. + */ +static inline void *net_buf_push(struct net_buf *buf, size_t len) +{ + return net_buf_simple_push(&buf->b, len); +} + +/** + * @brief Copies the given number of bytes to the start of the buffer + * + * Modifies the data pointer and buffer length to account for more data + * in the beginning of the buffer. + * + * @param buf Buffer to update. + * @param mem Location of data to be added. + * @param len Length of data to be added. + * + * @return The new beginning of the buffer data. + */ +static inline void *net_buf_push_mem(struct net_buf *buf, const void *mem, + size_t len) +{ + return net_buf_simple_push_mem(&buf->b, mem, len); +} + +/** + * @brief Push 8-bit value to the beginning of the buffer + * + * Adds 8-bit value the beginning of the buffer. + * + * @param buf Buffer to update. + * @param val 8-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_u8(struct net_buf *buf, uint8_t val) +{ + net_buf_simple_push_u8(&buf->b, val); +} + +/** + * @brief Push 16-bit value to the beginning of the buffer + * + * Adds 16-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 16-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le16(struct net_buf *buf, uint16_t val) +{ + net_buf_simple_push_le16(&buf->b, val); +} + +/** + * @brief Push 16-bit value to the beginning of the buffer + * + * Adds 16-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 16-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be16(struct net_buf *buf, uint16_t val) +{ + net_buf_simple_push_be16(&buf->b, val); +} + +/** + * @brief Push 24-bit value to the beginning of the buffer + * + * Adds 24-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 24-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le24(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_push_le24(&buf->b, val); +} + +/** + * @brief Push 24-bit value to the beginning of the buffer + * + * Adds 24-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 24-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be24(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_push_be24(&buf->b, val); +} + +/** + * @brief Push 32-bit value to the beginning of the buffer + * + * Adds 32-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 32-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le32(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_push_le32(&buf->b, val); +} + +/** + * @brief Push 32-bit value to the beginning of the buffer + * + * Adds 32-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 32-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be32(struct net_buf *buf, uint32_t val) +{ + net_buf_simple_push_be32(&buf->b, val); +} + +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_le40(&buf->b, val); +} + +/** + * @brief Push 40-bit value to the beginning of the buffer + * + * Adds 40-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 40-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be40(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_be40(&buf->b, val); +} + +/** + * @brief Push 48-bit value to the beginning of the buffer + * + * Adds 48-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 48-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le48(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_le48(&buf->b, val); +} + +/** + * @brief Push 48-bit value to the beginning of the buffer + * + * Adds 48-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 48-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be48(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_be48(&buf->b, val); +} + +/** + * @brief Push 64-bit value to the beginning of the buffer + * + * Adds 64-bit value in little endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 64-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_le64(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_le64(&buf->b, val); +} + +/** + * @brief Push 64-bit value to the beginning of the buffer + * + * Adds 64-bit value in big endian format to the beginning of the + * buffer. + * + * @param buf Buffer to update. + * @param val 64-bit value to be pushed to the buffer. + */ +static inline void net_buf_push_be64(struct net_buf *buf, uint64_t val) +{ + net_buf_simple_push_be64(&buf->b, val); +} + +/** + * @brief Remove data from the beginning of the buffer. + * + * Removes data from the beginning of the buffer by modifying the data + * pointer and buffer length. + * + * @param buf Buffer to update. + * @param len Number of bytes to remove. + * + * @return New beginning of the buffer data. + */ +static inline void *net_buf_pull(struct net_buf *buf, size_t len) +{ + return net_buf_simple_pull(&buf->b, len); +} + +/** + * @brief Remove data from the beginning of the buffer. + * + * Removes data from the beginning of the buffer by modifying the data + * pointer and buffer length. + * + * @param buf Buffer to update. + * @param len Number of bytes to remove. + * + * @return Pointer to the old beginning of the buffer data. + */ +static inline void *net_buf_pull_mem(struct net_buf *buf, size_t len) +{ + return net_buf_simple_pull_mem(&buf->b, len); +} + +/** + * @brief Remove a 8-bit value from the beginning of the buffer + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 8-bit values. + * + * @param buf A valid pointer on a buffer. + * + * @return The 8-bit removed value + */ +static inline uint8_t net_buf_pull_u8(struct net_buf *buf) +{ + return net_buf_simple_pull_u8(&buf->b); +} + +/** + * @brief Remove and convert 16 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 16-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from little endian to host endian. + */ +static inline uint16_t net_buf_pull_le16(struct net_buf *buf) +{ + return net_buf_simple_pull_le16(&buf->b); +} + +/** + * @brief Remove and convert 16 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 16-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 16-bit value converted from big endian to host endian. + */ +static inline uint16_t net_buf_pull_be16(struct net_buf *buf) +{ + return net_buf_simple_pull_be16(&buf->b); +} + +/** + * @brief Remove and convert 24 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 24-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from little endian to host endian. + */ +static inline uint32_t net_buf_pull_le24(struct net_buf *buf) +{ + return net_buf_simple_pull_le24(&buf->b); +} + +/** + * @brief Remove and convert 24 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 24-bit big endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 24-bit value converted from big endian to host endian. + */ +static inline uint32_t net_buf_pull_be24(struct net_buf *buf) +{ + return net_buf_simple_pull_be24(&buf->b); +} + +/** + * @brief Remove and convert 32 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 32-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 32-bit value converted from little endian to host endian. + */ +static inline uint32_t net_buf_pull_le32(struct net_buf *buf) +{ + return net_buf_simple_pull_le32(&buf->b); +} + +/** + * @brief Remove and convert 32 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 32-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 32-bit value converted from big endian to host endian. + */ +static inline uint32_t net_buf_pull_be32(struct net_buf *buf) +{ + return net_buf_simple_pull_be32(&buf->b); +} + +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 40-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 40-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_pull_le40(struct net_buf *buf) +{ + return net_buf_simple_pull_le40(&buf->b); +} + +/** + * @brief Remove and convert 40 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 40-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 40-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_pull_be40(struct net_buf *buf) +{ + return net_buf_simple_pull_be40(&buf->b); +} + +/** + * @brief Remove and convert 48 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 48-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 48-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_pull_le48(struct net_buf *buf) +{ + return net_buf_simple_pull_le48(&buf->b); +} + +/** + * @brief Remove and convert 48 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 48-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 48-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_pull_be48(struct net_buf *buf) +{ + return net_buf_simple_pull_be48(&buf->b); +} + +/** + * @brief Remove and convert 64 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 64-bit little endian data. + * + * @param buf A valid pointer on a buffer. + * + * @return 64-bit value converted from little endian to host endian. + */ +static inline uint64_t net_buf_pull_le64(struct net_buf *buf) +{ + return net_buf_simple_pull_le64(&buf->b); +} + +/** + * @brief Remove and convert 64 bits from the beginning of the buffer. + * + * Same idea as with net_buf_pull(), but a helper for operating on + * 64-bit big endian data. + * + * @param buf A valid pointer on a buffer + * + * @return 64-bit value converted from big endian to host endian. + */ +static inline uint64_t net_buf_pull_be64(struct net_buf *buf) +{ + return net_buf_simple_pull_be64(&buf->b); +} + +/** + * @brief Check buffer tailroom. + * + * Check how much free space there is at the end of the buffer. + * + * @param buf A valid pointer on a buffer + * + * @return Number of bytes available at the end of the buffer. + */ +static inline size_t net_buf_tailroom(const struct net_buf *buf) +{ + return net_buf_simple_tailroom(&buf->b); +} + +/** + * @brief Check buffer headroom. + * + * Check how much free space there is in the beginning of the buffer. + * + * buf A valid pointer on a buffer + * + * @return Number of bytes available in the beginning of the buffer. + */ +static inline size_t net_buf_headroom(const struct net_buf *buf) +{ + return net_buf_simple_headroom(&buf->b); +} + +/** + * @brief Check maximum net_buf::len value. + * + * This value is depending on the number of bytes being reserved as headroom. + * + * @param buf A valid pointer on a buffer + * + * @return Number of bytes usable behind the net_buf::data pointer. + */ +static inline uint16_t net_buf_max_len(const struct net_buf *buf) +{ + return net_buf_simple_max_len(&buf->b); +} + +/** + * @brief Get the tail pointer for a buffer. + * + * Get a pointer to the end of the data in a buffer. + * + * @param buf Buffer. + * + * @return Tail pointer for the buffer. + */ +static inline uint8_t *net_buf_tail(const struct net_buf *buf) +{ + return net_buf_simple_tail(&buf->b); +} + +/** + * @brief Find the last fragment in the fragment list. + * + * @return Pointer to last fragment in the list. + */ +struct net_buf *net_buf_frag_last(struct net_buf *frags); + +/** + * @brief Insert a new fragment to a chain of bufs. + * + * Insert a new fragment into the buffer fragments list after the parent. + * + * Note: This function takes ownership of the fragment reference so the + * caller is not required to unref. + * + * @param parent Parent buffer/fragment. + * @param frag Fragment to insert. + */ +void net_buf_frag_insert(struct net_buf *parent, struct net_buf *frag); + +/** + * @brief Add a new fragment to the end of a chain of bufs. + * + * Append a new fragment into the buffer fragments list. + * + * Note: This function takes ownership of the fragment reference so the + * caller is not required to unref. + * + * @param head Head of the fragment chain. + * @param frag Fragment to add. + * + * @return New head of the fragment chain. Either head (if head + * was non-NULL) or frag (if head was NULL). + */ +struct net_buf *net_buf_frag_add(struct net_buf *head, struct net_buf *frag); + +/** + * @brief Delete existing fragment from a chain of bufs. + * + * @param parent Parent buffer/fragment, or NULL if there is no parent. + * @param frag Fragment to delete. + * + * @return Pointer to the buffer following the fragment, or NULL if it + * had no further fragments. + */ +#if defined(CONFIG_NET_BUF_LOG) +struct net_buf *net_buf_frag_del_debug(struct net_buf *parent, + struct net_buf *frag, + const char *func, int line); +#define net_buf_frag_del(_parent, _frag) \ + net_buf_frag_del_debug(_parent, _frag, __func__, __LINE__) +#else +struct net_buf *net_buf_frag_del(struct net_buf *parent, struct net_buf *frag); +#endif + +/** + * @brief Copy bytes from net_buf chain starting at offset to linear buffer + * + * Copy (extract) @a len bytes from @a src net_buf chain, starting from @a + * offset in it, to a linear buffer @a dst. Return number of bytes actually + * copied, which may be less than requested, if net_buf chain doesn't have + * enough data, or destination buffer is too small. + * + * @param dst Destination buffer + * @param dst_len Destination buffer length + * @param src Source net_buf chain + * @param offset Starting offset to copy from + * @param len Number of bytes to copy + * @return number of bytes actually copied + */ +size_t net_buf_linearize(void *dst, size_t dst_len, + const struct net_buf *src, size_t offset, size_t len); + +/** + * @typedef net_buf_allocator_cb + * @brief Network buffer allocator callback. + * + * @details The allocator callback is called when net_buf_append_bytes + * needs to allocate a new net_buf. + * + * @param timeout Affects the action taken should the net buf pool be empty. + * If K_NO_WAIT, then return immediately. If K_FOREVER, then + * wait as long as necessary. Otherwise, wait until the specified + * timeout. + * @param user_data The user data given in net_buf_append_bytes call. + * @return pointer to allocated net_buf or NULL on error. + */ +typedef struct net_buf * __must_check (*net_buf_allocator_cb)(k_timeout_t timeout, + void *user_data); + +/** + * @brief Append data to a list of net_buf + * + * @details Append data to a net_buf. If there is not enough space in the + * net_buf then more net_buf will be added, unless there are no free net_buf + * and timeout occurs. If not allocator is provided it attempts to allocate from + * the same pool as the original buffer. + * + * @param buf Network buffer. + * @param len Total length of input data + * @param value Data to be added + * @param timeout Timeout is passed to the net_buf allocator callback. + * @param allocate_cb When a new net_buf is required, use this callback. + * @param user_data A user data pointer to be supplied to the allocate_cb. + * This pointer is can be anything from a mem_pool or a net_pkt, the + * logic is left up to the allocate_cb function. + * + * @return Length of data actually added. This may be less than input + * length if other timeout than K_FOREVER was used, and there + * were no free fragments in a pool to accommodate all data. + */ +size_t net_buf_append_bytes(struct net_buf *buf, size_t len, + const void *value, k_timeout_t timeout, + net_buf_allocator_cb allocate_cb, void *user_data); + +/** + * @brief Match data with a net_buf's content + * + * @details Compare data with a content of a net_buf. Provide information about + * the number of bytes matching between both. If needed, traverse + * through multiple buffer fragments. + * + * @param buf Network buffer + * @param offset Starting offset to compare from + * @param data Data buffer for comparison + * @param len Number of bytes to compare + * + * @return The number of bytes compared before the first difference. + */ +size_t net_buf_data_match(const struct net_buf *buf, size_t offset, const void *data, size_t len); + +/** + * @brief Skip N number of bytes in a net_buf + * + * @details Skip N number of bytes starting from fragment's offset. If the total + * length of data is placed in multiple fragments, this function will skip from + * all fragments until it reaches N number of bytes. Any fully skipped buffers + * are removed from the net_buf list. + * + * @param buf Network buffer. + * @param len Total length of data to be skipped. + * + * @return Pointer to the fragment or + * NULL and pos is 0 after successful skip, + * NULL and pos is 0xffff otherwise. + */ +static inline struct net_buf *net_buf_skip(struct net_buf *buf, size_t len) +{ + while (buf && len--) { + net_buf_pull_u8(buf); + if (!buf->len) { + buf = net_buf_frag_del(NULL, buf); + } + } + + return buf; +} + +/** + * @brief Calculate amount of bytes stored in fragments. + * + * Calculates the total amount of data stored in the given buffer and the + * fragments linked to it. + * + * @param buf Buffer to start off with. + * + * @return Number of bytes in the buffer and its fragments. + */ +static inline size_t net_buf_frags_len(const struct net_buf *buf) +{ + size_t bytes = 0; + + while (buf) { + bytes += buf->len; + buf = buf->frags; + } + + return bytes; +} + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_NET_BUF_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/platform/hooks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/platform/hooks.h new file mode 100644 index 00000000..9989f640 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/platform/hooks.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2024 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_PLATFORM_PLATFORM_H_ +#define ZEPHYR_INCLUDE_PLATFORM_PLATFORM_H_ + +/** + * @file + * @brief Soc and Board hooks + * + * This header file contains function prototypes for the interfaces between + * zephyr architecture and initialization code and the SoC and board specific logic + * that resides under boards/ and soc/ + * + * @note These are all standard soc and board interfaces that are exported from + * soc and board specific logic to OS internal logic. These should never be accessed + * directly from application code but may be freely used within the OS. + */ + + +/** + * @brief SoC hook executed at the beginning of the reset vector. + * + * This hook is implemented by the SoC and can be used to perform any + * SoC-specific initialization. + */ +void soc_reset_hook(void); + +/** + * @brief SoC hook executed after the reset vector. + * + * This hook is implemented by the SoC and can be used to perform any + * SoC-specific initialization. + */ +void soc_prep_hook(void); + +/** + * @brief SoC hook executed before the kernel and devices are initialized. + * + * This hook is implemented by the SoC and can be used to perform any + * SoC-specific initialization. + */ +void soc_early_init_hook(void); + +/** + * @brief SoC hook executed after the kernel and devices are initialized. + * + * This hook is implemented by the SoC and can be used to perform any + * SoC-specific initialization. + */ +void soc_late_init_hook(void); + +/** + * @brief SoC per-core initialization + * + * This hook is implemented by the SoC and can be used to perform any + * SoC-specific per-core initialization + */ +void soc_per_core_init_hook(void); + +/** + * @brief Board hook executed before the kernel starts. + * + * This is called before the kernel has started. This hook + * is implemented by the board and can be used to perform any board-specific + * initialization. + */ +void board_early_init_hook(void); + +/** + * @brief Board hook executed after the kernel starts. + * + * This is called after the kernel has started, but before the main function is + * called. This hook is implemented by the board and can be used to perform + * any board-specific initialization. + */ +void board_late_init_hook(void); + +#endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/device.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/device.h index 5d3b4a96..f7c008f3 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/device.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/device.h @@ -208,7 +208,7 @@ BUILD_ASSERT(offsetof(struct pm_device_isr, base) == 0); #ifdef CONFIG_PM_DEVICE_POWER_DOMAIN #define Z_PM_DEVICE_POWER_DOMAIN_INIT(_node_id) \ .domain = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(_node_id, \ - power_domain)), + power_domains)), #else #define Z_PM_DEVICE_POWER_DOMAIN_INIT(obj) #endif /* CONFIG_PM_DEVICE_POWER_DOMAIN */ @@ -625,7 +625,8 @@ bool pm_device_is_powered(const struct device *dev); * This helper function is intended to be called at the end of a driver * init function to automatically setup the device into the lowest power * mode. It assumes that the device has been configured as if it is in - * @ref PM_DEVICE_STATE_OFF. + * @ref PM_DEVICE_STATE_OFF, or @ref PM_DEVICE_STATE_SUSPENDED if device can + * never be powered off. * * @param dev Device instance. * @param action_cb Device PM control callback function. @@ -718,10 +719,16 @@ static inline int pm_device_driver_init(const struct device *dev, pm_device_acti /* When power management is not enabled, all drivers should initialise to active state */ rc = action_cb(dev, PM_DEVICE_ACTION_TURN_ON); - if (rc == 0) { - rc = action_cb(dev, PM_DEVICE_ACTION_RESUME); + if ((rc < 0) && (rc != -ENOTSUP)) { + return rc; } - return rc; + + rc = action_cb(dev, PM_DEVICE_ACTION_RESUME); + if (rc < 0) { + return rc; + } + + return 0; } #endif /* CONFIG_PM_DEVICE */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/policy.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/policy.h index 6fe91663..057488d7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/policy.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/policy.h @@ -67,7 +67,7 @@ struct pm_policy_latency_request { struct pm_policy_event { /** @cond INTERNAL_HIDDEN */ sys_snode_t node; - uint32_t value_cyc; + int64_t uptime_ticks; /** @endcond */ }; @@ -137,50 +137,6 @@ void pm_policy_state_lock_put(enum pm_state state, uint8_t substate_id); */ bool pm_policy_state_lock_is_active(enum pm_state state, uint8_t substate_id); -/** - * @brief Add a new latency requirement. - * - * The system will not enter any power state that would make the system to - * exceed the given latency value. - * - * @param req Latency request. - * @param value_us Maximum allowed latency in microseconds. - */ -void pm_policy_latency_request_add(struct pm_policy_latency_request *req, - uint32_t value_us); - -/** - * @brief Update a latency requirement. - * - * @param req Latency request. - * @param value_us New maximum allowed latency in microseconds. - */ -void pm_policy_latency_request_update(struct pm_policy_latency_request *req, - uint32_t value_us); - -/** - * @brief Remove a latency requirement. - * - * @param req Latency request. - */ -void pm_policy_latency_request_remove(struct pm_policy_latency_request *req); - -/** - * @brief Subscribe to maximum latency changes. - * - * @param req Subscription request. - * @param cb Callback function (NULL to disable). - */ -void pm_policy_latency_changed_subscribe(struct pm_policy_latency_subscription *req, - pm_policy_latency_changed_cb_t cb); - -/** - * @brief Unsubscribe to maximum latency changes. - * - * @param req Subscription request. - */ -void pm_policy_latency_changed_unsubscribe(struct pm_policy_latency_subscription *req); - /** * @brief Register an event. * @@ -189,27 +145,30 @@ void pm_policy_latency_changed_unsubscribe(struct pm_policy_latency_subscription * event, the policy manager will be able to decide whether certain power states * are worth entering or not. * - * @note It is mandatory to unregister events once they have happened by using - * pm_policy_event_unregister(). Not doing so is an API contract violation, - * because the system would continue to consider them as valid events in the - * *far* future, that is, after the cycle counter rollover. + * CPU is woken up before the time passed in cycle to minimize event handling + * latency. Once woken up, the CPU will be kept awake until the event has been + * handled, which is signaled by pm_policy_event_unregister() or moving event + * into the future using pm_policy_event_update(). * * @param evt Event. - * @param time_us When the event will occur, in microseconds from now. + * @param uptime_ticks When the event will occur, in uptime ticks. * - * @see pm_policy_event_unregister + * @see pm_policy_event_unregister() */ -void pm_policy_event_register(struct pm_policy_event *evt, uint32_t time_us); +void pm_policy_event_register(struct pm_policy_event *evt, int64_t uptime_ticks); /** * @brief Update an event. * + * This shortcut allows for moving the time an event will occur without the + * need for an unregister + register cycle. + * * @param evt Event. - * @param time_us When the event will occur, in microseconds from now. + * @param uptime_ticks When the event will occur, in uptime ticks. * * @see pm_policy_event_register */ -void pm_policy_event_update(struct pm_policy_event *evt, uint32_t time_us); +void pm_policy_event_update(struct pm_policy_event *evt, int64_t uptime_ticks); /** * @brief Unregister an event. @@ -246,6 +205,18 @@ void pm_policy_device_power_lock_get(const struct device *dev); */ void pm_policy_device_power_lock_put(const struct device *dev); +/** + * @brief Returns the ticks until the next event + * + * If an event is registred, it will return the number of ticks until the next event, if the + * "next"/"oldest" registered event is in the past, it will return 0. Otherwise it returns -1. + * + * @retval >0 If next registered event is in the future + * @retval 0 If next registered event is now or in the past + * @retval -1 Otherwise + */ +int64_t pm_policy_next_event_ticks(void); + #else static inline void pm_policy_state_lock_get(enum pm_state state, uint8_t substate_id) { @@ -267,38 +238,16 @@ static inline bool pm_policy_state_lock_is_active(enum pm_state state, uint8_t s return false; } -static inline void pm_policy_latency_request_add( - struct pm_policy_latency_request *req, uint32_t value_us) -{ - ARG_UNUSED(req); - ARG_UNUSED(value_us); -} - -static inline void pm_policy_latency_request_update( - struct pm_policy_latency_request *req, uint32_t value_us) -{ - ARG_UNUSED(req); - ARG_UNUSED(value_us); -} - -static inline void pm_policy_latency_request_remove( - struct pm_policy_latency_request *req) -{ - ARG_UNUSED(req); -} - -static inline void pm_policy_event_register(struct pm_policy_event *evt, - uint32_t time_us) +static inline void pm_policy_event_register(struct pm_policy_event *evt, uint32_t cycle) { ARG_UNUSED(evt); - ARG_UNUSED(time_us); + ARG_UNUSED(cycle); } -static inline void pm_policy_event_update(struct pm_policy_event *evt, - uint32_t time_us) +static inline void pm_policy_event_update(struct pm_policy_event *evt, uint32_t cycle) { ARG_UNUSED(evt); - ARG_UNUSED(time_us); + ARG_UNUSED(cycle); } static inline void pm_policy_event_unregister(struct pm_policy_event *evt) @@ -316,8 +265,79 @@ static inline void pm_policy_device_power_lock_put(const struct device *dev) ARG_UNUSED(dev); } +static inline int64_t pm_policy_next_event_ticks(void) +{ + return -1; +} + #endif /* CONFIG_PM */ +#if defined(CONFIG_PM) || defined(CONFIG_PM_POLICY_LATENCY_STANDALONE) || defined(__DOXYGEN__) +/** + * @brief Add a new latency requirement. + * + * The system will not enter any power state that would make the system to + * exceed the given latency value. + * + * @param req Latency request. + * @param value_us Maximum allowed latency in microseconds. + */ +void pm_policy_latency_request_add(struct pm_policy_latency_request *req, + uint32_t value_us); + +/** + * @brief Update a latency requirement. + * + * @param req Latency request. + * @param value_us New maximum allowed latency in microseconds. + */ +void pm_policy_latency_request_update(struct pm_policy_latency_request *req, + uint32_t value_us); + +/** + * @brief Remove a latency requirement. + * + * @param req Latency request. + */ +void pm_policy_latency_request_remove(struct pm_policy_latency_request *req); + +/** + * @brief Subscribe to maximum latency changes. + * + * @param req Subscription request. + * @param cb Callback function (NULL to disable). + */ +void pm_policy_latency_changed_subscribe(struct pm_policy_latency_subscription *req, + pm_policy_latency_changed_cb_t cb); + +/** + * @brief Unsubscribe to maximum latency changes. + * + * @param req Subscription request. + */ +void pm_policy_latency_changed_unsubscribe(struct pm_policy_latency_subscription *req); +#else +static inline void pm_policy_latency_request_add( + struct pm_policy_latency_request *req, uint32_t value_us) +{ + ARG_UNUSED(req); + ARG_UNUSED(value_us); +} + +static inline void pm_policy_latency_request_update( + struct pm_policy_latency_request *req, uint32_t value_us) +{ + ARG_UNUSED(req); + ARG_UNUSED(value_us); +} + +static inline void pm_policy_latency_request_remove( + struct pm_policy_latency_request *req) +{ + ARG_UNUSED(req); +} +#endif /* CONFIG_PM CONFIG_PM_POLICY_LATENCY_STANDALONE */ + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/state.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/state.h index 87363ea2..6590b90c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/state.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/pm/state.h @@ -194,7 +194,7 @@ struct pm_state_constraint { * @param idx Index within the array. */ #define Z_DT_PHANDLE_01(node_id, prop, idx) \ - COND_CODE_1(DT_NODE_HAS_STATUS(DT_PHANDLE_BY_IDX(node_id, prop, idx), okay), \ + COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_PHANDLE_BY_IDX(node_id, prop, idx)), \ (1), (0)) /** @@ -207,7 +207,7 @@ struct pm_state_constraint { * @param node_id A node identifier with compatible zephyr,power-state */ #define Z_PM_STATE_INFO_FROM_DT_CPU(i, node_id) \ - COND_CODE_1(DT_NODE_HAS_STATUS(DT_PHANDLE_BY_IDX(node_id, cpu_power_states, i), okay), \ + COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_PHANDLE_BY_IDX(node_id, cpu_power_states, i)), \ (PM_STATE_INFO_DT_INIT(DT_PHANDLE_BY_IDX(node_id, cpu_power_states, i)),), ()) /** @@ -220,7 +220,7 @@ struct pm_state_constraint { * @param node_id A node identifier with compatible zephyr,power-state */ #define Z_PM_STATE_FROM_DT_CPU(i, node_id) \ - COND_CODE_1(DT_NODE_HAS_STATUS(DT_PHANDLE_BY_IDX(node_id, cpu_power_states, i), okay), \ + COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_PHANDLE_BY_IDX(node_id, cpu_power_states, i)), \ (PM_STATE_DT_INIT(DT_PHANDLE_BY_IDX(node_id, cpu_power_states, i)),), ()) /** @endcond */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/dirent.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/dirent.h index 12f5d443..0ffe8756 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/dirent.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/dirent.h @@ -7,7 +7,8 @@ #define ZEPHYR_INCLUDE_POSIX_DIRENT_H_ #include -#include "posix_types.h" + +#include #ifdef CONFIG_POSIX_FILE_SYSTEM #include @@ -27,6 +28,8 @@ struct dirent { DIR *opendir(const char *dirname); int closedir(DIR *dirp); struct dirent *readdir(DIR *dirp); +int readdir_r(DIR *ZRESTRICT dirp, struct dirent *ZRESTRICT entry, + struct dirent **ZRESTRICT result); #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/fcntl.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/fcntl.h index 9689d1ae..24ed1776 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/fcntl.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/fcntl.h @@ -8,9 +8,13 @@ #define ZEPHYR_POSIX_FCNTL_H_ #ifdef CONFIG_PICOLIBC -#define O_CREAT 0x0040 +#define O_CREAT 0x0040 +#define O_TRUNC 0x0200 +#define O_APPEND 0x0400 #else -#define O_CREAT 0x0200 +#define O_CREAT 0x0200 +#define O_TRUNC 0x0400 +#define O_APPEND 0x0008 #endif #define O_ACCMODE (O_RDONLY | O_WRONLY | O_RDWR) @@ -19,7 +23,6 @@ #define O_WRONLY 01 #define O_RDWR 02 -#define O_APPEND 0x0400 #define O_EXCL 0x0800 #define O_NONBLOCK 0x4000 diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/grp.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/grp.h new file mode 100644 index 00000000..3f5616c3 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/grp.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_POSIX_GRP_H_ +#define ZEPHYR_INCLUDE_POSIX_GRP_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Group structure + */ +struct group { + /**< the name of the group */ + char *gr_name; + /**< numerical group ID */ + gid_t gr_gid; + /**< pointer to a null-terminated array of character pointers to member names */ + char **gr_mem; +}; + +int getgrnam_r(const char *name, struct group *grp, char *buffer, size_t bufsize, + struct group **result); +int getgrgid_r(gid_t gid, struct group *grp, char *buffer, size_t bufsize, struct group **result); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_POSIX_GRP_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/mqueue.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/mqueue.h index aac03426..40db0733 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/mqueue.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/mqueue.h @@ -12,7 +12,7 @@ #include #include #include -#include "posix_types.h" +#include #ifdef __cplusplus extern "C" { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/poll.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/poll.h index 4aeebeed..aa2c8921 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/poll.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/poll.h @@ -12,9 +12,12 @@ extern "C" { #endif +typedef unsigned int nfds_t; + #define pollfd zsock_pollfd #define POLLIN ZSOCK_POLLIN +#define POLLPRI ZSOCK_POLLPRI #define POLLOUT ZSOCK_POLLOUT #define POLLERR ZSOCK_POLLERR #define POLLHUP ZSOCK_POLLHUP diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_features.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_features.h index eb3c4b44..e4a91c6f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_features.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_features.h @@ -123,7 +123,10 @@ #endif /* #define _POSIX_SPORADIC_SERVER (-1L) */ -/* #define _POSIX_SYNCHRONIZED_IO (-1L) */ + +#ifdef CONFIG_POSIX_SYNCHRONIZED_IO +#define _POSIX_SYNCHRONIZED_IO _POSIX_VERSION +#endif #ifdef CONFIG_POSIX_THREAD_ATTR_STACKADDR #define _POSIX_THREAD_ATTR_STACKADDR _POSIX_VERSION @@ -328,7 +331,9 @@ #define SYMLOOP_MAX _POSIX_SYMLOOP_MAX #define TIMER_MAX _POSIX_TIMER_MAX #define TTY_NAME_MAX _POSIX_TTY_NAME_MAX +#ifndef TZNAME_MAX #define TZNAME_MAX _POSIX_TZNAME_MAX +#endif /* Pathname variable values */ #define FILESIZEBITS (32) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_types.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_types.h index cbe51fa7..e65a398c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_types.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/posix_types.h @@ -11,6 +11,18 @@ #include #endif +#if !defined(_CLOCK_T_DECLARED) && !defined(__clock_t_defined) +typedef unsigned long clock_t; +#define _CLOCK_T_DECLARED +#define __clock_t_defined +#endif + +#if !defined(_CLOCKID_T_DECLARED) && !defined(__clockid_t_defined) +typedef unsigned long clockid_t; +#define _CLOCKID_T_DECLARED +#define __clockid_t_defined +#endif + #ifdef CONFIG_NEWLIB_LIBC #include #endif @@ -21,6 +33,48 @@ extern "C" { #endif +#if !defined(_DEV_T_DECLARED) && !defined(__dev_t_defined) +typedef int dev_t; +#define _DEV_T_DECLARED +#define __dev_t_defined +#endif + +#if !defined(_INO_T_DECLARED) && !defined(__ino_t_defined) +typedef int ino_t; +#define _INO_T_DECLARED +#define __ino_t_defined +#endif + +#if !defined(_NLINK_T_DECLARED) && !defined(__nlink_t_defined) +typedef unsigned short nlink_t; +#define _NLINK_T_DECLARED +#define __nlink_t_defined +#endif + +#if !defined(_UID_T_DECLARED) && !defined(__uid_t_defined) +typedef unsigned short uid_t; +#define _UID_T_DECLARED +#define __uid_t_defined +#endif + +#if !defined(_GID_T_DECLARED) && !defined(__gid_t_defined) +typedef unsigned short gid_t; +#define _GID_T_DECLARED +#define __gid_t_defined +#endif + +#if !defined(_BLKSIZE_T_DECLARED) && !defined(__blksize_t_defined) +typedef unsigned long blksize_t; +#define _BLKSIZE_T_DECLARED +#define __blksize_t_defined +#endif + +#if !defined(_BLKCNT_T_DECLARED) && !defined(__blkcnt_t_defined) +typedef unsigned long blkcnt_t; +#define _BLKCNT_T_DECLARED +#define __blkcnt_t_defined +#endif + #if !defined(CONFIG_ARCMWDT_LIBC) typedef int pid_t; #endif @@ -30,12 +84,7 @@ typedef unsigned long useconds_t; #endif /* time related attributes */ -#if !defined(CONFIG_NEWLIB_LIBC) && !defined(CONFIG_ARCMWDT_LIBC) -#ifndef __clockid_t_defined -typedef uint32_t clockid_t; -#endif -#endif /* !CONFIG_NEWLIB_LIBC && !CONFIG_ARCMWDT_LIBC */ -#ifndef __timer_t_defined +#if !defined(__timer_t_defined) && !defined(_TIMER_T_DECLARED) typedef unsigned long timer_t; #endif @@ -45,12 +94,10 @@ struct pthread_attr { uint32_t details[2]; }; -#if defined(CONFIG_MINIMAL_LIBC) || defined(CONFIG_PICOLIBC) || defined(CONFIG_ARMCLANG_STD_LIBC) \ - || defined(CONFIG_ARCMWDT_LIBC) +#if !defined(CONFIG_NEWLIB_LIBC) typedef struct pthread_attr pthread_attr_t; -#endif - BUILD_ASSERT(sizeof(pthread_attr_t) >= sizeof(struct pthread_attr)); +#endif typedef uint32_t pthread_t; typedef uint32_t pthread_spinlock_t; @@ -65,11 +112,10 @@ struct pthread_mutexattr { unsigned char type: 2; bool initialized: 1; }; -#if defined(CONFIG_MINIMAL_LIBC) || defined(CONFIG_PICOLIBC) || defined(CONFIG_ARMCLANG_STD_LIBC) \ - || defined(CONFIG_ARCMWDT_LIBC) +#if !defined(CONFIG_NEWLIB_LIBC) typedef struct pthread_mutexattr pthread_mutexattr_t; -#endif BUILD_ASSERT(sizeof(pthread_mutexattr_t) >= sizeof(struct pthread_mutexattr)); +#endif /* Condition variables */ typedef uint32_t pthread_cond_t; @@ -78,11 +124,10 @@ struct pthread_condattr { clockid_t clock; }; -#if defined(CONFIG_MINIMAL_LIBC) || defined(CONFIG_PICOLIBC) || defined(CONFIG_ARMCLANG_STD_LIBC) \ - || defined(CONFIG_ARCMWDT_LIBC) +#if !defined(CONFIG_NEWLIB_LIBC) typedef struct pthread_condattr pthread_condattr_t; -#endif BUILD_ASSERT(sizeof(pthread_condattr_t) >= sizeof(struct pthread_condattr)); +#endif /* Barrier */ typedef uint32_t pthread_barrier_t; @@ -99,14 +144,12 @@ struct pthread_once { bool flag; }; -#if defined(CONFIG_MINIMAL_LIBC) || defined(CONFIG_PICOLIBC) || defined(CONFIG_ARMCLANG_STD_LIBC) \ - || defined(CONFIG_ARCMWDT_LIBC) +#if !defined(CONFIG_NEWLIB_LIBC) typedef uint32_t pthread_key_t; typedef struct pthread_once pthread_once_t; -#endif - /* Newlib typedefs pthread_once_t as a struct with two ints */ BUILD_ASSERT(sizeof(pthread_once_t) >= sizeof(struct pthread_once)); +#endif #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pthread.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pthread.h index eaa9ccb6..685a8d9a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pthread.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pthread.h @@ -183,6 +183,8 @@ int pthread_condattr_setclock(pthread_condattr_t *att, clockid_t clock_id); * FIXME: Only PRIO_NONE is supported. Implement other protocols. */ #define PTHREAD_PRIO_NONE 0 +#define PTHREAD_PRIO_INHERIT 1 +#define PTHREAD_PRIO_PROTECT 2 /** * @brief POSIX threading compatibility API @@ -348,16 +350,22 @@ int pthread_barrierattr_getpshared(const pthread_barrierattr_t *ZRESTRICT attr, int pthread_condattr_getpshared(const pthread_condattr_t * int *); int pthread_condattr_setpshared(pthread_condattr_t *, int); int pthread_mutex_consistent(pthread_mutex_t *); -int pthread_mutex_getprioceiling(const pthread_mutex_t * int *); -int pthread_mutex_setprioceiling(pthread_mutex_t *, int int *); -int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t *, int *); int pthread_mutexattr_getpshared(const pthread_mutexattr_t * int *); int pthread_mutexattr_getrobust(const pthread_mutexattr_t * int *); -int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *, int); int pthread_mutexattr_setpshared(pthread_mutexattr_t *, int); int pthread_mutexattr_setrobust(pthread_mutexattr_t *, int); */ +#ifdef CONFIG_POSIX_THREAD_PRIO_PROTECT +int pthread_mutex_getprioceiling(const pthread_mutex_t *ZRESTRICT mutex, + int *ZRESTRICT prioceiling); +int pthread_mutex_setprioceiling(pthread_mutex_t *ZRESTRICT mutex, int prioceiling, + int *ZRESTRICT old_ceiling); +int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t *ZRESTRICT attr, + int *ZRESTRICT prioceiling); +int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *attr, int prioceiling); +#endif /* CONFIG_POSIX_THREAD_PRIO_PROTECT */ + /* Base Pthread related APIs */ /** @@ -421,6 +429,8 @@ int pthread_attr_setinheritsched(pthread_attr_t *attr, int inheritsched); int pthread_once(pthread_once_t *once, void (*initFunc)(void)); #endif FUNC_NORETURN void pthread_exit(void *retval); +int pthread_timedjoin_np(pthread_t thread, void **status, const struct timespec *abstime); +int pthread_tryjoin_np(pthread_t thread, void **status); int pthread_join(pthread_t thread, void **status); int pthread_cancel(pthread_t pthread); int pthread_detach(pthread_t thread); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pwd.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pwd.h new file mode 100644 index 00000000..3557b20a --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/pwd.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_POSIX_PWD_H_ +#define ZEPHYR_INCLUDE_POSIX_PWD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +struct passwd { + /* user's login name */ + char *pw_name; + /* numerical user ID */ + uid_t pw_uid; + /* numerical group ID */ + gid_t pw_gid; + /* initial working directory */ + char *pw_dir; + /* program to use as shell */ + char *pw_shell; +}; + +int getpwnam_r(const char *nam, struct passwd *pwd, char *buffer, size_t bufsize, + struct passwd **result); +int getpwuid_r(uid_t uid, struct passwd *pwd, char *buffer, size_t bufsize, struct passwd **result); + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_POSIX_PWD_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sched.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sched.h index b337cc2c..29a3fa93 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sched.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sched.h @@ -7,8 +7,7 @@ #define ZEPHYR_INCLUDE_POSIX_SCHED_H_ #include - -#include "posix_types.h" +#include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/semaphore.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/semaphore.h index 3b0f53b0..e3f6014c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/semaphore.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/semaphore.h @@ -7,7 +7,7 @@ #define ZEPHYR_INCLUDE_POSIX_SEMAPHORE_H_ #include -#include "posix_types.h" +#include #ifdef __cplusplus extern "C" { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/signal.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/signal.h index 165050f2..e106642f 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/signal.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/signal.h @@ -6,7 +6,8 @@ #ifndef ZEPHYR_INCLUDE_POSIX_SIGNAL_H_ #define ZEPHYR_INCLUDE_POSIX_SIGNAL_H_ -#include "posix_types.h" +/* include posix_types.h before posix_features.h (here) to avoid build errors against newlib */ +#include #include "posix_features.h" #ifdef __cplusplus @@ -77,6 +78,16 @@ typedef struct { #define SIG_UNBLOCK 2 #endif +#define SIG_DFL ((void *)0) +#define SIG_IGN ((void *)1) +#define SIG_ERR ((void *)-1) + +#define SI_USER 1 +#define SI_QUEUE 2 +#define SI_TIMER 3 +#define SI_ASYNCIO 4 +#define SI_MESGQ 5 + typedef int sig_atomic_t; /* Atomic entity type (ANSI) */ union sigval { @@ -92,12 +103,36 @@ struct sigevent { int sigev_signo; }; +typedef struct { + int si_signo; + int si_code; + union sigval si_value; +} siginfo_t; + +struct sigaction { + void (*sa_handler)(int signno); + sigset_t sa_mask; + int sa_flags; + void (*sa_sigaction)(int signo, siginfo_t *info, void *context); +}; + +typedef void (*sighandler_t)(int signo); + +unsigned int alarm(unsigned int seconds); +int kill(pid_t pid, int sig); +int pause(void); +int raise(int signo); +int sigaction(int sig, const struct sigaction *ZRESTRICT act, struct sigaction *ZRESTRICT oact); +int sigpending(sigset_t *set); +int sigsuspend(const sigset_t *sigmask); +int sigwait(const sigset_t *ZRESTRICT set, int *ZRESTRICT signo); char *strsignal(int signum); int sigemptyset(sigset_t *set); int sigfillset(sigset_t *set); int sigaddset(sigset_t *set, int signo); int sigdelset(sigset_t *set, int signo); int sigismember(const sigset_t *set, int signo); +sighandler_t signal(int signo, sighandler_t handler); int sigprocmask(int how, const sigset_t *ZRESTRICT set, sigset_t *ZRESTRICT oset); int pthread_sigmask(int how, const sigset_t *ZRESTRICT set, sigset_t *ZRESTRICT oset); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/select.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/select.h index fc61c018..b51ace79 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/select.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/select.h @@ -6,23 +6,26 @@ #ifndef ZEPHYR_INCLUDE_POSIX_SYS_SELECT_H_ #define ZEPHYR_INCLUDE_POSIX_SYS_SELECT_H_ -#include -#include +#include +#include #ifdef __cplusplus extern "C" { #endif -#define fd_set zsock_fd_set -#define FD_SETSIZE ZSOCK_FD_SETSIZE -#define FD_ZERO ZSOCK_FD_ZERO -#define FD_SET ZSOCK_FD_SET -#define FD_CLR ZSOCK_FD_CLR -#define FD_ISSET ZSOCK_FD_ISSET +#define FD_SETSIZE ZVFS_FD_SETSIZE + +typedef struct zvfs_fd_set fd_set; struct timeval; -int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, struct timeval *timeout); +int pselect(int nfds, fd_set *readfds, fd_set *writefds, fd_set *exceptfds, + const struct timespec *timeout, const void *sigmask); +int select(int nfds, fd_set *readfds, fd_set *writefds, fd_set *errorfds, struct timeval *timeout); +void FD_CLR(int fd, fd_set *fdset); +int FD_ISSET(int fd, fd_set *fdset); +void FD_SET(int fd, fd_set *fdset); +void FD_ZERO(fd_set *fdset); #ifdef __cplusplus } diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/stat.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/stat.h index 2d19df29..fdd4e093 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/stat.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/stat.h @@ -36,43 +36,8 @@ extern "C" { #include #include -#include -#include -#ifndef _DEV_T_DECLARED -typedef int dev_t; -#define _DEV_T_DECLARED -#endif - -#ifndef _INO_T_DECLARED -typedef int ino_t; -#define _INO_T_DECLARED -#endif - -#ifndef _NLINK_T_DECLARED -typedef unsigned short nlink_t; -#define _NLINK_T_DECLARED -#endif - -#ifndef _UID_T_DECLARED -typedef unsigned short uid_t; -#define _UID_T_DECLARED -#endif - -#ifndef _GID_T_DECLARED -typedef unsigned short gid_t; -#define _GID_T_DECLARED -#endif - -#ifndef _BLKSIZE_T_DECLARED -typedef unsigned long blksize_t; -#define _BLKSIZE_T_DECLARED -#endif - -#ifndef _BLKCNT_T_DECLARED -typedef unsigned long blkcnt_t; -#define _BLKCNT_T_DECLARED -#endif +#include /* dj's stat defines _STAT_H_ */ #ifndef _STAT_H_ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/time.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/time.h index d7e108b5..71153f71 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/time.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/sys/time.h @@ -22,6 +22,7 @@ struct timeval { #endif #else +#include #include #endif /* CONFIG_NEWLIB_LIBC */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/time.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/time.h index f0ca0728..51542f30 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/time.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/time.h @@ -58,7 +58,7 @@ struct itimerspec { #include #include -#include "posix_types.h" +#include #include #ifdef __cplusplus @@ -97,6 +97,7 @@ int clock_getcpuclockid(pid_t pid, clockid_t *clock_id); /* Timer APIs */ int timer_create(clockid_t clockId, struct sigevent *evp, timer_t *timerid); int timer_delete(timer_t timerid); +struct itimerspec; int timer_gettime(timer_t timerid, struct itimerspec *its); int timer_settime(timer_t timerid, int flags, const struct itimerspec *value, struct itimerspec *ovalue); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/unistd.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/unistd.h index 194b2bff..b7ac069b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/unistd.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/posix/unistd.h @@ -6,7 +6,7 @@ #ifndef ZEPHYR_INCLUDE_POSIX_UNISTD_H_ #define ZEPHYR_INCLUDE_POSIX_UNISTD_H_ -#include "posix_types.h" +#include #ifdef CONFIG_POSIX_API #include @@ -35,11 +35,16 @@ off_t lseek(int file, off_t offset, int whence); int fsync(int fd); int ftruncate(int fd, off_t length); +#ifdef CONFIG_POSIX_SYNCHRONIZED_IO +int fdatasync(int fd); +#endif /* CONFIG_POSIX_SYNCHRONIZED_IO */ + /* File System related operations */ int rename(const char *old, const char *newp); int unlink(const char *path); int stat(const char *path, struct stat *buf); int mkdir(const char *path, mode_t mode); +int rmdir(const char *path); FUNC_NORETURN void _exit(int status); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/rtio/rtio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/rtio/rtio.h index 1bb3a844..228211a4 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/rtio/rtio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/rtio/rtio.h @@ -253,30 +253,36 @@ struct rtio_sqe { union { - /** OP_TX, OP_RX */ + /** OP_TX */ struct { uint32_t buf_len; /**< Length of buffer */ - uint8_t *buf; /**< Buffer to use*/ - }; + const uint8_t *buf; /**< Buffer to write from */ + } tx; + + /** OP_RX */ + struct { + uint32_t buf_len; /**< Length of buffer */ + uint8_t *buf; /**< Buffer to read into */ + } rx; /** OP_TINY_TX */ struct { - uint8_t tiny_buf_len; /**< Length of tiny buffer */ - uint8_t tiny_buf[7]; /**< Tiny buffer */ - }; + uint8_t buf_len; /**< Length of tiny buffer */ + uint8_t buf[7]; /**< Tiny buffer */ + } tiny_tx; /** OP_CALLBACK */ struct { rtio_callback_t callback; void *arg0; /**< Last argument given to callback */ - }; + } callback; /** OP_TXRX */ struct { - uint32_t txrx_buf_len; - uint8_t *tx_buf; - uint8_t *rx_buf; - }; + uint32_t buf_len; /**< Length of tx and rx buffers */ + const uint8_t *tx_buf; /**< Buffer to write from */ + uint8_t *rx_buf; /**< Buffer to read into */ + } txrx; /** OP_I2C_CONFIGURE */ uint32_t i2c_config; @@ -504,8 +510,8 @@ static inline void rtio_sqe_prep_read(struct rtio_sqe *sqe, sqe->op = RTIO_OP_RX; sqe->prio = prio; sqe->iodev = iodev; - sqe->buf_len = len; - sqe->buf = buf; + sqe->rx.buf_len = len; + sqe->rx.buf = buf; sqe->userdata = userdata; } @@ -536,7 +542,7 @@ static inline void rtio_sqe_prep_read_multishot(struct rtio_sqe *sqe, static inline void rtio_sqe_prep_write(struct rtio_sqe *sqe, const struct rtio_iodev *iodev, int8_t prio, - uint8_t *buf, + const uint8_t *buf, uint32_t len, void *userdata) { @@ -544,8 +550,8 @@ static inline void rtio_sqe_prep_write(struct rtio_sqe *sqe, sqe->op = RTIO_OP_TX; sqe->prio = prio; sqe->iodev = iodev; - sqe->buf_len = len; - sqe->buf = buf; + sqe->tx.buf_len = len; + sqe->tx.buf = buf; sqe->userdata = userdata; } @@ -566,14 +572,14 @@ static inline void rtio_sqe_prep_tiny_write(struct rtio_sqe *sqe, uint8_t tiny_write_len, void *userdata) { - __ASSERT_NO_MSG(tiny_write_len <= sizeof(sqe->tiny_buf)); + __ASSERT_NO_MSG(tiny_write_len <= sizeof(sqe->tiny_tx.buf)); memset(sqe, 0, sizeof(struct rtio_sqe)); sqe->op = RTIO_OP_TINY_TX; sqe->prio = prio; sqe->iodev = iodev; - sqe->tiny_buf_len = tiny_write_len; - memcpy(sqe->tiny_buf, tiny_write_data, tiny_write_len); + sqe->tiny_tx.buf_len = tiny_write_len; + memcpy(sqe->tiny_tx.buf, tiny_write_data, tiny_write_len); sqe->userdata = userdata; } @@ -594,18 +600,37 @@ static inline void rtio_sqe_prep_callback(struct rtio_sqe *sqe, sqe->op = RTIO_OP_CALLBACK; sqe->prio = 0; sqe->iodev = NULL; - sqe->callback = callback; - sqe->arg0 = arg0; + sqe->callback.callback = callback; + sqe->callback.arg0 = arg0; sqe->userdata = userdata; } +/** + * @brief Prepare a callback op submission that does not create a CQE + * + * Similar to @ref rtio_sqe_prep_callback, but the @ref RTIO_SQE_NO_RESPONSE + * flag is set on the SQE to prevent the generation of a CQE upon completion. + * + * This can be useful when the callback is the last operation in a sequence + * whose job is to clean up all the previous CQE's. Without @ref RTIO_SQE_NO_RESPONSE + * the completion itself will result in a CQE that cannot be consumed in the callback. + */ +static inline void rtio_sqe_prep_callback_no_cqe(struct rtio_sqe *sqe, + rtio_callback_t callback, + void *arg0, + void *userdata) +{ + rtio_sqe_prep_callback(sqe, callback, arg0, userdata); + sqe->flags |= RTIO_SQE_NO_RESPONSE; +} + /** * @brief Prepare a transceive op submission */ static inline void rtio_sqe_prep_transceive(struct rtio_sqe *sqe, const struct rtio_iodev *iodev, int8_t prio, - uint8_t *tx_buf, + const uint8_t *tx_buf, uint8_t *rx_buf, uint32_t buf_len, void *userdata) @@ -614,9 +639,9 @@ static inline void rtio_sqe_prep_transceive(struct rtio_sqe *sqe, sqe->op = RTIO_OP_TXRX; sqe->prio = prio; sqe->iodev = iodev; - sqe->txrx_buf_len = buf_len; - sqe->tx_buf = tx_buf; - sqe->rx_buf = rx_buf; + sqe->txrx.buf_len = buf_len; + sqe->txrx.tx_buf = tx_buf; + sqe->txrx.rx_buf = rx_buf; sqe->userdata = userdata; } @@ -696,6 +721,10 @@ static inline int rtio_block_pool_alloc(struct rtio *r, size_t min_sz, return 0; } + if (bytes <= block_size) { + break; + } + bytes -= block_size; } while (bytes >= min_sz); @@ -1036,9 +1065,9 @@ static inline uint32_t rtio_cqe_compute_flags(struct rtio_iodev_sqe *iodev_sqe) if (iodev_sqe->sqe.op == RTIO_OP_RX && iodev_sqe->sqe.flags & RTIO_SQE_MEMPOOL_BUFFER) { struct rtio *r = iodev_sqe->r; struct sys_mem_blocks *mem_pool = r->block_pool; - int blk_index = (iodev_sqe->sqe.buf - mem_pool->buffer) >> + int blk_index = (iodev_sqe->sqe.rx.buf - mem_pool->buffer) >> mem_pool->info.blk_sz_shift; - int blk_count = iodev_sqe->sqe.buf_len >> mem_pool->info.blk_sz_shift; + int blk_count = iodev_sqe->sqe.rx.buf_len >> mem_pool->info.blk_sz_shift; flags = RTIO_CQE_FLAG_PREP_MEMPOOL(blk_index, blk_count); } @@ -1185,19 +1214,19 @@ static inline int rtio_sqe_rx_buf(const struct rtio_iodev_sqe *iodev_sqe, uint32 if (sqe->op == RTIO_OP_RX && sqe->flags & RTIO_SQE_MEMPOOL_BUFFER) { struct rtio *r = iodev_sqe->r; - if (sqe->buf != NULL) { - if (sqe->buf_len < min_buf_len) { + if (sqe->rx.buf != NULL) { + if (sqe->rx.buf_len < min_buf_len) { return -ENOMEM; } - *buf = sqe->buf; - *buf_len = sqe->buf_len; + *buf = sqe->rx.buf; + *buf_len = sqe->rx.buf_len; return 0; } int rc = rtio_block_pool_alloc(r, min_buf_len, max_buf_len, buf, buf_len); if (rc == 0) { - sqe->buf = *buf; - sqe->buf_len = *buf_len; + sqe->rx.buf = *buf; + sqe->rx.buf_len = *buf_len; return 0; } @@ -1207,12 +1236,12 @@ static inline int rtio_sqe_rx_buf(const struct rtio_iodev_sqe *iodev_sqe, uint32 ARG_UNUSED(max_buf_len); #endif - if (sqe->buf_len < min_buf_len) { + if (sqe->rx.buf_len < min_buf_len) { return -ENOMEM; } - *buf = sqe->buf; - *buf_len = sqe->buf_len; + *buf = sqe->rx.buf; + *buf_len = sqe->rx.buf_len; return 0; } @@ -1381,12 +1410,7 @@ static inline int z_impl_rtio_cqe_copy_out(struct rtio *r, cqe = K_TIMEOUT_EQ(timeout, K_FOREVER) ? rtio_cqe_consume_block(r) : rtio_cqe_consume(r); if (cqe == NULL) { -#ifdef CONFIG_BOARD_NATIVE_POSIX - /* Native posix fakes the clock and only moves it forward when sleeping. */ - k_sleep(K_TICKS(1)); -#else - Z_SPIN_DELAY(1); -#endif + Z_SPIN_DELAY(25); continue; } cqes[copied++] = *cqe; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/settings/settings.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/settings/settings.h index 99b9fc21..f22f1aba 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/settings/settings.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/settings/settings.h @@ -70,6 +70,9 @@ struct settings_handler { const char *name; /**< Name of subtree. */ + int cprio; + /**< Priority of commit, lower value is higher priority */ + int (*h_get)(const char *key, char *val, int val_len_max); /**< Get values handler of settings items identified by keyword names. * @@ -136,6 +139,9 @@ struct settings_handler_static { const char *name; /**< Name of subtree. */ + int cprio; + /**< Priority of commit, lower value is higher priority */ + int (*h_get)(const char *key, char *val, int val_len_max); /**< Get values handler of settings items identified by keyword names. * @@ -196,22 +202,30 @@ struct settings_handler_static { * @param _set set routine (can be NULL) * @param _commit commit routine (can be NULL) * @param _export export routine (can be NULL) + * @param _cprio commit priority (lower value is higher priority) * * This creates a variable _hname prepended by settings_handler_. * */ -#define SETTINGS_STATIC_HANDLER_DEFINE(_hname, _tree, _get, _set, _commit, \ - _export) \ +#define SETTINGS_STATIC_HANDLER_DEFINE_WITH_CPRIO(_hname, _tree, _get, _set, \ + _commit, _export, _cprio) \ const STRUCT_SECTION_ITERABLE(settings_handler_static, \ settings_handler_ ## _hname) = { \ .name = _tree, \ + .cprio = _cprio, \ .h_get = _get, \ .h_set = _set, \ .h_commit = _commit, \ .h_export = _export, \ } +/* Handlers without commit priority are set to priority O */ +#define SETTINGS_STATIC_HANDLER_DEFINE(_hname, _tree, _get, _set, _commit, \ + _export) \ + SETTINGS_STATIC_HANDLER_DEFINE_WITH_CPRIO(_hname, _tree, _get, _set, \ + _commit, _export, 0) + /** * Initialization of settings and backend * @@ -224,7 +238,20 @@ struct settings_handler_static { int settings_subsys_init(void); /** - * Register a handler for settings items stored in RAM. + * Register a handler for settings items stored in RAM with + * commit priority. + * + * @param cf Structure containing registration info. + * @param cprio Commit priority (lower value is higher priority). + * + * @return 0 on success, non-zero on failure. + */ +int settings_register_with_cprio(struct settings_handler *cf, + int cprio); + +/** + * Register a handler for settings items stored in RAM with + * commit priority set to default. * * @param cf Structure containing registration info. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell.h index d99baf00..9f7d18f7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell.h @@ -159,6 +159,28 @@ typedef bool (*shell_device_filter_t)(const struct device *dev); const struct device *shell_device_filter(size_t idx, shell_device_filter_t filter); +/** + * @brief Get a @ref device reference from its @ref device.name field or label. + * + * This function iterates through the devices on the system. If a device with + * the given @p name field is found, and that device initialized successfully at + * boot time, this function returns a pointer to the device. + * + * If no device has the given @p name, this function returns `NULL`. + * + * This function also returns NULL when a device is found, but it failed to + * initialize successfully at boot time. (To troubleshoot this case, set a + * breakpoint on your device driver's initialization function.) + * + * @param name device name to search for. A null pointer, or a pointer to an + * empty string, will cause NULL to be returned. + * + * @return pointer to device structure with the given name; `NULL` if the device + * is not found or if the device with that name's initialization function + * failed. + */ +const struct device *shell_device_get_binding(const char *name); + /** * @brief Shell command handler prototype. * @@ -191,7 +213,7 @@ typedef int (*shell_dict_cmd_handler)(const struct shell *sh, size_t argc, char **argv, void *data); /* When entries are added to the memory section a padding is applied for - * native_posix_64 and x86_64 targets. Adding padding to allow handle data + * the posix architecture with 64bits builds and x86_64 targets. Adding padding to allow handle data * in the memory section as array. */ #if (defined(CONFIG_ARCH_POSIX) && defined(CONFIG_64BIT)) || defined(CONFIG_X86_64) @@ -912,6 +934,41 @@ struct shell { extern void z_shell_print_stream(const void *user_ctx, const char *data, size_t data_len); + +/** @brief Internal macro for defining a shell instance. + * + * As it does not create the default shell logging backend it allows to use + * custom approach for integrating logging with shell. + * + * @param[in] _name Instance name. + * @param[in] _prompt Shell default prompt string. + * @param[in] _transport_iface Pointer to the transport interface. + * @param[in] _out_buf Output buffer. + * @param[in] _log_backend Pointer to the log backend instance. + * @param[in] _shell_flag Shell output newline sequence. + */ +#define Z_SHELL_DEFINE(_name, _prompt, _transport_iface, _out_buf, _log_backend, _shell_flag) \ + static const struct shell _name; \ + static struct shell_ctx UTIL_CAT(_name, _ctx); \ + Z_SHELL_HISTORY_DEFINE(_name##_history, CONFIG_SHELL_HISTORY_BUFFER); \ + Z_SHELL_FPRINTF_DEFINE(_name##_fprintf, &_name, _out_buf, CONFIG_SHELL_PRINTF_BUFF_SIZE, \ + true, z_shell_print_stream); \ + LOG_INSTANCE_REGISTER(shell, _name, CONFIG_SHELL_LOG_LEVEL); \ + Z_SHELL_STATS_DEFINE(_name); \ + static K_KERNEL_STACK_DEFINE(_name##_stack, CONFIG_SHELL_STACK_SIZE); \ + static struct k_thread _name##_thread; \ + static const STRUCT_SECTION_ITERABLE(shell, _name) = { \ + .default_prompt = _prompt, \ + .iface = _transport_iface, \ + .ctx = &UTIL_CAT(_name, _ctx), \ + .history = IS_ENABLED(CONFIG_SHELL_HISTORY) ? &_name##_history : NULL, \ + .shell_flag = _shell_flag, \ + .fprintf_ctx = &_name##_fprintf, \ + .stats = Z_SHELL_STATS_PTR(_name), \ + .log_backend = _log_backend, \ + LOG_INSTANCE_PTR_INIT(log, shell, _name).name = \ + STRINGIFY(_name), .thread = &_name##_thread, .stack = _name##_stack} + /** * @brief Macro for defining a shell instance. * @@ -925,37 +982,12 @@ extern void z_shell_print_stream(const void *user_ctx, const char *data, * message is dropped. * @param[in] _shell_flag Shell output newline sequence. */ -#define SHELL_DEFINE(_name, _prompt, _transport_iface, \ - _log_queue_size, _log_timeout, _shell_flag) \ - static const struct shell _name; \ - static struct shell_ctx UTIL_CAT(_name, _ctx); \ - static uint8_t _name##_out_buffer[CONFIG_SHELL_PRINTF_BUFF_SIZE]; \ - Z_SHELL_LOG_BACKEND_DEFINE(_name, _name##_out_buffer, \ - CONFIG_SHELL_PRINTF_BUFF_SIZE, \ - _log_queue_size, _log_timeout); \ - Z_SHELL_HISTORY_DEFINE(_name##_history, CONFIG_SHELL_HISTORY_BUFFER); \ - Z_SHELL_FPRINTF_DEFINE(_name##_fprintf, &_name, _name##_out_buffer, \ - CONFIG_SHELL_PRINTF_BUFF_SIZE, \ - true, z_shell_print_stream); \ - LOG_INSTANCE_REGISTER(shell, _name, CONFIG_SHELL_LOG_LEVEL); \ - Z_SHELL_STATS_DEFINE(_name); \ - static K_KERNEL_STACK_DEFINE(_name##_stack, CONFIG_SHELL_STACK_SIZE); \ - static struct k_thread _name##_thread; \ - static const STRUCT_SECTION_ITERABLE(shell, _name) = { \ - .default_prompt = _prompt, \ - .iface = _transport_iface, \ - .ctx = &UTIL_CAT(_name, _ctx), \ - .history = IS_ENABLED(CONFIG_SHELL_HISTORY) ? \ - &_name##_history : NULL, \ - .shell_flag = _shell_flag, \ - .fprintf_ctx = &_name##_fprintf, \ - .stats = Z_SHELL_STATS_PTR(_name), \ - .log_backend = Z_SHELL_LOG_BACKEND_PTR(_name), \ - LOG_INSTANCE_PTR_INIT(log, shell, _name) \ - .name = STRINGIFY(_name), \ - .thread = &_name##_thread, \ - .stack = _name##_stack \ - } +#define SHELL_DEFINE(_name, _prompt, _transport_iface, _log_queue_size, _log_timeout, _shell_flag) \ + static uint8_t _name##_out_buffer[CONFIG_SHELL_PRINTF_BUFF_SIZE]; \ + Z_SHELL_LOG_BACKEND_DEFINE(_name, _name##_out_buffer, CONFIG_SHELL_PRINTF_BUFF_SIZE, \ + _log_queue_size, _log_timeout); \ + Z_SHELL_DEFINE(_name, _prompt, _transport_iface, _name##_out_buffer, \ + Z_SHELL_LOG_BACKEND_PTR(_name), _shell_flag) /** * @brief Function for initializing a transport layer and internal shell state. @@ -1093,7 +1125,8 @@ void shell_hexdump(const struct shell *sh, const uint8_t *data, size_t len); * @param[in] ... List of parameters to print. */ #define shell_info(_sh, _ft, ...) \ - shell_fprintf(_sh, SHELL_INFO, _ft "\n", ##__VA_ARGS__) + shell_fprintf_info(_sh, _ft "\n", ##__VA_ARGS__) +void __printf_like(2, 3) shell_fprintf_info(const struct shell *sh, const char *fmt, ...); /** * @brief Print normal message to the shell. @@ -1105,7 +1138,8 @@ void shell_hexdump(const struct shell *sh, const uint8_t *data, size_t len); * @param[in] ... List of parameters to print. */ #define shell_print(_sh, _ft, ...) \ - shell_fprintf(_sh, SHELL_NORMAL, _ft "\n", ##__VA_ARGS__) + shell_fprintf_normal(_sh, _ft "\n", ##__VA_ARGS__) +void __printf_like(2, 3) shell_fprintf_normal(const struct shell *sh, const char *fmt, ...); /** * @brief Print warning message to the shell. @@ -1117,7 +1151,8 @@ void shell_hexdump(const struct shell *sh, const uint8_t *data, size_t len); * @param[in] ... List of parameters to print. */ #define shell_warn(_sh, _ft, ...) \ - shell_fprintf(_sh, SHELL_WARNING, _ft "\n", ##__VA_ARGS__) + shell_fprintf_warn(_sh, _ft "\n", ##__VA_ARGS__) +void __printf_like(2, 3) shell_fprintf_warn(const struct shell *sh, const char *fmt, ...); /** * @brief Print error message to the shell. @@ -1129,7 +1164,8 @@ void shell_hexdump(const struct shell *sh, const uint8_t *data, size_t len); * @param[in] ... List of parameters to print. */ #define shell_error(_sh, _ft, ...) \ - shell_fprintf(_sh, SHELL_ERROR, _ft "\n", ##__VA_ARGS__) + shell_fprintf_error(_sh, _ft "\n", ##__VA_ARGS__) +void __printf_like(2, 3) shell_fprintf_error(const struct shell *sh, const char *fmt, ...); /** * @brief Process function, which should be executed when data is ready in the diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_backend.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_backend.h index ae8f8a5a..d0611f92 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_backend.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_backend.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_BACKEND_H__ -#define SHELL_BACKEND_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_BACKEND_H_ +#define ZEPHYR_INCLUDE_SHELL_BACKEND_H_ #include #include @@ -58,4 +58,4 @@ const struct shell *shell_backend_get_by_name(const char *backend_name); } #endif -#endif /* SHELL_BACKEND_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_BACKEND_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_dummy.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_dummy.h index 43dc4a86..bd520f4a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_dummy.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_dummy.h @@ -6,8 +6,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_DUMMY_H__ -#define SHELL_DUMMY_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_DUMMY_H_ +#define ZEPHYR_INCLUDE_SHELL_DUMMY_H_ #include @@ -68,4 +68,4 @@ void shell_backend_dummy_clear_output(const struct shell *sh); } #endif -#endif /* SHELL_DUMMY_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_DUMMY_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_fprintf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_fprintf.h index 979e88eb..aaac65ea 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_fprintf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_fprintf.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_FPRINTF_H__ -#define SHELL_FPRINTF_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_FPRINTF_H_ +#define ZEPHYR_INCLUDE_SHELL_FPRINTF_H_ #include #include @@ -80,4 +80,4 @@ void z_shell_fprintf_buffer_flush(const struct shell_fprintf *sh_fprintf); } #endif -#endif /* SHELL_FPRINTF_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_FPRINTF_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_history.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_history.h index 91483357..1ddf69b7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_history.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_history.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_HISTORY_H__ -#define SHELL_HISTORY_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_HISTORY_H_ +#define ZEPHYR_INCLUDE_SHELL_HISTORY_H_ #include #include @@ -111,4 +111,4 @@ static inline bool z_shell_history_active(struct shell_history *history) } #endif -#endif /* SHELL_HISTORY_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_HISTORY_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_log_backend.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_log_backend.h index 620709ff..327e82d8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_log_backend.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_log_backend.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_LOG_BACKEND_H__ -#define SHELL_LOG_BACKEND_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_LOG_BACKEND_H_ +#define ZEPHYR_INCLUDE_SHELL_LOG_BACKEND_H_ #include #include @@ -124,4 +124,4 @@ bool z_shell_log_backend_process(const struct shell_log_backend *backend); } #endif -#endif /* SHELL_LOG_BACKEND_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_LOG_BACKEND_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_mqtt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_mqtt.h index 72e597e6..92ce6987 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_mqtt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_mqtt.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_MQTT_H__ -#define SHELL_MQTT_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_MQTT_H_ +#define ZEPHYR_INCLUDE_SHELL_MQTT_H_ #include #include @@ -137,4 +137,4 @@ bool shell_mqtt_get_devid(char *id, int id_max_len); } #endif -#endif /* SHELL_MQTT_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_MQTT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rpmsg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rpmsg.h index 7a79c74c..726cab47 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rpmsg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rpmsg.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_RPMSG_H__ -#define SHELL_RPMSG_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_RPMSG_H_ +#define ZEPHYR_INCLUDE_SHELL_RPMSG_H_ #include #include @@ -84,4 +84,4 @@ const struct shell *shell_backend_rpmsg_get_ptr(void); } #endif -#endif /* SHELL_RPMSG_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_RPMSG_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rtt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rtt.h index ab1e60d9..930e5fff 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rtt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_rtt.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_RTT_H__ -#define SHELL_RTT_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_RTT_H_ +#define ZEPHYR_INCLUDE_SHELL_RTT_H_ #include @@ -41,4 +41,4 @@ const struct shell *shell_backend_rtt_get_ptr(void); } #endif -#endif /* SHELL_RTT_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_RTT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_string_conv.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_string_conv.h index 3b072426..0fed0b23 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_string_conv.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_string_conv.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_STRING_CONV_H__ -#define SHELL_STRING_CONV_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_STRING_CONV_H_ +#define ZEPHYR_INCLUDE_SHELL_STRING_CONV_H_ #include #include @@ -86,4 +86,4 @@ bool shell_strtobool(const char *str, int base, int *err); } #endif -#endif /* SHELL_STRING_CONV_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_STRING_CONV_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_telnet.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_telnet.h index 6501a63f..a3ed366e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_telnet.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_telnet.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_TELNET_H__ -#define SHELL_TELNET_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_TELNET_H_ +#define ZEPHYR_INCLUDE_SHELL_TELNET_H_ #include #include @@ -85,4 +85,4 @@ const struct shell *shell_backend_telnet_get_ptr(void); } #endif -#endif /* SHELL_TELNET_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_TELNET_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_types.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_types.h index a45f0c17..609c450c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_types.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_types.h @@ -3,8 +3,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_TYPES_H__ -#define SHELL_TYPES_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_TYPES_H_ +#define ZEPHYR_INCLUDE_SHELL_TYPES_H_ #ifdef __cplusplus @@ -51,4 +51,4 @@ struct shell_vt100_ctx { } #endif -#endif /* SHELL_TYPES_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_TYPES_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_uart.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_uart.h index e424a185..d1a8a4df 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_uart.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_uart.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef SHELL_UART_H__ -#define SHELL_UART_H__ +#ifndef ZEPHYR_INCLUDE_SHELL_UART_H_ +#define ZEPHYR_INCLUDE_SHELL_UART_H_ #include #include @@ -115,4 +115,4 @@ struct smp_shell_data *shell_uart_smp_shell_data_get_ptr(void); } #endif -#endif /* SHELL_UART_H__ */ +#endif /* ZEPHYR_INCLUDE_SHELL_UART_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_websocket.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_websocket.h new file mode 100644 index 00000000..12bd4972 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/shell/shell_websocket.h @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_SHELL_WEBSOCKET_H_ +#define ZEPHYR_INCLUDE_SHELL_WEBSOCKET_H_ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SHELL_WEBSOCKET_SERVICE_COUNT CONFIG_SHELL_WEBSOCKET_BACKEND_COUNT + +/** Line buffer structure. */ +struct shell_websocket_line_buf { + /** Line buffer. */ + char buf[CONFIG_SHELL_WEBSOCKET_LINE_BUF_SIZE]; + + /** Current line length. */ + uint16_t len; +}; + +/** WEBSOCKET-based shell transport. */ +struct shell_websocket { + /** Handler function registered by shell. */ + shell_transport_handler_t shell_handler; + + /** Context registered by shell. */ + void *shell_context; + + /** Buffer for outgoing line. */ + struct shell_websocket_line_buf line_out; + + /** Array for sockets used by the websocket service. */ + struct zsock_pollfd fds[1]; + + /** Input buffer. */ + uint8_t rx_buf[CONFIG_SHELL_CMD_BUFF_SIZE]; + + /** Number of data bytes within the input buffer. */ + size_t rx_len; + + /** Mutex protecting the input buffer access. */ + struct k_mutex rx_lock; + + /** The delayed work is used to send non-lf terminated output that has + * been around for "too long". This will prove to be useful + * to send the shell prompt for instance. + */ + struct k_work_delayable send_work; + struct k_work_sync work_sync; + + /** If set, no output is sent to the WEBSOCKET client. */ + bool output_lock; +}; + +extern const struct shell_transport_api shell_websocket_transport_api; +extern int shell_websocket_setup(int ws_socket, void *user_data); +extern int shell_websocket_enable(const struct shell *sh); + +#define GET_WS_NAME(_service) ws_ctx_##_service +#define GET_WS_SHELL_NAME(_name) shell_websocket_##_name +#define GET_WS_TRANSPORT_NAME(_service) transport_shell_ws_##_service +#define GET_WS_DETAIL_NAME(_service) ws_res_detail_##_service + +#define SHELL_WEBSOCKET_DEFINE(_service) \ + static struct shell_websocket GET_WS_NAME(_service); \ + static struct shell_transport GET_WS_TRANSPORT_NAME(_service) = { \ + .api = &shell_websocket_transport_api, \ + .ctx = &GET_WS_NAME(_service), \ + } + +#define SHELL_WS_PORT_NAME(_service) http_service_##_service +#define SHELL_WS_BUF_NAME(_service) ws_recv_buffer_##_service +#define SHELL_WS_TEMP_RECV_BUF_SIZE 256 + +#define DEFINE_WEBSOCKET_HTTP_SERVICE(_service) \ + uint8_t SHELL_WS_BUF_NAME(_service)[SHELL_WS_TEMP_RECV_BUF_SIZE]; \ + struct http_resource_detail_websocket \ + GET_WS_DETAIL_NAME(_service) = { \ + .common = { \ + .type = HTTP_RESOURCE_TYPE_WEBSOCKET, \ + \ + /* We need HTTP/1.1 GET method for upgrading */ \ + .bitmask_of_supported_http_methods = BIT(HTTP_GET), \ + }, \ + .cb = shell_websocket_setup, \ + .data_buffer = SHELL_WS_BUF_NAME(_service), \ + .data_buffer_len = sizeof(SHELL_WS_BUF_NAME(_service)), \ + .user_data = &GET_WS_NAME(_service), \ + }; \ + HTTP_RESOURCE_DEFINE(ws_resource_##_service, _service, \ + "/" CONFIG_SHELL_WEBSOCKET_ENDPOINT_URL, \ + &GET_WS_DETAIL_NAME(_service)) + +#define DEFINE_WEBSOCKET_SERVICE(_service) \ + SHELL_WEBSOCKET_DEFINE(_service); \ + SHELL_DEFINE(shell_websocket_##_service, \ + CONFIG_SHELL_WEBSOCKET_PROMPT, \ + &GET_WS_TRANSPORT_NAME(_service), \ + CONFIG_SHELL_WEBSOCKET_LOG_MESSAGE_QUEUE_SIZE, \ + CONFIG_SHELL_WEBSOCKET_LOG_MESSAGE_QUEUE_TIMEOUT, \ + SHELL_FLAG_OLF_CRLF); \ + DEFINE_WEBSOCKET_HTTP_SERVICE(_service) + +#if defined(CONFIG_NET_SOCKETS_SOCKOPT_TLS) +/* Use a secure connection only for Websocket. */ +#define WEBSOCKET_CONSOLE_DEFINE(_service, _sec_tag_list, _sec_tag_list_size) \ + static uint16_t SHELL_WS_PORT_NAME(_service) = \ + CONFIG_SHELL_WEBSOCKET_PORT; \ + HTTPS_SERVICE_DEFINE(_service, \ + CONFIG_SHELL_WEBSOCKET_IP_ADDR, \ + &SHELL_WS_PORT_NAME(_service), \ + SHELL_WEBSOCKET_SERVICE_COUNT, \ + SHELL_WEBSOCKET_SERVICE_COUNT, \ + NULL, \ + _sec_tag_list, \ + _sec_tag_list_size); \ + DEFINE_WEBSOCKET_SERVICE(_service); \ + + +#else /* CONFIG_NET_SOCKETS_SOCKOPT_TLS */ +/* TLS not possible so define only normal HTTP service */ +#define WEBSOCKET_CONSOLE_DEFINE(_service, _sec_tag_list, _sec_tag_list_size) \ + static uint16_t SHELL_WS_PORT_NAME(_service) = \ + CONFIG_SHELL_WEBSOCKET_PORT; \ + HTTP_SERVICE_DEFINE(_service, \ + CONFIG_SHELL_WEBSOCKET_IP_ADDR, \ + &SHELL_WS_PORT_NAME(_service), \ + SHELL_WEBSOCKET_SERVICE_COUNT, \ + SHELL_WEBSOCKET_SERVICE_COUNT, \ + NULL); \ + DEFINE_WEBSOCKET_SERVICE(_service) + +#endif /* CONFIG_NET_SOCKETS_SOCKOPT_TLS */ + +#define WEBSOCKET_CONSOLE_ENABLE(_service) \ + (void)shell_websocket_enable(&GET_WS_SHELL_NAME(_service)) + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_SHELL_WEBSOCKET_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/flash_map.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/flash_map.h index 937e2428..cdd9ae00 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/flash_map.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/flash_map.h @@ -45,11 +45,6 @@ extern "C" { #endif -/** Provided for compatibility with MCUboot */ -#define SOC_FLASH_0_ID 0 -/** Provided for compatibility with MCUboot */ -#define SPI_FLASH_0_ID 1 - /** * @brief Flash partition * @@ -138,6 +133,27 @@ int flash_area_open(uint8_t id, const struct flash_area **fa); */ void flash_area_close(const struct flash_area *fa); +/** + * @brief Verify that a device assigned to flash area is ready for use. + * + * Indicates whether the provided flash area has a device known to be + * in a state where it can be used with Flash Map API. + * + * This can be used with struct flash_area pointers captured from FIXED_PARTITION(). + * At minimum this means that the device has been successfully initialized. + * + * @param fa pointer to flash_area object to check. + * + * @retval true If the device is ready for use. + * @retval false If the device is not ready for use or if a NULL pointer is + * passed as flash area pointer or device pointer within flash area object + * is NULL. + */ +static ALWAYS_INLINE bool flash_area_device_is_ready(const struct flash_area *fa) +{ + return (fa != NULL && device_is_ready(fa->fa_dev)); +} + /** * @brief Read flash area data * @@ -237,6 +253,20 @@ uint32_t flash_area_align(const struct flash_area *fa); int flash_area_get_sectors(int fa_id, uint32_t *count, struct flash_sector *sectors); +/** + * Retrieve info about sectors within the area. + * + * @param[in] fa pointer to flash area object. + * @param[out] sectors buffer for sectors data + * @param[in,out] count On input Capacity of @p sectors, on output number of + * sectors retrieved. + * + * @return 0 on success, negative errno code on fail. Especially returns + * -ENOMEM if There are too many flash pages on the flash_area to fit in the + * array. + */ +int flash_area_sectors(const struct flash_area *fa, uint32_t *count, struct flash_sector *sectors); + /** * Flash map iteration callback * @@ -381,6 +411,32 @@ uint8_t flash_area_erased_val(const struct flash_area *fa); #define FIXED_PARTITION_NODE_DEVICE(node) \ DEVICE_DT_GET(DT_MTD_FROM_FIXED_PARTITION(node)) +/** + * Get pointer to flash_area object by partition label + * + * @param label DTS node label of a partition + * + * @return Pointer to flash_area type object representing partition + */ +#define FIXED_PARTITION(label) FIXED_PARTITION_1(DT_NODELABEL(label)) +#define FIXED_PARTITION_1(node) FIXED_PARTITION_0(DT_DEP_ORD(node)) +#define FIXED_PARTITION_0(ord) \ + ((const struct flash_area *)&DT_CAT(global_fixed_partition_ORD_, ord)) + +/** @cond INTERNAL_HIDDEN */ +#define DECLARE_PARTITION(node) DECLARE_PARTITION_0(DT_DEP_ORD(node)) +#define DECLARE_PARTITION_0(ord) \ + extern const struct flash_area DT_CAT(global_fixed_partition_ORD_, ord); +#define FOR_EACH_PARTITION_TABLE(table) DT_FOREACH_CHILD(table, DECLARE_PARTITION) + +/* Generate declarations */ +DT_FOREACH_STATUS_OKAY(fixed_partitions, FOR_EACH_PARTITION_TABLE) + +#undef DECLARE_PARTITION +#undef DECLARE_PARTITION_0 +#undef FOR_EACH_PARTITION_TABLE +/** @endcond */ + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/stream_flash.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/stream_flash.h index bc871dba..b1d78af9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/stream_flash.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/storage/stream_flash.h @@ -97,7 +97,7 @@ int stream_flash_init(struct stream_flash_ctx *ctx, const struct device *fdev, * * @return Number of payload bytes written to flash. */ -size_t stream_flash_bytes_written(struct stream_flash_ctx *ctx); +size_t stream_flash_bytes_written(const struct stream_flash_ctx *ctx); /** * @brief Process input buffers to be written to flash device in single blocks. @@ -149,7 +149,8 @@ int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off); * @param settings_key key to use with the settings module for loading * the stream write progress * - * @return non-negative on success, negative errno code on fail + * @return non-negative on success, -ERANGE in case when @p off is out + * of area designated for stream or negative errno code on fail */ int stream_flash_progress_load(struct stream_flash_ctx *ctx, const char *settings_key); @@ -163,7 +164,7 @@ int stream_flash_progress_load(struct stream_flash_ctx *ctx, * * @return non-negative on success, negative errno code on fail */ -int stream_flash_progress_save(struct stream_flash_ctx *ctx, +int stream_flash_progress_save(const struct stream_flash_ctx *ctx, const char *settings_key); /** @@ -175,7 +176,7 @@ int stream_flash_progress_save(struct stream_flash_ctx *ctx, * * @return non-negative on success, negative errno code on fail */ -int stream_flash_progress_clear(struct stream_flash_ctx *ctx, +int stream_flash_progress_clear(const struct stream_flash_ctx *ctx, const char *settings_key); #ifdef __cplusplus diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/atomic.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/atomic.h index 86ba2cdf..078be968 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/atomic.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/atomic.h @@ -73,7 +73,7 @@ extern "C" { * @cond INTERNAL_HIDDEN */ -#define ATOMIC_BITS (sizeof(atomic_val_t) * 8) +#define ATOMIC_BITS (sizeof(atomic_val_t) * BITS_PER_BYTE) #define ATOMIC_MASK(bit) BIT((unsigned long)(bit) & (ATOMIC_BITS - 1U)) #define ATOMIC_ELEM(addr, bit) ((addr) + ((bit) / ATOMIC_BITS)) @@ -112,9 +112,9 @@ extern "C" { atomic_t name[ATOMIC_BITMAP_SIZE(num_bits)] /** - * @brief Atomically test a bit. + * @brief Atomically get and test a bit. * - * This routine tests whether bit number @a bit of @a target is set or not. + * Atomically get a value and then test whether bit number @a bit of @a target is set or not. * The target may be a single atomic variable or an array of them. * * @note @atomic_api @@ -132,7 +132,7 @@ static inline bool atomic_test_bit(const atomic_t *target, int bit) } /** - * @brief Atomically test and clear a bit. + * @brief Atomically clear a bit and test it. * * Atomically clear bit number @a bit of @a target and return its old value. * The target may be a single atomic variable or an array of them. @@ -155,7 +155,7 @@ static inline bool atomic_test_and_clear_bit(atomic_t *target, int bit) } /** - * @brief Atomically set a bit. + * @brief Atomically set a bit and test it. * * Atomically set bit number @a bit of @a target and return its old value. * The target may be a single atomic variable or an array of them. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/cbprintf.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/cbprintf.h index 6a160a62..2685448d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/cbprintf.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/cbprintf.h @@ -216,8 +216,6 @@ BUILD_ASSERT(Z_IS_POW2(CBPRINTF_PACKAGE_ALIGNMENT)); * are also checked and if determined to be read-only they are also copied. */ #define CBPRINTF_PACKAGE_CONVERT_RO_STR BIT(0) -/** @deprecated Use @ref CBPRINTF_PACKAGE_CONVERT_RO_STR instead. */ -#define CBPRINTF_PACKAGE_COPY_RO_STR CBPRINTF_PACKAGE_CONVERT_RO_STR __DEPRECATED_MACRO /** @brief Append read-write strings from source package to destination package. * @@ -230,8 +228,6 @@ BUILD_ASSERT(Z_IS_POW2(CBPRINTF_PACKAGE_ALIGNMENT)); * package if @ref CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR is set. */ #define CBPRINTF_PACKAGE_CONVERT_RW_STR BIT(1) -/** @deprecated Use @ref CBPRINTF_PACKAGE_CONVERT_RW_STR instead. */ -#define CBPRINTF_PACKAGE_COPY_RW_STR CBPRINTF_PACKAGE_CONVERT_RW_STR __DEPRECATED_MACRO /** @brief Keep read-only location indexes in the package. * @@ -239,8 +235,6 @@ BUILD_ASSERT(Z_IS_POW2(CBPRINTF_PACKAGE_ALIGNMENT)); * not set they are discarded. */ #define CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR BIT(2) -/** @deprecated Use @ref CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR instead. */ -#define CBPRINTF_PACKAGE_COPY_KEEP_RO_STR CBPRINTF_PACKAGE_CONVERT_KEEP_RO_STR __DEPRECATED_MACRO /** @brief Check format string if %p argument was treated as %s in the package. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/crc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/crc.h index c16281b1..7a0c33cf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/crc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/crc.h @@ -29,6 +29,7 @@ extern "C" { * computation. */ #define CRC8_CCITT_INITIAL_VALUE 0xFF +#define CRC8_ROHC_INITIAL_VALUE 0xFF /* Initial value expected to be used at the beginning of the OpenPGP CRC-24 computation. */ #define CRC24_PGP_INITIAL_VALUE 0x00B704CEU @@ -58,9 +59,10 @@ enum crc_type { CRC4, /**< Use @ref crc4 */ CRC4_TI, /**< Use @ref crc4_ti */ CRC7_BE, /**< Use @ref crc7_be */ - CRC8, /**< Use @ref crc8 */ + CRC8, /**< Use @ref crc8 */ CRC8_CCITT, /**< Use @ref crc8_ccitt */ - CRC16, /**< Use @ref crc16 */ + CRC8_ROHC, /**< Use @ref crc8_rohc */ + CRC16, /**< Use @ref crc16 */ CRC16_ANSI, /**< Use @ref crc16_ansi */ CRC16_CCITT, /**< Use @ref crc16_ccitt */ CRC16_ITU_T, /**< Use @ref crc16_itu_t */ @@ -135,7 +137,7 @@ uint16_t crc16_reflect(uint16_t poly, uint16_t seed, const uint8_t *src, size_t * @return The computed CRC8 value */ uint8_t crc8(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, - bool reversed); + bool reversed); /** * @brief Compute the checksum of a buffer with polynomial 0x1021, reflecting @@ -274,6 +276,20 @@ uint32_t crc32_c(uint32_t crc, const uint8_t *data, */ uint8_t crc8_ccitt(uint8_t initial_value, const void *buf, size_t len); +/** + * @brief Compute ROHC variant of CRC 8 + * + * ROHC (Robust Header Compression) variant of CRC 8. + * Uses 0x07 as the polynomial with reflection. + * + * @param initial_value Initial value for the CRC computation + * @param buf Input bytes for the computation + * @param len Length of the input in bytes + * + * @return The computed CRC8 value + */ +uint8_t crc8_rohc(uint8_t initial_value, const void *buf, size_t len); + /** * @brief Compute the CRC-7 checksum of a buffer. * @@ -322,7 +338,7 @@ uint8_t crc4_ti(uint8_t seed, const uint8_t *src, size_t len); * @return The computed CRC4 value */ uint8_t crc4(const uint8_t *src, size_t len, uint8_t polynomial, uint8_t initial_value, - bool reversed); + bool reversed); /** * @brief Generate an OpenPGP CRC-24 checksum as defined in RFC 4880 section 6.1. @@ -384,6 +400,8 @@ static inline uint32_t crc_by_type(enum crc_type type, const uint8_t *src, size_ return crc8(src, len, poly, seed, reflect); case CRC8_CCITT: return crc8_ccitt(seed, src, len); + case CRC8_ROHC: + return crc8_rohc(seed, src, len); case CRC16: if (reflect) { return crc16_reflect(poly, seed, src, len); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/errno_private.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/errno_private.h index 5adba7bf..c8965060 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/errno_private.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/errno_private.h @@ -8,6 +8,7 @@ #define ZEPHYR_INCLUDE_SYS_ERRNO_PRIVATE_H_ #include +#include /* For Z_THREAD_LOCAL */ #ifdef __cplusplus extern "C" { @@ -26,7 +27,7 @@ static inline int *z_errno(void) } #elif defined(CONFIG_ERRNO_IN_TLS) -extern __thread int z_errno_var; +extern Z_THREAD_LOCAL int z_errno_var; static inline int *z_errno(void) { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/fdtable.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/fdtable.h index 785df8d4..3d0b7149 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/fdtable.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/fdtable.h @@ -7,9 +7,10 @@ #define ZEPHYR_INCLUDE_SYS_FDTABLE_H_ #include -#include +#include + /* FIXME: For native_posix ssize_t, off_t. */ -#include +#include #include #include @@ -27,10 +28,29 @@ #define ZVFS_MODE_IFLNK 0120000 #define ZVFS_MODE_IFSOCK 0140000 +#define ZVFS_POLLIN BIT(0) +#define ZVFS_POLLPRI BIT(1) +#define ZVFS_POLLOUT BIT(2) +#define ZVFS_POLLERR BIT(3) +#define ZVFS_POLLHUP BIT(4) +#define ZVFS_POLLNVAL BIT(5) + #ifdef __cplusplus extern "C" { #endif +/* FIXME: use k_off_t and k_ssize_t to avoid the POSIX->Zephyr->POSIX dependency cycle */ +#ifdef CONFIG_NEWLIB_LIBC +#ifndef _OFF_T_DECLARED +typedef __off_t off_t; +#define _OFF_T_DECLARED +#endif +#ifndef _SSIZE_T_DECLARED +typedef _ssize_t ssize_t; +#define _SSIZE_T_DECLARED +#endif +#endif + /** * File descriptor virtual method table. * Currently all operations beyond read/write/close go thru ioctl method. @@ -44,7 +64,10 @@ struct fd_op_vtable { ssize_t (*write)(void *obj, const void *buf, size_t sz); ssize_t (*write_offs)(void *obj, const void *buf, size_t sz, size_t offset); }; - int (*close)(void *obj); + union { + int (*close)(void *obj); + int (*close2)(void *obj, int fd); + }; int (*ioctl)(void *obj, unsigned int request, va_list args); }; @@ -192,6 +215,31 @@ static inline int zvfs_fdtable_call_ioctl(const struct fd_op_vtable *vtable, voi return res; } +struct zvfs_pollfd { + int fd; + short events; + short revents; +}; + +__syscall int zvfs_poll(struct zvfs_pollfd *fds, int nfds, int poll_timeout); + +struct zvfs_fd_set { + uint32_t bitset[(CONFIG_ZVFS_OPEN_MAX + 31) / 32]; +}; + +/** @brief Number of file descriptors which can be added @ref zvfs_fd_set */ +#define ZVFS_FD_SETSIZE (sizeof(((struct zvfs_fd_set *)0)->bitset) * 8) + +void ZVFS_FD_CLR(int fd, struct zvfs_fd_set *fdset); +int ZVFS_FD_ISSET(int fd, struct zvfs_fd_set *fdset); +void ZVFS_FD_SET(int fd, struct zvfs_fd_set *fdset); +void ZVFS_FD_ZERO(struct zvfs_fd_set *fdset); + +__syscall int zvfs_select(int nfds, struct zvfs_fd_set *ZRESTRICT readfds, + struct zvfs_fd_set *ZRESTRICT writefds, + struct zvfs_fd_set *ZRESTRICT errorfds, + const struct timespec *ZRESTRICT timeout, const void *ZRESTRICT sigmask); + /** * Request codes for fd_op_vtable.ioctl(). * @@ -221,4 +269,6 @@ enum { } #endif +#include + #endif /* ZEPHYR_INCLUDE_SYS_FDTABLE_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/libc-hooks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/libc-hooks.h index e737fc68..1b420674 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/libc-hooks.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/libc-hooks.h @@ -44,6 +44,8 @@ __syscall size_t zephyr_fwrite(const void *ZRESTRICT ptr, size_t size, #endif /* CONFIG_NEWLIB_LIBC */ +void __stdout_hook_install(int (*hook)(int)); + #ifdef CONFIG_USERSPACE #ifdef CONFIG_COMMON_LIBC_MALLOC @@ -56,7 +58,7 @@ __syscall size_t zephyr_fwrite(const void *ZRESTRICT ptr, size_t size, #define Z_MALLOC_PARTITION_EXISTS 1 #endif -#elif defined(CONFIG_NEWLIB_LIBC) +#elif defined(CONFIG_NEWLIB_LIBC) && !defined(CONFIG_NEWLIB_LIBC_CUSTOM_SBRK) /* If we are using newlib, the heap arena is in one of two areas: * - If we have an MPU that requires power of two alignment, the heap bounds * must be specified in Kconfig via CONFIG_NEWLIB_LIBC_ALIGNED_HEAP_SIZE. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/multi_heap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/multi_heap.h index af970cea..25e61e7e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/multi_heap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/multi_heap.h @@ -168,6 +168,32 @@ const struct sys_multi_heap_rec *sys_multi_heap_get_heap(const struct sys_multi_ */ void sys_multi_heap_free(struct sys_multi_heap *mheap, void *block); +/** @brief Expand the size of an existing allocation on the multi heap + * + * Returns a pointer to a new memory region with the same contents, + * but a different allocated size. If the new allocation can be + * expanded in place, the pointer returned will be identical. + * Otherwise the data will be copies to a new block and the old one + * will be freed as per sys_heap_free(). If the specified size is + * smaller than the original, the block will be truncated in place and + * the remaining memory returned to the heap. If the allocation of a + * new block fails, then NULL will be returned and the old block will + * not be freed or modified. If a new allocation is needed, the choice + * for the heap used will be bases on the cfg parameter (same as in sys_multi_heap_aligned_alloc). + * + * @param mheap Multi heap pointer + * @param cfg Opaque configuration parameter, as for sys_multi_heap_fn_t + * @param ptr Original pointer returned from a previous allocation + * @param align Alignment in bytes, must be a power of two + * @param bytes Number of bytes requested for the new block + * @return Pointer to memory the caller can now use, or NULL + */ +void *sys_multi_heap_aligned_realloc(struct sys_multi_heap *mheap, void *cfg, + void *ptr, size_t align, size_t bytes); + +#define sys_multi_heap_realloc(mheap, cfg, ptr, bytes) \ + sys_multi_heap_aligned_realloc(mheap, cfg, ptr, 0, bytes) + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/poweroff.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/poweroff.h index b4ecabcf..195e4eaf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/poweroff.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/poweroff.h @@ -29,8 +29,6 @@ extern "C" { */ FUNC_NORETURN void z_sys_poweroff(void); -/** @} */ - /** @endcond */ /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/printk-hooks.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/printk-hooks.h new file mode 100644 index 00000000..ef59469e --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/printk-hooks.h @@ -0,0 +1,38 @@ +/* + * Copyright 2024 Google LLC + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_SYS_PRINTK_HOOKS_H_ +#define ZEPHYR_INCLUDE_SYS_PRINTK_HOOKS_H_ + +/** + * @brief printk function handler + * + * @param c Character to output + * + * @returns The character passed as input. + */ +typedef int (*printk_hook_fn_t)(int c); + +/** + * @brief Install the character output routine for printk + * + * To be called by the platform's console driver at init time. Installs a + * routine that outputs one ASCII character at a time. + * @param fn putc routine to install + */ +void __printk_hook_install(printk_hook_fn_t fn); + +/** + * @brief Get the current character output routine for printk + * + * To be called by any console driver that would like to save + * current hook - if any - for later re-installation. + * + * @return a function pointer or NULL if no hook is set + */ +printk_hook_fn_t __printk_get_hook(void); + +#endif /* ZEPHYR_INCLUDE_SYS_PRINTK_HOOKS_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/rb.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/rb.h index 66003ef1..2ce368a9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/rb.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/rb.h @@ -66,8 +66,8 @@ struct rbnode { * packed binary tree, plus root... Works out to 59 entries for 32 * bit pointers and 121 at 64 bits. */ -#define Z_TBITS(t) ((sizeof(t)) < 8 ? 2 : 3) -#define Z_PBITS(t) (8 * sizeof(t)) +#define Z_TBITS(t) ((sizeof(t)) < sizeof(uint64_t) ? 2 : 3) +#define Z_PBITS(t) (BITS_PER_BYTE * sizeof(t)) #define Z_MAX_RBTREE_DEPTH (2 * (Z_PBITS(int *) - Z_TBITS(int *) - 1) + 1) /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/ring_buffer.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/ring_buffer.h index bd2cd5ef..6bec33e9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/ring_buffer.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/ring_buffer.h @@ -174,9 +174,6 @@ static inline void ring_buf_init(struct ring_buf *buf, * Each data item is an array of 32-bit words (from zero to 1020 bytes in * length), coupled with a 16-bit type identifier and an 8-bit integer value. * - * Each data item is an array of 32-bit words (from zero to 1020 bytes in - * length), coupled with a 16-bit type identifier and an 8-bit integer value. - * * @param buf Address of ring buffer. * @param size Ring buffer size (in 32-bit words) * @param data Ring buffer data area (uint32_t data[size]). diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sem.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sem.h index d4e93df4..73e4d873 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sem.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sem.h @@ -23,6 +23,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -138,6 +139,82 @@ int sys_sem_take(struct sys_sem *sem, k_timeout_t timeout); */ unsigned int sys_sem_count_get(struct sys_sem *sem); +/** + * @cond INTERNAL_HIDDEN + */ + +#if defined(__GNUC__) +static ALWAYS_INLINE void z_sys_sem_lock_onexit(__maybe_unused int *rc) +{ + __ASSERT(*rc == 1, "SYS_SEM_LOCK exited with goto, break or return, " + "use SYS_SEM_LOCK_BREAK instead."); +} +#define SYS_SEM_LOCK_ONEXIT __attribute__((__cleanup__(z_sys_sem_lock_onexit))) +#else +#define SYS_SEM_LOCK_ONEXIT +#endif + +/** + * INTERNAL_HIDDEN @endcond + */ + +/** + * @brief Leaves a code block guarded with @ref SYS_SEM_LOCK after releasing the + * lock. + * + * See @ref SYS_SEM_LOCK for details. + */ +#define SYS_SEM_LOCK_BREAK continue + +/** + * @brief Guards a code block with the given sys_sem, automatically acquiring + * the semaphore before executing the code block. The semaphore will be + * released either when reaching the end of the code block or when leaving the + * block with @ref SYS_SEM_LOCK_BREAK. + * + * @details Example usage: + * + * @code{.c} + * SYS_SEM_LOCK(&sem) { + * + * ...execute statements with the semaphore held... + * + * if (some_condition) { + * ...release the lock and leave the guarded section prematurely: + * SYS_SEM_LOCK_BREAK; + * } + * + * ...execute statements with the lock held... + * + * } + * @endcode + * + * Behind the scenes this pattern expands to a for-loop whose body is executed + * exactly once: + * + * @code{.c} + * for (sys_sem_take(&sem, K_FOREVER); ...; sys_sem_give(&sem)) { + * ... + * } + * @endcode + * + * @warning The code block must execute to its end or be left by calling + * @ref SYS_SEM_LOCK_BREAK. Otherwise, e.g. if exiting the block with a break, + * goto or return statement, the semaphore will not be released on exit. + * + * @param sem Semaphore (@ref sys_sem) used to guard the enclosed code block. + */ +#define SYS_SEM_LOCK(sem) \ + for (int __rc SYS_SEM_LOCK_ONEXIT = sys_sem_take((sem), K_FOREVER); ({ \ + __ASSERT(__rc >= 0, "Failed to take sem: %d", __rc); \ + __rc == 0; \ + }); \ + ({ \ + __rc = sys_sem_give((sem)); \ + __ASSERT(__rc == 0, "Failed to give sem: %d", __rc); \ + }), \ + __rc = 1) + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sys_heap.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sys_heap.h index a6a868b8..f01bae18 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sys_heap.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/sys_heap.h @@ -10,6 +10,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -209,7 +210,15 @@ size_t sys_heap_usable_size(struct sys_heap *heap, void *mem); * @param heap Heap to validate * @return true, if the heap is valid, otherwise false */ +#ifdef CONFIG_SYS_HEAP_VALIDATE bool sys_heap_validate(struct sys_heap *heap); +#else +static inline bool sys_heap_validate(struct sys_heap *heap) +{ + ARG_UNUSED(heap); + return true; +} +#endif /** @brief sys_heap stress test rig * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/timeutil.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/timeutil.h index 0f475a72..333ff76a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/timeutil.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/timeutil.h @@ -37,6 +37,9 @@ extern "C" { * @{ */ +/* Base Year value use in calculations in "timeutil_timegm64" API */ +#define TIME_UTILS_BASE_YEAR 1900 + /** * @brief Convert broken-down time to a POSIX epoch offset in seconds. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util.h index 95cf9c6d..6773490c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util.h @@ -30,7 +30,7 @@ #include /** @brief Number of bits that make up a type */ -#define NUM_BITS(t) (sizeof(t) * 8) +#define NUM_BITS(t) (sizeof(t) * BITS_PER_BYTE) #ifdef __cplusplus extern "C" { @@ -57,6 +57,15 @@ extern "C" { # error Missing required predefined macros for BITS_PER_LONG calculation #endif +/** Number of bits in a byte. */ +#define BITS_PER_BYTE (__CHAR_BIT__) + +/** Number of bits in a nibble. */ +#define BITS_PER_NIBBLE (__CHAR_BIT__ / 2) + +/** Number of nibbles in a byte. */ +#define NIBBLES_PER_BYTE (BITS_PER_BYTE / BITS_PER_NIBBLE) + /** Number of bits in a long int. */ #define BITS_PER_LONG (__CHAR_BIT__ * __SIZEOF_LONG__) @@ -77,22 +86,6 @@ extern "C" { #define GENMASK64(h, l) \ (((~0ULL) - (1ULL << (l)) + 1) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) -/** @brief Extract the Least Significant Bit from @p value. */ -#define LSB_GET(value) ((value) & -(value)) - -/** - * @brief Extract a bitfield element from @p value corresponding to - * the field mask @p mask. - */ -#define FIELD_GET(mask, value) (((value) & (mask)) / LSB_GET(mask)) - -/** - * @brief Prepare a bitfield element using @p value with @p mask representing - * its field position and width. The result should be combined - * with other fields using a logical OR. - */ -#define FIELD_PREP(mask, value) (((value) * LSB_GET(mask)) & (mask)) - /** @brief 0 if @p cond is true-ish; causes a compile error otherwise. */ #define ZERO_OR_COMPILE_ERROR(cond) ((int) sizeof(char[1 - 2 * !(cond)]) - 1) @@ -129,6 +122,29 @@ extern "C" { #endif /* __cplusplus */ +/** + * @brief Declare a flexible array member. + * + * This macro declares a flexible array member in a struct. The member + * is named @p name and has type @p type. + * + * Since C99, flexible arrays are part of the C standard, but for historical + * reasons many places still use an older GNU extension that is declare + * zero length arrays. + * + * Although zero length arrays are flexible arrays, we can't blindly + * replace [0] with [] because of some syntax limitations. This macro + * workaround these limitations. + * + * It is specially useful for cases where flexible arrays are + * used in unions or are not the last element in the struct. + */ +#define FLEXIBLE_ARRAY_DECLARE(type, name) \ + struct { \ + struct { } __unused_##name; \ + type name[]; \ + } + /** * @brief Whether @p ptr is an element of @p array * @@ -350,16 +366,10 @@ extern "C" { * * @return The result of @p n / @p d, rounded to the nearest integer. */ -#define DIV_ROUND_CLOSEST(n, d) \ - ((((n) < 0) ^ ((d) < 0)) ? ((n) - ((d) / 2)) / (d) : \ - ((n) + ((d) / 2)) / (d)) - -/** - * @brief Ceiling function applied to @p numerator / @p divider as a fraction. - * @deprecated Use DIV_ROUND_UP() instead. - */ -#define ceiling_fraction(numerator, divider) __DEPRECATED_MACRO \ - DIV_ROUND_UP(numerator, divider) +#define DIV_ROUND_CLOSEST(n, d) \ + (((((__typeof__(n))-1) < 0) && (((__typeof__(d))-1) < 0) && ((n) < 0) ^ ((d) < 0)) \ + ? ((n) - ((d) / 2)) / (d) \ + : ((n) + ((d) / 2)) / (d)) #ifndef MAX /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal.h index 5b57d2f7..8ec41f6c 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal.h @@ -50,7 +50,7 @@ #define Z_IS_ENABLED3(ignore_this, val, ...) val /* Implementation of IS_EQ(). Returns 1 if _0 and _1 are the same integer from - * 0 to 4095, 0 otherwise. + * 0 to 4096, 0 otherwise. */ #define Z_IS_EQ(_0, _1) Z_HAS_COMMA(Z_CAT4(Z_IS_, _0, _EQ_, _1)()) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal_is_eq.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal_is_eq.h index 0734cf35..11657c6a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal_is_eq.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_internal_is_eq.h @@ -13,4102 +13,16393 @@ #ifndef ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_IS_EQ_H_ #define ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_IS_EQ_H_ -#define Z_IS_0_EQ_0(...) \, -#define Z_IS_1_EQ_1(...) \, -#define Z_IS_2_EQ_2(...) \, -#define Z_IS_3_EQ_3(...) \, -#define Z_IS_4_EQ_4(...) \, -#define Z_IS_5_EQ_5(...) \, -#define Z_IS_6_EQ_6(...) \, -#define Z_IS_7_EQ_7(...) \, -#define Z_IS_8_EQ_8(...) \, -#define Z_IS_9_EQ_9(...) \, -#define Z_IS_10_EQ_10(...) \, -#define Z_IS_11_EQ_11(...) \, -#define Z_IS_12_EQ_12(...) \, -#define Z_IS_13_EQ_13(...) \, -#define Z_IS_14_EQ_14(...) \, -#define Z_IS_15_EQ_15(...) \, -#define Z_IS_16_EQ_16(...) \, -#define Z_IS_17_EQ_17(...) \, -#define Z_IS_18_EQ_18(...) \, -#define Z_IS_19_EQ_19(...) \, -#define Z_IS_20_EQ_20(...) \, -#define Z_IS_21_EQ_21(...) \, -#define Z_IS_22_EQ_22(...) \, -#define Z_IS_23_EQ_23(...) \, -#define Z_IS_24_EQ_24(...) \, -#define Z_IS_25_EQ_25(...) \, -#define Z_IS_26_EQ_26(...) \, -#define Z_IS_27_EQ_27(...) \, -#define Z_IS_28_EQ_28(...) \, -#define Z_IS_29_EQ_29(...) \, -#define Z_IS_30_EQ_30(...) \, -#define Z_IS_31_EQ_31(...) \, -#define Z_IS_32_EQ_32(...) \, -#define Z_IS_33_EQ_33(...) \, -#define Z_IS_34_EQ_34(...) \, -#define Z_IS_35_EQ_35(...) \, -#define Z_IS_36_EQ_36(...) \, -#define Z_IS_37_EQ_37(...) \, -#define Z_IS_38_EQ_38(...) \, -#define Z_IS_39_EQ_39(...) \, -#define Z_IS_40_EQ_40(...) \, -#define Z_IS_41_EQ_41(...) \, -#define Z_IS_42_EQ_42(...) \, -#define Z_IS_43_EQ_43(...) \, -#define Z_IS_44_EQ_44(...) \, -#define Z_IS_45_EQ_45(...) \, -#define Z_IS_46_EQ_46(...) \, -#define Z_IS_47_EQ_47(...) \, -#define Z_IS_48_EQ_48(...) \, -#define Z_IS_49_EQ_49(...) \, -#define Z_IS_50_EQ_50(...) \, -#define Z_IS_51_EQ_51(...) \, -#define Z_IS_52_EQ_52(...) \, -#define Z_IS_53_EQ_53(...) \, -#define Z_IS_54_EQ_54(...) \, -#define Z_IS_55_EQ_55(...) \, -#define Z_IS_56_EQ_56(...) \, -#define Z_IS_57_EQ_57(...) \, -#define Z_IS_58_EQ_58(...) \, -#define Z_IS_59_EQ_59(...) \, -#define Z_IS_60_EQ_60(...) \, -#define Z_IS_61_EQ_61(...) \, -#define Z_IS_62_EQ_62(...) \, -#define Z_IS_63_EQ_63(...) \, -#define Z_IS_64_EQ_64(...) \, -#define Z_IS_65_EQ_65(...) \, -#define Z_IS_66_EQ_66(...) \, -#define Z_IS_67_EQ_67(...) \, -#define Z_IS_68_EQ_68(...) \, -#define Z_IS_69_EQ_69(...) \, -#define Z_IS_70_EQ_70(...) \, -#define Z_IS_71_EQ_71(...) \, -#define Z_IS_72_EQ_72(...) \, -#define Z_IS_73_EQ_73(...) \, -#define Z_IS_74_EQ_74(...) \, -#define Z_IS_75_EQ_75(...) \, -#define Z_IS_76_EQ_76(...) \, -#define Z_IS_77_EQ_77(...) \, -#define Z_IS_78_EQ_78(...) \, -#define Z_IS_79_EQ_79(...) \, -#define Z_IS_80_EQ_80(...) \, -#define Z_IS_81_EQ_81(...) \, -#define Z_IS_82_EQ_82(...) \, -#define Z_IS_83_EQ_83(...) \, -#define Z_IS_84_EQ_84(...) \, -#define Z_IS_85_EQ_85(...) \, -#define Z_IS_86_EQ_86(...) \, -#define Z_IS_87_EQ_87(...) \, -#define Z_IS_88_EQ_88(...) \, -#define Z_IS_89_EQ_89(...) \, -#define Z_IS_90_EQ_90(...) \, -#define Z_IS_91_EQ_91(...) \, -#define Z_IS_92_EQ_92(...) \, -#define Z_IS_93_EQ_93(...) \, -#define Z_IS_94_EQ_94(...) \, -#define Z_IS_95_EQ_95(...) \, -#define Z_IS_96_EQ_96(...) \, -#define Z_IS_97_EQ_97(...) \, -#define Z_IS_98_EQ_98(...) \, -#define Z_IS_99_EQ_99(...) \, -#define Z_IS_100_EQ_100(...) \, -#define Z_IS_101_EQ_101(...) \, -#define Z_IS_102_EQ_102(...) \, -#define Z_IS_103_EQ_103(...) \, -#define Z_IS_104_EQ_104(...) \, -#define Z_IS_105_EQ_105(...) \, -#define Z_IS_106_EQ_106(...) \, -#define Z_IS_107_EQ_107(...) \, -#define Z_IS_108_EQ_108(...) \, -#define Z_IS_109_EQ_109(...) \, -#define Z_IS_110_EQ_110(...) \, -#define Z_IS_111_EQ_111(...) \, -#define Z_IS_112_EQ_112(...) \, -#define Z_IS_113_EQ_113(...) \, -#define Z_IS_114_EQ_114(...) \, -#define Z_IS_115_EQ_115(...) \, -#define Z_IS_116_EQ_116(...) \, -#define Z_IS_117_EQ_117(...) \, -#define Z_IS_118_EQ_118(...) \, -#define Z_IS_119_EQ_119(...) \, -#define Z_IS_120_EQ_120(...) \, -#define Z_IS_121_EQ_121(...) \, -#define Z_IS_122_EQ_122(...) \, -#define Z_IS_123_EQ_123(...) \, -#define Z_IS_124_EQ_124(...) \, -#define Z_IS_125_EQ_125(...) \, -#define Z_IS_126_EQ_126(...) \, -#define Z_IS_127_EQ_127(...) \, -#define Z_IS_128_EQ_128(...) \, -#define Z_IS_129_EQ_129(...) \, -#define Z_IS_130_EQ_130(...) \, -#define Z_IS_131_EQ_131(...) \, -#define Z_IS_132_EQ_132(...) \, -#define Z_IS_133_EQ_133(...) \, -#define Z_IS_134_EQ_134(...) \, -#define Z_IS_135_EQ_135(...) \, -#define Z_IS_136_EQ_136(...) \, -#define Z_IS_137_EQ_137(...) \, -#define Z_IS_138_EQ_138(...) \, -#define Z_IS_139_EQ_139(...) \, -#define Z_IS_140_EQ_140(...) \, -#define Z_IS_141_EQ_141(...) \, -#define Z_IS_142_EQ_142(...) \, -#define Z_IS_143_EQ_143(...) \, -#define Z_IS_144_EQ_144(...) \, -#define Z_IS_145_EQ_145(...) \, -#define Z_IS_146_EQ_146(...) \, -#define Z_IS_147_EQ_147(...) \, -#define Z_IS_148_EQ_148(...) \, -#define Z_IS_149_EQ_149(...) \, -#define Z_IS_150_EQ_150(...) \, -#define Z_IS_151_EQ_151(...) \, -#define Z_IS_152_EQ_152(...) \, -#define Z_IS_153_EQ_153(...) \, -#define Z_IS_154_EQ_154(...) \, -#define Z_IS_155_EQ_155(...) \, -#define Z_IS_156_EQ_156(...) \, -#define Z_IS_157_EQ_157(...) \, -#define Z_IS_158_EQ_158(...) \, -#define Z_IS_159_EQ_159(...) \, -#define Z_IS_160_EQ_160(...) \, -#define Z_IS_161_EQ_161(...) \, -#define Z_IS_162_EQ_162(...) \, -#define Z_IS_163_EQ_163(...) \, -#define Z_IS_164_EQ_164(...) \, -#define Z_IS_165_EQ_165(...) \, -#define Z_IS_166_EQ_166(...) \, -#define Z_IS_167_EQ_167(...) \, -#define Z_IS_168_EQ_168(...) \, -#define Z_IS_169_EQ_169(...) \, -#define Z_IS_170_EQ_170(...) \, -#define Z_IS_171_EQ_171(...) \, -#define Z_IS_172_EQ_172(...) \, -#define Z_IS_173_EQ_173(...) \, -#define Z_IS_174_EQ_174(...) \, -#define Z_IS_175_EQ_175(...) \, -#define Z_IS_176_EQ_176(...) \, -#define Z_IS_177_EQ_177(...) \, -#define Z_IS_178_EQ_178(...) \, -#define Z_IS_179_EQ_179(...) \, -#define Z_IS_180_EQ_180(...) \, -#define Z_IS_181_EQ_181(...) \, -#define Z_IS_182_EQ_182(...) \, -#define Z_IS_183_EQ_183(...) \, -#define Z_IS_184_EQ_184(...) \, -#define Z_IS_185_EQ_185(...) \, -#define Z_IS_186_EQ_186(...) \, -#define Z_IS_187_EQ_187(...) \, -#define Z_IS_188_EQ_188(...) \, -#define Z_IS_189_EQ_189(...) \, -#define Z_IS_190_EQ_190(...) \, -#define Z_IS_191_EQ_191(...) \, -#define Z_IS_192_EQ_192(...) \, -#define Z_IS_193_EQ_193(...) \, -#define Z_IS_194_EQ_194(...) \, -#define Z_IS_195_EQ_195(...) \, -#define Z_IS_196_EQ_196(...) \, -#define Z_IS_197_EQ_197(...) \, -#define Z_IS_198_EQ_198(...) \, -#define Z_IS_199_EQ_199(...) \, -#define Z_IS_200_EQ_200(...) \, -#define Z_IS_201_EQ_201(...) \, -#define Z_IS_202_EQ_202(...) \, -#define Z_IS_203_EQ_203(...) \, -#define Z_IS_204_EQ_204(...) \, -#define Z_IS_205_EQ_205(...) \, -#define Z_IS_206_EQ_206(...) \, -#define Z_IS_207_EQ_207(...) \, -#define Z_IS_208_EQ_208(...) \, -#define Z_IS_209_EQ_209(...) \, -#define Z_IS_210_EQ_210(...) \, -#define Z_IS_211_EQ_211(...) \, -#define Z_IS_212_EQ_212(...) \, -#define Z_IS_213_EQ_213(...) \, -#define Z_IS_214_EQ_214(...) \, -#define Z_IS_215_EQ_215(...) \, -#define Z_IS_216_EQ_216(...) \, -#define Z_IS_217_EQ_217(...) \, -#define Z_IS_218_EQ_218(...) \, -#define Z_IS_219_EQ_219(...) \, -#define Z_IS_220_EQ_220(...) \, -#define Z_IS_221_EQ_221(...) \, -#define Z_IS_222_EQ_222(...) \, -#define Z_IS_223_EQ_223(...) \, -#define Z_IS_224_EQ_224(...) \, -#define Z_IS_225_EQ_225(...) \, -#define Z_IS_226_EQ_226(...) \, -#define Z_IS_227_EQ_227(...) \, -#define Z_IS_228_EQ_228(...) \, -#define Z_IS_229_EQ_229(...) \, -#define Z_IS_230_EQ_230(...) \, -#define Z_IS_231_EQ_231(...) \, -#define Z_IS_232_EQ_232(...) \, -#define Z_IS_233_EQ_233(...) \, -#define Z_IS_234_EQ_234(...) \, -#define Z_IS_235_EQ_235(...) \, -#define Z_IS_236_EQ_236(...) \, -#define Z_IS_237_EQ_237(...) \, -#define Z_IS_238_EQ_238(...) \, -#define Z_IS_239_EQ_239(...) \, -#define Z_IS_240_EQ_240(...) \, -#define Z_IS_241_EQ_241(...) \, -#define Z_IS_242_EQ_242(...) \, -#define Z_IS_243_EQ_243(...) \, -#define Z_IS_244_EQ_244(...) \, -#define Z_IS_245_EQ_245(...) \, -#define Z_IS_246_EQ_246(...) \, -#define Z_IS_247_EQ_247(...) \, -#define Z_IS_248_EQ_248(...) \, -#define Z_IS_249_EQ_249(...) \, -#define Z_IS_250_EQ_250(...) \, -#define Z_IS_251_EQ_251(...) \, -#define Z_IS_252_EQ_252(...) \, -#define Z_IS_253_EQ_253(...) \, -#define Z_IS_254_EQ_254(...) \, -#define Z_IS_255_EQ_255(...) \, -#define Z_IS_256_EQ_256(...) \, -#define Z_IS_257_EQ_257(...) \, -#define Z_IS_258_EQ_258(...) \, -#define Z_IS_259_EQ_259(...) \, -#define Z_IS_260_EQ_260(...) \, -#define Z_IS_261_EQ_261(...) \, -#define Z_IS_262_EQ_262(...) \, -#define Z_IS_263_EQ_263(...) \, -#define Z_IS_264_EQ_264(...) \, -#define Z_IS_265_EQ_265(...) \, -#define Z_IS_266_EQ_266(...) \, -#define Z_IS_267_EQ_267(...) \, -#define Z_IS_268_EQ_268(...) \, -#define Z_IS_269_EQ_269(...) \, -#define Z_IS_270_EQ_270(...) \, -#define Z_IS_271_EQ_271(...) \, -#define Z_IS_272_EQ_272(...) \, -#define Z_IS_273_EQ_273(...) \, -#define Z_IS_274_EQ_274(...) \, -#define Z_IS_275_EQ_275(...) \, -#define Z_IS_276_EQ_276(...) \, -#define Z_IS_277_EQ_277(...) \, -#define Z_IS_278_EQ_278(...) \, -#define Z_IS_279_EQ_279(...) \, -#define Z_IS_280_EQ_280(...) \, -#define Z_IS_281_EQ_281(...) \, -#define Z_IS_282_EQ_282(...) \, -#define Z_IS_283_EQ_283(...) \, -#define Z_IS_284_EQ_284(...) \, -#define Z_IS_285_EQ_285(...) \, -#define Z_IS_286_EQ_286(...) \, -#define Z_IS_287_EQ_287(...) \, -#define Z_IS_288_EQ_288(...) \, -#define Z_IS_289_EQ_289(...) \, -#define Z_IS_290_EQ_290(...) \, -#define Z_IS_291_EQ_291(...) \, -#define Z_IS_292_EQ_292(...) \, -#define Z_IS_293_EQ_293(...) \, -#define Z_IS_294_EQ_294(...) \, -#define Z_IS_295_EQ_295(...) \, -#define Z_IS_296_EQ_296(...) \, -#define Z_IS_297_EQ_297(...) \, -#define Z_IS_298_EQ_298(...) \, -#define Z_IS_299_EQ_299(...) \, -#define Z_IS_300_EQ_300(...) \, -#define Z_IS_301_EQ_301(...) \, -#define Z_IS_302_EQ_302(...) \, -#define Z_IS_303_EQ_303(...) \, -#define Z_IS_304_EQ_304(...) \, -#define Z_IS_305_EQ_305(...) \, -#define Z_IS_306_EQ_306(...) \, -#define Z_IS_307_EQ_307(...) \, -#define Z_IS_308_EQ_308(...) \, -#define Z_IS_309_EQ_309(...) \, -#define Z_IS_310_EQ_310(...) \, -#define Z_IS_311_EQ_311(...) \, -#define Z_IS_312_EQ_312(...) \, -#define Z_IS_313_EQ_313(...) \, -#define Z_IS_314_EQ_314(...) \, -#define Z_IS_315_EQ_315(...) \, -#define Z_IS_316_EQ_316(...) \, -#define Z_IS_317_EQ_317(...) \, -#define Z_IS_318_EQ_318(...) \, -#define Z_IS_319_EQ_319(...) \, -#define Z_IS_320_EQ_320(...) \, -#define Z_IS_321_EQ_321(...) \, -#define Z_IS_322_EQ_322(...) \, -#define Z_IS_323_EQ_323(...) \, -#define Z_IS_324_EQ_324(...) \, -#define Z_IS_325_EQ_325(...) \, -#define Z_IS_326_EQ_326(...) \, -#define Z_IS_327_EQ_327(...) \, -#define Z_IS_328_EQ_328(...) \, -#define Z_IS_329_EQ_329(...) \, -#define Z_IS_330_EQ_330(...) \, -#define Z_IS_331_EQ_331(...) \, -#define Z_IS_332_EQ_332(...) \, -#define Z_IS_333_EQ_333(...) \, -#define Z_IS_334_EQ_334(...) \, -#define Z_IS_335_EQ_335(...) \, -#define Z_IS_336_EQ_336(...) \, -#define Z_IS_337_EQ_337(...) \, -#define Z_IS_338_EQ_338(...) \, -#define Z_IS_339_EQ_339(...) \, -#define Z_IS_340_EQ_340(...) \, -#define Z_IS_341_EQ_341(...) \, -#define Z_IS_342_EQ_342(...) \, -#define Z_IS_343_EQ_343(...) \, -#define Z_IS_344_EQ_344(...) \, -#define Z_IS_345_EQ_345(...) \, -#define Z_IS_346_EQ_346(...) \, -#define Z_IS_347_EQ_347(...) \, -#define Z_IS_348_EQ_348(...) \, -#define Z_IS_349_EQ_349(...) \, -#define Z_IS_350_EQ_350(...) \, -#define Z_IS_351_EQ_351(...) \, -#define Z_IS_352_EQ_352(...) \, -#define Z_IS_353_EQ_353(...) \, -#define Z_IS_354_EQ_354(...) \, -#define Z_IS_355_EQ_355(...) \, -#define Z_IS_356_EQ_356(...) \, -#define Z_IS_357_EQ_357(...) \, -#define Z_IS_358_EQ_358(...) \, -#define Z_IS_359_EQ_359(...) \, -#define Z_IS_360_EQ_360(...) \, -#define Z_IS_361_EQ_361(...) \, -#define Z_IS_362_EQ_362(...) \, -#define Z_IS_363_EQ_363(...) \, -#define Z_IS_364_EQ_364(...) \, -#define Z_IS_365_EQ_365(...) \, -#define Z_IS_366_EQ_366(...) \, -#define Z_IS_367_EQ_367(...) \, -#define Z_IS_368_EQ_368(...) \, -#define Z_IS_369_EQ_369(...) \, -#define Z_IS_370_EQ_370(...) \, -#define Z_IS_371_EQ_371(...) \, -#define Z_IS_372_EQ_372(...) \, -#define Z_IS_373_EQ_373(...) \, -#define Z_IS_374_EQ_374(...) \, -#define Z_IS_375_EQ_375(...) \, -#define Z_IS_376_EQ_376(...) \, -#define Z_IS_377_EQ_377(...) \, -#define Z_IS_378_EQ_378(...) \, -#define Z_IS_379_EQ_379(...) \, -#define Z_IS_380_EQ_380(...) \, -#define Z_IS_381_EQ_381(...) \, -#define Z_IS_382_EQ_382(...) \, -#define Z_IS_383_EQ_383(...) \, -#define Z_IS_384_EQ_384(...) \, -#define Z_IS_385_EQ_385(...) \, -#define Z_IS_386_EQ_386(...) \, -#define Z_IS_387_EQ_387(...) \, -#define Z_IS_388_EQ_388(...) \, -#define Z_IS_389_EQ_389(...) \, -#define Z_IS_390_EQ_390(...) \, -#define Z_IS_391_EQ_391(...) \, -#define Z_IS_392_EQ_392(...) \, -#define Z_IS_393_EQ_393(...) \, -#define Z_IS_394_EQ_394(...) \, -#define Z_IS_395_EQ_395(...) \, -#define Z_IS_396_EQ_396(...) \, -#define Z_IS_397_EQ_397(...) \, -#define Z_IS_398_EQ_398(...) \, -#define Z_IS_399_EQ_399(...) \, -#define Z_IS_400_EQ_400(...) \, -#define Z_IS_401_EQ_401(...) \, -#define Z_IS_402_EQ_402(...) \, -#define Z_IS_403_EQ_403(...) \, -#define Z_IS_404_EQ_404(...) \, -#define Z_IS_405_EQ_405(...) \, -#define Z_IS_406_EQ_406(...) \, -#define Z_IS_407_EQ_407(...) \, -#define Z_IS_408_EQ_408(...) \, -#define Z_IS_409_EQ_409(...) \, -#define Z_IS_410_EQ_410(...) \, -#define Z_IS_411_EQ_411(...) \, -#define Z_IS_412_EQ_412(...) \, -#define Z_IS_413_EQ_413(...) \, -#define Z_IS_414_EQ_414(...) \, -#define Z_IS_415_EQ_415(...) \, -#define Z_IS_416_EQ_416(...) \, -#define Z_IS_417_EQ_417(...) \, -#define Z_IS_418_EQ_418(...) \, -#define Z_IS_419_EQ_419(...) \, -#define Z_IS_420_EQ_420(...) \, -#define Z_IS_421_EQ_421(...) \, -#define Z_IS_422_EQ_422(...) \, -#define Z_IS_423_EQ_423(...) \, -#define Z_IS_424_EQ_424(...) \, -#define Z_IS_425_EQ_425(...) \, -#define Z_IS_426_EQ_426(...) \, -#define Z_IS_427_EQ_427(...) \, -#define Z_IS_428_EQ_428(...) \, -#define Z_IS_429_EQ_429(...) \, -#define Z_IS_430_EQ_430(...) \, -#define Z_IS_431_EQ_431(...) \, -#define Z_IS_432_EQ_432(...) \, -#define Z_IS_433_EQ_433(...) \, -#define Z_IS_434_EQ_434(...) \, -#define Z_IS_435_EQ_435(...) \, -#define Z_IS_436_EQ_436(...) \, -#define Z_IS_437_EQ_437(...) \, -#define Z_IS_438_EQ_438(...) \, -#define Z_IS_439_EQ_439(...) \, -#define Z_IS_440_EQ_440(...) \, -#define Z_IS_441_EQ_441(...) \, -#define Z_IS_442_EQ_442(...) \, -#define Z_IS_443_EQ_443(...) \, -#define Z_IS_444_EQ_444(...) \, -#define Z_IS_445_EQ_445(...) \, -#define Z_IS_446_EQ_446(...) \, -#define Z_IS_447_EQ_447(...) \, -#define Z_IS_448_EQ_448(...) \, -#define Z_IS_449_EQ_449(...) \, -#define Z_IS_450_EQ_450(...) \, -#define Z_IS_451_EQ_451(...) \, -#define Z_IS_452_EQ_452(...) \, -#define Z_IS_453_EQ_453(...) \, -#define Z_IS_454_EQ_454(...) \, -#define Z_IS_455_EQ_455(...) \, -#define Z_IS_456_EQ_456(...) \, -#define Z_IS_457_EQ_457(...) \, -#define Z_IS_458_EQ_458(...) \, -#define Z_IS_459_EQ_459(...) \, -#define Z_IS_460_EQ_460(...) \, -#define Z_IS_461_EQ_461(...) \, -#define Z_IS_462_EQ_462(...) \, -#define Z_IS_463_EQ_463(...) \, -#define Z_IS_464_EQ_464(...) \, -#define Z_IS_465_EQ_465(...) \, -#define Z_IS_466_EQ_466(...) \, -#define Z_IS_467_EQ_467(...) \, -#define Z_IS_468_EQ_468(...) \, -#define Z_IS_469_EQ_469(...) \, -#define Z_IS_470_EQ_470(...) \, -#define Z_IS_471_EQ_471(...) \, -#define Z_IS_472_EQ_472(...) \, -#define Z_IS_473_EQ_473(...) \, -#define Z_IS_474_EQ_474(...) \, -#define Z_IS_475_EQ_475(...) \, -#define Z_IS_476_EQ_476(...) \, -#define Z_IS_477_EQ_477(...) \, -#define Z_IS_478_EQ_478(...) \, -#define Z_IS_479_EQ_479(...) \, -#define Z_IS_480_EQ_480(...) \, -#define Z_IS_481_EQ_481(...) \, -#define Z_IS_482_EQ_482(...) \, -#define Z_IS_483_EQ_483(...) \, -#define Z_IS_484_EQ_484(...) \, -#define Z_IS_485_EQ_485(...) \, -#define Z_IS_486_EQ_486(...) \, -#define Z_IS_487_EQ_487(...) \, -#define Z_IS_488_EQ_488(...) \, -#define Z_IS_489_EQ_489(...) \, -#define Z_IS_490_EQ_490(...) \, -#define Z_IS_491_EQ_491(...) \, -#define Z_IS_492_EQ_492(...) \, -#define Z_IS_493_EQ_493(...) \, -#define Z_IS_494_EQ_494(...) \, -#define Z_IS_495_EQ_495(...) \, -#define Z_IS_496_EQ_496(...) \, -#define Z_IS_497_EQ_497(...) \, -#define Z_IS_498_EQ_498(...) \, -#define Z_IS_499_EQ_499(...) \, -#define Z_IS_500_EQ_500(...) \, -#define Z_IS_501_EQ_501(...) \, -#define Z_IS_502_EQ_502(...) \, -#define Z_IS_503_EQ_503(...) \, -#define Z_IS_504_EQ_504(...) \, -#define Z_IS_505_EQ_505(...) \, -#define Z_IS_506_EQ_506(...) \, -#define Z_IS_507_EQ_507(...) \, -#define Z_IS_508_EQ_508(...) \, -#define Z_IS_509_EQ_509(...) \, -#define Z_IS_510_EQ_510(...) \, -#define Z_IS_511_EQ_511(...) \, -#define Z_IS_512_EQ_512(...) \, -#define Z_IS_513_EQ_513(...) \, -#define Z_IS_514_EQ_514(...) \, -#define Z_IS_515_EQ_515(...) \, -#define Z_IS_516_EQ_516(...) \, -#define Z_IS_517_EQ_517(...) \, -#define Z_IS_518_EQ_518(...) \, -#define Z_IS_519_EQ_519(...) \, -#define Z_IS_520_EQ_520(...) \, -#define Z_IS_521_EQ_521(...) \, -#define Z_IS_522_EQ_522(...) \, -#define Z_IS_523_EQ_523(...) \, -#define Z_IS_524_EQ_524(...) \, -#define Z_IS_525_EQ_525(...) \, -#define Z_IS_526_EQ_526(...) \, -#define Z_IS_527_EQ_527(...) \, -#define Z_IS_528_EQ_528(...) \, -#define Z_IS_529_EQ_529(...) \, -#define Z_IS_530_EQ_530(...) \, -#define Z_IS_531_EQ_531(...) \, -#define Z_IS_532_EQ_532(...) \, -#define Z_IS_533_EQ_533(...) \, -#define Z_IS_534_EQ_534(...) \, -#define Z_IS_535_EQ_535(...) \, -#define Z_IS_536_EQ_536(...) \, -#define Z_IS_537_EQ_537(...) \, -#define Z_IS_538_EQ_538(...) \, -#define Z_IS_539_EQ_539(...) \, -#define Z_IS_540_EQ_540(...) \, -#define Z_IS_541_EQ_541(...) \, -#define Z_IS_542_EQ_542(...) \, -#define Z_IS_543_EQ_543(...) \, -#define Z_IS_544_EQ_544(...) \, -#define Z_IS_545_EQ_545(...) \, -#define Z_IS_546_EQ_546(...) \, -#define Z_IS_547_EQ_547(...) \, -#define Z_IS_548_EQ_548(...) \, -#define Z_IS_549_EQ_549(...) \, -#define Z_IS_550_EQ_550(...) \, -#define Z_IS_551_EQ_551(...) \, -#define Z_IS_552_EQ_552(...) \, -#define Z_IS_553_EQ_553(...) \, -#define Z_IS_554_EQ_554(...) \, -#define Z_IS_555_EQ_555(...) \, -#define Z_IS_556_EQ_556(...) \, -#define Z_IS_557_EQ_557(...) \, -#define Z_IS_558_EQ_558(...) \, -#define Z_IS_559_EQ_559(...) \, -#define Z_IS_560_EQ_560(...) \, -#define Z_IS_561_EQ_561(...) \, -#define Z_IS_562_EQ_562(...) \, -#define Z_IS_563_EQ_563(...) \, -#define Z_IS_564_EQ_564(...) \, -#define Z_IS_565_EQ_565(...) \, -#define Z_IS_566_EQ_566(...) \, -#define Z_IS_567_EQ_567(...) \, -#define Z_IS_568_EQ_568(...) \, -#define Z_IS_569_EQ_569(...) \, -#define Z_IS_570_EQ_570(...) \, -#define Z_IS_571_EQ_571(...) \, -#define Z_IS_572_EQ_572(...) \, -#define Z_IS_573_EQ_573(...) \, -#define Z_IS_574_EQ_574(...) \, -#define Z_IS_575_EQ_575(...) \, -#define Z_IS_576_EQ_576(...) \, -#define Z_IS_577_EQ_577(...) \, -#define Z_IS_578_EQ_578(...) \, -#define Z_IS_579_EQ_579(...) \, -#define Z_IS_580_EQ_580(...) \, -#define Z_IS_581_EQ_581(...) \, -#define Z_IS_582_EQ_582(...) \, -#define Z_IS_583_EQ_583(...) \, -#define Z_IS_584_EQ_584(...) \, -#define Z_IS_585_EQ_585(...) \, -#define Z_IS_586_EQ_586(...) \, -#define Z_IS_587_EQ_587(...) \, -#define Z_IS_588_EQ_588(...) \, -#define Z_IS_589_EQ_589(...) \, -#define Z_IS_590_EQ_590(...) \, -#define Z_IS_591_EQ_591(...) \, -#define Z_IS_592_EQ_592(...) \, -#define Z_IS_593_EQ_593(...) \, -#define Z_IS_594_EQ_594(...) \, -#define Z_IS_595_EQ_595(...) \, -#define Z_IS_596_EQ_596(...) \, -#define Z_IS_597_EQ_597(...) \, -#define Z_IS_598_EQ_598(...) \, -#define Z_IS_599_EQ_599(...) \, -#define Z_IS_600_EQ_600(...) \, -#define Z_IS_601_EQ_601(...) \, -#define Z_IS_602_EQ_602(...) \, -#define Z_IS_603_EQ_603(...) \, -#define Z_IS_604_EQ_604(...) \, -#define Z_IS_605_EQ_605(...) \, -#define Z_IS_606_EQ_606(...) \, -#define Z_IS_607_EQ_607(...) \, -#define Z_IS_608_EQ_608(...) \, -#define Z_IS_609_EQ_609(...) \, -#define Z_IS_610_EQ_610(...) \, -#define Z_IS_611_EQ_611(...) \, -#define Z_IS_612_EQ_612(...) \, -#define Z_IS_613_EQ_613(...) \, -#define Z_IS_614_EQ_614(...) \, -#define Z_IS_615_EQ_615(...) \, -#define Z_IS_616_EQ_616(...) \, -#define Z_IS_617_EQ_617(...) \, -#define Z_IS_618_EQ_618(...) \, -#define Z_IS_619_EQ_619(...) \, -#define Z_IS_620_EQ_620(...) \, -#define Z_IS_621_EQ_621(...) \, -#define Z_IS_622_EQ_622(...) \, -#define Z_IS_623_EQ_623(...) \, -#define Z_IS_624_EQ_624(...) \, -#define Z_IS_625_EQ_625(...) \, -#define Z_IS_626_EQ_626(...) \, -#define Z_IS_627_EQ_627(...) \, -#define Z_IS_628_EQ_628(...) \, -#define Z_IS_629_EQ_629(...) \, -#define Z_IS_630_EQ_630(...) \, -#define Z_IS_631_EQ_631(...) \, -#define Z_IS_632_EQ_632(...) \, -#define Z_IS_633_EQ_633(...) \, -#define Z_IS_634_EQ_634(...) \, -#define Z_IS_635_EQ_635(...) \, -#define Z_IS_636_EQ_636(...) \, -#define Z_IS_637_EQ_637(...) \, -#define Z_IS_638_EQ_638(...) \, -#define Z_IS_639_EQ_639(...) \, -#define Z_IS_640_EQ_640(...) \, -#define Z_IS_641_EQ_641(...) \, -#define Z_IS_642_EQ_642(...) \, -#define Z_IS_643_EQ_643(...) \, -#define Z_IS_644_EQ_644(...) \, -#define Z_IS_645_EQ_645(...) \, -#define Z_IS_646_EQ_646(...) \, -#define Z_IS_647_EQ_647(...) \, -#define Z_IS_648_EQ_648(...) \, -#define Z_IS_649_EQ_649(...) \, -#define Z_IS_650_EQ_650(...) \, -#define Z_IS_651_EQ_651(...) \, -#define Z_IS_652_EQ_652(...) \, -#define Z_IS_653_EQ_653(...) \, -#define Z_IS_654_EQ_654(...) \, -#define Z_IS_655_EQ_655(...) \, -#define Z_IS_656_EQ_656(...) \, -#define Z_IS_657_EQ_657(...) \, -#define Z_IS_658_EQ_658(...) \, -#define Z_IS_659_EQ_659(...) \, -#define Z_IS_660_EQ_660(...) \, -#define Z_IS_661_EQ_661(...) \, -#define Z_IS_662_EQ_662(...) \, -#define Z_IS_663_EQ_663(...) \, -#define Z_IS_664_EQ_664(...) \, -#define Z_IS_665_EQ_665(...) \, -#define Z_IS_666_EQ_666(...) \, -#define Z_IS_667_EQ_667(...) \, -#define Z_IS_668_EQ_668(...) \, -#define Z_IS_669_EQ_669(...) \, -#define Z_IS_670_EQ_670(...) \, -#define Z_IS_671_EQ_671(...) \, -#define Z_IS_672_EQ_672(...) \, -#define Z_IS_673_EQ_673(...) \, -#define Z_IS_674_EQ_674(...) \, -#define Z_IS_675_EQ_675(...) \, -#define Z_IS_676_EQ_676(...) \, -#define Z_IS_677_EQ_677(...) \, -#define Z_IS_678_EQ_678(...) \, -#define Z_IS_679_EQ_679(...) \, -#define Z_IS_680_EQ_680(...) \, -#define Z_IS_681_EQ_681(...) \, -#define Z_IS_682_EQ_682(...) \, -#define Z_IS_683_EQ_683(...) \, -#define Z_IS_684_EQ_684(...) \, -#define Z_IS_685_EQ_685(...) \, -#define Z_IS_686_EQ_686(...) \, -#define Z_IS_687_EQ_687(...) \, -#define Z_IS_688_EQ_688(...) \, -#define Z_IS_689_EQ_689(...) \, -#define Z_IS_690_EQ_690(...) \, -#define Z_IS_691_EQ_691(...) \, -#define Z_IS_692_EQ_692(...) \, -#define Z_IS_693_EQ_693(...) \, -#define Z_IS_694_EQ_694(...) \, -#define Z_IS_695_EQ_695(...) \, -#define Z_IS_696_EQ_696(...) \, -#define Z_IS_697_EQ_697(...) \, -#define Z_IS_698_EQ_698(...) \, -#define Z_IS_699_EQ_699(...) \, -#define Z_IS_700_EQ_700(...) \, -#define Z_IS_701_EQ_701(...) \, -#define Z_IS_702_EQ_702(...) \, -#define Z_IS_703_EQ_703(...) \, -#define Z_IS_704_EQ_704(...) \, -#define Z_IS_705_EQ_705(...) \, -#define Z_IS_706_EQ_706(...) \, -#define Z_IS_707_EQ_707(...) \, -#define Z_IS_708_EQ_708(...) \, -#define Z_IS_709_EQ_709(...) \, -#define Z_IS_710_EQ_710(...) \, -#define Z_IS_711_EQ_711(...) \, -#define Z_IS_712_EQ_712(...) \, -#define Z_IS_713_EQ_713(...) \, -#define Z_IS_714_EQ_714(...) \, -#define Z_IS_715_EQ_715(...) \, -#define Z_IS_716_EQ_716(...) \, -#define Z_IS_717_EQ_717(...) \, -#define Z_IS_718_EQ_718(...) \, -#define Z_IS_719_EQ_719(...) \, -#define Z_IS_720_EQ_720(...) \, -#define Z_IS_721_EQ_721(...) \, -#define Z_IS_722_EQ_722(...) \, -#define Z_IS_723_EQ_723(...) \, -#define Z_IS_724_EQ_724(...) \, -#define Z_IS_725_EQ_725(...) \, -#define Z_IS_726_EQ_726(...) \, -#define Z_IS_727_EQ_727(...) \, -#define Z_IS_728_EQ_728(...) \, -#define Z_IS_729_EQ_729(...) \, -#define Z_IS_730_EQ_730(...) \, -#define Z_IS_731_EQ_731(...) \, -#define Z_IS_732_EQ_732(...) \, -#define Z_IS_733_EQ_733(...) \, -#define Z_IS_734_EQ_734(...) \, -#define Z_IS_735_EQ_735(...) \, -#define Z_IS_736_EQ_736(...) \, -#define Z_IS_737_EQ_737(...) \, -#define Z_IS_738_EQ_738(...) \, -#define Z_IS_739_EQ_739(...) \, -#define Z_IS_740_EQ_740(...) \, -#define Z_IS_741_EQ_741(...) \, -#define Z_IS_742_EQ_742(...) \, -#define Z_IS_743_EQ_743(...) \, -#define Z_IS_744_EQ_744(...) \, -#define Z_IS_745_EQ_745(...) \, -#define Z_IS_746_EQ_746(...) \, -#define Z_IS_747_EQ_747(...) \, -#define Z_IS_748_EQ_748(...) \, -#define Z_IS_749_EQ_749(...) \, -#define Z_IS_750_EQ_750(...) \, -#define Z_IS_751_EQ_751(...) \, -#define Z_IS_752_EQ_752(...) \, -#define Z_IS_753_EQ_753(...) \, -#define Z_IS_754_EQ_754(...) \, -#define Z_IS_755_EQ_755(...) \, -#define Z_IS_756_EQ_756(...) \, -#define Z_IS_757_EQ_757(...) \, -#define Z_IS_758_EQ_758(...) \, -#define Z_IS_759_EQ_759(...) \, -#define Z_IS_760_EQ_760(...) \, -#define Z_IS_761_EQ_761(...) \, -#define Z_IS_762_EQ_762(...) \, -#define Z_IS_763_EQ_763(...) \, -#define Z_IS_764_EQ_764(...) \, -#define Z_IS_765_EQ_765(...) \, -#define Z_IS_766_EQ_766(...) \, -#define Z_IS_767_EQ_767(...) \, -#define Z_IS_768_EQ_768(...) \, -#define Z_IS_769_EQ_769(...) \, -#define Z_IS_770_EQ_770(...) \, -#define Z_IS_771_EQ_771(...) \, -#define Z_IS_772_EQ_772(...) \, -#define Z_IS_773_EQ_773(...) \, -#define Z_IS_774_EQ_774(...) \, -#define Z_IS_775_EQ_775(...) \, -#define Z_IS_776_EQ_776(...) \, -#define Z_IS_777_EQ_777(...) \, -#define Z_IS_778_EQ_778(...) \, -#define Z_IS_779_EQ_779(...) \, -#define Z_IS_780_EQ_780(...) \, -#define Z_IS_781_EQ_781(...) \, -#define Z_IS_782_EQ_782(...) \, -#define Z_IS_783_EQ_783(...) \, -#define Z_IS_784_EQ_784(...) \, -#define Z_IS_785_EQ_785(...) \, -#define Z_IS_786_EQ_786(...) \, -#define Z_IS_787_EQ_787(...) \, -#define Z_IS_788_EQ_788(...) \, -#define Z_IS_789_EQ_789(...) \, -#define Z_IS_790_EQ_790(...) \, -#define Z_IS_791_EQ_791(...) \, -#define Z_IS_792_EQ_792(...) \, -#define Z_IS_793_EQ_793(...) \, -#define Z_IS_794_EQ_794(...) \, -#define Z_IS_795_EQ_795(...) \, -#define Z_IS_796_EQ_796(...) \, -#define Z_IS_797_EQ_797(...) \, -#define Z_IS_798_EQ_798(...) \, -#define Z_IS_799_EQ_799(...) \, -#define Z_IS_800_EQ_800(...) \, -#define Z_IS_801_EQ_801(...) \, -#define Z_IS_802_EQ_802(...) \, -#define Z_IS_803_EQ_803(...) \, -#define Z_IS_804_EQ_804(...) \, -#define Z_IS_805_EQ_805(...) \, -#define Z_IS_806_EQ_806(...) \, -#define Z_IS_807_EQ_807(...) \, -#define Z_IS_808_EQ_808(...) \, -#define Z_IS_809_EQ_809(...) \, -#define Z_IS_810_EQ_810(...) \, -#define Z_IS_811_EQ_811(...) \, -#define Z_IS_812_EQ_812(...) \, -#define Z_IS_813_EQ_813(...) \, -#define Z_IS_814_EQ_814(...) \, -#define Z_IS_815_EQ_815(...) \, -#define Z_IS_816_EQ_816(...) \, -#define Z_IS_817_EQ_817(...) \, -#define Z_IS_818_EQ_818(...) \, -#define Z_IS_819_EQ_819(...) \, -#define Z_IS_820_EQ_820(...) \, -#define Z_IS_821_EQ_821(...) \, -#define Z_IS_822_EQ_822(...) \, -#define Z_IS_823_EQ_823(...) \, -#define Z_IS_824_EQ_824(...) \, -#define Z_IS_825_EQ_825(...) \, -#define Z_IS_826_EQ_826(...) \, -#define Z_IS_827_EQ_827(...) \, -#define Z_IS_828_EQ_828(...) \, -#define Z_IS_829_EQ_829(...) \, -#define Z_IS_830_EQ_830(...) \, -#define Z_IS_831_EQ_831(...) \, -#define Z_IS_832_EQ_832(...) \, -#define Z_IS_833_EQ_833(...) \, -#define Z_IS_834_EQ_834(...) \, -#define Z_IS_835_EQ_835(...) \, -#define Z_IS_836_EQ_836(...) \, -#define Z_IS_837_EQ_837(...) \, -#define Z_IS_838_EQ_838(...) \, -#define Z_IS_839_EQ_839(...) \, -#define Z_IS_840_EQ_840(...) \, -#define Z_IS_841_EQ_841(...) \, -#define Z_IS_842_EQ_842(...) \, -#define Z_IS_843_EQ_843(...) \, -#define Z_IS_844_EQ_844(...) \, -#define Z_IS_845_EQ_845(...) \, -#define Z_IS_846_EQ_846(...) \, -#define Z_IS_847_EQ_847(...) \, -#define Z_IS_848_EQ_848(...) \, -#define Z_IS_849_EQ_849(...) \, -#define Z_IS_850_EQ_850(...) \, -#define Z_IS_851_EQ_851(...) \, -#define Z_IS_852_EQ_852(...) \, -#define Z_IS_853_EQ_853(...) \, -#define Z_IS_854_EQ_854(...) \, -#define Z_IS_855_EQ_855(...) \, -#define Z_IS_856_EQ_856(...) \, -#define Z_IS_857_EQ_857(...) \, -#define Z_IS_858_EQ_858(...) \, -#define Z_IS_859_EQ_859(...) \, -#define Z_IS_860_EQ_860(...) \, -#define Z_IS_861_EQ_861(...) \, -#define Z_IS_862_EQ_862(...) \, -#define Z_IS_863_EQ_863(...) \, -#define Z_IS_864_EQ_864(...) \, -#define Z_IS_865_EQ_865(...) \, -#define Z_IS_866_EQ_866(...) \, -#define Z_IS_867_EQ_867(...) \, -#define Z_IS_868_EQ_868(...) \, -#define Z_IS_869_EQ_869(...) \, -#define Z_IS_870_EQ_870(...) \, -#define Z_IS_871_EQ_871(...) \, -#define Z_IS_872_EQ_872(...) \, -#define Z_IS_873_EQ_873(...) \, -#define Z_IS_874_EQ_874(...) \, -#define Z_IS_875_EQ_875(...) \, -#define Z_IS_876_EQ_876(...) \, -#define Z_IS_877_EQ_877(...) \, -#define Z_IS_878_EQ_878(...) \, -#define Z_IS_879_EQ_879(...) \, -#define Z_IS_880_EQ_880(...) \, -#define Z_IS_881_EQ_881(...) \, -#define Z_IS_882_EQ_882(...) \, -#define Z_IS_883_EQ_883(...) \, -#define Z_IS_884_EQ_884(...) \, -#define Z_IS_885_EQ_885(...) \, -#define Z_IS_886_EQ_886(...) \, -#define Z_IS_887_EQ_887(...) \, -#define Z_IS_888_EQ_888(...) \, -#define Z_IS_889_EQ_889(...) \, -#define Z_IS_890_EQ_890(...) \, -#define Z_IS_891_EQ_891(...) \, -#define Z_IS_892_EQ_892(...) \, -#define Z_IS_893_EQ_893(...) \, -#define Z_IS_894_EQ_894(...) \, -#define Z_IS_895_EQ_895(...) \, -#define Z_IS_896_EQ_896(...) \, -#define Z_IS_897_EQ_897(...) \, -#define Z_IS_898_EQ_898(...) \, -#define Z_IS_899_EQ_899(...) \, -#define Z_IS_900_EQ_900(...) \, -#define Z_IS_901_EQ_901(...) \, -#define Z_IS_902_EQ_902(...) \, -#define Z_IS_903_EQ_903(...) \, -#define Z_IS_904_EQ_904(...) \, -#define Z_IS_905_EQ_905(...) \, -#define Z_IS_906_EQ_906(...) \, -#define Z_IS_907_EQ_907(...) \, -#define Z_IS_908_EQ_908(...) \, -#define Z_IS_909_EQ_909(...) \, -#define Z_IS_910_EQ_910(...) \, -#define Z_IS_911_EQ_911(...) \, -#define Z_IS_912_EQ_912(...) \, -#define Z_IS_913_EQ_913(...) \, -#define Z_IS_914_EQ_914(...) \, -#define Z_IS_915_EQ_915(...) \, -#define Z_IS_916_EQ_916(...) \, -#define Z_IS_917_EQ_917(...) \, -#define Z_IS_918_EQ_918(...) \, -#define Z_IS_919_EQ_919(...) \, -#define Z_IS_920_EQ_920(...) \, -#define Z_IS_921_EQ_921(...) \, -#define Z_IS_922_EQ_922(...) \, -#define Z_IS_923_EQ_923(...) \, -#define Z_IS_924_EQ_924(...) \, -#define Z_IS_925_EQ_925(...) \, -#define Z_IS_926_EQ_926(...) \, -#define Z_IS_927_EQ_927(...) \, -#define Z_IS_928_EQ_928(...) \, -#define Z_IS_929_EQ_929(...) \, -#define Z_IS_930_EQ_930(...) \, -#define Z_IS_931_EQ_931(...) \, -#define Z_IS_932_EQ_932(...) \, -#define Z_IS_933_EQ_933(...) \, -#define Z_IS_934_EQ_934(...) \, -#define Z_IS_935_EQ_935(...) \, -#define Z_IS_936_EQ_936(...) \, -#define Z_IS_937_EQ_937(...) \, -#define Z_IS_938_EQ_938(...) \, -#define Z_IS_939_EQ_939(...) \, -#define Z_IS_940_EQ_940(...) \, -#define Z_IS_941_EQ_941(...) \, -#define Z_IS_942_EQ_942(...) \, -#define Z_IS_943_EQ_943(...) \, -#define Z_IS_944_EQ_944(...) \, -#define Z_IS_945_EQ_945(...) \, -#define Z_IS_946_EQ_946(...) \, -#define Z_IS_947_EQ_947(...) \, -#define Z_IS_948_EQ_948(...) \, -#define Z_IS_949_EQ_949(...) \, -#define Z_IS_950_EQ_950(...) \, -#define Z_IS_951_EQ_951(...) \, -#define Z_IS_952_EQ_952(...) \, -#define Z_IS_953_EQ_953(...) \, -#define Z_IS_954_EQ_954(...) \, -#define Z_IS_955_EQ_955(...) \, -#define Z_IS_956_EQ_956(...) \, -#define Z_IS_957_EQ_957(...) \, -#define Z_IS_958_EQ_958(...) \, -#define Z_IS_959_EQ_959(...) \, -#define Z_IS_960_EQ_960(...) \, -#define Z_IS_961_EQ_961(...) \, -#define Z_IS_962_EQ_962(...) \, -#define Z_IS_963_EQ_963(...) \, -#define Z_IS_964_EQ_964(...) \, -#define Z_IS_965_EQ_965(...) \, -#define Z_IS_966_EQ_966(...) \, -#define Z_IS_967_EQ_967(...) \, -#define Z_IS_968_EQ_968(...) \, -#define Z_IS_969_EQ_969(...) \, -#define Z_IS_970_EQ_970(...) \, -#define Z_IS_971_EQ_971(...) \, -#define Z_IS_972_EQ_972(...) \, -#define Z_IS_973_EQ_973(...) \, -#define Z_IS_974_EQ_974(...) \, -#define Z_IS_975_EQ_975(...) \, -#define Z_IS_976_EQ_976(...) \, -#define Z_IS_977_EQ_977(...) \, -#define Z_IS_978_EQ_978(...) \, -#define Z_IS_979_EQ_979(...) \, -#define Z_IS_980_EQ_980(...) \, -#define Z_IS_981_EQ_981(...) \, -#define Z_IS_982_EQ_982(...) \, -#define Z_IS_983_EQ_983(...) \, -#define Z_IS_984_EQ_984(...) \, -#define Z_IS_985_EQ_985(...) \, -#define Z_IS_986_EQ_986(...) \, -#define Z_IS_987_EQ_987(...) \, -#define Z_IS_988_EQ_988(...) \, -#define Z_IS_989_EQ_989(...) \, -#define Z_IS_990_EQ_990(...) \, -#define Z_IS_991_EQ_991(...) \, -#define Z_IS_992_EQ_992(...) \, -#define Z_IS_993_EQ_993(...) \, -#define Z_IS_994_EQ_994(...) \, -#define Z_IS_995_EQ_995(...) \, -#define Z_IS_996_EQ_996(...) \, -#define Z_IS_997_EQ_997(...) \, -#define Z_IS_998_EQ_998(...) \, -#define Z_IS_999_EQ_999(...) \, -#define Z_IS_1000_EQ_1000(...) \, -#define Z_IS_1001_EQ_1001(...) \, -#define Z_IS_1002_EQ_1002(...) \, -#define Z_IS_1003_EQ_1003(...) \, -#define Z_IS_1004_EQ_1004(...) \, -#define Z_IS_1005_EQ_1005(...) \, -#define Z_IS_1006_EQ_1006(...) \, -#define Z_IS_1007_EQ_1007(...) \, -#define Z_IS_1008_EQ_1008(...) \, -#define Z_IS_1009_EQ_1009(...) \, -#define Z_IS_1010_EQ_1010(...) \, -#define Z_IS_1011_EQ_1011(...) \, -#define Z_IS_1012_EQ_1012(...) \, -#define Z_IS_1013_EQ_1013(...) \, -#define Z_IS_1014_EQ_1014(...) \, -#define Z_IS_1015_EQ_1015(...) \, -#define Z_IS_1016_EQ_1016(...) \, -#define Z_IS_1017_EQ_1017(...) \, -#define Z_IS_1018_EQ_1018(...) \, -#define Z_IS_1019_EQ_1019(...) \, -#define Z_IS_1020_EQ_1020(...) \, -#define Z_IS_1021_EQ_1021(...) \, -#define Z_IS_1022_EQ_1022(...) \, -#define Z_IS_1023_EQ_1023(...) \, -#define Z_IS_1024_EQ_1024(...) \, -#define Z_IS_1025_EQ_1025(...) \, -#define Z_IS_1026_EQ_1026(...) \, -#define Z_IS_1027_EQ_1027(...) \, -#define Z_IS_1028_EQ_1028(...) \, -#define Z_IS_1029_EQ_1029(...) \, -#define Z_IS_1030_EQ_1030(...) \, -#define Z_IS_1031_EQ_1031(...) \, -#define Z_IS_1032_EQ_1032(...) \, -#define Z_IS_1033_EQ_1033(...) \, -#define Z_IS_1034_EQ_1034(...) \, -#define Z_IS_1035_EQ_1035(...) \, -#define Z_IS_1036_EQ_1036(...) \, -#define Z_IS_1037_EQ_1037(...) \, -#define Z_IS_1038_EQ_1038(...) \, -#define Z_IS_1039_EQ_1039(...) \, -#define Z_IS_1040_EQ_1040(...) \, -#define Z_IS_1041_EQ_1041(...) \, -#define Z_IS_1042_EQ_1042(...) \, -#define Z_IS_1043_EQ_1043(...) \, -#define Z_IS_1044_EQ_1044(...) \, -#define Z_IS_1045_EQ_1045(...) \, -#define Z_IS_1046_EQ_1046(...) \, -#define Z_IS_1047_EQ_1047(...) \, -#define Z_IS_1048_EQ_1048(...) \, -#define Z_IS_1049_EQ_1049(...) \, -#define Z_IS_1050_EQ_1050(...) \, -#define Z_IS_1051_EQ_1051(...) \, -#define Z_IS_1052_EQ_1052(...) \, -#define Z_IS_1053_EQ_1053(...) \, -#define Z_IS_1054_EQ_1054(...) \, -#define Z_IS_1055_EQ_1055(...) \, -#define Z_IS_1056_EQ_1056(...) \, -#define Z_IS_1057_EQ_1057(...) \, -#define Z_IS_1058_EQ_1058(...) \, -#define Z_IS_1059_EQ_1059(...) \, -#define Z_IS_1060_EQ_1060(...) \, -#define Z_IS_1061_EQ_1061(...) \, -#define Z_IS_1062_EQ_1062(...) \, -#define Z_IS_1063_EQ_1063(...) \, -#define Z_IS_1064_EQ_1064(...) \, -#define Z_IS_1065_EQ_1065(...) \, -#define Z_IS_1066_EQ_1066(...) \, -#define Z_IS_1067_EQ_1067(...) \, -#define Z_IS_1068_EQ_1068(...) \, -#define Z_IS_1069_EQ_1069(...) \, -#define Z_IS_1070_EQ_1070(...) \, -#define Z_IS_1071_EQ_1071(...) \, -#define Z_IS_1072_EQ_1072(...) \, -#define Z_IS_1073_EQ_1073(...) \, -#define Z_IS_1074_EQ_1074(...) \, -#define Z_IS_1075_EQ_1075(...) \, -#define Z_IS_1076_EQ_1076(...) \, -#define Z_IS_1077_EQ_1077(...) \, -#define Z_IS_1078_EQ_1078(...) \, -#define Z_IS_1079_EQ_1079(...) \, -#define Z_IS_1080_EQ_1080(...) \, -#define Z_IS_1081_EQ_1081(...) \, -#define Z_IS_1082_EQ_1082(...) \, -#define Z_IS_1083_EQ_1083(...) \, -#define Z_IS_1084_EQ_1084(...) \, -#define Z_IS_1085_EQ_1085(...) \, -#define Z_IS_1086_EQ_1086(...) \, -#define Z_IS_1087_EQ_1087(...) \, -#define Z_IS_1088_EQ_1088(...) \, -#define Z_IS_1089_EQ_1089(...) \, -#define Z_IS_1090_EQ_1090(...) \, -#define Z_IS_1091_EQ_1091(...) \, -#define Z_IS_1092_EQ_1092(...) \, -#define Z_IS_1093_EQ_1093(...) \, -#define Z_IS_1094_EQ_1094(...) \, -#define Z_IS_1095_EQ_1095(...) \, -#define Z_IS_1096_EQ_1096(...) \, -#define Z_IS_1097_EQ_1097(...) \, -#define Z_IS_1098_EQ_1098(...) \, -#define Z_IS_1099_EQ_1099(...) \, -#define Z_IS_1100_EQ_1100(...) \, -#define Z_IS_1101_EQ_1101(...) \, -#define Z_IS_1102_EQ_1102(...) \, -#define Z_IS_1103_EQ_1103(...) \, -#define Z_IS_1104_EQ_1104(...) \, -#define Z_IS_1105_EQ_1105(...) \, -#define Z_IS_1106_EQ_1106(...) \, -#define Z_IS_1107_EQ_1107(...) \, -#define Z_IS_1108_EQ_1108(...) \, -#define Z_IS_1109_EQ_1109(...) \, -#define Z_IS_1110_EQ_1110(...) \, -#define Z_IS_1111_EQ_1111(...) \, -#define Z_IS_1112_EQ_1112(...) \, -#define Z_IS_1113_EQ_1113(...) \, -#define Z_IS_1114_EQ_1114(...) \, -#define Z_IS_1115_EQ_1115(...) \, -#define Z_IS_1116_EQ_1116(...) \, -#define Z_IS_1117_EQ_1117(...) \, -#define Z_IS_1118_EQ_1118(...) \, -#define Z_IS_1119_EQ_1119(...) \, -#define Z_IS_1120_EQ_1120(...) \, -#define Z_IS_1121_EQ_1121(...) \, -#define Z_IS_1122_EQ_1122(...) \, -#define Z_IS_1123_EQ_1123(...) \, -#define Z_IS_1124_EQ_1124(...) \, -#define Z_IS_1125_EQ_1125(...) \, -#define Z_IS_1126_EQ_1126(...) \, -#define Z_IS_1127_EQ_1127(...) \, -#define Z_IS_1128_EQ_1128(...) \, -#define Z_IS_1129_EQ_1129(...) \, -#define Z_IS_1130_EQ_1130(...) \, -#define Z_IS_1131_EQ_1131(...) \, -#define Z_IS_1132_EQ_1132(...) \, -#define Z_IS_1133_EQ_1133(...) \, -#define Z_IS_1134_EQ_1134(...) \, -#define Z_IS_1135_EQ_1135(...) \, -#define Z_IS_1136_EQ_1136(...) \, -#define Z_IS_1137_EQ_1137(...) \, -#define Z_IS_1138_EQ_1138(...) \, -#define Z_IS_1139_EQ_1139(...) \, -#define Z_IS_1140_EQ_1140(...) \, -#define Z_IS_1141_EQ_1141(...) \, -#define Z_IS_1142_EQ_1142(...) \, -#define Z_IS_1143_EQ_1143(...) \, -#define Z_IS_1144_EQ_1144(...) \, -#define Z_IS_1145_EQ_1145(...) \, -#define Z_IS_1146_EQ_1146(...) \, -#define Z_IS_1147_EQ_1147(...) \, -#define Z_IS_1148_EQ_1148(...) \, -#define Z_IS_1149_EQ_1149(...) \, -#define Z_IS_1150_EQ_1150(...) \, -#define Z_IS_1151_EQ_1151(...) \, -#define Z_IS_1152_EQ_1152(...) \, -#define Z_IS_1153_EQ_1153(...) \, -#define Z_IS_1154_EQ_1154(...) \, -#define Z_IS_1155_EQ_1155(...) \, -#define Z_IS_1156_EQ_1156(...) \, -#define Z_IS_1157_EQ_1157(...) \, -#define Z_IS_1158_EQ_1158(...) \, -#define Z_IS_1159_EQ_1159(...) \, -#define Z_IS_1160_EQ_1160(...) \, -#define Z_IS_1161_EQ_1161(...) \, -#define Z_IS_1162_EQ_1162(...) \, -#define Z_IS_1163_EQ_1163(...) \, -#define Z_IS_1164_EQ_1164(...) \, -#define Z_IS_1165_EQ_1165(...) \, -#define Z_IS_1166_EQ_1166(...) \, -#define Z_IS_1167_EQ_1167(...) \, -#define Z_IS_1168_EQ_1168(...) \, -#define Z_IS_1169_EQ_1169(...) \, -#define Z_IS_1170_EQ_1170(...) \, -#define Z_IS_1171_EQ_1171(...) \, -#define Z_IS_1172_EQ_1172(...) \, -#define Z_IS_1173_EQ_1173(...) \, -#define Z_IS_1174_EQ_1174(...) \, -#define Z_IS_1175_EQ_1175(...) \, -#define Z_IS_1176_EQ_1176(...) \, -#define Z_IS_1177_EQ_1177(...) \, -#define Z_IS_1178_EQ_1178(...) \, -#define Z_IS_1179_EQ_1179(...) \, -#define Z_IS_1180_EQ_1180(...) \, -#define Z_IS_1181_EQ_1181(...) \, -#define Z_IS_1182_EQ_1182(...) \, -#define Z_IS_1183_EQ_1183(...) \, -#define Z_IS_1184_EQ_1184(...) \, -#define Z_IS_1185_EQ_1185(...) \, -#define Z_IS_1186_EQ_1186(...) \, -#define Z_IS_1187_EQ_1187(...) \, -#define Z_IS_1188_EQ_1188(...) \, -#define Z_IS_1189_EQ_1189(...) \, -#define Z_IS_1190_EQ_1190(...) \, -#define Z_IS_1191_EQ_1191(...) \, -#define Z_IS_1192_EQ_1192(...) \, -#define Z_IS_1193_EQ_1193(...) \, -#define Z_IS_1194_EQ_1194(...) \, -#define Z_IS_1195_EQ_1195(...) \, -#define Z_IS_1196_EQ_1196(...) \, -#define Z_IS_1197_EQ_1197(...) \, -#define Z_IS_1198_EQ_1198(...) \, -#define Z_IS_1199_EQ_1199(...) \, -#define Z_IS_1200_EQ_1200(...) \, -#define Z_IS_1201_EQ_1201(...) \, -#define Z_IS_1202_EQ_1202(...) \, -#define Z_IS_1203_EQ_1203(...) \, -#define Z_IS_1204_EQ_1204(...) \, -#define Z_IS_1205_EQ_1205(...) \, -#define Z_IS_1206_EQ_1206(...) \, -#define Z_IS_1207_EQ_1207(...) \, -#define Z_IS_1208_EQ_1208(...) \, -#define Z_IS_1209_EQ_1209(...) \, -#define Z_IS_1210_EQ_1210(...) \, -#define Z_IS_1211_EQ_1211(...) \, -#define Z_IS_1212_EQ_1212(...) \, -#define Z_IS_1213_EQ_1213(...) \, -#define Z_IS_1214_EQ_1214(...) \, -#define Z_IS_1215_EQ_1215(...) \, -#define Z_IS_1216_EQ_1216(...) \, -#define Z_IS_1217_EQ_1217(...) \, -#define Z_IS_1218_EQ_1218(...) \, -#define Z_IS_1219_EQ_1219(...) \, -#define Z_IS_1220_EQ_1220(...) \, -#define Z_IS_1221_EQ_1221(...) \, -#define Z_IS_1222_EQ_1222(...) \, -#define Z_IS_1223_EQ_1223(...) \, -#define Z_IS_1224_EQ_1224(...) \, -#define Z_IS_1225_EQ_1225(...) \, -#define Z_IS_1226_EQ_1226(...) \, -#define Z_IS_1227_EQ_1227(...) \, -#define Z_IS_1228_EQ_1228(...) \, -#define Z_IS_1229_EQ_1229(...) \, -#define Z_IS_1230_EQ_1230(...) \, -#define Z_IS_1231_EQ_1231(...) \, -#define Z_IS_1232_EQ_1232(...) \, -#define Z_IS_1233_EQ_1233(...) \, -#define Z_IS_1234_EQ_1234(...) \, -#define Z_IS_1235_EQ_1235(...) \, -#define Z_IS_1236_EQ_1236(...) \, -#define Z_IS_1237_EQ_1237(...) \, -#define Z_IS_1238_EQ_1238(...) \, -#define Z_IS_1239_EQ_1239(...) \, -#define Z_IS_1240_EQ_1240(...) \, -#define Z_IS_1241_EQ_1241(...) \, -#define Z_IS_1242_EQ_1242(...) \, -#define Z_IS_1243_EQ_1243(...) \, -#define Z_IS_1244_EQ_1244(...) \, -#define Z_IS_1245_EQ_1245(...) \, -#define Z_IS_1246_EQ_1246(...) \, -#define Z_IS_1247_EQ_1247(...) \, -#define Z_IS_1248_EQ_1248(...) \, -#define Z_IS_1249_EQ_1249(...) \, -#define Z_IS_1250_EQ_1250(...) \, -#define Z_IS_1251_EQ_1251(...) \, -#define Z_IS_1252_EQ_1252(...) \, -#define Z_IS_1253_EQ_1253(...) \, -#define Z_IS_1254_EQ_1254(...) \, -#define Z_IS_1255_EQ_1255(...) \, -#define Z_IS_1256_EQ_1256(...) \, -#define Z_IS_1257_EQ_1257(...) \, -#define Z_IS_1258_EQ_1258(...) \, -#define Z_IS_1259_EQ_1259(...) \, -#define Z_IS_1260_EQ_1260(...) \, -#define Z_IS_1261_EQ_1261(...) \, -#define Z_IS_1262_EQ_1262(...) \, -#define Z_IS_1263_EQ_1263(...) \, -#define Z_IS_1264_EQ_1264(...) \, -#define Z_IS_1265_EQ_1265(...) \, -#define Z_IS_1266_EQ_1266(...) \, -#define Z_IS_1267_EQ_1267(...) \, -#define Z_IS_1268_EQ_1268(...) \, -#define Z_IS_1269_EQ_1269(...) \, -#define Z_IS_1270_EQ_1270(...) \, -#define Z_IS_1271_EQ_1271(...) \, -#define Z_IS_1272_EQ_1272(...) \, -#define Z_IS_1273_EQ_1273(...) \, -#define Z_IS_1274_EQ_1274(...) \, -#define Z_IS_1275_EQ_1275(...) \, -#define Z_IS_1276_EQ_1276(...) \, -#define Z_IS_1277_EQ_1277(...) \, -#define Z_IS_1278_EQ_1278(...) \, -#define Z_IS_1279_EQ_1279(...) \, -#define Z_IS_1280_EQ_1280(...) \, -#define Z_IS_1281_EQ_1281(...) \, -#define Z_IS_1282_EQ_1282(...) \, -#define Z_IS_1283_EQ_1283(...) \, -#define Z_IS_1284_EQ_1284(...) \, -#define Z_IS_1285_EQ_1285(...) \, -#define Z_IS_1286_EQ_1286(...) \, -#define Z_IS_1287_EQ_1287(...) \, -#define Z_IS_1288_EQ_1288(...) \, -#define Z_IS_1289_EQ_1289(...) \, -#define Z_IS_1290_EQ_1290(...) \, -#define Z_IS_1291_EQ_1291(...) \, -#define Z_IS_1292_EQ_1292(...) \, -#define Z_IS_1293_EQ_1293(...) \, -#define Z_IS_1294_EQ_1294(...) \, -#define Z_IS_1295_EQ_1295(...) \, -#define Z_IS_1296_EQ_1296(...) \, -#define Z_IS_1297_EQ_1297(...) \, -#define Z_IS_1298_EQ_1298(...) \, -#define Z_IS_1299_EQ_1299(...) \, -#define Z_IS_1300_EQ_1300(...) \, -#define Z_IS_1301_EQ_1301(...) \, -#define Z_IS_1302_EQ_1302(...) \, -#define Z_IS_1303_EQ_1303(...) \, -#define Z_IS_1304_EQ_1304(...) \, -#define Z_IS_1305_EQ_1305(...) \, -#define Z_IS_1306_EQ_1306(...) \, -#define Z_IS_1307_EQ_1307(...) \, -#define Z_IS_1308_EQ_1308(...) \, -#define Z_IS_1309_EQ_1309(...) \, -#define Z_IS_1310_EQ_1310(...) \, -#define Z_IS_1311_EQ_1311(...) \, -#define Z_IS_1312_EQ_1312(...) \, -#define Z_IS_1313_EQ_1313(...) \, -#define Z_IS_1314_EQ_1314(...) \, -#define Z_IS_1315_EQ_1315(...) \, -#define Z_IS_1316_EQ_1316(...) \, -#define Z_IS_1317_EQ_1317(...) \, -#define Z_IS_1318_EQ_1318(...) \, -#define Z_IS_1319_EQ_1319(...) \, -#define Z_IS_1320_EQ_1320(...) \, -#define Z_IS_1321_EQ_1321(...) \, -#define Z_IS_1322_EQ_1322(...) \, -#define Z_IS_1323_EQ_1323(...) \, -#define Z_IS_1324_EQ_1324(...) \, -#define Z_IS_1325_EQ_1325(...) \, -#define Z_IS_1326_EQ_1326(...) \, -#define Z_IS_1327_EQ_1327(...) \, -#define Z_IS_1328_EQ_1328(...) \, -#define Z_IS_1329_EQ_1329(...) \, -#define Z_IS_1330_EQ_1330(...) \, -#define Z_IS_1331_EQ_1331(...) \, -#define Z_IS_1332_EQ_1332(...) \, -#define Z_IS_1333_EQ_1333(...) \, -#define Z_IS_1334_EQ_1334(...) \, -#define Z_IS_1335_EQ_1335(...) \, -#define Z_IS_1336_EQ_1336(...) \, -#define Z_IS_1337_EQ_1337(...) \, -#define Z_IS_1338_EQ_1338(...) \, -#define Z_IS_1339_EQ_1339(...) \, -#define Z_IS_1340_EQ_1340(...) \, -#define Z_IS_1341_EQ_1341(...) \, -#define Z_IS_1342_EQ_1342(...) \, -#define Z_IS_1343_EQ_1343(...) \, -#define Z_IS_1344_EQ_1344(...) \, -#define Z_IS_1345_EQ_1345(...) \, -#define Z_IS_1346_EQ_1346(...) \, -#define Z_IS_1347_EQ_1347(...) \, -#define Z_IS_1348_EQ_1348(...) \, -#define Z_IS_1349_EQ_1349(...) \, -#define Z_IS_1350_EQ_1350(...) \, -#define Z_IS_1351_EQ_1351(...) \, -#define Z_IS_1352_EQ_1352(...) \, -#define Z_IS_1353_EQ_1353(...) \, -#define Z_IS_1354_EQ_1354(...) \, -#define Z_IS_1355_EQ_1355(...) \, -#define Z_IS_1356_EQ_1356(...) \, -#define Z_IS_1357_EQ_1357(...) \, -#define Z_IS_1358_EQ_1358(...) \, -#define Z_IS_1359_EQ_1359(...) \, -#define Z_IS_1360_EQ_1360(...) \, -#define Z_IS_1361_EQ_1361(...) \, -#define Z_IS_1362_EQ_1362(...) \, -#define Z_IS_1363_EQ_1363(...) \, -#define Z_IS_1364_EQ_1364(...) \, -#define Z_IS_1365_EQ_1365(...) \, -#define Z_IS_1366_EQ_1366(...) \, -#define Z_IS_1367_EQ_1367(...) \, -#define Z_IS_1368_EQ_1368(...) \, -#define Z_IS_1369_EQ_1369(...) \, -#define Z_IS_1370_EQ_1370(...) \, -#define Z_IS_1371_EQ_1371(...) \, -#define Z_IS_1372_EQ_1372(...) \, -#define Z_IS_1373_EQ_1373(...) \, -#define Z_IS_1374_EQ_1374(...) \, -#define Z_IS_1375_EQ_1375(...) \, -#define Z_IS_1376_EQ_1376(...) \, -#define Z_IS_1377_EQ_1377(...) \, -#define Z_IS_1378_EQ_1378(...) \, -#define Z_IS_1379_EQ_1379(...) \, -#define Z_IS_1380_EQ_1380(...) \, -#define Z_IS_1381_EQ_1381(...) \, -#define Z_IS_1382_EQ_1382(...) \, -#define Z_IS_1383_EQ_1383(...) \, -#define Z_IS_1384_EQ_1384(...) \, -#define Z_IS_1385_EQ_1385(...) \, -#define Z_IS_1386_EQ_1386(...) \, -#define Z_IS_1387_EQ_1387(...) \, -#define Z_IS_1388_EQ_1388(...) \, -#define Z_IS_1389_EQ_1389(...) \, -#define Z_IS_1390_EQ_1390(...) \, -#define Z_IS_1391_EQ_1391(...) \, -#define Z_IS_1392_EQ_1392(...) \, -#define Z_IS_1393_EQ_1393(...) \, -#define Z_IS_1394_EQ_1394(...) \, -#define Z_IS_1395_EQ_1395(...) \, -#define Z_IS_1396_EQ_1396(...) \, -#define Z_IS_1397_EQ_1397(...) \, -#define Z_IS_1398_EQ_1398(...) \, -#define Z_IS_1399_EQ_1399(...) \, -#define Z_IS_1400_EQ_1400(...) \, -#define Z_IS_1401_EQ_1401(...) \, -#define Z_IS_1402_EQ_1402(...) \, -#define Z_IS_1403_EQ_1403(...) \, -#define Z_IS_1404_EQ_1404(...) \, -#define Z_IS_1405_EQ_1405(...) \, -#define Z_IS_1406_EQ_1406(...) \, -#define Z_IS_1407_EQ_1407(...) \, -#define Z_IS_1408_EQ_1408(...) \, -#define Z_IS_1409_EQ_1409(...) \, -#define Z_IS_1410_EQ_1410(...) \, -#define Z_IS_1411_EQ_1411(...) \, -#define Z_IS_1412_EQ_1412(...) \, -#define Z_IS_1413_EQ_1413(...) \, -#define Z_IS_1414_EQ_1414(...) \, -#define Z_IS_1415_EQ_1415(...) \, -#define Z_IS_1416_EQ_1416(...) \, -#define Z_IS_1417_EQ_1417(...) \, -#define Z_IS_1418_EQ_1418(...) \, -#define Z_IS_1419_EQ_1419(...) \, -#define Z_IS_1420_EQ_1420(...) \, -#define Z_IS_1421_EQ_1421(...) \, -#define Z_IS_1422_EQ_1422(...) \, -#define Z_IS_1423_EQ_1423(...) \, -#define Z_IS_1424_EQ_1424(...) \, -#define Z_IS_1425_EQ_1425(...) \, -#define Z_IS_1426_EQ_1426(...) \, -#define Z_IS_1427_EQ_1427(...) \, -#define Z_IS_1428_EQ_1428(...) \, -#define Z_IS_1429_EQ_1429(...) \, -#define Z_IS_1430_EQ_1430(...) \, -#define Z_IS_1431_EQ_1431(...) \, -#define Z_IS_1432_EQ_1432(...) \, -#define Z_IS_1433_EQ_1433(...) \, -#define Z_IS_1434_EQ_1434(...) \, -#define Z_IS_1435_EQ_1435(...) \, -#define Z_IS_1436_EQ_1436(...) \, -#define Z_IS_1437_EQ_1437(...) \, -#define Z_IS_1438_EQ_1438(...) \, -#define Z_IS_1439_EQ_1439(...) \, -#define Z_IS_1440_EQ_1440(...) \, -#define Z_IS_1441_EQ_1441(...) \, -#define Z_IS_1442_EQ_1442(...) \, -#define Z_IS_1443_EQ_1443(...) \, -#define Z_IS_1444_EQ_1444(...) \, -#define Z_IS_1445_EQ_1445(...) \, -#define Z_IS_1446_EQ_1446(...) \, -#define Z_IS_1447_EQ_1447(...) \, -#define Z_IS_1448_EQ_1448(...) \, -#define Z_IS_1449_EQ_1449(...) \, -#define Z_IS_1450_EQ_1450(...) \, -#define Z_IS_1451_EQ_1451(...) \, -#define Z_IS_1452_EQ_1452(...) \, -#define Z_IS_1453_EQ_1453(...) \, -#define Z_IS_1454_EQ_1454(...) \, -#define Z_IS_1455_EQ_1455(...) \, -#define Z_IS_1456_EQ_1456(...) \, -#define Z_IS_1457_EQ_1457(...) \, -#define Z_IS_1458_EQ_1458(...) \, -#define Z_IS_1459_EQ_1459(...) \, -#define Z_IS_1460_EQ_1460(...) \, -#define Z_IS_1461_EQ_1461(...) \, -#define Z_IS_1462_EQ_1462(...) \, -#define Z_IS_1463_EQ_1463(...) \, -#define Z_IS_1464_EQ_1464(...) \, -#define Z_IS_1465_EQ_1465(...) \, -#define Z_IS_1466_EQ_1466(...) \, -#define Z_IS_1467_EQ_1467(...) \, -#define Z_IS_1468_EQ_1468(...) \, -#define Z_IS_1469_EQ_1469(...) \, -#define Z_IS_1470_EQ_1470(...) \, -#define Z_IS_1471_EQ_1471(...) \, -#define Z_IS_1472_EQ_1472(...) \, -#define Z_IS_1473_EQ_1473(...) \, -#define Z_IS_1474_EQ_1474(...) \, -#define Z_IS_1475_EQ_1475(...) \, -#define Z_IS_1476_EQ_1476(...) \, -#define Z_IS_1477_EQ_1477(...) \, -#define Z_IS_1478_EQ_1478(...) \, -#define Z_IS_1479_EQ_1479(...) \, -#define Z_IS_1480_EQ_1480(...) \, -#define Z_IS_1481_EQ_1481(...) \, -#define Z_IS_1482_EQ_1482(...) \, -#define Z_IS_1483_EQ_1483(...) \, -#define Z_IS_1484_EQ_1484(...) \, -#define Z_IS_1485_EQ_1485(...) \, -#define Z_IS_1486_EQ_1486(...) \, -#define Z_IS_1487_EQ_1487(...) \, -#define Z_IS_1488_EQ_1488(...) \, -#define Z_IS_1489_EQ_1489(...) \, -#define Z_IS_1490_EQ_1490(...) \, -#define Z_IS_1491_EQ_1491(...) \, -#define Z_IS_1492_EQ_1492(...) \, -#define Z_IS_1493_EQ_1493(...) \, -#define Z_IS_1494_EQ_1494(...) \, -#define Z_IS_1495_EQ_1495(...) \, -#define Z_IS_1496_EQ_1496(...) \, -#define Z_IS_1497_EQ_1497(...) \, -#define Z_IS_1498_EQ_1498(...) \, -#define Z_IS_1499_EQ_1499(...) \, -#define Z_IS_1500_EQ_1500(...) \, -#define Z_IS_1501_EQ_1501(...) \, -#define Z_IS_1502_EQ_1502(...) \, -#define Z_IS_1503_EQ_1503(...) \, -#define Z_IS_1504_EQ_1504(...) \, -#define Z_IS_1505_EQ_1505(...) \, -#define Z_IS_1506_EQ_1506(...) \, -#define Z_IS_1507_EQ_1507(...) \, -#define Z_IS_1508_EQ_1508(...) \, -#define Z_IS_1509_EQ_1509(...) \, -#define Z_IS_1510_EQ_1510(...) \, -#define Z_IS_1511_EQ_1511(...) \, -#define Z_IS_1512_EQ_1512(...) \, -#define Z_IS_1513_EQ_1513(...) \, -#define Z_IS_1514_EQ_1514(...) \, -#define Z_IS_1515_EQ_1515(...) \, -#define Z_IS_1516_EQ_1516(...) \, -#define Z_IS_1517_EQ_1517(...) \, -#define Z_IS_1518_EQ_1518(...) \, -#define Z_IS_1519_EQ_1519(...) \, -#define Z_IS_1520_EQ_1520(...) \, -#define Z_IS_1521_EQ_1521(...) \, -#define Z_IS_1522_EQ_1522(...) \, -#define Z_IS_1523_EQ_1523(...) \, -#define Z_IS_1524_EQ_1524(...) \, -#define Z_IS_1525_EQ_1525(...) \, -#define Z_IS_1526_EQ_1526(...) \, -#define Z_IS_1527_EQ_1527(...) \, -#define Z_IS_1528_EQ_1528(...) \, -#define Z_IS_1529_EQ_1529(...) \, -#define Z_IS_1530_EQ_1530(...) \, -#define Z_IS_1531_EQ_1531(...) \, -#define Z_IS_1532_EQ_1532(...) \, -#define Z_IS_1533_EQ_1533(...) \, -#define Z_IS_1534_EQ_1534(...) \, -#define Z_IS_1535_EQ_1535(...) \, -#define Z_IS_1536_EQ_1536(...) \, -#define Z_IS_1537_EQ_1537(...) \, -#define Z_IS_1538_EQ_1538(...) \, -#define Z_IS_1539_EQ_1539(...) \, -#define Z_IS_1540_EQ_1540(...) \, -#define Z_IS_1541_EQ_1541(...) \, -#define Z_IS_1542_EQ_1542(...) \, -#define Z_IS_1543_EQ_1543(...) \, -#define Z_IS_1544_EQ_1544(...) \, -#define Z_IS_1545_EQ_1545(...) \, -#define Z_IS_1546_EQ_1546(...) \, -#define Z_IS_1547_EQ_1547(...) \, -#define Z_IS_1548_EQ_1548(...) \, -#define Z_IS_1549_EQ_1549(...) \, -#define Z_IS_1550_EQ_1550(...) \, -#define Z_IS_1551_EQ_1551(...) \, -#define Z_IS_1552_EQ_1552(...) \, -#define Z_IS_1553_EQ_1553(...) \, -#define Z_IS_1554_EQ_1554(...) \, -#define Z_IS_1555_EQ_1555(...) \, -#define Z_IS_1556_EQ_1556(...) \, -#define Z_IS_1557_EQ_1557(...) \, -#define Z_IS_1558_EQ_1558(...) \, -#define Z_IS_1559_EQ_1559(...) \, -#define Z_IS_1560_EQ_1560(...) \, -#define Z_IS_1561_EQ_1561(...) \, -#define Z_IS_1562_EQ_1562(...) \, -#define Z_IS_1563_EQ_1563(...) \, -#define Z_IS_1564_EQ_1564(...) \, -#define Z_IS_1565_EQ_1565(...) \, -#define Z_IS_1566_EQ_1566(...) \, -#define Z_IS_1567_EQ_1567(...) \, -#define Z_IS_1568_EQ_1568(...) \, -#define Z_IS_1569_EQ_1569(...) \, -#define Z_IS_1570_EQ_1570(...) \, -#define Z_IS_1571_EQ_1571(...) \, -#define Z_IS_1572_EQ_1572(...) \, -#define Z_IS_1573_EQ_1573(...) \, -#define Z_IS_1574_EQ_1574(...) \, -#define Z_IS_1575_EQ_1575(...) \, -#define Z_IS_1576_EQ_1576(...) \, -#define Z_IS_1577_EQ_1577(...) \, -#define Z_IS_1578_EQ_1578(...) \, -#define Z_IS_1579_EQ_1579(...) \, -#define Z_IS_1580_EQ_1580(...) \, -#define Z_IS_1581_EQ_1581(...) \, -#define Z_IS_1582_EQ_1582(...) \, -#define Z_IS_1583_EQ_1583(...) \, -#define Z_IS_1584_EQ_1584(...) \, -#define Z_IS_1585_EQ_1585(...) \, -#define Z_IS_1586_EQ_1586(...) \, -#define Z_IS_1587_EQ_1587(...) \, -#define Z_IS_1588_EQ_1588(...) \, -#define Z_IS_1589_EQ_1589(...) \, -#define Z_IS_1590_EQ_1590(...) \, -#define Z_IS_1591_EQ_1591(...) \, -#define Z_IS_1592_EQ_1592(...) \, -#define Z_IS_1593_EQ_1593(...) \, -#define Z_IS_1594_EQ_1594(...) \, -#define Z_IS_1595_EQ_1595(...) \, -#define Z_IS_1596_EQ_1596(...) \, -#define Z_IS_1597_EQ_1597(...) \, -#define Z_IS_1598_EQ_1598(...) \, -#define Z_IS_1599_EQ_1599(...) \, -#define Z_IS_1600_EQ_1600(...) \, -#define Z_IS_1601_EQ_1601(...) \, -#define Z_IS_1602_EQ_1602(...) \, -#define Z_IS_1603_EQ_1603(...) \, -#define Z_IS_1604_EQ_1604(...) \, -#define Z_IS_1605_EQ_1605(...) \, -#define Z_IS_1606_EQ_1606(...) \, -#define Z_IS_1607_EQ_1607(...) \, -#define Z_IS_1608_EQ_1608(...) \, -#define Z_IS_1609_EQ_1609(...) \, -#define Z_IS_1610_EQ_1610(...) \, -#define Z_IS_1611_EQ_1611(...) \, -#define Z_IS_1612_EQ_1612(...) \, -#define Z_IS_1613_EQ_1613(...) \, -#define Z_IS_1614_EQ_1614(...) \, -#define Z_IS_1615_EQ_1615(...) \, -#define Z_IS_1616_EQ_1616(...) \, -#define Z_IS_1617_EQ_1617(...) \, -#define Z_IS_1618_EQ_1618(...) \, -#define Z_IS_1619_EQ_1619(...) \, -#define Z_IS_1620_EQ_1620(...) \, -#define Z_IS_1621_EQ_1621(...) \, -#define Z_IS_1622_EQ_1622(...) \, -#define Z_IS_1623_EQ_1623(...) \, -#define Z_IS_1624_EQ_1624(...) \, -#define Z_IS_1625_EQ_1625(...) \, -#define Z_IS_1626_EQ_1626(...) \, -#define Z_IS_1627_EQ_1627(...) \, -#define Z_IS_1628_EQ_1628(...) \, -#define Z_IS_1629_EQ_1629(...) \, -#define Z_IS_1630_EQ_1630(...) \, -#define Z_IS_1631_EQ_1631(...) \, -#define Z_IS_1632_EQ_1632(...) \, -#define Z_IS_1633_EQ_1633(...) \, -#define Z_IS_1634_EQ_1634(...) \, -#define Z_IS_1635_EQ_1635(...) \, -#define Z_IS_1636_EQ_1636(...) \, -#define Z_IS_1637_EQ_1637(...) \, -#define Z_IS_1638_EQ_1638(...) \, -#define Z_IS_1639_EQ_1639(...) \, -#define Z_IS_1640_EQ_1640(...) \, -#define Z_IS_1641_EQ_1641(...) \, -#define Z_IS_1642_EQ_1642(...) \, -#define Z_IS_1643_EQ_1643(...) \, -#define Z_IS_1644_EQ_1644(...) \, -#define Z_IS_1645_EQ_1645(...) \, -#define Z_IS_1646_EQ_1646(...) \, -#define Z_IS_1647_EQ_1647(...) \, -#define Z_IS_1648_EQ_1648(...) \, -#define Z_IS_1649_EQ_1649(...) \, -#define Z_IS_1650_EQ_1650(...) \, -#define Z_IS_1651_EQ_1651(...) \, -#define Z_IS_1652_EQ_1652(...) \, -#define Z_IS_1653_EQ_1653(...) \, -#define Z_IS_1654_EQ_1654(...) \, -#define Z_IS_1655_EQ_1655(...) \, -#define Z_IS_1656_EQ_1656(...) \, -#define Z_IS_1657_EQ_1657(...) \, -#define Z_IS_1658_EQ_1658(...) \, -#define Z_IS_1659_EQ_1659(...) \, -#define Z_IS_1660_EQ_1660(...) \, -#define Z_IS_1661_EQ_1661(...) \, -#define Z_IS_1662_EQ_1662(...) \, -#define Z_IS_1663_EQ_1663(...) \, -#define Z_IS_1664_EQ_1664(...) \, -#define Z_IS_1665_EQ_1665(...) \, -#define Z_IS_1666_EQ_1666(...) \, -#define Z_IS_1667_EQ_1667(...) \, -#define Z_IS_1668_EQ_1668(...) \, -#define Z_IS_1669_EQ_1669(...) \, -#define Z_IS_1670_EQ_1670(...) \, -#define Z_IS_1671_EQ_1671(...) \, -#define Z_IS_1672_EQ_1672(...) \, -#define Z_IS_1673_EQ_1673(...) \, -#define Z_IS_1674_EQ_1674(...) \, -#define Z_IS_1675_EQ_1675(...) \, -#define Z_IS_1676_EQ_1676(...) \, -#define Z_IS_1677_EQ_1677(...) \, -#define Z_IS_1678_EQ_1678(...) \, -#define Z_IS_1679_EQ_1679(...) \, -#define Z_IS_1680_EQ_1680(...) \, -#define Z_IS_1681_EQ_1681(...) \, -#define Z_IS_1682_EQ_1682(...) \, -#define Z_IS_1683_EQ_1683(...) \, -#define Z_IS_1684_EQ_1684(...) \, -#define Z_IS_1685_EQ_1685(...) \, -#define Z_IS_1686_EQ_1686(...) \, -#define Z_IS_1687_EQ_1687(...) \, -#define Z_IS_1688_EQ_1688(...) \, -#define Z_IS_1689_EQ_1689(...) \, -#define Z_IS_1690_EQ_1690(...) \, -#define Z_IS_1691_EQ_1691(...) \, -#define Z_IS_1692_EQ_1692(...) \, -#define Z_IS_1693_EQ_1693(...) \, -#define Z_IS_1694_EQ_1694(...) \, -#define Z_IS_1695_EQ_1695(...) \, -#define Z_IS_1696_EQ_1696(...) \, -#define Z_IS_1697_EQ_1697(...) \, -#define Z_IS_1698_EQ_1698(...) \, -#define Z_IS_1699_EQ_1699(...) \, -#define Z_IS_1700_EQ_1700(...) \, -#define Z_IS_1701_EQ_1701(...) \, -#define Z_IS_1702_EQ_1702(...) \, -#define Z_IS_1703_EQ_1703(...) \, -#define Z_IS_1704_EQ_1704(...) \, -#define Z_IS_1705_EQ_1705(...) \, -#define Z_IS_1706_EQ_1706(...) \, -#define Z_IS_1707_EQ_1707(...) \, -#define Z_IS_1708_EQ_1708(...) \, -#define Z_IS_1709_EQ_1709(...) \, -#define Z_IS_1710_EQ_1710(...) \, -#define Z_IS_1711_EQ_1711(...) \, -#define Z_IS_1712_EQ_1712(...) \, -#define Z_IS_1713_EQ_1713(...) \, -#define Z_IS_1714_EQ_1714(...) \, -#define Z_IS_1715_EQ_1715(...) \, -#define Z_IS_1716_EQ_1716(...) \, -#define Z_IS_1717_EQ_1717(...) \, -#define Z_IS_1718_EQ_1718(...) \, -#define Z_IS_1719_EQ_1719(...) \, -#define Z_IS_1720_EQ_1720(...) \, -#define Z_IS_1721_EQ_1721(...) \, -#define Z_IS_1722_EQ_1722(...) \, -#define Z_IS_1723_EQ_1723(...) \, -#define Z_IS_1724_EQ_1724(...) \, -#define Z_IS_1725_EQ_1725(...) \, -#define Z_IS_1726_EQ_1726(...) \, -#define Z_IS_1727_EQ_1727(...) \, -#define Z_IS_1728_EQ_1728(...) \, -#define Z_IS_1729_EQ_1729(...) \, -#define Z_IS_1730_EQ_1730(...) \, -#define Z_IS_1731_EQ_1731(...) \, -#define Z_IS_1732_EQ_1732(...) \, -#define Z_IS_1733_EQ_1733(...) \, -#define Z_IS_1734_EQ_1734(...) \, -#define Z_IS_1735_EQ_1735(...) \, -#define Z_IS_1736_EQ_1736(...) \, -#define Z_IS_1737_EQ_1737(...) \, -#define Z_IS_1738_EQ_1738(...) \, -#define Z_IS_1739_EQ_1739(...) \, -#define Z_IS_1740_EQ_1740(...) \, -#define Z_IS_1741_EQ_1741(...) \, -#define Z_IS_1742_EQ_1742(...) \, -#define Z_IS_1743_EQ_1743(...) \, -#define Z_IS_1744_EQ_1744(...) \, -#define Z_IS_1745_EQ_1745(...) \, -#define Z_IS_1746_EQ_1746(...) \, -#define Z_IS_1747_EQ_1747(...) \, -#define Z_IS_1748_EQ_1748(...) \, -#define Z_IS_1749_EQ_1749(...) \, -#define Z_IS_1750_EQ_1750(...) \, -#define Z_IS_1751_EQ_1751(...) \, -#define Z_IS_1752_EQ_1752(...) \, -#define Z_IS_1753_EQ_1753(...) \, -#define Z_IS_1754_EQ_1754(...) \, -#define Z_IS_1755_EQ_1755(...) \, -#define Z_IS_1756_EQ_1756(...) \, -#define Z_IS_1757_EQ_1757(...) \, -#define Z_IS_1758_EQ_1758(...) \, -#define Z_IS_1759_EQ_1759(...) \, -#define Z_IS_1760_EQ_1760(...) \, -#define Z_IS_1761_EQ_1761(...) \, -#define Z_IS_1762_EQ_1762(...) \, -#define Z_IS_1763_EQ_1763(...) \, -#define Z_IS_1764_EQ_1764(...) \, -#define Z_IS_1765_EQ_1765(...) \, -#define Z_IS_1766_EQ_1766(...) \, -#define Z_IS_1767_EQ_1767(...) \, -#define Z_IS_1768_EQ_1768(...) \, -#define Z_IS_1769_EQ_1769(...) \, -#define Z_IS_1770_EQ_1770(...) \, -#define Z_IS_1771_EQ_1771(...) \, -#define Z_IS_1772_EQ_1772(...) \, -#define Z_IS_1773_EQ_1773(...) \, -#define Z_IS_1774_EQ_1774(...) \, -#define Z_IS_1775_EQ_1775(...) \, -#define Z_IS_1776_EQ_1776(...) \, -#define Z_IS_1777_EQ_1777(...) \, -#define Z_IS_1778_EQ_1778(...) \, -#define Z_IS_1779_EQ_1779(...) \, -#define Z_IS_1780_EQ_1780(...) \, -#define Z_IS_1781_EQ_1781(...) \, -#define Z_IS_1782_EQ_1782(...) \, -#define Z_IS_1783_EQ_1783(...) \, -#define Z_IS_1784_EQ_1784(...) \, -#define Z_IS_1785_EQ_1785(...) \, -#define Z_IS_1786_EQ_1786(...) \, -#define Z_IS_1787_EQ_1787(...) \, -#define Z_IS_1788_EQ_1788(...) \, -#define Z_IS_1789_EQ_1789(...) \, -#define Z_IS_1790_EQ_1790(...) \, -#define Z_IS_1791_EQ_1791(...) \, -#define Z_IS_1792_EQ_1792(...) \, -#define Z_IS_1793_EQ_1793(...) \, -#define Z_IS_1794_EQ_1794(...) \, -#define Z_IS_1795_EQ_1795(...) \, -#define Z_IS_1796_EQ_1796(...) \, -#define Z_IS_1797_EQ_1797(...) \, -#define Z_IS_1798_EQ_1798(...) \, -#define Z_IS_1799_EQ_1799(...) \, -#define Z_IS_1800_EQ_1800(...) \, -#define Z_IS_1801_EQ_1801(...) \, -#define Z_IS_1802_EQ_1802(...) \, -#define Z_IS_1803_EQ_1803(...) \, -#define Z_IS_1804_EQ_1804(...) \, -#define Z_IS_1805_EQ_1805(...) \, -#define Z_IS_1806_EQ_1806(...) \, -#define Z_IS_1807_EQ_1807(...) \, -#define Z_IS_1808_EQ_1808(...) \, -#define Z_IS_1809_EQ_1809(...) \, -#define Z_IS_1810_EQ_1810(...) \, -#define Z_IS_1811_EQ_1811(...) \, -#define Z_IS_1812_EQ_1812(...) \, -#define Z_IS_1813_EQ_1813(...) \, -#define Z_IS_1814_EQ_1814(...) \, -#define Z_IS_1815_EQ_1815(...) \, -#define Z_IS_1816_EQ_1816(...) \, -#define Z_IS_1817_EQ_1817(...) \, -#define Z_IS_1818_EQ_1818(...) \, -#define Z_IS_1819_EQ_1819(...) \, -#define Z_IS_1820_EQ_1820(...) \, -#define Z_IS_1821_EQ_1821(...) \, -#define Z_IS_1822_EQ_1822(...) \, -#define Z_IS_1823_EQ_1823(...) \, -#define Z_IS_1824_EQ_1824(...) \, -#define Z_IS_1825_EQ_1825(...) \, -#define Z_IS_1826_EQ_1826(...) \, -#define Z_IS_1827_EQ_1827(...) \, -#define Z_IS_1828_EQ_1828(...) \, -#define Z_IS_1829_EQ_1829(...) \, -#define Z_IS_1830_EQ_1830(...) \, -#define Z_IS_1831_EQ_1831(...) \, -#define Z_IS_1832_EQ_1832(...) \, -#define Z_IS_1833_EQ_1833(...) \, -#define Z_IS_1834_EQ_1834(...) \, -#define Z_IS_1835_EQ_1835(...) \, -#define Z_IS_1836_EQ_1836(...) \, -#define Z_IS_1837_EQ_1837(...) \, -#define Z_IS_1838_EQ_1838(...) \, -#define Z_IS_1839_EQ_1839(...) \, -#define Z_IS_1840_EQ_1840(...) \, -#define Z_IS_1841_EQ_1841(...) \, -#define Z_IS_1842_EQ_1842(...) \, -#define Z_IS_1843_EQ_1843(...) \, -#define Z_IS_1844_EQ_1844(...) \, -#define Z_IS_1845_EQ_1845(...) \, -#define Z_IS_1846_EQ_1846(...) \, -#define Z_IS_1847_EQ_1847(...) \, -#define Z_IS_1848_EQ_1848(...) \, -#define Z_IS_1849_EQ_1849(...) \, -#define Z_IS_1850_EQ_1850(...) \, -#define Z_IS_1851_EQ_1851(...) \, -#define Z_IS_1852_EQ_1852(...) \, -#define Z_IS_1853_EQ_1853(...) \, -#define Z_IS_1854_EQ_1854(...) \, -#define Z_IS_1855_EQ_1855(...) \, -#define Z_IS_1856_EQ_1856(...) \, -#define Z_IS_1857_EQ_1857(...) \, -#define Z_IS_1858_EQ_1858(...) \, -#define Z_IS_1859_EQ_1859(...) \, -#define Z_IS_1860_EQ_1860(...) \, -#define Z_IS_1861_EQ_1861(...) \, -#define Z_IS_1862_EQ_1862(...) \, -#define Z_IS_1863_EQ_1863(...) \, -#define Z_IS_1864_EQ_1864(...) \, -#define Z_IS_1865_EQ_1865(...) \, -#define Z_IS_1866_EQ_1866(...) \, -#define Z_IS_1867_EQ_1867(...) \, -#define Z_IS_1868_EQ_1868(...) \, -#define Z_IS_1869_EQ_1869(...) \, -#define Z_IS_1870_EQ_1870(...) \, -#define Z_IS_1871_EQ_1871(...) \, -#define Z_IS_1872_EQ_1872(...) \, -#define Z_IS_1873_EQ_1873(...) \, -#define Z_IS_1874_EQ_1874(...) \, -#define Z_IS_1875_EQ_1875(...) \, -#define Z_IS_1876_EQ_1876(...) \, -#define Z_IS_1877_EQ_1877(...) \, -#define Z_IS_1878_EQ_1878(...) \, -#define Z_IS_1879_EQ_1879(...) \, -#define Z_IS_1880_EQ_1880(...) \, -#define Z_IS_1881_EQ_1881(...) \, -#define Z_IS_1882_EQ_1882(...) \, -#define Z_IS_1883_EQ_1883(...) \, -#define Z_IS_1884_EQ_1884(...) \, -#define Z_IS_1885_EQ_1885(...) \, -#define Z_IS_1886_EQ_1886(...) \, -#define Z_IS_1887_EQ_1887(...) \, -#define Z_IS_1888_EQ_1888(...) \, -#define Z_IS_1889_EQ_1889(...) \, -#define Z_IS_1890_EQ_1890(...) \, -#define Z_IS_1891_EQ_1891(...) \, -#define Z_IS_1892_EQ_1892(...) \, -#define Z_IS_1893_EQ_1893(...) \, -#define Z_IS_1894_EQ_1894(...) \, -#define Z_IS_1895_EQ_1895(...) \, -#define Z_IS_1896_EQ_1896(...) \, -#define Z_IS_1897_EQ_1897(...) \, -#define Z_IS_1898_EQ_1898(...) \, -#define Z_IS_1899_EQ_1899(...) \, -#define Z_IS_1900_EQ_1900(...) \, -#define Z_IS_1901_EQ_1901(...) \, -#define Z_IS_1902_EQ_1902(...) \, -#define Z_IS_1903_EQ_1903(...) \, -#define Z_IS_1904_EQ_1904(...) \, -#define Z_IS_1905_EQ_1905(...) \, -#define Z_IS_1906_EQ_1906(...) \, -#define Z_IS_1907_EQ_1907(...) \, -#define Z_IS_1908_EQ_1908(...) \, -#define Z_IS_1909_EQ_1909(...) \, -#define Z_IS_1910_EQ_1910(...) \, -#define Z_IS_1911_EQ_1911(...) \, -#define Z_IS_1912_EQ_1912(...) \, -#define Z_IS_1913_EQ_1913(...) \, -#define Z_IS_1914_EQ_1914(...) \, -#define Z_IS_1915_EQ_1915(...) \, -#define Z_IS_1916_EQ_1916(...) \, -#define Z_IS_1917_EQ_1917(...) \, -#define Z_IS_1918_EQ_1918(...) \, -#define Z_IS_1919_EQ_1919(...) \, -#define Z_IS_1920_EQ_1920(...) \, -#define Z_IS_1921_EQ_1921(...) \, -#define Z_IS_1922_EQ_1922(...) \, -#define Z_IS_1923_EQ_1923(...) \, -#define Z_IS_1924_EQ_1924(...) \, -#define Z_IS_1925_EQ_1925(...) \, -#define Z_IS_1926_EQ_1926(...) \, -#define Z_IS_1927_EQ_1927(...) \, -#define Z_IS_1928_EQ_1928(...) \, -#define Z_IS_1929_EQ_1929(...) \, -#define Z_IS_1930_EQ_1930(...) \, -#define Z_IS_1931_EQ_1931(...) \, -#define Z_IS_1932_EQ_1932(...) \, -#define Z_IS_1933_EQ_1933(...) \, -#define Z_IS_1934_EQ_1934(...) \, -#define Z_IS_1935_EQ_1935(...) \, -#define Z_IS_1936_EQ_1936(...) \, -#define Z_IS_1937_EQ_1937(...) \, -#define Z_IS_1938_EQ_1938(...) \, -#define Z_IS_1939_EQ_1939(...) \, -#define Z_IS_1940_EQ_1940(...) \, -#define Z_IS_1941_EQ_1941(...) \, -#define Z_IS_1942_EQ_1942(...) \, -#define Z_IS_1943_EQ_1943(...) \, -#define Z_IS_1944_EQ_1944(...) \, -#define Z_IS_1945_EQ_1945(...) \, -#define Z_IS_1946_EQ_1946(...) \, -#define Z_IS_1947_EQ_1947(...) \, -#define Z_IS_1948_EQ_1948(...) \, -#define Z_IS_1949_EQ_1949(...) \, -#define Z_IS_1950_EQ_1950(...) \, -#define Z_IS_1951_EQ_1951(...) \, -#define Z_IS_1952_EQ_1952(...) \, -#define Z_IS_1953_EQ_1953(...) \, -#define Z_IS_1954_EQ_1954(...) \, -#define Z_IS_1955_EQ_1955(...) \, -#define Z_IS_1956_EQ_1956(...) \, -#define Z_IS_1957_EQ_1957(...) \, -#define Z_IS_1958_EQ_1958(...) \, -#define Z_IS_1959_EQ_1959(...) \, -#define Z_IS_1960_EQ_1960(...) \, -#define Z_IS_1961_EQ_1961(...) \, -#define Z_IS_1962_EQ_1962(...) \, -#define Z_IS_1963_EQ_1963(...) \, -#define Z_IS_1964_EQ_1964(...) \, -#define Z_IS_1965_EQ_1965(...) \, -#define Z_IS_1966_EQ_1966(...) \, -#define Z_IS_1967_EQ_1967(...) \, -#define Z_IS_1968_EQ_1968(...) \, -#define Z_IS_1969_EQ_1969(...) \, -#define Z_IS_1970_EQ_1970(...) \, -#define Z_IS_1971_EQ_1971(...) \, -#define Z_IS_1972_EQ_1972(...) \, -#define Z_IS_1973_EQ_1973(...) \, -#define Z_IS_1974_EQ_1974(...) \, -#define Z_IS_1975_EQ_1975(...) \, -#define Z_IS_1976_EQ_1976(...) \, -#define Z_IS_1977_EQ_1977(...) \, -#define Z_IS_1978_EQ_1978(...) \, -#define Z_IS_1979_EQ_1979(...) \, -#define Z_IS_1980_EQ_1980(...) \, -#define Z_IS_1981_EQ_1981(...) \, -#define Z_IS_1982_EQ_1982(...) \, -#define Z_IS_1983_EQ_1983(...) \, -#define Z_IS_1984_EQ_1984(...) \, -#define Z_IS_1985_EQ_1985(...) \, -#define Z_IS_1986_EQ_1986(...) \, -#define Z_IS_1987_EQ_1987(...) \, -#define Z_IS_1988_EQ_1988(...) \, -#define Z_IS_1989_EQ_1989(...) \, -#define Z_IS_1990_EQ_1990(...) \, -#define Z_IS_1991_EQ_1991(...) \, -#define Z_IS_1992_EQ_1992(...) \, -#define Z_IS_1993_EQ_1993(...) \, -#define Z_IS_1994_EQ_1994(...) \, -#define Z_IS_1995_EQ_1995(...) \, -#define Z_IS_1996_EQ_1996(...) \, -#define Z_IS_1997_EQ_1997(...) \, -#define Z_IS_1998_EQ_1998(...) \, -#define Z_IS_1999_EQ_1999(...) \, -#define Z_IS_2000_EQ_2000(...) \, -#define Z_IS_2001_EQ_2001(...) \, -#define Z_IS_2002_EQ_2002(...) \, -#define Z_IS_2003_EQ_2003(...) \, -#define Z_IS_2004_EQ_2004(...) \, -#define Z_IS_2005_EQ_2005(...) \, -#define Z_IS_2006_EQ_2006(...) \, -#define Z_IS_2007_EQ_2007(...) \, -#define Z_IS_2008_EQ_2008(...) \, -#define Z_IS_2009_EQ_2009(...) \, -#define Z_IS_2010_EQ_2010(...) \, -#define Z_IS_2011_EQ_2011(...) \, -#define Z_IS_2012_EQ_2012(...) \, -#define Z_IS_2013_EQ_2013(...) \, -#define Z_IS_2014_EQ_2014(...) \, -#define Z_IS_2015_EQ_2015(...) \, -#define Z_IS_2016_EQ_2016(...) \, -#define Z_IS_2017_EQ_2017(...) \, -#define Z_IS_2018_EQ_2018(...) \, -#define Z_IS_2019_EQ_2019(...) \, -#define Z_IS_2020_EQ_2020(...) \, -#define Z_IS_2021_EQ_2021(...) \, -#define Z_IS_2022_EQ_2022(...) \, -#define Z_IS_2023_EQ_2023(...) \, -#define Z_IS_2024_EQ_2024(...) \, -#define Z_IS_2025_EQ_2025(...) \, -#define Z_IS_2026_EQ_2026(...) \, -#define Z_IS_2027_EQ_2027(...) \, -#define Z_IS_2028_EQ_2028(...) \, -#define Z_IS_2029_EQ_2029(...) \, -#define Z_IS_2030_EQ_2030(...) \, -#define Z_IS_2031_EQ_2031(...) \, -#define Z_IS_2032_EQ_2032(...) \, -#define Z_IS_2033_EQ_2033(...) \, -#define Z_IS_2034_EQ_2034(...) \, -#define Z_IS_2035_EQ_2035(...) \, -#define Z_IS_2036_EQ_2036(...) \, -#define Z_IS_2037_EQ_2037(...) \, -#define Z_IS_2038_EQ_2038(...) \, -#define Z_IS_2039_EQ_2039(...) \, -#define Z_IS_2040_EQ_2040(...) \, -#define Z_IS_2041_EQ_2041(...) \, -#define Z_IS_2042_EQ_2042(...) \, -#define Z_IS_2043_EQ_2043(...) \, -#define Z_IS_2044_EQ_2044(...) \, -#define Z_IS_2045_EQ_2045(...) \, -#define Z_IS_2046_EQ_2046(...) \, -#define Z_IS_2047_EQ_2047(...) \, -#define Z_IS_2048_EQ_2048(...) \, -#define Z_IS_2049_EQ_2049(...) \, -#define Z_IS_2050_EQ_2050(...) \, -#define Z_IS_2051_EQ_2051(...) \, -#define Z_IS_2052_EQ_2052(...) \, -#define Z_IS_2053_EQ_2053(...) \, -#define Z_IS_2054_EQ_2054(...) \, -#define Z_IS_2055_EQ_2055(...) \, -#define Z_IS_2056_EQ_2056(...) \, -#define Z_IS_2057_EQ_2057(...) \, -#define Z_IS_2058_EQ_2058(...) \, -#define Z_IS_2059_EQ_2059(...) \, -#define Z_IS_2060_EQ_2060(...) \, -#define Z_IS_2061_EQ_2061(...) \, -#define Z_IS_2062_EQ_2062(...) \, -#define Z_IS_2063_EQ_2063(...) \, -#define Z_IS_2064_EQ_2064(...) \, -#define Z_IS_2065_EQ_2065(...) \, -#define Z_IS_2066_EQ_2066(...) \, -#define Z_IS_2067_EQ_2067(...) \, -#define Z_IS_2068_EQ_2068(...) \, -#define Z_IS_2069_EQ_2069(...) \, -#define Z_IS_2070_EQ_2070(...) \, -#define Z_IS_2071_EQ_2071(...) \, -#define Z_IS_2072_EQ_2072(...) \, -#define Z_IS_2073_EQ_2073(...) \, -#define Z_IS_2074_EQ_2074(...) \, -#define Z_IS_2075_EQ_2075(...) \, -#define Z_IS_2076_EQ_2076(...) \, -#define Z_IS_2077_EQ_2077(...) \, -#define Z_IS_2078_EQ_2078(...) \, -#define Z_IS_2079_EQ_2079(...) \, -#define Z_IS_2080_EQ_2080(...) \, -#define Z_IS_2081_EQ_2081(...) \, -#define Z_IS_2082_EQ_2082(...) \, -#define Z_IS_2083_EQ_2083(...) \, -#define Z_IS_2084_EQ_2084(...) \, -#define Z_IS_2085_EQ_2085(...) \, -#define Z_IS_2086_EQ_2086(...) \, -#define Z_IS_2087_EQ_2087(...) \, -#define Z_IS_2088_EQ_2088(...) \, -#define Z_IS_2089_EQ_2089(...) \, -#define Z_IS_2090_EQ_2090(...) \, -#define Z_IS_2091_EQ_2091(...) \, -#define Z_IS_2092_EQ_2092(...) \, -#define Z_IS_2093_EQ_2093(...) \, -#define Z_IS_2094_EQ_2094(...) \, -#define Z_IS_2095_EQ_2095(...) \, -#define Z_IS_2096_EQ_2096(...) \, -#define Z_IS_2097_EQ_2097(...) \, -#define Z_IS_2098_EQ_2098(...) \, -#define Z_IS_2099_EQ_2099(...) \, -#define Z_IS_2100_EQ_2100(...) \, -#define Z_IS_2101_EQ_2101(...) \, -#define Z_IS_2102_EQ_2102(...) \, -#define Z_IS_2103_EQ_2103(...) \, -#define Z_IS_2104_EQ_2104(...) \, -#define Z_IS_2105_EQ_2105(...) \, -#define Z_IS_2106_EQ_2106(...) \, -#define Z_IS_2107_EQ_2107(...) \, -#define Z_IS_2108_EQ_2108(...) \, -#define Z_IS_2109_EQ_2109(...) \, -#define Z_IS_2110_EQ_2110(...) \, -#define Z_IS_2111_EQ_2111(...) \, -#define Z_IS_2112_EQ_2112(...) \, -#define Z_IS_2113_EQ_2113(...) \, -#define Z_IS_2114_EQ_2114(...) \, -#define Z_IS_2115_EQ_2115(...) \, -#define Z_IS_2116_EQ_2116(...) \, -#define Z_IS_2117_EQ_2117(...) \, -#define Z_IS_2118_EQ_2118(...) \, -#define Z_IS_2119_EQ_2119(...) \, -#define Z_IS_2120_EQ_2120(...) \, -#define Z_IS_2121_EQ_2121(...) \, -#define Z_IS_2122_EQ_2122(...) \, -#define Z_IS_2123_EQ_2123(...) \, -#define Z_IS_2124_EQ_2124(...) \, -#define Z_IS_2125_EQ_2125(...) \, -#define Z_IS_2126_EQ_2126(...) \, -#define Z_IS_2127_EQ_2127(...) \, -#define Z_IS_2128_EQ_2128(...) \, -#define Z_IS_2129_EQ_2129(...) \, -#define Z_IS_2130_EQ_2130(...) \, -#define Z_IS_2131_EQ_2131(...) \, -#define Z_IS_2132_EQ_2132(...) \, -#define Z_IS_2133_EQ_2133(...) \, -#define Z_IS_2134_EQ_2134(...) \, -#define Z_IS_2135_EQ_2135(...) \, -#define Z_IS_2136_EQ_2136(...) \, -#define Z_IS_2137_EQ_2137(...) \, -#define Z_IS_2138_EQ_2138(...) \, -#define Z_IS_2139_EQ_2139(...) \, -#define Z_IS_2140_EQ_2140(...) \, -#define Z_IS_2141_EQ_2141(...) \, -#define Z_IS_2142_EQ_2142(...) \, -#define Z_IS_2143_EQ_2143(...) \, -#define Z_IS_2144_EQ_2144(...) \, -#define Z_IS_2145_EQ_2145(...) \, -#define Z_IS_2146_EQ_2146(...) \, -#define Z_IS_2147_EQ_2147(...) \, -#define Z_IS_2148_EQ_2148(...) \, -#define Z_IS_2149_EQ_2149(...) \, -#define Z_IS_2150_EQ_2150(...) \, -#define Z_IS_2151_EQ_2151(...) \, -#define Z_IS_2152_EQ_2152(...) \, -#define Z_IS_2153_EQ_2153(...) \, -#define Z_IS_2154_EQ_2154(...) \, -#define Z_IS_2155_EQ_2155(...) \, -#define Z_IS_2156_EQ_2156(...) \, -#define Z_IS_2157_EQ_2157(...) \, -#define Z_IS_2158_EQ_2158(...) \, -#define Z_IS_2159_EQ_2159(...) \, -#define Z_IS_2160_EQ_2160(...) \, -#define Z_IS_2161_EQ_2161(...) \, -#define Z_IS_2162_EQ_2162(...) \, -#define Z_IS_2163_EQ_2163(...) \, -#define Z_IS_2164_EQ_2164(...) \, -#define Z_IS_2165_EQ_2165(...) \, -#define Z_IS_2166_EQ_2166(...) \, -#define Z_IS_2167_EQ_2167(...) \, -#define Z_IS_2168_EQ_2168(...) \, -#define Z_IS_2169_EQ_2169(...) \, -#define Z_IS_2170_EQ_2170(...) \, -#define Z_IS_2171_EQ_2171(...) \, -#define Z_IS_2172_EQ_2172(...) \, -#define Z_IS_2173_EQ_2173(...) \, -#define Z_IS_2174_EQ_2174(...) \, -#define Z_IS_2175_EQ_2175(...) \, -#define Z_IS_2176_EQ_2176(...) \, -#define Z_IS_2177_EQ_2177(...) \, -#define Z_IS_2178_EQ_2178(...) \, -#define Z_IS_2179_EQ_2179(...) \, -#define Z_IS_2180_EQ_2180(...) \, -#define Z_IS_2181_EQ_2181(...) \, -#define Z_IS_2182_EQ_2182(...) \, -#define Z_IS_2183_EQ_2183(...) \, -#define Z_IS_2184_EQ_2184(...) \, -#define Z_IS_2185_EQ_2185(...) \, -#define Z_IS_2186_EQ_2186(...) \, -#define Z_IS_2187_EQ_2187(...) \, -#define Z_IS_2188_EQ_2188(...) \, -#define Z_IS_2189_EQ_2189(...) \, -#define Z_IS_2190_EQ_2190(...) \, -#define Z_IS_2191_EQ_2191(...) \, -#define Z_IS_2192_EQ_2192(...) \, -#define Z_IS_2193_EQ_2193(...) \, -#define Z_IS_2194_EQ_2194(...) \, -#define Z_IS_2195_EQ_2195(...) \, -#define Z_IS_2196_EQ_2196(...) \, -#define Z_IS_2197_EQ_2197(...) \, -#define Z_IS_2198_EQ_2198(...) \, -#define Z_IS_2199_EQ_2199(...) \, -#define Z_IS_2200_EQ_2200(...) \, -#define Z_IS_2201_EQ_2201(...) \, -#define Z_IS_2202_EQ_2202(...) \, -#define Z_IS_2203_EQ_2203(...) \, -#define Z_IS_2204_EQ_2204(...) \, -#define Z_IS_2205_EQ_2205(...) \, -#define Z_IS_2206_EQ_2206(...) \, -#define Z_IS_2207_EQ_2207(...) \, -#define Z_IS_2208_EQ_2208(...) \, -#define Z_IS_2209_EQ_2209(...) \, -#define Z_IS_2210_EQ_2210(...) \, -#define Z_IS_2211_EQ_2211(...) \, -#define Z_IS_2212_EQ_2212(...) \, -#define Z_IS_2213_EQ_2213(...) \, -#define Z_IS_2214_EQ_2214(...) \, -#define Z_IS_2215_EQ_2215(...) \, -#define Z_IS_2216_EQ_2216(...) \, -#define Z_IS_2217_EQ_2217(...) \, -#define Z_IS_2218_EQ_2218(...) \, -#define Z_IS_2219_EQ_2219(...) \, -#define Z_IS_2220_EQ_2220(...) \, -#define Z_IS_2221_EQ_2221(...) \, -#define Z_IS_2222_EQ_2222(...) \, -#define Z_IS_2223_EQ_2223(...) \, -#define Z_IS_2224_EQ_2224(...) \, -#define Z_IS_2225_EQ_2225(...) \, -#define Z_IS_2226_EQ_2226(...) \, -#define Z_IS_2227_EQ_2227(...) \, -#define Z_IS_2228_EQ_2228(...) \, -#define Z_IS_2229_EQ_2229(...) \, -#define Z_IS_2230_EQ_2230(...) \, -#define Z_IS_2231_EQ_2231(...) \, -#define Z_IS_2232_EQ_2232(...) \, -#define Z_IS_2233_EQ_2233(...) \, -#define Z_IS_2234_EQ_2234(...) \, -#define Z_IS_2235_EQ_2235(...) \, -#define Z_IS_2236_EQ_2236(...) \, -#define Z_IS_2237_EQ_2237(...) \, -#define Z_IS_2238_EQ_2238(...) \, -#define Z_IS_2239_EQ_2239(...) \, -#define Z_IS_2240_EQ_2240(...) \, -#define Z_IS_2241_EQ_2241(...) \, -#define Z_IS_2242_EQ_2242(...) \, -#define Z_IS_2243_EQ_2243(...) \, -#define Z_IS_2244_EQ_2244(...) \, -#define Z_IS_2245_EQ_2245(...) \, -#define Z_IS_2246_EQ_2246(...) \, -#define Z_IS_2247_EQ_2247(...) \, -#define Z_IS_2248_EQ_2248(...) \, -#define Z_IS_2249_EQ_2249(...) \, -#define Z_IS_2250_EQ_2250(...) \, -#define Z_IS_2251_EQ_2251(...) \, -#define Z_IS_2252_EQ_2252(...) \, -#define Z_IS_2253_EQ_2253(...) \, -#define Z_IS_2254_EQ_2254(...) \, -#define Z_IS_2255_EQ_2255(...) \, -#define Z_IS_2256_EQ_2256(...) \, -#define Z_IS_2257_EQ_2257(...) \, -#define Z_IS_2258_EQ_2258(...) \, -#define Z_IS_2259_EQ_2259(...) \, -#define Z_IS_2260_EQ_2260(...) \, -#define Z_IS_2261_EQ_2261(...) \, -#define Z_IS_2262_EQ_2262(...) \, -#define Z_IS_2263_EQ_2263(...) \, -#define Z_IS_2264_EQ_2264(...) \, -#define Z_IS_2265_EQ_2265(...) \, -#define Z_IS_2266_EQ_2266(...) \, -#define Z_IS_2267_EQ_2267(...) \, -#define Z_IS_2268_EQ_2268(...) \, -#define Z_IS_2269_EQ_2269(...) \, -#define Z_IS_2270_EQ_2270(...) \, -#define Z_IS_2271_EQ_2271(...) \, -#define Z_IS_2272_EQ_2272(...) \, -#define Z_IS_2273_EQ_2273(...) \, -#define Z_IS_2274_EQ_2274(...) \, -#define Z_IS_2275_EQ_2275(...) \, -#define Z_IS_2276_EQ_2276(...) \, -#define Z_IS_2277_EQ_2277(...) \, -#define Z_IS_2278_EQ_2278(...) \, -#define Z_IS_2279_EQ_2279(...) \, -#define Z_IS_2280_EQ_2280(...) \, -#define Z_IS_2281_EQ_2281(...) \, -#define Z_IS_2282_EQ_2282(...) \, -#define Z_IS_2283_EQ_2283(...) \, -#define Z_IS_2284_EQ_2284(...) \, -#define Z_IS_2285_EQ_2285(...) \, -#define Z_IS_2286_EQ_2286(...) \, -#define Z_IS_2287_EQ_2287(...) \, -#define Z_IS_2288_EQ_2288(...) \, -#define Z_IS_2289_EQ_2289(...) \, -#define Z_IS_2290_EQ_2290(...) \, -#define Z_IS_2291_EQ_2291(...) \, -#define Z_IS_2292_EQ_2292(...) \, -#define Z_IS_2293_EQ_2293(...) \, -#define Z_IS_2294_EQ_2294(...) \, -#define Z_IS_2295_EQ_2295(...) \, -#define Z_IS_2296_EQ_2296(...) \, -#define Z_IS_2297_EQ_2297(...) \, -#define Z_IS_2298_EQ_2298(...) \, -#define Z_IS_2299_EQ_2299(...) \, -#define Z_IS_2300_EQ_2300(...) \, -#define Z_IS_2301_EQ_2301(...) \, -#define Z_IS_2302_EQ_2302(...) \, -#define Z_IS_2303_EQ_2303(...) \, -#define Z_IS_2304_EQ_2304(...) \, -#define Z_IS_2305_EQ_2305(...) \, -#define Z_IS_2306_EQ_2306(...) \, -#define Z_IS_2307_EQ_2307(...) \, -#define Z_IS_2308_EQ_2308(...) \, -#define Z_IS_2309_EQ_2309(...) \, -#define Z_IS_2310_EQ_2310(...) \, -#define Z_IS_2311_EQ_2311(...) \, -#define Z_IS_2312_EQ_2312(...) \, -#define Z_IS_2313_EQ_2313(...) \, -#define Z_IS_2314_EQ_2314(...) \, -#define Z_IS_2315_EQ_2315(...) \, -#define Z_IS_2316_EQ_2316(...) \, -#define Z_IS_2317_EQ_2317(...) \, -#define Z_IS_2318_EQ_2318(...) \, -#define Z_IS_2319_EQ_2319(...) \, -#define Z_IS_2320_EQ_2320(...) \, -#define Z_IS_2321_EQ_2321(...) \, -#define Z_IS_2322_EQ_2322(...) \, -#define Z_IS_2323_EQ_2323(...) \, -#define Z_IS_2324_EQ_2324(...) \, -#define Z_IS_2325_EQ_2325(...) \, -#define Z_IS_2326_EQ_2326(...) \, -#define Z_IS_2327_EQ_2327(...) \, -#define Z_IS_2328_EQ_2328(...) \, -#define Z_IS_2329_EQ_2329(...) \, -#define Z_IS_2330_EQ_2330(...) \, -#define Z_IS_2331_EQ_2331(...) \, -#define Z_IS_2332_EQ_2332(...) \, -#define Z_IS_2333_EQ_2333(...) \, -#define Z_IS_2334_EQ_2334(...) \, -#define Z_IS_2335_EQ_2335(...) \, -#define Z_IS_2336_EQ_2336(...) \, -#define Z_IS_2337_EQ_2337(...) \, -#define Z_IS_2338_EQ_2338(...) \, -#define Z_IS_2339_EQ_2339(...) \, -#define Z_IS_2340_EQ_2340(...) \, -#define Z_IS_2341_EQ_2341(...) \, -#define Z_IS_2342_EQ_2342(...) \, -#define Z_IS_2343_EQ_2343(...) \, -#define Z_IS_2344_EQ_2344(...) \, -#define Z_IS_2345_EQ_2345(...) \, -#define Z_IS_2346_EQ_2346(...) \, -#define Z_IS_2347_EQ_2347(...) \, -#define Z_IS_2348_EQ_2348(...) \, -#define Z_IS_2349_EQ_2349(...) \, -#define Z_IS_2350_EQ_2350(...) \, -#define Z_IS_2351_EQ_2351(...) \, -#define Z_IS_2352_EQ_2352(...) \, -#define Z_IS_2353_EQ_2353(...) \, -#define Z_IS_2354_EQ_2354(...) \, -#define Z_IS_2355_EQ_2355(...) \, -#define Z_IS_2356_EQ_2356(...) \, -#define Z_IS_2357_EQ_2357(...) \, -#define Z_IS_2358_EQ_2358(...) \, -#define Z_IS_2359_EQ_2359(...) \, -#define Z_IS_2360_EQ_2360(...) \, -#define Z_IS_2361_EQ_2361(...) \, -#define Z_IS_2362_EQ_2362(...) \, -#define Z_IS_2363_EQ_2363(...) \, -#define Z_IS_2364_EQ_2364(...) \, -#define Z_IS_2365_EQ_2365(...) \, -#define Z_IS_2366_EQ_2366(...) \, -#define Z_IS_2367_EQ_2367(...) \, -#define Z_IS_2368_EQ_2368(...) \, -#define Z_IS_2369_EQ_2369(...) \, -#define Z_IS_2370_EQ_2370(...) \, -#define Z_IS_2371_EQ_2371(...) \, -#define Z_IS_2372_EQ_2372(...) \, -#define Z_IS_2373_EQ_2373(...) \, -#define Z_IS_2374_EQ_2374(...) \, -#define Z_IS_2375_EQ_2375(...) \, -#define Z_IS_2376_EQ_2376(...) \, -#define Z_IS_2377_EQ_2377(...) \, -#define Z_IS_2378_EQ_2378(...) \, -#define Z_IS_2379_EQ_2379(...) \, -#define Z_IS_2380_EQ_2380(...) \, -#define Z_IS_2381_EQ_2381(...) \, -#define Z_IS_2382_EQ_2382(...) \, -#define Z_IS_2383_EQ_2383(...) \, -#define Z_IS_2384_EQ_2384(...) \, -#define Z_IS_2385_EQ_2385(...) \, -#define Z_IS_2386_EQ_2386(...) \, -#define Z_IS_2387_EQ_2387(...) \, -#define Z_IS_2388_EQ_2388(...) \, -#define Z_IS_2389_EQ_2389(...) \, -#define Z_IS_2390_EQ_2390(...) \, -#define Z_IS_2391_EQ_2391(...) \, -#define Z_IS_2392_EQ_2392(...) \, -#define Z_IS_2393_EQ_2393(...) \, -#define Z_IS_2394_EQ_2394(...) \, -#define Z_IS_2395_EQ_2395(...) \, -#define Z_IS_2396_EQ_2396(...) \, -#define Z_IS_2397_EQ_2397(...) \, -#define Z_IS_2398_EQ_2398(...) \, -#define Z_IS_2399_EQ_2399(...) \, -#define Z_IS_2400_EQ_2400(...) \, -#define Z_IS_2401_EQ_2401(...) \, -#define Z_IS_2402_EQ_2402(...) \, -#define Z_IS_2403_EQ_2403(...) \, -#define Z_IS_2404_EQ_2404(...) \, -#define Z_IS_2405_EQ_2405(...) \, -#define Z_IS_2406_EQ_2406(...) \, -#define Z_IS_2407_EQ_2407(...) \, -#define Z_IS_2408_EQ_2408(...) \, -#define Z_IS_2409_EQ_2409(...) \, -#define Z_IS_2410_EQ_2410(...) \, -#define Z_IS_2411_EQ_2411(...) \, -#define Z_IS_2412_EQ_2412(...) \, -#define Z_IS_2413_EQ_2413(...) \, -#define Z_IS_2414_EQ_2414(...) \, -#define Z_IS_2415_EQ_2415(...) \, -#define Z_IS_2416_EQ_2416(...) \, -#define Z_IS_2417_EQ_2417(...) \, -#define Z_IS_2418_EQ_2418(...) \, -#define Z_IS_2419_EQ_2419(...) \, -#define Z_IS_2420_EQ_2420(...) \, -#define Z_IS_2421_EQ_2421(...) \, -#define Z_IS_2422_EQ_2422(...) \, -#define Z_IS_2423_EQ_2423(...) \, -#define Z_IS_2424_EQ_2424(...) \, -#define Z_IS_2425_EQ_2425(...) \, -#define Z_IS_2426_EQ_2426(...) \, -#define Z_IS_2427_EQ_2427(...) \, -#define Z_IS_2428_EQ_2428(...) \, -#define Z_IS_2429_EQ_2429(...) \, -#define Z_IS_2430_EQ_2430(...) \, -#define Z_IS_2431_EQ_2431(...) \, -#define Z_IS_2432_EQ_2432(...) \, -#define Z_IS_2433_EQ_2433(...) \, -#define Z_IS_2434_EQ_2434(...) \, -#define Z_IS_2435_EQ_2435(...) \, -#define Z_IS_2436_EQ_2436(...) \, -#define Z_IS_2437_EQ_2437(...) \, -#define Z_IS_2438_EQ_2438(...) \, -#define Z_IS_2439_EQ_2439(...) \, -#define Z_IS_2440_EQ_2440(...) \, -#define Z_IS_2441_EQ_2441(...) \, -#define Z_IS_2442_EQ_2442(...) \, -#define Z_IS_2443_EQ_2443(...) \, -#define Z_IS_2444_EQ_2444(...) \, -#define Z_IS_2445_EQ_2445(...) \, -#define Z_IS_2446_EQ_2446(...) \, -#define Z_IS_2447_EQ_2447(...) \, -#define Z_IS_2448_EQ_2448(...) \, -#define Z_IS_2449_EQ_2449(...) \, -#define Z_IS_2450_EQ_2450(...) \, -#define Z_IS_2451_EQ_2451(...) \, -#define Z_IS_2452_EQ_2452(...) \, -#define Z_IS_2453_EQ_2453(...) \, -#define Z_IS_2454_EQ_2454(...) \, -#define Z_IS_2455_EQ_2455(...) \, -#define Z_IS_2456_EQ_2456(...) \, -#define Z_IS_2457_EQ_2457(...) \, -#define Z_IS_2458_EQ_2458(...) \, -#define Z_IS_2459_EQ_2459(...) \, -#define Z_IS_2460_EQ_2460(...) \, -#define Z_IS_2461_EQ_2461(...) \, -#define Z_IS_2462_EQ_2462(...) \, -#define Z_IS_2463_EQ_2463(...) \, -#define Z_IS_2464_EQ_2464(...) \, -#define Z_IS_2465_EQ_2465(...) \, -#define Z_IS_2466_EQ_2466(...) \, -#define Z_IS_2467_EQ_2467(...) \, -#define Z_IS_2468_EQ_2468(...) \, -#define Z_IS_2469_EQ_2469(...) \, -#define Z_IS_2470_EQ_2470(...) \, -#define Z_IS_2471_EQ_2471(...) \, -#define Z_IS_2472_EQ_2472(...) \, -#define Z_IS_2473_EQ_2473(...) \, -#define Z_IS_2474_EQ_2474(...) \, -#define Z_IS_2475_EQ_2475(...) \, -#define Z_IS_2476_EQ_2476(...) \, -#define Z_IS_2477_EQ_2477(...) \, -#define Z_IS_2478_EQ_2478(...) \, -#define Z_IS_2479_EQ_2479(...) \, -#define Z_IS_2480_EQ_2480(...) \, -#define Z_IS_2481_EQ_2481(...) \, -#define Z_IS_2482_EQ_2482(...) \, -#define Z_IS_2483_EQ_2483(...) \, -#define Z_IS_2484_EQ_2484(...) \, -#define Z_IS_2485_EQ_2485(...) \, -#define Z_IS_2486_EQ_2486(...) \, -#define Z_IS_2487_EQ_2487(...) \, -#define Z_IS_2488_EQ_2488(...) \, -#define Z_IS_2489_EQ_2489(...) \, -#define Z_IS_2490_EQ_2490(...) \, -#define Z_IS_2491_EQ_2491(...) \, -#define Z_IS_2492_EQ_2492(...) \, -#define Z_IS_2493_EQ_2493(...) \, -#define Z_IS_2494_EQ_2494(...) \, -#define Z_IS_2495_EQ_2495(...) \, -#define Z_IS_2496_EQ_2496(...) \, -#define Z_IS_2497_EQ_2497(...) \, -#define Z_IS_2498_EQ_2498(...) \, -#define Z_IS_2499_EQ_2499(...) \, -#define Z_IS_2500_EQ_2500(...) \, -#define Z_IS_2501_EQ_2501(...) \, -#define Z_IS_2502_EQ_2502(...) \, -#define Z_IS_2503_EQ_2503(...) \, -#define Z_IS_2504_EQ_2504(...) \, -#define Z_IS_2505_EQ_2505(...) \, -#define Z_IS_2506_EQ_2506(...) \, -#define Z_IS_2507_EQ_2507(...) \, -#define Z_IS_2508_EQ_2508(...) \, -#define Z_IS_2509_EQ_2509(...) \, -#define Z_IS_2510_EQ_2510(...) \, -#define Z_IS_2511_EQ_2511(...) \, -#define Z_IS_2512_EQ_2512(...) \, -#define Z_IS_2513_EQ_2513(...) \, -#define Z_IS_2514_EQ_2514(...) \, -#define Z_IS_2515_EQ_2515(...) \, -#define Z_IS_2516_EQ_2516(...) \, -#define Z_IS_2517_EQ_2517(...) \, -#define Z_IS_2518_EQ_2518(...) \, -#define Z_IS_2519_EQ_2519(...) \, -#define Z_IS_2520_EQ_2520(...) \, -#define Z_IS_2521_EQ_2521(...) \, -#define Z_IS_2522_EQ_2522(...) \, -#define Z_IS_2523_EQ_2523(...) \, -#define Z_IS_2524_EQ_2524(...) \, -#define Z_IS_2525_EQ_2525(...) \, -#define Z_IS_2526_EQ_2526(...) \, -#define Z_IS_2527_EQ_2527(...) \, -#define Z_IS_2528_EQ_2528(...) \, -#define Z_IS_2529_EQ_2529(...) \, -#define Z_IS_2530_EQ_2530(...) \, -#define Z_IS_2531_EQ_2531(...) \, -#define Z_IS_2532_EQ_2532(...) \, -#define Z_IS_2533_EQ_2533(...) \, -#define Z_IS_2534_EQ_2534(...) \, -#define Z_IS_2535_EQ_2535(...) \, -#define Z_IS_2536_EQ_2536(...) \, -#define Z_IS_2537_EQ_2537(...) \, -#define Z_IS_2538_EQ_2538(...) \, -#define Z_IS_2539_EQ_2539(...) \, -#define Z_IS_2540_EQ_2540(...) \, -#define Z_IS_2541_EQ_2541(...) \, -#define Z_IS_2542_EQ_2542(...) \, -#define Z_IS_2543_EQ_2543(...) \, -#define Z_IS_2544_EQ_2544(...) \, -#define Z_IS_2545_EQ_2545(...) \, -#define Z_IS_2546_EQ_2546(...) \, -#define Z_IS_2547_EQ_2547(...) \, -#define Z_IS_2548_EQ_2548(...) \, -#define Z_IS_2549_EQ_2549(...) \, -#define Z_IS_2550_EQ_2550(...) \, -#define Z_IS_2551_EQ_2551(...) \, -#define Z_IS_2552_EQ_2552(...) \, -#define Z_IS_2553_EQ_2553(...) \, -#define Z_IS_2554_EQ_2554(...) \, -#define Z_IS_2555_EQ_2555(...) \, -#define Z_IS_2556_EQ_2556(...) \, -#define Z_IS_2557_EQ_2557(...) \, -#define Z_IS_2558_EQ_2558(...) \, -#define Z_IS_2559_EQ_2559(...) \, -#define Z_IS_2560_EQ_2560(...) \, -#define Z_IS_2561_EQ_2561(...) \, -#define Z_IS_2562_EQ_2562(...) \, -#define Z_IS_2563_EQ_2563(...) \, -#define Z_IS_2564_EQ_2564(...) \, -#define Z_IS_2565_EQ_2565(...) \, -#define Z_IS_2566_EQ_2566(...) \, -#define Z_IS_2567_EQ_2567(...) \, -#define Z_IS_2568_EQ_2568(...) \, -#define Z_IS_2569_EQ_2569(...) \, -#define Z_IS_2570_EQ_2570(...) \, -#define Z_IS_2571_EQ_2571(...) \, -#define Z_IS_2572_EQ_2572(...) \, -#define Z_IS_2573_EQ_2573(...) \, -#define Z_IS_2574_EQ_2574(...) \, -#define Z_IS_2575_EQ_2575(...) \, -#define Z_IS_2576_EQ_2576(...) \, -#define Z_IS_2577_EQ_2577(...) \, -#define Z_IS_2578_EQ_2578(...) \, -#define Z_IS_2579_EQ_2579(...) \, -#define Z_IS_2580_EQ_2580(...) \, -#define Z_IS_2581_EQ_2581(...) \, -#define Z_IS_2582_EQ_2582(...) \, -#define Z_IS_2583_EQ_2583(...) \, -#define Z_IS_2584_EQ_2584(...) \, -#define Z_IS_2585_EQ_2585(...) \, -#define Z_IS_2586_EQ_2586(...) \, -#define Z_IS_2587_EQ_2587(...) \, -#define Z_IS_2588_EQ_2588(...) \, -#define Z_IS_2589_EQ_2589(...) \, -#define Z_IS_2590_EQ_2590(...) \, -#define Z_IS_2591_EQ_2591(...) \, -#define Z_IS_2592_EQ_2592(...) \, -#define Z_IS_2593_EQ_2593(...) \, -#define Z_IS_2594_EQ_2594(...) \, -#define Z_IS_2595_EQ_2595(...) \, -#define Z_IS_2596_EQ_2596(...) \, -#define Z_IS_2597_EQ_2597(...) \, -#define Z_IS_2598_EQ_2598(...) \, -#define Z_IS_2599_EQ_2599(...) \, -#define Z_IS_2600_EQ_2600(...) \, -#define Z_IS_2601_EQ_2601(...) \, -#define Z_IS_2602_EQ_2602(...) \, -#define Z_IS_2603_EQ_2603(...) \, -#define Z_IS_2604_EQ_2604(...) \, -#define Z_IS_2605_EQ_2605(...) \, -#define Z_IS_2606_EQ_2606(...) \, -#define Z_IS_2607_EQ_2607(...) \, -#define Z_IS_2608_EQ_2608(...) \, -#define Z_IS_2609_EQ_2609(...) \, -#define Z_IS_2610_EQ_2610(...) \, -#define Z_IS_2611_EQ_2611(...) \, -#define Z_IS_2612_EQ_2612(...) \, -#define Z_IS_2613_EQ_2613(...) \, -#define Z_IS_2614_EQ_2614(...) \, -#define Z_IS_2615_EQ_2615(...) \, -#define Z_IS_2616_EQ_2616(...) \, -#define Z_IS_2617_EQ_2617(...) \, -#define Z_IS_2618_EQ_2618(...) \, -#define Z_IS_2619_EQ_2619(...) \, -#define Z_IS_2620_EQ_2620(...) \, -#define Z_IS_2621_EQ_2621(...) \, -#define Z_IS_2622_EQ_2622(...) \, -#define Z_IS_2623_EQ_2623(...) \, -#define Z_IS_2624_EQ_2624(...) \, -#define Z_IS_2625_EQ_2625(...) \, -#define Z_IS_2626_EQ_2626(...) \, -#define Z_IS_2627_EQ_2627(...) \, -#define Z_IS_2628_EQ_2628(...) \, -#define Z_IS_2629_EQ_2629(...) \, -#define Z_IS_2630_EQ_2630(...) \, -#define Z_IS_2631_EQ_2631(...) \, -#define Z_IS_2632_EQ_2632(...) \, -#define Z_IS_2633_EQ_2633(...) \, -#define Z_IS_2634_EQ_2634(...) \, -#define Z_IS_2635_EQ_2635(...) \, -#define Z_IS_2636_EQ_2636(...) \, -#define Z_IS_2637_EQ_2637(...) \, -#define Z_IS_2638_EQ_2638(...) \, -#define Z_IS_2639_EQ_2639(...) \, -#define Z_IS_2640_EQ_2640(...) \, -#define Z_IS_2641_EQ_2641(...) \, -#define Z_IS_2642_EQ_2642(...) \, -#define Z_IS_2643_EQ_2643(...) \, -#define Z_IS_2644_EQ_2644(...) \, -#define Z_IS_2645_EQ_2645(...) \, -#define Z_IS_2646_EQ_2646(...) \, -#define Z_IS_2647_EQ_2647(...) \, -#define Z_IS_2648_EQ_2648(...) \, -#define Z_IS_2649_EQ_2649(...) \, -#define Z_IS_2650_EQ_2650(...) \, -#define Z_IS_2651_EQ_2651(...) \, -#define Z_IS_2652_EQ_2652(...) \, -#define Z_IS_2653_EQ_2653(...) \, -#define Z_IS_2654_EQ_2654(...) \, -#define Z_IS_2655_EQ_2655(...) \, -#define Z_IS_2656_EQ_2656(...) \, -#define Z_IS_2657_EQ_2657(...) \, -#define Z_IS_2658_EQ_2658(...) \, -#define Z_IS_2659_EQ_2659(...) \, -#define Z_IS_2660_EQ_2660(...) \, -#define Z_IS_2661_EQ_2661(...) \, -#define Z_IS_2662_EQ_2662(...) \, -#define Z_IS_2663_EQ_2663(...) \, -#define Z_IS_2664_EQ_2664(...) \, -#define Z_IS_2665_EQ_2665(...) \, -#define Z_IS_2666_EQ_2666(...) \, -#define Z_IS_2667_EQ_2667(...) \, -#define Z_IS_2668_EQ_2668(...) \, -#define Z_IS_2669_EQ_2669(...) \, -#define Z_IS_2670_EQ_2670(...) \, -#define Z_IS_2671_EQ_2671(...) \, -#define Z_IS_2672_EQ_2672(...) \, -#define Z_IS_2673_EQ_2673(...) \, -#define Z_IS_2674_EQ_2674(...) \, -#define Z_IS_2675_EQ_2675(...) \, -#define Z_IS_2676_EQ_2676(...) \, -#define Z_IS_2677_EQ_2677(...) \, -#define Z_IS_2678_EQ_2678(...) \, -#define Z_IS_2679_EQ_2679(...) \, -#define Z_IS_2680_EQ_2680(...) \, -#define Z_IS_2681_EQ_2681(...) \, -#define Z_IS_2682_EQ_2682(...) \, -#define Z_IS_2683_EQ_2683(...) \, -#define Z_IS_2684_EQ_2684(...) \, -#define Z_IS_2685_EQ_2685(...) \, -#define Z_IS_2686_EQ_2686(...) \, -#define Z_IS_2687_EQ_2687(...) \, -#define Z_IS_2688_EQ_2688(...) \, -#define Z_IS_2689_EQ_2689(...) \, -#define Z_IS_2690_EQ_2690(...) \, -#define Z_IS_2691_EQ_2691(...) \, -#define Z_IS_2692_EQ_2692(...) \, -#define Z_IS_2693_EQ_2693(...) \, -#define Z_IS_2694_EQ_2694(...) \, -#define Z_IS_2695_EQ_2695(...) \, -#define Z_IS_2696_EQ_2696(...) \, -#define Z_IS_2697_EQ_2697(...) \, -#define Z_IS_2698_EQ_2698(...) \, -#define Z_IS_2699_EQ_2699(...) \, -#define Z_IS_2700_EQ_2700(...) \, -#define Z_IS_2701_EQ_2701(...) \, -#define Z_IS_2702_EQ_2702(...) \, -#define Z_IS_2703_EQ_2703(...) \, -#define Z_IS_2704_EQ_2704(...) \, -#define Z_IS_2705_EQ_2705(...) \, -#define Z_IS_2706_EQ_2706(...) \, -#define Z_IS_2707_EQ_2707(...) \, -#define Z_IS_2708_EQ_2708(...) \, -#define Z_IS_2709_EQ_2709(...) \, -#define Z_IS_2710_EQ_2710(...) \, -#define Z_IS_2711_EQ_2711(...) \, -#define Z_IS_2712_EQ_2712(...) \, -#define Z_IS_2713_EQ_2713(...) \, -#define Z_IS_2714_EQ_2714(...) \, -#define Z_IS_2715_EQ_2715(...) \, -#define Z_IS_2716_EQ_2716(...) \, -#define Z_IS_2717_EQ_2717(...) \, -#define Z_IS_2718_EQ_2718(...) \, -#define Z_IS_2719_EQ_2719(...) \, -#define Z_IS_2720_EQ_2720(...) \, -#define Z_IS_2721_EQ_2721(...) \, -#define Z_IS_2722_EQ_2722(...) \, -#define Z_IS_2723_EQ_2723(...) \, -#define Z_IS_2724_EQ_2724(...) \, -#define Z_IS_2725_EQ_2725(...) \, -#define Z_IS_2726_EQ_2726(...) \, -#define Z_IS_2727_EQ_2727(...) \, -#define Z_IS_2728_EQ_2728(...) \, -#define Z_IS_2729_EQ_2729(...) \, -#define Z_IS_2730_EQ_2730(...) \, -#define Z_IS_2731_EQ_2731(...) \, -#define Z_IS_2732_EQ_2732(...) \, -#define Z_IS_2733_EQ_2733(...) \, -#define Z_IS_2734_EQ_2734(...) \, -#define Z_IS_2735_EQ_2735(...) \, -#define Z_IS_2736_EQ_2736(...) \, -#define Z_IS_2737_EQ_2737(...) \, -#define Z_IS_2738_EQ_2738(...) \, -#define Z_IS_2739_EQ_2739(...) \, -#define Z_IS_2740_EQ_2740(...) \, -#define Z_IS_2741_EQ_2741(...) \, -#define Z_IS_2742_EQ_2742(...) \, -#define Z_IS_2743_EQ_2743(...) \, -#define Z_IS_2744_EQ_2744(...) \, -#define Z_IS_2745_EQ_2745(...) \, -#define Z_IS_2746_EQ_2746(...) \, -#define Z_IS_2747_EQ_2747(...) \, -#define Z_IS_2748_EQ_2748(...) \, -#define Z_IS_2749_EQ_2749(...) \, -#define Z_IS_2750_EQ_2750(...) \, -#define Z_IS_2751_EQ_2751(...) \, -#define Z_IS_2752_EQ_2752(...) \, -#define Z_IS_2753_EQ_2753(...) \, -#define Z_IS_2754_EQ_2754(...) \, -#define Z_IS_2755_EQ_2755(...) \, -#define Z_IS_2756_EQ_2756(...) \, -#define Z_IS_2757_EQ_2757(...) \, -#define Z_IS_2758_EQ_2758(...) \, -#define Z_IS_2759_EQ_2759(...) \, -#define Z_IS_2760_EQ_2760(...) \, -#define Z_IS_2761_EQ_2761(...) \, -#define Z_IS_2762_EQ_2762(...) \, -#define Z_IS_2763_EQ_2763(...) \, -#define Z_IS_2764_EQ_2764(...) \, -#define Z_IS_2765_EQ_2765(...) \, -#define Z_IS_2766_EQ_2766(...) \, -#define Z_IS_2767_EQ_2767(...) \, -#define Z_IS_2768_EQ_2768(...) \, -#define Z_IS_2769_EQ_2769(...) \, -#define Z_IS_2770_EQ_2770(...) \, -#define Z_IS_2771_EQ_2771(...) \, -#define Z_IS_2772_EQ_2772(...) \, -#define Z_IS_2773_EQ_2773(...) \, -#define Z_IS_2774_EQ_2774(...) \, -#define Z_IS_2775_EQ_2775(...) \, -#define Z_IS_2776_EQ_2776(...) \, -#define Z_IS_2777_EQ_2777(...) \, -#define Z_IS_2778_EQ_2778(...) \, -#define Z_IS_2779_EQ_2779(...) \, -#define Z_IS_2780_EQ_2780(...) \, -#define Z_IS_2781_EQ_2781(...) \, -#define Z_IS_2782_EQ_2782(...) \, -#define Z_IS_2783_EQ_2783(...) \, -#define Z_IS_2784_EQ_2784(...) \, -#define Z_IS_2785_EQ_2785(...) \, -#define Z_IS_2786_EQ_2786(...) \, -#define Z_IS_2787_EQ_2787(...) \, -#define Z_IS_2788_EQ_2788(...) \, -#define Z_IS_2789_EQ_2789(...) \, -#define Z_IS_2790_EQ_2790(...) \, -#define Z_IS_2791_EQ_2791(...) \, -#define Z_IS_2792_EQ_2792(...) \, -#define Z_IS_2793_EQ_2793(...) \, -#define Z_IS_2794_EQ_2794(...) \, -#define Z_IS_2795_EQ_2795(...) \, -#define Z_IS_2796_EQ_2796(...) \, -#define Z_IS_2797_EQ_2797(...) \, -#define Z_IS_2798_EQ_2798(...) \, -#define Z_IS_2799_EQ_2799(...) \, -#define Z_IS_2800_EQ_2800(...) \, -#define Z_IS_2801_EQ_2801(...) \, -#define Z_IS_2802_EQ_2802(...) \, -#define Z_IS_2803_EQ_2803(...) \, -#define Z_IS_2804_EQ_2804(...) \, -#define Z_IS_2805_EQ_2805(...) \, -#define Z_IS_2806_EQ_2806(...) \, -#define Z_IS_2807_EQ_2807(...) \, -#define Z_IS_2808_EQ_2808(...) \, -#define Z_IS_2809_EQ_2809(...) \, -#define Z_IS_2810_EQ_2810(...) \, -#define Z_IS_2811_EQ_2811(...) \, -#define Z_IS_2812_EQ_2812(...) \, -#define Z_IS_2813_EQ_2813(...) \, -#define Z_IS_2814_EQ_2814(...) \, -#define Z_IS_2815_EQ_2815(...) \, -#define Z_IS_2816_EQ_2816(...) \, -#define Z_IS_2817_EQ_2817(...) \, -#define Z_IS_2818_EQ_2818(...) \, -#define Z_IS_2819_EQ_2819(...) \, -#define Z_IS_2820_EQ_2820(...) \, -#define Z_IS_2821_EQ_2821(...) \, -#define Z_IS_2822_EQ_2822(...) \, -#define Z_IS_2823_EQ_2823(...) \, -#define Z_IS_2824_EQ_2824(...) \, -#define Z_IS_2825_EQ_2825(...) \, -#define Z_IS_2826_EQ_2826(...) \, -#define Z_IS_2827_EQ_2827(...) \, -#define Z_IS_2828_EQ_2828(...) \, -#define Z_IS_2829_EQ_2829(...) \, -#define Z_IS_2830_EQ_2830(...) \, -#define Z_IS_2831_EQ_2831(...) \, -#define Z_IS_2832_EQ_2832(...) \, -#define Z_IS_2833_EQ_2833(...) \, -#define Z_IS_2834_EQ_2834(...) \, -#define Z_IS_2835_EQ_2835(...) \, -#define Z_IS_2836_EQ_2836(...) \, -#define Z_IS_2837_EQ_2837(...) \, -#define Z_IS_2838_EQ_2838(...) \, -#define Z_IS_2839_EQ_2839(...) \, -#define Z_IS_2840_EQ_2840(...) \, -#define Z_IS_2841_EQ_2841(...) \, -#define Z_IS_2842_EQ_2842(...) \, -#define Z_IS_2843_EQ_2843(...) \, -#define Z_IS_2844_EQ_2844(...) \, -#define Z_IS_2845_EQ_2845(...) \, -#define Z_IS_2846_EQ_2846(...) \, -#define Z_IS_2847_EQ_2847(...) \, -#define Z_IS_2848_EQ_2848(...) \, -#define Z_IS_2849_EQ_2849(...) \, -#define Z_IS_2850_EQ_2850(...) \, -#define Z_IS_2851_EQ_2851(...) \, -#define Z_IS_2852_EQ_2852(...) \, -#define Z_IS_2853_EQ_2853(...) \, -#define Z_IS_2854_EQ_2854(...) \, -#define Z_IS_2855_EQ_2855(...) \, -#define Z_IS_2856_EQ_2856(...) \, -#define Z_IS_2857_EQ_2857(...) \, -#define Z_IS_2858_EQ_2858(...) \, -#define Z_IS_2859_EQ_2859(...) \, -#define Z_IS_2860_EQ_2860(...) \, -#define Z_IS_2861_EQ_2861(...) \, -#define Z_IS_2862_EQ_2862(...) \, -#define Z_IS_2863_EQ_2863(...) \, -#define Z_IS_2864_EQ_2864(...) \, -#define Z_IS_2865_EQ_2865(...) \, -#define Z_IS_2866_EQ_2866(...) \, -#define Z_IS_2867_EQ_2867(...) \, -#define Z_IS_2868_EQ_2868(...) \, -#define Z_IS_2869_EQ_2869(...) \, -#define Z_IS_2870_EQ_2870(...) \, -#define Z_IS_2871_EQ_2871(...) \, -#define Z_IS_2872_EQ_2872(...) \, -#define Z_IS_2873_EQ_2873(...) \, -#define Z_IS_2874_EQ_2874(...) \, -#define Z_IS_2875_EQ_2875(...) \, -#define Z_IS_2876_EQ_2876(...) \, -#define Z_IS_2877_EQ_2877(...) \, -#define Z_IS_2878_EQ_2878(...) \, -#define Z_IS_2879_EQ_2879(...) \, -#define Z_IS_2880_EQ_2880(...) \, -#define Z_IS_2881_EQ_2881(...) \, -#define Z_IS_2882_EQ_2882(...) \, -#define Z_IS_2883_EQ_2883(...) \, -#define Z_IS_2884_EQ_2884(...) \, -#define Z_IS_2885_EQ_2885(...) \, -#define Z_IS_2886_EQ_2886(...) \, -#define Z_IS_2887_EQ_2887(...) \, -#define Z_IS_2888_EQ_2888(...) \, -#define Z_IS_2889_EQ_2889(...) \, -#define Z_IS_2890_EQ_2890(...) \, -#define Z_IS_2891_EQ_2891(...) \, -#define Z_IS_2892_EQ_2892(...) \, -#define Z_IS_2893_EQ_2893(...) \, -#define Z_IS_2894_EQ_2894(...) \, -#define Z_IS_2895_EQ_2895(...) \, -#define Z_IS_2896_EQ_2896(...) \, -#define Z_IS_2897_EQ_2897(...) \, -#define Z_IS_2898_EQ_2898(...) \, -#define Z_IS_2899_EQ_2899(...) \, -#define Z_IS_2900_EQ_2900(...) \, -#define Z_IS_2901_EQ_2901(...) \, -#define Z_IS_2902_EQ_2902(...) \, -#define Z_IS_2903_EQ_2903(...) \, -#define Z_IS_2904_EQ_2904(...) \, -#define Z_IS_2905_EQ_2905(...) \, -#define Z_IS_2906_EQ_2906(...) \, -#define Z_IS_2907_EQ_2907(...) \, -#define Z_IS_2908_EQ_2908(...) \, -#define Z_IS_2909_EQ_2909(...) \, -#define Z_IS_2910_EQ_2910(...) \, -#define Z_IS_2911_EQ_2911(...) \, -#define Z_IS_2912_EQ_2912(...) \, -#define Z_IS_2913_EQ_2913(...) \, -#define Z_IS_2914_EQ_2914(...) \, -#define Z_IS_2915_EQ_2915(...) \, -#define Z_IS_2916_EQ_2916(...) \, -#define Z_IS_2917_EQ_2917(...) \, -#define Z_IS_2918_EQ_2918(...) \, -#define Z_IS_2919_EQ_2919(...) \, -#define Z_IS_2920_EQ_2920(...) \, -#define Z_IS_2921_EQ_2921(...) \, -#define Z_IS_2922_EQ_2922(...) \, -#define Z_IS_2923_EQ_2923(...) \, -#define Z_IS_2924_EQ_2924(...) \, -#define Z_IS_2925_EQ_2925(...) \, -#define Z_IS_2926_EQ_2926(...) \, -#define Z_IS_2927_EQ_2927(...) \, -#define Z_IS_2928_EQ_2928(...) \, -#define Z_IS_2929_EQ_2929(...) \, -#define Z_IS_2930_EQ_2930(...) \, -#define Z_IS_2931_EQ_2931(...) \, -#define Z_IS_2932_EQ_2932(...) \, -#define Z_IS_2933_EQ_2933(...) \, -#define Z_IS_2934_EQ_2934(...) \, -#define Z_IS_2935_EQ_2935(...) \, -#define Z_IS_2936_EQ_2936(...) \, -#define Z_IS_2937_EQ_2937(...) \, -#define Z_IS_2938_EQ_2938(...) \, -#define Z_IS_2939_EQ_2939(...) \, -#define Z_IS_2940_EQ_2940(...) \, -#define Z_IS_2941_EQ_2941(...) \, -#define Z_IS_2942_EQ_2942(...) \, -#define Z_IS_2943_EQ_2943(...) \, -#define Z_IS_2944_EQ_2944(...) \, -#define Z_IS_2945_EQ_2945(...) \, -#define Z_IS_2946_EQ_2946(...) \, -#define Z_IS_2947_EQ_2947(...) \, -#define Z_IS_2948_EQ_2948(...) \, -#define Z_IS_2949_EQ_2949(...) \, -#define Z_IS_2950_EQ_2950(...) \, -#define Z_IS_2951_EQ_2951(...) \, -#define Z_IS_2952_EQ_2952(...) \, -#define Z_IS_2953_EQ_2953(...) \, -#define Z_IS_2954_EQ_2954(...) \, -#define Z_IS_2955_EQ_2955(...) \, -#define Z_IS_2956_EQ_2956(...) \, -#define Z_IS_2957_EQ_2957(...) \, -#define Z_IS_2958_EQ_2958(...) \, -#define Z_IS_2959_EQ_2959(...) \, -#define Z_IS_2960_EQ_2960(...) \, -#define Z_IS_2961_EQ_2961(...) \, -#define Z_IS_2962_EQ_2962(...) \, -#define Z_IS_2963_EQ_2963(...) \, -#define Z_IS_2964_EQ_2964(...) \, -#define Z_IS_2965_EQ_2965(...) \, -#define Z_IS_2966_EQ_2966(...) \, -#define Z_IS_2967_EQ_2967(...) \, -#define Z_IS_2968_EQ_2968(...) \, -#define Z_IS_2969_EQ_2969(...) \, -#define Z_IS_2970_EQ_2970(...) \, -#define Z_IS_2971_EQ_2971(...) \, -#define Z_IS_2972_EQ_2972(...) \, -#define Z_IS_2973_EQ_2973(...) \, -#define Z_IS_2974_EQ_2974(...) \, -#define Z_IS_2975_EQ_2975(...) \, -#define Z_IS_2976_EQ_2976(...) \, -#define Z_IS_2977_EQ_2977(...) \, -#define Z_IS_2978_EQ_2978(...) \, -#define Z_IS_2979_EQ_2979(...) \, -#define Z_IS_2980_EQ_2980(...) \, -#define Z_IS_2981_EQ_2981(...) \, -#define Z_IS_2982_EQ_2982(...) \, -#define Z_IS_2983_EQ_2983(...) \, -#define Z_IS_2984_EQ_2984(...) \, -#define Z_IS_2985_EQ_2985(...) \, -#define Z_IS_2986_EQ_2986(...) \, -#define Z_IS_2987_EQ_2987(...) \, -#define Z_IS_2988_EQ_2988(...) \, -#define Z_IS_2989_EQ_2989(...) \, -#define Z_IS_2990_EQ_2990(...) \, -#define Z_IS_2991_EQ_2991(...) \, -#define Z_IS_2992_EQ_2992(...) \, -#define Z_IS_2993_EQ_2993(...) \, -#define Z_IS_2994_EQ_2994(...) \, -#define Z_IS_2995_EQ_2995(...) \, -#define Z_IS_2996_EQ_2996(...) \, -#define Z_IS_2997_EQ_2997(...) \, -#define Z_IS_2998_EQ_2998(...) \, -#define Z_IS_2999_EQ_2999(...) \, -#define Z_IS_3000_EQ_3000(...) \, -#define Z_IS_3001_EQ_3001(...) \, -#define Z_IS_3002_EQ_3002(...) \, -#define Z_IS_3003_EQ_3003(...) \, -#define Z_IS_3004_EQ_3004(...) \, -#define Z_IS_3005_EQ_3005(...) \, -#define Z_IS_3006_EQ_3006(...) \, -#define Z_IS_3007_EQ_3007(...) \, -#define Z_IS_3008_EQ_3008(...) \, -#define Z_IS_3009_EQ_3009(...) \, -#define Z_IS_3010_EQ_3010(...) \, -#define Z_IS_3011_EQ_3011(...) \, -#define Z_IS_3012_EQ_3012(...) \, -#define Z_IS_3013_EQ_3013(...) \, -#define Z_IS_3014_EQ_3014(...) \, -#define Z_IS_3015_EQ_3015(...) \, -#define Z_IS_3016_EQ_3016(...) \, -#define Z_IS_3017_EQ_3017(...) \, -#define Z_IS_3018_EQ_3018(...) \, -#define Z_IS_3019_EQ_3019(...) \, -#define Z_IS_3020_EQ_3020(...) \, -#define Z_IS_3021_EQ_3021(...) \, -#define Z_IS_3022_EQ_3022(...) \, -#define Z_IS_3023_EQ_3023(...) \, -#define Z_IS_3024_EQ_3024(...) \, -#define Z_IS_3025_EQ_3025(...) \, -#define Z_IS_3026_EQ_3026(...) \, -#define Z_IS_3027_EQ_3027(...) \, -#define Z_IS_3028_EQ_3028(...) \, -#define Z_IS_3029_EQ_3029(...) \, -#define Z_IS_3030_EQ_3030(...) \, -#define Z_IS_3031_EQ_3031(...) \, -#define Z_IS_3032_EQ_3032(...) \, -#define Z_IS_3033_EQ_3033(...) \, -#define Z_IS_3034_EQ_3034(...) \, -#define Z_IS_3035_EQ_3035(...) \, -#define Z_IS_3036_EQ_3036(...) \, -#define Z_IS_3037_EQ_3037(...) \, -#define Z_IS_3038_EQ_3038(...) \, -#define Z_IS_3039_EQ_3039(...) \, -#define Z_IS_3040_EQ_3040(...) \, -#define Z_IS_3041_EQ_3041(...) \, -#define Z_IS_3042_EQ_3042(...) \, -#define Z_IS_3043_EQ_3043(...) \, -#define Z_IS_3044_EQ_3044(...) \, -#define Z_IS_3045_EQ_3045(...) \, -#define Z_IS_3046_EQ_3046(...) \, -#define Z_IS_3047_EQ_3047(...) \, -#define Z_IS_3048_EQ_3048(...) \, -#define Z_IS_3049_EQ_3049(...) \, -#define Z_IS_3050_EQ_3050(...) \, -#define Z_IS_3051_EQ_3051(...) \, -#define Z_IS_3052_EQ_3052(...) \, -#define Z_IS_3053_EQ_3053(...) \, -#define Z_IS_3054_EQ_3054(...) \, -#define Z_IS_3055_EQ_3055(...) \, -#define Z_IS_3056_EQ_3056(...) \, -#define Z_IS_3057_EQ_3057(...) \, -#define Z_IS_3058_EQ_3058(...) \, -#define Z_IS_3059_EQ_3059(...) \, -#define Z_IS_3060_EQ_3060(...) \, -#define Z_IS_3061_EQ_3061(...) \, -#define Z_IS_3062_EQ_3062(...) \, -#define Z_IS_3063_EQ_3063(...) \, -#define Z_IS_3064_EQ_3064(...) \, -#define Z_IS_3065_EQ_3065(...) \, -#define Z_IS_3066_EQ_3066(...) \, -#define Z_IS_3067_EQ_3067(...) \, -#define Z_IS_3068_EQ_3068(...) \, -#define Z_IS_3069_EQ_3069(...) \, -#define Z_IS_3070_EQ_3070(...) \, -#define Z_IS_3071_EQ_3071(...) \, -#define Z_IS_3072_EQ_3072(...) \, -#define Z_IS_3073_EQ_3073(...) \, -#define Z_IS_3074_EQ_3074(...) \, -#define Z_IS_3075_EQ_3075(...) \, -#define Z_IS_3076_EQ_3076(...) \, -#define Z_IS_3077_EQ_3077(...) \, -#define Z_IS_3078_EQ_3078(...) \, -#define Z_IS_3079_EQ_3079(...) \, -#define Z_IS_3080_EQ_3080(...) \, -#define Z_IS_3081_EQ_3081(...) \, -#define Z_IS_3082_EQ_3082(...) \, -#define Z_IS_3083_EQ_3083(...) \, -#define Z_IS_3084_EQ_3084(...) \, -#define Z_IS_3085_EQ_3085(...) \, -#define Z_IS_3086_EQ_3086(...) \, -#define Z_IS_3087_EQ_3087(...) \, -#define Z_IS_3088_EQ_3088(...) \, -#define Z_IS_3089_EQ_3089(...) \, -#define Z_IS_3090_EQ_3090(...) \, -#define Z_IS_3091_EQ_3091(...) \, -#define Z_IS_3092_EQ_3092(...) \, -#define Z_IS_3093_EQ_3093(...) \, -#define Z_IS_3094_EQ_3094(...) \, -#define Z_IS_3095_EQ_3095(...) \, -#define Z_IS_3096_EQ_3096(...) \, -#define Z_IS_3097_EQ_3097(...) \, -#define Z_IS_3098_EQ_3098(...) \, -#define Z_IS_3099_EQ_3099(...) \, -#define Z_IS_3100_EQ_3100(...) \, -#define Z_IS_3101_EQ_3101(...) \, -#define Z_IS_3102_EQ_3102(...) \, -#define Z_IS_3103_EQ_3103(...) \, -#define Z_IS_3104_EQ_3104(...) \, -#define Z_IS_3105_EQ_3105(...) \, -#define Z_IS_3106_EQ_3106(...) \, -#define Z_IS_3107_EQ_3107(...) \, -#define Z_IS_3108_EQ_3108(...) \, -#define Z_IS_3109_EQ_3109(...) \, -#define Z_IS_3110_EQ_3110(...) \, -#define Z_IS_3111_EQ_3111(...) \, -#define Z_IS_3112_EQ_3112(...) \, -#define Z_IS_3113_EQ_3113(...) \, -#define Z_IS_3114_EQ_3114(...) \, -#define Z_IS_3115_EQ_3115(...) \, -#define Z_IS_3116_EQ_3116(...) \, -#define Z_IS_3117_EQ_3117(...) \, -#define Z_IS_3118_EQ_3118(...) \, -#define Z_IS_3119_EQ_3119(...) \, -#define Z_IS_3120_EQ_3120(...) \, -#define Z_IS_3121_EQ_3121(...) \, -#define Z_IS_3122_EQ_3122(...) \, -#define Z_IS_3123_EQ_3123(...) \, -#define Z_IS_3124_EQ_3124(...) \, -#define Z_IS_3125_EQ_3125(...) \, -#define Z_IS_3126_EQ_3126(...) \, -#define Z_IS_3127_EQ_3127(...) \, -#define Z_IS_3128_EQ_3128(...) \, -#define Z_IS_3129_EQ_3129(...) \, -#define Z_IS_3130_EQ_3130(...) \, -#define Z_IS_3131_EQ_3131(...) \, -#define Z_IS_3132_EQ_3132(...) \, -#define Z_IS_3133_EQ_3133(...) \, -#define Z_IS_3134_EQ_3134(...) \, -#define Z_IS_3135_EQ_3135(...) \, -#define Z_IS_3136_EQ_3136(...) \, -#define Z_IS_3137_EQ_3137(...) \, -#define Z_IS_3138_EQ_3138(...) \, -#define Z_IS_3139_EQ_3139(...) \, -#define Z_IS_3140_EQ_3140(...) \, -#define Z_IS_3141_EQ_3141(...) \, -#define Z_IS_3142_EQ_3142(...) \, -#define Z_IS_3143_EQ_3143(...) \, -#define Z_IS_3144_EQ_3144(...) \, -#define Z_IS_3145_EQ_3145(...) \, -#define Z_IS_3146_EQ_3146(...) \, -#define Z_IS_3147_EQ_3147(...) \, -#define Z_IS_3148_EQ_3148(...) \, -#define Z_IS_3149_EQ_3149(...) \, -#define Z_IS_3150_EQ_3150(...) \, -#define Z_IS_3151_EQ_3151(...) \, -#define Z_IS_3152_EQ_3152(...) \, -#define Z_IS_3153_EQ_3153(...) \, -#define Z_IS_3154_EQ_3154(...) \, -#define Z_IS_3155_EQ_3155(...) \, -#define Z_IS_3156_EQ_3156(...) \, -#define Z_IS_3157_EQ_3157(...) \, -#define Z_IS_3158_EQ_3158(...) \, -#define Z_IS_3159_EQ_3159(...) \, -#define Z_IS_3160_EQ_3160(...) \, -#define Z_IS_3161_EQ_3161(...) \, -#define Z_IS_3162_EQ_3162(...) \, -#define Z_IS_3163_EQ_3163(...) \, -#define Z_IS_3164_EQ_3164(...) \, -#define Z_IS_3165_EQ_3165(...) \, -#define Z_IS_3166_EQ_3166(...) \, -#define Z_IS_3167_EQ_3167(...) \, -#define Z_IS_3168_EQ_3168(...) \, -#define Z_IS_3169_EQ_3169(...) \, -#define Z_IS_3170_EQ_3170(...) \, -#define Z_IS_3171_EQ_3171(...) \, -#define Z_IS_3172_EQ_3172(...) \, -#define Z_IS_3173_EQ_3173(...) \, -#define Z_IS_3174_EQ_3174(...) \, -#define Z_IS_3175_EQ_3175(...) \, -#define Z_IS_3176_EQ_3176(...) \, -#define Z_IS_3177_EQ_3177(...) \, -#define Z_IS_3178_EQ_3178(...) \, -#define Z_IS_3179_EQ_3179(...) \, -#define Z_IS_3180_EQ_3180(...) \, -#define Z_IS_3181_EQ_3181(...) \, -#define Z_IS_3182_EQ_3182(...) \, -#define Z_IS_3183_EQ_3183(...) \, -#define Z_IS_3184_EQ_3184(...) \, -#define Z_IS_3185_EQ_3185(...) \, -#define Z_IS_3186_EQ_3186(...) \, -#define Z_IS_3187_EQ_3187(...) \, -#define Z_IS_3188_EQ_3188(...) \, -#define Z_IS_3189_EQ_3189(...) \, -#define Z_IS_3190_EQ_3190(...) \, -#define Z_IS_3191_EQ_3191(...) \, -#define Z_IS_3192_EQ_3192(...) \, -#define Z_IS_3193_EQ_3193(...) \, -#define Z_IS_3194_EQ_3194(...) \, -#define Z_IS_3195_EQ_3195(...) \, -#define Z_IS_3196_EQ_3196(...) \, -#define Z_IS_3197_EQ_3197(...) \, -#define Z_IS_3198_EQ_3198(...) \, -#define Z_IS_3199_EQ_3199(...) \, -#define Z_IS_3200_EQ_3200(...) \, -#define Z_IS_3201_EQ_3201(...) \, -#define Z_IS_3202_EQ_3202(...) \, -#define Z_IS_3203_EQ_3203(...) \, -#define Z_IS_3204_EQ_3204(...) \, -#define Z_IS_3205_EQ_3205(...) \, -#define Z_IS_3206_EQ_3206(...) \, -#define Z_IS_3207_EQ_3207(...) \, -#define Z_IS_3208_EQ_3208(...) \, -#define Z_IS_3209_EQ_3209(...) \, -#define Z_IS_3210_EQ_3210(...) \, -#define Z_IS_3211_EQ_3211(...) \, -#define Z_IS_3212_EQ_3212(...) \, -#define Z_IS_3213_EQ_3213(...) \, -#define Z_IS_3214_EQ_3214(...) \, -#define Z_IS_3215_EQ_3215(...) \, -#define Z_IS_3216_EQ_3216(...) \, -#define Z_IS_3217_EQ_3217(...) \, -#define Z_IS_3218_EQ_3218(...) \, -#define Z_IS_3219_EQ_3219(...) \, -#define Z_IS_3220_EQ_3220(...) \, -#define Z_IS_3221_EQ_3221(...) \, -#define Z_IS_3222_EQ_3222(...) \, -#define Z_IS_3223_EQ_3223(...) \, -#define Z_IS_3224_EQ_3224(...) \, -#define Z_IS_3225_EQ_3225(...) \, -#define Z_IS_3226_EQ_3226(...) \, -#define Z_IS_3227_EQ_3227(...) \, -#define Z_IS_3228_EQ_3228(...) \, -#define Z_IS_3229_EQ_3229(...) \, -#define Z_IS_3230_EQ_3230(...) \, -#define Z_IS_3231_EQ_3231(...) \, -#define Z_IS_3232_EQ_3232(...) \, -#define Z_IS_3233_EQ_3233(...) \, -#define Z_IS_3234_EQ_3234(...) \, -#define Z_IS_3235_EQ_3235(...) \, -#define Z_IS_3236_EQ_3236(...) \, -#define Z_IS_3237_EQ_3237(...) \, -#define Z_IS_3238_EQ_3238(...) \, -#define Z_IS_3239_EQ_3239(...) \, -#define Z_IS_3240_EQ_3240(...) \, -#define Z_IS_3241_EQ_3241(...) \, -#define Z_IS_3242_EQ_3242(...) \, -#define Z_IS_3243_EQ_3243(...) \, -#define Z_IS_3244_EQ_3244(...) \, -#define Z_IS_3245_EQ_3245(...) \, -#define Z_IS_3246_EQ_3246(...) \, -#define Z_IS_3247_EQ_3247(...) \, -#define Z_IS_3248_EQ_3248(...) \, -#define Z_IS_3249_EQ_3249(...) \, -#define Z_IS_3250_EQ_3250(...) \, -#define Z_IS_3251_EQ_3251(...) \, -#define Z_IS_3252_EQ_3252(...) \, -#define Z_IS_3253_EQ_3253(...) \, -#define Z_IS_3254_EQ_3254(...) \, -#define Z_IS_3255_EQ_3255(...) \, -#define Z_IS_3256_EQ_3256(...) \, -#define Z_IS_3257_EQ_3257(...) \, -#define Z_IS_3258_EQ_3258(...) \, -#define Z_IS_3259_EQ_3259(...) \, -#define Z_IS_3260_EQ_3260(...) \, -#define Z_IS_3261_EQ_3261(...) \, -#define Z_IS_3262_EQ_3262(...) \, -#define Z_IS_3263_EQ_3263(...) \, -#define Z_IS_3264_EQ_3264(...) \, -#define Z_IS_3265_EQ_3265(...) \, -#define Z_IS_3266_EQ_3266(...) \, -#define Z_IS_3267_EQ_3267(...) \, -#define Z_IS_3268_EQ_3268(...) \, -#define Z_IS_3269_EQ_3269(...) \, -#define Z_IS_3270_EQ_3270(...) \, -#define Z_IS_3271_EQ_3271(...) \, -#define Z_IS_3272_EQ_3272(...) \, -#define Z_IS_3273_EQ_3273(...) \, -#define Z_IS_3274_EQ_3274(...) \, -#define Z_IS_3275_EQ_3275(...) \, -#define Z_IS_3276_EQ_3276(...) \, -#define Z_IS_3277_EQ_3277(...) \, -#define Z_IS_3278_EQ_3278(...) \, -#define Z_IS_3279_EQ_3279(...) \, -#define Z_IS_3280_EQ_3280(...) \, -#define Z_IS_3281_EQ_3281(...) \, -#define Z_IS_3282_EQ_3282(...) \, -#define Z_IS_3283_EQ_3283(...) \, -#define Z_IS_3284_EQ_3284(...) \, -#define Z_IS_3285_EQ_3285(...) \, -#define Z_IS_3286_EQ_3286(...) \, -#define Z_IS_3287_EQ_3287(...) \, -#define Z_IS_3288_EQ_3288(...) \, -#define Z_IS_3289_EQ_3289(...) \, -#define Z_IS_3290_EQ_3290(...) \, -#define Z_IS_3291_EQ_3291(...) \, -#define Z_IS_3292_EQ_3292(...) \, -#define Z_IS_3293_EQ_3293(...) \, -#define Z_IS_3294_EQ_3294(...) \, -#define Z_IS_3295_EQ_3295(...) \, -#define Z_IS_3296_EQ_3296(...) \, -#define Z_IS_3297_EQ_3297(...) \, -#define Z_IS_3298_EQ_3298(...) \, -#define Z_IS_3299_EQ_3299(...) \, -#define Z_IS_3300_EQ_3300(...) \, -#define Z_IS_3301_EQ_3301(...) \, -#define Z_IS_3302_EQ_3302(...) \, -#define Z_IS_3303_EQ_3303(...) \, -#define Z_IS_3304_EQ_3304(...) \, -#define Z_IS_3305_EQ_3305(...) \, -#define Z_IS_3306_EQ_3306(...) \, -#define Z_IS_3307_EQ_3307(...) \, -#define Z_IS_3308_EQ_3308(...) \, -#define Z_IS_3309_EQ_3309(...) \, -#define Z_IS_3310_EQ_3310(...) \, -#define Z_IS_3311_EQ_3311(...) \, -#define Z_IS_3312_EQ_3312(...) \, -#define Z_IS_3313_EQ_3313(...) \, -#define Z_IS_3314_EQ_3314(...) \, -#define Z_IS_3315_EQ_3315(...) \, -#define Z_IS_3316_EQ_3316(...) \, -#define Z_IS_3317_EQ_3317(...) \, -#define Z_IS_3318_EQ_3318(...) \, -#define Z_IS_3319_EQ_3319(...) \, -#define Z_IS_3320_EQ_3320(...) \, -#define Z_IS_3321_EQ_3321(...) \, -#define Z_IS_3322_EQ_3322(...) \, -#define Z_IS_3323_EQ_3323(...) \, -#define Z_IS_3324_EQ_3324(...) \, -#define Z_IS_3325_EQ_3325(...) \, -#define Z_IS_3326_EQ_3326(...) \, -#define Z_IS_3327_EQ_3327(...) \, -#define Z_IS_3328_EQ_3328(...) \, -#define Z_IS_3329_EQ_3329(...) \, -#define Z_IS_3330_EQ_3330(...) \, -#define Z_IS_3331_EQ_3331(...) \, -#define Z_IS_3332_EQ_3332(...) \, -#define Z_IS_3333_EQ_3333(...) \, -#define Z_IS_3334_EQ_3334(...) \, -#define Z_IS_3335_EQ_3335(...) \, -#define Z_IS_3336_EQ_3336(...) \, -#define Z_IS_3337_EQ_3337(...) \, -#define Z_IS_3338_EQ_3338(...) \, -#define Z_IS_3339_EQ_3339(...) \, -#define Z_IS_3340_EQ_3340(...) \, -#define Z_IS_3341_EQ_3341(...) \, -#define Z_IS_3342_EQ_3342(...) \, -#define Z_IS_3343_EQ_3343(...) \, -#define Z_IS_3344_EQ_3344(...) \, -#define Z_IS_3345_EQ_3345(...) \, -#define Z_IS_3346_EQ_3346(...) \, -#define Z_IS_3347_EQ_3347(...) \, -#define Z_IS_3348_EQ_3348(...) \, -#define Z_IS_3349_EQ_3349(...) \, -#define Z_IS_3350_EQ_3350(...) \, -#define Z_IS_3351_EQ_3351(...) \, -#define Z_IS_3352_EQ_3352(...) \, -#define Z_IS_3353_EQ_3353(...) \, -#define Z_IS_3354_EQ_3354(...) \, -#define Z_IS_3355_EQ_3355(...) \, -#define Z_IS_3356_EQ_3356(...) \, -#define Z_IS_3357_EQ_3357(...) \, -#define Z_IS_3358_EQ_3358(...) \, -#define Z_IS_3359_EQ_3359(...) \, -#define Z_IS_3360_EQ_3360(...) \, -#define Z_IS_3361_EQ_3361(...) \, -#define Z_IS_3362_EQ_3362(...) \, -#define Z_IS_3363_EQ_3363(...) \, -#define Z_IS_3364_EQ_3364(...) \, -#define Z_IS_3365_EQ_3365(...) \, -#define Z_IS_3366_EQ_3366(...) \, -#define Z_IS_3367_EQ_3367(...) \, -#define Z_IS_3368_EQ_3368(...) \, -#define Z_IS_3369_EQ_3369(...) \, -#define Z_IS_3370_EQ_3370(...) \, -#define Z_IS_3371_EQ_3371(...) \, -#define Z_IS_3372_EQ_3372(...) \, -#define Z_IS_3373_EQ_3373(...) \, -#define Z_IS_3374_EQ_3374(...) \, -#define Z_IS_3375_EQ_3375(...) \, -#define Z_IS_3376_EQ_3376(...) \, -#define Z_IS_3377_EQ_3377(...) \, -#define Z_IS_3378_EQ_3378(...) \, -#define Z_IS_3379_EQ_3379(...) \, -#define Z_IS_3380_EQ_3380(...) \, -#define Z_IS_3381_EQ_3381(...) \, -#define Z_IS_3382_EQ_3382(...) \, -#define Z_IS_3383_EQ_3383(...) \, -#define Z_IS_3384_EQ_3384(...) \, -#define Z_IS_3385_EQ_3385(...) \, -#define Z_IS_3386_EQ_3386(...) \, -#define Z_IS_3387_EQ_3387(...) \, -#define Z_IS_3388_EQ_3388(...) \, -#define Z_IS_3389_EQ_3389(...) \, -#define Z_IS_3390_EQ_3390(...) \, -#define Z_IS_3391_EQ_3391(...) \, -#define Z_IS_3392_EQ_3392(...) \, -#define Z_IS_3393_EQ_3393(...) \, -#define Z_IS_3394_EQ_3394(...) \, -#define Z_IS_3395_EQ_3395(...) \, -#define Z_IS_3396_EQ_3396(...) \, -#define Z_IS_3397_EQ_3397(...) \, -#define Z_IS_3398_EQ_3398(...) \, -#define Z_IS_3399_EQ_3399(...) \, -#define Z_IS_3400_EQ_3400(...) \, -#define Z_IS_3401_EQ_3401(...) \, -#define Z_IS_3402_EQ_3402(...) \, -#define Z_IS_3403_EQ_3403(...) \, -#define Z_IS_3404_EQ_3404(...) \, -#define Z_IS_3405_EQ_3405(...) \, -#define Z_IS_3406_EQ_3406(...) \, -#define Z_IS_3407_EQ_3407(...) \, -#define Z_IS_3408_EQ_3408(...) \, -#define Z_IS_3409_EQ_3409(...) \, -#define Z_IS_3410_EQ_3410(...) \, -#define Z_IS_3411_EQ_3411(...) \, -#define Z_IS_3412_EQ_3412(...) \, -#define Z_IS_3413_EQ_3413(...) \, -#define Z_IS_3414_EQ_3414(...) \, -#define Z_IS_3415_EQ_3415(...) \, -#define Z_IS_3416_EQ_3416(...) \, -#define Z_IS_3417_EQ_3417(...) \, -#define Z_IS_3418_EQ_3418(...) \, -#define Z_IS_3419_EQ_3419(...) \, -#define Z_IS_3420_EQ_3420(...) \, -#define Z_IS_3421_EQ_3421(...) \, -#define Z_IS_3422_EQ_3422(...) \, -#define Z_IS_3423_EQ_3423(...) \, -#define Z_IS_3424_EQ_3424(...) \, -#define Z_IS_3425_EQ_3425(...) \, -#define Z_IS_3426_EQ_3426(...) \, -#define Z_IS_3427_EQ_3427(...) \, -#define Z_IS_3428_EQ_3428(...) \, -#define Z_IS_3429_EQ_3429(...) \, -#define Z_IS_3430_EQ_3430(...) \, -#define Z_IS_3431_EQ_3431(...) \, -#define Z_IS_3432_EQ_3432(...) \, -#define Z_IS_3433_EQ_3433(...) \, -#define Z_IS_3434_EQ_3434(...) \, -#define Z_IS_3435_EQ_3435(...) \, -#define Z_IS_3436_EQ_3436(...) \, -#define Z_IS_3437_EQ_3437(...) \, -#define Z_IS_3438_EQ_3438(...) \, -#define Z_IS_3439_EQ_3439(...) \, -#define Z_IS_3440_EQ_3440(...) \, -#define Z_IS_3441_EQ_3441(...) \, -#define Z_IS_3442_EQ_3442(...) \, -#define Z_IS_3443_EQ_3443(...) \, -#define Z_IS_3444_EQ_3444(...) \, -#define Z_IS_3445_EQ_3445(...) \, -#define Z_IS_3446_EQ_3446(...) \, -#define Z_IS_3447_EQ_3447(...) \, -#define Z_IS_3448_EQ_3448(...) \, -#define Z_IS_3449_EQ_3449(...) \, -#define Z_IS_3450_EQ_3450(...) \, -#define Z_IS_3451_EQ_3451(...) \, -#define Z_IS_3452_EQ_3452(...) \, -#define Z_IS_3453_EQ_3453(...) \, -#define Z_IS_3454_EQ_3454(...) \, -#define Z_IS_3455_EQ_3455(...) \, -#define Z_IS_3456_EQ_3456(...) \, -#define Z_IS_3457_EQ_3457(...) \, -#define Z_IS_3458_EQ_3458(...) \, -#define Z_IS_3459_EQ_3459(...) \, -#define Z_IS_3460_EQ_3460(...) \, -#define Z_IS_3461_EQ_3461(...) \, -#define Z_IS_3462_EQ_3462(...) \, -#define Z_IS_3463_EQ_3463(...) \, -#define Z_IS_3464_EQ_3464(...) \, -#define Z_IS_3465_EQ_3465(...) \, -#define Z_IS_3466_EQ_3466(...) \, -#define Z_IS_3467_EQ_3467(...) \, -#define Z_IS_3468_EQ_3468(...) \, -#define Z_IS_3469_EQ_3469(...) \, -#define Z_IS_3470_EQ_3470(...) \, -#define Z_IS_3471_EQ_3471(...) \, -#define Z_IS_3472_EQ_3472(...) \, -#define Z_IS_3473_EQ_3473(...) \, -#define Z_IS_3474_EQ_3474(...) \, -#define Z_IS_3475_EQ_3475(...) \, -#define Z_IS_3476_EQ_3476(...) \, -#define Z_IS_3477_EQ_3477(...) \, -#define Z_IS_3478_EQ_3478(...) \, -#define Z_IS_3479_EQ_3479(...) \, -#define Z_IS_3480_EQ_3480(...) \, -#define Z_IS_3481_EQ_3481(...) \, -#define Z_IS_3482_EQ_3482(...) \, -#define Z_IS_3483_EQ_3483(...) \, -#define Z_IS_3484_EQ_3484(...) \, -#define Z_IS_3485_EQ_3485(...) \, -#define Z_IS_3486_EQ_3486(...) \, -#define Z_IS_3487_EQ_3487(...) \, -#define Z_IS_3488_EQ_3488(...) \, -#define Z_IS_3489_EQ_3489(...) \, -#define Z_IS_3490_EQ_3490(...) \, -#define Z_IS_3491_EQ_3491(...) \, -#define Z_IS_3492_EQ_3492(...) \, -#define Z_IS_3493_EQ_3493(...) \, -#define Z_IS_3494_EQ_3494(...) \, -#define Z_IS_3495_EQ_3495(...) \, -#define Z_IS_3496_EQ_3496(...) \, -#define Z_IS_3497_EQ_3497(...) \, -#define Z_IS_3498_EQ_3498(...) \, -#define Z_IS_3499_EQ_3499(...) \, -#define Z_IS_3500_EQ_3500(...) \, -#define Z_IS_3501_EQ_3501(...) \, -#define Z_IS_3502_EQ_3502(...) \, -#define Z_IS_3503_EQ_3503(...) \, -#define Z_IS_3504_EQ_3504(...) \, -#define Z_IS_3505_EQ_3505(...) \, -#define Z_IS_3506_EQ_3506(...) \, -#define Z_IS_3507_EQ_3507(...) \, -#define Z_IS_3508_EQ_3508(...) \, -#define Z_IS_3509_EQ_3509(...) \, -#define Z_IS_3510_EQ_3510(...) \, -#define Z_IS_3511_EQ_3511(...) \, -#define Z_IS_3512_EQ_3512(...) \, -#define Z_IS_3513_EQ_3513(...) \, -#define Z_IS_3514_EQ_3514(...) \, -#define Z_IS_3515_EQ_3515(...) \, -#define Z_IS_3516_EQ_3516(...) \, -#define Z_IS_3517_EQ_3517(...) \, -#define Z_IS_3518_EQ_3518(...) \, -#define Z_IS_3519_EQ_3519(...) \, -#define Z_IS_3520_EQ_3520(...) \, -#define Z_IS_3521_EQ_3521(...) \, -#define Z_IS_3522_EQ_3522(...) \, -#define Z_IS_3523_EQ_3523(...) \, -#define Z_IS_3524_EQ_3524(...) \, -#define Z_IS_3525_EQ_3525(...) \, -#define Z_IS_3526_EQ_3526(...) \, -#define Z_IS_3527_EQ_3527(...) \, -#define Z_IS_3528_EQ_3528(...) \, -#define Z_IS_3529_EQ_3529(...) \, -#define Z_IS_3530_EQ_3530(...) \, -#define Z_IS_3531_EQ_3531(...) \, -#define Z_IS_3532_EQ_3532(...) \, -#define Z_IS_3533_EQ_3533(...) \, -#define Z_IS_3534_EQ_3534(...) \, -#define Z_IS_3535_EQ_3535(...) \, -#define Z_IS_3536_EQ_3536(...) \, -#define Z_IS_3537_EQ_3537(...) \, -#define Z_IS_3538_EQ_3538(...) \, -#define Z_IS_3539_EQ_3539(...) \, -#define Z_IS_3540_EQ_3540(...) \, -#define Z_IS_3541_EQ_3541(...) \, -#define Z_IS_3542_EQ_3542(...) \, -#define Z_IS_3543_EQ_3543(...) \, -#define Z_IS_3544_EQ_3544(...) \, -#define Z_IS_3545_EQ_3545(...) \, -#define Z_IS_3546_EQ_3546(...) \, -#define Z_IS_3547_EQ_3547(...) \, -#define Z_IS_3548_EQ_3548(...) \, -#define Z_IS_3549_EQ_3549(...) \, -#define Z_IS_3550_EQ_3550(...) \, -#define Z_IS_3551_EQ_3551(...) \, -#define Z_IS_3552_EQ_3552(...) \, -#define Z_IS_3553_EQ_3553(...) \, -#define Z_IS_3554_EQ_3554(...) \, -#define Z_IS_3555_EQ_3555(...) \, -#define Z_IS_3556_EQ_3556(...) \, -#define Z_IS_3557_EQ_3557(...) \, -#define Z_IS_3558_EQ_3558(...) \, -#define Z_IS_3559_EQ_3559(...) \, -#define Z_IS_3560_EQ_3560(...) \, -#define Z_IS_3561_EQ_3561(...) \, -#define Z_IS_3562_EQ_3562(...) \, -#define Z_IS_3563_EQ_3563(...) \, -#define Z_IS_3564_EQ_3564(...) \, -#define Z_IS_3565_EQ_3565(...) \, -#define Z_IS_3566_EQ_3566(...) \, -#define Z_IS_3567_EQ_3567(...) \, -#define Z_IS_3568_EQ_3568(...) \, -#define Z_IS_3569_EQ_3569(...) \, -#define Z_IS_3570_EQ_3570(...) \, -#define Z_IS_3571_EQ_3571(...) \, -#define Z_IS_3572_EQ_3572(...) \, -#define Z_IS_3573_EQ_3573(...) \, -#define Z_IS_3574_EQ_3574(...) \, -#define Z_IS_3575_EQ_3575(...) \, -#define Z_IS_3576_EQ_3576(...) \, -#define Z_IS_3577_EQ_3577(...) \, -#define Z_IS_3578_EQ_3578(...) \, -#define Z_IS_3579_EQ_3579(...) \, -#define Z_IS_3580_EQ_3580(...) \, -#define Z_IS_3581_EQ_3581(...) \, -#define Z_IS_3582_EQ_3582(...) \, -#define Z_IS_3583_EQ_3583(...) \, -#define Z_IS_3584_EQ_3584(...) \, -#define Z_IS_3585_EQ_3585(...) \, -#define Z_IS_3586_EQ_3586(...) \, -#define Z_IS_3587_EQ_3587(...) \, -#define Z_IS_3588_EQ_3588(...) \, -#define Z_IS_3589_EQ_3589(...) \, -#define Z_IS_3590_EQ_3590(...) \, -#define Z_IS_3591_EQ_3591(...) \, -#define Z_IS_3592_EQ_3592(...) \, -#define Z_IS_3593_EQ_3593(...) \, -#define Z_IS_3594_EQ_3594(...) \, -#define Z_IS_3595_EQ_3595(...) \, -#define Z_IS_3596_EQ_3596(...) \, -#define Z_IS_3597_EQ_3597(...) \, -#define Z_IS_3598_EQ_3598(...) \, -#define Z_IS_3599_EQ_3599(...) \, -#define Z_IS_3600_EQ_3600(...) \, -#define Z_IS_3601_EQ_3601(...) \, -#define Z_IS_3602_EQ_3602(...) \, -#define Z_IS_3603_EQ_3603(...) \, -#define Z_IS_3604_EQ_3604(...) \, -#define Z_IS_3605_EQ_3605(...) \, -#define Z_IS_3606_EQ_3606(...) \, -#define Z_IS_3607_EQ_3607(...) \, -#define Z_IS_3608_EQ_3608(...) \, -#define Z_IS_3609_EQ_3609(...) \, -#define Z_IS_3610_EQ_3610(...) \, -#define Z_IS_3611_EQ_3611(...) \, -#define Z_IS_3612_EQ_3612(...) \, -#define Z_IS_3613_EQ_3613(...) \, -#define Z_IS_3614_EQ_3614(...) \, -#define Z_IS_3615_EQ_3615(...) \, -#define Z_IS_3616_EQ_3616(...) \, -#define Z_IS_3617_EQ_3617(...) \, -#define Z_IS_3618_EQ_3618(...) \, -#define Z_IS_3619_EQ_3619(...) \, -#define Z_IS_3620_EQ_3620(...) \, -#define Z_IS_3621_EQ_3621(...) \, -#define Z_IS_3622_EQ_3622(...) \, -#define Z_IS_3623_EQ_3623(...) \, -#define Z_IS_3624_EQ_3624(...) \, -#define Z_IS_3625_EQ_3625(...) \, -#define Z_IS_3626_EQ_3626(...) \, -#define Z_IS_3627_EQ_3627(...) \, -#define Z_IS_3628_EQ_3628(...) \, -#define Z_IS_3629_EQ_3629(...) \, -#define Z_IS_3630_EQ_3630(...) \, -#define Z_IS_3631_EQ_3631(...) \, -#define Z_IS_3632_EQ_3632(...) \, -#define Z_IS_3633_EQ_3633(...) \, -#define Z_IS_3634_EQ_3634(...) \, -#define Z_IS_3635_EQ_3635(...) \, -#define Z_IS_3636_EQ_3636(...) \, -#define Z_IS_3637_EQ_3637(...) \, -#define Z_IS_3638_EQ_3638(...) \, -#define Z_IS_3639_EQ_3639(...) \, -#define Z_IS_3640_EQ_3640(...) \, -#define Z_IS_3641_EQ_3641(...) \, -#define Z_IS_3642_EQ_3642(...) \, -#define Z_IS_3643_EQ_3643(...) \, -#define Z_IS_3644_EQ_3644(...) \, -#define Z_IS_3645_EQ_3645(...) \, -#define Z_IS_3646_EQ_3646(...) \, -#define Z_IS_3647_EQ_3647(...) \, -#define Z_IS_3648_EQ_3648(...) \, -#define Z_IS_3649_EQ_3649(...) \, -#define Z_IS_3650_EQ_3650(...) \, -#define Z_IS_3651_EQ_3651(...) \, -#define Z_IS_3652_EQ_3652(...) \, -#define Z_IS_3653_EQ_3653(...) \, -#define Z_IS_3654_EQ_3654(...) \, -#define Z_IS_3655_EQ_3655(...) \, -#define Z_IS_3656_EQ_3656(...) \, -#define Z_IS_3657_EQ_3657(...) \, -#define Z_IS_3658_EQ_3658(...) \, -#define Z_IS_3659_EQ_3659(...) \, -#define Z_IS_3660_EQ_3660(...) \, -#define Z_IS_3661_EQ_3661(...) \, -#define Z_IS_3662_EQ_3662(...) \, -#define Z_IS_3663_EQ_3663(...) \, -#define Z_IS_3664_EQ_3664(...) \, -#define Z_IS_3665_EQ_3665(...) \, -#define Z_IS_3666_EQ_3666(...) \, -#define Z_IS_3667_EQ_3667(...) \, -#define Z_IS_3668_EQ_3668(...) \, -#define Z_IS_3669_EQ_3669(...) \, -#define Z_IS_3670_EQ_3670(...) \, -#define Z_IS_3671_EQ_3671(...) \, -#define Z_IS_3672_EQ_3672(...) \, -#define Z_IS_3673_EQ_3673(...) \, -#define Z_IS_3674_EQ_3674(...) \, -#define Z_IS_3675_EQ_3675(...) \, -#define Z_IS_3676_EQ_3676(...) \, -#define Z_IS_3677_EQ_3677(...) \, -#define Z_IS_3678_EQ_3678(...) \, -#define Z_IS_3679_EQ_3679(...) \, -#define Z_IS_3680_EQ_3680(...) \, -#define Z_IS_3681_EQ_3681(...) \, -#define Z_IS_3682_EQ_3682(...) \, -#define Z_IS_3683_EQ_3683(...) \, -#define Z_IS_3684_EQ_3684(...) \, -#define Z_IS_3685_EQ_3685(...) \, -#define Z_IS_3686_EQ_3686(...) \, -#define Z_IS_3687_EQ_3687(...) \, -#define Z_IS_3688_EQ_3688(...) \, -#define Z_IS_3689_EQ_3689(...) \, -#define Z_IS_3690_EQ_3690(...) \, -#define Z_IS_3691_EQ_3691(...) \, -#define Z_IS_3692_EQ_3692(...) \, -#define Z_IS_3693_EQ_3693(...) \, -#define Z_IS_3694_EQ_3694(...) \, -#define Z_IS_3695_EQ_3695(...) \, -#define Z_IS_3696_EQ_3696(...) \, -#define Z_IS_3697_EQ_3697(...) \, -#define Z_IS_3698_EQ_3698(...) \, -#define Z_IS_3699_EQ_3699(...) \, -#define Z_IS_3700_EQ_3700(...) \, -#define Z_IS_3701_EQ_3701(...) \, -#define Z_IS_3702_EQ_3702(...) \, -#define Z_IS_3703_EQ_3703(...) \, -#define Z_IS_3704_EQ_3704(...) \, -#define Z_IS_3705_EQ_3705(...) \, -#define Z_IS_3706_EQ_3706(...) \, -#define Z_IS_3707_EQ_3707(...) \, -#define Z_IS_3708_EQ_3708(...) \, -#define Z_IS_3709_EQ_3709(...) \, -#define Z_IS_3710_EQ_3710(...) \, -#define Z_IS_3711_EQ_3711(...) \, -#define Z_IS_3712_EQ_3712(...) \, -#define Z_IS_3713_EQ_3713(...) \, -#define Z_IS_3714_EQ_3714(...) \, -#define Z_IS_3715_EQ_3715(...) \, -#define Z_IS_3716_EQ_3716(...) \, -#define Z_IS_3717_EQ_3717(...) \, -#define Z_IS_3718_EQ_3718(...) \, -#define Z_IS_3719_EQ_3719(...) \, -#define Z_IS_3720_EQ_3720(...) \, -#define Z_IS_3721_EQ_3721(...) \, -#define Z_IS_3722_EQ_3722(...) \, -#define Z_IS_3723_EQ_3723(...) \, -#define Z_IS_3724_EQ_3724(...) \, -#define Z_IS_3725_EQ_3725(...) \, -#define Z_IS_3726_EQ_3726(...) \, -#define Z_IS_3727_EQ_3727(...) \, -#define Z_IS_3728_EQ_3728(...) \, -#define Z_IS_3729_EQ_3729(...) \, -#define Z_IS_3730_EQ_3730(...) \, -#define Z_IS_3731_EQ_3731(...) \, -#define Z_IS_3732_EQ_3732(...) \, -#define Z_IS_3733_EQ_3733(...) \, -#define Z_IS_3734_EQ_3734(...) \, -#define Z_IS_3735_EQ_3735(...) \, -#define Z_IS_3736_EQ_3736(...) \, -#define Z_IS_3737_EQ_3737(...) \, -#define Z_IS_3738_EQ_3738(...) \, -#define Z_IS_3739_EQ_3739(...) \, -#define Z_IS_3740_EQ_3740(...) \, -#define Z_IS_3741_EQ_3741(...) \, -#define Z_IS_3742_EQ_3742(...) \, -#define Z_IS_3743_EQ_3743(...) \, -#define Z_IS_3744_EQ_3744(...) \, -#define Z_IS_3745_EQ_3745(...) \, -#define Z_IS_3746_EQ_3746(...) \, -#define Z_IS_3747_EQ_3747(...) \, -#define Z_IS_3748_EQ_3748(...) \, -#define Z_IS_3749_EQ_3749(...) \, -#define Z_IS_3750_EQ_3750(...) \, -#define Z_IS_3751_EQ_3751(...) \, -#define Z_IS_3752_EQ_3752(...) \, -#define Z_IS_3753_EQ_3753(...) \, -#define Z_IS_3754_EQ_3754(...) \, -#define Z_IS_3755_EQ_3755(...) \, -#define Z_IS_3756_EQ_3756(...) \, -#define Z_IS_3757_EQ_3757(...) \, -#define Z_IS_3758_EQ_3758(...) \, -#define Z_IS_3759_EQ_3759(...) \, -#define Z_IS_3760_EQ_3760(...) \, -#define Z_IS_3761_EQ_3761(...) \, -#define Z_IS_3762_EQ_3762(...) \, -#define Z_IS_3763_EQ_3763(...) \, -#define Z_IS_3764_EQ_3764(...) \, -#define Z_IS_3765_EQ_3765(...) \, -#define Z_IS_3766_EQ_3766(...) \, -#define Z_IS_3767_EQ_3767(...) \, -#define Z_IS_3768_EQ_3768(...) \, -#define Z_IS_3769_EQ_3769(...) \, -#define Z_IS_3770_EQ_3770(...) \, -#define Z_IS_3771_EQ_3771(...) \, -#define Z_IS_3772_EQ_3772(...) \, -#define Z_IS_3773_EQ_3773(...) \, -#define Z_IS_3774_EQ_3774(...) \, -#define Z_IS_3775_EQ_3775(...) \, -#define Z_IS_3776_EQ_3776(...) \, -#define Z_IS_3777_EQ_3777(...) \, -#define Z_IS_3778_EQ_3778(...) \, -#define Z_IS_3779_EQ_3779(...) \, -#define Z_IS_3780_EQ_3780(...) \, -#define Z_IS_3781_EQ_3781(...) \, -#define Z_IS_3782_EQ_3782(...) \, -#define Z_IS_3783_EQ_3783(...) \, -#define Z_IS_3784_EQ_3784(...) \, -#define Z_IS_3785_EQ_3785(...) \, -#define Z_IS_3786_EQ_3786(...) \, -#define Z_IS_3787_EQ_3787(...) \, -#define Z_IS_3788_EQ_3788(...) \, -#define Z_IS_3789_EQ_3789(...) \, -#define Z_IS_3790_EQ_3790(...) \, -#define Z_IS_3791_EQ_3791(...) \, -#define Z_IS_3792_EQ_3792(...) \, -#define Z_IS_3793_EQ_3793(...) \, -#define Z_IS_3794_EQ_3794(...) \, -#define Z_IS_3795_EQ_3795(...) \, -#define Z_IS_3796_EQ_3796(...) \, -#define Z_IS_3797_EQ_3797(...) \, -#define Z_IS_3798_EQ_3798(...) \, -#define Z_IS_3799_EQ_3799(...) \, -#define Z_IS_3800_EQ_3800(...) \, -#define Z_IS_3801_EQ_3801(...) \, -#define Z_IS_3802_EQ_3802(...) \, -#define Z_IS_3803_EQ_3803(...) \, -#define Z_IS_3804_EQ_3804(...) \, -#define Z_IS_3805_EQ_3805(...) \, -#define Z_IS_3806_EQ_3806(...) \, -#define Z_IS_3807_EQ_3807(...) \, -#define Z_IS_3808_EQ_3808(...) \, -#define Z_IS_3809_EQ_3809(...) \, -#define Z_IS_3810_EQ_3810(...) \, -#define Z_IS_3811_EQ_3811(...) \, -#define Z_IS_3812_EQ_3812(...) \, -#define Z_IS_3813_EQ_3813(...) \, -#define Z_IS_3814_EQ_3814(...) \, -#define Z_IS_3815_EQ_3815(...) \, -#define Z_IS_3816_EQ_3816(...) \, -#define Z_IS_3817_EQ_3817(...) \, -#define Z_IS_3818_EQ_3818(...) \, -#define Z_IS_3819_EQ_3819(...) \, -#define Z_IS_3820_EQ_3820(...) \, -#define Z_IS_3821_EQ_3821(...) \, -#define Z_IS_3822_EQ_3822(...) \, -#define Z_IS_3823_EQ_3823(...) \, -#define Z_IS_3824_EQ_3824(...) \, -#define Z_IS_3825_EQ_3825(...) \, -#define Z_IS_3826_EQ_3826(...) \, -#define Z_IS_3827_EQ_3827(...) \, -#define Z_IS_3828_EQ_3828(...) \, -#define Z_IS_3829_EQ_3829(...) \, -#define Z_IS_3830_EQ_3830(...) \, -#define Z_IS_3831_EQ_3831(...) \, -#define Z_IS_3832_EQ_3832(...) \, -#define Z_IS_3833_EQ_3833(...) \, -#define Z_IS_3834_EQ_3834(...) \, -#define Z_IS_3835_EQ_3835(...) \, -#define Z_IS_3836_EQ_3836(...) \, -#define Z_IS_3837_EQ_3837(...) \, -#define Z_IS_3838_EQ_3838(...) \, -#define Z_IS_3839_EQ_3839(...) \, -#define Z_IS_3840_EQ_3840(...) \, -#define Z_IS_3841_EQ_3841(...) \, -#define Z_IS_3842_EQ_3842(...) \, -#define Z_IS_3843_EQ_3843(...) \, -#define Z_IS_3844_EQ_3844(...) \, -#define Z_IS_3845_EQ_3845(...) \, -#define Z_IS_3846_EQ_3846(...) \, -#define Z_IS_3847_EQ_3847(...) \, -#define Z_IS_3848_EQ_3848(...) \, -#define Z_IS_3849_EQ_3849(...) \, -#define Z_IS_3850_EQ_3850(...) \, -#define Z_IS_3851_EQ_3851(...) \, -#define Z_IS_3852_EQ_3852(...) \, -#define Z_IS_3853_EQ_3853(...) \, -#define Z_IS_3854_EQ_3854(...) \, -#define Z_IS_3855_EQ_3855(...) \, -#define Z_IS_3856_EQ_3856(...) \, -#define Z_IS_3857_EQ_3857(...) \, -#define Z_IS_3858_EQ_3858(...) \, -#define Z_IS_3859_EQ_3859(...) \, -#define Z_IS_3860_EQ_3860(...) \, -#define Z_IS_3861_EQ_3861(...) \, -#define Z_IS_3862_EQ_3862(...) \, -#define Z_IS_3863_EQ_3863(...) \, -#define Z_IS_3864_EQ_3864(...) \, -#define Z_IS_3865_EQ_3865(...) \, -#define Z_IS_3866_EQ_3866(...) \, -#define Z_IS_3867_EQ_3867(...) \, -#define Z_IS_3868_EQ_3868(...) \, -#define Z_IS_3869_EQ_3869(...) \, -#define Z_IS_3870_EQ_3870(...) \, -#define Z_IS_3871_EQ_3871(...) \, -#define Z_IS_3872_EQ_3872(...) \, -#define Z_IS_3873_EQ_3873(...) \, -#define Z_IS_3874_EQ_3874(...) \, -#define Z_IS_3875_EQ_3875(...) \, -#define Z_IS_3876_EQ_3876(...) \, -#define Z_IS_3877_EQ_3877(...) \, -#define Z_IS_3878_EQ_3878(...) \, -#define Z_IS_3879_EQ_3879(...) \, -#define Z_IS_3880_EQ_3880(...) \, -#define Z_IS_3881_EQ_3881(...) \, -#define Z_IS_3882_EQ_3882(...) \, -#define Z_IS_3883_EQ_3883(...) \, -#define Z_IS_3884_EQ_3884(...) \, -#define Z_IS_3885_EQ_3885(...) \, -#define Z_IS_3886_EQ_3886(...) \, -#define Z_IS_3887_EQ_3887(...) \, -#define Z_IS_3888_EQ_3888(...) \, -#define Z_IS_3889_EQ_3889(...) \, -#define Z_IS_3890_EQ_3890(...) \, -#define Z_IS_3891_EQ_3891(...) \, -#define Z_IS_3892_EQ_3892(...) \, -#define Z_IS_3893_EQ_3893(...) \, -#define Z_IS_3894_EQ_3894(...) \, -#define Z_IS_3895_EQ_3895(...) \, -#define Z_IS_3896_EQ_3896(...) \, -#define Z_IS_3897_EQ_3897(...) \, -#define Z_IS_3898_EQ_3898(...) \, -#define Z_IS_3899_EQ_3899(...) \, -#define Z_IS_3900_EQ_3900(...) \, -#define Z_IS_3901_EQ_3901(...) \, -#define Z_IS_3902_EQ_3902(...) \, -#define Z_IS_3903_EQ_3903(...) \, -#define Z_IS_3904_EQ_3904(...) \, -#define Z_IS_3905_EQ_3905(...) \, -#define Z_IS_3906_EQ_3906(...) \, -#define Z_IS_3907_EQ_3907(...) \, -#define Z_IS_3908_EQ_3908(...) \, -#define Z_IS_3909_EQ_3909(...) \, -#define Z_IS_3910_EQ_3910(...) \, -#define Z_IS_3911_EQ_3911(...) \, -#define Z_IS_3912_EQ_3912(...) \, -#define Z_IS_3913_EQ_3913(...) \, -#define Z_IS_3914_EQ_3914(...) \, -#define Z_IS_3915_EQ_3915(...) \, -#define Z_IS_3916_EQ_3916(...) \, -#define Z_IS_3917_EQ_3917(...) \, -#define Z_IS_3918_EQ_3918(...) \, -#define Z_IS_3919_EQ_3919(...) \, -#define Z_IS_3920_EQ_3920(...) \, -#define Z_IS_3921_EQ_3921(...) \, -#define Z_IS_3922_EQ_3922(...) \, -#define Z_IS_3923_EQ_3923(...) \, -#define Z_IS_3924_EQ_3924(...) \, -#define Z_IS_3925_EQ_3925(...) \, -#define Z_IS_3926_EQ_3926(...) \, -#define Z_IS_3927_EQ_3927(...) \, -#define Z_IS_3928_EQ_3928(...) \, -#define Z_IS_3929_EQ_3929(...) \, -#define Z_IS_3930_EQ_3930(...) \, -#define Z_IS_3931_EQ_3931(...) \, -#define Z_IS_3932_EQ_3932(...) \, -#define Z_IS_3933_EQ_3933(...) \, -#define Z_IS_3934_EQ_3934(...) \, -#define Z_IS_3935_EQ_3935(...) \, -#define Z_IS_3936_EQ_3936(...) \, -#define Z_IS_3937_EQ_3937(...) \, -#define Z_IS_3938_EQ_3938(...) \, -#define Z_IS_3939_EQ_3939(...) \, -#define Z_IS_3940_EQ_3940(...) \, -#define Z_IS_3941_EQ_3941(...) \, -#define Z_IS_3942_EQ_3942(...) \, -#define Z_IS_3943_EQ_3943(...) \, -#define Z_IS_3944_EQ_3944(...) \, -#define Z_IS_3945_EQ_3945(...) \, -#define Z_IS_3946_EQ_3946(...) \, -#define Z_IS_3947_EQ_3947(...) \, -#define Z_IS_3948_EQ_3948(...) \, -#define Z_IS_3949_EQ_3949(...) \, -#define Z_IS_3950_EQ_3950(...) \, -#define Z_IS_3951_EQ_3951(...) \, -#define Z_IS_3952_EQ_3952(...) \, -#define Z_IS_3953_EQ_3953(...) \, -#define Z_IS_3954_EQ_3954(...) \, -#define Z_IS_3955_EQ_3955(...) \, -#define Z_IS_3956_EQ_3956(...) \, -#define Z_IS_3957_EQ_3957(...) \, -#define Z_IS_3958_EQ_3958(...) \, -#define Z_IS_3959_EQ_3959(...) \, -#define Z_IS_3960_EQ_3960(...) \, -#define Z_IS_3961_EQ_3961(...) \, -#define Z_IS_3962_EQ_3962(...) \, -#define Z_IS_3963_EQ_3963(...) \, -#define Z_IS_3964_EQ_3964(...) \, -#define Z_IS_3965_EQ_3965(...) \, -#define Z_IS_3966_EQ_3966(...) \, -#define Z_IS_3967_EQ_3967(...) \, -#define Z_IS_3968_EQ_3968(...) \, -#define Z_IS_3969_EQ_3969(...) \, -#define Z_IS_3970_EQ_3970(...) \, -#define Z_IS_3971_EQ_3971(...) \, -#define Z_IS_3972_EQ_3972(...) \, -#define Z_IS_3973_EQ_3973(...) \, -#define Z_IS_3974_EQ_3974(...) \, -#define Z_IS_3975_EQ_3975(...) \, -#define Z_IS_3976_EQ_3976(...) \, -#define Z_IS_3977_EQ_3977(...) \, -#define Z_IS_3978_EQ_3978(...) \, -#define Z_IS_3979_EQ_3979(...) \, -#define Z_IS_3980_EQ_3980(...) \, -#define Z_IS_3981_EQ_3981(...) \, -#define Z_IS_3982_EQ_3982(...) \, -#define Z_IS_3983_EQ_3983(...) \, -#define Z_IS_3984_EQ_3984(...) \, -#define Z_IS_3985_EQ_3985(...) \, -#define Z_IS_3986_EQ_3986(...) \, -#define Z_IS_3987_EQ_3987(...) \, -#define Z_IS_3988_EQ_3988(...) \, -#define Z_IS_3989_EQ_3989(...) \, -#define Z_IS_3990_EQ_3990(...) \, -#define Z_IS_3991_EQ_3991(...) \, -#define Z_IS_3992_EQ_3992(...) \, -#define Z_IS_3993_EQ_3993(...) \, -#define Z_IS_3994_EQ_3994(...) \, -#define Z_IS_3995_EQ_3995(...) \, -#define Z_IS_3996_EQ_3996(...) \, -#define Z_IS_3997_EQ_3997(...) \, -#define Z_IS_3998_EQ_3998(...) \, -#define Z_IS_3999_EQ_3999(...) \, -#define Z_IS_4000_EQ_4000(...) \, -#define Z_IS_4001_EQ_4001(...) \, -#define Z_IS_4002_EQ_4002(...) \, -#define Z_IS_4003_EQ_4003(...) \, -#define Z_IS_4004_EQ_4004(...) \, -#define Z_IS_4005_EQ_4005(...) \, -#define Z_IS_4006_EQ_4006(...) \, -#define Z_IS_4007_EQ_4007(...) \, -#define Z_IS_4008_EQ_4008(...) \, -#define Z_IS_4009_EQ_4009(...) \, -#define Z_IS_4010_EQ_4010(...) \, -#define Z_IS_4011_EQ_4011(...) \, -#define Z_IS_4012_EQ_4012(...) \, -#define Z_IS_4013_EQ_4013(...) \, -#define Z_IS_4014_EQ_4014(...) \, -#define Z_IS_4015_EQ_4015(...) \, -#define Z_IS_4016_EQ_4016(...) \, -#define Z_IS_4017_EQ_4017(...) \, -#define Z_IS_4018_EQ_4018(...) \, -#define Z_IS_4019_EQ_4019(...) \, -#define Z_IS_4020_EQ_4020(...) \, -#define Z_IS_4021_EQ_4021(...) \, -#define Z_IS_4022_EQ_4022(...) \, -#define Z_IS_4023_EQ_4023(...) \, -#define Z_IS_4024_EQ_4024(...) \, -#define Z_IS_4025_EQ_4025(...) \, -#define Z_IS_4026_EQ_4026(...) \, -#define Z_IS_4027_EQ_4027(...) \, -#define Z_IS_4028_EQ_4028(...) \, -#define Z_IS_4029_EQ_4029(...) \, -#define Z_IS_4030_EQ_4030(...) \, -#define Z_IS_4031_EQ_4031(...) \, -#define Z_IS_4032_EQ_4032(...) \, -#define Z_IS_4033_EQ_4033(...) \, -#define Z_IS_4034_EQ_4034(...) \, -#define Z_IS_4035_EQ_4035(...) \, -#define Z_IS_4036_EQ_4036(...) \, -#define Z_IS_4037_EQ_4037(...) \, -#define Z_IS_4038_EQ_4038(...) \, -#define Z_IS_4039_EQ_4039(...) \, -#define Z_IS_4040_EQ_4040(...) \, -#define Z_IS_4041_EQ_4041(...) \, -#define Z_IS_4042_EQ_4042(...) \, -#define Z_IS_4043_EQ_4043(...) \, -#define Z_IS_4044_EQ_4044(...) \, -#define Z_IS_4045_EQ_4045(...) \, -#define Z_IS_4046_EQ_4046(...) \, -#define Z_IS_4047_EQ_4047(...) \, -#define Z_IS_4048_EQ_4048(...) \, -#define Z_IS_4049_EQ_4049(...) \, -#define Z_IS_4050_EQ_4050(...) \, -#define Z_IS_4051_EQ_4051(...) \, -#define Z_IS_4052_EQ_4052(...) \, -#define Z_IS_4053_EQ_4053(...) \, -#define Z_IS_4054_EQ_4054(...) \, -#define Z_IS_4055_EQ_4055(...) \, -#define Z_IS_4056_EQ_4056(...) \, -#define Z_IS_4057_EQ_4057(...) \, -#define Z_IS_4058_EQ_4058(...) \, -#define Z_IS_4059_EQ_4059(...) \, -#define Z_IS_4060_EQ_4060(...) \, -#define Z_IS_4061_EQ_4061(...) \, -#define Z_IS_4062_EQ_4062(...) \, -#define Z_IS_4063_EQ_4063(...) \, -#define Z_IS_4064_EQ_4064(...) \, -#define Z_IS_4065_EQ_4065(...) \, -#define Z_IS_4066_EQ_4066(...) \, -#define Z_IS_4067_EQ_4067(...) \, -#define Z_IS_4068_EQ_4068(...) \, -#define Z_IS_4069_EQ_4069(...) \, -#define Z_IS_4070_EQ_4070(...) \, -#define Z_IS_4071_EQ_4071(...) \, -#define Z_IS_4072_EQ_4072(...) \, -#define Z_IS_4073_EQ_4073(...) \, -#define Z_IS_4074_EQ_4074(...) \, -#define Z_IS_4075_EQ_4075(...) \, -#define Z_IS_4076_EQ_4076(...) \, -#define Z_IS_4077_EQ_4077(...) \, -#define Z_IS_4078_EQ_4078(...) \, -#define Z_IS_4079_EQ_4079(...) \, -#define Z_IS_4080_EQ_4080(...) \, -#define Z_IS_4081_EQ_4081(...) \, -#define Z_IS_4082_EQ_4082(...) \, -#define Z_IS_4083_EQ_4083(...) \, -#define Z_IS_4084_EQ_4084(...) \, -#define Z_IS_4085_EQ_4085(...) \, -#define Z_IS_4086_EQ_4086(...) \, -#define Z_IS_4087_EQ_4087(...) \, -#define Z_IS_4088_EQ_4088(...) \, -#define Z_IS_4089_EQ_4089(...) \, -#define Z_IS_4090_EQ_4090(...) \, -#define Z_IS_4091_EQ_4091(...) \, -#define Z_IS_4092_EQ_4092(...) \, -#define Z_IS_4093_EQ_4093(...) \, -#define Z_IS_4094_EQ_4094(...) \, -#define Z_IS_4095_EQ_4095(...) \, -#define Z_IS_4096_EQ_4096(...) \, +#define Z_IS_0_EQ_0(...) \, +#define Z_IS_0U_EQ_0(...) \, +#define Z_IS_0_EQ_0U(...) \, +#define Z_IS_0U_EQ_0U(...) \, +#define Z_IS_1_EQ_1(...) \, +#define Z_IS_1U_EQ_1(...) \, +#define Z_IS_1_EQ_1U(...) \, +#define Z_IS_1U_EQ_1U(...) \, +#define Z_IS_2_EQ_2(...) \, +#define Z_IS_2U_EQ_2(...) \, +#define Z_IS_2_EQ_2U(...) \, +#define Z_IS_2U_EQ_2U(...) \, +#define Z_IS_3_EQ_3(...) \, +#define Z_IS_3U_EQ_3(...) \, +#define Z_IS_3_EQ_3U(...) \, +#define Z_IS_3U_EQ_3U(...) \, +#define Z_IS_4_EQ_4(...) \, +#define Z_IS_4U_EQ_4(...) \, +#define Z_IS_4_EQ_4U(...) \, +#define Z_IS_4U_EQ_4U(...) \, +#define Z_IS_5_EQ_5(...) \, +#define Z_IS_5U_EQ_5(...) \, +#define Z_IS_5_EQ_5U(...) \, +#define Z_IS_5U_EQ_5U(...) \, +#define Z_IS_6_EQ_6(...) \, +#define Z_IS_6U_EQ_6(...) \, +#define Z_IS_6_EQ_6U(...) \, +#define Z_IS_6U_EQ_6U(...) \, +#define Z_IS_7_EQ_7(...) \, +#define Z_IS_7U_EQ_7(...) \, +#define Z_IS_7_EQ_7U(...) \, +#define Z_IS_7U_EQ_7U(...) \, +#define Z_IS_8_EQ_8(...) \, +#define Z_IS_8U_EQ_8(...) \, +#define Z_IS_8_EQ_8U(...) \, +#define Z_IS_8U_EQ_8U(...) \, +#define Z_IS_9_EQ_9(...) \, +#define Z_IS_9U_EQ_9(...) \, +#define Z_IS_9_EQ_9U(...) \, +#define Z_IS_9U_EQ_9U(...) \, +#define Z_IS_10_EQ_10(...) \, +#define Z_IS_10U_EQ_10(...) \, +#define Z_IS_10_EQ_10U(...) \, +#define Z_IS_10U_EQ_10U(...) \, +#define Z_IS_11_EQ_11(...) \, +#define Z_IS_11U_EQ_11(...) \, +#define Z_IS_11_EQ_11U(...) \, +#define Z_IS_11U_EQ_11U(...) \, +#define Z_IS_12_EQ_12(...) \, +#define Z_IS_12U_EQ_12(...) \, +#define Z_IS_12_EQ_12U(...) \, +#define Z_IS_12U_EQ_12U(...) \, +#define Z_IS_13_EQ_13(...) \, +#define Z_IS_13U_EQ_13(...) \, +#define Z_IS_13_EQ_13U(...) \, +#define Z_IS_13U_EQ_13U(...) \, +#define Z_IS_14_EQ_14(...) \, +#define Z_IS_14U_EQ_14(...) \, +#define Z_IS_14_EQ_14U(...) \, +#define Z_IS_14U_EQ_14U(...) \, +#define Z_IS_15_EQ_15(...) \, +#define Z_IS_15U_EQ_15(...) \, +#define Z_IS_15_EQ_15U(...) \, +#define Z_IS_15U_EQ_15U(...) \, +#define Z_IS_16_EQ_16(...) \, +#define Z_IS_16U_EQ_16(...) \, +#define Z_IS_16_EQ_16U(...) \, +#define Z_IS_16U_EQ_16U(...) \, +#define Z_IS_17_EQ_17(...) \, +#define Z_IS_17U_EQ_17(...) \, +#define Z_IS_17_EQ_17U(...) \, +#define Z_IS_17U_EQ_17U(...) \, +#define Z_IS_18_EQ_18(...) \, +#define Z_IS_18U_EQ_18(...) \, +#define Z_IS_18_EQ_18U(...) \, +#define Z_IS_18U_EQ_18U(...) \, +#define Z_IS_19_EQ_19(...) \, +#define Z_IS_19U_EQ_19(...) \, +#define Z_IS_19_EQ_19U(...) \, +#define Z_IS_19U_EQ_19U(...) \, +#define Z_IS_20_EQ_20(...) \, +#define Z_IS_20U_EQ_20(...) \, +#define Z_IS_20_EQ_20U(...) \, +#define Z_IS_20U_EQ_20U(...) \, +#define Z_IS_21_EQ_21(...) \, +#define Z_IS_21U_EQ_21(...) \, +#define Z_IS_21_EQ_21U(...) \, +#define Z_IS_21U_EQ_21U(...) \, +#define Z_IS_22_EQ_22(...) \, +#define Z_IS_22U_EQ_22(...) \, +#define Z_IS_22_EQ_22U(...) \, +#define Z_IS_22U_EQ_22U(...) \, +#define Z_IS_23_EQ_23(...) \, +#define Z_IS_23U_EQ_23(...) \, +#define Z_IS_23_EQ_23U(...) \, +#define Z_IS_23U_EQ_23U(...) \, +#define Z_IS_24_EQ_24(...) \, +#define Z_IS_24U_EQ_24(...) \, +#define Z_IS_24_EQ_24U(...) \, +#define Z_IS_24U_EQ_24U(...) \, +#define Z_IS_25_EQ_25(...) \, +#define Z_IS_25U_EQ_25(...) \, +#define Z_IS_25_EQ_25U(...) \, +#define Z_IS_25U_EQ_25U(...) \, +#define Z_IS_26_EQ_26(...) \, +#define Z_IS_26U_EQ_26(...) \, +#define Z_IS_26_EQ_26U(...) \, +#define Z_IS_26U_EQ_26U(...) \, +#define Z_IS_27_EQ_27(...) \, +#define Z_IS_27U_EQ_27(...) \, +#define Z_IS_27_EQ_27U(...) \, +#define Z_IS_27U_EQ_27U(...) \, +#define Z_IS_28_EQ_28(...) \, +#define Z_IS_28U_EQ_28(...) \, +#define Z_IS_28_EQ_28U(...) \, +#define Z_IS_28U_EQ_28U(...) \, +#define Z_IS_29_EQ_29(...) \, +#define Z_IS_29U_EQ_29(...) \, +#define Z_IS_29_EQ_29U(...) \, +#define Z_IS_29U_EQ_29U(...) \, +#define Z_IS_30_EQ_30(...) \, +#define Z_IS_30U_EQ_30(...) \, +#define Z_IS_30_EQ_30U(...) \, +#define Z_IS_30U_EQ_30U(...) \, +#define Z_IS_31_EQ_31(...) \, +#define Z_IS_31U_EQ_31(...) \, +#define Z_IS_31_EQ_31U(...) \, +#define Z_IS_31U_EQ_31U(...) \, +#define Z_IS_32_EQ_32(...) \, +#define Z_IS_32U_EQ_32(...) \, +#define Z_IS_32_EQ_32U(...) \, +#define Z_IS_32U_EQ_32U(...) \, +#define Z_IS_33_EQ_33(...) \, +#define Z_IS_33U_EQ_33(...) \, +#define Z_IS_33_EQ_33U(...) \, +#define Z_IS_33U_EQ_33U(...) \, +#define Z_IS_34_EQ_34(...) \, +#define Z_IS_34U_EQ_34(...) \, +#define Z_IS_34_EQ_34U(...) \, +#define Z_IS_34U_EQ_34U(...) \, +#define Z_IS_35_EQ_35(...) \, +#define Z_IS_35U_EQ_35(...) \, +#define Z_IS_35_EQ_35U(...) \, +#define Z_IS_35U_EQ_35U(...) \, +#define Z_IS_36_EQ_36(...) \, +#define Z_IS_36U_EQ_36(...) \, +#define Z_IS_36_EQ_36U(...) \, +#define Z_IS_36U_EQ_36U(...) \, +#define Z_IS_37_EQ_37(...) \, +#define Z_IS_37U_EQ_37(...) \, +#define Z_IS_37_EQ_37U(...) \, +#define Z_IS_37U_EQ_37U(...) \, +#define Z_IS_38_EQ_38(...) \, +#define Z_IS_38U_EQ_38(...) \, +#define Z_IS_38_EQ_38U(...) \, +#define Z_IS_38U_EQ_38U(...) \, +#define Z_IS_39_EQ_39(...) \, +#define Z_IS_39U_EQ_39(...) \, +#define Z_IS_39_EQ_39U(...) \, +#define Z_IS_39U_EQ_39U(...) \, +#define Z_IS_40_EQ_40(...) \, +#define Z_IS_40U_EQ_40(...) \, +#define Z_IS_40_EQ_40U(...) \, +#define Z_IS_40U_EQ_40U(...) \, +#define Z_IS_41_EQ_41(...) \, +#define Z_IS_41U_EQ_41(...) \, +#define Z_IS_41_EQ_41U(...) \, +#define Z_IS_41U_EQ_41U(...) \, +#define Z_IS_42_EQ_42(...) \, +#define Z_IS_42U_EQ_42(...) \, +#define Z_IS_42_EQ_42U(...) \, +#define Z_IS_42U_EQ_42U(...) \, +#define Z_IS_43_EQ_43(...) \, +#define Z_IS_43U_EQ_43(...) \, +#define Z_IS_43_EQ_43U(...) \, +#define Z_IS_43U_EQ_43U(...) \, +#define Z_IS_44_EQ_44(...) \, +#define Z_IS_44U_EQ_44(...) \, +#define Z_IS_44_EQ_44U(...) \, +#define Z_IS_44U_EQ_44U(...) \, +#define Z_IS_45_EQ_45(...) \, +#define Z_IS_45U_EQ_45(...) \, +#define Z_IS_45_EQ_45U(...) \, +#define Z_IS_45U_EQ_45U(...) \, +#define Z_IS_46_EQ_46(...) \, +#define Z_IS_46U_EQ_46(...) \, +#define Z_IS_46_EQ_46U(...) \, +#define Z_IS_46U_EQ_46U(...) \, +#define Z_IS_47_EQ_47(...) \, +#define Z_IS_47U_EQ_47(...) \, +#define Z_IS_47_EQ_47U(...) \, +#define Z_IS_47U_EQ_47U(...) \, +#define Z_IS_48_EQ_48(...) \, +#define Z_IS_48U_EQ_48(...) \, +#define Z_IS_48_EQ_48U(...) \, +#define Z_IS_48U_EQ_48U(...) \, +#define Z_IS_49_EQ_49(...) \, +#define Z_IS_49U_EQ_49(...) \, +#define Z_IS_49_EQ_49U(...) \, +#define Z_IS_49U_EQ_49U(...) \, +#define Z_IS_50_EQ_50(...) \, +#define Z_IS_50U_EQ_50(...) \, +#define Z_IS_50_EQ_50U(...) \, +#define Z_IS_50U_EQ_50U(...) \, +#define Z_IS_51_EQ_51(...) \, +#define Z_IS_51U_EQ_51(...) \, +#define Z_IS_51_EQ_51U(...) \, +#define Z_IS_51U_EQ_51U(...) \, +#define Z_IS_52_EQ_52(...) \, +#define Z_IS_52U_EQ_52(...) \, +#define Z_IS_52_EQ_52U(...) \, +#define Z_IS_52U_EQ_52U(...) \, +#define Z_IS_53_EQ_53(...) \, +#define Z_IS_53U_EQ_53(...) \, +#define Z_IS_53_EQ_53U(...) \, +#define Z_IS_53U_EQ_53U(...) \, +#define Z_IS_54_EQ_54(...) \, +#define Z_IS_54U_EQ_54(...) \, +#define Z_IS_54_EQ_54U(...) \, +#define Z_IS_54U_EQ_54U(...) \, +#define Z_IS_55_EQ_55(...) \, +#define Z_IS_55U_EQ_55(...) \, +#define Z_IS_55_EQ_55U(...) \, +#define Z_IS_55U_EQ_55U(...) \, +#define Z_IS_56_EQ_56(...) \, +#define Z_IS_56U_EQ_56(...) \, +#define Z_IS_56_EQ_56U(...) \, +#define Z_IS_56U_EQ_56U(...) \, +#define Z_IS_57_EQ_57(...) \, +#define Z_IS_57U_EQ_57(...) \, +#define Z_IS_57_EQ_57U(...) \, +#define Z_IS_57U_EQ_57U(...) \, +#define Z_IS_58_EQ_58(...) \, +#define Z_IS_58U_EQ_58(...) \, +#define Z_IS_58_EQ_58U(...) \, +#define Z_IS_58U_EQ_58U(...) \, +#define Z_IS_59_EQ_59(...) \, +#define Z_IS_59U_EQ_59(...) \, +#define Z_IS_59_EQ_59U(...) \, +#define Z_IS_59U_EQ_59U(...) \, +#define Z_IS_60_EQ_60(...) \, +#define Z_IS_60U_EQ_60(...) \, +#define Z_IS_60_EQ_60U(...) \, +#define Z_IS_60U_EQ_60U(...) \, +#define Z_IS_61_EQ_61(...) \, +#define Z_IS_61U_EQ_61(...) \, +#define Z_IS_61_EQ_61U(...) \, +#define Z_IS_61U_EQ_61U(...) \, +#define Z_IS_62_EQ_62(...) \, +#define Z_IS_62U_EQ_62(...) \, +#define Z_IS_62_EQ_62U(...) \, +#define Z_IS_62U_EQ_62U(...) \, +#define Z_IS_63_EQ_63(...) \, +#define Z_IS_63U_EQ_63(...) \, +#define Z_IS_63_EQ_63U(...) \, +#define Z_IS_63U_EQ_63U(...) \, +#define Z_IS_64_EQ_64(...) \, +#define Z_IS_64U_EQ_64(...) \, +#define Z_IS_64_EQ_64U(...) \, +#define Z_IS_64U_EQ_64U(...) \, +#define Z_IS_65_EQ_65(...) \, +#define Z_IS_65U_EQ_65(...) \, +#define Z_IS_65_EQ_65U(...) \, +#define Z_IS_65U_EQ_65U(...) \, +#define Z_IS_66_EQ_66(...) \, +#define Z_IS_66U_EQ_66(...) \, +#define Z_IS_66_EQ_66U(...) \, +#define Z_IS_66U_EQ_66U(...) \, +#define Z_IS_67_EQ_67(...) \, +#define Z_IS_67U_EQ_67(...) \, +#define Z_IS_67_EQ_67U(...) \, +#define Z_IS_67U_EQ_67U(...) \, +#define Z_IS_68_EQ_68(...) \, +#define Z_IS_68U_EQ_68(...) \, +#define Z_IS_68_EQ_68U(...) \, +#define Z_IS_68U_EQ_68U(...) \, +#define Z_IS_69_EQ_69(...) \, +#define Z_IS_69U_EQ_69(...) \, +#define Z_IS_69_EQ_69U(...) \, +#define Z_IS_69U_EQ_69U(...) \, +#define Z_IS_70_EQ_70(...) \, +#define Z_IS_70U_EQ_70(...) \, +#define Z_IS_70_EQ_70U(...) \, +#define Z_IS_70U_EQ_70U(...) \, +#define Z_IS_71_EQ_71(...) \, +#define Z_IS_71U_EQ_71(...) \, +#define Z_IS_71_EQ_71U(...) \, +#define Z_IS_71U_EQ_71U(...) \, +#define Z_IS_72_EQ_72(...) \, +#define Z_IS_72U_EQ_72(...) \, +#define Z_IS_72_EQ_72U(...) \, +#define Z_IS_72U_EQ_72U(...) \, +#define Z_IS_73_EQ_73(...) \, +#define Z_IS_73U_EQ_73(...) \, +#define Z_IS_73_EQ_73U(...) \, +#define Z_IS_73U_EQ_73U(...) \, +#define Z_IS_74_EQ_74(...) \, +#define Z_IS_74U_EQ_74(...) \, +#define Z_IS_74_EQ_74U(...) \, +#define Z_IS_74U_EQ_74U(...) \, +#define Z_IS_75_EQ_75(...) \, +#define Z_IS_75U_EQ_75(...) \, +#define Z_IS_75_EQ_75U(...) \, +#define Z_IS_75U_EQ_75U(...) \, +#define Z_IS_76_EQ_76(...) \, +#define Z_IS_76U_EQ_76(...) \, +#define Z_IS_76_EQ_76U(...) \, +#define Z_IS_76U_EQ_76U(...) \, +#define Z_IS_77_EQ_77(...) \, +#define Z_IS_77U_EQ_77(...) \, +#define Z_IS_77_EQ_77U(...) \, +#define Z_IS_77U_EQ_77U(...) \, +#define Z_IS_78_EQ_78(...) \, +#define Z_IS_78U_EQ_78(...) \, +#define Z_IS_78_EQ_78U(...) \, +#define Z_IS_78U_EQ_78U(...) \, +#define Z_IS_79_EQ_79(...) \, +#define Z_IS_79U_EQ_79(...) \, +#define Z_IS_79_EQ_79U(...) \, +#define Z_IS_79U_EQ_79U(...) \, +#define Z_IS_80_EQ_80(...) \, +#define Z_IS_80U_EQ_80(...) \, +#define Z_IS_80_EQ_80U(...) \, +#define Z_IS_80U_EQ_80U(...) \, +#define Z_IS_81_EQ_81(...) \, +#define Z_IS_81U_EQ_81(...) \, +#define Z_IS_81_EQ_81U(...) \, +#define Z_IS_81U_EQ_81U(...) \, +#define Z_IS_82_EQ_82(...) \, +#define Z_IS_82U_EQ_82(...) \, +#define Z_IS_82_EQ_82U(...) \, +#define Z_IS_82U_EQ_82U(...) \, +#define Z_IS_83_EQ_83(...) \, +#define Z_IS_83U_EQ_83(...) \, +#define Z_IS_83_EQ_83U(...) \, +#define Z_IS_83U_EQ_83U(...) \, +#define Z_IS_84_EQ_84(...) \, +#define Z_IS_84U_EQ_84(...) \, +#define Z_IS_84_EQ_84U(...) \, +#define Z_IS_84U_EQ_84U(...) \, +#define Z_IS_85_EQ_85(...) \, +#define Z_IS_85U_EQ_85(...) \, +#define Z_IS_85_EQ_85U(...) \, +#define Z_IS_85U_EQ_85U(...) \, +#define Z_IS_86_EQ_86(...) \, +#define Z_IS_86U_EQ_86(...) \, +#define Z_IS_86_EQ_86U(...) \, +#define Z_IS_86U_EQ_86U(...) \, +#define Z_IS_87_EQ_87(...) \, +#define Z_IS_87U_EQ_87(...) \, +#define Z_IS_87_EQ_87U(...) \, +#define Z_IS_87U_EQ_87U(...) \, +#define Z_IS_88_EQ_88(...) \, +#define Z_IS_88U_EQ_88(...) \, +#define Z_IS_88_EQ_88U(...) \, +#define Z_IS_88U_EQ_88U(...) \, +#define Z_IS_89_EQ_89(...) \, +#define Z_IS_89U_EQ_89(...) \, +#define Z_IS_89_EQ_89U(...) \, +#define Z_IS_89U_EQ_89U(...) \, +#define Z_IS_90_EQ_90(...) \, +#define Z_IS_90U_EQ_90(...) \, +#define Z_IS_90_EQ_90U(...) \, +#define Z_IS_90U_EQ_90U(...) \, +#define Z_IS_91_EQ_91(...) \, +#define Z_IS_91U_EQ_91(...) \, +#define Z_IS_91_EQ_91U(...) \, +#define Z_IS_91U_EQ_91U(...) \, +#define Z_IS_92_EQ_92(...) \, +#define Z_IS_92U_EQ_92(...) \, +#define Z_IS_92_EQ_92U(...) \, +#define Z_IS_92U_EQ_92U(...) \, +#define Z_IS_93_EQ_93(...) \, +#define Z_IS_93U_EQ_93(...) \, +#define Z_IS_93_EQ_93U(...) \, +#define Z_IS_93U_EQ_93U(...) \, +#define Z_IS_94_EQ_94(...) \, +#define Z_IS_94U_EQ_94(...) \, +#define Z_IS_94_EQ_94U(...) \, +#define Z_IS_94U_EQ_94U(...) \, +#define Z_IS_95_EQ_95(...) \, +#define Z_IS_95U_EQ_95(...) \, +#define Z_IS_95_EQ_95U(...) \, +#define Z_IS_95U_EQ_95U(...) \, +#define Z_IS_96_EQ_96(...) \, +#define Z_IS_96U_EQ_96(...) \, +#define Z_IS_96_EQ_96U(...) \, +#define Z_IS_96U_EQ_96U(...) \, +#define Z_IS_97_EQ_97(...) \, +#define Z_IS_97U_EQ_97(...) \, +#define Z_IS_97_EQ_97U(...) \, +#define Z_IS_97U_EQ_97U(...) \, +#define Z_IS_98_EQ_98(...) \, +#define Z_IS_98U_EQ_98(...) \, +#define Z_IS_98_EQ_98U(...) \, +#define Z_IS_98U_EQ_98U(...) \, +#define Z_IS_99_EQ_99(...) \, +#define Z_IS_99U_EQ_99(...) \, +#define Z_IS_99_EQ_99U(...) \, +#define Z_IS_99U_EQ_99U(...) \, +#define Z_IS_100_EQ_100(...) \, +#define Z_IS_100U_EQ_100(...) \, +#define Z_IS_100_EQ_100U(...) \, +#define Z_IS_100U_EQ_100U(...) \, +#define Z_IS_101_EQ_101(...) \, +#define Z_IS_101U_EQ_101(...) \, +#define Z_IS_101_EQ_101U(...) \, +#define Z_IS_101U_EQ_101U(...) \, +#define Z_IS_102_EQ_102(...) \, +#define Z_IS_102U_EQ_102(...) \, +#define Z_IS_102_EQ_102U(...) \, +#define Z_IS_102U_EQ_102U(...) \, +#define Z_IS_103_EQ_103(...) \, +#define Z_IS_103U_EQ_103(...) \, +#define Z_IS_103_EQ_103U(...) \, +#define Z_IS_103U_EQ_103U(...) \, +#define Z_IS_104_EQ_104(...) \, +#define Z_IS_104U_EQ_104(...) \, +#define Z_IS_104_EQ_104U(...) \, +#define Z_IS_104U_EQ_104U(...) \, +#define Z_IS_105_EQ_105(...) \, +#define Z_IS_105U_EQ_105(...) \, +#define Z_IS_105_EQ_105U(...) \, +#define Z_IS_105U_EQ_105U(...) \, +#define Z_IS_106_EQ_106(...) \, +#define Z_IS_106U_EQ_106(...) \, +#define Z_IS_106_EQ_106U(...) \, +#define Z_IS_106U_EQ_106U(...) \, +#define Z_IS_107_EQ_107(...) \, +#define Z_IS_107U_EQ_107(...) \, +#define Z_IS_107_EQ_107U(...) \, +#define Z_IS_107U_EQ_107U(...) \, +#define Z_IS_108_EQ_108(...) \, +#define Z_IS_108U_EQ_108(...) \, +#define Z_IS_108_EQ_108U(...) \, +#define Z_IS_108U_EQ_108U(...) \, +#define Z_IS_109_EQ_109(...) \, +#define Z_IS_109U_EQ_109(...) \, +#define Z_IS_109_EQ_109U(...) \, +#define Z_IS_109U_EQ_109U(...) \, +#define Z_IS_110_EQ_110(...) \, +#define Z_IS_110U_EQ_110(...) \, +#define Z_IS_110_EQ_110U(...) \, +#define Z_IS_110U_EQ_110U(...) \, +#define Z_IS_111_EQ_111(...) \, +#define Z_IS_111U_EQ_111(...) \, +#define Z_IS_111_EQ_111U(...) \, +#define Z_IS_111U_EQ_111U(...) \, +#define Z_IS_112_EQ_112(...) \, +#define Z_IS_112U_EQ_112(...) \, +#define Z_IS_112_EQ_112U(...) \, +#define Z_IS_112U_EQ_112U(...) \, +#define Z_IS_113_EQ_113(...) \, +#define Z_IS_113U_EQ_113(...) \, +#define Z_IS_113_EQ_113U(...) \, +#define Z_IS_113U_EQ_113U(...) \, +#define Z_IS_114_EQ_114(...) \, +#define Z_IS_114U_EQ_114(...) \, +#define Z_IS_114_EQ_114U(...) \, +#define Z_IS_114U_EQ_114U(...) \, +#define Z_IS_115_EQ_115(...) \, +#define Z_IS_115U_EQ_115(...) \, +#define Z_IS_115_EQ_115U(...) \, +#define Z_IS_115U_EQ_115U(...) \, +#define Z_IS_116_EQ_116(...) \, +#define Z_IS_116U_EQ_116(...) \, +#define Z_IS_116_EQ_116U(...) \, +#define Z_IS_116U_EQ_116U(...) \, +#define Z_IS_117_EQ_117(...) \, +#define Z_IS_117U_EQ_117(...) \, +#define Z_IS_117_EQ_117U(...) \, +#define Z_IS_117U_EQ_117U(...) \, +#define Z_IS_118_EQ_118(...) \, +#define Z_IS_118U_EQ_118(...) \, +#define Z_IS_118_EQ_118U(...) \, +#define Z_IS_118U_EQ_118U(...) \, +#define Z_IS_119_EQ_119(...) \, +#define Z_IS_119U_EQ_119(...) \, +#define Z_IS_119_EQ_119U(...) \, +#define Z_IS_119U_EQ_119U(...) \, +#define Z_IS_120_EQ_120(...) \, +#define Z_IS_120U_EQ_120(...) \, +#define Z_IS_120_EQ_120U(...) \, +#define Z_IS_120U_EQ_120U(...) \, +#define Z_IS_121_EQ_121(...) \, +#define Z_IS_121U_EQ_121(...) \, +#define Z_IS_121_EQ_121U(...) \, +#define Z_IS_121U_EQ_121U(...) \, +#define Z_IS_122_EQ_122(...) \, +#define Z_IS_122U_EQ_122(...) \, +#define Z_IS_122_EQ_122U(...) \, +#define Z_IS_122U_EQ_122U(...) \, +#define Z_IS_123_EQ_123(...) \, +#define Z_IS_123U_EQ_123(...) \, +#define Z_IS_123_EQ_123U(...) \, +#define Z_IS_123U_EQ_123U(...) \, +#define Z_IS_124_EQ_124(...) \, +#define Z_IS_124U_EQ_124(...) \, +#define Z_IS_124_EQ_124U(...) \, +#define Z_IS_124U_EQ_124U(...) \, +#define Z_IS_125_EQ_125(...) \, +#define Z_IS_125U_EQ_125(...) \, +#define Z_IS_125_EQ_125U(...) \, +#define Z_IS_125U_EQ_125U(...) \, +#define Z_IS_126_EQ_126(...) \, +#define Z_IS_126U_EQ_126(...) \, +#define Z_IS_126_EQ_126U(...) \, +#define Z_IS_126U_EQ_126U(...) \, +#define Z_IS_127_EQ_127(...) \, +#define Z_IS_127U_EQ_127(...) \, +#define Z_IS_127_EQ_127U(...) \, +#define Z_IS_127U_EQ_127U(...) \, +#define Z_IS_128_EQ_128(...) \, +#define Z_IS_128U_EQ_128(...) \, +#define Z_IS_128_EQ_128U(...) \, +#define Z_IS_128U_EQ_128U(...) \, +#define Z_IS_129_EQ_129(...) \, +#define Z_IS_129U_EQ_129(...) \, +#define Z_IS_129_EQ_129U(...) \, +#define Z_IS_129U_EQ_129U(...) \, +#define Z_IS_130_EQ_130(...) \, +#define Z_IS_130U_EQ_130(...) \, +#define Z_IS_130_EQ_130U(...) \, +#define Z_IS_130U_EQ_130U(...) \, +#define Z_IS_131_EQ_131(...) \, +#define Z_IS_131U_EQ_131(...) \, +#define Z_IS_131_EQ_131U(...) \, +#define Z_IS_131U_EQ_131U(...) \, +#define Z_IS_132_EQ_132(...) \, +#define Z_IS_132U_EQ_132(...) \, +#define Z_IS_132_EQ_132U(...) \, +#define Z_IS_132U_EQ_132U(...) \, +#define Z_IS_133_EQ_133(...) \, +#define Z_IS_133U_EQ_133(...) \, +#define Z_IS_133_EQ_133U(...) \, +#define Z_IS_133U_EQ_133U(...) \, +#define Z_IS_134_EQ_134(...) \, +#define Z_IS_134U_EQ_134(...) \, +#define Z_IS_134_EQ_134U(...) \, +#define Z_IS_134U_EQ_134U(...) \, +#define Z_IS_135_EQ_135(...) \, +#define Z_IS_135U_EQ_135(...) \, +#define Z_IS_135_EQ_135U(...) \, +#define Z_IS_135U_EQ_135U(...) \, +#define Z_IS_136_EQ_136(...) \, +#define Z_IS_136U_EQ_136(...) \, +#define Z_IS_136_EQ_136U(...) \, +#define Z_IS_136U_EQ_136U(...) \, +#define Z_IS_137_EQ_137(...) \, +#define Z_IS_137U_EQ_137(...) \, +#define Z_IS_137_EQ_137U(...) \, +#define Z_IS_137U_EQ_137U(...) \, +#define Z_IS_138_EQ_138(...) \, +#define Z_IS_138U_EQ_138(...) \, +#define Z_IS_138_EQ_138U(...) \, +#define Z_IS_138U_EQ_138U(...) \, +#define Z_IS_139_EQ_139(...) \, +#define Z_IS_139U_EQ_139(...) \, +#define Z_IS_139_EQ_139U(...) \, +#define Z_IS_139U_EQ_139U(...) \, +#define Z_IS_140_EQ_140(...) \, +#define Z_IS_140U_EQ_140(...) \, +#define Z_IS_140_EQ_140U(...) \, +#define Z_IS_140U_EQ_140U(...) \, +#define Z_IS_141_EQ_141(...) \, +#define Z_IS_141U_EQ_141(...) \, +#define Z_IS_141_EQ_141U(...) \, +#define Z_IS_141U_EQ_141U(...) \, +#define Z_IS_142_EQ_142(...) \, +#define Z_IS_142U_EQ_142(...) \, +#define Z_IS_142_EQ_142U(...) \, +#define Z_IS_142U_EQ_142U(...) \, +#define Z_IS_143_EQ_143(...) \, +#define Z_IS_143U_EQ_143(...) \, +#define Z_IS_143_EQ_143U(...) \, +#define Z_IS_143U_EQ_143U(...) \, +#define Z_IS_144_EQ_144(...) \, +#define Z_IS_144U_EQ_144(...) \, +#define Z_IS_144_EQ_144U(...) \, +#define Z_IS_144U_EQ_144U(...) \, +#define Z_IS_145_EQ_145(...) \, +#define Z_IS_145U_EQ_145(...) \, +#define Z_IS_145_EQ_145U(...) \, +#define Z_IS_145U_EQ_145U(...) \, +#define Z_IS_146_EQ_146(...) \, +#define Z_IS_146U_EQ_146(...) \, +#define Z_IS_146_EQ_146U(...) \, +#define Z_IS_146U_EQ_146U(...) \, +#define Z_IS_147_EQ_147(...) \, +#define Z_IS_147U_EQ_147(...) \, +#define Z_IS_147_EQ_147U(...) \, +#define Z_IS_147U_EQ_147U(...) \, +#define Z_IS_148_EQ_148(...) \, +#define Z_IS_148U_EQ_148(...) \, +#define Z_IS_148_EQ_148U(...) \, +#define Z_IS_148U_EQ_148U(...) \, +#define Z_IS_149_EQ_149(...) \, +#define Z_IS_149U_EQ_149(...) \, +#define Z_IS_149_EQ_149U(...) \, +#define Z_IS_149U_EQ_149U(...) \, +#define Z_IS_150_EQ_150(...) \, +#define Z_IS_150U_EQ_150(...) \, +#define Z_IS_150_EQ_150U(...) \, +#define Z_IS_150U_EQ_150U(...) \, +#define Z_IS_151_EQ_151(...) \, +#define Z_IS_151U_EQ_151(...) \, +#define Z_IS_151_EQ_151U(...) \, +#define Z_IS_151U_EQ_151U(...) \, +#define Z_IS_152_EQ_152(...) \, +#define Z_IS_152U_EQ_152(...) \, +#define Z_IS_152_EQ_152U(...) \, +#define Z_IS_152U_EQ_152U(...) \, +#define Z_IS_153_EQ_153(...) \, +#define Z_IS_153U_EQ_153(...) \, +#define Z_IS_153_EQ_153U(...) \, +#define Z_IS_153U_EQ_153U(...) \, +#define Z_IS_154_EQ_154(...) \, +#define Z_IS_154U_EQ_154(...) \, +#define Z_IS_154_EQ_154U(...) \, +#define Z_IS_154U_EQ_154U(...) \, +#define Z_IS_155_EQ_155(...) \, +#define Z_IS_155U_EQ_155(...) \, +#define Z_IS_155_EQ_155U(...) \, +#define Z_IS_155U_EQ_155U(...) \, +#define Z_IS_156_EQ_156(...) \, +#define Z_IS_156U_EQ_156(...) \, +#define Z_IS_156_EQ_156U(...) \, +#define Z_IS_156U_EQ_156U(...) \, +#define Z_IS_157_EQ_157(...) \, +#define Z_IS_157U_EQ_157(...) \, +#define Z_IS_157_EQ_157U(...) \, +#define Z_IS_157U_EQ_157U(...) \, +#define Z_IS_158_EQ_158(...) \, +#define Z_IS_158U_EQ_158(...) \, +#define Z_IS_158_EQ_158U(...) \, +#define Z_IS_158U_EQ_158U(...) \, +#define Z_IS_159_EQ_159(...) \, +#define Z_IS_159U_EQ_159(...) \, +#define Z_IS_159_EQ_159U(...) \, +#define Z_IS_159U_EQ_159U(...) \, +#define Z_IS_160_EQ_160(...) \, +#define Z_IS_160U_EQ_160(...) \, +#define Z_IS_160_EQ_160U(...) \, +#define Z_IS_160U_EQ_160U(...) \, +#define Z_IS_161_EQ_161(...) \, +#define Z_IS_161U_EQ_161(...) \, +#define Z_IS_161_EQ_161U(...) \, +#define Z_IS_161U_EQ_161U(...) \, +#define Z_IS_162_EQ_162(...) \, +#define Z_IS_162U_EQ_162(...) \, +#define Z_IS_162_EQ_162U(...) \, +#define Z_IS_162U_EQ_162U(...) \, +#define Z_IS_163_EQ_163(...) \, +#define Z_IS_163U_EQ_163(...) \, +#define Z_IS_163_EQ_163U(...) \, +#define Z_IS_163U_EQ_163U(...) \, +#define Z_IS_164_EQ_164(...) \, +#define Z_IS_164U_EQ_164(...) \, +#define Z_IS_164_EQ_164U(...) \, +#define Z_IS_164U_EQ_164U(...) \, +#define Z_IS_165_EQ_165(...) \, +#define Z_IS_165U_EQ_165(...) \, +#define Z_IS_165_EQ_165U(...) \, +#define Z_IS_165U_EQ_165U(...) \, +#define Z_IS_166_EQ_166(...) \, +#define Z_IS_166U_EQ_166(...) \, +#define Z_IS_166_EQ_166U(...) \, +#define Z_IS_166U_EQ_166U(...) \, +#define Z_IS_167_EQ_167(...) \, +#define Z_IS_167U_EQ_167(...) \, +#define Z_IS_167_EQ_167U(...) \, +#define Z_IS_167U_EQ_167U(...) \, +#define Z_IS_168_EQ_168(...) \, +#define Z_IS_168U_EQ_168(...) \, +#define Z_IS_168_EQ_168U(...) \, +#define Z_IS_168U_EQ_168U(...) \, +#define Z_IS_169_EQ_169(...) \, +#define Z_IS_169U_EQ_169(...) \, +#define Z_IS_169_EQ_169U(...) \, +#define Z_IS_169U_EQ_169U(...) \, +#define Z_IS_170_EQ_170(...) \, +#define Z_IS_170U_EQ_170(...) \, +#define Z_IS_170_EQ_170U(...) \, +#define Z_IS_170U_EQ_170U(...) \, +#define Z_IS_171_EQ_171(...) \, +#define Z_IS_171U_EQ_171(...) \, +#define Z_IS_171_EQ_171U(...) \, +#define Z_IS_171U_EQ_171U(...) \, +#define Z_IS_172_EQ_172(...) \, +#define Z_IS_172U_EQ_172(...) \, +#define Z_IS_172_EQ_172U(...) \, +#define Z_IS_172U_EQ_172U(...) \, +#define Z_IS_173_EQ_173(...) \, +#define Z_IS_173U_EQ_173(...) \, +#define Z_IS_173_EQ_173U(...) \, +#define Z_IS_173U_EQ_173U(...) \, +#define Z_IS_174_EQ_174(...) \, +#define Z_IS_174U_EQ_174(...) \, +#define Z_IS_174_EQ_174U(...) \, +#define Z_IS_174U_EQ_174U(...) \, +#define Z_IS_175_EQ_175(...) \, +#define Z_IS_175U_EQ_175(...) \, +#define Z_IS_175_EQ_175U(...) \, +#define Z_IS_175U_EQ_175U(...) \, +#define Z_IS_176_EQ_176(...) \, +#define Z_IS_176U_EQ_176(...) \, +#define Z_IS_176_EQ_176U(...) \, +#define Z_IS_176U_EQ_176U(...) \, +#define Z_IS_177_EQ_177(...) \, +#define Z_IS_177U_EQ_177(...) \, +#define Z_IS_177_EQ_177U(...) \, +#define Z_IS_177U_EQ_177U(...) \, +#define Z_IS_178_EQ_178(...) \, +#define Z_IS_178U_EQ_178(...) \, +#define Z_IS_178_EQ_178U(...) \, +#define Z_IS_178U_EQ_178U(...) \, +#define Z_IS_179_EQ_179(...) \, +#define Z_IS_179U_EQ_179(...) \, +#define Z_IS_179_EQ_179U(...) \, +#define Z_IS_179U_EQ_179U(...) \, +#define Z_IS_180_EQ_180(...) \, +#define Z_IS_180U_EQ_180(...) \, +#define Z_IS_180_EQ_180U(...) \, +#define Z_IS_180U_EQ_180U(...) \, +#define Z_IS_181_EQ_181(...) \, +#define Z_IS_181U_EQ_181(...) \, +#define Z_IS_181_EQ_181U(...) \, +#define Z_IS_181U_EQ_181U(...) \, +#define Z_IS_182_EQ_182(...) \, +#define Z_IS_182U_EQ_182(...) \, +#define Z_IS_182_EQ_182U(...) \, +#define Z_IS_182U_EQ_182U(...) \, +#define Z_IS_183_EQ_183(...) \, +#define Z_IS_183U_EQ_183(...) \, +#define Z_IS_183_EQ_183U(...) \, +#define Z_IS_183U_EQ_183U(...) \, +#define Z_IS_184_EQ_184(...) \, +#define Z_IS_184U_EQ_184(...) \, +#define Z_IS_184_EQ_184U(...) \, +#define Z_IS_184U_EQ_184U(...) \, +#define Z_IS_185_EQ_185(...) \, +#define Z_IS_185U_EQ_185(...) \, +#define Z_IS_185_EQ_185U(...) \, +#define Z_IS_185U_EQ_185U(...) \, +#define Z_IS_186_EQ_186(...) \, +#define Z_IS_186U_EQ_186(...) \, +#define Z_IS_186_EQ_186U(...) \, +#define Z_IS_186U_EQ_186U(...) \, +#define Z_IS_187_EQ_187(...) \, +#define Z_IS_187U_EQ_187(...) \, +#define Z_IS_187_EQ_187U(...) \, +#define Z_IS_187U_EQ_187U(...) \, +#define Z_IS_188_EQ_188(...) \, +#define Z_IS_188U_EQ_188(...) \, +#define Z_IS_188_EQ_188U(...) \, +#define Z_IS_188U_EQ_188U(...) \, +#define Z_IS_189_EQ_189(...) \, +#define Z_IS_189U_EQ_189(...) \, +#define Z_IS_189_EQ_189U(...) \, +#define Z_IS_189U_EQ_189U(...) \, +#define Z_IS_190_EQ_190(...) \, +#define Z_IS_190U_EQ_190(...) \, +#define Z_IS_190_EQ_190U(...) \, +#define Z_IS_190U_EQ_190U(...) \, +#define Z_IS_191_EQ_191(...) \, +#define Z_IS_191U_EQ_191(...) \, +#define Z_IS_191_EQ_191U(...) \, +#define Z_IS_191U_EQ_191U(...) \, +#define Z_IS_192_EQ_192(...) \, +#define Z_IS_192U_EQ_192(...) \, +#define Z_IS_192_EQ_192U(...) \, +#define Z_IS_192U_EQ_192U(...) \, +#define Z_IS_193_EQ_193(...) \, +#define Z_IS_193U_EQ_193(...) \, +#define Z_IS_193_EQ_193U(...) \, +#define Z_IS_193U_EQ_193U(...) \, +#define Z_IS_194_EQ_194(...) \, +#define Z_IS_194U_EQ_194(...) \, +#define Z_IS_194_EQ_194U(...) \, +#define Z_IS_194U_EQ_194U(...) \, +#define Z_IS_195_EQ_195(...) \, +#define Z_IS_195U_EQ_195(...) \, +#define Z_IS_195_EQ_195U(...) \, +#define Z_IS_195U_EQ_195U(...) \, +#define Z_IS_196_EQ_196(...) \, +#define Z_IS_196U_EQ_196(...) \, +#define Z_IS_196_EQ_196U(...) \, +#define Z_IS_196U_EQ_196U(...) \, +#define Z_IS_197_EQ_197(...) \, +#define Z_IS_197U_EQ_197(...) \, +#define Z_IS_197_EQ_197U(...) \, +#define Z_IS_197U_EQ_197U(...) \, +#define Z_IS_198_EQ_198(...) \, +#define Z_IS_198U_EQ_198(...) \, +#define Z_IS_198_EQ_198U(...) \, +#define Z_IS_198U_EQ_198U(...) \, +#define Z_IS_199_EQ_199(...) \, +#define Z_IS_199U_EQ_199(...) \, +#define Z_IS_199_EQ_199U(...) \, +#define Z_IS_199U_EQ_199U(...) \, +#define Z_IS_200_EQ_200(...) \, +#define Z_IS_200U_EQ_200(...) \, +#define Z_IS_200_EQ_200U(...) \, +#define Z_IS_200U_EQ_200U(...) \, +#define Z_IS_201_EQ_201(...) \, +#define Z_IS_201U_EQ_201(...) \, +#define Z_IS_201_EQ_201U(...) \, +#define Z_IS_201U_EQ_201U(...) \, +#define Z_IS_202_EQ_202(...) \, +#define Z_IS_202U_EQ_202(...) \, +#define Z_IS_202_EQ_202U(...) \, +#define Z_IS_202U_EQ_202U(...) \, +#define Z_IS_203_EQ_203(...) \, +#define Z_IS_203U_EQ_203(...) \, +#define Z_IS_203_EQ_203U(...) \, +#define Z_IS_203U_EQ_203U(...) \, +#define Z_IS_204_EQ_204(...) \, +#define Z_IS_204U_EQ_204(...) \, +#define Z_IS_204_EQ_204U(...) \, +#define Z_IS_204U_EQ_204U(...) \, +#define Z_IS_205_EQ_205(...) \, +#define Z_IS_205U_EQ_205(...) \, +#define Z_IS_205_EQ_205U(...) \, +#define Z_IS_205U_EQ_205U(...) \, +#define Z_IS_206_EQ_206(...) \, +#define Z_IS_206U_EQ_206(...) \, +#define Z_IS_206_EQ_206U(...) \, +#define Z_IS_206U_EQ_206U(...) \, +#define Z_IS_207_EQ_207(...) \, +#define Z_IS_207U_EQ_207(...) \, +#define Z_IS_207_EQ_207U(...) \, +#define Z_IS_207U_EQ_207U(...) \, +#define Z_IS_208_EQ_208(...) \, +#define Z_IS_208U_EQ_208(...) \, +#define Z_IS_208_EQ_208U(...) \, +#define Z_IS_208U_EQ_208U(...) \, +#define Z_IS_209_EQ_209(...) \, +#define Z_IS_209U_EQ_209(...) \, +#define Z_IS_209_EQ_209U(...) \, +#define Z_IS_209U_EQ_209U(...) \, +#define Z_IS_210_EQ_210(...) \, +#define Z_IS_210U_EQ_210(...) \, +#define Z_IS_210_EQ_210U(...) \, +#define Z_IS_210U_EQ_210U(...) \, +#define Z_IS_211_EQ_211(...) \, +#define Z_IS_211U_EQ_211(...) \, +#define Z_IS_211_EQ_211U(...) \, +#define Z_IS_211U_EQ_211U(...) \, +#define Z_IS_212_EQ_212(...) \, +#define Z_IS_212U_EQ_212(...) \, +#define Z_IS_212_EQ_212U(...) \, +#define Z_IS_212U_EQ_212U(...) \, +#define Z_IS_213_EQ_213(...) \, +#define Z_IS_213U_EQ_213(...) \, +#define Z_IS_213_EQ_213U(...) \, +#define Z_IS_213U_EQ_213U(...) \, +#define Z_IS_214_EQ_214(...) \, +#define Z_IS_214U_EQ_214(...) \, +#define Z_IS_214_EQ_214U(...) \, +#define Z_IS_214U_EQ_214U(...) \, +#define Z_IS_215_EQ_215(...) \, +#define Z_IS_215U_EQ_215(...) \, +#define Z_IS_215_EQ_215U(...) \, +#define Z_IS_215U_EQ_215U(...) \, +#define Z_IS_216_EQ_216(...) \, +#define Z_IS_216U_EQ_216(...) \, +#define Z_IS_216_EQ_216U(...) \, +#define Z_IS_216U_EQ_216U(...) \, +#define Z_IS_217_EQ_217(...) \, +#define Z_IS_217U_EQ_217(...) \, +#define Z_IS_217_EQ_217U(...) \, +#define Z_IS_217U_EQ_217U(...) \, +#define Z_IS_218_EQ_218(...) \, +#define Z_IS_218U_EQ_218(...) \, +#define Z_IS_218_EQ_218U(...) \, +#define Z_IS_218U_EQ_218U(...) \, +#define Z_IS_219_EQ_219(...) \, +#define Z_IS_219U_EQ_219(...) \, +#define Z_IS_219_EQ_219U(...) \, +#define Z_IS_219U_EQ_219U(...) \, +#define Z_IS_220_EQ_220(...) \, +#define Z_IS_220U_EQ_220(...) \, +#define Z_IS_220_EQ_220U(...) \, +#define Z_IS_220U_EQ_220U(...) \, +#define Z_IS_221_EQ_221(...) \, +#define Z_IS_221U_EQ_221(...) \, +#define Z_IS_221_EQ_221U(...) \, +#define Z_IS_221U_EQ_221U(...) \, +#define Z_IS_222_EQ_222(...) \, +#define Z_IS_222U_EQ_222(...) \, +#define Z_IS_222_EQ_222U(...) \, +#define Z_IS_222U_EQ_222U(...) \, +#define Z_IS_223_EQ_223(...) \, +#define Z_IS_223U_EQ_223(...) \, +#define Z_IS_223_EQ_223U(...) \, +#define Z_IS_223U_EQ_223U(...) \, +#define Z_IS_224_EQ_224(...) \, +#define Z_IS_224U_EQ_224(...) \, +#define Z_IS_224_EQ_224U(...) \, +#define Z_IS_224U_EQ_224U(...) \, +#define Z_IS_225_EQ_225(...) \, +#define Z_IS_225U_EQ_225(...) \, +#define Z_IS_225_EQ_225U(...) \, +#define Z_IS_225U_EQ_225U(...) \, +#define Z_IS_226_EQ_226(...) \, +#define Z_IS_226U_EQ_226(...) \, +#define Z_IS_226_EQ_226U(...) \, +#define Z_IS_226U_EQ_226U(...) \, +#define Z_IS_227_EQ_227(...) \, +#define Z_IS_227U_EQ_227(...) \, +#define Z_IS_227_EQ_227U(...) \, +#define Z_IS_227U_EQ_227U(...) \, +#define Z_IS_228_EQ_228(...) \, +#define Z_IS_228U_EQ_228(...) \, +#define Z_IS_228_EQ_228U(...) \, +#define Z_IS_228U_EQ_228U(...) \, +#define Z_IS_229_EQ_229(...) \, +#define Z_IS_229U_EQ_229(...) \, +#define Z_IS_229_EQ_229U(...) \, +#define Z_IS_229U_EQ_229U(...) \, +#define Z_IS_230_EQ_230(...) \, +#define Z_IS_230U_EQ_230(...) \, +#define Z_IS_230_EQ_230U(...) \, +#define Z_IS_230U_EQ_230U(...) \, +#define Z_IS_231_EQ_231(...) \, +#define Z_IS_231U_EQ_231(...) \, +#define Z_IS_231_EQ_231U(...) \, +#define Z_IS_231U_EQ_231U(...) \, +#define Z_IS_232_EQ_232(...) \, +#define Z_IS_232U_EQ_232(...) \, +#define Z_IS_232_EQ_232U(...) \, +#define Z_IS_232U_EQ_232U(...) \, +#define Z_IS_233_EQ_233(...) \, +#define Z_IS_233U_EQ_233(...) \, +#define Z_IS_233_EQ_233U(...) \, +#define Z_IS_233U_EQ_233U(...) \, +#define Z_IS_234_EQ_234(...) \, +#define Z_IS_234U_EQ_234(...) \, +#define Z_IS_234_EQ_234U(...) \, +#define Z_IS_234U_EQ_234U(...) \, +#define Z_IS_235_EQ_235(...) \, +#define Z_IS_235U_EQ_235(...) \, +#define Z_IS_235_EQ_235U(...) \, +#define Z_IS_235U_EQ_235U(...) \, +#define Z_IS_236_EQ_236(...) \, +#define Z_IS_236U_EQ_236(...) \, +#define Z_IS_236_EQ_236U(...) \, +#define Z_IS_236U_EQ_236U(...) \, +#define Z_IS_237_EQ_237(...) \, +#define Z_IS_237U_EQ_237(...) \, +#define Z_IS_237_EQ_237U(...) \, +#define Z_IS_237U_EQ_237U(...) \, +#define Z_IS_238_EQ_238(...) \, +#define Z_IS_238U_EQ_238(...) \, +#define Z_IS_238_EQ_238U(...) \, +#define Z_IS_238U_EQ_238U(...) \, +#define Z_IS_239_EQ_239(...) \, +#define Z_IS_239U_EQ_239(...) \, +#define Z_IS_239_EQ_239U(...) \, +#define Z_IS_239U_EQ_239U(...) \, +#define Z_IS_240_EQ_240(...) \, +#define Z_IS_240U_EQ_240(...) \, +#define Z_IS_240_EQ_240U(...) \, +#define Z_IS_240U_EQ_240U(...) \, +#define Z_IS_241_EQ_241(...) \, +#define Z_IS_241U_EQ_241(...) \, +#define Z_IS_241_EQ_241U(...) \, +#define Z_IS_241U_EQ_241U(...) \, +#define Z_IS_242_EQ_242(...) \, +#define Z_IS_242U_EQ_242(...) \, +#define Z_IS_242_EQ_242U(...) \, +#define Z_IS_242U_EQ_242U(...) \, +#define Z_IS_243_EQ_243(...) \, +#define Z_IS_243U_EQ_243(...) \, +#define Z_IS_243_EQ_243U(...) \, +#define Z_IS_243U_EQ_243U(...) \, +#define Z_IS_244_EQ_244(...) \, +#define Z_IS_244U_EQ_244(...) \, +#define Z_IS_244_EQ_244U(...) \, +#define Z_IS_244U_EQ_244U(...) \, +#define Z_IS_245_EQ_245(...) \, +#define Z_IS_245U_EQ_245(...) \, +#define Z_IS_245_EQ_245U(...) \, +#define Z_IS_245U_EQ_245U(...) \, +#define Z_IS_246_EQ_246(...) \, +#define Z_IS_246U_EQ_246(...) \, +#define Z_IS_246_EQ_246U(...) \, +#define Z_IS_246U_EQ_246U(...) \, +#define Z_IS_247_EQ_247(...) \, +#define Z_IS_247U_EQ_247(...) \, +#define Z_IS_247_EQ_247U(...) \, +#define Z_IS_247U_EQ_247U(...) \, +#define Z_IS_248_EQ_248(...) \, +#define Z_IS_248U_EQ_248(...) \, +#define Z_IS_248_EQ_248U(...) \, +#define Z_IS_248U_EQ_248U(...) \, +#define Z_IS_249_EQ_249(...) \, +#define Z_IS_249U_EQ_249(...) \, +#define Z_IS_249_EQ_249U(...) \, +#define Z_IS_249U_EQ_249U(...) \, +#define Z_IS_250_EQ_250(...) \, +#define Z_IS_250U_EQ_250(...) \, +#define Z_IS_250_EQ_250U(...) \, +#define Z_IS_250U_EQ_250U(...) \, +#define Z_IS_251_EQ_251(...) \, +#define Z_IS_251U_EQ_251(...) \, +#define Z_IS_251_EQ_251U(...) \, +#define Z_IS_251U_EQ_251U(...) \, +#define Z_IS_252_EQ_252(...) \, +#define Z_IS_252U_EQ_252(...) \, +#define Z_IS_252_EQ_252U(...) \, +#define Z_IS_252U_EQ_252U(...) \, +#define Z_IS_253_EQ_253(...) \, +#define Z_IS_253U_EQ_253(...) \, +#define Z_IS_253_EQ_253U(...) \, +#define Z_IS_253U_EQ_253U(...) \, +#define Z_IS_254_EQ_254(...) \, +#define Z_IS_254U_EQ_254(...) \, +#define Z_IS_254_EQ_254U(...) \, +#define Z_IS_254U_EQ_254U(...) \, +#define Z_IS_255_EQ_255(...) \, +#define Z_IS_255U_EQ_255(...) \, +#define Z_IS_255_EQ_255U(...) \, +#define Z_IS_255U_EQ_255U(...) \, +#define Z_IS_256_EQ_256(...) \, +#define Z_IS_256U_EQ_256(...) \, +#define Z_IS_256_EQ_256U(...) \, +#define Z_IS_256U_EQ_256U(...) \, +#define Z_IS_257_EQ_257(...) \, +#define Z_IS_257U_EQ_257(...) \, +#define Z_IS_257_EQ_257U(...) \, +#define Z_IS_257U_EQ_257U(...) \, +#define Z_IS_258_EQ_258(...) \, +#define Z_IS_258U_EQ_258(...) \, +#define Z_IS_258_EQ_258U(...) \, +#define Z_IS_258U_EQ_258U(...) \, +#define Z_IS_259_EQ_259(...) \, +#define Z_IS_259U_EQ_259(...) \, +#define Z_IS_259_EQ_259U(...) \, +#define Z_IS_259U_EQ_259U(...) \, +#define Z_IS_260_EQ_260(...) \, +#define Z_IS_260U_EQ_260(...) \, +#define Z_IS_260_EQ_260U(...) \, +#define Z_IS_260U_EQ_260U(...) \, +#define Z_IS_261_EQ_261(...) \, +#define Z_IS_261U_EQ_261(...) \, +#define Z_IS_261_EQ_261U(...) \, +#define Z_IS_261U_EQ_261U(...) \, +#define Z_IS_262_EQ_262(...) \, +#define Z_IS_262U_EQ_262(...) \, +#define Z_IS_262_EQ_262U(...) \, +#define Z_IS_262U_EQ_262U(...) \, +#define Z_IS_263_EQ_263(...) \, +#define Z_IS_263U_EQ_263(...) \, +#define Z_IS_263_EQ_263U(...) \, +#define Z_IS_263U_EQ_263U(...) \, +#define Z_IS_264_EQ_264(...) \, +#define Z_IS_264U_EQ_264(...) \, +#define Z_IS_264_EQ_264U(...) \, +#define Z_IS_264U_EQ_264U(...) \, +#define Z_IS_265_EQ_265(...) \, +#define Z_IS_265U_EQ_265(...) \, +#define Z_IS_265_EQ_265U(...) \, +#define Z_IS_265U_EQ_265U(...) \, +#define Z_IS_266_EQ_266(...) \, +#define Z_IS_266U_EQ_266(...) \, +#define Z_IS_266_EQ_266U(...) \, +#define Z_IS_266U_EQ_266U(...) \, +#define Z_IS_267_EQ_267(...) \, +#define Z_IS_267U_EQ_267(...) \, +#define Z_IS_267_EQ_267U(...) \, +#define Z_IS_267U_EQ_267U(...) \, +#define Z_IS_268_EQ_268(...) \, +#define Z_IS_268U_EQ_268(...) \, +#define Z_IS_268_EQ_268U(...) \, +#define Z_IS_268U_EQ_268U(...) \, +#define Z_IS_269_EQ_269(...) \, +#define Z_IS_269U_EQ_269(...) \, +#define Z_IS_269_EQ_269U(...) \, +#define Z_IS_269U_EQ_269U(...) \, +#define Z_IS_270_EQ_270(...) \, +#define Z_IS_270U_EQ_270(...) \, +#define Z_IS_270_EQ_270U(...) \, +#define Z_IS_270U_EQ_270U(...) \, +#define Z_IS_271_EQ_271(...) \, +#define Z_IS_271U_EQ_271(...) \, +#define Z_IS_271_EQ_271U(...) \, +#define Z_IS_271U_EQ_271U(...) \, +#define Z_IS_272_EQ_272(...) \, +#define Z_IS_272U_EQ_272(...) \, +#define Z_IS_272_EQ_272U(...) \, +#define Z_IS_272U_EQ_272U(...) \, +#define Z_IS_273_EQ_273(...) \, +#define Z_IS_273U_EQ_273(...) \, +#define Z_IS_273_EQ_273U(...) \, +#define Z_IS_273U_EQ_273U(...) \, +#define Z_IS_274_EQ_274(...) \, +#define Z_IS_274U_EQ_274(...) \, +#define Z_IS_274_EQ_274U(...) \, +#define Z_IS_274U_EQ_274U(...) \, +#define Z_IS_275_EQ_275(...) \, +#define Z_IS_275U_EQ_275(...) \, +#define Z_IS_275_EQ_275U(...) \, +#define Z_IS_275U_EQ_275U(...) \, +#define Z_IS_276_EQ_276(...) \, +#define Z_IS_276U_EQ_276(...) \, +#define Z_IS_276_EQ_276U(...) \, +#define Z_IS_276U_EQ_276U(...) \, +#define Z_IS_277_EQ_277(...) \, +#define Z_IS_277U_EQ_277(...) \, +#define Z_IS_277_EQ_277U(...) \, +#define Z_IS_277U_EQ_277U(...) \, +#define Z_IS_278_EQ_278(...) \, +#define Z_IS_278U_EQ_278(...) \, +#define Z_IS_278_EQ_278U(...) \, +#define Z_IS_278U_EQ_278U(...) \, +#define Z_IS_279_EQ_279(...) \, +#define Z_IS_279U_EQ_279(...) \, +#define Z_IS_279_EQ_279U(...) \, +#define Z_IS_279U_EQ_279U(...) \, +#define Z_IS_280_EQ_280(...) \, +#define Z_IS_280U_EQ_280(...) \, +#define Z_IS_280_EQ_280U(...) \, +#define Z_IS_280U_EQ_280U(...) \, +#define Z_IS_281_EQ_281(...) \, +#define Z_IS_281U_EQ_281(...) \, +#define Z_IS_281_EQ_281U(...) \, +#define Z_IS_281U_EQ_281U(...) \, +#define Z_IS_282_EQ_282(...) \, +#define Z_IS_282U_EQ_282(...) \, +#define Z_IS_282_EQ_282U(...) \, +#define Z_IS_282U_EQ_282U(...) \, +#define Z_IS_283_EQ_283(...) \, +#define Z_IS_283U_EQ_283(...) \, +#define Z_IS_283_EQ_283U(...) \, +#define Z_IS_283U_EQ_283U(...) \, +#define Z_IS_284_EQ_284(...) \, +#define Z_IS_284U_EQ_284(...) \, +#define Z_IS_284_EQ_284U(...) \, +#define Z_IS_284U_EQ_284U(...) \, +#define Z_IS_285_EQ_285(...) \, +#define Z_IS_285U_EQ_285(...) \, +#define Z_IS_285_EQ_285U(...) \, +#define Z_IS_285U_EQ_285U(...) \, +#define Z_IS_286_EQ_286(...) \, +#define Z_IS_286U_EQ_286(...) \, +#define Z_IS_286_EQ_286U(...) \, +#define Z_IS_286U_EQ_286U(...) \, +#define Z_IS_287_EQ_287(...) \, +#define Z_IS_287U_EQ_287(...) \, +#define Z_IS_287_EQ_287U(...) \, +#define Z_IS_287U_EQ_287U(...) \, +#define Z_IS_288_EQ_288(...) \, +#define Z_IS_288U_EQ_288(...) \, +#define Z_IS_288_EQ_288U(...) \, +#define Z_IS_288U_EQ_288U(...) \, +#define Z_IS_289_EQ_289(...) \, +#define Z_IS_289U_EQ_289(...) \, +#define Z_IS_289_EQ_289U(...) \, +#define Z_IS_289U_EQ_289U(...) \, +#define Z_IS_290_EQ_290(...) \, +#define Z_IS_290U_EQ_290(...) \, +#define Z_IS_290_EQ_290U(...) \, +#define Z_IS_290U_EQ_290U(...) \, +#define Z_IS_291_EQ_291(...) \, +#define Z_IS_291U_EQ_291(...) \, +#define Z_IS_291_EQ_291U(...) \, +#define Z_IS_291U_EQ_291U(...) \, +#define Z_IS_292_EQ_292(...) \, +#define Z_IS_292U_EQ_292(...) \, +#define Z_IS_292_EQ_292U(...) \, +#define Z_IS_292U_EQ_292U(...) \, +#define Z_IS_293_EQ_293(...) \, +#define Z_IS_293U_EQ_293(...) \, +#define Z_IS_293_EQ_293U(...) \, +#define Z_IS_293U_EQ_293U(...) \, +#define Z_IS_294_EQ_294(...) \, +#define Z_IS_294U_EQ_294(...) \, +#define Z_IS_294_EQ_294U(...) \, +#define Z_IS_294U_EQ_294U(...) \, +#define Z_IS_295_EQ_295(...) \, +#define Z_IS_295U_EQ_295(...) \, +#define Z_IS_295_EQ_295U(...) \, +#define Z_IS_295U_EQ_295U(...) \, +#define Z_IS_296_EQ_296(...) \, +#define Z_IS_296U_EQ_296(...) \, +#define Z_IS_296_EQ_296U(...) \, +#define Z_IS_296U_EQ_296U(...) \, +#define Z_IS_297_EQ_297(...) \, +#define Z_IS_297U_EQ_297(...) \, +#define Z_IS_297_EQ_297U(...) \, +#define Z_IS_297U_EQ_297U(...) \, +#define Z_IS_298_EQ_298(...) \, +#define Z_IS_298U_EQ_298(...) \, +#define Z_IS_298_EQ_298U(...) \, +#define Z_IS_298U_EQ_298U(...) \, +#define Z_IS_299_EQ_299(...) \, +#define Z_IS_299U_EQ_299(...) \, +#define Z_IS_299_EQ_299U(...) \, +#define Z_IS_299U_EQ_299U(...) \, +#define Z_IS_300_EQ_300(...) \, +#define Z_IS_300U_EQ_300(...) \, +#define Z_IS_300_EQ_300U(...) \, +#define Z_IS_300U_EQ_300U(...) \, +#define Z_IS_301_EQ_301(...) \, +#define Z_IS_301U_EQ_301(...) \, +#define Z_IS_301_EQ_301U(...) \, +#define Z_IS_301U_EQ_301U(...) \, +#define Z_IS_302_EQ_302(...) \, +#define Z_IS_302U_EQ_302(...) \, +#define Z_IS_302_EQ_302U(...) \, +#define Z_IS_302U_EQ_302U(...) \, +#define Z_IS_303_EQ_303(...) \, +#define Z_IS_303U_EQ_303(...) \, +#define Z_IS_303_EQ_303U(...) \, +#define Z_IS_303U_EQ_303U(...) \, +#define Z_IS_304_EQ_304(...) \, +#define Z_IS_304U_EQ_304(...) \, +#define Z_IS_304_EQ_304U(...) \, +#define Z_IS_304U_EQ_304U(...) \, +#define Z_IS_305_EQ_305(...) \, +#define Z_IS_305U_EQ_305(...) \, +#define Z_IS_305_EQ_305U(...) \, +#define Z_IS_305U_EQ_305U(...) \, +#define Z_IS_306_EQ_306(...) \, +#define Z_IS_306U_EQ_306(...) \, +#define Z_IS_306_EQ_306U(...) \, +#define Z_IS_306U_EQ_306U(...) \, +#define Z_IS_307_EQ_307(...) \, +#define Z_IS_307U_EQ_307(...) \, +#define Z_IS_307_EQ_307U(...) \, +#define Z_IS_307U_EQ_307U(...) \, +#define Z_IS_308_EQ_308(...) \, +#define Z_IS_308U_EQ_308(...) \, +#define Z_IS_308_EQ_308U(...) \, +#define Z_IS_308U_EQ_308U(...) \, +#define Z_IS_309_EQ_309(...) \, +#define Z_IS_309U_EQ_309(...) \, +#define Z_IS_309_EQ_309U(...) \, +#define Z_IS_309U_EQ_309U(...) \, +#define Z_IS_310_EQ_310(...) \, +#define Z_IS_310U_EQ_310(...) \, +#define Z_IS_310_EQ_310U(...) \, +#define Z_IS_310U_EQ_310U(...) \, +#define Z_IS_311_EQ_311(...) \, +#define Z_IS_311U_EQ_311(...) \, +#define Z_IS_311_EQ_311U(...) \, +#define Z_IS_311U_EQ_311U(...) \, +#define Z_IS_312_EQ_312(...) \, +#define Z_IS_312U_EQ_312(...) \, +#define Z_IS_312_EQ_312U(...) \, +#define Z_IS_312U_EQ_312U(...) \, +#define Z_IS_313_EQ_313(...) \, +#define Z_IS_313U_EQ_313(...) \, +#define Z_IS_313_EQ_313U(...) \, +#define Z_IS_313U_EQ_313U(...) \, +#define Z_IS_314_EQ_314(...) \, +#define Z_IS_314U_EQ_314(...) \, +#define Z_IS_314_EQ_314U(...) \, +#define Z_IS_314U_EQ_314U(...) \, +#define Z_IS_315_EQ_315(...) \, +#define Z_IS_315U_EQ_315(...) \, +#define Z_IS_315_EQ_315U(...) \, +#define Z_IS_315U_EQ_315U(...) \, +#define Z_IS_316_EQ_316(...) \, +#define Z_IS_316U_EQ_316(...) \, +#define Z_IS_316_EQ_316U(...) \, +#define Z_IS_316U_EQ_316U(...) \, +#define Z_IS_317_EQ_317(...) \, +#define Z_IS_317U_EQ_317(...) \, +#define Z_IS_317_EQ_317U(...) \, +#define Z_IS_317U_EQ_317U(...) \, +#define Z_IS_318_EQ_318(...) \, +#define Z_IS_318U_EQ_318(...) \, +#define Z_IS_318_EQ_318U(...) \, +#define Z_IS_318U_EQ_318U(...) \, +#define Z_IS_319_EQ_319(...) \, +#define Z_IS_319U_EQ_319(...) \, +#define Z_IS_319_EQ_319U(...) \, +#define Z_IS_319U_EQ_319U(...) \, +#define Z_IS_320_EQ_320(...) \, +#define Z_IS_320U_EQ_320(...) \, +#define Z_IS_320_EQ_320U(...) \, +#define Z_IS_320U_EQ_320U(...) \, +#define Z_IS_321_EQ_321(...) \, +#define Z_IS_321U_EQ_321(...) \, +#define Z_IS_321_EQ_321U(...) \, +#define Z_IS_321U_EQ_321U(...) \, +#define Z_IS_322_EQ_322(...) \, +#define Z_IS_322U_EQ_322(...) \, +#define Z_IS_322_EQ_322U(...) \, +#define Z_IS_322U_EQ_322U(...) \, +#define Z_IS_323_EQ_323(...) \, +#define Z_IS_323U_EQ_323(...) \, +#define Z_IS_323_EQ_323U(...) \, +#define Z_IS_323U_EQ_323U(...) \, +#define Z_IS_324_EQ_324(...) \, +#define Z_IS_324U_EQ_324(...) \, +#define Z_IS_324_EQ_324U(...) \, +#define Z_IS_324U_EQ_324U(...) \, +#define Z_IS_325_EQ_325(...) \, +#define Z_IS_325U_EQ_325(...) \, +#define Z_IS_325_EQ_325U(...) \, +#define Z_IS_325U_EQ_325U(...) \, +#define Z_IS_326_EQ_326(...) \, +#define Z_IS_326U_EQ_326(...) \, +#define Z_IS_326_EQ_326U(...) \, +#define Z_IS_326U_EQ_326U(...) \, +#define Z_IS_327_EQ_327(...) \, +#define Z_IS_327U_EQ_327(...) \, +#define Z_IS_327_EQ_327U(...) \, +#define Z_IS_327U_EQ_327U(...) \, +#define Z_IS_328_EQ_328(...) \, +#define Z_IS_328U_EQ_328(...) \, +#define Z_IS_328_EQ_328U(...) \, +#define Z_IS_328U_EQ_328U(...) \, +#define Z_IS_329_EQ_329(...) \, +#define Z_IS_329U_EQ_329(...) \, +#define Z_IS_329_EQ_329U(...) \, +#define Z_IS_329U_EQ_329U(...) \, +#define Z_IS_330_EQ_330(...) \, +#define Z_IS_330U_EQ_330(...) \, +#define Z_IS_330_EQ_330U(...) \, +#define Z_IS_330U_EQ_330U(...) \, +#define Z_IS_331_EQ_331(...) \, +#define Z_IS_331U_EQ_331(...) \, +#define Z_IS_331_EQ_331U(...) \, +#define Z_IS_331U_EQ_331U(...) \, +#define Z_IS_332_EQ_332(...) \, +#define Z_IS_332U_EQ_332(...) \, +#define Z_IS_332_EQ_332U(...) \, +#define Z_IS_332U_EQ_332U(...) \, +#define Z_IS_333_EQ_333(...) \, +#define Z_IS_333U_EQ_333(...) \, +#define Z_IS_333_EQ_333U(...) \, +#define Z_IS_333U_EQ_333U(...) \, +#define Z_IS_334_EQ_334(...) \, +#define Z_IS_334U_EQ_334(...) \, +#define Z_IS_334_EQ_334U(...) \, +#define Z_IS_334U_EQ_334U(...) \, +#define Z_IS_335_EQ_335(...) \, +#define Z_IS_335U_EQ_335(...) \, +#define Z_IS_335_EQ_335U(...) \, +#define Z_IS_335U_EQ_335U(...) \, +#define Z_IS_336_EQ_336(...) \, +#define Z_IS_336U_EQ_336(...) \, +#define Z_IS_336_EQ_336U(...) \, +#define Z_IS_336U_EQ_336U(...) \, +#define Z_IS_337_EQ_337(...) \, +#define Z_IS_337U_EQ_337(...) \, +#define Z_IS_337_EQ_337U(...) \, +#define Z_IS_337U_EQ_337U(...) \, +#define Z_IS_338_EQ_338(...) \, +#define Z_IS_338U_EQ_338(...) \, +#define Z_IS_338_EQ_338U(...) \, +#define Z_IS_338U_EQ_338U(...) \, +#define Z_IS_339_EQ_339(...) \, +#define Z_IS_339U_EQ_339(...) \, +#define Z_IS_339_EQ_339U(...) \, +#define Z_IS_339U_EQ_339U(...) \, +#define Z_IS_340_EQ_340(...) \, +#define Z_IS_340U_EQ_340(...) \, +#define Z_IS_340_EQ_340U(...) \, +#define Z_IS_340U_EQ_340U(...) \, +#define Z_IS_341_EQ_341(...) \, +#define Z_IS_341U_EQ_341(...) \, +#define Z_IS_341_EQ_341U(...) \, +#define Z_IS_341U_EQ_341U(...) \, +#define Z_IS_342_EQ_342(...) \, +#define Z_IS_342U_EQ_342(...) \, +#define Z_IS_342_EQ_342U(...) \, +#define Z_IS_342U_EQ_342U(...) \, +#define Z_IS_343_EQ_343(...) \, +#define Z_IS_343U_EQ_343(...) \, +#define Z_IS_343_EQ_343U(...) \, +#define Z_IS_343U_EQ_343U(...) \, +#define Z_IS_344_EQ_344(...) \, +#define Z_IS_344U_EQ_344(...) \, +#define Z_IS_344_EQ_344U(...) \, +#define Z_IS_344U_EQ_344U(...) \, +#define Z_IS_345_EQ_345(...) \, +#define Z_IS_345U_EQ_345(...) \, +#define Z_IS_345_EQ_345U(...) \, +#define Z_IS_345U_EQ_345U(...) \, +#define Z_IS_346_EQ_346(...) \, +#define Z_IS_346U_EQ_346(...) \, +#define Z_IS_346_EQ_346U(...) \, +#define Z_IS_346U_EQ_346U(...) \, +#define Z_IS_347_EQ_347(...) \, +#define Z_IS_347U_EQ_347(...) \, +#define Z_IS_347_EQ_347U(...) \, +#define Z_IS_347U_EQ_347U(...) \, +#define Z_IS_348_EQ_348(...) \, +#define Z_IS_348U_EQ_348(...) \, +#define Z_IS_348_EQ_348U(...) \, +#define Z_IS_348U_EQ_348U(...) \, +#define Z_IS_349_EQ_349(...) \, +#define Z_IS_349U_EQ_349(...) \, +#define Z_IS_349_EQ_349U(...) \, +#define Z_IS_349U_EQ_349U(...) \, +#define Z_IS_350_EQ_350(...) \, +#define Z_IS_350U_EQ_350(...) \, +#define Z_IS_350_EQ_350U(...) \, +#define Z_IS_350U_EQ_350U(...) \, +#define Z_IS_351_EQ_351(...) \, +#define Z_IS_351U_EQ_351(...) \, +#define Z_IS_351_EQ_351U(...) \, +#define Z_IS_351U_EQ_351U(...) \, +#define Z_IS_352_EQ_352(...) \, +#define Z_IS_352U_EQ_352(...) \, +#define Z_IS_352_EQ_352U(...) \, +#define Z_IS_352U_EQ_352U(...) \, +#define Z_IS_353_EQ_353(...) \, +#define Z_IS_353U_EQ_353(...) \, +#define Z_IS_353_EQ_353U(...) \, +#define Z_IS_353U_EQ_353U(...) \, +#define Z_IS_354_EQ_354(...) \, +#define Z_IS_354U_EQ_354(...) \, +#define Z_IS_354_EQ_354U(...) \, +#define Z_IS_354U_EQ_354U(...) \, +#define Z_IS_355_EQ_355(...) \, +#define Z_IS_355U_EQ_355(...) \, +#define Z_IS_355_EQ_355U(...) \, +#define Z_IS_355U_EQ_355U(...) \, +#define Z_IS_356_EQ_356(...) \, +#define Z_IS_356U_EQ_356(...) \, +#define Z_IS_356_EQ_356U(...) \, +#define Z_IS_356U_EQ_356U(...) \, +#define Z_IS_357_EQ_357(...) \, +#define Z_IS_357U_EQ_357(...) \, +#define Z_IS_357_EQ_357U(...) \, +#define Z_IS_357U_EQ_357U(...) \, +#define Z_IS_358_EQ_358(...) \, +#define Z_IS_358U_EQ_358(...) \, +#define Z_IS_358_EQ_358U(...) \, +#define Z_IS_358U_EQ_358U(...) \, +#define Z_IS_359_EQ_359(...) \, +#define Z_IS_359U_EQ_359(...) \, +#define Z_IS_359_EQ_359U(...) \, +#define Z_IS_359U_EQ_359U(...) \, +#define Z_IS_360_EQ_360(...) \, +#define Z_IS_360U_EQ_360(...) \, +#define Z_IS_360_EQ_360U(...) \, +#define Z_IS_360U_EQ_360U(...) \, +#define Z_IS_361_EQ_361(...) \, +#define Z_IS_361U_EQ_361(...) \, +#define Z_IS_361_EQ_361U(...) \, +#define Z_IS_361U_EQ_361U(...) \, +#define Z_IS_362_EQ_362(...) \, +#define Z_IS_362U_EQ_362(...) \, +#define Z_IS_362_EQ_362U(...) \, +#define Z_IS_362U_EQ_362U(...) \, +#define Z_IS_363_EQ_363(...) \, +#define Z_IS_363U_EQ_363(...) \, +#define Z_IS_363_EQ_363U(...) \, +#define Z_IS_363U_EQ_363U(...) \, +#define Z_IS_364_EQ_364(...) \, +#define Z_IS_364U_EQ_364(...) \, +#define Z_IS_364_EQ_364U(...) \, +#define Z_IS_364U_EQ_364U(...) \, +#define Z_IS_365_EQ_365(...) \, +#define Z_IS_365U_EQ_365(...) \, +#define Z_IS_365_EQ_365U(...) \, +#define Z_IS_365U_EQ_365U(...) \, +#define Z_IS_366_EQ_366(...) \, +#define Z_IS_366U_EQ_366(...) \, +#define Z_IS_366_EQ_366U(...) \, +#define Z_IS_366U_EQ_366U(...) \, +#define Z_IS_367_EQ_367(...) \, +#define Z_IS_367U_EQ_367(...) \, +#define Z_IS_367_EQ_367U(...) \, +#define Z_IS_367U_EQ_367U(...) \, +#define Z_IS_368_EQ_368(...) \, +#define Z_IS_368U_EQ_368(...) \, +#define Z_IS_368_EQ_368U(...) \, +#define Z_IS_368U_EQ_368U(...) \, +#define Z_IS_369_EQ_369(...) \, +#define Z_IS_369U_EQ_369(...) \, +#define Z_IS_369_EQ_369U(...) \, +#define Z_IS_369U_EQ_369U(...) \, +#define Z_IS_370_EQ_370(...) \, +#define Z_IS_370U_EQ_370(...) \, +#define Z_IS_370_EQ_370U(...) \, +#define Z_IS_370U_EQ_370U(...) \, +#define Z_IS_371_EQ_371(...) \, +#define Z_IS_371U_EQ_371(...) \, +#define Z_IS_371_EQ_371U(...) \, +#define Z_IS_371U_EQ_371U(...) \, +#define Z_IS_372_EQ_372(...) \, +#define Z_IS_372U_EQ_372(...) \, +#define Z_IS_372_EQ_372U(...) \, +#define Z_IS_372U_EQ_372U(...) \, +#define Z_IS_373_EQ_373(...) \, +#define Z_IS_373U_EQ_373(...) \, +#define Z_IS_373_EQ_373U(...) \, +#define Z_IS_373U_EQ_373U(...) \, +#define Z_IS_374_EQ_374(...) \, +#define Z_IS_374U_EQ_374(...) \, +#define Z_IS_374_EQ_374U(...) \, +#define Z_IS_374U_EQ_374U(...) \, +#define Z_IS_375_EQ_375(...) \, +#define Z_IS_375U_EQ_375(...) \, +#define Z_IS_375_EQ_375U(...) \, +#define Z_IS_375U_EQ_375U(...) \, +#define Z_IS_376_EQ_376(...) \, +#define Z_IS_376U_EQ_376(...) \, +#define Z_IS_376_EQ_376U(...) \, +#define Z_IS_376U_EQ_376U(...) \, +#define Z_IS_377_EQ_377(...) \, +#define Z_IS_377U_EQ_377(...) \, +#define Z_IS_377_EQ_377U(...) \, +#define Z_IS_377U_EQ_377U(...) \, +#define Z_IS_378_EQ_378(...) \, +#define Z_IS_378U_EQ_378(...) \, +#define Z_IS_378_EQ_378U(...) \, +#define Z_IS_378U_EQ_378U(...) \, +#define Z_IS_379_EQ_379(...) \, +#define Z_IS_379U_EQ_379(...) \, +#define Z_IS_379_EQ_379U(...) \, +#define Z_IS_379U_EQ_379U(...) \, +#define Z_IS_380_EQ_380(...) \, +#define Z_IS_380U_EQ_380(...) \, +#define Z_IS_380_EQ_380U(...) \, +#define Z_IS_380U_EQ_380U(...) \, +#define Z_IS_381_EQ_381(...) \, +#define Z_IS_381U_EQ_381(...) \, +#define Z_IS_381_EQ_381U(...) \, +#define Z_IS_381U_EQ_381U(...) \, +#define Z_IS_382_EQ_382(...) \, +#define Z_IS_382U_EQ_382(...) \, +#define Z_IS_382_EQ_382U(...) \, +#define Z_IS_382U_EQ_382U(...) \, +#define Z_IS_383_EQ_383(...) \, +#define Z_IS_383U_EQ_383(...) \, +#define Z_IS_383_EQ_383U(...) \, +#define Z_IS_383U_EQ_383U(...) \, +#define Z_IS_384_EQ_384(...) \, +#define Z_IS_384U_EQ_384(...) \, +#define Z_IS_384_EQ_384U(...) \, +#define Z_IS_384U_EQ_384U(...) \, +#define Z_IS_385_EQ_385(...) \, +#define Z_IS_385U_EQ_385(...) \, +#define Z_IS_385_EQ_385U(...) \, +#define Z_IS_385U_EQ_385U(...) \, +#define Z_IS_386_EQ_386(...) \, +#define Z_IS_386U_EQ_386(...) \, +#define Z_IS_386_EQ_386U(...) \, +#define Z_IS_386U_EQ_386U(...) \, +#define Z_IS_387_EQ_387(...) \, +#define Z_IS_387U_EQ_387(...) \, +#define Z_IS_387_EQ_387U(...) \, +#define Z_IS_387U_EQ_387U(...) \, +#define Z_IS_388_EQ_388(...) \, +#define Z_IS_388U_EQ_388(...) \, +#define Z_IS_388_EQ_388U(...) \, +#define Z_IS_388U_EQ_388U(...) \, +#define Z_IS_389_EQ_389(...) \, +#define Z_IS_389U_EQ_389(...) \, +#define Z_IS_389_EQ_389U(...) \, +#define Z_IS_389U_EQ_389U(...) \, +#define Z_IS_390_EQ_390(...) \, +#define Z_IS_390U_EQ_390(...) \, +#define Z_IS_390_EQ_390U(...) \, +#define Z_IS_390U_EQ_390U(...) \, +#define Z_IS_391_EQ_391(...) \, +#define Z_IS_391U_EQ_391(...) \, +#define Z_IS_391_EQ_391U(...) \, +#define Z_IS_391U_EQ_391U(...) \, +#define Z_IS_392_EQ_392(...) \, +#define Z_IS_392U_EQ_392(...) \, +#define Z_IS_392_EQ_392U(...) \, +#define Z_IS_392U_EQ_392U(...) \, +#define Z_IS_393_EQ_393(...) \, +#define Z_IS_393U_EQ_393(...) \, +#define Z_IS_393_EQ_393U(...) \, +#define Z_IS_393U_EQ_393U(...) \, +#define Z_IS_394_EQ_394(...) \, +#define Z_IS_394U_EQ_394(...) \, +#define Z_IS_394_EQ_394U(...) \, +#define Z_IS_394U_EQ_394U(...) \, +#define Z_IS_395_EQ_395(...) \, +#define Z_IS_395U_EQ_395(...) \, +#define Z_IS_395_EQ_395U(...) \, +#define Z_IS_395U_EQ_395U(...) \, +#define Z_IS_396_EQ_396(...) \, +#define Z_IS_396U_EQ_396(...) \, +#define Z_IS_396_EQ_396U(...) \, +#define Z_IS_396U_EQ_396U(...) \, +#define Z_IS_397_EQ_397(...) \, +#define Z_IS_397U_EQ_397(...) \, +#define Z_IS_397_EQ_397U(...) \, +#define Z_IS_397U_EQ_397U(...) \, +#define Z_IS_398_EQ_398(...) \, +#define Z_IS_398U_EQ_398(...) \, +#define Z_IS_398_EQ_398U(...) \, +#define Z_IS_398U_EQ_398U(...) \, +#define Z_IS_399_EQ_399(...) \, +#define Z_IS_399U_EQ_399(...) \, +#define Z_IS_399_EQ_399U(...) \, +#define Z_IS_399U_EQ_399U(...) \, +#define Z_IS_400_EQ_400(...) \, +#define Z_IS_400U_EQ_400(...) \, +#define Z_IS_400_EQ_400U(...) \, +#define Z_IS_400U_EQ_400U(...) \, +#define Z_IS_401_EQ_401(...) \, +#define Z_IS_401U_EQ_401(...) \, +#define Z_IS_401_EQ_401U(...) \, +#define Z_IS_401U_EQ_401U(...) \, +#define Z_IS_402_EQ_402(...) \, +#define Z_IS_402U_EQ_402(...) \, +#define Z_IS_402_EQ_402U(...) \, +#define Z_IS_402U_EQ_402U(...) \, +#define Z_IS_403_EQ_403(...) \, +#define Z_IS_403U_EQ_403(...) \, +#define Z_IS_403_EQ_403U(...) \, +#define Z_IS_403U_EQ_403U(...) \, +#define Z_IS_404_EQ_404(...) \, +#define Z_IS_404U_EQ_404(...) \, +#define Z_IS_404_EQ_404U(...) \, +#define Z_IS_404U_EQ_404U(...) \, +#define Z_IS_405_EQ_405(...) \, +#define Z_IS_405U_EQ_405(...) \, +#define Z_IS_405_EQ_405U(...) \, +#define Z_IS_405U_EQ_405U(...) \, +#define Z_IS_406_EQ_406(...) \, +#define Z_IS_406U_EQ_406(...) \, +#define Z_IS_406_EQ_406U(...) \, +#define Z_IS_406U_EQ_406U(...) \, +#define Z_IS_407_EQ_407(...) \, +#define Z_IS_407U_EQ_407(...) \, +#define Z_IS_407_EQ_407U(...) \, +#define Z_IS_407U_EQ_407U(...) \, +#define Z_IS_408_EQ_408(...) \, +#define Z_IS_408U_EQ_408(...) \, +#define Z_IS_408_EQ_408U(...) \, +#define Z_IS_408U_EQ_408U(...) \, +#define Z_IS_409_EQ_409(...) \, +#define Z_IS_409U_EQ_409(...) \, +#define Z_IS_409_EQ_409U(...) \, +#define Z_IS_409U_EQ_409U(...) \, +#define Z_IS_410_EQ_410(...) \, +#define Z_IS_410U_EQ_410(...) \, +#define Z_IS_410_EQ_410U(...) \, +#define Z_IS_410U_EQ_410U(...) \, +#define Z_IS_411_EQ_411(...) \, +#define Z_IS_411U_EQ_411(...) \, +#define Z_IS_411_EQ_411U(...) \, +#define Z_IS_411U_EQ_411U(...) \, +#define Z_IS_412_EQ_412(...) \, +#define Z_IS_412U_EQ_412(...) \, +#define Z_IS_412_EQ_412U(...) \, +#define Z_IS_412U_EQ_412U(...) \, +#define Z_IS_413_EQ_413(...) \, +#define Z_IS_413U_EQ_413(...) \, +#define Z_IS_413_EQ_413U(...) \, +#define Z_IS_413U_EQ_413U(...) \, +#define Z_IS_414_EQ_414(...) \, +#define Z_IS_414U_EQ_414(...) \, +#define Z_IS_414_EQ_414U(...) \, +#define Z_IS_414U_EQ_414U(...) \, +#define Z_IS_415_EQ_415(...) \, +#define Z_IS_415U_EQ_415(...) \, +#define Z_IS_415_EQ_415U(...) \, +#define Z_IS_415U_EQ_415U(...) \, +#define Z_IS_416_EQ_416(...) \, +#define Z_IS_416U_EQ_416(...) \, +#define Z_IS_416_EQ_416U(...) \, +#define Z_IS_416U_EQ_416U(...) \, +#define Z_IS_417_EQ_417(...) \, +#define Z_IS_417U_EQ_417(...) \, +#define Z_IS_417_EQ_417U(...) \, +#define Z_IS_417U_EQ_417U(...) \, +#define Z_IS_418_EQ_418(...) \, +#define Z_IS_418U_EQ_418(...) \, +#define Z_IS_418_EQ_418U(...) \, +#define Z_IS_418U_EQ_418U(...) \, +#define Z_IS_419_EQ_419(...) \, +#define Z_IS_419U_EQ_419(...) \, +#define Z_IS_419_EQ_419U(...) \, +#define Z_IS_419U_EQ_419U(...) \, +#define Z_IS_420_EQ_420(...) \, +#define Z_IS_420U_EQ_420(...) \, +#define Z_IS_420_EQ_420U(...) \, +#define Z_IS_420U_EQ_420U(...) \, +#define Z_IS_421_EQ_421(...) \, +#define Z_IS_421U_EQ_421(...) \, +#define Z_IS_421_EQ_421U(...) \, +#define Z_IS_421U_EQ_421U(...) \, +#define Z_IS_422_EQ_422(...) \, +#define Z_IS_422U_EQ_422(...) \, +#define Z_IS_422_EQ_422U(...) \, +#define Z_IS_422U_EQ_422U(...) \, +#define Z_IS_423_EQ_423(...) \, +#define Z_IS_423U_EQ_423(...) \, +#define Z_IS_423_EQ_423U(...) \, +#define Z_IS_423U_EQ_423U(...) \, +#define Z_IS_424_EQ_424(...) \, +#define Z_IS_424U_EQ_424(...) \, +#define Z_IS_424_EQ_424U(...) \, +#define Z_IS_424U_EQ_424U(...) \, +#define Z_IS_425_EQ_425(...) \, +#define Z_IS_425U_EQ_425(...) \, +#define Z_IS_425_EQ_425U(...) \, +#define Z_IS_425U_EQ_425U(...) \, +#define Z_IS_426_EQ_426(...) \, +#define Z_IS_426U_EQ_426(...) \, +#define Z_IS_426_EQ_426U(...) \, +#define Z_IS_426U_EQ_426U(...) \, +#define Z_IS_427_EQ_427(...) \, +#define Z_IS_427U_EQ_427(...) \, +#define Z_IS_427_EQ_427U(...) \, +#define Z_IS_427U_EQ_427U(...) \, +#define Z_IS_428_EQ_428(...) \, +#define Z_IS_428U_EQ_428(...) \, +#define Z_IS_428_EQ_428U(...) \, +#define Z_IS_428U_EQ_428U(...) \, +#define Z_IS_429_EQ_429(...) \, +#define Z_IS_429U_EQ_429(...) \, +#define Z_IS_429_EQ_429U(...) \, +#define Z_IS_429U_EQ_429U(...) \, +#define Z_IS_430_EQ_430(...) \, +#define Z_IS_430U_EQ_430(...) \, +#define Z_IS_430_EQ_430U(...) \, +#define Z_IS_430U_EQ_430U(...) \, +#define Z_IS_431_EQ_431(...) \, +#define Z_IS_431U_EQ_431(...) \, +#define Z_IS_431_EQ_431U(...) \, +#define Z_IS_431U_EQ_431U(...) \, +#define Z_IS_432_EQ_432(...) \, +#define Z_IS_432U_EQ_432(...) \, +#define Z_IS_432_EQ_432U(...) \, +#define Z_IS_432U_EQ_432U(...) \, +#define Z_IS_433_EQ_433(...) \, +#define Z_IS_433U_EQ_433(...) \, +#define Z_IS_433_EQ_433U(...) \, +#define Z_IS_433U_EQ_433U(...) \, +#define Z_IS_434_EQ_434(...) \, +#define Z_IS_434U_EQ_434(...) \, +#define Z_IS_434_EQ_434U(...) \, +#define Z_IS_434U_EQ_434U(...) \, +#define Z_IS_435_EQ_435(...) \, +#define Z_IS_435U_EQ_435(...) \, +#define Z_IS_435_EQ_435U(...) \, +#define Z_IS_435U_EQ_435U(...) \, +#define Z_IS_436_EQ_436(...) \, +#define Z_IS_436U_EQ_436(...) \, +#define Z_IS_436_EQ_436U(...) \, +#define Z_IS_436U_EQ_436U(...) \, +#define Z_IS_437_EQ_437(...) \, +#define Z_IS_437U_EQ_437(...) \, +#define Z_IS_437_EQ_437U(...) \, +#define Z_IS_437U_EQ_437U(...) \, +#define Z_IS_438_EQ_438(...) \, +#define Z_IS_438U_EQ_438(...) \, +#define Z_IS_438_EQ_438U(...) \, +#define Z_IS_438U_EQ_438U(...) \, +#define Z_IS_439_EQ_439(...) \, +#define Z_IS_439U_EQ_439(...) \, +#define Z_IS_439_EQ_439U(...) \, +#define Z_IS_439U_EQ_439U(...) \, +#define Z_IS_440_EQ_440(...) \, +#define Z_IS_440U_EQ_440(...) \, +#define Z_IS_440_EQ_440U(...) \, +#define Z_IS_440U_EQ_440U(...) \, +#define Z_IS_441_EQ_441(...) \, +#define Z_IS_441U_EQ_441(...) \, +#define Z_IS_441_EQ_441U(...) \, +#define Z_IS_441U_EQ_441U(...) \, +#define Z_IS_442_EQ_442(...) \, +#define Z_IS_442U_EQ_442(...) \, +#define Z_IS_442_EQ_442U(...) \, +#define Z_IS_442U_EQ_442U(...) \, +#define Z_IS_443_EQ_443(...) \, +#define Z_IS_443U_EQ_443(...) \, +#define Z_IS_443_EQ_443U(...) \, +#define Z_IS_443U_EQ_443U(...) \, +#define Z_IS_444_EQ_444(...) \, +#define Z_IS_444U_EQ_444(...) \, +#define Z_IS_444_EQ_444U(...) \, +#define Z_IS_444U_EQ_444U(...) \, +#define Z_IS_445_EQ_445(...) \, +#define Z_IS_445U_EQ_445(...) \, +#define Z_IS_445_EQ_445U(...) \, +#define Z_IS_445U_EQ_445U(...) \, +#define Z_IS_446_EQ_446(...) \, +#define Z_IS_446U_EQ_446(...) \, +#define Z_IS_446_EQ_446U(...) \, +#define Z_IS_446U_EQ_446U(...) \, +#define Z_IS_447_EQ_447(...) \, +#define Z_IS_447U_EQ_447(...) \, +#define Z_IS_447_EQ_447U(...) \, +#define Z_IS_447U_EQ_447U(...) \, +#define Z_IS_448_EQ_448(...) \, +#define Z_IS_448U_EQ_448(...) \, +#define Z_IS_448_EQ_448U(...) \, +#define Z_IS_448U_EQ_448U(...) \, +#define Z_IS_449_EQ_449(...) \, +#define Z_IS_449U_EQ_449(...) \, +#define Z_IS_449_EQ_449U(...) \, +#define Z_IS_449U_EQ_449U(...) \, +#define Z_IS_450_EQ_450(...) \, +#define Z_IS_450U_EQ_450(...) \, +#define Z_IS_450_EQ_450U(...) \, +#define Z_IS_450U_EQ_450U(...) \, +#define Z_IS_451_EQ_451(...) \, +#define Z_IS_451U_EQ_451(...) \, +#define Z_IS_451_EQ_451U(...) \, +#define Z_IS_451U_EQ_451U(...) \, +#define Z_IS_452_EQ_452(...) \, +#define Z_IS_452U_EQ_452(...) \, +#define Z_IS_452_EQ_452U(...) \, +#define Z_IS_452U_EQ_452U(...) \, +#define Z_IS_453_EQ_453(...) \, +#define Z_IS_453U_EQ_453(...) \, +#define Z_IS_453_EQ_453U(...) \, +#define Z_IS_453U_EQ_453U(...) \, +#define Z_IS_454_EQ_454(...) \, +#define Z_IS_454U_EQ_454(...) \, +#define Z_IS_454_EQ_454U(...) \, +#define Z_IS_454U_EQ_454U(...) \, +#define Z_IS_455_EQ_455(...) \, +#define Z_IS_455U_EQ_455(...) \, +#define Z_IS_455_EQ_455U(...) \, +#define Z_IS_455U_EQ_455U(...) \, +#define Z_IS_456_EQ_456(...) \, +#define Z_IS_456U_EQ_456(...) \, +#define Z_IS_456_EQ_456U(...) \, +#define Z_IS_456U_EQ_456U(...) \, +#define Z_IS_457_EQ_457(...) \, +#define Z_IS_457U_EQ_457(...) \, +#define Z_IS_457_EQ_457U(...) \, +#define Z_IS_457U_EQ_457U(...) \, +#define Z_IS_458_EQ_458(...) \, +#define Z_IS_458U_EQ_458(...) \, +#define Z_IS_458_EQ_458U(...) \, +#define Z_IS_458U_EQ_458U(...) \, +#define Z_IS_459_EQ_459(...) \, +#define Z_IS_459U_EQ_459(...) \, +#define Z_IS_459_EQ_459U(...) \, +#define Z_IS_459U_EQ_459U(...) \, +#define Z_IS_460_EQ_460(...) \, +#define Z_IS_460U_EQ_460(...) \, +#define Z_IS_460_EQ_460U(...) \, +#define Z_IS_460U_EQ_460U(...) \, +#define Z_IS_461_EQ_461(...) \, +#define Z_IS_461U_EQ_461(...) \, +#define Z_IS_461_EQ_461U(...) \, +#define Z_IS_461U_EQ_461U(...) \, +#define Z_IS_462_EQ_462(...) \, +#define Z_IS_462U_EQ_462(...) \, +#define Z_IS_462_EQ_462U(...) \, +#define Z_IS_462U_EQ_462U(...) \, +#define Z_IS_463_EQ_463(...) \, +#define Z_IS_463U_EQ_463(...) \, +#define Z_IS_463_EQ_463U(...) \, +#define Z_IS_463U_EQ_463U(...) \, +#define Z_IS_464_EQ_464(...) \, +#define Z_IS_464U_EQ_464(...) \, +#define Z_IS_464_EQ_464U(...) \, +#define Z_IS_464U_EQ_464U(...) \, +#define Z_IS_465_EQ_465(...) \, +#define Z_IS_465U_EQ_465(...) \, +#define Z_IS_465_EQ_465U(...) \, +#define Z_IS_465U_EQ_465U(...) \, +#define Z_IS_466_EQ_466(...) \, +#define Z_IS_466U_EQ_466(...) \, +#define Z_IS_466_EQ_466U(...) \, +#define Z_IS_466U_EQ_466U(...) \, +#define Z_IS_467_EQ_467(...) \, +#define Z_IS_467U_EQ_467(...) \, +#define Z_IS_467_EQ_467U(...) \, +#define Z_IS_467U_EQ_467U(...) \, +#define Z_IS_468_EQ_468(...) \, +#define Z_IS_468U_EQ_468(...) \, +#define Z_IS_468_EQ_468U(...) \, +#define Z_IS_468U_EQ_468U(...) \, +#define Z_IS_469_EQ_469(...) \, +#define Z_IS_469U_EQ_469(...) \, +#define Z_IS_469_EQ_469U(...) \, +#define Z_IS_469U_EQ_469U(...) \, +#define Z_IS_470_EQ_470(...) \, +#define Z_IS_470U_EQ_470(...) \, +#define Z_IS_470_EQ_470U(...) \, +#define Z_IS_470U_EQ_470U(...) \, +#define Z_IS_471_EQ_471(...) \, +#define Z_IS_471U_EQ_471(...) \, +#define Z_IS_471_EQ_471U(...) \, +#define Z_IS_471U_EQ_471U(...) \, +#define Z_IS_472_EQ_472(...) \, +#define Z_IS_472U_EQ_472(...) \, +#define Z_IS_472_EQ_472U(...) \, +#define Z_IS_472U_EQ_472U(...) \, +#define Z_IS_473_EQ_473(...) \, +#define Z_IS_473U_EQ_473(...) \, +#define Z_IS_473_EQ_473U(...) \, +#define Z_IS_473U_EQ_473U(...) \, +#define Z_IS_474_EQ_474(...) \, +#define Z_IS_474U_EQ_474(...) \, +#define Z_IS_474_EQ_474U(...) \, +#define Z_IS_474U_EQ_474U(...) \, +#define Z_IS_475_EQ_475(...) \, +#define Z_IS_475U_EQ_475(...) \, +#define Z_IS_475_EQ_475U(...) \, +#define Z_IS_475U_EQ_475U(...) \, +#define Z_IS_476_EQ_476(...) \, +#define Z_IS_476U_EQ_476(...) \, +#define Z_IS_476_EQ_476U(...) \, +#define Z_IS_476U_EQ_476U(...) \, +#define Z_IS_477_EQ_477(...) \, +#define Z_IS_477U_EQ_477(...) \, +#define Z_IS_477_EQ_477U(...) \, +#define Z_IS_477U_EQ_477U(...) \, +#define Z_IS_478_EQ_478(...) \, +#define Z_IS_478U_EQ_478(...) \, +#define Z_IS_478_EQ_478U(...) \, +#define Z_IS_478U_EQ_478U(...) \, +#define Z_IS_479_EQ_479(...) \, +#define Z_IS_479U_EQ_479(...) \, +#define Z_IS_479_EQ_479U(...) \, +#define Z_IS_479U_EQ_479U(...) \, +#define Z_IS_480_EQ_480(...) \, +#define Z_IS_480U_EQ_480(...) \, +#define Z_IS_480_EQ_480U(...) \, +#define Z_IS_480U_EQ_480U(...) \, +#define Z_IS_481_EQ_481(...) \, +#define Z_IS_481U_EQ_481(...) \, +#define Z_IS_481_EQ_481U(...) \, +#define Z_IS_481U_EQ_481U(...) \, +#define Z_IS_482_EQ_482(...) \, +#define Z_IS_482U_EQ_482(...) \, +#define Z_IS_482_EQ_482U(...) \, +#define Z_IS_482U_EQ_482U(...) \, +#define Z_IS_483_EQ_483(...) \, +#define Z_IS_483U_EQ_483(...) \, +#define Z_IS_483_EQ_483U(...) \, +#define Z_IS_483U_EQ_483U(...) \, +#define Z_IS_484_EQ_484(...) \, +#define Z_IS_484U_EQ_484(...) \, +#define Z_IS_484_EQ_484U(...) \, +#define Z_IS_484U_EQ_484U(...) \, +#define Z_IS_485_EQ_485(...) \, +#define Z_IS_485U_EQ_485(...) \, +#define Z_IS_485_EQ_485U(...) \, +#define Z_IS_485U_EQ_485U(...) \, +#define Z_IS_486_EQ_486(...) \, +#define Z_IS_486U_EQ_486(...) \, +#define Z_IS_486_EQ_486U(...) \, +#define Z_IS_486U_EQ_486U(...) \, +#define Z_IS_487_EQ_487(...) \, +#define Z_IS_487U_EQ_487(...) \, +#define Z_IS_487_EQ_487U(...) \, +#define Z_IS_487U_EQ_487U(...) \, +#define Z_IS_488_EQ_488(...) \, +#define Z_IS_488U_EQ_488(...) \, +#define Z_IS_488_EQ_488U(...) \, +#define Z_IS_488U_EQ_488U(...) \, +#define Z_IS_489_EQ_489(...) \, +#define Z_IS_489U_EQ_489(...) \, +#define Z_IS_489_EQ_489U(...) \, +#define Z_IS_489U_EQ_489U(...) \, +#define Z_IS_490_EQ_490(...) \, +#define Z_IS_490U_EQ_490(...) \, +#define Z_IS_490_EQ_490U(...) \, +#define Z_IS_490U_EQ_490U(...) \, +#define Z_IS_491_EQ_491(...) \, +#define Z_IS_491U_EQ_491(...) \, +#define Z_IS_491_EQ_491U(...) \, +#define Z_IS_491U_EQ_491U(...) \, +#define Z_IS_492_EQ_492(...) \, +#define Z_IS_492U_EQ_492(...) \, +#define Z_IS_492_EQ_492U(...) \, +#define Z_IS_492U_EQ_492U(...) \, +#define Z_IS_493_EQ_493(...) \, +#define Z_IS_493U_EQ_493(...) \, +#define Z_IS_493_EQ_493U(...) \, +#define Z_IS_493U_EQ_493U(...) \, +#define Z_IS_494_EQ_494(...) \, +#define Z_IS_494U_EQ_494(...) \, +#define Z_IS_494_EQ_494U(...) \, +#define Z_IS_494U_EQ_494U(...) \, +#define Z_IS_495_EQ_495(...) \, +#define Z_IS_495U_EQ_495(...) \, +#define Z_IS_495_EQ_495U(...) \, +#define Z_IS_495U_EQ_495U(...) \, +#define Z_IS_496_EQ_496(...) \, +#define Z_IS_496U_EQ_496(...) \, +#define Z_IS_496_EQ_496U(...) \, +#define Z_IS_496U_EQ_496U(...) \, +#define Z_IS_497_EQ_497(...) \, +#define Z_IS_497U_EQ_497(...) \, +#define Z_IS_497_EQ_497U(...) \, +#define Z_IS_497U_EQ_497U(...) \, +#define Z_IS_498_EQ_498(...) \, +#define Z_IS_498U_EQ_498(...) \, +#define Z_IS_498_EQ_498U(...) \, +#define Z_IS_498U_EQ_498U(...) \, +#define Z_IS_499_EQ_499(...) \, +#define Z_IS_499U_EQ_499(...) \, +#define Z_IS_499_EQ_499U(...) \, +#define Z_IS_499U_EQ_499U(...) \, +#define Z_IS_500_EQ_500(...) \, +#define Z_IS_500U_EQ_500(...) \, +#define Z_IS_500_EQ_500U(...) \, +#define Z_IS_500U_EQ_500U(...) \, +#define Z_IS_501_EQ_501(...) \, +#define Z_IS_501U_EQ_501(...) \, +#define Z_IS_501_EQ_501U(...) \, +#define Z_IS_501U_EQ_501U(...) \, +#define Z_IS_502_EQ_502(...) \, +#define Z_IS_502U_EQ_502(...) \, +#define Z_IS_502_EQ_502U(...) \, +#define Z_IS_502U_EQ_502U(...) \, +#define Z_IS_503_EQ_503(...) \, +#define Z_IS_503U_EQ_503(...) \, +#define Z_IS_503_EQ_503U(...) \, +#define Z_IS_503U_EQ_503U(...) \, +#define Z_IS_504_EQ_504(...) \, +#define Z_IS_504U_EQ_504(...) \, +#define Z_IS_504_EQ_504U(...) \, +#define Z_IS_504U_EQ_504U(...) \, +#define Z_IS_505_EQ_505(...) \, +#define Z_IS_505U_EQ_505(...) \, +#define Z_IS_505_EQ_505U(...) \, +#define Z_IS_505U_EQ_505U(...) \, +#define Z_IS_506_EQ_506(...) \, +#define Z_IS_506U_EQ_506(...) \, +#define Z_IS_506_EQ_506U(...) \, +#define Z_IS_506U_EQ_506U(...) \, +#define Z_IS_507_EQ_507(...) \, +#define Z_IS_507U_EQ_507(...) \, +#define Z_IS_507_EQ_507U(...) \, +#define Z_IS_507U_EQ_507U(...) \, +#define Z_IS_508_EQ_508(...) \, +#define Z_IS_508U_EQ_508(...) \, +#define Z_IS_508_EQ_508U(...) \, +#define Z_IS_508U_EQ_508U(...) \, +#define Z_IS_509_EQ_509(...) \, +#define Z_IS_509U_EQ_509(...) \, +#define Z_IS_509_EQ_509U(...) \, +#define Z_IS_509U_EQ_509U(...) \, +#define Z_IS_510_EQ_510(...) \, +#define Z_IS_510U_EQ_510(...) \, +#define Z_IS_510_EQ_510U(...) \, +#define Z_IS_510U_EQ_510U(...) \, +#define Z_IS_511_EQ_511(...) \, +#define Z_IS_511U_EQ_511(...) \, +#define Z_IS_511_EQ_511U(...) \, +#define Z_IS_511U_EQ_511U(...) \, +#define Z_IS_512_EQ_512(...) \, +#define Z_IS_512U_EQ_512(...) \, +#define Z_IS_512_EQ_512U(...) \, +#define Z_IS_512U_EQ_512U(...) \, +#define Z_IS_513_EQ_513(...) \, +#define Z_IS_513U_EQ_513(...) \, +#define Z_IS_513_EQ_513U(...) \, +#define Z_IS_513U_EQ_513U(...) \, +#define Z_IS_514_EQ_514(...) \, +#define Z_IS_514U_EQ_514(...) \, +#define Z_IS_514_EQ_514U(...) \, +#define Z_IS_514U_EQ_514U(...) \, +#define Z_IS_515_EQ_515(...) \, +#define Z_IS_515U_EQ_515(...) \, +#define Z_IS_515_EQ_515U(...) \, +#define Z_IS_515U_EQ_515U(...) \, +#define Z_IS_516_EQ_516(...) \, +#define Z_IS_516U_EQ_516(...) \, +#define Z_IS_516_EQ_516U(...) \, +#define Z_IS_516U_EQ_516U(...) \, +#define Z_IS_517_EQ_517(...) \, +#define Z_IS_517U_EQ_517(...) \, +#define Z_IS_517_EQ_517U(...) \, +#define Z_IS_517U_EQ_517U(...) \, +#define Z_IS_518_EQ_518(...) \, +#define Z_IS_518U_EQ_518(...) \, +#define Z_IS_518_EQ_518U(...) \, +#define Z_IS_518U_EQ_518U(...) \, +#define Z_IS_519_EQ_519(...) \, +#define Z_IS_519U_EQ_519(...) \, +#define Z_IS_519_EQ_519U(...) \, +#define Z_IS_519U_EQ_519U(...) \, +#define Z_IS_520_EQ_520(...) \, +#define Z_IS_520U_EQ_520(...) \, +#define Z_IS_520_EQ_520U(...) \, +#define Z_IS_520U_EQ_520U(...) \, +#define Z_IS_521_EQ_521(...) \, +#define Z_IS_521U_EQ_521(...) \, +#define Z_IS_521_EQ_521U(...) \, +#define Z_IS_521U_EQ_521U(...) \, +#define Z_IS_522_EQ_522(...) \, +#define Z_IS_522U_EQ_522(...) \, +#define Z_IS_522_EQ_522U(...) \, +#define Z_IS_522U_EQ_522U(...) \, +#define Z_IS_523_EQ_523(...) \, +#define Z_IS_523U_EQ_523(...) \, +#define Z_IS_523_EQ_523U(...) \, +#define Z_IS_523U_EQ_523U(...) \, +#define Z_IS_524_EQ_524(...) \, +#define Z_IS_524U_EQ_524(...) \, +#define Z_IS_524_EQ_524U(...) \, +#define Z_IS_524U_EQ_524U(...) \, +#define Z_IS_525_EQ_525(...) \, +#define Z_IS_525U_EQ_525(...) \, +#define Z_IS_525_EQ_525U(...) \, +#define Z_IS_525U_EQ_525U(...) \, +#define Z_IS_526_EQ_526(...) \, +#define Z_IS_526U_EQ_526(...) \, +#define Z_IS_526_EQ_526U(...) \, +#define Z_IS_526U_EQ_526U(...) \, +#define Z_IS_527_EQ_527(...) \, +#define Z_IS_527U_EQ_527(...) \, +#define Z_IS_527_EQ_527U(...) \, +#define Z_IS_527U_EQ_527U(...) \, +#define Z_IS_528_EQ_528(...) \, +#define Z_IS_528U_EQ_528(...) \, +#define Z_IS_528_EQ_528U(...) \, +#define Z_IS_528U_EQ_528U(...) \, +#define Z_IS_529_EQ_529(...) \, +#define Z_IS_529U_EQ_529(...) \, +#define Z_IS_529_EQ_529U(...) \, +#define Z_IS_529U_EQ_529U(...) \, +#define Z_IS_530_EQ_530(...) \, +#define Z_IS_530U_EQ_530(...) \, +#define Z_IS_530_EQ_530U(...) \, +#define Z_IS_530U_EQ_530U(...) \, +#define Z_IS_531_EQ_531(...) \, +#define Z_IS_531U_EQ_531(...) \, +#define Z_IS_531_EQ_531U(...) \, +#define Z_IS_531U_EQ_531U(...) \, +#define Z_IS_532_EQ_532(...) \, +#define Z_IS_532U_EQ_532(...) \, +#define Z_IS_532_EQ_532U(...) \, +#define Z_IS_532U_EQ_532U(...) \, +#define Z_IS_533_EQ_533(...) \, +#define Z_IS_533U_EQ_533(...) \, +#define Z_IS_533_EQ_533U(...) \, +#define Z_IS_533U_EQ_533U(...) \, +#define Z_IS_534_EQ_534(...) \, +#define Z_IS_534U_EQ_534(...) \, +#define Z_IS_534_EQ_534U(...) \, +#define Z_IS_534U_EQ_534U(...) \, +#define Z_IS_535_EQ_535(...) \, +#define Z_IS_535U_EQ_535(...) \, +#define Z_IS_535_EQ_535U(...) \, +#define Z_IS_535U_EQ_535U(...) \, +#define Z_IS_536_EQ_536(...) \, +#define Z_IS_536U_EQ_536(...) \, +#define Z_IS_536_EQ_536U(...) \, +#define Z_IS_536U_EQ_536U(...) \, +#define Z_IS_537_EQ_537(...) \, +#define Z_IS_537U_EQ_537(...) \, +#define Z_IS_537_EQ_537U(...) \, +#define Z_IS_537U_EQ_537U(...) \, +#define Z_IS_538_EQ_538(...) \, +#define Z_IS_538U_EQ_538(...) \, +#define Z_IS_538_EQ_538U(...) \, +#define Z_IS_538U_EQ_538U(...) \, +#define Z_IS_539_EQ_539(...) \, +#define Z_IS_539U_EQ_539(...) \, +#define Z_IS_539_EQ_539U(...) \, +#define Z_IS_539U_EQ_539U(...) \, +#define Z_IS_540_EQ_540(...) \, +#define Z_IS_540U_EQ_540(...) \, +#define Z_IS_540_EQ_540U(...) \, +#define Z_IS_540U_EQ_540U(...) \, +#define Z_IS_541_EQ_541(...) \, +#define Z_IS_541U_EQ_541(...) \, +#define Z_IS_541_EQ_541U(...) \, +#define Z_IS_541U_EQ_541U(...) \, +#define Z_IS_542_EQ_542(...) \, +#define Z_IS_542U_EQ_542(...) \, +#define Z_IS_542_EQ_542U(...) \, +#define Z_IS_542U_EQ_542U(...) \, +#define Z_IS_543_EQ_543(...) \, +#define Z_IS_543U_EQ_543(...) \, +#define Z_IS_543_EQ_543U(...) \, +#define Z_IS_543U_EQ_543U(...) \, +#define Z_IS_544_EQ_544(...) \, +#define Z_IS_544U_EQ_544(...) \, +#define Z_IS_544_EQ_544U(...) \, +#define Z_IS_544U_EQ_544U(...) \, +#define Z_IS_545_EQ_545(...) \, +#define Z_IS_545U_EQ_545(...) \, +#define Z_IS_545_EQ_545U(...) \, +#define Z_IS_545U_EQ_545U(...) \, +#define Z_IS_546_EQ_546(...) \, +#define Z_IS_546U_EQ_546(...) \, +#define Z_IS_546_EQ_546U(...) \, +#define Z_IS_546U_EQ_546U(...) \, +#define Z_IS_547_EQ_547(...) \, +#define Z_IS_547U_EQ_547(...) \, +#define Z_IS_547_EQ_547U(...) \, +#define Z_IS_547U_EQ_547U(...) \, +#define Z_IS_548_EQ_548(...) \, +#define Z_IS_548U_EQ_548(...) \, +#define Z_IS_548_EQ_548U(...) \, +#define Z_IS_548U_EQ_548U(...) \, +#define Z_IS_549_EQ_549(...) \, +#define Z_IS_549U_EQ_549(...) \, +#define Z_IS_549_EQ_549U(...) \, +#define Z_IS_549U_EQ_549U(...) \, +#define Z_IS_550_EQ_550(...) \, +#define Z_IS_550U_EQ_550(...) \, +#define Z_IS_550_EQ_550U(...) \, +#define Z_IS_550U_EQ_550U(...) \, +#define Z_IS_551_EQ_551(...) \, +#define Z_IS_551U_EQ_551(...) \, +#define Z_IS_551_EQ_551U(...) \, +#define Z_IS_551U_EQ_551U(...) \, +#define Z_IS_552_EQ_552(...) \, +#define Z_IS_552U_EQ_552(...) \, +#define Z_IS_552_EQ_552U(...) \, +#define Z_IS_552U_EQ_552U(...) \, +#define Z_IS_553_EQ_553(...) \, +#define Z_IS_553U_EQ_553(...) \, +#define Z_IS_553_EQ_553U(...) \, +#define Z_IS_553U_EQ_553U(...) \, +#define Z_IS_554_EQ_554(...) \, +#define Z_IS_554U_EQ_554(...) \, +#define Z_IS_554_EQ_554U(...) \, +#define Z_IS_554U_EQ_554U(...) \, +#define Z_IS_555_EQ_555(...) \, +#define Z_IS_555U_EQ_555(...) \, +#define Z_IS_555_EQ_555U(...) \, +#define Z_IS_555U_EQ_555U(...) \, +#define Z_IS_556_EQ_556(...) \, +#define Z_IS_556U_EQ_556(...) \, +#define Z_IS_556_EQ_556U(...) \, +#define Z_IS_556U_EQ_556U(...) \, +#define Z_IS_557_EQ_557(...) \, +#define Z_IS_557U_EQ_557(...) \, +#define Z_IS_557_EQ_557U(...) \, +#define Z_IS_557U_EQ_557U(...) \, +#define Z_IS_558_EQ_558(...) \, +#define Z_IS_558U_EQ_558(...) \, +#define Z_IS_558_EQ_558U(...) \, +#define Z_IS_558U_EQ_558U(...) \, +#define Z_IS_559_EQ_559(...) \, +#define Z_IS_559U_EQ_559(...) \, +#define Z_IS_559_EQ_559U(...) \, +#define Z_IS_559U_EQ_559U(...) \, +#define Z_IS_560_EQ_560(...) \, +#define Z_IS_560U_EQ_560(...) \, +#define Z_IS_560_EQ_560U(...) \, +#define Z_IS_560U_EQ_560U(...) \, +#define Z_IS_561_EQ_561(...) \, +#define Z_IS_561U_EQ_561(...) \, +#define Z_IS_561_EQ_561U(...) \, +#define Z_IS_561U_EQ_561U(...) \, +#define Z_IS_562_EQ_562(...) \, +#define Z_IS_562U_EQ_562(...) \, +#define Z_IS_562_EQ_562U(...) \, +#define Z_IS_562U_EQ_562U(...) \, +#define Z_IS_563_EQ_563(...) \, +#define Z_IS_563U_EQ_563(...) \, +#define Z_IS_563_EQ_563U(...) \, +#define Z_IS_563U_EQ_563U(...) \, +#define Z_IS_564_EQ_564(...) \, +#define Z_IS_564U_EQ_564(...) \, +#define Z_IS_564_EQ_564U(...) \, +#define Z_IS_564U_EQ_564U(...) \, +#define Z_IS_565_EQ_565(...) \, +#define Z_IS_565U_EQ_565(...) \, +#define Z_IS_565_EQ_565U(...) \, +#define Z_IS_565U_EQ_565U(...) \, +#define Z_IS_566_EQ_566(...) \, +#define Z_IS_566U_EQ_566(...) \, +#define Z_IS_566_EQ_566U(...) \, +#define Z_IS_566U_EQ_566U(...) \, +#define Z_IS_567_EQ_567(...) \, +#define Z_IS_567U_EQ_567(...) \, +#define Z_IS_567_EQ_567U(...) \, +#define Z_IS_567U_EQ_567U(...) \, +#define Z_IS_568_EQ_568(...) \, +#define Z_IS_568U_EQ_568(...) \, +#define Z_IS_568_EQ_568U(...) \, +#define Z_IS_568U_EQ_568U(...) \, +#define Z_IS_569_EQ_569(...) \, +#define Z_IS_569U_EQ_569(...) \, +#define Z_IS_569_EQ_569U(...) \, +#define Z_IS_569U_EQ_569U(...) \, +#define Z_IS_570_EQ_570(...) \, +#define Z_IS_570U_EQ_570(...) \, +#define Z_IS_570_EQ_570U(...) \, +#define Z_IS_570U_EQ_570U(...) \, +#define Z_IS_571_EQ_571(...) \, +#define Z_IS_571U_EQ_571(...) \, +#define Z_IS_571_EQ_571U(...) \, +#define Z_IS_571U_EQ_571U(...) \, +#define Z_IS_572_EQ_572(...) \, +#define Z_IS_572U_EQ_572(...) \, +#define Z_IS_572_EQ_572U(...) \, +#define Z_IS_572U_EQ_572U(...) \, +#define Z_IS_573_EQ_573(...) \, +#define Z_IS_573U_EQ_573(...) \, +#define Z_IS_573_EQ_573U(...) \, +#define Z_IS_573U_EQ_573U(...) \, +#define Z_IS_574_EQ_574(...) \, +#define Z_IS_574U_EQ_574(...) \, +#define Z_IS_574_EQ_574U(...) \, +#define Z_IS_574U_EQ_574U(...) \, +#define Z_IS_575_EQ_575(...) \, +#define Z_IS_575U_EQ_575(...) \, +#define Z_IS_575_EQ_575U(...) \, +#define Z_IS_575U_EQ_575U(...) \, +#define Z_IS_576_EQ_576(...) \, +#define Z_IS_576U_EQ_576(...) \, +#define Z_IS_576_EQ_576U(...) \, +#define Z_IS_576U_EQ_576U(...) \, +#define Z_IS_577_EQ_577(...) \, +#define Z_IS_577U_EQ_577(...) \, +#define Z_IS_577_EQ_577U(...) \, +#define Z_IS_577U_EQ_577U(...) \, +#define Z_IS_578_EQ_578(...) \, +#define Z_IS_578U_EQ_578(...) \, +#define Z_IS_578_EQ_578U(...) \, +#define Z_IS_578U_EQ_578U(...) \, +#define Z_IS_579_EQ_579(...) \, +#define Z_IS_579U_EQ_579(...) \, +#define Z_IS_579_EQ_579U(...) \, +#define Z_IS_579U_EQ_579U(...) \, +#define Z_IS_580_EQ_580(...) \, +#define Z_IS_580U_EQ_580(...) \, +#define Z_IS_580_EQ_580U(...) \, +#define Z_IS_580U_EQ_580U(...) \, +#define Z_IS_581_EQ_581(...) \, +#define Z_IS_581U_EQ_581(...) \, +#define Z_IS_581_EQ_581U(...) \, +#define Z_IS_581U_EQ_581U(...) \, +#define Z_IS_582_EQ_582(...) \, +#define Z_IS_582U_EQ_582(...) \, +#define Z_IS_582_EQ_582U(...) \, +#define Z_IS_582U_EQ_582U(...) \, +#define Z_IS_583_EQ_583(...) \, +#define Z_IS_583U_EQ_583(...) \, +#define Z_IS_583_EQ_583U(...) \, +#define Z_IS_583U_EQ_583U(...) \, +#define Z_IS_584_EQ_584(...) \, +#define Z_IS_584U_EQ_584(...) \, +#define Z_IS_584_EQ_584U(...) \, +#define Z_IS_584U_EQ_584U(...) \, +#define Z_IS_585_EQ_585(...) \, +#define Z_IS_585U_EQ_585(...) \, +#define Z_IS_585_EQ_585U(...) \, +#define Z_IS_585U_EQ_585U(...) \, +#define Z_IS_586_EQ_586(...) \, +#define Z_IS_586U_EQ_586(...) \, +#define Z_IS_586_EQ_586U(...) \, +#define Z_IS_586U_EQ_586U(...) \, +#define Z_IS_587_EQ_587(...) \, +#define Z_IS_587U_EQ_587(...) \, +#define Z_IS_587_EQ_587U(...) \, +#define Z_IS_587U_EQ_587U(...) \, +#define Z_IS_588_EQ_588(...) \, +#define Z_IS_588U_EQ_588(...) \, +#define Z_IS_588_EQ_588U(...) \, +#define Z_IS_588U_EQ_588U(...) \, +#define Z_IS_589_EQ_589(...) \, +#define Z_IS_589U_EQ_589(...) \, +#define Z_IS_589_EQ_589U(...) \, +#define Z_IS_589U_EQ_589U(...) \, +#define Z_IS_590_EQ_590(...) \, +#define Z_IS_590U_EQ_590(...) \, +#define Z_IS_590_EQ_590U(...) \, +#define Z_IS_590U_EQ_590U(...) \, +#define Z_IS_591_EQ_591(...) \, +#define Z_IS_591U_EQ_591(...) \, +#define Z_IS_591_EQ_591U(...) \, +#define Z_IS_591U_EQ_591U(...) \, +#define Z_IS_592_EQ_592(...) \, +#define Z_IS_592U_EQ_592(...) \, +#define Z_IS_592_EQ_592U(...) \, +#define Z_IS_592U_EQ_592U(...) \, +#define Z_IS_593_EQ_593(...) \, +#define Z_IS_593U_EQ_593(...) \, +#define Z_IS_593_EQ_593U(...) \, +#define Z_IS_593U_EQ_593U(...) \, +#define Z_IS_594_EQ_594(...) \, +#define Z_IS_594U_EQ_594(...) \, +#define Z_IS_594_EQ_594U(...) \, +#define Z_IS_594U_EQ_594U(...) \, +#define Z_IS_595_EQ_595(...) \, +#define Z_IS_595U_EQ_595(...) \, +#define Z_IS_595_EQ_595U(...) \, +#define Z_IS_595U_EQ_595U(...) \, +#define Z_IS_596_EQ_596(...) \, +#define Z_IS_596U_EQ_596(...) \, +#define Z_IS_596_EQ_596U(...) \, +#define Z_IS_596U_EQ_596U(...) \, +#define Z_IS_597_EQ_597(...) \, +#define Z_IS_597U_EQ_597(...) \, +#define Z_IS_597_EQ_597U(...) \, +#define Z_IS_597U_EQ_597U(...) \, +#define Z_IS_598_EQ_598(...) \, +#define Z_IS_598U_EQ_598(...) \, +#define Z_IS_598_EQ_598U(...) \, +#define Z_IS_598U_EQ_598U(...) \, +#define Z_IS_599_EQ_599(...) \, +#define Z_IS_599U_EQ_599(...) \, +#define Z_IS_599_EQ_599U(...) \, +#define Z_IS_599U_EQ_599U(...) \, +#define Z_IS_600_EQ_600(...) \, +#define Z_IS_600U_EQ_600(...) \, +#define Z_IS_600_EQ_600U(...) \, +#define Z_IS_600U_EQ_600U(...) \, +#define Z_IS_601_EQ_601(...) \, +#define Z_IS_601U_EQ_601(...) \, +#define Z_IS_601_EQ_601U(...) \, +#define Z_IS_601U_EQ_601U(...) \, +#define Z_IS_602_EQ_602(...) \, +#define Z_IS_602U_EQ_602(...) \, +#define Z_IS_602_EQ_602U(...) \, +#define Z_IS_602U_EQ_602U(...) \, +#define Z_IS_603_EQ_603(...) \, +#define Z_IS_603U_EQ_603(...) \, +#define Z_IS_603_EQ_603U(...) \, +#define Z_IS_603U_EQ_603U(...) \, +#define Z_IS_604_EQ_604(...) \, +#define Z_IS_604U_EQ_604(...) \, +#define Z_IS_604_EQ_604U(...) \, +#define Z_IS_604U_EQ_604U(...) \, +#define Z_IS_605_EQ_605(...) \, +#define Z_IS_605U_EQ_605(...) \, +#define Z_IS_605_EQ_605U(...) \, +#define Z_IS_605U_EQ_605U(...) \, +#define Z_IS_606_EQ_606(...) \, +#define Z_IS_606U_EQ_606(...) \, +#define Z_IS_606_EQ_606U(...) \, +#define Z_IS_606U_EQ_606U(...) \, +#define Z_IS_607_EQ_607(...) \, +#define Z_IS_607U_EQ_607(...) \, +#define Z_IS_607_EQ_607U(...) \, +#define Z_IS_607U_EQ_607U(...) \, +#define Z_IS_608_EQ_608(...) \, +#define Z_IS_608U_EQ_608(...) \, +#define Z_IS_608_EQ_608U(...) \, +#define Z_IS_608U_EQ_608U(...) \, +#define Z_IS_609_EQ_609(...) \, +#define Z_IS_609U_EQ_609(...) \, +#define Z_IS_609_EQ_609U(...) \, +#define Z_IS_609U_EQ_609U(...) \, +#define Z_IS_610_EQ_610(...) \, +#define Z_IS_610U_EQ_610(...) \, +#define Z_IS_610_EQ_610U(...) \, +#define Z_IS_610U_EQ_610U(...) \, +#define Z_IS_611_EQ_611(...) \, +#define Z_IS_611U_EQ_611(...) \, +#define Z_IS_611_EQ_611U(...) \, +#define Z_IS_611U_EQ_611U(...) \, +#define Z_IS_612_EQ_612(...) \, +#define Z_IS_612U_EQ_612(...) \, +#define Z_IS_612_EQ_612U(...) \, +#define Z_IS_612U_EQ_612U(...) \, +#define Z_IS_613_EQ_613(...) \, +#define Z_IS_613U_EQ_613(...) \, +#define Z_IS_613_EQ_613U(...) \, +#define Z_IS_613U_EQ_613U(...) \, +#define Z_IS_614_EQ_614(...) \, +#define Z_IS_614U_EQ_614(...) \, +#define Z_IS_614_EQ_614U(...) \, +#define Z_IS_614U_EQ_614U(...) \, +#define Z_IS_615_EQ_615(...) \, +#define Z_IS_615U_EQ_615(...) \, +#define Z_IS_615_EQ_615U(...) \, +#define Z_IS_615U_EQ_615U(...) \, +#define Z_IS_616_EQ_616(...) \, +#define Z_IS_616U_EQ_616(...) \, +#define Z_IS_616_EQ_616U(...) \, +#define Z_IS_616U_EQ_616U(...) \, +#define Z_IS_617_EQ_617(...) \, +#define Z_IS_617U_EQ_617(...) \, +#define Z_IS_617_EQ_617U(...) \, +#define Z_IS_617U_EQ_617U(...) \, +#define Z_IS_618_EQ_618(...) \, +#define Z_IS_618U_EQ_618(...) \, +#define Z_IS_618_EQ_618U(...) \, +#define Z_IS_618U_EQ_618U(...) \, +#define Z_IS_619_EQ_619(...) \, +#define Z_IS_619U_EQ_619(...) \, +#define Z_IS_619_EQ_619U(...) \, +#define Z_IS_619U_EQ_619U(...) \, +#define Z_IS_620_EQ_620(...) \, +#define Z_IS_620U_EQ_620(...) \, +#define Z_IS_620_EQ_620U(...) \, +#define Z_IS_620U_EQ_620U(...) \, +#define Z_IS_621_EQ_621(...) \, +#define Z_IS_621U_EQ_621(...) \, +#define Z_IS_621_EQ_621U(...) \, +#define Z_IS_621U_EQ_621U(...) \, +#define Z_IS_622_EQ_622(...) \, +#define Z_IS_622U_EQ_622(...) \, +#define Z_IS_622_EQ_622U(...) \, +#define Z_IS_622U_EQ_622U(...) \, +#define Z_IS_623_EQ_623(...) \, +#define Z_IS_623U_EQ_623(...) \, +#define Z_IS_623_EQ_623U(...) \, +#define Z_IS_623U_EQ_623U(...) \, +#define Z_IS_624_EQ_624(...) \, +#define Z_IS_624U_EQ_624(...) \, +#define Z_IS_624_EQ_624U(...) \, +#define Z_IS_624U_EQ_624U(...) \, +#define Z_IS_625_EQ_625(...) \, +#define Z_IS_625U_EQ_625(...) \, +#define Z_IS_625_EQ_625U(...) \, +#define Z_IS_625U_EQ_625U(...) \, +#define Z_IS_626_EQ_626(...) \, +#define Z_IS_626U_EQ_626(...) \, +#define Z_IS_626_EQ_626U(...) \, +#define Z_IS_626U_EQ_626U(...) \, +#define Z_IS_627_EQ_627(...) \, +#define Z_IS_627U_EQ_627(...) \, +#define Z_IS_627_EQ_627U(...) \, +#define Z_IS_627U_EQ_627U(...) \, +#define Z_IS_628_EQ_628(...) \, +#define Z_IS_628U_EQ_628(...) \, +#define Z_IS_628_EQ_628U(...) \, +#define Z_IS_628U_EQ_628U(...) \, +#define Z_IS_629_EQ_629(...) \, +#define Z_IS_629U_EQ_629(...) \, +#define Z_IS_629_EQ_629U(...) \, +#define Z_IS_629U_EQ_629U(...) \, +#define Z_IS_630_EQ_630(...) \, +#define Z_IS_630U_EQ_630(...) \, +#define Z_IS_630_EQ_630U(...) \, +#define Z_IS_630U_EQ_630U(...) \, +#define Z_IS_631_EQ_631(...) \, +#define Z_IS_631U_EQ_631(...) \, +#define Z_IS_631_EQ_631U(...) \, +#define Z_IS_631U_EQ_631U(...) \, +#define Z_IS_632_EQ_632(...) \, +#define Z_IS_632U_EQ_632(...) \, +#define Z_IS_632_EQ_632U(...) \, +#define Z_IS_632U_EQ_632U(...) \, +#define Z_IS_633_EQ_633(...) \, +#define Z_IS_633U_EQ_633(...) \, +#define Z_IS_633_EQ_633U(...) \, +#define Z_IS_633U_EQ_633U(...) \, +#define Z_IS_634_EQ_634(...) \, +#define Z_IS_634U_EQ_634(...) \, +#define Z_IS_634_EQ_634U(...) \, +#define Z_IS_634U_EQ_634U(...) \, +#define Z_IS_635_EQ_635(...) \, +#define Z_IS_635U_EQ_635(...) \, +#define Z_IS_635_EQ_635U(...) \, +#define Z_IS_635U_EQ_635U(...) \, +#define Z_IS_636_EQ_636(...) \, +#define Z_IS_636U_EQ_636(...) \, +#define Z_IS_636_EQ_636U(...) \, +#define Z_IS_636U_EQ_636U(...) \, +#define Z_IS_637_EQ_637(...) \, +#define Z_IS_637U_EQ_637(...) \, +#define Z_IS_637_EQ_637U(...) \, +#define Z_IS_637U_EQ_637U(...) \, +#define Z_IS_638_EQ_638(...) \, +#define Z_IS_638U_EQ_638(...) \, +#define Z_IS_638_EQ_638U(...) \, +#define Z_IS_638U_EQ_638U(...) \, +#define Z_IS_639_EQ_639(...) \, +#define Z_IS_639U_EQ_639(...) \, +#define Z_IS_639_EQ_639U(...) \, +#define Z_IS_639U_EQ_639U(...) \, +#define Z_IS_640_EQ_640(...) \, +#define Z_IS_640U_EQ_640(...) \, +#define Z_IS_640_EQ_640U(...) \, +#define Z_IS_640U_EQ_640U(...) \, +#define Z_IS_641_EQ_641(...) \, +#define Z_IS_641U_EQ_641(...) \, +#define Z_IS_641_EQ_641U(...) \, +#define Z_IS_641U_EQ_641U(...) \, +#define Z_IS_642_EQ_642(...) \, +#define Z_IS_642U_EQ_642(...) \, +#define Z_IS_642_EQ_642U(...) \, +#define Z_IS_642U_EQ_642U(...) \, +#define Z_IS_643_EQ_643(...) \, +#define Z_IS_643U_EQ_643(...) \, +#define Z_IS_643_EQ_643U(...) \, +#define Z_IS_643U_EQ_643U(...) \, +#define Z_IS_644_EQ_644(...) \, +#define Z_IS_644U_EQ_644(...) \, +#define Z_IS_644_EQ_644U(...) \, +#define Z_IS_644U_EQ_644U(...) \, +#define Z_IS_645_EQ_645(...) \, +#define Z_IS_645U_EQ_645(...) \, +#define Z_IS_645_EQ_645U(...) \, +#define Z_IS_645U_EQ_645U(...) \, +#define Z_IS_646_EQ_646(...) \, +#define Z_IS_646U_EQ_646(...) \, +#define Z_IS_646_EQ_646U(...) \, +#define Z_IS_646U_EQ_646U(...) \, +#define Z_IS_647_EQ_647(...) \, +#define Z_IS_647U_EQ_647(...) \, +#define Z_IS_647_EQ_647U(...) \, +#define Z_IS_647U_EQ_647U(...) \, +#define Z_IS_648_EQ_648(...) \, +#define Z_IS_648U_EQ_648(...) \, +#define Z_IS_648_EQ_648U(...) \, +#define Z_IS_648U_EQ_648U(...) \, +#define Z_IS_649_EQ_649(...) \, +#define Z_IS_649U_EQ_649(...) \, +#define Z_IS_649_EQ_649U(...) \, +#define Z_IS_649U_EQ_649U(...) \, +#define Z_IS_650_EQ_650(...) \, +#define Z_IS_650U_EQ_650(...) \, +#define Z_IS_650_EQ_650U(...) \, +#define Z_IS_650U_EQ_650U(...) \, +#define Z_IS_651_EQ_651(...) \, +#define Z_IS_651U_EQ_651(...) \, +#define Z_IS_651_EQ_651U(...) \, +#define Z_IS_651U_EQ_651U(...) \, +#define Z_IS_652_EQ_652(...) \, +#define Z_IS_652U_EQ_652(...) \, +#define Z_IS_652_EQ_652U(...) \, +#define Z_IS_652U_EQ_652U(...) \, +#define Z_IS_653_EQ_653(...) \, +#define Z_IS_653U_EQ_653(...) \, +#define Z_IS_653_EQ_653U(...) \, +#define Z_IS_653U_EQ_653U(...) \, +#define Z_IS_654_EQ_654(...) \, +#define Z_IS_654U_EQ_654(...) \, +#define Z_IS_654_EQ_654U(...) \, +#define Z_IS_654U_EQ_654U(...) \, +#define Z_IS_655_EQ_655(...) \, +#define Z_IS_655U_EQ_655(...) \, +#define Z_IS_655_EQ_655U(...) \, +#define Z_IS_655U_EQ_655U(...) \, +#define Z_IS_656_EQ_656(...) \, +#define Z_IS_656U_EQ_656(...) \, +#define Z_IS_656_EQ_656U(...) \, +#define Z_IS_656U_EQ_656U(...) \, +#define Z_IS_657_EQ_657(...) \, +#define Z_IS_657U_EQ_657(...) \, +#define Z_IS_657_EQ_657U(...) \, +#define Z_IS_657U_EQ_657U(...) \, +#define Z_IS_658_EQ_658(...) \, +#define Z_IS_658U_EQ_658(...) \, +#define Z_IS_658_EQ_658U(...) \, +#define Z_IS_658U_EQ_658U(...) \, +#define Z_IS_659_EQ_659(...) \, +#define Z_IS_659U_EQ_659(...) \, +#define Z_IS_659_EQ_659U(...) \, +#define Z_IS_659U_EQ_659U(...) \, +#define Z_IS_660_EQ_660(...) \, +#define Z_IS_660U_EQ_660(...) \, +#define Z_IS_660_EQ_660U(...) \, +#define Z_IS_660U_EQ_660U(...) \, +#define Z_IS_661_EQ_661(...) \, +#define Z_IS_661U_EQ_661(...) \, +#define Z_IS_661_EQ_661U(...) \, +#define Z_IS_661U_EQ_661U(...) \, +#define Z_IS_662_EQ_662(...) \, +#define Z_IS_662U_EQ_662(...) \, +#define Z_IS_662_EQ_662U(...) \, +#define Z_IS_662U_EQ_662U(...) \, +#define Z_IS_663_EQ_663(...) \, +#define Z_IS_663U_EQ_663(...) \, +#define Z_IS_663_EQ_663U(...) \, +#define Z_IS_663U_EQ_663U(...) \, +#define Z_IS_664_EQ_664(...) \, +#define Z_IS_664U_EQ_664(...) \, +#define Z_IS_664_EQ_664U(...) \, +#define Z_IS_664U_EQ_664U(...) \, +#define Z_IS_665_EQ_665(...) \, +#define Z_IS_665U_EQ_665(...) \, +#define Z_IS_665_EQ_665U(...) \, +#define Z_IS_665U_EQ_665U(...) \, +#define Z_IS_666_EQ_666(...) \, +#define Z_IS_666U_EQ_666(...) \, +#define Z_IS_666_EQ_666U(...) \, +#define Z_IS_666U_EQ_666U(...) \, +#define Z_IS_667_EQ_667(...) \, +#define Z_IS_667U_EQ_667(...) \, +#define Z_IS_667_EQ_667U(...) \, +#define Z_IS_667U_EQ_667U(...) \, +#define Z_IS_668_EQ_668(...) \, +#define Z_IS_668U_EQ_668(...) \, +#define Z_IS_668_EQ_668U(...) \, +#define Z_IS_668U_EQ_668U(...) \, +#define Z_IS_669_EQ_669(...) \, +#define Z_IS_669U_EQ_669(...) \, +#define Z_IS_669_EQ_669U(...) \, +#define Z_IS_669U_EQ_669U(...) \, +#define Z_IS_670_EQ_670(...) \, +#define Z_IS_670U_EQ_670(...) \, +#define Z_IS_670_EQ_670U(...) \, +#define Z_IS_670U_EQ_670U(...) \, +#define Z_IS_671_EQ_671(...) \, +#define Z_IS_671U_EQ_671(...) \, +#define Z_IS_671_EQ_671U(...) \, +#define Z_IS_671U_EQ_671U(...) \, +#define Z_IS_672_EQ_672(...) \, +#define Z_IS_672U_EQ_672(...) \, +#define Z_IS_672_EQ_672U(...) \, +#define Z_IS_672U_EQ_672U(...) \, +#define Z_IS_673_EQ_673(...) \, +#define Z_IS_673U_EQ_673(...) \, +#define Z_IS_673_EQ_673U(...) \, +#define Z_IS_673U_EQ_673U(...) \, +#define Z_IS_674_EQ_674(...) \, +#define Z_IS_674U_EQ_674(...) \, +#define Z_IS_674_EQ_674U(...) \, +#define Z_IS_674U_EQ_674U(...) \, +#define Z_IS_675_EQ_675(...) \, +#define Z_IS_675U_EQ_675(...) \, +#define Z_IS_675_EQ_675U(...) \, +#define Z_IS_675U_EQ_675U(...) \, +#define Z_IS_676_EQ_676(...) \, +#define Z_IS_676U_EQ_676(...) \, +#define Z_IS_676_EQ_676U(...) \, +#define Z_IS_676U_EQ_676U(...) \, +#define Z_IS_677_EQ_677(...) \, +#define Z_IS_677U_EQ_677(...) \, +#define Z_IS_677_EQ_677U(...) \, +#define Z_IS_677U_EQ_677U(...) \, +#define Z_IS_678_EQ_678(...) \, +#define Z_IS_678U_EQ_678(...) \, +#define Z_IS_678_EQ_678U(...) \, +#define Z_IS_678U_EQ_678U(...) \, +#define Z_IS_679_EQ_679(...) \, +#define Z_IS_679U_EQ_679(...) \, +#define Z_IS_679_EQ_679U(...) \, +#define Z_IS_679U_EQ_679U(...) \, +#define Z_IS_680_EQ_680(...) \, +#define Z_IS_680U_EQ_680(...) \, +#define Z_IS_680_EQ_680U(...) \, +#define Z_IS_680U_EQ_680U(...) \, +#define Z_IS_681_EQ_681(...) \, +#define Z_IS_681U_EQ_681(...) \, +#define Z_IS_681_EQ_681U(...) \, +#define Z_IS_681U_EQ_681U(...) \, +#define Z_IS_682_EQ_682(...) \, +#define Z_IS_682U_EQ_682(...) \, +#define Z_IS_682_EQ_682U(...) \, +#define Z_IS_682U_EQ_682U(...) \, +#define Z_IS_683_EQ_683(...) \, +#define Z_IS_683U_EQ_683(...) \, +#define Z_IS_683_EQ_683U(...) \, +#define Z_IS_683U_EQ_683U(...) \, +#define Z_IS_684_EQ_684(...) \, +#define Z_IS_684U_EQ_684(...) \, +#define Z_IS_684_EQ_684U(...) \, +#define Z_IS_684U_EQ_684U(...) \, +#define Z_IS_685_EQ_685(...) \, +#define Z_IS_685U_EQ_685(...) \, +#define Z_IS_685_EQ_685U(...) \, +#define Z_IS_685U_EQ_685U(...) \, +#define Z_IS_686_EQ_686(...) \, +#define Z_IS_686U_EQ_686(...) \, +#define Z_IS_686_EQ_686U(...) \, +#define Z_IS_686U_EQ_686U(...) \, +#define Z_IS_687_EQ_687(...) \, +#define Z_IS_687U_EQ_687(...) \, +#define Z_IS_687_EQ_687U(...) \, +#define Z_IS_687U_EQ_687U(...) \, +#define Z_IS_688_EQ_688(...) \, +#define Z_IS_688U_EQ_688(...) \, +#define Z_IS_688_EQ_688U(...) \, +#define Z_IS_688U_EQ_688U(...) \, +#define Z_IS_689_EQ_689(...) \, +#define Z_IS_689U_EQ_689(...) \, +#define Z_IS_689_EQ_689U(...) \, +#define Z_IS_689U_EQ_689U(...) \, +#define Z_IS_690_EQ_690(...) \, +#define Z_IS_690U_EQ_690(...) \, +#define Z_IS_690_EQ_690U(...) \, +#define Z_IS_690U_EQ_690U(...) \, +#define Z_IS_691_EQ_691(...) \, +#define Z_IS_691U_EQ_691(...) \, +#define Z_IS_691_EQ_691U(...) \, +#define Z_IS_691U_EQ_691U(...) \, +#define Z_IS_692_EQ_692(...) \, +#define Z_IS_692U_EQ_692(...) \, +#define Z_IS_692_EQ_692U(...) \, +#define Z_IS_692U_EQ_692U(...) \, +#define Z_IS_693_EQ_693(...) \, +#define Z_IS_693U_EQ_693(...) \, +#define Z_IS_693_EQ_693U(...) \, +#define Z_IS_693U_EQ_693U(...) \, +#define Z_IS_694_EQ_694(...) \, +#define Z_IS_694U_EQ_694(...) \, +#define Z_IS_694_EQ_694U(...) \, +#define Z_IS_694U_EQ_694U(...) \, +#define Z_IS_695_EQ_695(...) \, +#define Z_IS_695U_EQ_695(...) \, +#define Z_IS_695_EQ_695U(...) \, +#define Z_IS_695U_EQ_695U(...) \, +#define Z_IS_696_EQ_696(...) \, +#define Z_IS_696U_EQ_696(...) \, +#define Z_IS_696_EQ_696U(...) \, +#define Z_IS_696U_EQ_696U(...) \, +#define Z_IS_697_EQ_697(...) \, +#define Z_IS_697U_EQ_697(...) \, +#define Z_IS_697_EQ_697U(...) \, +#define Z_IS_697U_EQ_697U(...) \, +#define Z_IS_698_EQ_698(...) \, +#define Z_IS_698U_EQ_698(...) \, +#define Z_IS_698_EQ_698U(...) \, +#define Z_IS_698U_EQ_698U(...) \, +#define Z_IS_699_EQ_699(...) \, +#define Z_IS_699U_EQ_699(...) \, +#define Z_IS_699_EQ_699U(...) \, +#define Z_IS_699U_EQ_699U(...) \, +#define Z_IS_700_EQ_700(...) \, +#define Z_IS_700U_EQ_700(...) \, +#define Z_IS_700_EQ_700U(...) \, +#define Z_IS_700U_EQ_700U(...) \, +#define Z_IS_701_EQ_701(...) \, +#define Z_IS_701U_EQ_701(...) \, +#define Z_IS_701_EQ_701U(...) \, +#define Z_IS_701U_EQ_701U(...) \, +#define Z_IS_702_EQ_702(...) \, +#define Z_IS_702U_EQ_702(...) \, +#define Z_IS_702_EQ_702U(...) \, +#define Z_IS_702U_EQ_702U(...) \, +#define Z_IS_703_EQ_703(...) \, +#define Z_IS_703U_EQ_703(...) \, +#define Z_IS_703_EQ_703U(...) \, +#define Z_IS_703U_EQ_703U(...) \, +#define Z_IS_704_EQ_704(...) \, +#define Z_IS_704U_EQ_704(...) \, +#define Z_IS_704_EQ_704U(...) \, +#define Z_IS_704U_EQ_704U(...) \, +#define Z_IS_705_EQ_705(...) \, +#define Z_IS_705U_EQ_705(...) \, +#define Z_IS_705_EQ_705U(...) \, +#define Z_IS_705U_EQ_705U(...) \, +#define Z_IS_706_EQ_706(...) \, +#define Z_IS_706U_EQ_706(...) \, +#define Z_IS_706_EQ_706U(...) \, +#define Z_IS_706U_EQ_706U(...) \, +#define Z_IS_707_EQ_707(...) \, +#define Z_IS_707U_EQ_707(...) \, +#define Z_IS_707_EQ_707U(...) \, +#define Z_IS_707U_EQ_707U(...) \, +#define Z_IS_708_EQ_708(...) \, +#define Z_IS_708U_EQ_708(...) \, +#define Z_IS_708_EQ_708U(...) \, +#define Z_IS_708U_EQ_708U(...) \, +#define Z_IS_709_EQ_709(...) \, +#define Z_IS_709U_EQ_709(...) \, +#define Z_IS_709_EQ_709U(...) \, +#define Z_IS_709U_EQ_709U(...) \, +#define Z_IS_710_EQ_710(...) \, +#define Z_IS_710U_EQ_710(...) \, +#define Z_IS_710_EQ_710U(...) \, +#define Z_IS_710U_EQ_710U(...) \, +#define Z_IS_711_EQ_711(...) \, +#define Z_IS_711U_EQ_711(...) \, +#define Z_IS_711_EQ_711U(...) \, +#define Z_IS_711U_EQ_711U(...) \, +#define Z_IS_712_EQ_712(...) \, +#define Z_IS_712U_EQ_712(...) \, +#define Z_IS_712_EQ_712U(...) \, +#define Z_IS_712U_EQ_712U(...) \, +#define Z_IS_713_EQ_713(...) \, +#define Z_IS_713U_EQ_713(...) \, +#define Z_IS_713_EQ_713U(...) \, +#define Z_IS_713U_EQ_713U(...) \, +#define Z_IS_714_EQ_714(...) \, +#define Z_IS_714U_EQ_714(...) \, +#define Z_IS_714_EQ_714U(...) \, +#define Z_IS_714U_EQ_714U(...) \, +#define Z_IS_715_EQ_715(...) \, +#define Z_IS_715U_EQ_715(...) \, +#define Z_IS_715_EQ_715U(...) \, +#define Z_IS_715U_EQ_715U(...) \, +#define Z_IS_716_EQ_716(...) \, +#define Z_IS_716U_EQ_716(...) \, +#define Z_IS_716_EQ_716U(...) \, +#define Z_IS_716U_EQ_716U(...) \, +#define Z_IS_717_EQ_717(...) \, +#define Z_IS_717U_EQ_717(...) \, +#define Z_IS_717_EQ_717U(...) \, +#define Z_IS_717U_EQ_717U(...) \, +#define Z_IS_718_EQ_718(...) \, +#define Z_IS_718U_EQ_718(...) \, +#define Z_IS_718_EQ_718U(...) \, +#define Z_IS_718U_EQ_718U(...) \, +#define Z_IS_719_EQ_719(...) \, +#define Z_IS_719U_EQ_719(...) \, +#define Z_IS_719_EQ_719U(...) \, +#define Z_IS_719U_EQ_719U(...) \, +#define Z_IS_720_EQ_720(...) \, +#define Z_IS_720U_EQ_720(...) \, +#define Z_IS_720_EQ_720U(...) \, +#define Z_IS_720U_EQ_720U(...) \, +#define Z_IS_721_EQ_721(...) \, +#define Z_IS_721U_EQ_721(...) \, +#define Z_IS_721_EQ_721U(...) \, +#define Z_IS_721U_EQ_721U(...) \, +#define Z_IS_722_EQ_722(...) \, +#define Z_IS_722U_EQ_722(...) \, +#define Z_IS_722_EQ_722U(...) \, +#define Z_IS_722U_EQ_722U(...) \, +#define Z_IS_723_EQ_723(...) \, +#define Z_IS_723U_EQ_723(...) \, +#define Z_IS_723_EQ_723U(...) \, +#define Z_IS_723U_EQ_723U(...) \, +#define Z_IS_724_EQ_724(...) \, +#define Z_IS_724U_EQ_724(...) \, +#define Z_IS_724_EQ_724U(...) \, +#define Z_IS_724U_EQ_724U(...) \, +#define Z_IS_725_EQ_725(...) \, +#define Z_IS_725U_EQ_725(...) \, +#define Z_IS_725_EQ_725U(...) \, +#define Z_IS_725U_EQ_725U(...) \, +#define Z_IS_726_EQ_726(...) \, +#define Z_IS_726U_EQ_726(...) \, +#define Z_IS_726_EQ_726U(...) \, +#define Z_IS_726U_EQ_726U(...) \, +#define Z_IS_727_EQ_727(...) \, +#define Z_IS_727U_EQ_727(...) \, +#define Z_IS_727_EQ_727U(...) \, +#define Z_IS_727U_EQ_727U(...) \, +#define Z_IS_728_EQ_728(...) \, +#define Z_IS_728U_EQ_728(...) \, +#define Z_IS_728_EQ_728U(...) \, +#define Z_IS_728U_EQ_728U(...) \, +#define Z_IS_729_EQ_729(...) \, +#define Z_IS_729U_EQ_729(...) \, +#define Z_IS_729_EQ_729U(...) \, +#define Z_IS_729U_EQ_729U(...) \, +#define Z_IS_730_EQ_730(...) \, +#define Z_IS_730U_EQ_730(...) \, +#define Z_IS_730_EQ_730U(...) \, +#define Z_IS_730U_EQ_730U(...) \, +#define Z_IS_731_EQ_731(...) \, +#define Z_IS_731U_EQ_731(...) \, +#define Z_IS_731_EQ_731U(...) \, +#define Z_IS_731U_EQ_731U(...) \, +#define Z_IS_732_EQ_732(...) \, +#define Z_IS_732U_EQ_732(...) \, +#define Z_IS_732_EQ_732U(...) \, +#define Z_IS_732U_EQ_732U(...) \, +#define Z_IS_733_EQ_733(...) \, +#define Z_IS_733U_EQ_733(...) \, +#define Z_IS_733_EQ_733U(...) \, +#define Z_IS_733U_EQ_733U(...) \, +#define Z_IS_734_EQ_734(...) \, +#define Z_IS_734U_EQ_734(...) \, +#define Z_IS_734_EQ_734U(...) \, +#define Z_IS_734U_EQ_734U(...) \, +#define Z_IS_735_EQ_735(...) \, +#define Z_IS_735U_EQ_735(...) \, +#define Z_IS_735_EQ_735U(...) \, +#define Z_IS_735U_EQ_735U(...) \, +#define Z_IS_736_EQ_736(...) \, +#define Z_IS_736U_EQ_736(...) \, +#define Z_IS_736_EQ_736U(...) \, +#define Z_IS_736U_EQ_736U(...) \, +#define Z_IS_737_EQ_737(...) \, +#define Z_IS_737U_EQ_737(...) \, +#define Z_IS_737_EQ_737U(...) \, +#define Z_IS_737U_EQ_737U(...) \, +#define Z_IS_738_EQ_738(...) \, +#define Z_IS_738U_EQ_738(...) \, +#define Z_IS_738_EQ_738U(...) \, +#define Z_IS_738U_EQ_738U(...) \, +#define Z_IS_739_EQ_739(...) \, +#define Z_IS_739U_EQ_739(...) \, +#define Z_IS_739_EQ_739U(...) \, +#define Z_IS_739U_EQ_739U(...) \, +#define Z_IS_740_EQ_740(...) \, +#define Z_IS_740U_EQ_740(...) \, +#define Z_IS_740_EQ_740U(...) \, +#define Z_IS_740U_EQ_740U(...) \, +#define Z_IS_741_EQ_741(...) \, +#define Z_IS_741U_EQ_741(...) \, +#define Z_IS_741_EQ_741U(...) \, +#define Z_IS_741U_EQ_741U(...) \, +#define Z_IS_742_EQ_742(...) \, +#define Z_IS_742U_EQ_742(...) \, +#define Z_IS_742_EQ_742U(...) \, +#define Z_IS_742U_EQ_742U(...) \, +#define Z_IS_743_EQ_743(...) \, +#define Z_IS_743U_EQ_743(...) \, +#define Z_IS_743_EQ_743U(...) \, +#define Z_IS_743U_EQ_743U(...) \, +#define Z_IS_744_EQ_744(...) \, +#define Z_IS_744U_EQ_744(...) \, +#define Z_IS_744_EQ_744U(...) \, +#define Z_IS_744U_EQ_744U(...) \, +#define Z_IS_745_EQ_745(...) \, +#define Z_IS_745U_EQ_745(...) \, +#define Z_IS_745_EQ_745U(...) \, +#define Z_IS_745U_EQ_745U(...) \, +#define Z_IS_746_EQ_746(...) \, +#define Z_IS_746U_EQ_746(...) \, +#define Z_IS_746_EQ_746U(...) \, +#define Z_IS_746U_EQ_746U(...) \, +#define Z_IS_747_EQ_747(...) \, +#define Z_IS_747U_EQ_747(...) \, +#define Z_IS_747_EQ_747U(...) \, +#define Z_IS_747U_EQ_747U(...) \, +#define Z_IS_748_EQ_748(...) \, +#define Z_IS_748U_EQ_748(...) \, +#define Z_IS_748_EQ_748U(...) \, +#define Z_IS_748U_EQ_748U(...) \, +#define Z_IS_749_EQ_749(...) \, +#define Z_IS_749U_EQ_749(...) \, +#define Z_IS_749_EQ_749U(...) \, +#define Z_IS_749U_EQ_749U(...) \, +#define Z_IS_750_EQ_750(...) \, +#define Z_IS_750U_EQ_750(...) \, +#define Z_IS_750_EQ_750U(...) \, +#define Z_IS_750U_EQ_750U(...) \, +#define Z_IS_751_EQ_751(...) \, +#define Z_IS_751U_EQ_751(...) \, +#define Z_IS_751_EQ_751U(...) \, +#define Z_IS_751U_EQ_751U(...) \, +#define Z_IS_752_EQ_752(...) \, +#define Z_IS_752U_EQ_752(...) \, +#define Z_IS_752_EQ_752U(...) \, +#define Z_IS_752U_EQ_752U(...) \, +#define Z_IS_753_EQ_753(...) \, +#define Z_IS_753U_EQ_753(...) \, +#define Z_IS_753_EQ_753U(...) \, +#define Z_IS_753U_EQ_753U(...) \, +#define Z_IS_754_EQ_754(...) \, +#define Z_IS_754U_EQ_754(...) \, +#define Z_IS_754_EQ_754U(...) \, +#define Z_IS_754U_EQ_754U(...) \, +#define Z_IS_755_EQ_755(...) \, +#define Z_IS_755U_EQ_755(...) \, +#define Z_IS_755_EQ_755U(...) \, +#define Z_IS_755U_EQ_755U(...) \, +#define Z_IS_756_EQ_756(...) \, +#define Z_IS_756U_EQ_756(...) \, +#define Z_IS_756_EQ_756U(...) \, +#define Z_IS_756U_EQ_756U(...) \, +#define Z_IS_757_EQ_757(...) \, +#define Z_IS_757U_EQ_757(...) \, +#define Z_IS_757_EQ_757U(...) \, +#define Z_IS_757U_EQ_757U(...) \, +#define Z_IS_758_EQ_758(...) \, +#define Z_IS_758U_EQ_758(...) \, +#define Z_IS_758_EQ_758U(...) \, +#define Z_IS_758U_EQ_758U(...) \, +#define Z_IS_759_EQ_759(...) \, +#define Z_IS_759U_EQ_759(...) \, +#define Z_IS_759_EQ_759U(...) \, +#define Z_IS_759U_EQ_759U(...) \, +#define Z_IS_760_EQ_760(...) \, +#define Z_IS_760U_EQ_760(...) \, +#define Z_IS_760_EQ_760U(...) \, +#define Z_IS_760U_EQ_760U(...) \, +#define Z_IS_761_EQ_761(...) \, +#define Z_IS_761U_EQ_761(...) \, +#define Z_IS_761_EQ_761U(...) \, +#define Z_IS_761U_EQ_761U(...) \, +#define Z_IS_762_EQ_762(...) \, +#define Z_IS_762U_EQ_762(...) \, +#define Z_IS_762_EQ_762U(...) \, +#define Z_IS_762U_EQ_762U(...) \, +#define Z_IS_763_EQ_763(...) \, +#define Z_IS_763U_EQ_763(...) \, +#define Z_IS_763_EQ_763U(...) \, +#define Z_IS_763U_EQ_763U(...) \, +#define Z_IS_764_EQ_764(...) \, +#define Z_IS_764U_EQ_764(...) \, +#define Z_IS_764_EQ_764U(...) \, +#define Z_IS_764U_EQ_764U(...) \, +#define Z_IS_765_EQ_765(...) \, +#define Z_IS_765U_EQ_765(...) \, +#define Z_IS_765_EQ_765U(...) \, +#define Z_IS_765U_EQ_765U(...) \, +#define Z_IS_766_EQ_766(...) \, +#define Z_IS_766U_EQ_766(...) \, +#define Z_IS_766_EQ_766U(...) \, +#define Z_IS_766U_EQ_766U(...) \, +#define Z_IS_767_EQ_767(...) \, +#define Z_IS_767U_EQ_767(...) \, +#define Z_IS_767_EQ_767U(...) \, +#define Z_IS_767U_EQ_767U(...) \, +#define Z_IS_768_EQ_768(...) \, +#define Z_IS_768U_EQ_768(...) \, +#define Z_IS_768_EQ_768U(...) \, +#define Z_IS_768U_EQ_768U(...) \, +#define Z_IS_769_EQ_769(...) \, +#define Z_IS_769U_EQ_769(...) \, +#define Z_IS_769_EQ_769U(...) \, +#define Z_IS_769U_EQ_769U(...) \, +#define Z_IS_770_EQ_770(...) \, +#define Z_IS_770U_EQ_770(...) \, +#define Z_IS_770_EQ_770U(...) \, +#define Z_IS_770U_EQ_770U(...) \, +#define Z_IS_771_EQ_771(...) \, +#define Z_IS_771U_EQ_771(...) \, +#define Z_IS_771_EQ_771U(...) \, +#define Z_IS_771U_EQ_771U(...) \, +#define Z_IS_772_EQ_772(...) \, +#define Z_IS_772U_EQ_772(...) \, +#define Z_IS_772_EQ_772U(...) \, +#define Z_IS_772U_EQ_772U(...) \, +#define Z_IS_773_EQ_773(...) \, +#define Z_IS_773U_EQ_773(...) \, +#define Z_IS_773_EQ_773U(...) \, +#define Z_IS_773U_EQ_773U(...) \, +#define Z_IS_774_EQ_774(...) \, +#define Z_IS_774U_EQ_774(...) \, +#define Z_IS_774_EQ_774U(...) \, +#define Z_IS_774U_EQ_774U(...) \, +#define Z_IS_775_EQ_775(...) \, +#define Z_IS_775U_EQ_775(...) \, +#define Z_IS_775_EQ_775U(...) \, +#define Z_IS_775U_EQ_775U(...) \, +#define Z_IS_776_EQ_776(...) \, +#define Z_IS_776U_EQ_776(...) \, +#define Z_IS_776_EQ_776U(...) \, +#define Z_IS_776U_EQ_776U(...) \, +#define Z_IS_777_EQ_777(...) \, +#define Z_IS_777U_EQ_777(...) \, +#define Z_IS_777_EQ_777U(...) \, +#define Z_IS_777U_EQ_777U(...) \, +#define Z_IS_778_EQ_778(...) \, +#define Z_IS_778U_EQ_778(...) \, +#define Z_IS_778_EQ_778U(...) \, +#define Z_IS_778U_EQ_778U(...) \, +#define Z_IS_779_EQ_779(...) \, +#define Z_IS_779U_EQ_779(...) \, +#define Z_IS_779_EQ_779U(...) \, +#define Z_IS_779U_EQ_779U(...) \, +#define Z_IS_780_EQ_780(...) \, +#define Z_IS_780U_EQ_780(...) \, +#define Z_IS_780_EQ_780U(...) \, +#define Z_IS_780U_EQ_780U(...) \, +#define Z_IS_781_EQ_781(...) \, +#define Z_IS_781U_EQ_781(...) \, +#define Z_IS_781_EQ_781U(...) \, +#define Z_IS_781U_EQ_781U(...) \, +#define Z_IS_782_EQ_782(...) \, +#define Z_IS_782U_EQ_782(...) \, +#define Z_IS_782_EQ_782U(...) \, +#define Z_IS_782U_EQ_782U(...) \, +#define Z_IS_783_EQ_783(...) \, +#define Z_IS_783U_EQ_783(...) \, +#define Z_IS_783_EQ_783U(...) \, +#define Z_IS_783U_EQ_783U(...) \, +#define Z_IS_784_EQ_784(...) \, +#define Z_IS_784U_EQ_784(...) \, +#define Z_IS_784_EQ_784U(...) \, +#define Z_IS_784U_EQ_784U(...) \, +#define Z_IS_785_EQ_785(...) \, +#define Z_IS_785U_EQ_785(...) \, +#define Z_IS_785_EQ_785U(...) \, +#define Z_IS_785U_EQ_785U(...) \, +#define Z_IS_786_EQ_786(...) \, +#define Z_IS_786U_EQ_786(...) \, +#define Z_IS_786_EQ_786U(...) \, +#define Z_IS_786U_EQ_786U(...) \, +#define Z_IS_787_EQ_787(...) \, +#define Z_IS_787U_EQ_787(...) \, +#define Z_IS_787_EQ_787U(...) \, +#define Z_IS_787U_EQ_787U(...) \, +#define Z_IS_788_EQ_788(...) \, +#define Z_IS_788U_EQ_788(...) \, +#define Z_IS_788_EQ_788U(...) \, +#define Z_IS_788U_EQ_788U(...) \, +#define Z_IS_789_EQ_789(...) \, +#define Z_IS_789U_EQ_789(...) \, +#define Z_IS_789_EQ_789U(...) \, +#define Z_IS_789U_EQ_789U(...) \, +#define Z_IS_790_EQ_790(...) \, +#define Z_IS_790U_EQ_790(...) \, +#define Z_IS_790_EQ_790U(...) \, +#define Z_IS_790U_EQ_790U(...) \, +#define Z_IS_791_EQ_791(...) \, +#define Z_IS_791U_EQ_791(...) \, +#define Z_IS_791_EQ_791U(...) \, +#define Z_IS_791U_EQ_791U(...) \, +#define Z_IS_792_EQ_792(...) \, +#define Z_IS_792U_EQ_792(...) \, +#define Z_IS_792_EQ_792U(...) \, +#define Z_IS_792U_EQ_792U(...) \, +#define Z_IS_793_EQ_793(...) \, +#define Z_IS_793U_EQ_793(...) \, +#define Z_IS_793_EQ_793U(...) \, +#define Z_IS_793U_EQ_793U(...) \, +#define Z_IS_794_EQ_794(...) \, +#define Z_IS_794U_EQ_794(...) \, +#define Z_IS_794_EQ_794U(...) \, +#define Z_IS_794U_EQ_794U(...) \, +#define Z_IS_795_EQ_795(...) \, +#define Z_IS_795U_EQ_795(...) \, +#define Z_IS_795_EQ_795U(...) \, +#define Z_IS_795U_EQ_795U(...) \, +#define Z_IS_796_EQ_796(...) \, +#define Z_IS_796U_EQ_796(...) \, +#define Z_IS_796_EQ_796U(...) \, +#define Z_IS_796U_EQ_796U(...) \, +#define Z_IS_797_EQ_797(...) \, +#define Z_IS_797U_EQ_797(...) \, +#define Z_IS_797_EQ_797U(...) \, +#define Z_IS_797U_EQ_797U(...) \, +#define Z_IS_798_EQ_798(...) \, +#define Z_IS_798U_EQ_798(...) \, +#define Z_IS_798_EQ_798U(...) \, +#define Z_IS_798U_EQ_798U(...) \, +#define Z_IS_799_EQ_799(...) \, +#define Z_IS_799U_EQ_799(...) \, +#define Z_IS_799_EQ_799U(...) \, +#define Z_IS_799U_EQ_799U(...) \, +#define Z_IS_800_EQ_800(...) \, +#define Z_IS_800U_EQ_800(...) \, +#define Z_IS_800_EQ_800U(...) \, +#define Z_IS_800U_EQ_800U(...) \, +#define Z_IS_801_EQ_801(...) \, +#define Z_IS_801U_EQ_801(...) \, +#define Z_IS_801_EQ_801U(...) \, +#define Z_IS_801U_EQ_801U(...) \, +#define Z_IS_802_EQ_802(...) \, +#define Z_IS_802U_EQ_802(...) \, +#define Z_IS_802_EQ_802U(...) \, +#define Z_IS_802U_EQ_802U(...) \, +#define Z_IS_803_EQ_803(...) \, +#define Z_IS_803U_EQ_803(...) \, +#define Z_IS_803_EQ_803U(...) \, +#define Z_IS_803U_EQ_803U(...) \, +#define Z_IS_804_EQ_804(...) \, +#define Z_IS_804U_EQ_804(...) \, +#define Z_IS_804_EQ_804U(...) \, +#define Z_IS_804U_EQ_804U(...) \, +#define Z_IS_805_EQ_805(...) \, +#define Z_IS_805U_EQ_805(...) \, +#define Z_IS_805_EQ_805U(...) \, +#define Z_IS_805U_EQ_805U(...) \, +#define Z_IS_806_EQ_806(...) \, +#define Z_IS_806U_EQ_806(...) \, +#define Z_IS_806_EQ_806U(...) \, +#define Z_IS_806U_EQ_806U(...) \, +#define Z_IS_807_EQ_807(...) \, +#define Z_IS_807U_EQ_807(...) \, +#define Z_IS_807_EQ_807U(...) \, +#define Z_IS_807U_EQ_807U(...) \, +#define Z_IS_808_EQ_808(...) \, +#define Z_IS_808U_EQ_808(...) \, +#define Z_IS_808_EQ_808U(...) \, +#define Z_IS_808U_EQ_808U(...) \, +#define Z_IS_809_EQ_809(...) \, +#define Z_IS_809U_EQ_809(...) \, +#define Z_IS_809_EQ_809U(...) \, +#define Z_IS_809U_EQ_809U(...) \, +#define Z_IS_810_EQ_810(...) \, +#define Z_IS_810U_EQ_810(...) \, +#define Z_IS_810_EQ_810U(...) \, +#define Z_IS_810U_EQ_810U(...) \, +#define Z_IS_811_EQ_811(...) \, +#define Z_IS_811U_EQ_811(...) \, +#define Z_IS_811_EQ_811U(...) \, +#define Z_IS_811U_EQ_811U(...) \, +#define Z_IS_812_EQ_812(...) \, +#define Z_IS_812U_EQ_812(...) \, +#define Z_IS_812_EQ_812U(...) \, +#define Z_IS_812U_EQ_812U(...) \, +#define Z_IS_813_EQ_813(...) \, +#define Z_IS_813U_EQ_813(...) \, +#define Z_IS_813_EQ_813U(...) \, +#define Z_IS_813U_EQ_813U(...) \, +#define Z_IS_814_EQ_814(...) \, +#define Z_IS_814U_EQ_814(...) \, +#define Z_IS_814_EQ_814U(...) \, +#define Z_IS_814U_EQ_814U(...) \, +#define Z_IS_815_EQ_815(...) \, +#define Z_IS_815U_EQ_815(...) \, +#define Z_IS_815_EQ_815U(...) \, +#define Z_IS_815U_EQ_815U(...) \, +#define Z_IS_816_EQ_816(...) \, +#define Z_IS_816U_EQ_816(...) \, +#define Z_IS_816_EQ_816U(...) \, +#define Z_IS_816U_EQ_816U(...) \, +#define Z_IS_817_EQ_817(...) \, +#define Z_IS_817U_EQ_817(...) \, +#define Z_IS_817_EQ_817U(...) \, +#define Z_IS_817U_EQ_817U(...) \, +#define Z_IS_818_EQ_818(...) \, +#define Z_IS_818U_EQ_818(...) \, +#define Z_IS_818_EQ_818U(...) \, +#define Z_IS_818U_EQ_818U(...) \, +#define Z_IS_819_EQ_819(...) \, +#define Z_IS_819U_EQ_819(...) \, +#define Z_IS_819_EQ_819U(...) \, +#define Z_IS_819U_EQ_819U(...) \, +#define Z_IS_820_EQ_820(...) \, +#define Z_IS_820U_EQ_820(...) \, +#define Z_IS_820_EQ_820U(...) \, +#define Z_IS_820U_EQ_820U(...) \, +#define Z_IS_821_EQ_821(...) \, +#define Z_IS_821U_EQ_821(...) \, +#define Z_IS_821_EQ_821U(...) \, +#define Z_IS_821U_EQ_821U(...) \, +#define Z_IS_822_EQ_822(...) \, +#define Z_IS_822U_EQ_822(...) \, +#define Z_IS_822_EQ_822U(...) \, +#define Z_IS_822U_EQ_822U(...) \, +#define Z_IS_823_EQ_823(...) \, +#define Z_IS_823U_EQ_823(...) \, +#define Z_IS_823_EQ_823U(...) \, +#define Z_IS_823U_EQ_823U(...) \, +#define Z_IS_824_EQ_824(...) \, +#define Z_IS_824U_EQ_824(...) \, +#define Z_IS_824_EQ_824U(...) \, +#define Z_IS_824U_EQ_824U(...) \, +#define Z_IS_825_EQ_825(...) \, +#define Z_IS_825U_EQ_825(...) \, +#define Z_IS_825_EQ_825U(...) \, +#define Z_IS_825U_EQ_825U(...) \, +#define Z_IS_826_EQ_826(...) \, +#define Z_IS_826U_EQ_826(...) \, +#define Z_IS_826_EQ_826U(...) \, +#define Z_IS_826U_EQ_826U(...) \, +#define Z_IS_827_EQ_827(...) \, +#define Z_IS_827U_EQ_827(...) \, +#define Z_IS_827_EQ_827U(...) \, +#define Z_IS_827U_EQ_827U(...) \, +#define Z_IS_828_EQ_828(...) \, +#define Z_IS_828U_EQ_828(...) \, +#define Z_IS_828_EQ_828U(...) \, +#define Z_IS_828U_EQ_828U(...) \, +#define Z_IS_829_EQ_829(...) \, +#define Z_IS_829U_EQ_829(...) \, +#define Z_IS_829_EQ_829U(...) \, +#define Z_IS_829U_EQ_829U(...) \, +#define Z_IS_830_EQ_830(...) \, +#define Z_IS_830U_EQ_830(...) \, +#define Z_IS_830_EQ_830U(...) \, +#define Z_IS_830U_EQ_830U(...) \, +#define Z_IS_831_EQ_831(...) \, +#define Z_IS_831U_EQ_831(...) \, +#define Z_IS_831_EQ_831U(...) \, +#define Z_IS_831U_EQ_831U(...) \, +#define Z_IS_832_EQ_832(...) \, +#define Z_IS_832U_EQ_832(...) \, +#define Z_IS_832_EQ_832U(...) \, +#define Z_IS_832U_EQ_832U(...) \, +#define Z_IS_833_EQ_833(...) \, +#define Z_IS_833U_EQ_833(...) \, +#define Z_IS_833_EQ_833U(...) \, +#define Z_IS_833U_EQ_833U(...) \, +#define Z_IS_834_EQ_834(...) \, +#define Z_IS_834U_EQ_834(...) \, +#define Z_IS_834_EQ_834U(...) \, +#define Z_IS_834U_EQ_834U(...) \, +#define Z_IS_835_EQ_835(...) \, +#define Z_IS_835U_EQ_835(...) \, +#define Z_IS_835_EQ_835U(...) \, +#define Z_IS_835U_EQ_835U(...) \, +#define Z_IS_836_EQ_836(...) \, +#define Z_IS_836U_EQ_836(...) \, +#define Z_IS_836_EQ_836U(...) \, +#define Z_IS_836U_EQ_836U(...) \, +#define Z_IS_837_EQ_837(...) \, +#define Z_IS_837U_EQ_837(...) \, +#define Z_IS_837_EQ_837U(...) \, +#define Z_IS_837U_EQ_837U(...) \, +#define Z_IS_838_EQ_838(...) \, +#define Z_IS_838U_EQ_838(...) \, +#define Z_IS_838_EQ_838U(...) \, +#define Z_IS_838U_EQ_838U(...) \, +#define Z_IS_839_EQ_839(...) \, +#define Z_IS_839U_EQ_839(...) \, +#define Z_IS_839_EQ_839U(...) \, +#define Z_IS_839U_EQ_839U(...) \, +#define Z_IS_840_EQ_840(...) \, +#define Z_IS_840U_EQ_840(...) \, +#define Z_IS_840_EQ_840U(...) \, +#define Z_IS_840U_EQ_840U(...) \, +#define Z_IS_841_EQ_841(...) \, +#define Z_IS_841U_EQ_841(...) \, +#define Z_IS_841_EQ_841U(...) \, +#define Z_IS_841U_EQ_841U(...) \, +#define Z_IS_842_EQ_842(...) \, +#define Z_IS_842U_EQ_842(...) \, +#define Z_IS_842_EQ_842U(...) \, +#define Z_IS_842U_EQ_842U(...) \, +#define Z_IS_843_EQ_843(...) \, +#define Z_IS_843U_EQ_843(...) \, +#define Z_IS_843_EQ_843U(...) \, +#define Z_IS_843U_EQ_843U(...) \, +#define Z_IS_844_EQ_844(...) \, +#define Z_IS_844U_EQ_844(...) \, +#define Z_IS_844_EQ_844U(...) \, +#define Z_IS_844U_EQ_844U(...) \, +#define Z_IS_845_EQ_845(...) \, +#define Z_IS_845U_EQ_845(...) \, +#define Z_IS_845_EQ_845U(...) \, +#define Z_IS_845U_EQ_845U(...) \, +#define Z_IS_846_EQ_846(...) \, +#define Z_IS_846U_EQ_846(...) \, +#define Z_IS_846_EQ_846U(...) \, +#define Z_IS_846U_EQ_846U(...) \, +#define Z_IS_847_EQ_847(...) \, +#define Z_IS_847U_EQ_847(...) \, +#define Z_IS_847_EQ_847U(...) \, +#define Z_IS_847U_EQ_847U(...) \, +#define Z_IS_848_EQ_848(...) \, +#define Z_IS_848U_EQ_848(...) \, +#define Z_IS_848_EQ_848U(...) \, +#define Z_IS_848U_EQ_848U(...) \, +#define Z_IS_849_EQ_849(...) \, +#define Z_IS_849U_EQ_849(...) \, +#define Z_IS_849_EQ_849U(...) \, +#define Z_IS_849U_EQ_849U(...) \, +#define Z_IS_850_EQ_850(...) \, +#define Z_IS_850U_EQ_850(...) \, +#define Z_IS_850_EQ_850U(...) \, +#define Z_IS_850U_EQ_850U(...) \, +#define Z_IS_851_EQ_851(...) \, +#define Z_IS_851U_EQ_851(...) \, +#define Z_IS_851_EQ_851U(...) \, +#define Z_IS_851U_EQ_851U(...) \, +#define Z_IS_852_EQ_852(...) \, +#define Z_IS_852U_EQ_852(...) \, +#define Z_IS_852_EQ_852U(...) \, +#define Z_IS_852U_EQ_852U(...) \, +#define Z_IS_853_EQ_853(...) \, +#define Z_IS_853U_EQ_853(...) \, +#define Z_IS_853_EQ_853U(...) \, +#define Z_IS_853U_EQ_853U(...) \, +#define Z_IS_854_EQ_854(...) \, +#define Z_IS_854U_EQ_854(...) \, +#define Z_IS_854_EQ_854U(...) \, +#define Z_IS_854U_EQ_854U(...) \, +#define Z_IS_855_EQ_855(...) \, +#define Z_IS_855U_EQ_855(...) \, +#define Z_IS_855_EQ_855U(...) \, +#define Z_IS_855U_EQ_855U(...) \, +#define Z_IS_856_EQ_856(...) \, +#define Z_IS_856U_EQ_856(...) \, +#define Z_IS_856_EQ_856U(...) \, +#define Z_IS_856U_EQ_856U(...) \, +#define Z_IS_857_EQ_857(...) \, +#define Z_IS_857U_EQ_857(...) \, +#define Z_IS_857_EQ_857U(...) \, +#define Z_IS_857U_EQ_857U(...) \, +#define Z_IS_858_EQ_858(...) \, +#define Z_IS_858U_EQ_858(...) \, +#define Z_IS_858_EQ_858U(...) \, +#define Z_IS_858U_EQ_858U(...) \, +#define Z_IS_859_EQ_859(...) \, +#define Z_IS_859U_EQ_859(...) \, +#define Z_IS_859_EQ_859U(...) \, +#define Z_IS_859U_EQ_859U(...) \, +#define Z_IS_860_EQ_860(...) \, +#define Z_IS_860U_EQ_860(...) \, +#define Z_IS_860_EQ_860U(...) \, +#define Z_IS_860U_EQ_860U(...) \, +#define Z_IS_861_EQ_861(...) \, +#define Z_IS_861U_EQ_861(...) \, +#define Z_IS_861_EQ_861U(...) \, +#define Z_IS_861U_EQ_861U(...) \, +#define Z_IS_862_EQ_862(...) \, +#define Z_IS_862U_EQ_862(...) \, +#define Z_IS_862_EQ_862U(...) \, +#define Z_IS_862U_EQ_862U(...) \, +#define Z_IS_863_EQ_863(...) \, +#define Z_IS_863U_EQ_863(...) \, +#define Z_IS_863_EQ_863U(...) \, +#define Z_IS_863U_EQ_863U(...) \, +#define Z_IS_864_EQ_864(...) \, +#define Z_IS_864U_EQ_864(...) \, +#define Z_IS_864_EQ_864U(...) \, +#define Z_IS_864U_EQ_864U(...) \, +#define Z_IS_865_EQ_865(...) \, +#define Z_IS_865U_EQ_865(...) \, +#define Z_IS_865_EQ_865U(...) \, +#define Z_IS_865U_EQ_865U(...) \, +#define Z_IS_866_EQ_866(...) \, +#define Z_IS_866U_EQ_866(...) \, +#define Z_IS_866_EQ_866U(...) \, +#define Z_IS_866U_EQ_866U(...) \, +#define Z_IS_867_EQ_867(...) \, +#define Z_IS_867U_EQ_867(...) \, +#define Z_IS_867_EQ_867U(...) \, +#define Z_IS_867U_EQ_867U(...) \, +#define Z_IS_868_EQ_868(...) \, +#define Z_IS_868U_EQ_868(...) \, +#define Z_IS_868_EQ_868U(...) \, +#define Z_IS_868U_EQ_868U(...) \, +#define Z_IS_869_EQ_869(...) \, +#define Z_IS_869U_EQ_869(...) \, +#define Z_IS_869_EQ_869U(...) \, +#define Z_IS_869U_EQ_869U(...) \, +#define Z_IS_870_EQ_870(...) \, +#define Z_IS_870U_EQ_870(...) \, +#define Z_IS_870_EQ_870U(...) \, +#define Z_IS_870U_EQ_870U(...) \, +#define Z_IS_871_EQ_871(...) \, +#define Z_IS_871U_EQ_871(...) \, +#define Z_IS_871_EQ_871U(...) \, +#define Z_IS_871U_EQ_871U(...) \, +#define Z_IS_872_EQ_872(...) \, +#define Z_IS_872U_EQ_872(...) \, +#define Z_IS_872_EQ_872U(...) \, +#define Z_IS_872U_EQ_872U(...) \, +#define Z_IS_873_EQ_873(...) \, +#define Z_IS_873U_EQ_873(...) \, +#define Z_IS_873_EQ_873U(...) \, +#define Z_IS_873U_EQ_873U(...) \, +#define Z_IS_874_EQ_874(...) \, +#define Z_IS_874U_EQ_874(...) \, +#define Z_IS_874_EQ_874U(...) \, +#define Z_IS_874U_EQ_874U(...) \, +#define Z_IS_875_EQ_875(...) \, +#define Z_IS_875U_EQ_875(...) \, +#define Z_IS_875_EQ_875U(...) \, +#define Z_IS_875U_EQ_875U(...) \, +#define Z_IS_876_EQ_876(...) \, +#define Z_IS_876U_EQ_876(...) \, +#define Z_IS_876_EQ_876U(...) \, +#define Z_IS_876U_EQ_876U(...) \, +#define Z_IS_877_EQ_877(...) \, +#define Z_IS_877U_EQ_877(...) \, +#define Z_IS_877_EQ_877U(...) \, +#define Z_IS_877U_EQ_877U(...) \, +#define Z_IS_878_EQ_878(...) \, +#define Z_IS_878U_EQ_878(...) \, +#define Z_IS_878_EQ_878U(...) \, +#define Z_IS_878U_EQ_878U(...) \, +#define Z_IS_879_EQ_879(...) \, +#define Z_IS_879U_EQ_879(...) \, +#define Z_IS_879_EQ_879U(...) \, +#define Z_IS_879U_EQ_879U(...) \, +#define Z_IS_880_EQ_880(...) \, +#define Z_IS_880U_EQ_880(...) \, +#define Z_IS_880_EQ_880U(...) \, +#define Z_IS_880U_EQ_880U(...) \, +#define Z_IS_881_EQ_881(...) \, +#define Z_IS_881U_EQ_881(...) \, +#define Z_IS_881_EQ_881U(...) \, +#define Z_IS_881U_EQ_881U(...) \, +#define Z_IS_882_EQ_882(...) \, +#define Z_IS_882U_EQ_882(...) \, +#define Z_IS_882_EQ_882U(...) \, +#define Z_IS_882U_EQ_882U(...) \, +#define Z_IS_883_EQ_883(...) \, +#define Z_IS_883U_EQ_883(...) \, +#define Z_IS_883_EQ_883U(...) \, +#define Z_IS_883U_EQ_883U(...) \, +#define Z_IS_884_EQ_884(...) \, +#define Z_IS_884U_EQ_884(...) \, +#define Z_IS_884_EQ_884U(...) \, +#define Z_IS_884U_EQ_884U(...) \, +#define Z_IS_885_EQ_885(...) \, +#define Z_IS_885U_EQ_885(...) \, +#define Z_IS_885_EQ_885U(...) \, +#define Z_IS_885U_EQ_885U(...) \, +#define Z_IS_886_EQ_886(...) \, +#define Z_IS_886U_EQ_886(...) \, +#define Z_IS_886_EQ_886U(...) \, +#define Z_IS_886U_EQ_886U(...) \, +#define Z_IS_887_EQ_887(...) \, +#define Z_IS_887U_EQ_887(...) \, +#define Z_IS_887_EQ_887U(...) \, +#define Z_IS_887U_EQ_887U(...) \, +#define Z_IS_888_EQ_888(...) \, +#define Z_IS_888U_EQ_888(...) \, +#define Z_IS_888_EQ_888U(...) \, +#define Z_IS_888U_EQ_888U(...) \, +#define Z_IS_889_EQ_889(...) \, +#define Z_IS_889U_EQ_889(...) \, +#define Z_IS_889_EQ_889U(...) \, +#define Z_IS_889U_EQ_889U(...) \, +#define Z_IS_890_EQ_890(...) \, +#define Z_IS_890U_EQ_890(...) \, +#define Z_IS_890_EQ_890U(...) \, +#define Z_IS_890U_EQ_890U(...) \, +#define Z_IS_891_EQ_891(...) \, +#define Z_IS_891U_EQ_891(...) \, +#define Z_IS_891_EQ_891U(...) \, +#define Z_IS_891U_EQ_891U(...) \, +#define Z_IS_892_EQ_892(...) \, +#define Z_IS_892U_EQ_892(...) \, +#define Z_IS_892_EQ_892U(...) \, +#define Z_IS_892U_EQ_892U(...) \, +#define Z_IS_893_EQ_893(...) \, +#define Z_IS_893U_EQ_893(...) \, +#define Z_IS_893_EQ_893U(...) \, +#define Z_IS_893U_EQ_893U(...) \, +#define Z_IS_894_EQ_894(...) \, +#define Z_IS_894U_EQ_894(...) \, +#define Z_IS_894_EQ_894U(...) \, +#define Z_IS_894U_EQ_894U(...) \, +#define Z_IS_895_EQ_895(...) \, +#define Z_IS_895U_EQ_895(...) \, +#define Z_IS_895_EQ_895U(...) \, +#define Z_IS_895U_EQ_895U(...) \, +#define Z_IS_896_EQ_896(...) \, +#define Z_IS_896U_EQ_896(...) \, +#define Z_IS_896_EQ_896U(...) \, +#define Z_IS_896U_EQ_896U(...) \, +#define Z_IS_897_EQ_897(...) \, +#define Z_IS_897U_EQ_897(...) \, +#define Z_IS_897_EQ_897U(...) \, +#define Z_IS_897U_EQ_897U(...) \, +#define Z_IS_898_EQ_898(...) \, +#define Z_IS_898U_EQ_898(...) \, +#define Z_IS_898_EQ_898U(...) \, +#define Z_IS_898U_EQ_898U(...) \, +#define Z_IS_899_EQ_899(...) \, +#define Z_IS_899U_EQ_899(...) \, +#define Z_IS_899_EQ_899U(...) \, +#define Z_IS_899U_EQ_899U(...) \, +#define Z_IS_900_EQ_900(...) \, +#define Z_IS_900U_EQ_900(...) \, +#define Z_IS_900_EQ_900U(...) \, +#define Z_IS_900U_EQ_900U(...) \, +#define Z_IS_901_EQ_901(...) \, +#define Z_IS_901U_EQ_901(...) \, +#define Z_IS_901_EQ_901U(...) \, +#define Z_IS_901U_EQ_901U(...) \, +#define Z_IS_902_EQ_902(...) \, +#define Z_IS_902U_EQ_902(...) \, +#define Z_IS_902_EQ_902U(...) \, +#define Z_IS_902U_EQ_902U(...) \, +#define Z_IS_903_EQ_903(...) \, +#define Z_IS_903U_EQ_903(...) \, +#define Z_IS_903_EQ_903U(...) \, +#define Z_IS_903U_EQ_903U(...) \, +#define Z_IS_904_EQ_904(...) \, +#define Z_IS_904U_EQ_904(...) \, +#define Z_IS_904_EQ_904U(...) \, +#define Z_IS_904U_EQ_904U(...) \, +#define Z_IS_905_EQ_905(...) \, +#define Z_IS_905U_EQ_905(...) \, +#define Z_IS_905_EQ_905U(...) \, +#define Z_IS_905U_EQ_905U(...) \, +#define Z_IS_906_EQ_906(...) \, +#define Z_IS_906U_EQ_906(...) \, +#define Z_IS_906_EQ_906U(...) \, +#define Z_IS_906U_EQ_906U(...) \, +#define Z_IS_907_EQ_907(...) \, +#define Z_IS_907U_EQ_907(...) \, +#define Z_IS_907_EQ_907U(...) \, +#define Z_IS_907U_EQ_907U(...) \, +#define Z_IS_908_EQ_908(...) \, +#define Z_IS_908U_EQ_908(...) \, +#define Z_IS_908_EQ_908U(...) \, +#define Z_IS_908U_EQ_908U(...) \, +#define Z_IS_909_EQ_909(...) \, +#define Z_IS_909U_EQ_909(...) \, +#define Z_IS_909_EQ_909U(...) \, +#define Z_IS_909U_EQ_909U(...) \, +#define Z_IS_910_EQ_910(...) \, +#define Z_IS_910U_EQ_910(...) \, +#define Z_IS_910_EQ_910U(...) \, +#define Z_IS_910U_EQ_910U(...) \, +#define Z_IS_911_EQ_911(...) \, +#define Z_IS_911U_EQ_911(...) \, +#define Z_IS_911_EQ_911U(...) \, +#define Z_IS_911U_EQ_911U(...) \, +#define Z_IS_912_EQ_912(...) \, +#define Z_IS_912U_EQ_912(...) \, +#define Z_IS_912_EQ_912U(...) \, +#define Z_IS_912U_EQ_912U(...) \, +#define Z_IS_913_EQ_913(...) \, +#define Z_IS_913U_EQ_913(...) \, +#define Z_IS_913_EQ_913U(...) \, +#define Z_IS_913U_EQ_913U(...) \, +#define Z_IS_914_EQ_914(...) \, +#define Z_IS_914U_EQ_914(...) \, +#define Z_IS_914_EQ_914U(...) \, +#define Z_IS_914U_EQ_914U(...) \, +#define Z_IS_915_EQ_915(...) \, +#define Z_IS_915U_EQ_915(...) \, +#define Z_IS_915_EQ_915U(...) \, +#define Z_IS_915U_EQ_915U(...) \, +#define Z_IS_916_EQ_916(...) \, +#define Z_IS_916U_EQ_916(...) \, +#define Z_IS_916_EQ_916U(...) \, +#define Z_IS_916U_EQ_916U(...) \, +#define Z_IS_917_EQ_917(...) \, +#define Z_IS_917U_EQ_917(...) \, +#define Z_IS_917_EQ_917U(...) \, +#define Z_IS_917U_EQ_917U(...) \, +#define Z_IS_918_EQ_918(...) \, +#define Z_IS_918U_EQ_918(...) \, +#define Z_IS_918_EQ_918U(...) \, +#define Z_IS_918U_EQ_918U(...) \, +#define Z_IS_919_EQ_919(...) \, +#define Z_IS_919U_EQ_919(...) \, +#define Z_IS_919_EQ_919U(...) \, +#define Z_IS_919U_EQ_919U(...) \, +#define Z_IS_920_EQ_920(...) \, +#define Z_IS_920U_EQ_920(...) \, +#define Z_IS_920_EQ_920U(...) \, +#define Z_IS_920U_EQ_920U(...) \, +#define Z_IS_921_EQ_921(...) \, +#define Z_IS_921U_EQ_921(...) \, +#define Z_IS_921_EQ_921U(...) \, +#define Z_IS_921U_EQ_921U(...) \, +#define Z_IS_922_EQ_922(...) \, +#define Z_IS_922U_EQ_922(...) \, +#define Z_IS_922_EQ_922U(...) \, +#define Z_IS_922U_EQ_922U(...) \, +#define Z_IS_923_EQ_923(...) \, +#define Z_IS_923U_EQ_923(...) \, +#define Z_IS_923_EQ_923U(...) \, +#define Z_IS_923U_EQ_923U(...) \, +#define Z_IS_924_EQ_924(...) \, +#define Z_IS_924U_EQ_924(...) \, +#define Z_IS_924_EQ_924U(...) \, +#define Z_IS_924U_EQ_924U(...) \, +#define Z_IS_925_EQ_925(...) \, +#define Z_IS_925U_EQ_925(...) \, +#define Z_IS_925_EQ_925U(...) \, +#define Z_IS_925U_EQ_925U(...) \, +#define Z_IS_926_EQ_926(...) \, +#define Z_IS_926U_EQ_926(...) \, +#define Z_IS_926_EQ_926U(...) \, +#define Z_IS_926U_EQ_926U(...) \, +#define Z_IS_927_EQ_927(...) \, +#define Z_IS_927U_EQ_927(...) \, +#define Z_IS_927_EQ_927U(...) \, +#define Z_IS_927U_EQ_927U(...) \, +#define Z_IS_928_EQ_928(...) \, +#define Z_IS_928U_EQ_928(...) \, +#define Z_IS_928_EQ_928U(...) \, +#define Z_IS_928U_EQ_928U(...) \, +#define Z_IS_929_EQ_929(...) \, +#define Z_IS_929U_EQ_929(...) \, +#define Z_IS_929_EQ_929U(...) \, +#define Z_IS_929U_EQ_929U(...) \, +#define Z_IS_930_EQ_930(...) \, +#define Z_IS_930U_EQ_930(...) \, +#define Z_IS_930_EQ_930U(...) \, +#define Z_IS_930U_EQ_930U(...) \, +#define Z_IS_931_EQ_931(...) \, +#define Z_IS_931U_EQ_931(...) \, +#define Z_IS_931_EQ_931U(...) \, +#define Z_IS_931U_EQ_931U(...) \, +#define Z_IS_932_EQ_932(...) \, +#define Z_IS_932U_EQ_932(...) \, +#define Z_IS_932_EQ_932U(...) \, +#define Z_IS_932U_EQ_932U(...) \, +#define Z_IS_933_EQ_933(...) \, +#define Z_IS_933U_EQ_933(...) \, +#define Z_IS_933_EQ_933U(...) \, +#define Z_IS_933U_EQ_933U(...) \, +#define Z_IS_934_EQ_934(...) \, +#define Z_IS_934U_EQ_934(...) \, +#define Z_IS_934_EQ_934U(...) \, +#define Z_IS_934U_EQ_934U(...) \, +#define Z_IS_935_EQ_935(...) \, +#define Z_IS_935U_EQ_935(...) \, +#define Z_IS_935_EQ_935U(...) \, +#define Z_IS_935U_EQ_935U(...) \, +#define Z_IS_936_EQ_936(...) \, +#define Z_IS_936U_EQ_936(...) \, +#define Z_IS_936_EQ_936U(...) \, +#define Z_IS_936U_EQ_936U(...) \, +#define Z_IS_937_EQ_937(...) \, +#define Z_IS_937U_EQ_937(...) \, +#define Z_IS_937_EQ_937U(...) \, +#define Z_IS_937U_EQ_937U(...) \, +#define Z_IS_938_EQ_938(...) \, +#define Z_IS_938U_EQ_938(...) \, +#define Z_IS_938_EQ_938U(...) \, +#define Z_IS_938U_EQ_938U(...) \, +#define Z_IS_939_EQ_939(...) \, +#define Z_IS_939U_EQ_939(...) \, +#define Z_IS_939_EQ_939U(...) \, +#define Z_IS_939U_EQ_939U(...) \, +#define Z_IS_940_EQ_940(...) \, +#define Z_IS_940U_EQ_940(...) \, +#define Z_IS_940_EQ_940U(...) \, +#define Z_IS_940U_EQ_940U(...) \, +#define Z_IS_941_EQ_941(...) \, +#define Z_IS_941U_EQ_941(...) \, +#define Z_IS_941_EQ_941U(...) \, +#define Z_IS_941U_EQ_941U(...) \, +#define Z_IS_942_EQ_942(...) \, +#define Z_IS_942U_EQ_942(...) \, +#define Z_IS_942_EQ_942U(...) \, +#define Z_IS_942U_EQ_942U(...) \, +#define Z_IS_943_EQ_943(...) \, +#define Z_IS_943U_EQ_943(...) \, +#define Z_IS_943_EQ_943U(...) \, +#define Z_IS_943U_EQ_943U(...) \, +#define Z_IS_944_EQ_944(...) \, +#define Z_IS_944U_EQ_944(...) \, +#define Z_IS_944_EQ_944U(...) \, +#define Z_IS_944U_EQ_944U(...) \, +#define Z_IS_945_EQ_945(...) \, +#define Z_IS_945U_EQ_945(...) \, +#define Z_IS_945_EQ_945U(...) \, +#define Z_IS_945U_EQ_945U(...) \, +#define Z_IS_946_EQ_946(...) \, +#define Z_IS_946U_EQ_946(...) \, +#define Z_IS_946_EQ_946U(...) \, +#define Z_IS_946U_EQ_946U(...) \, +#define Z_IS_947_EQ_947(...) \, +#define Z_IS_947U_EQ_947(...) \, +#define Z_IS_947_EQ_947U(...) \, +#define Z_IS_947U_EQ_947U(...) \, +#define Z_IS_948_EQ_948(...) \, +#define Z_IS_948U_EQ_948(...) \, +#define Z_IS_948_EQ_948U(...) \, +#define Z_IS_948U_EQ_948U(...) \, +#define Z_IS_949_EQ_949(...) \, +#define Z_IS_949U_EQ_949(...) \, +#define Z_IS_949_EQ_949U(...) \, +#define Z_IS_949U_EQ_949U(...) \, +#define Z_IS_950_EQ_950(...) \, +#define Z_IS_950U_EQ_950(...) \, +#define Z_IS_950_EQ_950U(...) \, +#define Z_IS_950U_EQ_950U(...) \, +#define Z_IS_951_EQ_951(...) \, +#define Z_IS_951U_EQ_951(...) \, +#define Z_IS_951_EQ_951U(...) \, +#define Z_IS_951U_EQ_951U(...) \, +#define Z_IS_952_EQ_952(...) \, +#define Z_IS_952U_EQ_952(...) \, +#define Z_IS_952_EQ_952U(...) \, +#define Z_IS_952U_EQ_952U(...) \, +#define Z_IS_953_EQ_953(...) \, +#define Z_IS_953U_EQ_953(...) \, +#define Z_IS_953_EQ_953U(...) \, +#define Z_IS_953U_EQ_953U(...) \, +#define Z_IS_954_EQ_954(...) \, +#define Z_IS_954U_EQ_954(...) \, +#define Z_IS_954_EQ_954U(...) \, +#define Z_IS_954U_EQ_954U(...) \, +#define Z_IS_955_EQ_955(...) \, +#define Z_IS_955U_EQ_955(...) \, +#define Z_IS_955_EQ_955U(...) \, +#define Z_IS_955U_EQ_955U(...) \, +#define Z_IS_956_EQ_956(...) \, +#define Z_IS_956U_EQ_956(...) \, +#define Z_IS_956_EQ_956U(...) \, +#define Z_IS_956U_EQ_956U(...) \, +#define Z_IS_957_EQ_957(...) \, +#define Z_IS_957U_EQ_957(...) \, +#define Z_IS_957_EQ_957U(...) \, +#define Z_IS_957U_EQ_957U(...) \, +#define Z_IS_958_EQ_958(...) \, +#define Z_IS_958U_EQ_958(...) \, +#define Z_IS_958_EQ_958U(...) \, +#define Z_IS_958U_EQ_958U(...) \, +#define Z_IS_959_EQ_959(...) \, +#define Z_IS_959U_EQ_959(...) \, +#define Z_IS_959_EQ_959U(...) \, +#define Z_IS_959U_EQ_959U(...) \, +#define Z_IS_960_EQ_960(...) \, +#define Z_IS_960U_EQ_960(...) \, +#define Z_IS_960_EQ_960U(...) \, +#define Z_IS_960U_EQ_960U(...) \, +#define Z_IS_961_EQ_961(...) \, +#define Z_IS_961U_EQ_961(...) \, +#define Z_IS_961_EQ_961U(...) \, +#define Z_IS_961U_EQ_961U(...) \, +#define Z_IS_962_EQ_962(...) \, +#define Z_IS_962U_EQ_962(...) \, +#define Z_IS_962_EQ_962U(...) \, +#define Z_IS_962U_EQ_962U(...) \, +#define Z_IS_963_EQ_963(...) \, +#define Z_IS_963U_EQ_963(...) \, +#define Z_IS_963_EQ_963U(...) \, +#define Z_IS_963U_EQ_963U(...) \, +#define Z_IS_964_EQ_964(...) \, +#define Z_IS_964U_EQ_964(...) \, +#define Z_IS_964_EQ_964U(...) \, +#define Z_IS_964U_EQ_964U(...) \, +#define Z_IS_965_EQ_965(...) \, +#define Z_IS_965U_EQ_965(...) \, +#define Z_IS_965_EQ_965U(...) \, +#define Z_IS_965U_EQ_965U(...) \, +#define Z_IS_966_EQ_966(...) \, +#define Z_IS_966U_EQ_966(...) \, +#define Z_IS_966_EQ_966U(...) \, +#define Z_IS_966U_EQ_966U(...) \, +#define Z_IS_967_EQ_967(...) \, +#define Z_IS_967U_EQ_967(...) \, +#define Z_IS_967_EQ_967U(...) \, +#define Z_IS_967U_EQ_967U(...) \, +#define Z_IS_968_EQ_968(...) \, +#define Z_IS_968U_EQ_968(...) \, +#define Z_IS_968_EQ_968U(...) \, +#define Z_IS_968U_EQ_968U(...) \, +#define Z_IS_969_EQ_969(...) \, +#define Z_IS_969U_EQ_969(...) \, +#define Z_IS_969_EQ_969U(...) \, +#define Z_IS_969U_EQ_969U(...) \, +#define Z_IS_970_EQ_970(...) \, +#define Z_IS_970U_EQ_970(...) \, +#define Z_IS_970_EQ_970U(...) \, +#define Z_IS_970U_EQ_970U(...) \, +#define Z_IS_971_EQ_971(...) \, +#define Z_IS_971U_EQ_971(...) \, +#define Z_IS_971_EQ_971U(...) \, +#define Z_IS_971U_EQ_971U(...) \, +#define Z_IS_972_EQ_972(...) \, +#define Z_IS_972U_EQ_972(...) \, +#define Z_IS_972_EQ_972U(...) \, +#define Z_IS_972U_EQ_972U(...) \, +#define Z_IS_973_EQ_973(...) \, +#define Z_IS_973U_EQ_973(...) \, +#define Z_IS_973_EQ_973U(...) \, +#define Z_IS_973U_EQ_973U(...) \, +#define Z_IS_974_EQ_974(...) \, +#define Z_IS_974U_EQ_974(...) \, +#define Z_IS_974_EQ_974U(...) \, +#define Z_IS_974U_EQ_974U(...) \, +#define Z_IS_975_EQ_975(...) \, +#define Z_IS_975U_EQ_975(...) \, +#define Z_IS_975_EQ_975U(...) \, +#define Z_IS_975U_EQ_975U(...) \, +#define Z_IS_976_EQ_976(...) \, +#define Z_IS_976U_EQ_976(...) \, +#define Z_IS_976_EQ_976U(...) \, +#define Z_IS_976U_EQ_976U(...) \, +#define Z_IS_977_EQ_977(...) \, +#define Z_IS_977U_EQ_977(...) \, +#define Z_IS_977_EQ_977U(...) \, +#define Z_IS_977U_EQ_977U(...) \, +#define Z_IS_978_EQ_978(...) \, +#define Z_IS_978U_EQ_978(...) \, +#define Z_IS_978_EQ_978U(...) \, +#define Z_IS_978U_EQ_978U(...) \, +#define Z_IS_979_EQ_979(...) \, +#define Z_IS_979U_EQ_979(...) \, +#define Z_IS_979_EQ_979U(...) \, +#define Z_IS_979U_EQ_979U(...) \, +#define Z_IS_980_EQ_980(...) \, +#define Z_IS_980U_EQ_980(...) \, +#define Z_IS_980_EQ_980U(...) \, +#define Z_IS_980U_EQ_980U(...) \, +#define Z_IS_981_EQ_981(...) \, +#define Z_IS_981U_EQ_981(...) \, +#define Z_IS_981_EQ_981U(...) \, +#define Z_IS_981U_EQ_981U(...) \, +#define Z_IS_982_EQ_982(...) \, +#define Z_IS_982U_EQ_982(...) \, +#define Z_IS_982_EQ_982U(...) \, +#define Z_IS_982U_EQ_982U(...) \, +#define Z_IS_983_EQ_983(...) \, +#define Z_IS_983U_EQ_983(...) \, +#define Z_IS_983_EQ_983U(...) \, +#define Z_IS_983U_EQ_983U(...) \, +#define Z_IS_984_EQ_984(...) \, +#define Z_IS_984U_EQ_984(...) \, +#define Z_IS_984_EQ_984U(...) \, +#define Z_IS_984U_EQ_984U(...) \, +#define Z_IS_985_EQ_985(...) \, +#define Z_IS_985U_EQ_985(...) \, +#define Z_IS_985_EQ_985U(...) \, +#define Z_IS_985U_EQ_985U(...) \, +#define Z_IS_986_EQ_986(...) \, +#define Z_IS_986U_EQ_986(...) \, +#define Z_IS_986_EQ_986U(...) \, +#define Z_IS_986U_EQ_986U(...) \, +#define Z_IS_987_EQ_987(...) \, +#define Z_IS_987U_EQ_987(...) \, +#define Z_IS_987_EQ_987U(...) \, +#define Z_IS_987U_EQ_987U(...) \, +#define Z_IS_988_EQ_988(...) \, +#define Z_IS_988U_EQ_988(...) \, +#define Z_IS_988_EQ_988U(...) \, +#define Z_IS_988U_EQ_988U(...) \, +#define Z_IS_989_EQ_989(...) \, +#define Z_IS_989U_EQ_989(...) \, +#define Z_IS_989_EQ_989U(...) \, +#define Z_IS_989U_EQ_989U(...) \, +#define Z_IS_990_EQ_990(...) \, +#define Z_IS_990U_EQ_990(...) \, +#define Z_IS_990_EQ_990U(...) \, +#define Z_IS_990U_EQ_990U(...) \, +#define Z_IS_991_EQ_991(...) \, +#define Z_IS_991U_EQ_991(...) \, +#define Z_IS_991_EQ_991U(...) \, +#define Z_IS_991U_EQ_991U(...) \, +#define Z_IS_992_EQ_992(...) \, +#define Z_IS_992U_EQ_992(...) \, +#define Z_IS_992_EQ_992U(...) \, +#define Z_IS_992U_EQ_992U(...) \, +#define Z_IS_993_EQ_993(...) \, +#define Z_IS_993U_EQ_993(...) \, +#define Z_IS_993_EQ_993U(...) \, +#define Z_IS_993U_EQ_993U(...) \, +#define Z_IS_994_EQ_994(...) \, +#define Z_IS_994U_EQ_994(...) \, +#define Z_IS_994_EQ_994U(...) \, +#define Z_IS_994U_EQ_994U(...) \, +#define Z_IS_995_EQ_995(...) \, +#define Z_IS_995U_EQ_995(...) \, +#define Z_IS_995_EQ_995U(...) \, +#define Z_IS_995U_EQ_995U(...) \, +#define Z_IS_996_EQ_996(...) \, +#define Z_IS_996U_EQ_996(...) \, +#define Z_IS_996_EQ_996U(...) \, +#define Z_IS_996U_EQ_996U(...) \, +#define Z_IS_997_EQ_997(...) \, +#define Z_IS_997U_EQ_997(...) \, +#define Z_IS_997_EQ_997U(...) \, +#define Z_IS_997U_EQ_997U(...) \, +#define Z_IS_998_EQ_998(...) \, +#define Z_IS_998U_EQ_998(...) \, +#define Z_IS_998_EQ_998U(...) \, +#define Z_IS_998U_EQ_998U(...) \, +#define Z_IS_999_EQ_999(...) \, +#define Z_IS_999U_EQ_999(...) \, +#define Z_IS_999_EQ_999U(...) \, +#define Z_IS_999U_EQ_999U(...) \, +#define Z_IS_1000_EQ_1000(...) \, +#define Z_IS_1000U_EQ_1000(...) \, +#define Z_IS_1000_EQ_1000U(...) \, +#define Z_IS_1000U_EQ_1000U(...) \, +#define Z_IS_1001_EQ_1001(...) \, +#define Z_IS_1001U_EQ_1001(...) \, +#define Z_IS_1001_EQ_1001U(...) \, +#define Z_IS_1001U_EQ_1001U(...) \, +#define Z_IS_1002_EQ_1002(...) \, +#define Z_IS_1002U_EQ_1002(...) \, +#define Z_IS_1002_EQ_1002U(...) \, +#define Z_IS_1002U_EQ_1002U(...) \, +#define Z_IS_1003_EQ_1003(...) \, +#define Z_IS_1003U_EQ_1003(...) \, +#define Z_IS_1003_EQ_1003U(...) \, +#define Z_IS_1003U_EQ_1003U(...) \, +#define Z_IS_1004_EQ_1004(...) \, +#define Z_IS_1004U_EQ_1004(...) \, +#define Z_IS_1004_EQ_1004U(...) \, +#define Z_IS_1004U_EQ_1004U(...) \, +#define Z_IS_1005_EQ_1005(...) \, +#define Z_IS_1005U_EQ_1005(...) \, +#define Z_IS_1005_EQ_1005U(...) \, +#define Z_IS_1005U_EQ_1005U(...) \, +#define Z_IS_1006_EQ_1006(...) \, +#define Z_IS_1006U_EQ_1006(...) \, +#define Z_IS_1006_EQ_1006U(...) \, +#define Z_IS_1006U_EQ_1006U(...) \, +#define Z_IS_1007_EQ_1007(...) \, +#define Z_IS_1007U_EQ_1007(...) \, +#define Z_IS_1007_EQ_1007U(...) \, +#define Z_IS_1007U_EQ_1007U(...) \, +#define Z_IS_1008_EQ_1008(...) \, +#define Z_IS_1008U_EQ_1008(...) \, +#define Z_IS_1008_EQ_1008U(...) \, +#define Z_IS_1008U_EQ_1008U(...) \, +#define Z_IS_1009_EQ_1009(...) \, +#define Z_IS_1009U_EQ_1009(...) \, +#define Z_IS_1009_EQ_1009U(...) \, +#define Z_IS_1009U_EQ_1009U(...) \, +#define Z_IS_1010_EQ_1010(...) \, +#define Z_IS_1010U_EQ_1010(...) \, +#define Z_IS_1010_EQ_1010U(...) \, +#define Z_IS_1010U_EQ_1010U(...) \, +#define Z_IS_1011_EQ_1011(...) \, +#define Z_IS_1011U_EQ_1011(...) \, +#define Z_IS_1011_EQ_1011U(...) \, +#define Z_IS_1011U_EQ_1011U(...) \, +#define Z_IS_1012_EQ_1012(...) \, +#define Z_IS_1012U_EQ_1012(...) \, +#define Z_IS_1012_EQ_1012U(...) \, +#define Z_IS_1012U_EQ_1012U(...) \, +#define Z_IS_1013_EQ_1013(...) \, +#define Z_IS_1013U_EQ_1013(...) \, +#define Z_IS_1013_EQ_1013U(...) \, +#define Z_IS_1013U_EQ_1013U(...) \, +#define Z_IS_1014_EQ_1014(...) \, +#define Z_IS_1014U_EQ_1014(...) \, +#define Z_IS_1014_EQ_1014U(...) \, +#define Z_IS_1014U_EQ_1014U(...) \, +#define Z_IS_1015_EQ_1015(...) \, +#define Z_IS_1015U_EQ_1015(...) \, +#define Z_IS_1015_EQ_1015U(...) \, +#define Z_IS_1015U_EQ_1015U(...) \, +#define Z_IS_1016_EQ_1016(...) \, +#define Z_IS_1016U_EQ_1016(...) \, +#define Z_IS_1016_EQ_1016U(...) \, +#define Z_IS_1016U_EQ_1016U(...) \, +#define Z_IS_1017_EQ_1017(...) \, +#define Z_IS_1017U_EQ_1017(...) \, +#define Z_IS_1017_EQ_1017U(...) \, +#define Z_IS_1017U_EQ_1017U(...) \, +#define Z_IS_1018_EQ_1018(...) \, +#define Z_IS_1018U_EQ_1018(...) \, +#define Z_IS_1018_EQ_1018U(...) \, +#define Z_IS_1018U_EQ_1018U(...) \, +#define Z_IS_1019_EQ_1019(...) \, +#define Z_IS_1019U_EQ_1019(...) \, +#define Z_IS_1019_EQ_1019U(...) \, +#define Z_IS_1019U_EQ_1019U(...) \, +#define Z_IS_1020_EQ_1020(...) \, +#define Z_IS_1020U_EQ_1020(...) \, +#define Z_IS_1020_EQ_1020U(...) \, +#define Z_IS_1020U_EQ_1020U(...) \, +#define Z_IS_1021_EQ_1021(...) \, +#define Z_IS_1021U_EQ_1021(...) \, +#define Z_IS_1021_EQ_1021U(...) \, +#define Z_IS_1021U_EQ_1021U(...) \, +#define Z_IS_1022_EQ_1022(...) \, +#define Z_IS_1022U_EQ_1022(...) \, +#define Z_IS_1022_EQ_1022U(...) \, +#define Z_IS_1022U_EQ_1022U(...) \, +#define Z_IS_1023_EQ_1023(...) \, +#define Z_IS_1023U_EQ_1023(...) \, +#define Z_IS_1023_EQ_1023U(...) \, +#define Z_IS_1023U_EQ_1023U(...) \, +#define Z_IS_1024_EQ_1024(...) \, +#define Z_IS_1024U_EQ_1024(...) \, +#define Z_IS_1024_EQ_1024U(...) \, +#define Z_IS_1024U_EQ_1024U(...) \, +#define Z_IS_1025_EQ_1025(...) \, +#define Z_IS_1025U_EQ_1025(...) \, +#define Z_IS_1025_EQ_1025U(...) \, +#define Z_IS_1025U_EQ_1025U(...) \, +#define Z_IS_1026_EQ_1026(...) \, +#define Z_IS_1026U_EQ_1026(...) \, +#define Z_IS_1026_EQ_1026U(...) \, +#define Z_IS_1026U_EQ_1026U(...) \, +#define Z_IS_1027_EQ_1027(...) \, +#define Z_IS_1027U_EQ_1027(...) \, +#define Z_IS_1027_EQ_1027U(...) \, +#define Z_IS_1027U_EQ_1027U(...) \, +#define Z_IS_1028_EQ_1028(...) \, +#define Z_IS_1028U_EQ_1028(...) \, +#define Z_IS_1028_EQ_1028U(...) \, +#define Z_IS_1028U_EQ_1028U(...) \, +#define Z_IS_1029_EQ_1029(...) \, +#define Z_IS_1029U_EQ_1029(...) \, +#define Z_IS_1029_EQ_1029U(...) \, +#define Z_IS_1029U_EQ_1029U(...) \, +#define Z_IS_1030_EQ_1030(...) \, +#define Z_IS_1030U_EQ_1030(...) \, +#define Z_IS_1030_EQ_1030U(...) \, +#define Z_IS_1030U_EQ_1030U(...) \, +#define Z_IS_1031_EQ_1031(...) \, +#define Z_IS_1031U_EQ_1031(...) \, +#define Z_IS_1031_EQ_1031U(...) \, +#define Z_IS_1031U_EQ_1031U(...) \, +#define Z_IS_1032_EQ_1032(...) \, +#define Z_IS_1032U_EQ_1032(...) \, +#define Z_IS_1032_EQ_1032U(...) \, +#define Z_IS_1032U_EQ_1032U(...) \, +#define Z_IS_1033_EQ_1033(...) \, +#define Z_IS_1033U_EQ_1033(...) \, +#define Z_IS_1033_EQ_1033U(...) \, +#define Z_IS_1033U_EQ_1033U(...) \, +#define Z_IS_1034_EQ_1034(...) \, +#define Z_IS_1034U_EQ_1034(...) \, +#define Z_IS_1034_EQ_1034U(...) \, +#define Z_IS_1034U_EQ_1034U(...) \, +#define Z_IS_1035_EQ_1035(...) \, +#define Z_IS_1035U_EQ_1035(...) \, +#define Z_IS_1035_EQ_1035U(...) \, +#define Z_IS_1035U_EQ_1035U(...) \, +#define Z_IS_1036_EQ_1036(...) \, +#define Z_IS_1036U_EQ_1036(...) \, +#define Z_IS_1036_EQ_1036U(...) \, +#define Z_IS_1036U_EQ_1036U(...) \, +#define Z_IS_1037_EQ_1037(...) \, +#define Z_IS_1037U_EQ_1037(...) \, +#define Z_IS_1037_EQ_1037U(...) \, +#define Z_IS_1037U_EQ_1037U(...) \, +#define Z_IS_1038_EQ_1038(...) \, +#define Z_IS_1038U_EQ_1038(...) \, +#define Z_IS_1038_EQ_1038U(...) \, +#define Z_IS_1038U_EQ_1038U(...) \, +#define Z_IS_1039_EQ_1039(...) \, +#define Z_IS_1039U_EQ_1039(...) \, +#define Z_IS_1039_EQ_1039U(...) \, +#define Z_IS_1039U_EQ_1039U(...) \, +#define Z_IS_1040_EQ_1040(...) \, +#define Z_IS_1040U_EQ_1040(...) \, +#define Z_IS_1040_EQ_1040U(...) \, +#define Z_IS_1040U_EQ_1040U(...) \, +#define Z_IS_1041_EQ_1041(...) \, +#define Z_IS_1041U_EQ_1041(...) \, +#define Z_IS_1041_EQ_1041U(...) \, +#define Z_IS_1041U_EQ_1041U(...) \, +#define Z_IS_1042_EQ_1042(...) \, +#define Z_IS_1042U_EQ_1042(...) \, +#define Z_IS_1042_EQ_1042U(...) \, +#define Z_IS_1042U_EQ_1042U(...) \, +#define Z_IS_1043_EQ_1043(...) \, +#define Z_IS_1043U_EQ_1043(...) \, +#define Z_IS_1043_EQ_1043U(...) \, +#define Z_IS_1043U_EQ_1043U(...) \, +#define Z_IS_1044_EQ_1044(...) \, +#define Z_IS_1044U_EQ_1044(...) \, +#define Z_IS_1044_EQ_1044U(...) \, +#define Z_IS_1044U_EQ_1044U(...) \, +#define Z_IS_1045_EQ_1045(...) \, +#define Z_IS_1045U_EQ_1045(...) \, +#define Z_IS_1045_EQ_1045U(...) \, +#define Z_IS_1045U_EQ_1045U(...) \, +#define Z_IS_1046_EQ_1046(...) \, +#define Z_IS_1046U_EQ_1046(...) \, +#define Z_IS_1046_EQ_1046U(...) \, +#define Z_IS_1046U_EQ_1046U(...) \, +#define Z_IS_1047_EQ_1047(...) \, +#define Z_IS_1047U_EQ_1047(...) \, +#define Z_IS_1047_EQ_1047U(...) \, +#define Z_IS_1047U_EQ_1047U(...) \, +#define Z_IS_1048_EQ_1048(...) \, +#define Z_IS_1048U_EQ_1048(...) \, +#define Z_IS_1048_EQ_1048U(...) \, +#define Z_IS_1048U_EQ_1048U(...) \, +#define Z_IS_1049_EQ_1049(...) \, +#define Z_IS_1049U_EQ_1049(...) \, +#define Z_IS_1049_EQ_1049U(...) \, +#define Z_IS_1049U_EQ_1049U(...) \, +#define Z_IS_1050_EQ_1050(...) \, +#define Z_IS_1050U_EQ_1050(...) \, +#define Z_IS_1050_EQ_1050U(...) \, +#define Z_IS_1050U_EQ_1050U(...) \, +#define Z_IS_1051_EQ_1051(...) \, +#define Z_IS_1051U_EQ_1051(...) \, +#define Z_IS_1051_EQ_1051U(...) \, +#define Z_IS_1051U_EQ_1051U(...) \, +#define Z_IS_1052_EQ_1052(...) \, +#define Z_IS_1052U_EQ_1052(...) \, +#define Z_IS_1052_EQ_1052U(...) \, +#define Z_IS_1052U_EQ_1052U(...) \, +#define Z_IS_1053_EQ_1053(...) \, +#define Z_IS_1053U_EQ_1053(...) \, +#define Z_IS_1053_EQ_1053U(...) \, +#define Z_IS_1053U_EQ_1053U(...) \, +#define Z_IS_1054_EQ_1054(...) \, +#define Z_IS_1054U_EQ_1054(...) \, +#define Z_IS_1054_EQ_1054U(...) \, +#define Z_IS_1054U_EQ_1054U(...) \, +#define Z_IS_1055_EQ_1055(...) \, +#define Z_IS_1055U_EQ_1055(...) \, +#define Z_IS_1055_EQ_1055U(...) \, +#define Z_IS_1055U_EQ_1055U(...) \, +#define Z_IS_1056_EQ_1056(...) \, +#define Z_IS_1056U_EQ_1056(...) \, +#define Z_IS_1056_EQ_1056U(...) \, +#define Z_IS_1056U_EQ_1056U(...) \, +#define Z_IS_1057_EQ_1057(...) \, +#define Z_IS_1057U_EQ_1057(...) \, +#define Z_IS_1057_EQ_1057U(...) \, +#define Z_IS_1057U_EQ_1057U(...) \, +#define Z_IS_1058_EQ_1058(...) \, +#define Z_IS_1058U_EQ_1058(...) \, +#define Z_IS_1058_EQ_1058U(...) \, +#define Z_IS_1058U_EQ_1058U(...) \, +#define Z_IS_1059_EQ_1059(...) \, +#define Z_IS_1059U_EQ_1059(...) \, +#define Z_IS_1059_EQ_1059U(...) \, +#define Z_IS_1059U_EQ_1059U(...) \, +#define Z_IS_1060_EQ_1060(...) \, +#define Z_IS_1060U_EQ_1060(...) \, +#define Z_IS_1060_EQ_1060U(...) \, +#define Z_IS_1060U_EQ_1060U(...) \, +#define Z_IS_1061_EQ_1061(...) \, +#define Z_IS_1061U_EQ_1061(...) \, +#define Z_IS_1061_EQ_1061U(...) \, +#define Z_IS_1061U_EQ_1061U(...) \, +#define Z_IS_1062_EQ_1062(...) \, +#define Z_IS_1062U_EQ_1062(...) \, +#define Z_IS_1062_EQ_1062U(...) \, +#define Z_IS_1062U_EQ_1062U(...) \, +#define Z_IS_1063_EQ_1063(...) \, +#define Z_IS_1063U_EQ_1063(...) \, +#define Z_IS_1063_EQ_1063U(...) \, +#define Z_IS_1063U_EQ_1063U(...) \, +#define Z_IS_1064_EQ_1064(...) \, +#define Z_IS_1064U_EQ_1064(...) \, +#define Z_IS_1064_EQ_1064U(...) \, +#define Z_IS_1064U_EQ_1064U(...) \, +#define Z_IS_1065_EQ_1065(...) \, +#define Z_IS_1065U_EQ_1065(...) \, +#define Z_IS_1065_EQ_1065U(...) \, +#define Z_IS_1065U_EQ_1065U(...) \, +#define Z_IS_1066_EQ_1066(...) \, +#define Z_IS_1066U_EQ_1066(...) \, +#define Z_IS_1066_EQ_1066U(...) \, +#define Z_IS_1066U_EQ_1066U(...) \, +#define Z_IS_1067_EQ_1067(...) \, +#define Z_IS_1067U_EQ_1067(...) \, +#define Z_IS_1067_EQ_1067U(...) \, +#define Z_IS_1067U_EQ_1067U(...) \, +#define Z_IS_1068_EQ_1068(...) \, +#define Z_IS_1068U_EQ_1068(...) \, +#define Z_IS_1068_EQ_1068U(...) \, +#define Z_IS_1068U_EQ_1068U(...) \, +#define Z_IS_1069_EQ_1069(...) \, +#define Z_IS_1069U_EQ_1069(...) \, +#define Z_IS_1069_EQ_1069U(...) \, +#define Z_IS_1069U_EQ_1069U(...) \, +#define Z_IS_1070_EQ_1070(...) \, +#define Z_IS_1070U_EQ_1070(...) \, +#define Z_IS_1070_EQ_1070U(...) \, +#define Z_IS_1070U_EQ_1070U(...) \, +#define Z_IS_1071_EQ_1071(...) \, +#define Z_IS_1071U_EQ_1071(...) \, +#define Z_IS_1071_EQ_1071U(...) \, +#define Z_IS_1071U_EQ_1071U(...) \, +#define Z_IS_1072_EQ_1072(...) \, +#define Z_IS_1072U_EQ_1072(...) \, +#define Z_IS_1072_EQ_1072U(...) \, +#define Z_IS_1072U_EQ_1072U(...) \, +#define Z_IS_1073_EQ_1073(...) \, +#define Z_IS_1073U_EQ_1073(...) \, +#define Z_IS_1073_EQ_1073U(...) \, +#define Z_IS_1073U_EQ_1073U(...) \, +#define Z_IS_1074_EQ_1074(...) \, +#define Z_IS_1074U_EQ_1074(...) \, +#define Z_IS_1074_EQ_1074U(...) \, +#define Z_IS_1074U_EQ_1074U(...) \, +#define Z_IS_1075_EQ_1075(...) \, +#define Z_IS_1075U_EQ_1075(...) \, +#define Z_IS_1075_EQ_1075U(...) \, +#define Z_IS_1075U_EQ_1075U(...) \, +#define Z_IS_1076_EQ_1076(...) \, +#define Z_IS_1076U_EQ_1076(...) \, +#define Z_IS_1076_EQ_1076U(...) \, +#define Z_IS_1076U_EQ_1076U(...) \, +#define Z_IS_1077_EQ_1077(...) \, +#define Z_IS_1077U_EQ_1077(...) \, +#define Z_IS_1077_EQ_1077U(...) \, +#define Z_IS_1077U_EQ_1077U(...) \, +#define Z_IS_1078_EQ_1078(...) \, +#define Z_IS_1078U_EQ_1078(...) \, +#define Z_IS_1078_EQ_1078U(...) \, +#define Z_IS_1078U_EQ_1078U(...) \, +#define Z_IS_1079_EQ_1079(...) \, +#define Z_IS_1079U_EQ_1079(...) \, +#define Z_IS_1079_EQ_1079U(...) \, +#define Z_IS_1079U_EQ_1079U(...) \, +#define Z_IS_1080_EQ_1080(...) \, +#define Z_IS_1080U_EQ_1080(...) \, +#define Z_IS_1080_EQ_1080U(...) \, +#define Z_IS_1080U_EQ_1080U(...) \, +#define Z_IS_1081_EQ_1081(...) \, +#define Z_IS_1081U_EQ_1081(...) \, +#define Z_IS_1081_EQ_1081U(...) \, +#define Z_IS_1081U_EQ_1081U(...) \, +#define Z_IS_1082_EQ_1082(...) \, +#define Z_IS_1082U_EQ_1082(...) \, +#define Z_IS_1082_EQ_1082U(...) \, +#define Z_IS_1082U_EQ_1082U(...) \, +#define Z_IS_1083_EQ_1083(...) \, +#define Z_IS_1083U_EQ_1083(...) \, +#define Z_IS_1083_EQ_1083U(...) \, +#define Z_IS_1083U_EQ_1083U(...) \, +#define Z_IS_1084_EQ_1084(...) \, +#define Z_IS_1084U_EQ_1084(...) \, +#define Z_IS_1084_EQ_1084U(...) \, +#define Z_IS_1084U_EQ_1084U(...) \, +#define Z_IS_1085_EQ_1085(...) \, +#define Z_IS_1085U_EQ_1085(...) \, +#define Z_IS_1085_EQ_1085U(...) \, +#define Z_IS_1085U_EQ_1085U(...) \, +#define Z_IS_1086_EQ_1086(...) \, +#define Z_IS_1086U_EQ_1086(...) \, +#define Z_IS_1086_EQ_1086U(...) \, +#define Z_IS_1086U_EQ_1086U(...) \, +#define Z_IS_1087_EQ_1087(...) \, +#define Z_IS_1087U_EQ_1087(...) \, +#define Z_IS_1087_EQ_1087U(...) \, +#define Z_IS_1087U_EQ_1087U(...) \, +#define Z_IS_1088_EQ_1088(...) \, +#define Z_IS_1088U_EQ_1088(...) \, +#define Z_IS_1088_EQ_1088U(...) \, +#define Z_IS_1088U_EQ_1088U(...) \, +#define Z_IS_1089_EQ_1089(...) \, +#define Z_IS_1089U_EQ_1089(...) \, +#define Z_IS_1089_EQ_1089U(...) \, +#define Z_IS_1089U_EQ_1089U(...) \, +#define Z_IS_1090_EQ_1090(...) \, +#define Z_IS_1090U_EQ_1090(...) \, +#define Z_IS_1090_EQ_1090U(...) \, +#define Z_IS_1090U_EQ_1090U(...) \, +#define Z_IS_1091_EQ_1091(...) \, +#define Z_IS_1091U_EQ_1091(...) \, +#define Z_IS_1091_EQ_1091U(...) \, +#define Z_IS_1091U_EQ_1091U(...) \, +#define Z_IS_1092_EQ_1092(...) \, +#define Z_IS_1092U_EQ_1092(...) \, +#define Z_IS_1092_EQ_1092U(...) \, +#define Z_IS_1092U_EQ_1092U(...) \, +#define Z_IS_1093_EQ_1093(...) \, +#define Z_IS_1093U_EQ_1093(...) \, +#define Z_IS_1093_EQ_1093U(...) \, +#define Z_IS_1093U_EQ_1093U(...) \, +#define Z_IS_1094_EQ_1094(...) \, +#define Z_IS_1094U_EQ_1094(...) \, +#define Z_IS_1094_EQ_1094U(...) \, +#define Z_IS_1094U_EQ_1094U(...) \, +#define Z_IS_1095_EQ_1095(...) \, +#define Z_IS_1095U_EQ_1095(...) \, +#define Z_IS_1095_EQ_1095U(...) \, +#define Z_IS_1095U_EQ_1095U(...) \, +#define Z_IS_1096_EQ_1096(...) \, +#define Z_IS_1096U_EQ_1096(...) \, +#define Z_IS_1096_EQ_1096U(...) \, +#define Z_IS_1096U_EQ_1096U(...) \, +#define Z_IS_1097_EQ_1097(...) \, +#define Z_IS_1097U_EQ_1097(...) \, +#define Z_IS_1097_EQ_1097U(...) \, +#define Z_IS_1097U_EQ_1097U(...) \, +#define Z_IS_1098_EQ_1098(...) \, +#define Z_IS_1098U_EQ_1098(...) \, +#define Z_IS_1098_EQ_1098U(...) \, +#define Z_IS_1098U_EQ_1098U(...) \, +#define Z_IS_1099_EQ_1099(...) \, +#define Z_IS_1099U_EQ_1099(...) \, +#define Z_IS_1099_EQ_1099U(...) \, +#define Z_IS_1099U_EQ_1099U(...) \, +#define Z_IS_1100_EQ_1100(...) \, +#define Z_IS_1100U_EQ_1100(...) \, +#define Z_IS_1100_EQ_1100U(...) \, +#define Z_IS_1100U_EQ_1100U(...) \, +#define Z_IS_1101_EQ_1101(...) \, +#define Z_IS_1101U_EQ_1101(...) \, +#define Z_IS_1101_EQ_1101U(...) \, +#define Z_IS_1101U_EQ_1101U(...) \, +#define Z_IS_1102_EQ_1102(...) \, +#define Z_IS_1102U_EQ_1102(...) \, +#define Z_IS_1102_EQ_1102U(...) \, +#define Z_IS_1102U_EQ_1102U(...) \, +#define Z_IS_1103_EQ_1103(...) \, +#define Z_IS_1103U_EQ_1103(...) \, +#define Z_IS_1103_EQ_1103U(...) \, +#define Z_IS_1103U_EQ_1103U(...) \, +#define Z_IS_1104_EQ_1104(...) \, +#define Z_IS_1104U_EQ_1104(...) \, +#define Z_IS_1104_EQ_1104U(...) \, +#define Z_IS_1104U_EQ_1104U(...) \, +#define Z_IS_1105_EQ_1105(...) \, +#define Z_IS_1105U_EQ_1105(...) \, +#define Z_IS_1105_EQ_1105U(...) \, +#define Z_IS_1105U_EQ_1105U(...) \, +#define Z_IS_1106_EQ_1106(...) \, +#define Z_IS_1106U_EQ_1106(...) \, +#define Z_IS_1106_EQ_1106U(...) \, +#define Z_IS_1106U_EQ_1106U(...) \, +#define Z_IS_1107_EQ_1107(...) \, +#define Z_IS_1107U_EQ_1107(...) \, +#define Z_IS_1107_EQ_1107U(...) \, +#define Z_IS_1107U_EQ_1107U(...) \, +#define Z_IS_1108_EQ_1108(...) \, +#define Z_IS_1108U_EQ_1108(...) \, +#define Z_IS_1108_EQ_1108U(...) \, +#define Z_IS_1108U_EQ_1108U(...) \, +#define Z_IS_1109_EQ_1109(...) \, +#define Z_IS_1109U_EQ_1109(...) \, +#define Z_IS_1109_EQ_1109U(...) \, +#define Z_IS_1109U_EQ_1109U(...) \, +#define Z_IS_1110_EQ_1110(...) \, +#define Z_IS_1110U_EQ_1110(...) \, +#define Z_IS_1110_EQ_1110U(...) \, +#define Z_IS_1110U_EQ_1110U(...) \, +#define Z_IS_1111_EQ_1111(...) \, +#define Z_IS_1111U_EQ_1111(...) \, +#define Z_IS_1111_EQ_1111U(...) \, +#define Z_IS_1111U_EQ_1111U(...) \, +#define Z_IS_1112_EQ_1112(...) \, +#define Z_IS_1112U_EQ_1112(...) \, +#define Z_IS_1112_EQ_1112U(...) \, +#define Z_IS_1112U_EQ_1112U(...) \, +#define Z_IS_1113_EQ_1113(...) \, +#define Z_IS_1113U_EQ_1113(...) \, +#define Z_IS_1113_EQ_1113U(...) \, +#define Z_IS_1113U_EQ_1113U(...) \, +#define Z_IS_1114_EQ_1114(...) \, +#define Z_IS_1114U_EQ_1114(...) \, +#define Z_IS_1114_EQ_1114U(...) \, +#define Z_IS_1114U_EQ_1114U(...) \, +#define Z_IS_1115_EQ_1115(...) \, +#define Z_IS_1115U_EQ_1115(...) \, +#define Z_IS_1115_EQ_1115U(...) \, +#define Z_IS_1115U_EQ_1115U(...) \, +#define Z_IS_1116_EQ_1116(...) \, +#define Z_IS_1116U_EQ_1116(...) \, +#define Z_IS_1116_EQ_1116U(...) \, +#define Z_IS_1116U_EQ_1116U(...) \, +#define Z_IS_1117_EQ_1117(...) \, +#define Z_IS_1117U_EQ_1117(...) \, +#define Z_IS_1117_EQ_1117U(...) \, +#define Z_IS_1117U_EQ_1117U(...) \, +#define Z_IS_1118_EQ_1118(...) \, +#define Z_IS_1118U_EQ_1118(...) \, +#define Z_IS_1118_EQ_1118U(...) \, +#define Z_IS_1118U_EQ_1118U(...) \, +#define Z_IS_1119_EQ_1119(...) \, +#define Z_IS_1119U_EQ_1119(...) \, +#define Z_IS_1119_EQ_1119U(...) \, +#define Z_IS_1119U_EQ_1119U(...) \, +#define Z_IS_1120_EQ_1120(...) \, +#define Z_IS_1120U_EQ_1120(...) \, +#define Z_IS_1120_EQ_1120U(...) \, +#define Z_IS_1120U_EQ_1120U(...) \, +#define Z_IS_1121_EQ_1121(...) \, +#define Z_IS_1121U_EQ_1121(...) \, +#define Z_IS_1121_EQ_1121U(...) \, +#define Z_IS_1121U_EQ_1121U(...) \, +#define Z_IS_1122_EQ_1122(...) \, +#define Z_IS_1122U_EQ_1122(...) \, +#define Z_IS_1122_EQ_1122U(...) \, +#define Z_IS_1122U_EQ_1122U(...) \, +#define Z_IS_1123_EQ_1123(...) \, +#define Z_IS_1123U_EQ_1123(...) \, +#define Z_IS_1123_EQ_1123U(...) \, +#define Z_IS_1123U_EQ_1123U(...) \, +#define Z_IS_1124_EQ_1124(...) \, +#define Z_IS_1124U_EQ_1124(...) \, +#define Z_IS_1124_EQ_1124U(...) \, +#define Z_IS_1124U_EQ_1124U(...) \, +#define Z_IS_1125_EQ_1125(...) \, +#define Z_IS_1125U_EQ_1125(...) \, +#define Z_IS_1125_EQ_1125U(...) \, +#define Z_IS_1125U_EQ_1125U(...) \, +#define Z_IS_1126_EQ_1126(...) \, +#define Z_IS_1126U_EQ_1126(...) \, +#define Z_IS_1126_EQ_1126U(...) \, +#define Z_IS_1126U_EQ_1126U(...) \, +#define Z_IS_1127_EQ_1127(...) \, +#define Z_IS_1127U_EQ_1127(...) \, +#define Z_IS_1127_EQ_1127U(...) \, +#define Z_IS_1127U_EQ_1127U(...) \, +#define Z_IS_1128_EQ_1128(...) \, +#define Z_IS_1128U_EQ_1128(...) \, +#define Z_IS_1128_EQ_1128U(...) \, +#define Z_IS_1128U_EQ_1128U(...) \, +#define Z_IS_1129_EQ_1129(...) \, +#define Z_IS_1129U_EQ_1129(...) \, +#define Z_IS_1129_EQ_1129U(...) \, +#define Z_IS_1129U_EQ_1129U(...) \, +#define Z_IS_1130_EQ_1130(...) \, +#define Z_IS_1130U_EQ_1130(...) \, +#define Z_IS_1130_EQ_1130U(...) \, +#define Z_IS_1130U_EQ_1130U(...) \, +#define Z_IS_1131_EQ_1131(...) \, +#define Z_IS_1131U_EQ_1131(...) \, +#define Z_IS_1131_EQ_1131U(...) \, +#define Z_IS_1131U_EQ_1131U(...) \, +#define Z_IS_1132_EQ_1132(...) \, +#define Z_IS_1132U_EQ_1132(...) \, +#define Z_IS_1132_EQ_1132U(...) \, +#define Z_IS_1132U_EQ_1132U(...) \, +#define Z_IS_1133_EQ_1133(...) \, +#define Z_IS_1133U_EQ_1133(...) \, +#define Z_IS_1133_EQ_1133U(...) \, +#define Z_IS_1133U_EQ_1133U(...) \, +#define Z_IS_1134_EQ_1134(...) \, +#define Z_IS_1134U_EQ_1134(...) \, +#define Z_IS_1134_EQ_1134U(...) \, +#define Z_IS_1134U_EQ_1134U(...) \, +#define Z_IS_1135_EQ_1135(...) \, +#define Z_IS_1135U_EQ_1135(...) \, +#define Z_IS_1135_EQ_1135U(...) \, +#define Z_IS_1135U_EQ_1135U(...) \, +#define Z_IS_1136_EQ_1136(...) \, +#define Z_IS_1136U_EQ_1136(...) \, +#define Z_IS_1136_EQ_1136U(...) \, +#define Z_IS_1136U_EQ_1136U(...) \, +#define Z_IS_1137_EQ_1137(...) \, +#define Z_IS_1137U_EQ_1137(...) \, +#define Z_IS_1137_EQ_1137U(...) \, +#define Z_IS_1137U_EQ_1137U(...) \, +#define Z_IS_1138_EQ_1138(...) \, +#define Z_IS_1138U_EQ_1138(...) \, +#define Z_IS_1138_EQ_1138U(...) \, +#define Z_IS_1138U_EQ_1138U(...) \, +#define Z_IS_1139_EQ_1139(...) \, +#define Z_IS_1139U_EQ_1139(...) \, +#define Z_IS_1139_EQ_1139U(...) \, +#define Z_IS_1139U_EQ_1139U(...) \, +#define Z_IS_1140_EQ_1140(...) \, +#define Z_IS_1140U_EQ_1140(...) \, +#define Z_IS_1140_EQ_1140U(...) \, +#define Z_IS_1140U_EQ_1140U(...) \, +#define Z_IS_1141_EQ_1141(...) \, +#define Z_IS_1141U_EQ_1141(...) \, +#define Z_IS_1141_EQ_1141U(...) \, +#define Z_IS_1141U_EQ_1141U(...) \, +#define Z_IS_1142_EQ_1142(...) \, +#define Z_IS_1142U_EQ_1142(...) \, +#define Z_IS_1142_EQ_1142U(...) \, +#define Z_IS_1142U_EQ_1142U(...) \, +#define Z_IS_1143_EQ_1143(...) \, +#define Z_IS_1143U_EQ_1143(...) \, +#define Z_IS_1143_EQ_1143U(...) \, +#define Z_IS_1143U_EQ_1143U(...) \, +#define Z_IS_1144_EQ_1144(...) \, +#define Z_IS_1144U_EQ_1144(...) \, +#define Z_IS_1144_EQ_1144U(...) \, +#define Z_IS_1144U_EQ_1144U(...) \, +#define Z_IS_1145_EQ_1145(...) \, +#define Z_IS_1145U_EQ_1145(...) \, +#define Z_IS_1145_EQ_1145U(...) \, +#define Z_IS_1145U_EQ_1145U(...) \, +#define Z_IS_1146_EQ_1146(...) \, +#define Z_IS_1146U_EQ_1146(...) \, +#define Z_IS_1146_EQ_1146U(...) \, +#define Z_IS_1146U_EQ_1146U(...) \, +#define Z_IS_1147_EQ_1147(...) \, +#define Z_IS_1147U_EQ_1147(...) \, +#define Z_IS_1147_EQ_1147U(...) \, +#define Z_IS_1147U_EQ_1147U(...) \, +#define Z_IS_1148_EQ_1148(...) \, +#define Z_IS_1148U_EQ_1148(...) \, +#define Z_IS_1148_EQ_1148U(...) \, +#define Z_IS_1148U_EQ_1148U(...) \, +#define Z_IS_1149_EQ_1149(...) \, +#define Z_IS_1149U_EQ_1149(...) \, +#define Z_IS_1149_EQ_1149U(...) \, +#define Z_IS_1149U_EQ_1149U(...) \, +#define Z_IS_1150_EQ_1150(...) \, +#define Z_IS_1150U_EQ_1150(...) \, +#define Z_IS_1150_EQ_1150U(...) \, +#define Z_IS_1150U_EQ_1150U(...) \, +#define Z_IS_1151_EQ_1151(...) \, +#define Z_IS_1151U_EQ_1151(...) \, +#define Z_IS_1151_EQ_1151U(...) \, +#define Z_IS_1151U_EQ_1151U(...) \, +#define Z_IS_1152_EQ_1152(...) \, +#define Z_IS_1152U_EQ_1152(...) \, +#define Z_IS_1152_EQ_1152U(...) \, +#define Z_IS_1152U_EQ_1152U(...) \, +#define Z_IS_1153_EQ_1153(...) \, +#define Z_IS_1153U_EQ_1153(...) \, +#define Z_IS_1153_EQ_1153U(...) \, +#define Z_IS_1153U_EQ_1153U(...) \, +#define Z_IS_1154_EQ_1154(...) \, +#define Z_IS_1154U_EQ_1154(...) \, +#define Z_IS_1154_EQ_1154U(...) \, +#define Z_IS_1154U_EQ_1154U(...) \, +#define Z_IS_1155_EQ_1155(...) \, +#define Z_IS_1155U_EQ_1155(...) \, +#define Z_IS_1155_EQ_1155U(...) \, +#define Z_IS_1155U_EQ_1155U(...) \, +#define Z_IS_1156_EQ_1156(...) \, +#define Z_IS_1156U_EQ_1156(...) \, +#define Z_IS_1156_EQ_1156U(...) \, +#define Z_IS_1156U_EQ_1156U(...) \, +#define Z_IS_1157_EQ_1157(...) \, +#define Z_IS_1157U_EQ_1157(...) \, +#define Z_IS_1157_EQ_1157U(...) \, +#define Z_IS_1157U_EQ_1157U(...) \, +#define Z_IS_1158_EQ_1158(...) \, +#define Z_IS_1158U_EQ_1158(...) \, +#define Z_IS_1158_EQ_1158U(...) \, +#define Z_IS_1158U_EQ_1158U(...) \, +#define Z_IS_1159_EQ_1159(...) \, +#define Z_IS_1159U_EQ_1159(...) \, +#define Z_IS_1159_EQ_1159U(...) \, +#define Z_IS_1159U_EQ_1159U(...) \, +#define Z_IS_1160_EQ_1160(...) \, +#define Z_IS_1160U_EQ_1160(...) \, +#define Z_IS_1160_EQ_1160U(...) \, +#define Z_IS_1160U_EQ_1160U(...) \, +#define Z_IS_1161_EQ_1161(...) \, +#define Z_IS_1161U_EQ_1161(...) \, +#define Z_IS_1161_EQ_1161U(...) \, +#define Z_IS_1161U_EQ_1161U(...) \, +#define Z_IS_1162_EQ_1162(...) \, +#define Z_IS_1162U_EQ_1162(...) \, +#define Z_IS_1162_EQ_1162U(...) \, +#define Z_IS_1162U_EQ_1162U(...) \, +#define Z_IS_1163_EQ_1163(...) \, +#define Z_IS_1163U_EQ_1163(...) \, +#define Z_IS_1163_EQ_1163U(...) \, +#define Z_IS_1163U_EQ_1163U(...) \, +#define Z_IS_1164_EQ_1164(...) \, +#define Z_IS_1164U_EQ_1164(...) \, +#define Z_IS_1164_EQ_1164U(...) \, +#define Z_IS_1164U_EQ_1164U(...) \, +#define Z_IS_1165_EQ_1165(...) \, +#define Z_IS_1165U_EQ_1165(...) \, +#define Z_IS_1165_EQ_1165U(...) \, +#define Z_IS_1165U_EQ_1165U(...) \, +#define Z_IS_1166_EQ_1166(...) \, +#define Z_IS_1166U_EQ_1166(...) \, +#define Z_IS_1166_EQ_1166U(...) \, +#define Z_IS_1166U_EQ_1166U(...) \, +#define Z_IS_1167_EQ_1167(...) \, +#define Z_IS_1167U_EQ_1167(...) \, +#define Z_IS_1167_EQ_1167U(...) \, +#define Z_IS_1167U_EQ_1167U(...) \, +#define Z_IS_1168_EQ_1168(...) \, +#define Z_IS_1168U_EQ_1168(...) \, +#define Z_IS_1168_EQ_1168U(...) \, +#define Z_IS_1168U_EQ_1168U(...) \, +#define Z_IS_1169_EQ_1169(...) \, +#define Z_IS_1169U_EQ_1169(...) \, +#define Z_IS_1169_EQ_1169U(...) \, +#define Z_IS_1169U_EQ_1169U(...) \, +#define Z_IS_1170_EQ_1170(...) \, +#define Z_IS_1170U_EQ_1170(...) \, +#define Z_IS_1170_EQ_1170U(...) \, +#define Z_IS_1170U_EQ_1170U(...) \, +#define Z_IS_1171_EQ_1171(...) \, +#define Z_IS_1171U_EQ_1171(...) \, +#define Z_IS_1171_EQ_1171U(...) \, +#define Z_IS_1171U_EQ_1171U(...) \, +#define Z_IS_1172_EQ_1172(...) \, +#define Z_IS_1172U_EQ_1172(...) \, +#define Z_IS_1172_EQ_1172U(...) \, +#define Z_IS_1172U_EQ_1172U(...) \, +#define Z_IS_1173_EQ_1173(...) \, +#define Z_IS_1173U_EQ_1173(...) \, +#define Z_IS_1173_EQ_1173U(...) \, +#define Z_IS_1173U_EQ_1173U(...) \, +#define Z_IS_1174_EQ_1174(...) \, +#define Z_IS_1174U_EQ_1174(...) \, +#define Z_IS_1174_EQ_1174U(...) \, +#define Z_IS_1174U_EQ_1174U(...) \, +#define Z_IS_1175_EQ_1175(...) \, +#define Z_IS_1175U_EQ_1175(...) \, +#define Z_IS_1175_EQ_1175U(...) \, +#define Z_IS_1175U_EQ_1175U(...) \, +#define Z_IS_1176_EQ_1176(...) \, +#define Z_IS_1176U_EQ_1176(...) \, +#define Z_IS_1176_EQ_1176U(...) \, +#define Z_IS_1176U_EQ_1176U(...) \, +#define Z_IS_1177_EQ_1177(...) \, +#define Z_IS_1177U_EQ_1177(...) \, +#define Z_IS_1177_EQ_1177U(...) \, +#define Z_IS_1177U_EQ_1177U(...) \, +#define Z_IS_1178_EQ_1178(...) \, +#define Z_IS_1178U_EQ_1178(...) \, +#define Z_IS_1178_EQ_1178U(...) \, +#define Z_IS_1178U_EQ_1178U(...) \, +#define Z_IS_1179_EQ_1179(...) \, +#define Z_IS_1179U_EQ_1179(...) \, +#define Z_IS_1179_EQ_1179U(...) \, +#define Z_IS_1179U_EQ_1179U(...) \, +#define Z_IS_1180_EQ_1180(...) \, +#define Z_IS_1180U_EQ_1180(...) \, +#define Z_IS_1180_EQ_1180U(...) \, +#define Z_IS_1180U_EQ_1180U(...) \, +#define Z_IS_1181_EQ_1181(...) \, +#define Z_IS_1181U_EQ_1181(...) \, +#define Z_IS_1181_EQ_1181U(...) \, +#define Z_IS_1181U_EQ_1181U(...) \, +#define Z_IS_1182_EQ_1182(...) \, +#define Z_IS_1182U_EQ_1182(...) \, +#define Z_IS_1182_EQ_1182U(...) \, +#define Z_IS_1182U_EQ_1182U(...) \, +#define Z_IS_1183_EQ_1183(...) \, +#define Z_IS_1183U_EQ_1183(...) \, +#define Z_IS_1183_EQ_1183U(...) \, +#define Z_IS_1183U_EQ_1183U(...) \, +#define Z_IS_1184_EQ_1184(...) \, +#define Z_IS_1184U_EQ_1184(...) \, +#define Z_IS_1184_EQ_1184U(...) \, +#define Z_IS_1184U_EQ_1184U(...) \, +#define Z_IS_1185_EQ_1185(...) \, +#define Z_IS_1185U_EQ_1185(...) \, +#define Z_IS_1185_EQ_1185U(...) \, +#define Z_IS_1185U_EQ_1185U(...) \, +#define Z_IS_1186_EQ_1186(...) \, +#define Z_IS_1186U_EQ_1186(...) \, +#define Z_IS_1186_EQ_1186U(...) \, +#define Z_IS_1186U_EQ_1186U(...) \, +#define Z_IS_1187_EQ_1187(...) \, +#define Z_IS_1187U_EQ_1187(...) \, +#define Z_IS_1187_EQ_1187U(...) \, +#define Z_IS_1187U_EQ_1187U(...) \, +#define Z_IS_1188_EQ_1188(...) \, +#define Z_IS_1188U_EQ_1188(...) \, +#define Z_IS_1188_EQ_1188U(...) \, +#define Z_IS_1188U_EQ_1188U(...) \, +#define Z_IS_1189_EQ_1189(...) \, +#define Z_IS_1189U_EQ_1189(...) \, +#define Z_IS_1189_EQ_1189U(...) \, +#define Z_IS_1189U_EQ_1189U(...) \, +#define Z_IS_1190_EQ_1190(...) \, +#define Z_IS_1190U_EQ_1190(...) \, +#define Z_IS_1190_EQ_1190U(...) \, +#define Z_IS_1190U_EQ_1190U(...) \, +#define Z_IS_1191_EQ_1191(...) \, +#define Z_IS_1191U_EQ_1191(...) \, +#define Z_IS_1191_EQ_1191U(...) \, +#define Z_IS_1191U_EQ_1191U(...) \, +#define Z_IS_1192_EQ_1192(...) \, +#define Z_IS_1192U_EQ_1192(...) \, +#define Z_IS_1192_EQ_1192U(...) \, +#define Z_IS_1192U_EQ_1192U(...) \, +#define Z_IS_1193_EQ_1193(...) \, +#define Z_IS_1193U_EQ_1193(...) \, +#define Z_IS_1193_EQ_1193U(...) \, +#define Z_IS_1193U_EQ_1193U(...) \, +#define Z_IS_1194_EQ_1194(...) \, +#define Z_IS_1194U_EQ_1194(...) \, +#define Z_IS_1194_EQ_1194U(...) \, +#define Z_IS_1194U_EQ_1194U(...) \, +#define Z_IS_1195_EQ_1195(...) \, +#define Z_IS_1195U_EQ_1195(...) \, +#define Z_IS_1195_EQ_1195U(...) \, +#define Z_IS_1195U_EQ_1195U(...) \, +#define Z_IS_1196_EQ_1196(...) \, +#define Z_IS_1196U_EQ_1196(...) \, +#define Z_IS_1196_EQ_1196U(...) \, +#define Z_IS_1196U_EQ_1196U(...) \, +#define Z_IS_1197_EQ_1197(...) \, +#define Z_IS_1197U_EQ_1197(...) \, +#define Z_IS_1197_EQ_1197U(...) \, +#define Z_IS_1197U_EQ_1197U(...) \, +#define Z_IS_1198_EQ_1198(...) \, +#define Z_IS_1198U_EQ_1198(...) \, +#define Z_IS_1198_EQ_1198U(...) \, +#define Z_IS_1198U_EQ_1198U(...) \, +#define Z_IS_1199_EQ_1199(...) \, +#define Z_IS_1199U_EQ_1199(...) \, +#define Z_IS_1199_EQ_1199U(...) \, +#define Z_IS_1199U_EQ_1199U(...) \, +#define Z_IS_1200_EQ_1200(...) \, +#define Z_IS_1200U_EQ_1200(...) \, +#define Z_IS_1200_EQ_1200U(...) \, +#define Z_IS_1200U_EQ_1200U(...) \, +#define Z_IS_1201_EQ_1201(...) \, +#define Z_IS_1201U_EQ_1201(...) \, +#define Z_IS_1201_EQ_1201U(...) \, +#define Z_IS_1201U_EQ_1201U(...) \, +#define Z_IS_1202_EQ_1202(...) \, +#define Z_IS_1202U_EQ_1202(...) \, +#define Z_IS_1202_EQ_1202U(...) \, +#define Z_IS_1202U_EQ_1202U(...) \, +#define Z_IS_1203_EQ_1203(...) \, +#define Z_IS_1203U_EQ_1203(...) \, +#define Z_IS_1203_EQ_1203U(...) \, +#define Z_IS_1203U_EQ_1203U(...) \, +#define Z_IS_1204_EQ_1204(...) \, +#define Z_IS_1204U_EQ_1204(...) \, +#define Z_IS_1204_EQ_1204U(...) \, +#define Z_IS_1204U_EQ_1204U(...) \, +#define Z_IS_1205_EQ_1205(...) \, +#define Z_IS_1205U_EQ_1205(...) \, +#define Z_IS_1205_EQ_1205U(...) \, +#define Z_IS_1205U_EQ_1205U(...) \, +#define Z_IS_1206_EQ_1206(...) \, +#define Z_IS_1206U_EQ_1206(...) \, +#define Z_IS_1206_EQ_1206U(...) \, +#define Z_IS_1206U_EQ_1206U(...) \, +#define Z_IS_1207_EQ_1207(...) \, +#define Z_IS_1207U_EQ_1207(...) \, +#define Z_IS_1207_EQ_1207U(...) \, +#define Z_IS_1207U_EQ_1207U(...) \, +#define Z_IS_1208_EQ_1208(...) \, +#define Z_IS_1208U_EQ_1208(...) \, +#define Z_IS_1208_EQ_1208U(...) \, +#define Z_IS_1208U_EQ_1208U(...) \, +#define Z_IS_1209_EQ_1209(...) \, +#define Z_IS_1209U_EQ_1209(...) \, +#define Z_IS_1209_EQ_1209U(...) \, +#define Z_IS_1209U_EQ_1209U(...) \, +#define Z_IS_1210_EQ_1210(...) \, +#define Z_IS_1210U_EQ_1210(...) \, +#define Z_IS_1210_EQ_1210U(...) \, +#define Z_IS_1210U_EQ_1210U(...) \, +#define Z_IS_1211_EQ_1211(...) \, +#define Z_IS_1211U_EQ_1211(...) \, +#define Z_IS_1211_EQ_1211U(...) \, +#define Z_IS_1211U_EQ_1211U(...) \, +#define Z_IS_1212_EQ_1212(...) \, +#define Z_IS_1212U_EQ_1212(...) \, +#define Z_IS_1212_EQ_1212U(...) \, +#define Z_IS_1212U_EQ_1212U(...) \, +#define Z_IS_1213_EQ_1213(...) \, +#define Z_IS_1213U_EQ_1213(...) \, +#define Z_IS_1213_EQ_1213U(...) \, +#define Z_IS_1213U_EQ_1213U(...) \, +#define Z_IS_1214_EQ_1214(...) \, +#define Z_IS_1214U_EQ_1214(...) \, +#define Z_IS_1214_EQ_1214U(...) \, +#define Z_IS_1214U_EQ_1214U(...) \, +#define Z_IS_1215_EQ_1215(...) \, +#define Z_IS_1215U_EQ_1215(...) \, +#define Z_IS_1215_EQ_1215U(...) \, +#define Z_IS_1215U_EQ_1215U(...) \, +#define Z_IS_1216_EQ_1216(...) \, +#define Z_IS_1216U_EQ_1216(...) \, +#define Z_IS_1216_EQ_1216U(...) \, +#define Z_IS_1216U_EQ_1216U(...) \, +#define Z_IS_1217_EQ_1217(...) \, +#define Z_IS_1217U_EQ_1217(...) \, +#define Z_IS_1217_EQ_1217U(...) \, +#define Z_IS_1217U_EQ_1217U(...) \, +#define Z_IS_1218_EQ_1218(...) \, +#define Z_IS_1218U_EQ_1218(...) \, +#define Z_IS_1218_EQ_1218U(...) \, +#define Z_IS_1218U_EQ_1218U(...) \, +#define Z_IS_1219_EQ_1219(...) \, +#define Z_IS_1219U_EQ_1219(...) \, +#define Z_IS_1219_EQ_1219U(...) \, +#define Z_IS_1219U_EQ_1219U(...) \, +#define Z_IS_1220_EQ_1220(...) \, +#define Z_IS_1220U_EQ_1220(...) \, +#define Z_IS_1220_EQ_1220U(...) \, +#define Z_IS_1220U_EQ_1220U(...) \, +#define Z_IS_1221_EQ_1221(...) \, +#define Z_IS_1221U_EQ_1221(...) \, +#define Z_IS_1221_EQ_1221U(...) \, +#define Z_IS_1221U_EQ_1221U(...) \, +#define Z_IS_1222_EQ_1222(...) \, +#define Z_IS_1222U_EQ_1222(...) \, +#define Z_IS_1222_EQ_1222U(...) \, +#define Z_IS_1222U_EQ_1222U(...) \, +#define Z_IS_1223_EQ_1223(...) \, +#define Z_IS_1223U_EQ_1223(...) \, +#define Z_IS_1223_EQ_1223U(...) \, +#define Z_IS_1223U_EQ_1223U(...) \, +#define Z_IS_1224_EQ_1224(...) \, +#define Z_IS_1224U_EQ_1224(...) \, +#define Z_IS_1224_EQ_1224U(...) \, +#define Z_IS_1224U_EQ_1224U(...) \, +#define Z_IS_1225_EQ_1225(...) \, +#define Z_IS_1225U_EQ_1225(...) \, +#define Z_IS_1225_EQ_1225U(...) \, +#define Z_IS_1225U_EQ_1225U(...) \, +#define Z_IS_1226_EQ_1226(...) \, +#define Z_IS_1226U_EQ_1226(...) \, +#define Z_IS_1226_EQ_1226U(...) \, +#define Z_IS_1226U_EQ_1226U(...) \, +#define Z_IS_1227_EQ_1227(...) \, +#define Z_IS_1227U_EQ_1227(...) \, +#define Z_IS_1227_EQ_1227U(...) \, +#define Z_IS_1227U_EQ_1227U(...) \, +#define Z_IS_1228_EQ_1228(...) \, +#define Z_IS_1228U_EQ_1228(...) \, +#define Z_IS_1228_EQ_1228U(...) \, +#define Z_IS_1228U_EQ_1228U(...) \, +#define Z_IS_1229_EQ_1229(...) \, +#define Z_IS_1229U_EQ_1229(...) \, +#define Z_IS_1229_EQ_1229U(...) \, +#define Z_IS_1229U_EQ_1229U(...) \, +#define Z_IS_1230_EQ_1230(...) \, +#define Z_IS_1230U_EQ_1230(...) \, +#define Z_IS_1230_EQ_1230U(...) \, +#define Z_IS_1230U_EQ_1230U(...) \, +#define Z_IS_1231_EQ_1231(...) \, +#define Z_IS_1231U_EQ_1231(...) \, +#define Z_IS_1231_EQ_1231U(...) \, +#define Z_IS_1231U_EQ_1231U(...) \, +#define Z_IS_1232_EQ_1232(...) \, +#define Z_IS_1232U_EQ_1232(...) \, +#define Z_IS_1232_EQ_1232U(...) \, +#define Z_IS_1232U_EQ_1232U(...) \, +#define Z_IS_1233_EQ_1233(...) \, +#define Z_IS_1233U_EQ_1233(...) \, +#define Z_IS_1233_EQ_1233U(...) \, +#define Z_IS_1233U_EQ_1233U(...) \, +#define Z_IS_1234_EQ_1234(...) \, +#define Z_IS_1234U_EQ_1234(...) \, +#define Z_IS_1234_EQ_1234U(...) \, +#define Z_IS_1234U_EQ_1234U(...) \, +#define Z_IS_1235_EQ_1235(...) \, +#define Z_IS_1235U_EQ_1235(...) \, +#define Z_IS_1235_EQ_1235U(...) \, +#define Z_IS_1235U_EQ_1235U(...) \, +#define Z_IS_1236_EQ_1236(...) \, +#define Z_IS_1236U_EQ_1236(...) \, +#define Z_IS_1236_EQ_1236U(...) \, +#define Z_IS_1236U_EQ_1236U(...) \, +#define Z_IS_1237_EQ_1237(...) \, +#define Z_IS_1237U_EQ_1237(...) \, +#define Z_IS_1237_EQ_1237U(...) \, +#define Z_IS_1237U_EQ_1237U(...) \, +#define Z_IS_1238_EQ_1238(...) \, +#define Z_IS_1238U_EQ_1238(...) \, +#define Z_IS_1238_EQ_1238U(...) \, +#define Z_IS_1238U_EQ_1238U(...) \, +#define Z_IS_1239_EQ_1239(...) \, +#define Z_IS_1239U_EQ_1239(...) \, +#define Z_IS_1239_EQ_1239U(...) \, +#define Z_IS_1239U_EQ_1239U(...) \, +#define Z_IS_1240_EQ_1240(...) \, +#define Z_IS_1240U_EQ_1240(...) \, +#define Z_IS_1240_EQ_1240U(...) \, +#define Z_IS_1240U_EQ_1240U(...) \, +#define Z_IS_1241_EQ_1241(...) \, +#define Z_IS_1241U_EQ_1241(...) \, +#define Z_IS_1241_EQ_1241U(...) \, +#define Z_IS_1241U_EQ_1241U(...) \, +#define Z_IS_1242_EQ_1242(...) \, +#define Z_IS_1242U_EQ_1242(...) \, +#define Z_IS_1242_EQ_1242U(...) \, +#define Z_IS_1242U_EQ_1242U(...) \, +#define Z_IS_1243_EQ_1243(...) \, +#define Z_IS_1243U_EQ_1243(...) \, +#define Z_IS_1243_EQ_1243U(...) \, +#define Z_IS_1243U_EQ_1243U(...) \, +#define Z_IS_1244_EQ_1244(...) \, +#define Z_IS_1244U_EQ_1244(...) \, +#define Z_IS_1244_EQ_1244U(...) \, +#define Z_IS_1244U_EQ_1244U(...) \, +#define Z_IS_1245_EQ_1245(...) \, +#define Z_IS_1245U_EQ_1245(...) \, +#define Z_IS_1245_EQ_1245U(...) \, +#define Z_IS_1245U_EQ_1245U(...) \, +#define Z_IS_1246_EQ_1246(...) \, +#define Z_IS_1246U_EQ_1246(...) \, +#define Z_IS_1246_EQ_1246U(...) \, +#define Z_IS_1246U_EQ_1246U(...) \, +#define Z_IS_1247_EQ_1247(...) \, +#define Z_IS_1247U_EQ_1247(...) \, +#define Z_IS_1247_EQ_1247U(...) \, +#define Z_IS_1247U_EQ_1247U(...) \, +#define Z_IS_1248_EQ_1248(...) \, +#define Z_IS_1248U_EQ_1248(...) \, +#define Z_IS_1248_EQ_1248U(...) \, +#define Z_IS_1248U_EQ_1248U(...) \, +#define Z_IS_1249_EQ_1249(...) \, +#define Z_IS_1249U_EQ_1249(...) \, +#define Z_IS_1249_EQ_1249U(...) \, +#define Z_IS_1249U_EQ_1249U(...) \, +#define Z_IS_1250_EQ_1250(...) \, +#define Z_IS_1250U_EQ_1250(...) \, +#define Z_IS_1250_EQ_1250U(...) \, +#define Z_IS_1250U_EQ_1250U(...) \, +#define Z_IS_1251_EQ_1251(...) \, +#define Z_IS_1251U_EQ_1251(...) \, +#define Z_IS_1251_EQ_1251U(...) \, +#define Z_IS_1251U_EQ_1251U(...) \, +#define Z_IS_1252_EQ_1252(...) \, +#define Z_IS_1252U_EQ_1252(...) \, +#define Z_IS_1252_EQ_1252U(...) \, +#define Z_IS_1252U_EQ_1252U(...) \, +#define Z_IS_1253_EQ_1253(...) \, +#define Z_IS_1253U_EQ_1253(...) \, +#define Z_IS_1253_EQ_1253U(...) \, +#define Z_IS_1253U_EQ_1253U(...) \, +#define Z_IS_1254_EQ_1254(...) \, +#define Z_IS_1254U_EQ_1254(...) \, +#define Z_IS_1254_EQ_1254U(...) \, +#define Z_IS_1254U_EQ_1254U(...) \, +#define Z_IS_1255_EQ_1255(...) \, +#define Z_IS_1255U_EQ_1255(...) \, +#define Z_IS_1255_EQ_1255U(...) \, +#define Z_IS_1255U_EQ_1255U(...) \, +#define Z_IS_1256_EQ_1256(...) \, +#define Z_IS_1256U_EQ_1256(...) \, +#define Z_IS_1256_EQ_1256U(...) \, +#define Z_IS_1256U_EQ_1256U(...) \, +#define Z_IS_1257_EQ_1257(...) \, +#define Z_IS_1257U_EQ_1257(...) \, +#define Z_IS_1257_EQ_1257U(...) \, +#define Z_IS_1257U_EQ_1257U(...) \, +#define Z_IS_1258_EQ_1258(...) \, +#define Z_IS_1258U_EQ_1258(...) \, +#define Z_IS_1258_EQ_1258U(...) \, +#define Z_IS_1258U_EQ_1258U(...) \, +#define Z_IS_1259_EQ_1259(...) \, +#define Z_IS_1259U_EQ_1259(...) \, +#define Z_IS_1259_EQ_1259U(...) \, +#define Z_IS_1259U_EQ_1259U(...) \, +#define Z_IS_1260_EQ_1260(...) \, +#define Z_IS_1260U_EQ_1260(...) \, +#define Z_IS_1260_EQ_1260U(...) \, +#define Z_IS_1260U_EQ_1260U(...) \, +#define Z_IS_1261_EQ_1261(...) \, +#define Z_IS_1261U_EQ_1261(...) \, +#define Z_IS_1261_EQ_1261U(...) \, +#define Z_IS_1261U_EQ_1261U(...) \, +#define Z_IS_1262_EQ_1262(...) \, +#define Z_IS_1262U_EQ_1262(...) \, +#define Z_IS_1262_EQ_1262U(...) \, +#define Z_IS_1262U_EQ_1262U(...) \, +#define Z_IS_1263_EQ_1263(...) \, +#define Z_IS_1263U_EQ_1263(...) \, +#define Z_IS_1263_EQ_1263U(...) \, +#define Z_IS_1263U_EQ_1263U(...) \, +#define Z_IS_1264_EQ_1264(...) \, +#define Z_IS_1264U_EQ_1264(...) \, +#define Z_IS_1264_EQ_1264U(...) \, +#define Z_IS_1264U_EQ_1264U(...) \, +#define Z_IS_1265_EQ_1265(...) \, +#define Z_IS_1265U_EQ_1265(...) \, +#define Z_IS_1265_EQ_1265U(...) \, +#define Z_IS_1265U_EQ_1265U(...) \, +#define Z_IS_1266_EQ_1266(...) \, +#define Z_IS_1266U_EQ_1266(...) \, +#define Z_IS_1266_EQ_1266U(...) \, +#define Z_IS_1266U_EQ_1266U(...) \, +#define Z_IS_1267_EQ_1267(...) \, +#define Z_IS_1267U_EQ_1267(...) \, +#define Z_IS_1267_EQ_1267U(...) \, +#define Z_IS_1267U_EQ_1267U(...) \, +#define Z_IS_1268_EQ_1268(...) \, +#define Z_IS_1268U_EQ_1268(...) \, +#define Z_IS_1268_EQ_1268U(...) \, +#define Z_IS_1268U_EQ_1268U(...) \, +#define Z_IS_1269_EQ_1269(...) \, +#define Z_IS_1269U_EQ_1269(...) \, +#define Z_IS_1269_EQ_1269U(...) \, +#define Z_IS_1269U_EQ_1269U(...) \, +#define Z_IS_1270_EQ_1270(...) \, +#define Z_IS_1270U_EQ_1270(...) \, +#define Z_IS_1270_EQ_1270U(...) \, +#define Z_IS_1270U_EQ_1270U(...) \, +#define Z_IS_1271_EQ_1271(...) \, +#define Z_IS_1271U_EQ_1271(...) \, +#define Z_IS_1271_EQ_1271U(...) \, +#define Z_IS_1271U_EQ_1271U(...) \, +#define Z_IS_1272_EQ_1272(...) \, +#define Z_IS_1272U_EQ_1272(...) \, +#define Z_IS_1272_EQ_1272U(...) \, +#define Z_IS_1272U_EQ_1272U(...) \, +#define Z_IS_1273_EQ_1273(...) \, +#define Z_IS_1273U_EQ_1273(...) \, +#define Z_IS_1273_EQ_1273U(...) \, +#define Z_IS_1273U_EQ_1273U(...) \, +#define Z_IS_1274_EQ_1274(...) \, +#define Z_IS_1274U_EQ_1274(...) \, +#define Z_IS_1274_EQ_1274U(...) \, +#define Z_IS_1274U_EQ_1274U(...) \, +#define Z_IS_1275_EQ_1275(...) \, +#define Z_IS_1275U_EQ_1275(...) \, +#define Z_IS_1275_EQ_1275U(...) \, +#define Z_IS_1275U_EQ_1275U(...) \, +#define Z_IS_1276_EQ_1276(...) \, +#define Z_IS_1276U_EQ_1276(...) \, +#define Z_IS_1276_EQ_1276U(...) \, +#define Z_IS_1276U_EQ_1276U(...) \, +#define Z_IS_1277_EQ_1277(...) \, +#define Z_IS_1277U_EQ_1277(...) \, +#define Z_IS_1277_EQ_1277U(...) \, +#define Z_IS_1277U_EQ_1277U(...) \, +#define Z_IS_1278_EQ_1278(...) \, +#define Z_IS_1278U_EQ_1278(...) \, +#define Z_IS_1278_EQ_1278U(...) \, +#define Z_IS_1278U_EQ_1278U(...) \, +#define Z_IS_1279_EQ_1279(...) \, +#define Z_IS_1279U_EQ_1279(...) \, +#define Z_IS_1279_EQ_1279U(...) \, +#define Z_IS_1279U_EQ_1279U(...) \, +#define Z_IS_1280_EQ_1280(...) \, +#define Z_IS_1280U_EQ_1280(...) \, +#define Z_IS_1280_EQ_1280U(...) \, +#define Z_IS_1280U_EQ_1280U(...) \, +#define Z_IS_1281_EQ_1281(...) \, +#define Z_IS_1281U_EQ_1281(...) \, +#define Z_IS_1281_EQ_1281U(...) \, +#define Z_IS_1281U_EQ_1281U(...) \, +#define Z_IS_1282_EQ_1282(...) \, +#define Z_IS_1282U_EQ_1282(...) \, +#define Z_IS_1282_EQ_1282U(...) \, +#define Z_IS_1282U_EQ_1282U(...) \, +#define Z_IS_1283_EQ_1283(...) \, +#define Z_IS_1283U_EQ_1283(...) \, +#define Z_IS_1283_EQ_1283U(...) \, +#define Z_IS_1283U_EQ_1283U(...) \, +#define Z_IS_1284_EQ_1284(...) \, +#define Z_IS_1284U_EQ_1284(...) \, +#define Z_IS_1284_EQ_1284U(...) \, +#define Z_IS_1284U_EQ_1284U(...) \, +#define Z_IS_1285_EQ_1285(...) \, +#define Z_IS_1285U_EQ_1285(...) \, +#define Z_IS_1285_EQ_1285U(...) \, +#define Z_IS_1285U_EQ_1285U(...) \, +#define Z_IS_1286_EQ_1286(...) \, +#define Z_IS_1286U_EQ_1286(...) \, +#define Z_IS_1286_EQ_1286U(...) \, +#define Z_IS_1286U_EQ_1286U(...) \, +#define Z_IS_1287_EQ_1287(...) \, +#define Z_IS_1287U_EQ_1287(...) \, +#define Z_IS_1287_EQ_1287U(...) \, +#define Z_IS_1287U_EQ_1287U(...) \, +#define Z_IS_1288_EQ_1288(...) \, +#define Z_IS_1288U_EQ_1288(...) \, +#define Z_IS_1288_EQ_1288U(...) \, +#define Z_IS_1288U_EQ_1288U(...) \, +#define Z_IS_1289_EQ_1289(...) \, +#define Z_IS_1289U_EQ_1289(...) \, +#define Z_IS_1289_EQ_1289U(...) \, +#define Z_IS_1289U_EQ_1289U(...) \, +#define Z_IS_1290_EQ_1290(...) \, +#define Z_IS_1290U_EQ_1290(...) \, +#define Z_IS_1290_EQ_1290U(...) \, +#define Z_IS_1290U_EQ_1290U(...) \, +#define Z_IS_1291_EQ_1291(...) \, +#define Z_IS_1291U_EQ_1291(...) \, +#define Z_IS_1291_EQ_1291U(...) \, +#define Z_IS_1291U_EQ_1291U(...) \, +#define Z_IS_1292_EQ_1292(...) \, +#define Z_IS_1292U_EQ_1292(...) \, +#define Z_IS_1292_EQ_1292U(...) \, +#define Z_IS_1292U_EQ_1292U(...) \, +#define Z_IS_1293_EQ_1293(...) \, +#define Z_IS_1293U_EQ_1293(...) \, +#define Z_IS_1293_EQ_1293U(...) \, +#define Z_IS_1293U_EQ_1293U(...) \, +#define Z_IS_1294_EQ_1294(...) \, +#define Z_IS_1294U_EQ_1294(...) \, +#define Z_IS_1294_EQ_1294U(...) \, +#define Z_IS_1294U_EQ_1294U(...) \, +#define Z_IS_1295_EQ_1295(...) \, +#define Z_IS_1295U_EQ_1295(...) \, +#define Z_IS_1295_EQ_1295U(...) \, +#define Z_IS_1295U_EQ_1295U(...) \, +#define Z_IS_1296_EQ_1296(...) \, +#define Z_IS_1296U_EQ_1296(...) \, +#define Z_IS_1296_EQ_1296U(...) \, +#define Z_IS_1296U_EQ_1296U(...) \, +#define Z_IS_1297_EQ_1297(...) \, +#define Z_IS_1297U_EQ_1297(...) \, +#define Z_IS_1297_EQ_1297U(...) \, +#define Z_IS_1297U_EQ_1297U(...) \, +#define Z_IS_1298_EQ_1298(...) \, +#define Z_IS_1298U_EQ_1298(...) \, +#define Z_IS_1298_EQ_1298U(...) \, +#define Z_IS_1298U_EQ_1298U(...) \, +#define Z_IS_1299_EQ_1299(...) \, +#define Z_IS_1299U_EQ_1299(...) \, +#define Z_IS_1299_EQ_1299U(...) \, +#define Z_IS_1299U_EQ_1299U(...) \, +#define Z_IS_1300_EQ_1300(...) \, +#define Z_IS_1300U_EQ_1300(...) \, +#define Z_IS_1300_EQ_1300U(...) \, +#define Z_IS_1300U_EQ_1300U(...) \, +#define Z_IS_1301_EQ_1301(...) \, +#define Z_IS_1301U_EQ_1301(...) \, +#define Z_IS_1301_EQ_1301U(...) \, +#define Z_IS_1301U_EQ_1301U(...) \, +#define Z_IS_1302_EQ_1302(...) \, +#define Z_IS_1302U_EQ_1302(...) \, +#define Z_IS_1302_EQ_1302U(...) \, +#define Z_IS_1302U_EQ_1302U(...) \, +#define Z_IS_1303_EQ_1303(...) \, +#define Z_IS_1303U_EQ_1303(...) \, +#define Z_IS_1303_EQ_1303U(...) \, +#define Z_IS_1303U_EQ_1303U(...) \, +#define Z_IS_1304_EQ_1304(...) \, +#define Z_IS_1304U_EQ_1304(...) \, +#define Z_IS_1304_EQ_1304U(...) \, +#define Z_IS_1304U_EQ_1304U(...) \, +#define Z_IS_1305_EQ_1305(...) \, +#define Z_IS_1305U_EQ_1305(...) \, +#define Z_IS_1305_EQ_1305U(...) \, +#define Z_IS_1305U_EQ_1305U(...) \, +#define Z_IS_1306_EQ_1306(...) \, +#define Z_IS_1306U_EQ_1306(...) \, +#define Z_IS_1306_EQ_1306U(...) \, +#define Z_IS_1306U_EQ_1306U(...) \, +#define Z_IS_1307_EQ_1307(...) \, +#define Z_IS_1307U_EQ_1307(...) \, +#define Z_IS_1307_EQ_1307U(...) \, +#define Z_IS_1307U_EQ_1307U(...) \, +#define Z_IS_1308_EQ_1308(...) \, +#define Z_IS_1308U_EQ_1308(...) \, +#define Z_IS_1308_EQ_1308U(...) \, +#define Z_IS_1308U_EQ_1308U(...) \, +#define Z_IS_1309_EQ_1309(...) \, +#define Z_IS_1309U_EQ_1309(...) \, +#define Z_IS_1309_EQ_1309U(...) \, +#define Z_IS_1309U_EQ_1309U(...) \, +#define Z_IS_1310_EQ_1310(...) \, +#define Z_IS_1310U_EQ_1310(...) \, +#define Z_IS_1310_EQ_1310U(...) \, +#define Z_IS_1310U_EQ_1310U(...) \, +#define Z_IS_1311_EQ_1311(...) \, +#define Z_IS_1311U_EQ_1311(...) \, +#define Z_IS_1311_EQ_1311U(...) \, +#define Z_IS_1311U_EQ_1311U(...) \, +#define Z_IS_1312_EQ_1312(...) \, +#define Z_IS_1312U_EQ_1312(...) \, +#define Z_IS_1312_EQ_1312U(...) \, +#define Z_IS_1312U_EQ_1312U(...) \, +#define Z_IS_1313_EQ_1313(...) \, +#define Z_IS_1313U_EQ_1313(...) \, +#define Z_IS_1313_EQ_1313U(...) \, +#define Z_IS_1313U_EQ_1313U(...) \, +#define Z_IS_1314_EQ_1314(...) \, +#define Z_IS_1314U_EQ_1314(...) \, +#define Z_IS_1314_EQ_1314U(...) \, +#define Z_IS_1314U_EQ_1314U(...) \, +#define Z_IS_1315_EQ_1315(...) \, +#define Z_IS_1315U_EQ_1315(...) \, +#define Z_IS_1315_EQ_1315U(...) \, +#define Z_IS_1315U_EQ_1315U(...) \, +#define Z_IS_1316_EQ_1316(...) \, +#define Z_IS_1316U_EQ_1316(...) \, +#define Z_IS_1316_EQ_1316U(...) \, +#define Z_IS_1316U_EQ_1316U(...) \, +#define Z_IS_1317_EQ_1317(...) \, +#define Z_IS_1317U_EQ_1317(...) \, +#define Z_IS_1317_EQ_1317U(...) \, +#define Z_IS_1317U_EQ_1317U(...) \, +#define Z_IS_1318_EQ_1318(...) \, +#define Z_IS_1318U_EQ_1318(...) \, +#define Z_IS_1318_EQ_1318U(...) \, +#define Z_IS_1318U_EQ_1318U(...) \, +#define Z_IS_1319_EQ_1319(...) \, +#define Z_IS_1319U_EQ_1319(...) \, +#define Z_IS_1319_EQ_1319U(...) \, +#define Z_IS_1319U_EQ_1319U(...) \, +#define Z_IS_1320_EQ_1320(...) \, +#define Z_IS_1320U_EQ_1320(...) \, +#define Z_IS_1320_EQ_1320U(...) \, +#define Z_IS_1320U_EQ_1320U(...) \, +#define Z_IS_1321_EQ_1321(...) \, +#define Z_IS_1321U_EQ_1321(...) \, +#define Z_IS_1321_EQ_1321U(...) \, +#define Z_IS_1321U_EQ_1321U(...) \, +#define Z_IS_1322_EQ_1322(...) \, +#define Z_IS_1322U_EQ_1322(...) \, +#define Z_IS_1322_EQ_1322U(...) \, +#define Z_IS_1322U_EQ_1322U(...) \, +#define Z_IS_1323_EQ_1323(...) \, +#define Z_IS_1323U_EQ_1323(...) \, +#define Z_IS_1323_EQ_1323U(...) \, +#define Z_IS_1323U_EQ_1323U(...) \, +#define Z_IS_1324_EQ_1324(...) \, +#define Z_IS_1324U_EQ_1324(...) \, +#define Z_IS_1324_EQ_1324U(...) \, +#define Z_IS_1324U_EQ_1324U(...) \, +#define Z_IS_1325_EQ_1325(...) \, +#define Z_IS_1325U_EQ_1325(...) \, +#define Z_IS_1325_EQ_1325U(...) \, +#define Z_IS_1325U_EQ_1325U(...) \, +#define Z_IS_1326_EQ_1326(...) \, +#define Z_IS_1326U_EQ_1326(...) \, +#define Z_IS_1326_EQ_1326U(...) \, +#define Z_IS_1326U_EQ_1326U(...) \, +#define Z_IS_1327_EQ_1327(...) \, +#define Z_IS_1327U_EQ_1327(...) \, +#define Z_IS_1327_EQ_1327U(...) \, +#define Z_IS_1327U_EQ_1327U(...) \, +#define Z_IS_1328_EQ_1328(...) \, +#define Z_IS_1328U_EQ_1328(...) \, +#define Z_IS_1328_EQ_1328U(...) \, +#define Z_IS_1328U_EQ_1328U(...) \, +#define Z_IS_1329_EQ_1329(...) \, +#define Z_IS_1329U_EQ_1329(...) \, +#define Z_IS_1329_EQ_1329U(...) \, +#define Z_IS_1329U_EQ_1329U(...) \, +#define Z_IS_1330_EQ_1330(...) \, +#define Z_IS_1330U_EQ_1330(...) \, +#define Z_IS_1330_EQ_1330U(...) \, +#define Z_IS_1330U_EQ_1330U(...) \, +#define Z_IS_1331_EQ_1331(...) \, +#define Z_IS_1331U_EQ_1331(...) \, +#define Z_IS_1331_EQ_1331U(...) \, +#define Z_IS_1331U_EQ_1331U(...) \, +#define Z_IS_1332_EQ_1332(...) \, +#define Z_IS_1332U_EQ_1332(...) \, +#define Z_IS_1332_EQ_1332U(...) \, +#define Z_IS_1332U_EQ_1332U(...) \, +#define Z_IS_1333_EQ_1333(...) \, +#define Z_IS_1333U_EQ_1333(...) \, +#define Z_IS_1333_EQ_1333U(...) \, +#define Z_IS_1333U_EQ_1333U(...) \, +#define Z_IS_1334_EQ_1334(...) \, +#define Z_IS_1334U_EQ_1334(...) \, +#define Z_IS_1334_EQ_1334U(...) \, +#define Z_IS_1334U_EQ_1334U(...) \, +#define Z_IS_1335_EQ_1335(...) \, +#define Z_IS_1335U_EQ_1335(...) \, +#define Z_IS_1335_EQ_1335U(...) \, +#define Z_IS_1335U_EQ_1335U(...) \, +#define Z_IS_1336_EQ_1336(...) \, +#define Z_IS_1336U_EQ_1336(...) \, +#define Z_IS_1336_EQ_1336U(...) \, +#define Z_IS_1336U_EQ_1336U(...) \, +#define Z_IS_1337_EQ_1337(...) \, +#define Z_IS_1337U_EQ_1337(...) \, +#define Z_IS_1337_EQ_1337U(...) \, +#define Z_IS_1337U_EQ_1337U(...) \, +#define Z_IS_1338_EQ_1338(...) \, +#define Z_IS_1338U_EQ_1338(...) \, +#define Z_IS_1338_EQ_1338U(...) \, +#define Z_IS_1338U_EQ_1338U(...) \, +#define Z_IS_1339_EQ_1339(...) \, +#define Z_IS_1339U_EQ_1339(...) \, +#define Z_IS_1339_EQ_1339U(...) \, +#define Z_IS_1339U_EQ_1339U(...) \, +#define Z_IS_1340_EQ_1340(...) \, +#define Z_IS_1340U_EQ_1340(...) \, +#define Z_IS_1340_EQ_1340U(...) \, +#define Z_IS_1340U_EQ_1340U(...) \, +#define Z_IS_1341_EQ_1341(...) \, +#define Z_IS_1341U_EQ_1341(...) \, +#define Z_IS_1341_EQ_1341U(...) \, +#define Z_IS_1341U_EQ_1341U(...) \, +#define Z_IS_1342_EQ_1342(...) \, +#define Z_IS_1342U_EQ_1342(...) \, +#define Z_IS_1342_EQ_1342U(...) \, +#define Z_IS_1342U_EQ_1342U(...) \, +#define Z_IS_1343_EQ_1343(...) \, +#define Z_IS_1343U_EQ_1343(...) \, +#define Z_IS_1343_EQ_1343U(...) \, +#define Z_IS_1343U_EQ_1343U(...) \, +#define Z_IS_1344_EQ_1344(...) \, +#define Z_IS_1344U_EQ_1344(...) \, +#define Z_IS_1344_EQ_1344U(...) \, +#define Z_IS_1344U_EQ_1344U(...) \, +#define Z_IS_1345_EQ_1345(...) \, +#define Z_IS_1345U_EQ_1345(...) \, +#define Z_IS_1345_EQ_1345U(...) \, +#define Z_IS_1345U_EQ_1345U(...) \, +#define Z_IS_1346_EQ_1346(...) \, +#define Z_IS_1346U_EQ_1346(...) \, +#define Z_IS_1346_EQ_1346U(...) \, +#define Z_IS_1346U_EQ_1346U(...) \, +#define Z_IS_1347_EQ_1347(...) \, +#define Z_IS_1347U_EQ_1347(...) \, +#define Z_IS_1347_EQ_1347U(...) \, +#define Z_IS_1347U_EQ_1347U(...) \, +#define Z_IS_1348_EQ_1348(...) \, +#define Z_IS_1348U_EQ_1348(...) \, +#define Z_IS_1348_EQ_1348U(...) \, +#define Z_IS_1348U_EQ_1348U(...) \, +#define Z_IS_1349_EQ_1349(...) \, +#define Z_IS_1349U_EQ_1349(...) \, +#define Z_IS_1349_EQ_1349U(...) \, +#define Z_IS_1349U_EQ_1349U(...) \, +#define Z_IS_1350_EQ_1350(...) \, +#define Z_IS_1350U_EQ_1350(...) \, +#define Z_IS_1350_EQ_1350U(...) \, +#define Z_IS_1350U_EQ_1350U(...) \, +#define Z_IS_1351_EQ_1351(...) \, +#define Z_IS_1351U_EQ_1351(...) \, +#define Z_IS_1351_EQ_1351U(...) \, +#define Z_IS_1351U_EQ_1351U(...) \, +#define Z_IS_1352_EQ_1352(...) \, +#define Z_IS_1352U_EQ_1352(...) \, +#define Z_IS_1352_EQ_1352U(...) \, +#define Z_IS_1352U_EQ_1352U(...) \, +#define Z_IS_1353_EQ_1353(...) \, +#define Z_IS_1353U_EQ_1353(...) \, +#define Z_IS_1353_EQ_1353U(...) \, +#define Z_IS_1353U_EQ_1353U(...) \, +#define Z_IS_1354_EQ_1354(...) \, +#define Z_IS_1354U_EQ_1354(...) \, +#define Z_IS_1354_EQ_1354U(...) \, +#define Z_IS_1354U_EQ_1354U(...) \, +#define Z_IS_1355_EQ_1355(...) \, +#define Z_IS_1355U_EQ_1355(...) \, +#define Z_IS_1355_EQ_1355U(...) \, +#define Z_IS_1355U_EQ_1355U(...) \, +#define Z_IS_1356_EQ_1356(...) \, +#define Z_IS_1356U_EQ_1356(...) \, +#define Z_IS_1356_EQ_1356U(...) \, +#define Z_IS_1356U_EQ_1356U(...) \, +#define Z_IS_1357_EQ_1357(...) \, +#define Z_IS_1357U_EQ_1357(...) \, +#define Z_IS_1357_EQ_1357U(...) \, +#define Z_IS_1357U_EQ_1357U(...) \, +#define Z_IS_1358_EQ_1358(...) \, +#define Z_IS_1358U_EQ_1358(...) \, +#define Z_IS_1358_EQ_1358U(...) \, +#define Z_IS_1358U_EQ_1358U(...) \, +#define Z_IS_1359_EQ_1359(...) \, +#define Z_IS_1359U_EQ_1359(...) \, +#define Z_IS_1359_EQ_1359U(...) \, +#define Z_IS_1359U_EQ_1359U(...) \, +#define Z_IS_1360_EQ_1360(...) \, +#define Z_IS_1360U_EQ_1360(...) \, +#define Z_IS_1360_EQ_1360U(...) \, +#define Z_IS_1360U_EQ_1360U(...) \, +#define Z_IS_1361_EQ_1361(...) \, +#define Z_IS_1361U_EQ_1361(...) \, +#define Z_IS_1361_EQ_1361U(...) \, +#define Z_IS_1361U_EQ_1361U(...) \, +#define Z_IS_1362_EQ_1362(...) \, +#define Z_IS_1362U_EQ_1362(...) \, +#define Z_IS_1362_EQ_1362U(...) \, +#define Z_IS_1362U_EQ_1362U(...) \, +#define Z_IS_1363_EQ_1363(...) \, +#define Z_IS_1363U_EQ_1363(...) \, +#define Z_IS_1363_EQ_1363U(...) \, +#define Z_IS_1363U_EQ_1363U(...) \, +#define Z_IS_1364_EQ_1364(...) \, +#define Z_IS_1364U_EQ_1364(...) \, +#define Z_IS_1364_EQ_1364U(...) \, +#define Z_IS_1364U_EQ_1364U(...) \, +#define Z_IS_1365_EQ_1365(...) \, +#define Z_IS_1365U_EQ_1365(...) \, +#define Z_IS_1365_EQ_1365U(...) \, +#define Z_IS_1365U_EQ_1365U(...) \, +#define Z_IS_1366_EQ_1366(...) \, +#define Z_IS_1366U_EQ_1366(...) \, +#define Z_IS_1366_EQ_1366U(...) \, +#define Z_IS_1366U_EQ_1366U(...) \, +#define Z_IS_1367_EQ_1367(...) \, +#define Z_IS_1367U_EQ_1367(...) \, +#define Z_IS_1367_EQ_1367U(...) \, +#define Z_IS_1367U_EQ_1367U(...) \, +#define Z_IS_1368_EQ_1368(...) \, +#define Z_IS_1368U_EQ_1368(...) \, +#define Z_IS_1368_EQ_1368U(...) \, +#define Z_IS_1368U_EQ_1368U(...) \, +#define Z_IS_1369_EQ_1369(...) \, +#define Z_IS_1369U_EQ_1369(...) \, +#define Z_IS_1369_EQ_1369U(...) \, +#define Z_IS_1369U_EQ_1369U(...) \, +#define Z_IS_1370_EQ_1370(...) \, +#define Z_IS_1370U_EQ_1370(...) \, +#define Z_IS_1370_EQ_1370U(...) \, +#define Z_IS_1370U_EQ_1370U(...) \, +#define Z_IS_1371_EQ_1371(...) \, +#define Z_IS_1371U_EQ_1371(...) \, +#define Z_IS_1371_EQ_1371U(...) \, +#define Z_IS_1371U_EQ_1371U(...) \, +#define Z_IS_1372_EQ_1372(...) \, +#define Z_IS_1372U_EQ_1372(...) \, +#define Z_IS_1372_EQ_1372U(...) \, +#define Z_IS_1372U_EQ_1372U(...) \, +#define Z_IS_1373_EQ_1373(...) \, +#define Z_IS_1373U_EQ_1373(...) \, +#define Z_IS_1373_EQ_1373U(...) \, +#define Z_IS_1373U_EQ_1373U(...) \, +#define Z_IS_1374_EQ_1374(...) \, +#define Z_IS_1374U_EQ_1374(...) \, +#define Z_IS_1374_EQ_1374U(...) \, +#define Z_IS_1374U_EQ_1374U(...) \, +#define Z_IS_1375_EQ_1375(...) \, +#define Z_IS_1375U_EQ_1375(...) \, +#define Z_IS_1375_EQ_1375U(...) \, +#define Z_IS_1375U_EQ_1375U(...) \, +#define Z_IS_1376_EQ_1376(...) \, +#define Z_IS_1376U_EQ_1376(...) \, +#define Z_IS_1376_EQ_1376U(...) \, +#define Z_IS_1376U_EQ_1376U(...) \, +#define Z_IS_1377_EQ_1377(...) \, +#define Z_IS_1377U_EQ_1377(...) \, +#define Z_IS_1377_EQ_1377U(...) \, +#define Z_IS_1377U_EQ_1377U(...) \, +#define Z_IS_1378_EQ_1378(...) \, +#define Z_IS_1378U_EQ_1378(...) \, +#define Z_IS_1378_EQ_1378U(...) \, +#define Z_IS_1378U_EQ_1378U(...) \, +#define Z_IS_1379_EQ_1379(...) \, +#define Z_IS_1379U_EQ_1379(...) \, +#define Z_IS_1379_EQ_1379U(...) \, +#define Z_IS_1379U_EQ_1379U(...) \, +#define Z_IS_1380_EQ_1380(...) \, +#define Z_IS_1380U_EQ_1380(...) \, +#define Z_IS_1380_EQ_1380U(...) \, +#define Z_IS_1380U_EQ_1380U(...) \, +#define Z_IS_1381_EQ_1381(...) \, +#define Z_IS_1381U_EQ_1381(...) \, +#define Z_IS_1381_EQ_1381U(...) \, +#define Z_IS_1381U_EQ_1381U(...) \, +#define Z_IS_1382_EQ_1382(...) \, +#define Z_IS_1382U_EQ_1382(...) \, +#define Z_IS_1382_EQ_1382U(...) \, +#define Z_IS_1382U_EQ_1382U(...) \, +#define Z_IS_1383_EQ_1383(...) \, +#define Z_IS_1383U_EQ_1383(...) \, +#define Z_IS_1383_EQ_1383U(...) \, +#define Z_IS_1383U_EQ_1383U(...) \, +#define Z_IS_1384_EQ_1384(...) \, +#define Z_IS_1384U_EQ_1384(...) \, +#define Z_IS_1384_EQ_1384U(...) \, +#define Z_IS_1384U_EQ_1384U(...) \, +#define Z_IS_1385_EQ_1385(...) \, +#define Z_IS_1385U_EQ_1385(...) \, +#define Z_IS_1385_EQ_1385U(...) \, +#define Z_IS_1385U_EQ_1385U(...) \, +#define Z_IS_1386_EQ_1386(...) \, +#define Z_IS_1386U_EQ_1386(...) \, +#define Z_IS_1386_EQ_1386U(...) \, +#define Z_IS_1386U_EQ_1386U(...) \, +#define Z_IS_1387_EQ_1387(...) \, +#define Z_IS_1387U_EQ_1387(...) \, +#define Z_IS_1387_EQ_1387U(...) \, +#define Z_IS_1387U_EQ_1387U(...) \, +#define Z_IS_1388_EQ_1388(...) \, +#define Z_IS_1388U_EQ_1388(...) \, +#define Z_IS_1388_EQ_1388U(...) \, +#define Z_IS_1388U_EQ_1388U(...) \, +#define Z_IS_1389_EQ_1389(...) \, +#define Z_IS_1389U_EQ_1389(...) \, +#define Z_IS_1389_EQ_1389U(...) \, +#define Z_IS_1389U_EQ_1389U(...) \, +#define Z_IS_1390_EQ_1390(...) \, +#define Z_IS_1390U_EQ_1390(...) \, +#define Z_IS_1390_EQ_1390U(...) \, +#define Z_IS_1390U_EQ_1390U(...) \, +#define Z_IS_1391_EQ_1391(...) \, +#define Z_IS_1391U_EQ_1391(...) \, +#define Z_IS_1391_EQ_1391U(...) \, +#define Z_IS_1391U_EQ_1391U(...) \, +#define Z_IS_1392_EQ_1392(...) \, +#define Z_IS_1392U_EQ_1392(...) \, +#define Z_IS_1392_EQ_1392U(...) \, +#define Z_IS_1392U_EQ_1392U(...) \, +#define Z_IS_1393_EQ_1393(...) \, +#define Z_IS_1393U_EQ_1393(...) \, +#define Z_IS_1393_EQ_1393U(...) \, +#define Z_IS_1393U_EQ_1393U(...) \, +#define Z_IS_1394_EQ_1394(...) \, +#define Z_IS_1394U_EQ_1394(...) \, +#define Z_IS_1394_EQ_1394U(...) \, +#define Z_IS_1394U_EQ_1394U(...) \, +#define Z_IS_1395_EQ_1395(...) \, +#define Z_IS_1395U_EQ_1395(...) \, +#define Z_IS_1395_EQ_1395U(...) \, +#define Z_IS_1395U_EQ_1395U(...) \, +#define Z_IS_1396_EQ_1396(...) \, +#define Z_IS_1396U_EQ_1396(...) \, +#define Z_IS_1396_EQ_1396U(...) \, +#define Z_IS_1396U_EQ_1396U(...) \, +#define Z_IS_1397_EQ_1397(...) \, +#define Z_IS_1397U_EQ_1397(...) \, +#define Z_IS_1397_EQ_1397U(...) \, +#define Z_IS_1397U_EQ_1397U(...) \, +#define Z_IS_1398_EQ_1398(...) \, +#define Z_IS_1398U_EQ_1398(...) \, +#define Z_IS_1398_EQ_1398U(...) \, +#define Z_IS_1398U_EQ_1398U(...) \, +#define Z_IS_1399_EQ_1399(...) \, +#define Z_IS_1399U_EQ_1399(...) \, +#define Z_IS_1399_EQ_1399U(...) \, +#define Z_IS_1399U_EQ_1399U(...) \, +#define Z_IS_1400_EQ_1400(...) \, +#define Z_IS_1400U_EQ_1400(...) \, +#define Z_IS_1400_EQ_1400U(...) \, +#define Z_IS_1400U_EQ_1400U(...) \, +#define Z_IS_1401_EQ_1401(...) \, +#define Z_IS_1401U_EQ_1401(...) \, +#define Z_IS_1401_EQ_1401U(...) \, +#define Z_IS_1401U_EQ_1401U(...) \, +#define Z_IS_1402_EQ_1402(...) \, +#define Z_IS_1402U_EQ_1402(...) \, +#define Z_IS_1402_EQ_1402U(...) \, +#define Z_IS_1402U_EQ_1402U(...) \, +#define Z_IS_1403_EQ_1403(...) \, +#define Z_IS_1403U_EQ_1403(...) \, +#define Z_IS_1403_EQ_1403U(...) \, +#define Z_IS_1403U_EQ_1403U(...) \, +#define Z_IS_1404_EQ_1404(...) \, +#define Z_IS_1404U_EQ_1404(...) \, +#define Z_IS_1404_EQ_1404U(...) \, +#define Z_IS_1404U_EQ_1404U(...) \, +#define Z_IS_1405_EQ_1405(...) \, +#define Z_IS_1405U_EQ_1405(...) \, +#define Z_IS_1405_EQ_1405U(...) \, +#define Z_IS_1405U_EQ_1405U(...) \, +#define Z_IS_1406_EQ_1406(...) \, +#define Z_IS_1406U_EQ_1406(...) \, +#define Z_IS_1406_EQ_1406U(...) \, +#define Z_IS_1406U_EQ_1406U(...) \, +#define Z_IS_1407_EQ_1407(...) \, +#define Z_IS_1407U_EQ_1407(...) \, +#define Z_IS_1407_EQ_1407U(...) \, +#define Z_IS_1407U_EQ_1407U(...) \, +#define Z_IS_1408_EQ_1408(...) \, +#define Z_IS_1408U_EQ_1408(...) \, +#define Z_IS_1408_EQ_1408U(...) \, +#define Z_IS_1408U_EQ_1408U(...) \, +#define Z_IS_1409_EQ_1409(...) \, +#define Z_IS_1409U_EQ_1409(...) \, +#define Z_IS_1409_EQ_1409U(...) \, +#define Z_IS_1409U_EQ_1409U(...) \, +#define Z_IS_1410_EQ_1410(...) \, +#define Z_IS_1410U_EQ_1410(...) \, +#define Z_IS_1410_EQ_1410U(...) \, +#define Z_IS_1410U_EQ_1410U(...) \, +#define Z_IS_1411_EQ_1411(...) \, +#define Z_IS_1411U_EQ_1411(...) \, +#define Z_IS_1411_EQ_1411U(...) \, +#define Z_IS_1411U_EQ_1411U(...) \, +#define Z_IS_1412_EQ_1412(...) \, +#define Z_IS_1412U_EQ_1412(...) \, +#define Z_IS_1412_EQ_1412U(...) \, +#define Z_IS_1412U_EQ_1412U(...) \, +#define Z_IS_1413_EQ_1413(...) \, +#define Z_IS_1413U_EQ_1413(...) \, +#define Z_IS_1413_EQ_1413U(...) \, +#define Z_IS_1413U_EQ_1413U(...) \, +#define Z_IS_1414_EQ_1414(...) \, +#define Z_IS_1414U_EQ_1414(...) \, +#define Z_IS_1414_EQ_1414U(...) \, +#define Z_IS_1414U_EQ_1414U(...) \, +#define Z_IS_1415_EQ_1415(...) \, +#define Z_IS_1415U_EQ_1415(...) \, +#define Z_IS_1415_EQ_1415U(...) \, +#define Z_IS_1415U_EQ_1415U(...) \, +#define Z_IS_1416_EQ_1416(...) \, +#define Z_IS_1416U_EQ_1416(...) \, +#define Z_IS_1416_EQ_1416U(...) \, +#define Z_IS_1416U_EQ_1416U(...) \, +#define Z_IS_1417_EQ_1417(...) \, +#define Z_IS_1417U_EQ_1417(...) \, +#define Z_IS_1417_EQ_1417U(...) \, +#define Z_IS_1417U_EQ_1417U(...) \, +#define Z_IS_1418_EQ_1418(...) \, +#define Z_IS_1418U_EQ_1418(...) \, +#define Z_IS_1418_EQ_1418U(...) \, +#define Z_IS_1418U_EQ_1418U(...) \, +#define Z_IS_1419_EQ_1419(...) \, +#define Z_IS_1419U_EQ_1419(...) \, +#define Z_IS_1419_EQ_1419U(...) \, +#define Z_IS_1419U_EQ_1419U(...) \, +#define Z_IS_1420_EQ_1420(...) \, +#define Z_IS_1420U_EQ_1420(...) \, +#define Z_IS_1420_EQ_1420U(...) \, +#define Z_IS_1420U_EQ_1420U(...) \, +#define Z_IS_1421_EQ_1421(...) \, +#define Z_IS_1421U_EQ_1421(...) \, +#define Z_IS_1421_EQ_1421U(...) \, +#define Z_IS_1421U_EQ_1421U(...) \, +#define Z_IS_1422_EQ_1422(...) \, +#define Z_IS_1422U_EQ_1422(...) \, +#define Z_IS_1422_EQ_1422U(...) \, +#define Z_IS_1422U_EQ_1422U(...) \, +#define Z_IS_1423_EQ_1423(...) \, +#define Z_IS_1423U_EQ_1423(...) \, +#define Z_IS_1423_EQ_1423U(...) \, +#define Z_IS_1423U_EQ_1423U(...) \, +#define Z_IS_1424_EQ_1424(...) \, +#define Z_IS_1424U_EQ_1424(...) \, +#define Z_IS_1424_EQ_1424U(...) \, +#define Z_IS_1424U_EQ_1424U(...) \, +#define Z_IS_1425_EQ_1425(...) \, +#define Z_IS_1425U_EQ_1425(...) \, +#define Z_IS_1425_EQ_1425U(...) \, +#define Z_IS_1425U_EQ_1425U(...) \, +#define Z_IS_1426_EQ_1426(...) \, +#define Z_IS_1426U_EQ_1426(...) \, +#define Z_IS_1426_EQ_1426U(...) \, +#define Z_IS_1426U_EQ_1426U(...) \, +#define Z_IS_1427_EQ_1427(...) \, +#define Z_IS_1427U_EQ_1427(...) \, +#define Z_IS_1427_EQ_1427U(...) \, +#define Z_IS_1427U_EQ_1427U(...) \, +#define Z_IS_1428_EQ_1428(...) \, +#define Z_IS_1428U_EQ_1428(...) \, +#define Z_IS_1428_EQ_1428U(...) \, +#define Z_IS_1428U_EQ_1428U(...) \, +#define Z_IS_1429_EQ_1429(...) \, +#define Z_IS_1429U_EQ_1429(...) \, +#define Z_IS_1429_EQ_1429U(...) \, +#define Z_IS_1429U_EQ_1429U(...) \, +#define Z_IS_1430_EQ_1430(...) \, +#define Z_IS_1430U_EQ_1430(...) \, +#define Z_IS_1430_EQ_1430U(...) \, +#define Z_IS_1430U_EQ_1430U(...) \, +#define Z_IS_1431_EQ_1431(...) \, +#define Z_IS_1431U_EQ_1431(...) \, +#define Z_IS_1431_EQ_1431U(...) \, +#define Z_IS_1431U_EQ_1431U(...) \, +#define Z_IS_1432_EQ_1432(...) \, +#define Z_IS_1432U_EQ_1432(...) \, +#define Z_IS_1432_EQ_1432U(...) \, +#define Z_IS_1432U_EQ_1432U(...) \, +#define Z_IS_1433_EQ_1433(...) \, +#define Z_IS_1433U_EQ_1433(...) \, +#define Z_IS_1433_EQ_1433U(...) \, +#define Z_IS_1433U_EQ_1433U(...) \, +#define Z_IS_1434_EQ_1434(...) \, +#define Z_IS_1434U_EQ_1434(...) \, +#define Z_IS_1434_EQ_1434U(...) \, +#define Z_IS_1434U_EQ_1434U(...) \, +#define Z_IS_1435_EQ_1435(...) \, +#define Z_IS_1435U_EQ_1435(...) \, +#define Z_IS_1435_EQ_1435U(...) \, +#define Z_IS_1435U_EQ_1435U(...) \, +#define Z_IS_1436_EQ_1436(...) \, +#define Z_IS_1436U_EQ_1436(...) \, +#define Z_IS_1436_EQ_1436U(...) \, +#define Z_IS_1436U_EQ_1436U(...) \, +#define Z_IS_1437_EQ_1437(...) \, +#define Z_IS_1437U_EQ_1437(...) \, +#define Z_IS_1437_EQ_1437U(...) \, +#define Z_IS_1437U_EQ_1437U(...) \, +#define Z_IS_1438_EQ_1438(...) \, +#define Z_IS_1438U_EQ_1438(...) \, +#define Z_IS_1438_EQ_1438U(...) \, +#define Z_IS_1438U_EQ_1438U(...) \, +#define Z_IS_1439_EQ_1439(...) \, +#define Z_IS_1439U_EQ_1439(...) \, +#define Z_IS_1439_EQ_1439U(...) \, +#define Z_IS_1439U_EQ_1439U(...) \, +#define Z_IS_1440_EQ_1440(...) \, +#define Z_IS_1440U_EQ_1440(...) \, +#define Z_IS_1440_EQ_1440U(...) \, +#define Z_IS_1440U_EQ_1440U(...) \, +#define Z_IS_1441_EQ_1441(...) \, +#define Z_IS_1441U_EQ_1441(...) \, +#define Z_IS_1441_EQ_1441U(...) \, +#define Z_IS_1441U_EQ_1441U(...) \, +#define Z_IS_1442_EQ_1442(...) \, +#define Z_IS_1442U_EQ_1442(...) \, +#define Z_IS_1442_EQ_1442U(...) \, +#define Z_IS_1442U_EQ_1442U(...) \, +#define Z_IS_1443_EQ_1443(...) \, +#define Z_IS_1443U_EQ_1443(...) \, +#define Z_IS_1443_EQ_1443U(...) \, +#define Z_IS_1443U_EQ_1443U(...) \, +#define Z_IS_1444_EQ_1444(...) \, +#define Z_IS_1444U_EQ_1444(...) \, +#define Z_IS_1444_EQ_1444U(...) \, +#define Z_IS_1444U_EQ_1444U(...) \, +#define Z_IS_1445_EQ_1445(...) \, +#define Z_IS_1445U_EQ_1445(...) \, +#define Z_IS_1445_EQ_1445U(...) \, +#define Z_IS_1445U_EQ_1445U(...) \, +#define Z_IS_1446_EQ_1446(...) \, +#define Z_IS_1446U_EQ_1446(...) \, +#define Z_IS_1446_EQ_1446U(...) \, +#define Z_IS_1446U_EQ_1446U(...) \, +#define Z_IS_1447_EQ_1447(...) \, +#define Z_IS_1447U_EQ_1447(...) \, +#define Z_IS_1447_EQ_1447U(...) \, +#define Z_IS_1447U_EQ_1447U(...) \, +#define Z_IS_1448_EQ_1448(...) \, +#define Z_IS_1448U_EQ_1448(...) \, +#define Z_IS_1448_EQ_1448U(...) \, +#define Z_IS_1448U_EQ_1448U(...) \, +#define Z_IS_1449_EQ_1449(...) \, +#define Z_IS_1449U_EQ_1449(...) \, +#define Z_IS_1449_EQ_1449U(...) \, +#define Z_IS_1449U_EQ_1449U(...) \, +#define Z_IS_1450_EQ_1450(...) \, +#define Z_IS_1450U_EQ_1450(...) \, +#define Z_IS_1450_EQ_1450U(...) \, +#define Z_IS_1450U_EQ_1450U(...) \, +#define Z_IS_1451_EQ_1451(...) \, +#define Z_IS_1451U_EQ_1451(...) \, +#define Z_IS_1451_EQ_1451U(...) \, +#define Z_IS_1451U_EQ_1451U(...) \, +#define Z_IS_1452_EQ_1452(...) \, +#define Z_IS_1452U_EQ_1452(...) \, +#define Z_IS_1452_EQ_1452U(...) \, +#define Z_IS_1452U_EQ_1452U(...) \, +#define Z_IS_1453_EQ_1453(...) \, +#define Z_IS_1453U_EQ_1453(...) \, +#define Z_IS_1453_EQ_1453U(...) \, +#define Z_IS_1453U_EQ_1453U(...) \, +#define Z_IS_1454_EQ_1454(...) \, +#define Z_IS_1454U_EQ_1454(...) \, +#define Z_IS_1454_EQ_1454U(...) \, +#define Z_IS_1454U_EQ_1454U(...) \, +#define Z_IS_1455_EQ_1455(...) \, +#define Z_IS_1455U_EQ_1455(...) \, +#define Z_IS_1455_EQ_1455U(...) \, +#define Z_IS_1455U_EQ_1455U(...) \, +#define Z_IS_1456_EQ_1456(...) \, +#define Z_IS_1456U_EQ_1456(...) \, +#define Z_IS_1456_EQ_1456U(...) \, +#define Z_IS_1456U_EQ_1456U(...) \, +#define Z_IS_1457_EQ_1457(...) \, +#define Z_IS_1457U_EQ_1457(...) \, +#define Z_IS_1457_EQ_1457U(...) \, +#define Z_IS_1457U_EQ_1457U(...) \, +#define Z_IS_1458_EQ_1458(...) \, +#define Z_IS_1458U_EQ_1458(...) \, +#define Z_IS_1458_EQ_1458U(...) \, +#define Z_IS_1458U_EQ_1458U(...) \, +#define Z_IS_1459_EQ_1459(...) \, +#define Z_IS_1459U_EQ_1459(...) \, +#define Z_IS_1459_EQ_1459U(...) \, +#define Z_IS_1459U_EQ_1459U(...) \, +#define Z_IS_1460_EQ_1460(...) \, +#define Z_IS_1460U_EQ_1460(...) \, +#define Z_IS_1460_EQ_1460U(...) \, +#define Z_IS_1460U_EQ_1460U(...) \, +#define Z_IS_1461_EQ_1461(...) \, +#define Z_IS_1461U_EQ_1461(...) \, +#define Z_IS_1461_EQ_1461U(...) \, +#define Z_IS_1461U_EQ_1461U(...) \, +#define Z_IS_1462_EQ_1462(...) \, +#define Z_IS_1462U_EQ_1462(...) \, +#define Z_IS_1462_EQ_1462U(...) \, +#define Z_IS_1462U_EQ_1462U(...) \, +#define Z_IS_1463_EQ_1463(...) \, +#define Z_IS_1463U_EQ_1463(...) \, +#define Z_IS_1463_EQ_1463U(...) \, +#define Z_IS_1463U_EQ_1463U(...) \, +#define Z_IS_1464_EQ_1464(...) \, +#define Z_IS_1464U_EQ_1464(...) \, +#define Z_IS_1464_EQ_1464U(...) \, +#define Z_IS_1464U_EQ_1464U(...) \, +#define Z_IS_1465_EQ_1465(...) \, +#define Z_IS_1465U_EQ_1465(...) \, +#define Z_IS_1465_EQ_1465U(...) \, +#define Z_IS_1465U_EQ_1465U(...) \, +#define Z_IS_1466_EQ_1466(...) \, +#define Z_IS_1466U_EQ_1466(...) \, +#define Z_IS_1466_EQ_1466U(...) \, +#define Z_IS_1466U_EQ_1466U(...) \, +#define Z_IS_1467_EQ_1467(...) \, +#define Z_IS_1467U_EQ_1467(...) \, +#define Z_IS_1467_EQ_1467U(...) \, +#define Z_IS_1467U_EQ_1467U(...) \, +#define Z_IS_1468_EQ_1468(...) \, +#define Z_IS_1468U_EQ_1468(...) \, +#define Z_IS_1468_EQ_1468U(...) \, +#define Z_IS_1468U_EQ_1468U(...) \, +#define Z_IS_1469_EQ_1469(...) \, +#define Z_IS_1469U_EQ_1469(...) \, +#define Z_IS_1469_EQ_1469U(...) \, +#define Z_IS_1469U_EQ_1469U(...) \, +#define Z_IS_1470_EQ_1470(...) \, +#define Z_IS_1470U_EQ_1470(...) \, +#define Z_IS_1470_EQ_1470U(...) \, +#define Z_IS_1470U_EQ_1470U(...) \, +#define Z_IS_1471_EQ_1471(...) \, +#define Z_IS_1471U_EQ_1471(...) \, +#define Z_IS_1471_EQ_1471U(...) \, +#define Z_IS_1471U_EQ_1471U(...) \, +#define Z_IS_1472_EQ_1472(...) \, +#define Z_IS_1472U_EQ_1472(...) \, +#define Z_IS_1472_EQ_1472U(...) \, +#define Z_IS_1472U_EQ_1472U(...) \, +#define Z_IS_1473_EQ_1473(...) \, +#define Z_IS_1473U_EQ_1473(...) \, +#define Z_IS_1473_EQ_1473U(...) \, +#define Z_IS_1473U_EQ_1473U(...) \, +#define Z_IS_1474_EQ_1474(...) \, +#define Z_IS_1474U_EQ_1474(...) \, +#define Z_IS_1474_EQ_1474U(...) \, +#define Z_IS_1474U_EQ_1474U(...) \, +#define Z_IS_1475_EQ_1475(...) \, +#define Z_IS_1475U_EQ_1475(...) \, +#define Z_IS_1475_EQ_1475U(...) \, +#define Z_IS_1475U_EQ_1475U(...) \, +#define Z_IS_1476_EQ_1476(...) \, +#define Z_IS_1476U_EQ_1476(...) \, +#define Z_IS_1476_EQ_1476U(...) \, +#define Z_IS_1476U_EQ_1476U(...) \, +#define Z_IS_1477_EQ_1477(...) \, +#define Z_IS_1477U_EQ_1477(...) \, +#define Z_IS_1477_EQ_1477U(...) \, +#define Z_IS_1477U_EQ_1477U(...) \, +#define Z_IS_1478_EQ_1478(...) \, +#define Z_IS_1478U_EQ_1478(...) \, +#define Z_IS_1478_EQ_1478U(...) \, +#define Z_IS_1478U_EQ_1478U(...) \, +#define Z_IS_1479_EQ_1479(...) \, +#define Z_IS_1479U_EQ_1479(...) \, +#define Z_IS_1479_EQ_1479U(...) \, +#define Z_IS_1479U_EQ_1479U(...) \, +#define Z_IS_1480_EQ_1480(...) \, +#define Z_IS_1480U_EQ_1480(...) \, +#define Z_IS_1480_EQ_1480U(...) \, +#define Z_IS_1480U_EQ_1480U(...) \, +#define Z_IS_1481_EQ_1481(...) \, +#define Z_IS_1481U_EQ_1481(...) \, +#define Z_IS_1481_EQ_1481U(...) \, +#define Z_IS_1481U_EQ_1481U(...) \, +#define Z_IS_1482_EQ_1482(...) \, +#define Z_IS_1482U_EQ_1482(...) \, +#define Z_IS_1482_EQ_1482U(...) \, +#define Z_IS_1482U_EQ_1482U(...) \, +#define Z_IS_1483_EQ_1483(...) \, +#define Z_IS_1483U_EQ_1483(...) \, +#define Z_IS_1483_EQ_1483U(...) \, +#define Z_IS_1483U_EQ_1483U(...) \, +#define Z_IS_1484_EQ_1484(...) \, +#define Z_IS_1484U_EQ_1484(...) \, +#define Z_IS_1484_EQ_1484U(...) \, +#define Z_IS_1484U_EQ_1484U(...) \, +#define Z_IS_1485_EQ_1485(...) \, +#define Z_IS_1485U_EQ_1485(...) \, +#define Z_IS_1485_EQ_1485U(...) \, +#define Z_IS_1485U_EQ_1485U(...) \, +#define Z_IS_1486_EQ_1486(...) \, +#define Z_IS_1486U_EQ_1486(...) \, +#define Z_IS_1486_EQ_1486U(...) \, +#define Z_IS_1486U_EQ_1486U(...) \, +#define Z_IS_1487_EQ_1487(...) \, +#define Z_IS_1487U_EQ_1487(...) \, +#define Z_IS_1487_EQ_1487U(...) \, +#define Z_IS_1487U_EQ_1487U(...) \, +#define Z_IS_1488_EQ_1488(...) \, +#define Z_IS_1488U_EQ_1488(...) \, +#define Z_IS_1488_EQ_1488U(...) \, +#define Z_IS_1488U_EQ_1488U(...) \, +#define Z_IS_1489_EQ_1489(...) \, +#define Z_IS_1489U_EQ_1489(...) \, +#define Z_IS_1489_EQ_1489U(...) \, +#define Z_IS_1489U_EQ_1489U(...) \, +#define Z_IS_1490_EQ_1490(...) \, +#define Z_IS_1490U_EQ_1490(...) \, +#define Z_IS_1490_EQ_1490U(...) \, +#define Z_IS_1490U_EQ_1490U(...) \, +#define Z_IS_1491_EQ_1491(...) \, +#define Z_IS_1491U_EQ_1491(...) \, +#define Z_IS_1491_EQ_1491U(...) \, +#define Z_IS_1491U_EQ_1491U(...) \, +#define Z_IS_1492_EQ_1492(...) \, +#define Z_IS_1492U_EQ_1492(...) \, +#define Z_IS_1492_EQ_1492U(...) \, +#define Z_IS_1492U_EQ_1492U(...) \, +#define Z_IS_1493_EQ_1493(...) \, +#define Z_IS_1493U_EQ_1493(...) \, +#define Z_IS_1493_EQ_1493U(...) \, +#define Z_IS_1493U_EQ_1493U(...) \, +#define Z_IS_1494_EQ_1494(...) \, +#define Z_IS_1494U_EQ_1494(...) \, +#define Z_IS_1494_EQ_1494U(...) \, +#define Z_IS_1494U_EQ_1494U(...) \, +#define Z_IS_1495_EQ_1495(...) \, +#define Z_IS_1495U_EQ_1495(...) \, +#define Z_IS_1495_EQ_1495U(...) \, +#define Z_IS_1495U_EQ_1495U(...) \, +#define Z_IS_1496_EQ_1496(...) \, +#define Z_IS_1496U_EQ_1496(...) \, +#define Z_IS_1496_EQ_1496U(...) \, +#define Z_IS_1496U_EQ_1496U(...) \, +#define Z_IS_1497_EQ_1497(...) \, +#define Z_IS_1497U_EQ_1497(...) \, +#define Z_IS_1497_EQ_1497U(...) \, +#define Z_IS_1497U_EQ_1497U(...) \, +#define Z_IS_1498_EQ_1498(...) \, +#define Z_IS_1498U_EQ_1498(...) \, +#define Z_IS_1498_EQ_1498U(...) \, +#define Z_IS_1498U_EQ_1498U(...) \, +#define Z_IS_1499_EQ_1499(...) \, +#define Z_IS_1499U_EQ_1499(...) \, +#define Z_IS_1499_EQ_1499U(...) \, +#define Z_IS_1499U_EQ_1499U(...) \, +#define Z_IS_1500_EQ_1500(...) \, +#define Z_IS_1500U_EQ_1500(...) \, +#define Z_IS_1500_EQ_1500U(...) \, +#define Z_IS_1500U_EQ_1500U(...) \, +#define Z_IS_1501_EQ_1501(...) \, +#define Z_IS_1501U_EQ_1501(...) \, +#define Z_IS_1501_EQ_1501U(...) \, +#define Z_IS_1501U_EQ_1501U(...) \, +#define Z_IS_1502_EQ_1502(...) \, +#define Z_IS_1502U_EQ_1502(...) \, +#define Z_IS_1502_EQ_1502U(...) \, +#define Z_IS_1502U_EQ_1502U(...) \, +#define Z_IS_1503_EQ_1503(...) \, +#define Z_IS_1503U_EQ_1503(...) \, +#define Z_IS_1503_EQ_1503U(...) \, +#define Z_IS_1503U_EQ_1503U(...) \, +#define Z_IS_1504_EQ_1504(...) \, +#define Z_IS_1504U_EQ_1504(...) \, +#define Z_IS_1504_EQ_1504U(...) \, +#define Z_IS_1504U_EQ_1504U(...) \, +#define Z_IS_1505_EQ_1505(...) \, +#define Z_IS_1505U_EQ_1505(...) \, +#define Z_IS_1505_EQ_1505U(...) \, +#define Z_IS_1505U_EQ_1505U(...) \, +#define Z_IS_1506_EQ_1506(...) \, +#define Z_IS_1506U_EQ_1506(...) \, +#define Z_IS_1506_EQ_1506U(...) \, +#define Z_IS_1506U_EQ_1506U(...) \, +#define Z_IS_1507_EQ_1507(...) \, +#define Z_IS_1507U_EQ_1507(...) \, +#define Z_IS_1507_EQ_1507U(...) \, +#define Z_IS_1507U_EQ_1507U(...) \, +#define Z_IS_1508_EQ_1508(...) \, +#define Z_IS_1508U_EQ_1508(...) \, +#define Z_IS_1508_EQ_1508U(...) \, +#define Z_IS_1508U_EQ_1508U(...) \, +#define Z_IS_1509_EQ_1509(...) \, +#define Z_IS_1509U_EQ_1509(...) \, +#define Z_IS_1509_EQ_1509U(...) \, +#define Z_IS_1509U_EQ_1509U(...) \, +#define Z_IS_1510_EQ_1510(...) \, +#define Z_IS_1510U_EQ_1510(...) \, +#define Z_IS_1510_EQ_1510U(...) \, +#define Z_IS_1510U_EQ_1510U(...) \, +#define Z_IS_1511_EQ_1511(...) \, +#define Z_IS_1511U_EQ_1511(...) \, +#define Z_IS_1511_EQ_1511U(...) \, +#define Z_IS_1511U_EQ_1511U(...) \, +#define Z_IS_1512_EQ_1512(...) \, +#define Z_IS_1512U_EQ_1512(...) \, +#define Z_IS_1512_EQ_1512U(...) \, +#define Z_IS_1512U_EQ_1512U(...) \, +#define Z_IS_1513_EQ_1513(...) \, +#define Z_IS_1513U_EQ_1513(...) \, +#define Z_IS_1513_EQ_1513U(...) \, +#define Z_IS_1513U_EQ_1513U(...) \, +#define Z_IS_1514_EQ_1514(...) \, +#define Z_IS_1514U_EQ_1514(...) \, +#define Z_IS_1514_EQ_1514U(...) \, +#define Z_IS_1514U_EQ_1514U(...) \, +#define Z_IS_1515_EQ_1515(...) \, +#define Z_IS_1515U_EQ_1515(...) \, +#define Z_IS_1515_EQ_1515U(...) \, +#define Z_IS_1515U_EQ_1515U(...) \, +#define Z_IS_1516_EQ_1516(...) \, +#define Z_IS_1516U_EQ_1516(...) \, +#define Z_IS_1516_EQ_1516U(...) \, +#define Z_IS_1516U_EQ_1516U(...) \, +#define Z_IS_1517_EQ_1517(...) \, +#define Z_IS_1517U_EQ_1517(...) \, +#define Z_IS_1517_EQ_1517U(...) \, +#define Z_IS_1517U_EQ_1517U(...) \, +#define Z_IS_1518_EQ_1518(...) \, +#define Z_IS_1518U_EQ_1518(...) \, +#define Z_IS_1518_EQ_1518U(...) \, +#define Z_IS_1518U_EQ_1518U(...) \, +#define Z_IS_1519_EQ_1519(...) \, +#define Z_IS_1519U_EQ_1519(...) \, +#define Z_IS_1519_EQ_1519U(...) \, +#define Z_IS_1519U_EQ_1519U(...) \, +#define Z_IS_1520_EQ_1520(...) \, +#define Z_IS_1520U_EQ_1520(...) \, +#define Z_IS_1520_EQ_1520U(...) \, +#define Z_IS_1520U_EQ_1520U(...) \, +#define Z_IS_1521_EQ_1521(...) \, +#define Z_IS_1521U_EQ_1521(...) \, +#define Z_IS_1521_EQ_1521U(...) \, +#define Z_IS_1521U_EQ_1521U(...) \, +#define Z_IS_1522_EQ_1522(...) \, +#define Z_IS_1522U_EQ_1522(...) \, +#define Z_IS_1522_EQ_1522U(...) \, +#define Z_IS_1522U_EQ_1522U(...) \, +#define Z_IS_1523_EQ_1523(...) \, +#define Z_IS_1523U_EQ_1523(...) \, +#define Z_IS_1523_EQ_1523U(...) \, +#define Z_IS_1523U_EQ_1523U(...) \, +#define Z_IS_1524_EQ_1524(...) \, +#define Z_IS_1524U_EQ_1524(...) \, +#define Z_IS_1524_EQ_1524U(...) \, +#define Z_IS_1524U_EQ_1524U(...) \, +#define Z_IS_1525_EQ_1525(...) \, +#define Z_IS_1525U_EQ_1525(...) \, +#define Z_IS_1525_EQ_1525U(...) \, +#define Z_IS_1525U_EQ_1525U(...) \, +#define Z_IS_1526_EQ_1526(...) \, +#define Z_IS_1526U_EQ_1526(...) \, +#define Z_IS_1526_EQ_1526U(...) \, +#define Z_IS_1526U_EQ_1526U(...) \, +#define Z_IS_1527_EQ_1527(...) \, +#define Z_IS_1527U_EQ_1527(...) \, +#define Z_IS_1527_EQ_1527U(...) \, +#define Z_IS_1527U_EQ_1527U(...) \, +#define Z_IS_1528_EQ_1528(...) \, +#define Z_IS_1528U_EQ_1528(...) \, +#define Z_IS_1528_EQ_1528U(...) \, +#define Z_IS_1528U_EQ_1528U(...) \, +#define Z_IS_1529_EQ_1529(...) \, +#define Z_IS_1529U_EQ_1529(...) \, +#define Z_IS_1529_EQ_1529U(...) \, +#define Z_IS_1529U_EQ_1529U(...) \, +#define Z_IS_1530_EQ_1530(...) \, +#define Z_IS_1530U_EQ_1530(...) \, +#define Z_IS_1530_EQ_1530U(...) \, +#define Z_IS_1530U_EQ_1530U(...) \, +#define Z_IS_1531_EQ_1531(...) \, +#define Z_IS_1531U_EQ_1531(...) \, +#define Z_IS_1531_EQ_1531U(...) \, +#define Z_IS_1531U_EQ_1531U(...) \, +#define Z_IS_1532_EQ_1532(...) \, +#define Z_IS_1532U_EQ_1532(...) \, +#define Z_IS_1532_EQ_1532U(...) \, +#define Z_IS_1532U_EQ_1532U(...) \, +#define Z_IS_1533_EQ_1533(...) \, +#define Z_IS_1533U_EQ_1533(...) \, +#define Z_IS_1533_EQ_1533U(...) \, +#define Z_IS_1533U_EQ_1533U(...) \, +#define Z_IS_1534_EQ_1534(...) \, +#define Z_IS_1534U_EQ_1534(...) \, +#define Z_IS_1534_EQ_1534U(...) \, +#define Z_IS_1534U_EQ_1534U(...) \, +#define Z_IS_1535_EQ_1535(...) \, +#define Z_IS_1535U_EQ_1535(...) \, +#define Z_IS_1535_EQ_1535U(...) \, +#define Z_IS_1535U_EQ_1535U(...) \, +#define Z_IS_1536_EQ_1536(...) \, +#define Z_IS_1536U_EQ_1536(...) \, +#define Z_IS_1536_EQ_1536U(...) \, +#define Z_IS_1536U_EQ_1536U(...) \, +#define Z_IS_1537_EQ_1537(...) \, +#define Z_IS_1537U_EQ_1537(...) \, +#define Z_IS_1537_EQ_1537U(...) \, +#define Z_IS_1537U_EQ_1537U(...) \, +#define Z_IS_1538_EQ_1538(...) \, +#define Z_IS_1538U_EQ_1538(...) \, +#define Z_IS_1538_EQ_1538U(...) \, +#define Z_IS_1538U_EQ_1538U(...) \, +#define Z_IS_1539_EQ_1539(...) \, +#define Z_IS_1539U_EQ_1539(...) \, +#define Z_IS_1539_EQ_1539U(...) \, +#define Z_IS_1539U_EQ_1539U(...) \, +#define Z_IS_1540_EQ_1540(...) \, +#define Z_IS_1540U_EQ_1540(...) \, +#define Z_IS_1540_EQ_1540U(...) \, +#define Z_IS_1540U_EQ_1540U(...) \, +#define Z_IS_1541_EQ_1541(...) \, +#define Z_IS_1541U_EQ_1541(...) \, +#define Z_IS_1541_EQ_1541U(...) \, +#define Z_IS_1541U_EQ_1541U(...) \, +#define Z_IS_1542_EQ_1542(...) \, +#define Z_IS_1542U_EQ_1542(...) \, +#define Z_IS_1542_EQ_1542U(...) \, +#define Z_IS_1542U_EQ_1542U(...) \, +#define Z_IS_1543_EQ_1543(...) \, +#define Z_IS_1543U_EQ_1543(...) \, +#define Z_IS_1543_EQ_1543U(...) \, +#define Z_IS_1543U_EQ_1543U(...) \, +#define Z_IS_1544_EQ_1544(...) \, +#define Z_IS_1544U_EQ_1544(...) \, +#define Z_IS_1544_EQ_1544U(...) \, +#define Z_IS_1544U_EQ_1544U(...) \, +#define Z_IS_1545_EQ_1545(...) \, +#define Z_IS_1545U_EQ_1545(...) \, +#define Z_IS_1545_EQ_1545U(...) \, +#define Z_IS_1545U_EQ_1545U(...) \, +#define Z_IS_1546_EQ_1546(...) \, +#define Z_IS_1546U_EQ_1546(...) \, +#define Z_IS_1546_EQ_1546U(...) \, +#define Z_IS_1546U_EQ_1546U(...) \, +#define Z_IS_1547_EQ_1547(...) \, +#define Z_IS_1547U_EQ_1547(...) \, +#define Z_IS_1547_EQ_1547U(...) \, +#define Z_IS_1547U_EQ_1547U(...) \, +#define Z_IS_1548_EQ_1548(...) \, +#define Z_IS_1548U_EQ_1548(...) \, +#define Z_IS_1548_EQ_1548U(...) \, +#define Z_IS_1548U_EQ_1548U(...) \, +#define Z_IS_1549_EQ_1549(...) \, +#define Z_IS_1549U_EQ_1549(...) \, +#define Z_IS_1549_EQ_1549U(...) \, +#define Z_IS_1549U_EQ_1549U(...) \, +#define Z_IS_1550_EQ_1550(...) \, +#define Z_IS_1550U_EQ_1550(...) \, +#define Z_IS_1550_EQ_1550U(...) \, +#define Z_IS_1550U_EQ_1550U(...) \, +#define Z_IS_1551_EQ_1551(...) \, +#define Z_IS_1551U_EQ_1551(...) \, +#define Z_IS_1551_EQ_1551U(...) \, +#define Z_IS_1551U_EQ_1551U(...) \, +#define Z_IS_1552_EQ_1552(...) \, +#define Z_IS_1552U_EQ_1552(...) \, +#define Z_IS_1552_EQ_1552U(...) \, +#define Z_IS_1552U_EQ_1552U(...) \, +#define Z_IS_1553_EQ_1553(...) \, +#define Z_IS_1553U_EQ_1553(...) \, +#define Z_IS_1553_EQ_1553U(...) \, +#define Z_IS_1553U_EQ_1553U(...) \, +#define Z_IS_1554_EQ_1554(...) \, +#define Z_IS_1554U_EQ_1554(...) \, +#define Z_IS_1554_EQ_1554U(...) \, +#define Z_IS_1554U_EQ_1554U(...) \, +#define Z_IS_1555_EQ_1555(...) \, +#define Z_IS_1555U_EQ_1555(...) \, +#define Z_IS_1555_EQ_1555U(...) \, +#define Z_IS_1555U_EQ_1555U(...) \, +#define Z_IS_1556_EQ_1556(...) \, +#define Z_IS_1556U_EQ_1556(...) \, +#define Z_IS_1556_EQ_1556U(...) \, +#define Z_IS_1556U_EQ_1556U(...) \, +#define Z_IS_1557_EQ_1557(...) \, +#define Z_IS_1557U_EQ_1557(...) \, +#define Z_IS_1557_EQ_1557U(...) \, +#define Z_IS_1557U_EQ_1557U(...) \, +#define Z_IS_1558_EQ_1558(...) \, +#define Z_IS_1558U_EQ_1558(...) \, +#define Z_IS_1558_EQ_1558U(...) \, +#define Z_IS_1558U_EQ_1558U(...) \, +#define Z_IS_1559_EQ_1559(...) \, +#define Z_IS_1559U_EQ_1559(...) \, +#define Z_IS_1559_EQ_1559U(...) \, +#define Z_IS_1559U_EQ_1559U(...) \, +#define Z_IS_1560_EQ_1560(...) \, +#define Z_IS_1560U_EQ_1560(...) \, +#define Z_IS_1560_EQ_1560U(...) \, +#define Z_IS_1560U_EQ_1560U(...) \, +#define Z_IS_1561_EQ_1561(...) \, +#define Z_IS_1561U_EQ_1561(...) \, +#define Z_IS_1561_EQ_1561U(...) \, +#define Z_IS_1561U_EQ_1561U(...) \, +#define Z_IS_1562_EQ_1562(...) \, +#define Z_IS_1562U_EQ_1562(...) \, +#define Z_IS_1562_EQ_1562U(...) \, +#define Z_IS_1562U_EQ_1562U(...) \, +#define Z_IS_1563_EQ_1563(...) \, +#define Z_IS_1563U_EQ_1563(...) \, +#define Z_IS_1563_EQ_1563U(...) \, +#define Z_IS_1563U_EQ_1563U(...) \, +#define Z_IS_1564_EQ_1564(...) \, +#define Z_IS_1564U_EQ_1564(...) \, +#define Z_IS_1564_EQ_1564U(...) \, +#define Z_IS_1564U_EQ_1564U(...) \, +#define Z_IS_1565_EQ_1565(...) \, +#define Z_IS_1565U_EQ_1565(...) \, +#define Z_IS_1565_EQ_1565U(...) \, +#define Z_IS_1565U_EQ_1565U(...) \, +#define Z_IS_1566_EQ_1566(...) \, +#define Z_IS_1566U_EQ_1566(...) \, +#define Z_IS_1566_EQ_1566U(...) \, +#define Z_IS_1566U_EQ_1566U(...) \, +#define Z_IS_1567_EQ_1567(...) \, +#define Z_IS_1567U_EQ_1567(...) \, +#define Z_IS_1567_EQ_1567U(...) \, +#define Z_IS_1567U_EQ_1567U(...) \, +#define Z_IS_1568_EQ_1568(...) \, +#define Z_IS_1568U_EQ_1568(...) \, +#define Z_IS_1568_EQ_1568U(...) \, +#define Z_IS_1568U_EQ_1568U(...) \, +#define Z_IS_1569_EQ_1569(...) \, +#define Z_IS_1569U_EQ_1569(...) \, +#define Z_IS_1569_EQ_1569U(...) \, +#define Z_IS_1569U_EQ_1569U(...) \, +#define Z_IS_1570_EQ_1570(...) \, +#define Z_IS_1570U_EQ_1570(...) \, +#define Z_IS_1570_EQ_1570U(...) \, +#define Z_IS_1570U_EQ_1570U(...) \, +#define Z_IS_1571_EQ_1571(...) \, +#define Z_IS_1571U_EQ_1571(...) \, +#define Z_IS_1571_EQ_1571U(...) \, +#define Z_IS_1571U_EQ_1571U(...) \, +#define Z_IS_1572_EQ_1572(...) \, +#define Z_IS_1572U_EQ_1572(...) \, +#define Z_IS_1572_EQ_1572U(...) \, +#define Z_IS_1572U_EQ_1572U(...) \, +#define Z_IS_1573_EQ_1573(...) \, +#define Z_IS_1573U_EQ_1573(...) \, +#define Z_IS_1573_EQ_1573U(...) \, +#define Z_IS_1573U_EQ_1573U(...) \, +#define Z_IS_1574_EQ_1574(...) \, +#define Z_IS_1574U_EQ_1574(...) \, +#define Z_IS_1574_EQ_1574U(...) \, +#define Z_IS_1574U_EQ_1574U(...) \, +#define Z_IS_1575_EQ_1575(...) \, +#define Z_IS_1575U_EQ_1575(...) \, +#define Z_IS_1575_EQ_1575U(...) \, +#define Z_IS_1575U_EQ_1575U(...) \, +#define Z_IS_1576_EQ_1576(...) \, +#define Z_IS_1576U_EQ_1576(...) \, +#define Z_IS_1576_EQ_1576U(...) \, +#define Z_IS_1576U_EQ_1576U(...) \, +#define Z_IS_1577_EQ_1577(...) \, +#define Z_IS_1577U_EQ_1577(...) \, +#define Z_IS_1577_EQ_1577U(...) \, +#define Z_IS_1577U_EQ_1577U(...) \, +#define Z_IS_1578_EQ_1578(...) \, +#define Z_IS_1578U_EQ_1578(...) \, +#define Z_IS_1578_EQ_1578U(...) \, +#define Z_IS_1578U_EQ_1578U(...) \, +#define Z_IS_1579_EQ_1579(...) \, +#define Z_IS_1579U_EQ_1579(...) \, +#define Z_IS_1579_EQ_1579U(...) \, +#define Z_IS_1579U_EQ_1579U(...) \, +#define Z_IS_1580_EQ_1580(...) \, +#define Z_IS_1580U_EQ_1580(...) \, +#define Z_IS_1580_EQ_1580U(...) \, +#define Z_IS_1580U_EQ_1580U(...) \, +#define Z_IS_1581_EQ_1581(...) \, +#define Z_IS_1581U_EQ_1581(...) \, +#define Z_IS_1581_EQ_1581U(...) \, +#define Z_IS_1581U_EQ_1581U(...) \, +#define Z_IS_1582_EQ_1582(...) \, +#define Z_IS_1582U_EQ_1582(...) \, +#define Z_IS_1582_EQ_1582U(...) \, +#define Z_IS_1582U_EQ_1582U(...) \, +#define Z_IS_1583_EQ_1583(...) \, +#define Z_IS_1583U_EQ_1583(...) \, +#define Z_IS_1583_EQ_1583U(...) \, +#define Z_IS_1583U_EQ_1583U(...) \, +#define Z_IS_1584_EQ_1584(...) \, +#define Z_IS_1584U_EQ_1584(...) \, +#define Z_IS_1584_EQ_1584U(...) \, +#define Z_IS_1584U_EQ_1584U(...) \, +#define Z_IS_1585_EQ_1585(...) \, +#define Z_IS_1585U_EQ_1585(...) \, +#define Z_IS_1585_EQ_1585U(...) \, +#define Z_IS_1585U_EQ_1585U(...) \, +#define Z_IS_1586_EQ_1586(...) \, +#define Z_IS_1586U_EQ_1586(...) \, +#define Z_IS_1586_EQ_1586U(...) \, +#define Z_IS_1586U_EQ_1586U(...) \, +#define Z_IS_1587_EQ_1587(...) \, +#define Z_IS_1587U_EQ_1587(...) \, +#define Z_IS_1587_EQ_1587U(...) \, +#define Z_IS_1587U_EQ_1587U(...) \, +#define Z_IS_1588_EQ_1588(...) \, +#define Z_IS_1588U_EQ_1588(...) \, +#define Z_IS_1588_EQ_1588U(...) \, +#define Z_IS_1588U_EQ_1588U(...) \, +#define Z_IS_1589_EQ_1589(...) \, +#define Z_IS_1589U_EQ_1589(...) \, +#define Z_IS_1589_EQ_1589U(...) \, +#define Z_IS_1589U_EQ_1589U(...) \, +#define Z_IS_1590_EQ_1590(...) \, +#define Z_IS_1590U_EQ_1590(...) \, +#define Z_IS_1590_EQ_1590U(...) \, +#define Z_IS_1590U_EQ_1590U(...) \, +#define Z_IS_1591_EQ_1591(...) \, +#define Z_IS_1591U_EQ_1591(...) \, +#define Z_IS_1591_EQ_1591U(...) \, +#define Z_IS_1591U_EQ_1591U(...) \, +#define Z_IS_1592_EQ_1592(...) \, +#define Z_IS_1592U_EQ_1592(...) \, +#define Z_IS_1592_EQ_1592U(...) \, +#define Z_IS_1592U_EQ_1592U(...) \, +#define Z_IS_1593_EQ_1593(...) \, +#define Z_IS_1593U_EQ_1593(...) \, +#define Z_IS_1593_EQ_1593U(...) \, +#define Z_IS_1593U_EQ_1593U(...) \, +#define Z_IS_1594_EQ_1594(...) \, +#define Z_IS_1594U_EQ_1594(...) \, +#define Z_IS_1594_EQ_1594U(...) \, +#define Z_IS_1594U_EQ_1594U(...) \, +#define Z_IS_1595_EQ_1595(...) \, +#define Z_IS_1595U_EQ_1595(...) \, +#define Z_IS_1595_EQ_1595U(...) \, +#define Z_IS_1595U_EQ_1595U(...) \, +#define Z_IS_1596_EQ_1596(...) \, +#define Z_IS_1596U_EQ_1596(...) \, +#define Z_IS_1596_EQ_1596U(...) \, +#define Z_IS_1596U_EQ_1596U(...) \, +#define Z_IS_1597_EQ_1597(...) \, +#define Z_IS_1597U_EQ_1597(...) \, +#define Z_IS_1597_EQ_1597U(...) \, +#define Z_IS_1597U_EQ_1597U(...) \, +#define Z_IS_1598_EQ_1598(...) \, +#define Z_IS_1598U_EQ_1598(...) \, +#define Z_IS_1598_EQ_1598U(...) \, +#define Z_IS_1598U_EQ_1598U(...) \, +#define Z_IS_1599_EQ_1599(...) \, +#define Z_IS_1599U_EQ_1599(...) \, +#define Z_IS_1599_EQ_1599U(...) \, +#define Z_IS_1599U_EQ_1599U(...) \, +#define Z_IS_1600_EQ_1600(...) \, +#define Z_IS_1600U_EQ_1600(...) \, +#define Z_IS_1600_EQ_1600U(...) \, +#define Z_IS_1600U_EQ_1600U(...) \, +#define Z_IS_1601_EQ_1601(...) \, +#define Z_IS_1601U_EQ_1601(...) \, +#define Z_IS_1601_EQ_1601U(...) \, +#define Z_IS_1601U_EQ_1601U(...) \, +#define Z_IS_1602_EQ_1602(...) \, +#define Z_IS_1602U_EQ_1602(...) \, +#define Z_IS_1602_EQ_1602U(...) \, +#define Z_IS_1602U_EQ_1602U(...) \, +#define Z_IS_1603_EQ_1603(...) \, +#define Z_IS_1603U_EQ_1603(...) \, +#define Z_IS_1603_EQ_1603U(...) \, +#define Z_IS_1603U_EQ_1603U(...) \, +#define Z_IS_1604_EQ_1604(...) \, +#define Z_IS_1604U_EQ_1604(...) \, +#define Z_IS_1604_EQ_1604U(...) \, +#define Z_IS_1604U_EQ_1604U(...) \, +#define Z_IS_1605_EQ_1605(...) \, +#define Z_IS_1605U_EQ_1605(...) \, +#define Z_IS_1605_EQ_1605U(...) \, +#define Z_IS_1605U_EQ_1605U(...) \, +#define Z_IS_1606_EQ_1606(...) \, +#define Z_IS_1606U_EQ_1606(...) \, +#define Z_IS_1606_EQ_1606U(...) \, +#define Z_IS_1606U_EQ_1606U(...) \, +#define Z_IS_1607_EQ_1607(...) \, +#define Z_IS_1607U_EQ_1607(...) \, +#define Z_IS_1607_EQ_1607U(...) \, +#define Z_IS_1607U_EQ_1607U(...) \, +#define Z_IS_1608_EQ_1608(...) \, +#define Z_IS_1608U_EQ_1608(...) \, +#define Z_IS_1608_EQ_1608U(...) \, +#define Z_IS_1608U_EQ_1608U(...) \, +#define Z_IS_1609_EQ_1609(...) \, +#define Z_IS_1609U_EQ_1609(...) \, +#define Z_IS_1609_EQ_1609U(...) \, +#define Z_IS_1609U_EQ_1609U(...) \, +#define Z_IS_1610_EQ_1610(...) \, +#define Z_IS_1610U_EQ_1610(...) \, +#define Z_IS_1610_EQ_1610U(...) \, +#define Z_IS_1610U_EQ_1610U(...) \, +#define Z_IS_1611_EQ_1611(...) \, +#define Z_IS_1611U_EQ_1611(...) \, +#define Z_IS_1611_EQ_1611U(...) \, +#define Z_IS_1611U_EQ_1611U(...) \, +#define Z_IS_1612_EQ_1612(...) \, +#define Z_IS_1612U_EQ_1612(...) \, +#define Z_IS_1612_EQ_1612U(...) \, +#define Z_IS_1612U_EQ_1612U(...) \, +#define Z_IS_1613_EQ_1613(...) \, +#define Z_IS_1613U_EQ_1613(...) \, +#define Z_IS_1613_EQ_1613U(...) \, +#define Z_IS_1613U_EQ_1613U(...) \, +#define Z_IS_1614_EQ_1614(...) \, +#define Z_IS_1614U_EQ_1614(...) \, +#define Z_IS_1614_EQ_1614U(...) \, +#define Z_IS_1614U_EQ_1614U(...) \, +#define Z_IS_1615_EQ_1615(...) \, +#define Z_IS_1615U_EQ_1615(...) \, +#define Z_IS_1615_EQ_1615U(...) \, +#define Z_IS_1615U_EQ_1615U(...) \, +#define Z_IS_1616_EQ_1616(...) \, +#define Z_IS_1616U_EQ_1616(...) \, +#define Z_IS_1616_EQ_1616U(...) \, +#define Z_IS_1616U_EQ_1616U(...) \, +#define Z_IS_1617_EQ_1617(...) \, +#define Z_IS_1617U_EQ_1617(...) \, +#define Z_IS_1617_EQ_1617U(...) \, +#define Z_IS_1617U_EQ_1617U(...) \, +#define Z_IS_1618_EQ_1618(...) \, +#define Z_IS_1618U_EQ_1618(...) \, +#define Z_IS_1618_EQ_1618U(...) \, +#define Z_IS_1618U_EQ_1618U(...) \, +#define Z_IS_1619_EQ_1619(...) \, +#define Z_IS_1619U_EQ_1619(...) \, +#define Z_IS_1619_EQ_1619U(...) \, +#define Z_IS_1619U_EQ_1619U(...) \, +#define Z_IS_1620_EQ_1620(...) \, +#define Z_IS_1620U_EQ_1620(...) \, +#define Z_IS_1620_EQ_1620U(...) \, +#define Z_IS_1620U_EQ_1620U(...) \, +#define Z_IS_1621_EQ_1621(...) \, +#define Z_IS_1621U_EQ_1621(...) \, +#define Z_IS_1621_EQ_1621U(...) \, +#define Z_IS_1621U_EQ_1621U(...) \, +#define Z_IS_1622_EQ_1622(...) \, +#define Z_IS_1622U_EQ_1622(...) \, +#define Z_IS_1622_EQ_1622U(...) \, +#define Z_IS_1622U_EQ_1622U(...) \, +#define Z_IS_1623_EQ_1623(...) \, +#define Z_IS_1623U_EQ_1623(...) \, +#define Z_IS_1623_EQ_1623U(...) \, +#define Z_IS_1623U_EQ_1623U(...) \, +#define Z_IS_1624_EQ_1624(...) \, +#define Z_IS_1624U_EQ_1624(...) \, +#define Z_IS_1624_EQ_1624U(...) \, +#define Z_IS_1624U_EQ_1624U(...) \, +#define Z_IS_1625_EQ_1625(...) \, +#define Z_IS_1625U_EQ_1625(...) \, +#define Z_IS_1625_EQ_1625U(...) \, +#define Z_IS_1625U_EQ_1625U(...) \, +#define Z_IS_1626_EQ_1626(...) \, +#define Z_IS_1626U_EQ_1626(...) \, +#define Z_IS_1626_EQ_1626U(...) \, +#define Z_IS_1626U_EQ_1626U(...) \, +#define Z_IS_1627_EQ_1627(...) \, +#define Z_IS_1627U_EQ_1627(...) \, +#define Z_IS_1627_EQ_1627U(...) \, +#define Z_IS_1627U_EQ_1627U(...) \, +#define Z_IS_1628_EQ_1628(...) \, +#define Z_IS_1628U_EQ_1628(...) \, +#define Z_IS_1628_EQ_1628U(...) \, +#define Z_IS_1628U_EQ_1628U(...) \, +#define Z_IS_1629_EQ_1629(...) \, +#define Z_IS_1629U_EQ_1629(...) \, +#define Z_IS_1629_EQ_1629U(...) \, +#define Z_IS_1629U_EQ_1629U(...) \, +#define Z_IS_1630_EQ_1630(...) \, +#define Z_IS_1630U_EQ_1630(...) \, +#define Z_IS_1630_EQ_1630U(...) \, +#define Z_IS_1630U_EQ_1630U(...) \, +#define Z_IS_1631_EQ_1631(...) \, +#define Z_IS_1631U_EQ_1631(...) \, +#define Z_IS_1631_EQ_1631U(...) \, +#define Z_IS_1631U_EQ_1631U(...) \, +#define Z_IS_1632_EQ_1632(...) \, +#define Z_IS_1632U_EQ_1632(...) \, +#define Z_IS_1632_EQ_1632U(...) \, +#define Z_IS_1632U_EQ_1632U(...) \, +#define Z_IS_1633_EQ_1633(...) \, +#define Z_IS_1633U_EQ_1633(...) \, +#define Z_IS_1633_EQ_1633U(...) \, +#define Z_IS_1633U_EQ_1633U(...) \, +#define Z_IS_1634_EQ_1634(...) \, +#define Z_IS_1634U_EQ_1634(...) \, +#define Z_IS_1634_EQ_1634U(...) \, +#define Z_IS_1634U_EQ_1634U(...) \, +#define Z_IS_1635_EQ_1635(...) \, +#define Z_IS_1635U_EQ_1635(...) \, +#define Z_IS_1635_EQ_1635U(...) \, +#define Z_IS_1635U_EQ_1635U(...) \, +#define Z_IS_1636_EQ_1636(...) \, +#define Z_IS_1636U_EQ_1636(...) \, +#define Z_IS_1636_EQ_1636U(...) \, +#define Z_IS_1636U_EQ_1636U(...) \, +#define Z_IS_1637_EQ_1637(...) \, +#define Z_IS_1637U_EQ_1637(...) \, +#define Z_IS_1637_EQ_1637U(...) \, +#define Z_IS_1637U_EQ_1637U(...) \, +#define Z_IS_1638_EQ_1638(...) \, +#define Z_IS_1638U_EQ_1638(...) \, +#define Z_IS_1638_EQ_1638U(...) \, +#define Z_IS_1638U_EQ_1638U(...) \, +#define Z_IS_1639_EQ_1639(...) \, +#define Z_IS_1639U_EQ_1639(...) \, +#define Z_IS_1639_EQ_1639U(...) \, +#define Z_IS_1639U_EQ_1639U(...) \, +#define Z_IS_1640_EQ_1640(...) \, +#define Z_IS_1640U_EQ_1640(...) \, +#define Z_IS_1640_EQ_1640U(...) \, +#define Z_IS_1640U_EQ_1640U(...) \, +#define Z_IS_1641_EQ_1641(...) \, +#define Z_IS_1641U_EQ_1641(...) \, +#define Z_IS_1641_EQ_1641U(...) \, +#define Z_IS_1641U_EQ_1641U(...) \, +#define Z_IS_1642_EQ_1642(...) \, +#define Z_IS_1642U_EQ_1642(...) \, +#define Z_IS_1642_EQ_1642U(...) \, +#define Z_IS_1642U_EQ_1642U(...) \, +#define Z_IS_1643_EQ_1643(...) \, +#define Z_IS_1643U_EQ_1643(...) \, +#define Z_IS_1643_EQ_1643U(...) \, +#define Z_IS_1643U_EQ_1643U(...) \, +#define Z_IS_1644_EQ_1644(...) \, +#define Z_IS_1644U_EQ_1644(...) \, +#define Z_IS_1644_EQ_1644U(...) \, +#define Z_IS_1644U_EQ_1644U(...) \, +#define Z_IS_1645_EQ_1645(...) \, +#define Z_IS_1645U_EQ_1645(...) \, +#define Z_IS_1645_EQ_1645U(...) \, +#define Z_IS_1645U_EQ_1645U(...) \, +#define Z_IS_1646_EQ_1646(...) \, +#define Z_IS_1646U_EQ_1646(...) \, +#define Z_IS_1646_EQ_1646U(...) \, +#define Z_IS_1646U_EQ_1646U(...) \, +#define Z_IS_1647_EQ_1647(...) \, +#define Z_IS_1647U_EQ_1647(...) \, +#define Z_IS_1647_EQ_1647U(...) \, +#define Z_IS_1647U_EQ_1647U(...) \, +#define Z_IS_1648_EQ_1648(...) \, +#define Z_IS_1648U_EQ_1648(...) \, +#define Z_IS_1648_EQ_1648U(...) \, +#define Z_IS_1648U_EQ_1648U(...) \, +#define Z_IS_1649_EQ_1649(...) \, +#define Z_IS_1649U_EQ_1649(...) \, +#define Z_IS_1649_EQ_1649U(...) \, +#define Z_IS_1649U_EQ_1649U(...) \, +#define Z_IS_1650_EQ_1650(...) \, +#define Z_IS_1650U_EQ_1650(...) \, +#define Z_IS_1650_EQ_1650U(...) \, +#define Z_IS_1650U_EQ_1650U(...) \, +#define Z_IS_1651_EQ_1651(...) \, +#define Z_IS_1651U_EQ_1651(...) \, +#define Z_IS_1651_EQ_1651U(...) \, +#define Z_IS_1651U_EQ_1651U(...) \, +#define Z_IS_1652_EQ_1652(...) \, +#define Z_IS_1652U_EQ_1652(...) \, +#define Z_IS_1652_EQ_1652U(...) \, +#define Z_IS_1652U_EQ_1652U(...) \, +#define Z_IS_1653_EQ_1653(...) \, +#define Z_IS_1653U_EQ_1653(...) \, +#define Z_IS_1653_EQ_1653U(...) \, +#define Z_IS_1653U_EQ_1653U(...) \, +#define Z_IS_1654_EQ_1654(...) \, +#define Z_IS_1654U_EQ_1654(...) \, +#define Z_IS_1654_EQ_1654U(...) \, +#define Z_IS_1654U_EQ_1654U(...) \, +#define Z_IS_1655_EQ_1655(...) \, +#define Z_IS_1655U_EQ_1655(...) \, +#define Z_IS_1655_EQ_1655U(...) \, +#define Z_IS_1655U_EQ_1655U(...) \, +#define Z_IS_1656_EQ_1656(...) \, +#define Z_IS_1656U_EQ_1656(...) \, +#define Z_IS_1656_EQ_1656U(...) \, +#define Z_IS_1656U_EQ_1656U(...) \, +#define Z_IS_1657_EQ_1657(...) \, +#define Z_IS_1657U_EQ_1657(...) \, +#define Z_IS_1657_EQ_1657U(...) \, +#define Z_IS_1657U_EQ_1657U(...) \, +#define Z_IS_1658_EQ_1658(...) \, +#define Z_IS_1658U_EQ_1658(...) \, +#define Z_IS_1658_EQ_1658U(...) \, +#define Z_IS_1658U_EQ_1658U(...) \, +#define Z_IS_1659_EQ_1659(...) \, +#define Z_IS_1659U_EQ_1659(...) \, +#define Z_IS_1659_EQ_1659U(...) \, +#define Z_IS_1659U_EQ_1659U(...) \, +#define Z_IS_1660_EQ_1660(...) \, +#define Z_IS_1660U_EQ_1660(...) \, +#define Z_IS_1660_EQ_1660U(...) \, +#define Z_IS_1660U_EQ_1660U(...) \, +#define Z_IS_1661_EQ_1661(...) \, +#define Z_IS_1661U_EQ_1661(...) \, +#define Z_IS_1661_EQ_1661U(...) \, +#define Z_IS_1661U_EQ_1661U(...) \, +#define Z_IS_1662_EQ_1662(...) \, +#define Z_IS_1662U_EQ_1662(...) \, +#define Z_IS_1662_EQ_1662U(...) \, +#define Z_IS_1662U_EQ_1662U(...) \, +#define Z_IS_1663_EQ_1663(...) \, +#define Z_IS_1663U_EQ_1663(...) \, +#define Z_IS_1663_EQ_1663U(...) \, +#define Z_IS_1663U_EQ_1663U(...) \, +#define Z_IS_1664_EQ_1664(...) \, +#define Z_IS_1664U_EQ_1664(...) \, +#define Z_IS_1664_EQ_1664U(...) \, +#define Z_IS_1664U_EQ_1664U(...) \, +#define Z_IS_1665_EQ_1665(...) \, +#define Z_IS_1665U_EQ_1665(...) \, +#define Z_IS_1665_EQ_1665U(...) \, +#define Z_IS_1665U_EQ_1665U(...) \, +#define Z_IS_1666_EQ_1666(...) \, +#define Z_IS_1666U_EQ_1666(...) \, +#define Z_IS_1666_EQ_1666U(...) \, +#define Z_IS_1666U_EQ_1666U(...) \, +#define Z_IS_1667_EQ_1667(...) \, +#define Z_IS_1667U_EQ_1667(...) \, +#define Z_IS_1667_EQ_1667U(...) \, +#define Z_IS_1667U_EQ_1667U(...) \, +#define Z_IS_1668_EQ_1668(...) \, +#define Z_IS_1668U_EQ_1668(...) \, +#define Z_IS_1668_EQ_1668U(...) \, +#define Z_IS_1668U_EQ_1668U(...) \, +#define Z_IS_1669_EQ_1669(...) \, +#define Z_IS_1669U_EQ_1669(...) \, +#define Z_IS_1669_EQ_1669U(...) \, +#define Z_IS_1669U_EQ_1669U(...) \, +#define Z_IS_1670_EQ_1670(...) \, +#define Z_IS_1670U_EQ_1670(...) \, +#define Z_IS_1670_EQ_1670U(...) \, +#define Z_IS_1670U_EQ_1670U(...) \, +#define Z_IS_1671_EQ_1671(...) \, +#define Z_IS_1671U_EQ_1671(...) \, +#define Z_IS_1671_EQ_1671U(...) \, +#define Z_IS_1671U_EQ_1671U(...) \, +#define Z_IS_1672_EQ_1672(...) \, +#define Z_IS_1672U_EQ_1672(...) \, +#define Z_IS_1672_EQ_1672U(...) \, +#define Z_IS_1672U_EQ_1672U(...) \, +#define Z_IS_1673_EQ_1673(...) \, +#define Z_IS_1673U_EQ_1673(...) \, +#define Z_IS_1673_EQ_1673U(...) \, +#define Z_IS_1673U_EQ_1673U(...) \, +#define Z_IS_1674_EQ_1674(...) \, +#define Z_IS_1674U_EQ_1674(...) \, +#define Z_IS_1674_EQ_1674U(...) \, +#define Z_IS_1674U_EQ_1674U(...) \, +#define Z_IS_1675_EQ_1675(...) \, +#define Z_IS_1675U_EQ_1675(...) \, +#define Z_IS_1675_EQ_1675U(...) \, +#define Z_IS_1675U_EQ_1675U(...) \, +#define Z_IS_1676_EQ_1676(...) \, +#define Z_IS_1676U_EQ_1676(...) \, +#define Z_IS_1676_EQ_1676U(...) \, +#define Z_IS_1676U_EQ_1676U(...) \, +#define Z_IS_1677_EQ_1677(...) \, +#define Z_IS_1677U_EQ_1677(...) \, +#define Z_IS_1677_EQ_1677U(...) \, +#define Z_IS_1677U_EQ_1677U(...) \, +#define Z_IS_1678_EQ_1678(...) \, +#define Z_IS_1678U_EQ_1678(...) \, +#define Z_IS_1678_EQ_1678U(...) \, +#define Z_IS_1678U_EQ_1678U(...) \, +#define Z_IS_1679_EQ_1679(...) \, +#define Z_IS_1679U_EQ_1679(...) \, +#define Z_IS_1679_EQ_1679U(...) \, +#define Z_IS_1679U_EQ_1679U(...) \, +#define Z_IS_1680_EQ_1680(...) \, +#define Z_IS_1680U_EQ_1680(...) \, +#define Z_IS_1680_EQ_1680U(...) \, +#define Z_IS_1680U_EQ_1680U(...) \, +#define Z_IS_1681_EQ_1681(...) \, +#define Z_IS_1681U_EQ_1681(...) \, +#define Z_IS_1681_EQ_1681U(...) \, +#define Z_IS_1681U_EQ_1681U(...) \, +#define Z_IS_1682_EQ_1682(...) \, +#define Z_IS_1682U_EQ_1682(...) \, +#define Z_IS_1682_EQ_1682U(...) \, +#define Z_IS_1682U_EQ_1682U(...) \, +#define Z_IS_1683_EQ_1683(...) \, +#define Z_IS_1683U_EQ_1683(...) \, +#define Z_IS_1683_EQ_1683U(...) \, +#define Z_IS_1683U_EQ_1683U(...) \, +#define Z_IS_1684_EQ_1684(...) \, +#define Z_IS_1684U_EQ_1684(...) \, +#define Z_IS_1684_EQ_1684U(...) \, +#define Z_IS_1684U_EQ_1684U(...) \, +#define Z_IS_1685_EQ_1685(...) \, +#define Z_IS_1685U_EQ_1685(...) \, +#define Z_IS_1685_EQ_1685U(...) \, +#define Z_IS_1685U_EQ_1685U(...) \, +#define Z_IS_1686_EQ_1686(...) \, +#define Z_IS_1686U_EQ_1686(...) \, +#define Z_IS_1686_EQ_1686U(...) \, +#define Z_IS_1686U_EQ_1686U(...) \, +#define Z_IS_1687_EQ_1687(...) \, +#define Z_IS_1687U_EQ_1687(...) \, +#define Z_IS_1687_EQ_1687U(...) \, +#define Z_IS_1687U_EQ_1687U(...) \, +#define Z_IS_1688_EQ_1688(...) \, +#define Z_IS_1688U_EQ_1688(...) \, +#define Z_IS_1688_EQ_1688U(...) \, +#define Z_IS_1688U_EQ_1688U(...) \, +#define Z_IS_1689_EQ_1689(...) \, +#define Z_IS_1689U_EQ_1689(...) \, +#define Z_IS_1689_EQ_1689U(...) \, +#define Z_IS_1689U_EQ_1689U(...) \, +#define Z_IS_1690_EQ_1690(...) \, +#define Z_IS_1690U_EQ_1690(...) \, +#define Z_IS_1690_EQ_1690U(...) \, +#define Z_IS_1690U_EQ_1690U(...) \, +#define Z_IS_1691_EQ_1691(...) \, +#define Z_IS_1691U_EQ_1691(...) \, +#define Z_IS_1691_EQ_1691U(...) \, +#define Z_IS_1691U_EQ_1691U(...) \, +#define Z_IS_1692_EQ_1692(...) \, +#define Z_IS_1692U_EQ_1692(...) \, +#define Z_IS_1692_EQ_1692U(...) \, +#define Z_IS_1692U_EQ_1692U(...) \, +#define Z_IS_1693_EQ_1693(...) \, +#define Z_IS_1693U_EQ_1693(...) \, +#define Z_IS_1693_EQ_1693U(...) \, +#define Z_IS_1693U_EQ_1693U(...) \, +#define Z_IS_1694_EQ_1694(...) \, +#define Z_IS_1694U_EQ_1694(...) \, +#define Z_IS_1694_EQ_1694U(...) \, +#define Z_IS_1694U_EQ_1694U(...) \, +#define Z_IS_1695_EQ_1695(...) \, +#define Z_IS_1695U_EQ_1695(...) \, +#define Z_IS_1695_EQ_1695U(...) \, +#define Z_IS_1695U_EQ_1695U(...) \, +#define Z_IS_1696_EQ_1696(...) \, +#define Z_IS_1696U_EQ_1696(...) \, +#define Z_IS_1696_EQ_1696U(...) \, +#define Z_IS_1696U_EQ_1696U(...) \, +#define Z_IS_1697_EQ_1697(...) \, +#define Z_IS_1697U_EQ_1697(...) \, +#define Z_IS_1697_EQ_1697U(...) \, +#define Z_IS_1697U_EQ_1697U(...) \, +#define Z_IS_1698_EQ_1698(...) \, +#define Z_IS_1698U_EQ_1698(...) \, +#define Z_IS_1698_EQ_1698U(...) \, +#define Z_IS_1698U_EQ_1698U(...) \, +#define Z_IS_1699_EQ_1699(...) \, +#define Z_IS_1699U_EQ_1699(...) \, +#define Z_IS_1699_EQ_1699U(...) \, +#define Z_IS_1699U_EQ_1699U(...) \, +#define Z_IS_1700_EQ_1700(...) \, +#define Z_IS_1700U_EQ_1700(...) \, +#define Z_IS_1700_EQ_1700U(...) \, +#define Z_IS_1700U_EQ_1700U(...) \, +#define Z_IS_1701_EQ_1701(...) \, +#define Z_IS_1701U_EQ_1701(...) \, +#define Z_IS_1701_EQ_1701U(...) \, +#define Z_IS_1701U_EQ_1701U(...) \, +#define Z_IS_1702_EQ_1702(...) \, +#define Z_IS_1702U_EQ_1702(...) \, +#define Z_IS_1702_EQ_1702U(...) \, +#define Z_IS_1702U_EQ_1702U(...) \, +#define Z_IS_1703_EQ_1703(...) \, +#define Z_IS_1703U_EQ_1703(...) \, +#define Z_IS_1703_EQ_1703U(...) \, +#define Z_IS_1703U_EQ_1703U(...) \, +#define Z_IS_1704_EQ_1704(...) \, +#define Z_IS_1704U_EQ_1704(...) \, +#define Z_IS_1704_EQ_1704U(...) \, +#define Z_IS_1704U_EQ_1704U(...) \, +#define Z_IS_1705_EQ_1705(...) \, +#define Z_IS_1705U_EQ_1705(...) \, +#define Z_IS_1705_EQ_1705U(...) \, +#define Z_IS_1705U_EQ_1705U(...) \, +#define Z_IS_1706_EQ_1706(...) \, +#define Z_IS_1706U_EQ_1706(...) \, +#define Z_IS_1706_EQ_1706U(...) \, +#define Z_IS_1706U_EQ_1706U(...) \, +#define Z_IS_1707_EQ_1707(...) \, +#define Z_IS_1707U_EQ_1707(...) \, +#define Z_IS_1707_EQ_1707U(...) \, +#define Z_IS_1707U_EQ_1707U(...) \, +#define Z_IS_1708_EQ_1708(...) \, +#define Z_IS_1708U_EQ_1708(...) \, +#define Z_IS_1708_EQ_1708U(...) \, +#define Z_IS_1708U_EQ_1708U(...) \, +#define Z_IS_1709_EQ_1709(...) \, +#define Z_IS_1709U_EQ_1709(...) \, +#define Z_IS_1709_EQ_1709U(...) \, +#define Z_IS_1709U_EQ_1709U(...) \, +#define Z_IS_1710_EQ_1710(...) \, +#define Z_IS_1710U_EQ_1710(...) \, +#define Z_IS_1710_EQ_1710U(...) \, +#define Z_IS_1710U_EQ_1710U(...) \, +#define Z_IS_1711_EQ_1711(...) \, +#define Z_IS_1711U_EQ_1711(...) \, +#define Z_IS_1711_EQ_1711U(...) \, +#define Z_IS_1711U_EQ_1711U(...) \, +#define Z_IS_1712_EQ_1712(...) \, +#define Z_IS_1712U_EQ_1712(...) \, +#define Z_IS_1712_EQ_1712U(...) \, +#define Z_IS_1712U_EQ_1712U(...) \, +#define Z_IS_1713_EQ_1713(...) \, +#define Z_IS_1713U_EQ_1713(...) \, +#define Z_IS_1713_EQ_1713U(...) \, +#define Z_IS_1713U_EQ_1713U(...) \, +#define Z_IS_1714_EQ_1714(...) \, +#define Z_IS_1714U_EQ_1714(...) \, +#define Z_IS_1714_EQ_1714U(...) \, +#define Z_IS_1714U_EQ_1714U(...) \, +#define Z_IS_1715_EQ_1715(...) \, +#define Z_IS_1715U_EQ_1715(...) \, +#define Z_IS_1715_EQ_1715U(...) \, +#define Z_IS_1715U_EQ_1715U(...) \, +#define Z_IS_1716_EQ_1716(...) \, +#define Z_IS_1716U_EQ_1716(...) \, +#define Z_IS_1716_EQ_1716U(...) \, +#define Z_IS_1716U_EQ_1716U(...) \, +#define Z_IS_1717_EQ_1717(...) \, +#define Z_IS_1717U_EQ_1717(...) \, +#define Z_IS_1717_EQ_1717U(...) \, +#define Z_IS_1717U_EQ_1717U(...) \, +#define Z_IS_1718_EQ_1718(...) \, +#define Z_IS_1718U_EQ_1718(...) \, +#define Z_IS_1718_EQ_1718U(...) \, +#define Z_IS_1718U_EQ_1718U(...) \, +#define Z_IS_1719_EQ_1719(...) \, +#define Z_IS_1719U_EQ_1719(...) \, +#define Z_IS_1719_EQ_1719U(...) \, +#define Z_IS_1719U_EQ_1719U(...) \, +#define Z_IS_1720_EQ_1720(...) \, +#define Z_IS_1720U_EQ_1720(...) \, +#define Z_IS_1720_EQ_1720U(...) \, +#define Z_IS_1720U_EQ_1720U(...) \, +#define Z_IS_1721_EQ_1721(...) \, +#define Z_IS_1721U_EQ_1721(...) \, +#define Z_IS_1721_EQ_1721U(...) \, +#define Z_IS_1721U_EQ_1721U(...) \, +#define Z_IS_1722_EQ_1722(...) \, +#define Z_IS_1722U_EQ_1722(...) \, +#define Z_IS_1722_EQ_1722U(...) \, +#define Z_IS_1722U_EQ_1722U(...) \, +#define Z_IS_1723_EQ_1723(...) \, +#define Z_IS_1723U_EQ_1723(...) \, +#define Z_IS_1723_EQ_1723U(...) \, +#define Z_IS_1723U_EQ_1723U(...) \, +#define Z_IS_1724_EQ_1724(...) \, +#define Z_IS_1724U_EQ_1724(...) \, +#define Z_IS_1724_EQ_1724U(...) \, +#define Z_IS_1724U_EQ_1724U(...) \, +#define Z_IS_1725_EQ_1725(...) \, +#define Z_IS_1725U_EQ_1725(...) \, +#define Z_IS_1725_EQ_1725U(...) \, +#define Z_IS_1725U_EQ_1725U(...) \, +#define Z_IS_1726_EQ_1726(...) \, +#define Z_IS_1726U_EQ_1726(...) \, +#define Z_IS_1726_EQ_1726U(...) \, +#define Z_IS_1726U_EQ_1726U(...) \, +#define Z_IS_1727_EQ_1727(...) \, +#define Z_IS_1727U_EQ_1727(...) \, +#define Z_IS_1727_EQ_1727U(...) \, +#define Z_IS_1727U_EQ_1727U(...) \, +#define Z_IS_1728_EQ_1728(...) \, +#define Z_IS_1728U_EQ_1728(...) \, +#define Z_IS_1728_EQ_1728U(...) \, +#define Z_IS_1728U_EQ_1728U(...) \, +#define Z_IS_1729_EQ_1729(...) \, +#define Z_IS_1729U_EQ_1729(...) \, +#define Z_IS_1729_EQ_1729U(...) \, +#define Z_IS_1729U_EQ_1729U(...) \, +#define Z_IS_1730_EQ_1730(...) \, +#define Z_IS_1730U_EQ_1730(...) \, +#define Z_IS_1730_EQ_1730U(...) \, +#define Z_IS_1730U_EQ_1730U(...) \, +#define Z_IS_1731_EQ_1731(...) \, +#define Z_IS_1731U_EQ_1731(...) \, +#define Z_IS_1731_EQ_1731U(...) \, +#define Z_IS_1731U_EQ_1731U(...) \, +#define Z_IS_1732_EQ_1732(...) \, +#define Z_IS_1732U_EQ_1732(...) \, +#define Z_IS_1732_EQ_1732U(...) \, +#define Z_IS_1732U_EQ_1732U(...) \, +#define Z_IS_1733_EQ_1733(...) \, +#define Z_IS_1733U_EQ_1733(...) \, +#define Z_IS_1733_EQ_1733U(...) \, +#define Z_IS_1733U_EQ_1733U(...) \, +#define Z_IS_1734_EQ_1734(...) \, +#define Z_IS_1734U_EQ_1734(...) \, +#define Z_IS_1734_EQ_1734U(...) \, +#define Z_IS_1734U_EQ_1734U(...) \, +#define Z_IS_1735_EQ_1735(...) \, +#define Z_IS_1735U_EQ_1735(...) \, +#define Z_IS_1735_EQ_1735U(...) \, +#define Z_IS_1735U_EQ_1735U(...) \, +#define Z_IS_1736_EQ_1736(...) \, +#define Z_IS_1736U_EQ_1736(...) \, +#define Z_IS_1736_EQ_1736U(...) \, +#define Z_IS_1736U_EQ_1736U(...) \, +#define Z_IS_1737_EQ_1737(...) \, +#define Z_IS_1737U_EQ_1737(...) \, +#define Z_IS_1737_EQ_1737U(...) \, +#define Z_IS_1737U_EQ_1737U(...) \, +#define Z_IS_1738_EQ_1738(...) \, +#define Z_IS_1738U_EQ_1738(...) \, +#define Z_IS_1738_EQ_1738U(...) \, +#define Z_IS_1738U_EQ_1738U(...) \, +#define Z_IS_1739_EQ_1739(...) \, +#define Z_IS_1739U_EQ_1739(...) \, +#define Z_IS_1739_EQ_1739U(...) \, +#define Z_IS_1739U_EQ_1739U(...) \, +#define Z_IS_1740_EQ_1740(...) \, +#define Z_IS_1740U_EQ_1740(...) \, +#define Z_IS_1740_EQ_1740U(...) \, +#define Z_IS_1740U_EQ_1740U(...) \, +#define Z_IS_1741_EQ_1741(...) \, +#define Z_IS_1741U_EQ_1741(...) \, +#define Z_IS_1741_EQ_1741U(...) \, +#define Z_IS_1741U_EQ_1741U(...) \, +#define Z_IS_1742_EQ_1742(...) \, +#define Z_IS_1742U_EQ_1742(...) \, +#define Z_IS_1742_EQ_1742U(...) \, +#define Z_IS_1742U_EQ_1742U(...) \, +#define Z_IS_1743_EQ_1743(...) \, +#define Z_IS_1743U_EQ_1743(...) \, +#define Z_IS_1743_EQ_1743U(...) \, +#define Z_IS_1743U_EQ_1743U(...) \, +#define Z_IS_1744_EQ_1744(...) \, +#define Z_IS_1744U_EQ_1744(...) \, +#define Z_IS_1744_EQ_1744U(...) \, +#define Z_IS_1744U_EQ_1744U(...) \, +#define Z_IS_1745_EQ_1745(...) \, +#define Z_IS_1745U_EQ_1745(...) \, +#define Z_IS_1745_EQ_1745U(...) \, +#define Z_IS_1745U_EQ_1745U(...) \, +#define Z_IS_1746_EQ_1746(...) \, +#define Z_IS_1746U_EQ_1746(...) \, +#define Z_IS_1746_EQ_1746U(...) \, +#define Z_IS_1746U_EQ_1746U(...) \, +#define Z_IS_1747_EQ_1747(...) \, +#define Z_IS_1747U_EQ_1747(...) \, +#define Z_IS_1747_EQ_1747U(...) \, +#define Z_IS_1747U_EQ_1747U(...) \, +#define Z_IS_1748_EQ_1748(...) \, +#define Z_IS_1748U_EQ_1748(...) \, +#define Z_IS_1748_EQ_1748U(...) \, +#define Z_IS_1748U_EQ_1748U(...) \, +#define Z_IS_1749_EQ_1749(...) \, +#define Z_IS_1749U_EQ_1749(...) \, +#define Z_IS_1749_EQ_1749U(...) \, +#define Z_IS_1749U_EQ_1749U(...) \, +#define Z_IS_1750_EQ_1750(...) \, +#define Z_IS_1750U_EQ_1750(...) \, +#define Z_IS_1750_EQ_1750U(...) \, +#define Z_IS_1750U_EQ_1750U(...) \, +#define Z_IS_1751_EQ_1751(...) \, +#define Z_IS_1751U_EQ_1751(...) \, +#define Z_IS_1751_EQ_1751U(...) \, +#define Z_IS_1751U_EQ_1751U(...) \, +#define Z_IS_1752_EQ_1752(...) \, +#define Z_IS_1752U_EQ_1752(...) \, +#define Z_IS_1752_EQ_1752U(...) \, +#define Z_IS_1752U_EQ_1752U(...) \, +#define Z_IS_1753_EQ_1753(...) \, +#define Z_IS_1753U_EQ_1753(...) \, +#define Z_IS_1753_EQ_1753U(...) \, +#define Z_IS_1753U_EQ_1753U(...) \, +#define Z_IS_1754_EQ_1754(...) \, +#define Z_IS_1754U_EQ_1754(...) \, +#define Z_IS_1754_EQ_1754U(...) \, +#define Z_IS_1754U_EQ_1754U(...) \, +#define Z_IS_1755_EQ_1755(...) \, +#define Z_IS_1755U_EQ_1755(...) \, +#define Z_IS_1755_EQ_1755U(...) \, +#define Z_IS_1755U_EQ_1755U(...) \, +#define Z_IS_1756_EQ_1756(...) \, +#define Z_IS_1756U_EQ_1756(...) \, +#define Z_IS_1756_EQ_1756U(...) \, +#define Z_IS_1756U_EQ_1756U(...) \, +#define Z_IS_1757_EQ_1757(...) \, +#define Z_IS_1757U_EQ_1757(...) \, +#define Z_IS_1757_EQ_1757U(...) \, +#define Z_IS_1757U_EQ_1757U(...) \, +#define Z_IS_1758_EQ_1758(...) \, +#define Z_IS_1758U_EQ_1758(...) \, +#define Z_IS_1758_EQ_1758U(...) \, +#define Z_IS_1758U_EQ_1758U(...) \, +#define Z_IS_1759_EQ_1759(...) \, +#define Z_IS_1759U_EQ_1759(...) \, +#define Z_IS_1759_EQ_1759U(...) \, +#define Z_IS_1759U_EQ_1759U(...) \, +#define Z_IS_1760_EQ_1760(...) \, +#define Z_IS_1760U_EQ_1760(...) \, +#define Z_IS_1760_EQ_1760U(...) \, +#define Z_IS_1760U_EQ_1760U(...) \, +#define Z_IS_1761_EQ_1761(...) \, +#define Z_IS_1761U_EQ_1761(...) \, +#define Z_IS_1761_EQ_1761U(...) \, +#define Z_IS_1761U_EQ_1761U(...) \, +#define Z_IS_1762_EQ_1762(...) \, +#define Z_IS_1762U_EQ_1762(...) \, +#define Z_IS_1762_EQ_1762U(...) \, +#define Z_IS_1762U_EQ_1762U(...) \, +#define Z_IS_1763_EQ_1763(...) \, +#define Z_IS_1763U_EQ_1763(...) \, +#define Z_IS_1763_EQ_1763U(...) \, +#define Z_IS_1763U_EQ_1763U(...) \, +#define Z_IS_1764_EQ_1764(...) \, +#define Z_IS_1764U_EQ_1764(...) \, +#define Z_IS_1764_EQ_1764U(...) \, +#define Z_IS_1764U_EQ_1764U(...) \, +#define Z_IS_1765_EQ_1765(...) \, +#define Z_IS_1765U_EQ_1765(...) \, +#define Z_IS_1765_EQ_1765U(...) \, +#define Z_IS_1765U_EQ_1765U(...) \, +#define Z_IS_1766_EQ_1766(...) \, +#define Z_IS_1766U_EQ_1766(...) \, +#define Z_IS_1766_EQ_1766U(...) \, +#define Z_IS_1766U_EQ_1766U(...) \, +#define Z_IS_1767_EQ_1767(...) \, +#define Z_IS_1767U_EQ_1767(...) \, +#define Z_IS_1767_EQ_1767U(...) \, +#define Z_IS_1767U_EQ_1767U(...) \, +#define Z_IS_1768_EQ_1768(...) \, +#define Z_IS_1768U_EQ_1768(...) \, +#define Z_IS_1768_EQ_1768U(...) \, +#define Z_IS_1768U_EQ_1768U(...) \, +#define Z_IS_1769_EQ_1769(...) \, +#define Z_IS_1769U_EQ_1769(...) \, +#define Z_IS_1769_EQ_1769U(...) \, +#define Z_IS_1769U_EQ_1769U(...) \, +#define Z_IS_1770_EQ_1770(...) \, +#define Z_IS_1770U_EQ_1770(...) \, +#define Z_IS_1770_EQ_1770U(...) \, +#define Z_IS_1770U_EQ_1770U(...) \, +#define Z_IS_1771_EQ_1771(...) \, +#define Z_IS_1771U_EQ_1771(...) \, +#define Z_IS_1771_EQ_1771U(...) \, +#define Z_IS_1771U_EQ_1771U(...) \, +#define Z_IS_1772_EQ_1772(...) \, +#define Z_IS_1772U_EQ_1772(...) \, +#define Z_IS_1772_EQ_1772U(...) \, +#define Z_IS_1772U_EQ_1772U(...) \, +#define Z_IS_1773_EQ_1773(...) \, +#define Z_IS_1773U_EQ_1773(...) \, +#define Z_IS_1773_EQ_1773U(...) \, +#define Z_IS_1773U_EQ_1773U(...) \, +#define Z_IS_1774_EQ_1774(...) \, +#define Z_IS_1774U_EQ_1774(...) \, +#define Z_IS_1774_EQ_1774U(...) \, +#define Z_IS_1774U_EQ_1774U(...) \, +#define Z_IS_1775_EQ_1775(...) \, +#define Z_IS_1775U_EQ_1775(...) \, +#define Z_IS_1775_EQ_1775U(...) \, +#define Z_IS_1775U_EQ_1775U(...) \, +#define Z_IS_1776_EQ_1776(...) \, +#define Z_IS_1776U_EQ_1776(...) \, +#define Z_IS_1776_EQ_1776U(...) \, +#define Z_IS_1776U_EQ_1776U(...) \, +#define Z_IS_1777_EQ_1777(...) \, +#define Z_IS_1777U_EQ_1777(...) \, +#define Z_IS_1777_EQ_1777U(...) \, +#define Z_IS_1777U_EQ_1777U(...) \, +#define Z_IS_1778_EQ_1778(...) \, +#define Z_IS_1778U_EQ_1778(...) \, +#define Z_IS_1778_EQ_1778U(...) \, +#define Z_IS_1778U_EQ_1778U(...) \, +#define Z_IS_1779_EQ_1779(...) \, +#define Z_IS_1779U_EQ_1779(...) \, +#define Z_IS_1779_EQ_1779U(...) \, +#define Z_IS_1779U_EQ_1779U(...) \, +#define Z_IS_1780_EQ_1780(...) \, +#define Z_IS_1780U_EQ_1780(...) \, +#define Z_IS_1780_EQ_1780U(...) \, +#define Z_IS_1780U_EQ_1780U(...) \, +#define Z_IS_1781_EQ_1781(...) \, +#define Z_IS_1781U_EQ_1781(...) \, +#define Z_IS_1781_EQ_1781U(...) \, +#define Z_IS_1781U_EQ_1781U(...) \, +#define Z_IS_1782_EQ_1782(...) \, +#define Z_IS_1782U_EQ_1782(...) \, +#define Z_IS_1782_EQ_1782U(...) \, +#define Z_IS_1782U_EQ_1782U(...) \, +#define Z_IS_1783_EQ_1783(...) \, +#define Z_IS_1783U_EQ_1783(...) \, +#define Z_IS_1783_EQ_1783U(...) \, +#define Z_IS_1783U_EQ_1783U(...) \, +#define Z_IS_1784_EQ_1784(...) \, +#define Z_IS_1784U_EQ_1784(...) \, +#define Z_IS_1784_EQ_1784U(...) \, +#define Z_IS_1784U_EQ_1784U(...) \, +#define Z_IS_1785_EQ_1785(...) \, +#define Z_IS_1785U_EQ_1785(...) \, +#define Z_IS_1785_EQ_1785U(...) \, +#define Z_IS_1785U_EQ_1785U(...) \, +#define Z_IS_1786_EQ_1786(...) \, +#define Z_IS_1786U_EQ_1786(...) \, +#define Z_IS_1786_EQ_1786U(...) \, +#define Z_IS_1786U_EQ_1786U(...) \, +#define Z_IS_1787_EQ_1787(...) \, +#define Z_IS_1787U_EQ_1787(...) \, +#define Z_IS_1787_EQ_1787U(...) \, +#define Z_IS_1787U_EQ_1787U(...) \, +#define Z_IS_1788_EQ_1788(...) \, +#define Z_IS_1788U_EQ_1788(...) \, +#define Z_IS_1788_EQ_1788U(...) \, +#define Z_IS_1788U_EQ_1788U(...) \, +#define Z_IS_1789_EQ_1789(...) \, +#define Z_IS_1789U_EQ_1789(...) \, +#define Z_IS_1789_EQ_1789U(...) \, +#define Z_IS_1789U_EQ_1789U(...) \, +#define Z_IS_1790_EQ_1790(...) \, +#define Z_IS_1790U_EQ_1790(...) \, +#define Z_IS_1790_EQ_1790U(...) \, +#define Z_IS_1790U_EQ_1790U(...) \, +#define Z_IS_1791_EQ_1791(...) \, +#define Z_IS_1791U_EQ_1791(...) \, +#define Z_IS_1791_EQ_1791U(...) \, +#define Z_IS_1791U_EQ_1791U(...) \, +#define Z_IS_1792_EQ_1792(...) \, +#define Z_IS_1792U_EQ_1792(...) \, +#define Z_IS_1792_EQ_1792U(...) \, +#define Z_IS_1792U_EQ_1792U(...) \, +#define Z_IS_1793_EQ_1793(...) \, +#define Z_IS_1793U_EQ_1793(...) \, +#define Z_IS_1793_EQ_1793U(...) \, +#define Z_IS_1793U_EQ_1793U(...) \, +#define Z_IS_1794_EQ_1794(...) \, +#define Z_IS_1794U_EQ_1794(...) \, +#define Z_IS_1794_EQ_1794U(...) \, +#define Z_IS_1794U_EQ_1794U(...) \, +#define Z_IS_1795_EQ_1795(...) \, +#define Z_IS_1795U_EQ_1795(...) \, +#define Z_IS_1795_EQ_1795U(...) \, +#define Z_IS_1795U_EQ_1795U(...) \, +#define Z_IS_1796_EQ_1796(...) \, +#define Z_IS_1796U_EQ_1796(...) \, +#define Z_IS_1796_EQ_1796U(...) \, +#define Z_IS_1796U_EQ_1796U(...) \, +#define Z_IS_1797_EQ_1797(...) \, +#define Z_IS_1797U_EQ_1797(...) \, +#define Z_IS_1797_EQ_1797U(...) \, +#define Z_IS_1797U_EQ_1797U(...) \, +#define Z_IS_1798_EQ_1798(...) \, +#define Z_IS_1798U_EQ_1798(...) \, +#define Z_IS_1798_EQ_1798U(...) \, +#define Z_IS_1798U_EQ_1798U(...) \, +#define Z_IS_1799_EQ_1799(...) \, +#define Z_IS_1799U_EQ_1799(...) \, +#define Z_IS_1799_EQ_1799U(...) \, +#define Z_IS_1799U_EQ_1799U(...) \, +#define Z_IS_1800_EQ_1800(...) \, +#define Z_IS_1800U_EQ_1800(...) \, +#define Z_IS_1800_EQ_1800U(...) \, +#define Z_IS_1800U_EQ_1800U(...) \, +#define Z_IS_1801_EQ_1801(...) \, +#define Z_IS_1801U_EQ_1801(...) \, +#define Z_IS_1801_EQ_1801U(...) \, +#define Z_IS_1801U_EQ_1801U(...) \, +#define Z_IS_1802_EQ_1802(...) \, +#define Z_IS_1802U_EQ_1802(...) \, +#define Z_IS_1802_EQ_1802U(...) \, +#define Z_IS_1802U_EQ_1802U(...) \, +#define Z_IS_1803_EQ_1803(...) \, +#define Z_IS_1803U_EQ_1803(...) \, +#define Z_IS_1803_EQ_1803U(...) \, +#define Z_IS_1803U_EQ_1803U(...) \, +#define Z_IS_1804_EQ_1804(...) \, +#define Z_IS_1804U_EQ_1804(...) \, +#define Z_IS_1804_EQ_1804U(...) \, +#define Z_IS_1804U_EQ_1804U(...) \, +#define Z_IS_1805_EQ_1805(...) \, +#define Z_IS_1805U_EQ_1805(...) \, +#define Z_IS_1805_EQ_1805U(...) \, +#define Z_IS_1805U_EQ_1805U(...) \, +#define Z_IS_1806_EQ_1806(...) \, +#define Z_IS_1806U_EQ_1806(...) \, +#define Z_IS_1806_EQ_1806U(...) \, +#define Z_IS_1806U_EQ_1806U(...) \, +#define Z_IS_1807_EQ_1807(...) \, +#define Z_IS_1807U_EQ_1807(...) \, +#define Z_IS_1807_EQ_1807U(...) \, +#define Z_IS_1807U_EQ_1807U(...) \, +#define Z_IS_1808_EQ_1808(...) \, +#define Z_IS_1808U_EQ_1808(...) \, +#define Z_IS_1808_EQ_1808U(...) \, +#define Z_IS_1808U_EQ_1808U(...) \, +#define Z_IS_1809_EQ_1809(...) \, +#define Z_IS_1809U_EQ_1809(...) \, +#define Z_IS_1809_EQ_1809U(...) \, +#define Z_IS_1809U_EQ_1809U(...) \, +#define Z_IS_1810_EQ_1810(...) \, +#define Z_IS_1810U_EQ_1810(...) \, +#define Z_IS_1810_EQ_1810U(...) \, +#define Z_IS_1810U_EQ_1810U(...) \, +#define Z_IS_1811_EQ_1811(...) \, +#define Z_IS_1811U_EQ_1811(...) \, +#define Z_IS_1811_EQ_1811U(...) \, +#define Z_IS_1811U_EQ_1811U(...) \, +#define Z_IS_1812_EQ_1812(...) \, +#define Z_IS_1812U_EQ_1812(...) \, +#define Z_IS_1812_EQ_1812U(...) \, +#define Z_IS_1812U_EQ_1812U(...) \, +#define Z_IS_1813_EQ_1813(...) \, +#define Z_IS_1813U_EQ_1813(...) \, +#define Z_IS_1813_EQ_1813U(...) \, +#define Z_IS_1813U_EQ_1813U(...) \, +#define Z_IS_1814_EQ_1814(...) \, +#define Z_IS_1814U_EQ_1814(...) \, +#define Z_IS_1814_EQ_1814U(...) \, +#define Z_IS_1814U_EQ_1814U(...) \, +#define Z_IS_1815_EQ_1815(...) \, +#define Z_IS_1815U_EQ_1815(...) \, +#define Z_IS_1815_EQ_1815U(...) \, +#define Z_IS_1815U_EQ_1815U(...) \, +#define Z_IS_1816_EQ_1816(...) \, +#define Z_IS_1816U_EQ_1816(...) \, +#define Z_IS_1816_EQ_1816U(...) \, +#define Z_IS_1816U_EQ_1816U(...) \, +#define Z_IS_1817_EQ_1817(...) \, +#define Z_IS_1817U_EQ_1817(...) \, +#define Z_IS_1817_EQ_1817U(...) \, +#define Z_IS_1817U_EQ_1817U(...) \, +#define Z_IS_1818_EQ_1818(...) \, +#define Z_IS_1818U_EQ_1818(...) \, +#define Z_IS_1818_EQ_1818U(...) \, +#define Z_IS_1818U_EQ_1818U(...) \, +#define Z_IS_1819_EQ_1819(...) \, +#define Z_IS_1819U_EQ_1819(...) \, +#define Z_IS_1819_EQ_1819U(...) \, +#define Z_IS_1819U_EQ_1819U(...) \, +#define Z_IS_1820_EQ_1820(...) \, +#define Z_IS_1820U_EQ_1820(...) \, +#define Z_IS_1820_EQ_1820U(...) \, +#define Z_IS_1820U_EQ_1820U(...) \, +#define Z_IS_1821_EQ_1821(...) \, +#define Z_IS_1821U_EQ_1821(...) \, +#define Z_IS_1821_EQ_1821U(...) \, +#define Z_IS_1821U_EQ_1821U(...) \, +#define Z_IS_1822_EQ_1822(...) \, +#define Z_IS_1822U_EQ_1822(...) \, +#define Z_IS_1822_EQ_1822U(...) \, +#define Z_IS_1822U_EQ_1822U(...) \, +#define Z_IS_1823_EQ_1823(...) \, +#define Z_IS_1823U_EQ_1823(...) \, +#define Z_IS_1823_EQ_1823U(...) \, +#define Z_IS_1823U_EQ_1823U(...) \, +#define Z_IS_1824_EQ_1824(...) \, +#define Z_IS_1824U_EQ_1824(...) \, +#define Z_IS_1824_EQ_1824U(...) \, +#define Z_IS_1824U_EQ_1824U(...) \, +#define Z_IS_1825_EQ_1825(...) \, +#define Z_IS_1825U_EQ_1825(...) \, +#define Z_IS_1825_EQ_1825U(...) \, +#define Z_IS_1825U_EQ_1825U(...) \, +#define Z_IS_1826_EQ_1826(...) \, +#define Z_IS_1826U_EQ_1826(...) \, +#define Z_IS_1826_EQ_1826U(...) \, +#define Z_IS_1826U_EQ_1826U(...) \, +#define Z_IS_1827_EQ_1827(...) \, +#define Z_IS_1827U_EQ_1827(...) \, +#define Z_IS_1827_EQ_1827U(...) \, +#define Z_IS_1827U_EQ_1827U(...) \, +#define Z_IS_1828_EQ_1828(...) \, +#define Z_IS_1828U_EQ_1828(...) \, +#define Z_IS_1828_EQ_1828U(...) \, +#define Z_IS_1828U_EQ_1828U(...) \, +#define Z_IS_1829_EQ_1829(...) \, +#define Z_IS_1829U_EQ_1829(...) \, +#define Z_IS_1829_EQ_1829U(...) \, +#define Z_IS_1829U_EQ_1829U(...) \, +#define Z_IS_1830_EQ_1830(...) \, +#define Z_IS_1830U_EQ_1830(...) \, +#define Z_IS_1830_EQ_1830U(...) \, +#define Z_IS_1830U_EQ_1830U(...) \, +#define Z_IS_1831_EQ_1831(...) \, +#define Z_IS_1831U_EQ_1831(...) \, +#define Z_IS_1831_EQ_1831U(...) \, +#define Z_IS_1831U_EQ_1831U(...) \, +#define Z_IS_1832_EQ_1832(...) \, +#define Z_IS_1832U_EQ_1832(...) \, +#define Z_IS_1832_EQ_1832U(...) \, +#define Z_IS_1832U_EQ_1832U(...) \, +#define Z_IS_1833_EQ_1833(...) \, +#define Z_IS_1833U_EQ_1833(...) \, +#define Z_IS_1833_EQ_1833U(...) \, +#define Z_IS_1833U_EQ_1833U(...) \, +#define Z_IS_1834_EQ_1834(...) \, +#define Z_IS_1834U_EQ_1834(...) \, +#define Z_IS_1834_EQ_1834U(...) \, +#define Z_IS_1834U_EQ_1834U(...) \, +#define Z_IS_1835_EQ_1835(...) \, +#define Z_IS_1835U_EQ_1835(...) \, +#define Z_IS_1835_EQ_1835U(...) \, +#define Z_IS_1835U_EQ_1835U(...) \, +#define Z_IS_1836_EQ_1836(...) \, +#define Z_IS_1836U_EQ_1836(...) \, +#define Z_IS_1836_EQ_1836U(...) \, +#define Z_IS_1836U_EQ_1836U(...) \, +#define Z_IS_1837_EQ_1837(...) \, +#define Z_IS_1837U_EQ_1837(...) \, +#define Z_IS_1837_EQ_1837U(...) \, +#define Z_IS_1837U_EQ_1837U(...) \, +#define Z_IS_1838_EQ_1838(...) \, +#define Z_IS_1838U_EQ_1838(...) \, +#define Z_IS_1838_EQ_1838U(...) \, +#define Z_IS_1838U_EQ_1838U(...) \, +#define Z_IS_1839_EQ_1839(...) \, +#define Z_IS_1839U_EQ_1839(...) \, +#define Z_IS_1839_EQ_1839U(...) \, +#define Z_IS_1839U_EQ_1839U(...) \, +#define Z_IS_1840_EQ_1840(...) \, +#define Z_IS_1840U_EQ_1840(...) \, +#define Z_IS_1840_EQ_1840U(...) \, +#define Z_IS_1840U_EQ_1840U(...) \, +#define Z_IS_1841_EQ_1841(...) \, +#define Z_IS_1841U_EQ_1841(...) \, +#define Z_IS_1841_EQ_1841U(...) \, +#define Z_IS_1841U_EQ_1841U(...) \, +#define Z_IS_1842_EQ_1842(...) \, +#define Z_IS_1842U_EQ_1842(...) \, +#define Z_IS_1842_EQ_1842U(...) \, +#define Z_IS_1842U_EQ_1842U(...) \, +#define Z_IS_1843_EQ_1843(...) \, +#define Z_IS_1843U_EQ_1843(...) \, +#define Z_IS_1843_EQ_1843U(...) \, +#define Z_IS_1843U_EQ_1843U(...) \, +#define Z_IS_1844_EQ_1844(...) \, +#define Z_IS_1844U_EQ_1844(...) \, +#define Z_IS_1844_EQ_1844U(...) \, +#define Z_IS_1844U_EQ_1844U(...) \, +#define Z_IS_1845_EQ_1845(...) \, +#define Z_IS_1845U_EQ_1845(...) \, +#define Z_IS_1845_EQ_1845U(...) \, +#define Z_IS_1845U_EQ_1845U(...) \, +#define Z_IS_1846_EQ_1846(...) \, +#define Z_IS_1846U_EQ_1846(...) \, +#define Z_IS_1846_EQ_1846U(...) \, +#define Z_IS_1846U_EQ_1846U(...) \, +#define Z_IS_1847_EQ_1847(...) \, +#define Z_IS_1847U_EQ_1847(...) \, +#define Z_IS_1847_EQ_1847U(...) \, +#define Z_IS_1847U_EQ_1847U(...) \, +#define Z_IS_1848_EQ_1848(...) \, +#define Z_IS_1848U_EQ_1848(...) \, +#define Z_IS_1848_EQ_1848U(...) \, +#define Z_IS_1848U_EQ_1848U(...) \, +#define Z_IS_1849_EQ_1849(...) \, +#define Z_IS_1849U_EQ_1849(...) \, +#define Z_IS_1849_EQ_1849U(...) \, +#define Z_IS_1849U_EQ_1849U(...) \, +#define Z_IS_1850_EQ_1850(...) \, +#define Z_IS_1850U_EQ_1850(...) \, +#define Z_IS_1850_EQ_1850U(...) \, +#define Z_IS_1850U_EQ_1850U(...) \, +#define Z_IS_1851_EQ_1851(...) \, +#define Z_IS_1851U_EQ_1851(...) \, +#define Z_IS_1851_EQ_1851U(...) \, +#define Z_IS_1851U_EQ_1851U(...) \, +#define Z_IS_1852_EQ_1852(...) \, +#define Z_IS_1852U_EQ_1852(...) \, +#define Z_IS_1852_EQ_1852U(...) \, +#define Z_IS_1852U_EQ_1852U(...) \, +#define Z_IS_1853_EQ_1853(...) \, +#define Z_IS_1853U_EQ_1853(...) \, +#define Z_IS_1853_EQ_1853U(...) \, +#define Z_IS_1853U_EQ_1853U(...) \, +#define Z_IS_1854_EQ_1854(...) \, +#define Z_IS_1854U_EQ_1854(...) \, +#define Z_IS_1854_EQ_1854U(...) \, +#define Z_IS_1854U_EQ_1854U(...) \, +#define Z_IS_1855_EQ_1855(...) \, +#define Z_IS_1855U_EQ_1855(...) \, +#define Z_IS_1855_EQ_1855U(...) \, +#define Z_IS_1855U_EQ_1855U(...) \, +#define Z_IS_1856_EQ_1856(...) \, +#define Z_IS_1856U_EQ_1856(...) \, +#define Z_IS_1856_EQ_1856U(...) \, +#define Z_IS_1856U_EQ_1856U(...) \, +#define Z_IS_1857_EQ_1857(...) \, +#define Z_IS_1857U_EQ_1857(...) \, +#define Z_IS_1857_EQ_1857U(...) \, +#define Z_IS_1857U_EQ_1857U(...) \, +#define Z_IS_1858_EQ_1858(...) \, +#define Z_IS_1858U_EQ_1858(...) \, +#define Z_IS_1858_EQ_1858U(...) \, +#define Z_IS_1858U_EQ_1858U(...) \, +#define Z_IS_1859_EQ_1859(...) \, +#define Z_IS_1859U_EQ_1859(...) \, +#define Z_IS_1859_EQ_1859U(...) \, +#define Z_IS_1859U_EQ_1859U(...) \, +#define Z_IS_1860_EQ_1860(...) \, +#define Z_IS_1860U_EQ_1860(...) \, +#define Z_IS_1860_EQ_1860U(...) \, +#define Z_IS_1860U_EQ_1860U(...) \, +#define Z_IS_1861_EQ_1861(...) \, +#define Z_IS_1861U_EQ_1861(...) \, +#define Z_IS_1861_EQ_1861U(...) \, +#define Z_IS_1861U_EQ_1861U(...) \, +#define Z_IS_1862_EQ_1862(...) \, +#define Z_IS_1862U_EQ_1862(...) \, +#define Z_IS_1862_EQ_1862U(...) \, +#define Z_IS_1862U_EQ_1862U(...) \, +#define Z_IS_1863_EQ_1863(...) \, +#define Z_IS_1863U_EQ_1863(...) \, +#define Z_IS_1863_EQ_1863U(...) \, +#define Z_IS_1863U_EQ_1863U(...) \, +#define Z_IS_1864_EQ_1864(...) \, +#define Z_IS_1864U_EQ_1864(...) \, +#define Z_IS_1864_EQ_1864U(...) \, +#define Z_IS_1864U_EQ_1864U(...) \, +#define Z_IS_1865_EQ_1865(...) \, +#define Z_IS_1865U_EQ_1865(...) \, +#define Z_IS_1865_EQ_1865U(...) \, +#define Z_IS_1865U_EQ_1865U(...) \, +#define Z_IS_1866_EQ_1866(...) \, +#define Z_IS_1866U_EQ_1866(...) \, +#define Z_IS_1866_EQ_1866U(...) \, +#define Z_IS_1866U_EQ_1866U(...) \, +#define Z_IS_1867_EQ_1867(...) \, +#define Z_IS_1867U_EQ_1867(...) \, +#define Z_IS_1867_EQ_1867U(...) \, +#define Z_IS_1867U_EQ_1867U(...) \, +#define Z_IS_1868_EQ_1868(...) \, +#define Z_IS_1868U_EQ_1868(...) \, +#define Z_IS_1868_EQ_1868U(...) \, +#define Z_IS_1868U_EQ_1868U(...) \, +#define Z_IS_1869_EQ_1869(...) \, +#define Z_IS_1869U_EQ_1869(...) \, +#define Z_IS_1869_EQ_1869U(...) \, +#define Z_IS_1869U_EQ_1869U(...) \, +#define Z_IS_1870_EQ_1870(...) \, +#define Z_IS_1870U_EQ_1870(...) \, +#define Z_IS_1870_EQ_1870U(...) \, +#define Z_IS_1870U_EQ_1870U(...) \, +#define Z_IS_1871_EQ_1871(...) \, +#define Z_IS_1871U_EQ_1871(...) \, +#define Z_IS_1871_EQ_1871U(...) \, +#define Z_IS_1871U_EQ_1871U(...) \, +#define Z_IS_1872_EQ_1872(...) \, +#define Z_IS_1872U_EQ_1872(...) \, +#define Z_IS_1872_EQ_1872U(...) \, +#define Z_IS_1872U_EQ_1872U(...) \, +#define Z_IS_1873_EQ_1873(...) \, +#define Z_IS_1873U_EQ_1873(...) \, +#define Z_IS_1873_EQ_1873U(...) \, +#define Z_IS_1873U_EQ_1873U(...) \, +#define Z_IS_1874_EQ_1874(...) \, +#define Z_IS_1874U_EQ_1874(...) \, +#define Z_IS_1874_EQ_1874U(...) \, +#define Z_IS_1874U_EQ_1874U(...) \, +#define Z_IS_1875_EQ_1875(...) \, +#define Z_IS_1875U_EQ_1875(...) \, +#define Z_IS_1875_EQ_1875U(...) \, +#define Z_IS_1875U_EQ_1875U(...) \, +#define Z_IS_1876_EQ_1876(...) \, +#define Z_IS_1876U_EQ_1876(...) \, +#define Z_IS_1876_EQ_1876U(...) \, +#define Z_IS_1876U_EQ_1876U(...) \, +#define Z_IS_1877_EQ_1877(...) \, +#define Z_IS_1877U_EQ_1877(...) \, +#define Z_IS_1877_EQ_1877U(...) \, +#define Z_IS_1877U_EQ_1877U(...) \, +#define Z_IS_1878_EQ_1878(...) \, +#define Z_IS_1878U_EQ_1878(...) \, +#define Z_IS_1878_EQ_1878U(...) \, +#define Z_IS_1878U_EQ_1878U(...) \, +#define Z_IS_1879_EQ_1879(...) \, +#define Z_IS_1879U_EQ_1879(...) \, +#define Z_IS_1879_EQ_1879U(...) \, +#define Z_IS_1879U_EQ_1879U(...) \, +#define Z_IS_1880_EQ_1880(...) \, +#define Z_IS_1880U_EQ_1880(...) \, +#define Z_IS_1880_EQ_1880U(...) \, +#define Z_IS_1880U_EQ_1880U(...) \, +#define Z_IS_1881_EQ_1881(...) \, +#define Z_IS_1881U_EQ_1881(...) \, +#define Z_IS_1881_EQ_1881U(...) \, +#define Z_IS_1881U_EQ_1881U(...) \, +#define Z_IS_1882_EQ_1882(...) \, +#define Z_IS_1882U_EQ_1882(...) \, +#define Z_IS_1882_EQ_1882U(...) \, +#define Z_IS_1882U_EQ_1882U(...) \, +#define Z_IS_1883_EQ_1883(...) \, +#define Z_IS_1883U_EQ_1883(...) \, +#define Z_IS_1883_EQ_1883U(...) \, +#define Z_IS_1883U_EQ_1883U(...) \, +#define Z_IS_1884_EQ_1884(...) \, +#define Z_IS_1884U_EQ_1884(...) \, +#define Z_IS_1884_EQ_1884U(...) \, +#define Z_IS_1884U_EQ_1884U(...) \, +#define Z_IS_1885_EQ_1885(...) \, +#define Z_IS_1885U_EQ_1885(...) \, +#define Z_IS_1885_EQ_1885U(...) \, +#define Z_IS_1885U_EQ_1885U(...) \, +#define Z_IS_1886_EQ_1886(...) \, +#define Z_IS_1886U_EQ_1886(...) \, +#define Z_IS_1886_EQ_1886U(...) \, +#define Z_IS_1886U_EQ_1886U(...) \, +#define Z_IS_1887_EQ_1887(...) \, +#define Z_IS_1887U_EQ_1887(...) \, +#define Z_IS_1887_EQ_1887U(...) \, +#define Z_IS_1887U_EQ_1887U(...) \, +#define Z_IS_1888_EQ_1888(...) \, +#define Z_IS_1888U_EQ_1888(...) \, +#define Z_IS_1888_EQ_1888U(...) \, +#define Z_IS_1888U_EQ_1888U(...) \, +#define Z_IS_1889_EQ_1889(...) \, +#define Z_IS_1889U_EQ_1889(...) \, +#define Z_IS_1889_EQ_1889U(...) \, +#define Z_IS_1889U_EQ_1889U(...) \, +#define Z_IS_1890_EQ_1890(...) \, +#define Z_IS_1890U_EQ_1890(...) \, +#define Z_IS_1890_EQ_1890U(...) \, +#define Z_IS_1890U_EQ_1890U(...) \, +#define Z_IS_1891_EQ_1891(...) \, +#define Z_IS_1891U_EQ_1891(...) \, +#define Z_IS_1891_EQ_1891U(...) \, +#define Z_IS_1891U_EQ_1891U(...) \, +#define Z_IS_1892_EQ_1892(...) \, +#define Z_IS_1892U_EQ_1892(...) \, +#define Z_IS_1892_EQ_1892U(...) \, +#define Z_IS_1892U_EQ_1892U(...) \, +#define Z_IS_1893_EQ_1893(...) \, +#define Z_IS_1893U_EQ_1893(...) \, +#define Z_IS_1893_EQ_1893U(...) \, +#define Z_IS_1893U_EQ_1893U(...) \, +#define Z_IS_1894_EQ_1894(...) \, +#define Z_IS_1894U_EQ_1894(...) \, +#define Z_IS_1894_EQ_1894U(...) \, +#define Z_IS_1894U_EQ_1894U(...) \, +#define Z_IS_1895_EQ_1895(...) \, +#define Z_IS_1895U_EQ_1895(...) \, +#define Z_IS_1895_EQ_1895U(...) \, +#define Z_IS_1895U_EQ_1895U(...) \, +#define Z_IS_1896_EQ_1896(...) \, +#define Z_IS_1896U_EQ_1896(...) \, +#define Z_IS_1896_EQ_1896U(...) \, +#define Z_IS_1896U_EQ_1896U(...) \, +#define Z_IS_1897_EQ_1897(...) \, +#define Z_IS_1897U_EQ_1897(...) \, +#define Z_IS_1897_EQ_1897U(...) \, +#define Z_IS_1897U_EQ_1897U(...) \, +#define Z_IS_1898_EQ_1898(...) \, +#define Z_IS_1898U_EQ_1898(...) \, +#define Z_IS_1898_EQ_1898U(...) \, +#define Z_IS_1898U_EQ_1898U(...) \, +#define Z_IS_1899_EQ_1899(...) \, +#define Z_IS_1899U_EQ_1899(...) \, +#define Z_IS_1899_EQ_1899U(...) \, +#define Z_IS_1899U_EQ_1899U(...) \, +#define Z_IS_1900_EQ_1900(...) \, +#define Z_IS_1900U_EQ_1900(...) \, +#define Z_IS_1900_EQ_1900U(...) \, +#define Z_IS_1900U_EQ_1900U(...) \, +#define Z_IS_1901_EQ_1901(...) \, +#define Z_IS_1901U_EQ_1901(...) \, +#define Z_IS_1901_EQ_1901U(...) \, +#define Z_IS_1901U_EQ_1901U(...) \, +#define Z_IS_1902_EQ_1902(...) \, +#define Z_IS_1902U_EQ_1902(...) \, +#define Z_IS_1902_EQ_1902U(...) \, +#define Z_IS_1902U_EQ_1902U(...) \, +#define Z_IS_1903_EQ_1903(...) \, +#define Z_IS_1903U_EQ_1903(...) \, +#define Z_IS_1903_EQ_1903U(...) \, +#define Z_IS_1903U_EQ_1903U(...) \, +#define Z_IS_1904_EQ_1904(...) \, +#define Z_IS_1904U_EQ_1904(...) \, +#define Z_IS_1904_EQ_1904U(...) \, +#define Z_IS_1904U_EQ_1904U(...) \, +#define Z_IS_1905_EQ_1905(...) \, +#define Z_IS_1905U_EQ_1905(...) \, +#define Z_IS_1905_EQ_1905U(...) \, +#define Z_IS_1905U_EQ_1905U(...) \, +#define Z_IS_1906_EQ_1906(...) \, +#define Z_IS_1906U_EQ_1906(...) \, +#define Z_IS_1906_EQ_1906U(...) \, +#define Z_IS_1906U_EQ_1906U(...) \, +#define Z_IS_1907_EQ_1907(...) \, +#define Z_IS_1907U_EQ_1907(...) \, +#define Z_IS_1907_EQ_1907U(...) \, +#define Z_IS_1907U_EQ_1907U(...) \, +#define Z_IS_1908_EQ_1908(...) \, +#define Z_IS_1908U_EQ_1908(...) \, +#define Z_IS_1908_EQ_1908U(...) \, +#define Z_IS_1908U_EQ_1908U(...) \, +#define Z_IS_1909_EQ_1909(...) \, +#define Z_IS_1909U_EQ_1909(...) \, +#define Z_IS_1909_EQ_1909U(...) \, +#define Z_IS_1909U_EQ_1909U(...) \, +#define Z_IS_1910_EQ_1910(...) \, +#define Z_IS_1910U_EQ_1910(...) \, +#define Z_IS_1910_EQ_1910U(...) \, +#define Z_IS_1910U_EQ_1910U(...) \, +#define Z_IS_1911_EQ_1911(...) \, +#define Z_IS_1911U_EQ_1911(...) \, +#define Z_IS_1911_EQ_1911U(...) \, +#define Z_IS_1911U_EQ_1911U(...) \, +#define Z_IS_1912_EQ_1912(...) \, +#define Z_IS_1912U_EQ_1912(...) \, +#define Z_IS_1912_EQ_1912U(...) \, +#define Z_IS_1912U_EQ_1912U(...) \, +#define Z_IS_1913_EQ_1913(...) \, +#define Z_IS_1913U_EQ_1913(...) \, +#define Z_IS_1913_EQ_1913U(...) \, +#define Z_IS_1913U_EQ_1913U(...) \, +#define Z_IS_1914_EQ_1914(...) \, +#define Z_IS_1914U_EQ_1914(...) \, +#define Z_IS_1914_EQ_1914U(...) \, +#define Z_IS_1914U_EQ_1914U(...) \, +#define Z_IS_1915_EQ_1915(...) \, +#define Z_IS_1915U_EQ_1915(...) \, +#define Z_IS_1915_EQ_1915U(...) \, +#define Z_IS_1915U_EQ_1915U(...) \, +#define Z_IS_1916_EQ_1916(...) \, +#define Z_IS_1916U_EQ_1916(...) \, +#define Z_IS_1916_EQ_1916U(...) \, +#define Z_IS_1916U_EQ_1916U(...) \, +#define Z_IS_1917_EQ_1917(...) \, +#define Z_IS_1917U_EQ_1917(...) \, +#define Z_IS_1917_EQ_1917U(...) \, +#define Z_IS_1917U_EQ_1917U(...) \, +#define Z_IS_1918_EQ_1918(...) \, +#define Z_IS_1918U_EQ_1918(...) \, +#define Z_IS_1918_EQ_1918U(...) \, +#define Z_IS_1918U_EQ_1918U(...) \, +#define Z_IS_1919_EQ_1919(...) \, +#define Z_IS_1919U_EQ_1919(...) \, +#define Z_IS_1919_EQ_1919U(...) \, +#define Z_IS_1919U_EQ_1919U(...) \, +#define Z_IS_1920_EQ_1920(...) \, +#define Z_IS_1920U_EQ_1920(...) \, +#define Z_IS_1920_EQ_1920U(...) \, +#define Z_IS_1920U_EQ_1920U(...) \, +#define Z_IS_1921_EQ_1921(...) \, +#define Z_IS_1921U_EQ_1921(...) \, +#define Z_IS_1921_EQ_1921U(...) \, +#define Z_IS_1921U_EQ_1921U(...) \, +#define Z_IS_1922_EQ_1922(...) \, +#define Z_IS_1922U_EQ_1922(...) \, +#define Z_IS_1922_EQ_1922U(...) \, +#define Z_IS_1922U_EQ_1922U(...) \, +#define Z_IS_1923_EQ_1923(...) \, +#define Z_IS_1923U_EQ_1923(...) \, +#define Z_IS_1923_EQ_1923U(...) \, +#define Z_IS_1923U_EQ_1923U(...) \, +#define Z_IS_1924_EQ_1924(...) \, +#define Z_IS_1924U_EQ_1924(...) \, +#define Z_IS_1924_EQ_1924U(...) \, +#define Z_IS_1924U_EQ_1924U(...) \, +#define Z_IS_1925_EQ_1925(...) \, +#define Z_IS_1925U_EQ_1925(...) \, +#define Z_IS_1925_EQ_1925U(...) \, +#define Z_IS_1925U_EQ_1925U(...) \, +#define Z_IS_1926_EQ_1926(...) \, +#define Z_IS_1926U_EQ_1926(...) \, +#define Z_IS_1926_EQ_1926U(...) \, +#define Z_IS_1926U_EQ_1926U(...) \, +#define Z_IS_1927_EQ_1927(...) \, +#define Z_IS_1927U_EQ_1927(...) \, +#define Z_IS_1927_EQ_1927U(...) \, +#define Z_IS_1927U_EQ_1927U(...) \, +#define Z_IS_1928_EQ_1928(...) \, +#define Z_IS_1928U_EQ_1928(...) \, +#define Z_IS_1928_EQ_1928U(...) \, +#define Z_IS_1928U_EQ_1928U(...) \, +#define Z_IS_1929_EQ_1929(...) \, +#define Z_IS_1929U_EQ_1929(...) \, +#define Z_IS_1929_EQ_1929U(...) \, +#define Z_IS_1929U_EQ_1929U(...) \, +#define Z_IS_1930_EQ_1930(...) \, +#define Z_IS_1930U_EQ_1930(...) \, +#define Z_IS_1930_EQ_1930U(...) \, +#define Z_IS_1930U_EQ_1930U(...) \, +#define Z_IS_1931_EQ_1931(...) \, +#define Z_IS_1931U_EQ_1931(...) \, +#define Z_IS_1931_EQ_1931U(...) \, +#define Z_IS_1931U_EQ_1931U(...) \, +#define Z_IS_1932_EQ_1932(...) \, +#define Z_IS_1932U_EQ_1932(...) \, +#define Z_IS_1932_EQ_1932U(...) \, +#define Z_IS_1932U_EQ_1932U(...) \, +#define Z_IS_1933_EQ_1933(...) \, +#define Z_IS_1933U_EQ_1933(...) \, +#define Z_IS_1933_EQ_1933U(...) \, +#define Z_IS_1933U_EQ_1933U(...) \, +#define Z_IS_1934_EQ_1934(...) \, +#define Z_IS_1934U_EQ_1934(...) \, +#define Z_IS_1934_EQ_1934U(...) \, +#define Z_IS_1934U_EQ_1934U(...) \, +#define Z_IS_1935_EQ_1935(...) \, +#define Z_IS_1935U_EQ_1935(...) \, +#define Z_IS_1935_EQ_1935U(...) \, +#define Z_IS_1935U_EQ_1935U(...) \, +#define Z_IS_1936_EQ_1936(...) \, +#define Z_IS_1936U_EQ_1936(...) \, +#define Z_IS_1936_EQ_1936U(...) \, +#define Z_IS_1936U_EQ_1936U(...) \, +#define Z_IS_1937_EQ_1937(...) \, +#define Z_IS_1937U_EQ_1937(...) \, +#define Z_IS_1937_EQ_1937U(...) \, +#define Z_IS_1937U_EQ_1937U(...) \, +#define Z_IS_1938_EQ_1938(...) \, +#define Z_IS_1938U_EQ_1938(...) \, +#define Z_IS_1938_EQ_1938U(...) \, +#define Z_IS_1938U_EQ_1938U(...) \, +#define Z_IS_1939_EQ_1939(...) \, +#define Z_IS_1939U_EQ_1939(...) \, +#define Z_IS_1939_EQ_1939U(...) \, +#define Z_IS_1939U_EQ_1939U(...) \, +#define Z_IS_1940_EQ_1940(...) \, +#define Z_IS_1940U_EQ_1940(...) \, +#define Z_IS_1940_EQ_1940U(...) \, +#define Z_IS_1940U_EQ_1940U(...) \, +#define Z_IS_1941_EQ_1941(...) \, +#define Z_IS_1941U_EQ_1941(...) \, +#define Z_IS_1941_EQ_1941U(...) \, +#define Z_IS_1941U_EQ_1941U(...) \, +#define Z_IS_1942_EQ_1942(...) \, +#define Z_IS_1942U_EQ_1942(...) \, +#define Z_IS_1942_EQ_1942U(...) \, +#define Z_IS_1942U_EQ_1942U(...) \, +#define Z_IS_1943_EQ_1943(...) \, +#define Z_IS_1943U_EQ_1943(...) \, +#define Z_IS_1943_EQ_1943U(...) \, +#define Z_IS_1943U_EQ_1943U(...) \, +#define Z_IS_1944_EQ_1944(...) \, +#define Z_IS_1944U_EQ_1944(...) \, +#define Z_IS_1944_EQ_1944U(...) \, +#define Z_IS_1944U_EQ_1944U(...) \, +#define Z_IS_1945_EQ_1945(...) \, +#define Z_IS_1945U_EQ_1945(...) \, +#define Z_IS_1945_EQ_1945U(...) \, +#define Z_IS_1945U_EQ_1945U(...) \, +#define Z_IS_1946_EQ_1946(...) \, +#define Z_IS_1946U_EQ_1946(...) \, +#define Z_IS_1946_EQ_1946U(...) \, +#define Z_IS_1946U_EQ_1946U(...) \, +#define Z_IS_1947_EQ_1947(...) \, +#define Z_IS_1947U_EQ_1947(...) \, +#define Z_IS_1947_EQ_1947U(...) \, +#define Z_IS_1947U_EQ_1947U(...) \, +#define Z_IS_1948_EQ_1948(...) \, +#define Z_IS_1948U_EQ_1948(...) \, +#define Z_IS_1948_EQ_1948U(...) \, +#define Z_IS_1948U_EQ_1948U(...) \, +#define Z_IS_1949_EQ_1949(...) \, +#define Z_IS_1949U_EQ_1949(...) \, +#define Z_IS_1949_EQ_1949U(...) \, +#define Z_IS_1949U_EQ_1949U(...) \, +#define Z_IS_1950_EQ_1950(...) \, +#define Z_IS_1950U_EQ_1950(...) \, +#define Z_IS_1950_EQ_1950U(...) \, +#define Z_IS_1950U_EQ_1950U(...) \, +#define Z_IS_1951_EQ_1951(...) \, +#define Z_IS_1951U_EQ_1951(...) \, +#define Z_IS_1951_EQ_1951U(...) \, +#define Z_IS_1951U_EQ_1951U(...) \, +#define Z_IS_1952_EQ_1952(...) \, +#define Z_IS_1952U_EQ_1952(...) \, +#define Z_IS_1952_EQ_1952U(...) \, +#define Z_IS_1952U_EQ_1952U(...) \, +#define Z_IS_1953_EQ_1953(...) \, +#define Z_IS_1953U_EQ_1953(...) \, +#define Z_IS_1953_EQ_1953U(...) \, +#define Z_IS_1953U_EQ_1953U(...) \, +#define Z_IS_1954_EQ_1954(...) \, +#define Z_IS_1954U_EQ_1954(...) \, +#define Z_IS_1954_EQ_1954U(...) \, +#define Z_IS_1954U_EQ_1954U(...) \, +#define Z_IS_1955_EQ_1955(...) \, +#define Z_IS_1955U_EQ_1955(...) \, +#define Z_IS_1955_EQ_1955U(...) \, +#define Z_IS_1955U_EQ_1955U(...) \, +#define Z_IS_1956_EQ_1956(...) \, +#define Z_IS_1956U_EQ_1956(...) \, +#define Z_IS_1956_EQ_1956U(...) \, +#define Z_IS_1956U_EQ_1956U(...) \, +#define Z_IS_1957_EQ_1957(...) \, +#define Z_IS_1957U_EQ_1957(...) \, +#define Z_IS_1957_EQ_1957U(...) \, +#define Z_IS_1957U_EQ_1957U(...) \, +#define Z_IS_1958_EQ_1958(...) \, +#define Z_IS_1958U_EQ_1958(...) \, +#define Z_IS_1958_EQ_1958U(...) \, +#define Z_IS_1958U_EQ_1958U(...) \, +#define Z_IS_1959_EQ_1959(...) \, +#define Z_IS_1959U_EQ_1959(...) \, +#define Z_IS_1959_EQ_1959U(...) \, +#define Z_IS_1959U_EQ_1959U(...) \, +#define Z_IS_1960_EQ_1960(...) \, +#define Z_IS_1960U_EQ_1960(...) \, +#define Z_IS_1960_EQ_1960U(...) \, +#define Z_IS_1960U_EQ_1960U(...) \, +#define Z_IS_1961_EQ_1961(...) \, +#define Z_IS_1961U_EQ_1961(...) \, +#define Z_IS_1961_EQ_1961U(...) \, +#define Z_IS_1961U_EQ_1961U(...) \, +#define Z_IS_1962_EQ_1962(...) \, +#define Z_IS_1962U_EQ_1962(...) \, +#define Z_IS_1962_EQ_1962U(...) \, +#define Z_IS_1962U_EQ_1962U(...) \, +#define Z_IS_1963_EQ_1963(...) \, +#define Z_IS_1963U_EQ_1963(...) \, +#define Z_IS_1963_EQ_1963U(...) \, +#define Z_IS_1963U_EQ_1963U(...) \, +#define Z_IS_1964_EQ_1964(...) \, +#define Z_IS_1964U_EQ_1964(...) \, +#define Z_IS_1964_EQ_1964U(...) \, +#define Z_IS_1964U_EQ_1964U(...) \, +#define Z_IS_1965_EQ_1965(...) \, +#define Z_IS_1965U_EQ_1965(...) \, +#define Z_IS_1965_EQ_1965U(...) \, +#define Z_IS_1965U_EQ_1965U(...) \, +#define Z_IS_1966_EQ_1966(...) \, +#define Z_IS_1966U_EQ_1966(...) \, +#define Z_IS_1966_EQ_1966U(...) \, +#define Z_IS_1966U_EQ_1966U(...) \, +#define Z_IS_1967_EQ_1967(...) \, +#define Z_IS_1967U_EQ_1967(...) \, +#define Z_IS_1967_EQ_1967U(...) \, +#define Z_IS_1967U_EQ_1967U(...) \, +#define Z_IS_1968_EQ_1968(...) \, +#define Z_IS_1968U_EQ_1968(...) \, +#define Z_IS_1968_EQ_1968U(...) \, +#define Z_IS_1968U_EQ_1968U(...) \, +#define Z_IS_1969_EQ_1969(...) \, +#define Z_IS_1969U_EQ_1969(...) \, +#define Z_IS_1969_EQ_1969U(...) \, +#define Z_IS_1969U_EQ_1969U(...) \, +#define Z_IS_1970_EQ_1970(...) \, +#define Z_IS_1970U_EQ_1970(...) \, +#define Z_IS_1970_EQ_1970U(...) \, +#define Z_IS_1970U_EQ_1970U(...) \, +#define Z_IS_1971_EQ_1971(...) \, +#define Z_IS_1971U_EQ_1971(...) \, +#define Z_IS_1971_EQ_1971U(...) \, +#define Z_IS_1971U_EQ_1971U(...) \, +#define Z_IS_1972_EQ_1972(...) \, +#define Z_IS_1972U_EQ_1972(...) \, +#define Z_IS_1972_EQ_1972U(...) \, +#define Z_IS_1972U_EQ_1972U(...) \, +#define Z_IS_1973_EQ_1973(...) \, +#define Z_IS_1973U_EQ_1973(...) \, +#define Z_IS_1973_EQ_1973U(...) \, +#define Z_IS_1973U_EQ_1973U(...) \, +#define Z_IS_1974_EQ_1974(...) \, +#define Z_IS_1974U_EQ_1974(...) \, +#define Z_IS_1974_EQ_1974U(...) \, +#define Z_IS_1974U_EQ_1974U(...) \, +#define Z_IS_1975_EQ_1975(...) \, +#define Z_IS_1975U_EQ_1975(...) \, +#define Z_IS_1975_EQ_1975U(...) \, +#define Z_IS_1975U_EQ_1975U(...) \, +#define Z_IS_1976_EQ_1976(...) \, +#define Z_IS_1976U_EQ_1976(...) \, +#define Z_IS_1976_EQ_1976U(...) \, +#define Z_IS_1976U_EQ_1976U(...) \, +#define Z_IS_1977_EQ_1977(...) \, +#define Z_IS_1977U_EQ_1977(...) \, +#define Z_IS_1977_EQ_1977U(...) \, +#define Z_IS_1977U_EQ_1977U(...) \, +#define Z_IS_1978_EQ_1978(...) \, +#define Z_IS_1978U_EQ_1978(...) \, +#define Z_IS_1978_EQ_1978U(...) \, +#define Z_IS_1978U_EQ_1978U(...) \, +#define Z_IS_1979_EQ_1979(...) \, +#define Z_IS_1979U_EQ_1979(...) \, +#define Z_IS_1979_EQ_1979U(...) \, +#define Z_IS_1979U_EQ_1979U(...) \, +#define Z_IS_1980_EQ_1980(...) \, +#define Z_IS_1980U_EQ_1980(...) \, +#define Z_IS_1980_EQ_1980U(...) \, +#define Z_IS_1980U_EQ_1980U(...) \, +#define Z_IS_1981_EQ_1981(...) \, +#define Z_IS_1981U_EQ_1981(...) \, +#define Z_IS_1981_EQ_1981U(...) \, +#define Z_IS_1981U_EQ_1981U(...) \, +#define Z_IS_1982_EQ_1982(...) \, +#define Z_IS_1982U_EQ_1982(...) \, +#define Z_IS_1982_EQ_1982U(...) \, +#define Z_IS_1982U_EQ_1982U(...) \, +#define Z_IS_1983_EQ_1983(...) \, +#define Z_IS_1983U_EQ_1983(...) \, +#define Z_IS_1983_EQ_1983U(...) \, +#define Z_IS_1983U_EQ_1983U(...) \, +#define Z_IS_1984_EQ_1984(...) \, +#define Z_IS_1984U_EQ_1984(...) \, +#define Z_IS_1984_EQ_1984U(...) \, +#define Z_IS_1984U_EQ_1984U(...) \, +#define Z_IS_1985_EQ_1985(...) \, +#define Z_IS_1985U_EQ_1985(...) \, +#define Z_IS_1985_EQ_1985U(...) \, +#define Z_IS_1985U_EQ_1985U(...) \, +#define Z_IS_1986_EQ_1986(...) \, +#define Z_IS_1986U_EQ_1986(...) \, +#define Z_IS_1986_EQ_1986U(...) \, +#define Z_IS_1986U_EQ_1986U(...) \, +#define Z_IS_1987_EQ_1987(...) \, +#define Z_IS_1987U_EQ_1987(...) \, +#define Z_IS_1987_EQ_1987U(...) \, +#define Z_IS_1987U_EQ_1987U(...) \, +#define Z_IS_1988_EQ_1988(...) \, +#define Z_IS_1988U_EQ_1988(...) \, +#define Z_IS_1988_EQ_1988U(...) \, +#define Z_IS_1988U_EQ_1988U(...) \, +#define Z_IS_1989_EQ_1989(...) \, +#define Z_IS_1989U_EQ_1989(...) \, +#define Z_IS_1989_EQ_1989U(...) \, +#define Z_IS_1989U_EQ_1989U(...) \, +#define Z_IS_1990_EQ_1990(...) \, +#define Z_IS_1990U_EQ_1990(...) \, +#define Z_IS_1990_EQ_1990U(...) \, +#define Z_IS_1990U_EQ_1990U(...) \, +#define Z_IS_1991_EQ_1991(...) \, +#define Z_IS_1991U_EQ_1991(...) \, +#define Z_IS_1991_EQ_1991U(...) \, +#define Z_IS_1991U_EQ_1991U(...) \, +#define Z_IS_1992_EQ_1992(...) \, +#define Z_IS_1992U_EQ_1992(...) \, +#define Z_IS_1992_EQ_1992U(...) \, +#define Z_IS_1992U_EQ_1992U(...) \, +#define Z_IS_1993_EQ_1993(...) \, +#define Z_IS_1993U_EQ_1993(...) \, +#define Z_IS_1993_EQ_1993U(...) \, +#define Z_IS_1993U_EQ_1993U(...) \, +#define Z_IS_1994_EQ_1994(...) \, +#define Z_IS_1994U_EQ_1994(...) \, +#define Z_IS_1994_EQ_1994U(...) \, +#define Z_IS_1994U_EQ_1994U(...) \, +#define Z_IS_1995_EQ_1995(...) \, +#define Z_IS_1995U_EQ_1995(...) \, +#define Z_IS_1995_EQ_1995U(...) \, +#define Z_IS_1995U_EQ_1995U(...) \, +#define Z_IS_1996_EQ_1996(...) \, +#define Z_IS_1996U_EQ_1996(...) \, +#define Z_IS_1996_EQ_1996U(...) \, +#define Z_IS_1996U_EQ_1996U(...) \, +#define Z_IS_1997_EQ_1997(...) \, +#define Z_IS_1997U_EQ_1997(...) \, +#define Z_IS_1997_EQ_1997U(...) \, +#define Z_IS_1997U_EQ_1997U(...) \, +#define Z_IS_1998_EQ_1998(...) \, +#define Z_IS_1998U_EQ_1998(...) \, +#define Z_IS_1998_EQ_1998U(...) \, +#define Z_IS_1998U_EQ_1998U(...) \, +#define Z_IS_1999_EQ_1999(...) \, +#define Z_IS_1999U_EQ_1999(...) \, +#define Z_IS_1999_EQ_1999U(...) \, +#define Z_IS_1999U_EQ_1999U(...) \, +#define Z_IS_2000_EQ_2000(...) \, +#define Z_IS_2000U_EQ_2000(...) \, +#define Z_IS_2000_EQ_2000U(...) \, +#define Z_IS_2000U_EQ_2000U(...) \, +#define Z_IS_2001_EQ_2001(...) \, +#define Z_IS_2001U_EQ_2001(...) \, +#define Z_IS_2001_EQ_2001U(...) \, +#define Z_IS_2001U_EQ_2001U(...) \, +#define Z_IS_2002_EQ_2002(...) \, +#define Z_IS_2002U_EQ_2002(...) \, +#define Z_IS_2002_EQ_2002U(...) \, +#define Z_IS_2002U_EQ_2002U(...) \, +#define Z_IS_2003_EQ_2003(...) \, +#define Z_IS_2003U_EQ_2003(...) \, +#define Z_IS_2003_EQ_2003U(...) \, +#define Z_IS_2003U_EQ_2003U(...) \, +#define Z_IS_2004_EQ_2004(...) \, +#define Z_IS_2004U_EQ_2004(...) \, +#define Z_IS_2004_EQ_2004U(...) \, +#define Z_IS_2004U_EQ_2004U(...) \, +#define Z_IS_2005_EQ_2005(...) \, +#define Z_IS_2005U_EQ_2005(...) \, +#define Z_IS_2005_EQ_2005U(...) \, +#define Z_IS_2005U_EQ_2005U(...) \, +#define Z_IS_2006_EQ_2006(...) \, +#define Z_IS_2006U_EQ_2006(...) \, +#define Z_IS_2006_EQ_2006U(...) \, +#define Z_IS_2006U_EQ_2006U(...) \, +#define Z_IS_2007_EQ_2007(...) \, +#define Z_IS_2007U_EQ_2007(...) \, +#define Z_IS_2007_EQ_2007U(...) \, +#define Z_IS_2007U_EQ_2007U(...) \, +#define Z_IS_2008_EQ_2008(...) \, +#define Z_IS_2008U_EQ_2008(...) \, +#define Z_IS_2008_EQ_2008U(...) \, +#define Z_IS_2008U_EQ_2008U(...) \, +#define Z_IS_2009_EQ_2009(...) \, +#define Z_IS_2009U_EQ_2009(...) \, +#define Z_IS_2009_EQ_2009U(...) \, +#define Z_IS_2009U_EQ_2009U(...) \, +#define Z_IS_2010_EQ_2010(...) \, +#define Z_IS_2010U_EQ_2010(...) \, +#define Z_IS_2010_EQ_2010U(...) \, +#define Z_IS_2010U_EQ_2010U(...) \, +#define Z_IS_2011_EQ_2011(...) \, +#define Z_IS_2011U_EQ_2011(...) \, +#define Z_IS_2011_EQ_2011U(...) \, +#define Z_IS_2011U_EQ_2011U(...) \, +#define Z_IS_2012_EQ_2012(...) \, +#define Z_IS_2012U_EQ_2012(...) \, +#define Z_IS_2012_EQ_2012U(...) \, +#define Z_IS_2012U_EQ_2012U(...) \, +#define Z_IS_2013_EQ_2013(...) \, +#define Z_IS_2013U_EQ_2013(...) \, +#define Z_IS_2013_EQ_2013U(...) \, +#define Z_IS_2013U_EQ_2013U(...) \, +#define Z_IS_2014_EQ_2014(...) \, +#define Z_IS_2014U_EQ_2014(...) \, +#define Z_IS_2014_EQ_2014U(...) \, +#define Z_IS_2014U_EQ_2014U(...) \, +#define Z_IS_2015_EQ_2015(...) \, +#define Z_IS_2015U_EQ_2015(...) \, +#define Z_IS_2015_EQ_2015U(...) \, +#define Z_IS_2015U_EQ_2015U(...) \, +#define Z_IS_2016_EQ_2016(...) \, +#define Z_IS_2016U_EQ_2016(...) \, +#define Z_IS_2016_EQ_2016U(...) \, +#define Z_IS_2016U_EQ_2016U(...) \, +#define Z_IS_2017_EQ_2017(...) \, +#define Z_IS_2017U_EQ_2017(...) \, +#define Z_IS_2017_EQ_2017U(...) \, +#define Z_IS_2017U_EQ_2017U(...) \, +#define Z_IS_2018_EQ_2018(...) \, +#define Z_IS_2018U_EQ_2018(...) \, +#define Z_IS_2018_EQ_2018U(...) \, +#define Z_IS_2018U_EQ_2018U(...) \, +#define Z_IS_2019_EQ_2019(...) \, +#define Z_IS_2019U_EQ_2019(...) \, +#define Z_IS_2019_EQ_2019U(...) \, +#define Z_IS_2019U_EQ_2019U(...) \, +#define Z_IS_2020_EQ_2020(...) \, +#define Z_IS_2020U_EQ_2020(...) \, +#define Z_IS_2020_EQ_2020U(...) \, +#define Z_IS_2020U_EQ_2020U(...) \, +#define Z_IS_2021_EQ_2021(...) \, +#define Z_IS_2021U_EQ_2021(...) \, +#define Z_IS_2021_EQ_2021U(...) \, +#define Z_IS_2021U_EQ_2021U(...) \, +#define Z_IS_2022_EQ_2022(...) \, +#define Z_IS_2022U_EQ_2022(...) \, +#define Z_IS_2022_EQ_2022U(...) \, +#define Z_IS_2022U_EQ_2022U(...) \, +#define Z_IS_2023_EQ_2023(...) \, +#define Z_IS_2023U_EQ_2023(...) \, +#define Z_IS_2023_EQ_2023U(...) \, +#define Z_IS_2023U_EQ_2023U(...) \, +#define Z_IS_2024_EQ_2024(...) \, +#define Z_IS_2024U_EQ_2024(...) \, +#define Z_IS_2024_EQ_2024U(...) \, +#define Z_IS_2024U_EQ_2024U(...) \, +#define Z_IS_2025_EQ_2025(...) \, +#define Z_IS_2025U_EQ_2025(...) \, +#define Z_IS_2025_EQ_2025U(...) \, +#define Z_IS_2025U_EQ_2025U(...) \, +#define Z_IS_2026_EQ_2026(...) \, +#define Z_IS_2026U_EQ_2026(...) \, +#define Z_IS_2026_EQ_2026U(...) \, +#define Z_IS_2026U_EQ_2026U(...) \, +#define Z_IS_2027_EQ_2027(...) \, +#define Z_IS_2027U_EQ_2027(...) \, +#define Z_IS_2027_EQ_2027U(...) \, +#define Z_IS_2027U_EQ_2027U(...) \, +#define Z_IS_2028_EQ_2028(...) \, +#define Z_IS_2028U_EQ_2028(...) \, +#define Z_IS_2028_EQ_2028U(...) \, +#define Z_IS_2028U_EQ_2028U(...) \, +#define Z_IS_2029_EQ_2029(...) \, +#define Z_IS_2029U_EQ_2029(...) \, +#define Z_IS_2029_EQ_2029U(...) \, +#define Z_IS_2029U_EQ_2029U(...) \, +#define Z_IS_2030_EQ_2030(...) \, +#define Z_IS_2030U_EQ_2030(...) \, +#define Z_IS_2030_EQ_2030U(...) \, +#define Z_IS_2030U_EQ_2030U(...) \, +#define Z_IS_2031_EQ_2031(...) \, +#define Z_IS_2031U_EQ_2031(...) \, +#define Z_IS_2031_EQ_2031U(...) \, +#define Z_IS_2031U_EQ_2031U(...) \, +#define Z_IS_2032_EQ_2032(...) \, +#define Z_IS_2032U_EQ_2032(...) \, +#define Z_IS_2032_EQ_2032U(...) \, +#define Z_IS_2032U_EQ_2032U(...) \, +#define Z_IS_2033_EQ_2033(...) \, +#define Z_IS_2033U_EQ_2033(...) \, +#define Z_IS_2033_EQ_2033U(...) \, +#define Z_IS_2033U_EQ_2033U(...) \, +#define Z_IS_2034_EQ_2034(...) \, +#define Z_IS_2034U_EQ_2034(...) \, +#define Z_IS_2034_EQ_2034U(...) \, +#define Z_IS_2034U_EQ_2034U(...) \, +#define Z_IS_2035_EQ_2035(...) \, +#define Z_IS_2035U_EQ_2035(...) \, +#define Z_IS_2035_EQ_2035U(...) \, +#define Z_IS_2035U_EQ_2035U(...) \, +#define Z_IS_2036_EQ_2036(...) \, +#define Z_IS_2036U_EQ_2036(...) \, +#define Z_IS_2036_EQ_2036U(...) \, +#define Z_IS_2036U_EQ_2036U(...) \, +#define Z_IS_2037_EQ_2037(...) \, +#define Z_IS_2037U_EQ_2037(...) \, +#define Z_IS_2037_EQ_2037U(...) \, +#define Z_IS_2037U_EQ_2037U(...) \, +#define Z_IS_2038_EQ_2038(...) \, +#define Z_IS_2038U_EQ_2038(...) \, +#define Z_IS_2038_EQ_2038U(...) \, +#define Z_IS_2038U_EQ_2038U(...) \, +#define Z_IS_2039_EQ_2039(...) \, +#define Z_IS_2039U_EQ_2039(...) \, +#define Z_IS_2039_EQ_2039U(...) \, +#define Z_IS_2039U_EQ_2039U(...) \, +#define Z_IS_2040_EQ_2040(...) \, +#define Z_IS_2040U_EQ_2040(...) \, +#define Z_IS_2040_EQ_2040U(...) \, +#define Z_IS_2040U_EQ_2040U(...) \, +#define Z_IS_2041_EQ_2041(...) \, +#define Z_IS_2041U_EQ_2041(...) \, +#define Z_IS_2041_EQ_2041U(...) \, +#define Z_IS_2041U_EQ_2041U(...) \, +#define Z_IS_2042_EQ_2042(...) \, +#define Z_IS_2042U_EQ_2042(...) \, +#define Z_IS_2042_EQ_2042U(...) \, +#define Z_IS_2042U_EQ_2042U(...) \, +#define Z_IS_2043_EQ_2043(...) \, +#define Z_IS_2043U_EQ_2043(...) \, +#define Z_IS_2043_EQ_2043U(...) \, +#define Z_IS_2043U_EQ_2043U(...) \, +#define Z_IS_2044_EQ_2044(...) \, +#define Z_IS_2044U_EQ_2044(...) \, +#define Z_IS_2044_EQ_2044U(...) \, +#define Z_IS_2044U_EQ_2044U(...) \, +#define Z_IS_2045_EQ_2045(...) \, +#define Z_IS_2045U_EQ_2045(...) \, +#define Z_IS_2045_EQ_2045U(...) \, +#define Z_IS_2045U_EQ_2045U(...) \, +#define Z_IS_2046_EQ_2046(...) \, +#define Z_IS_2046U_EQ_2046(...) \, +#define Z_IS_2046_EQ_2046U(...) \, +#define Z_IS_2046U_EQ_2046U(...) \, +#define Z_IS_2047_EQ_2047(...) \, +#define Z_IS_2047U_EQ_2047(...) \, +#define Z_IS_2047_EQ_2047U(...) \, +#define Z_IS_2047U_EQ_2047U(...) \, +#define Z_IS_2048_EQ_2048(...) \, +#define Z_IS_2048U_EQ_2048(...) \, +#define Z_IS_2048_EQ_2048U(...) \, +#define Z_IS_2048U_EQ_2048U(...) \, +#define Z_IS_2049_EQ_2049(...) \, +#define Z_IS_2049U_EQ_2049(...) \, +#define Z_IS_2049_EQ_2049U(...) \, +#define Z_IS_2049U_EQ_2049U(...) \, +#define Z_IS_2050_EQ_2050(...) \, +#define Z_IS_2050U_EQ_2050(...) \, +#define Z_IS_2050_EQ_2050U(...) \, +#define Z_IS_2050U_EQ_2050U(...) \, +#define Z_IS_2051_EQ_2051(...) \, +#define Z_IS_2051U_EQ_2051(...) \, +#define Z_IS_2051_EQ_2051U(...) \, +#define Z_IS_2051U_EQ_2051U(...) \, +#define Z_IS_2052_EQ_2052(...) \, +#define Z_IS_2052U_EQ_2052(...) \, +#define Z_IS_2052_EQ_2052U(...) \, +#define Z_IS_2052U_EQ_2052U(...) \, +#define Z_IS_2053_EQ_2053(...) \, +#define Z_IS_2053U_EQ_2053(...) \, +#define Z_IS_2053_EQ_2053U(...) \, +#define Z_IS_2053U_EQ_2053U(...) \, +#define Z_IS_2054_EQ_2054(...) \, +#define Z_IS_2054U_EQ_2054(...) \, +#define Z_IS_2054_EQ_2054U(...) \, +#define Z_IS_2054U_EQ_2054U(...) \, +#define Z_IS_2055_EQ_2055(...) \, +#define Z_IS_2055U_EQ_2055(...) \, +#define Z_IS_2055_EQ_2055U(...) \, +#define Z_IS_2055U_EQ_2055U(...) \, +#define Z_IS_2056_EQ_2056(...) \, +#define Z_IS_2056U_EQ_2056(...) \, +#define Z_IS_2056_EQ_2056U(...) \, +#define Z_IS_2056U_EQ_2056U(...) \, +#define Z_IS_2057_EQ_2057(...) \, +#define Z_IS_2057U_EQ_2057(...) \, +#define Z_IS_2057_EQ_2057U(...) \, +#define Z_IS_2057U_EQ_2057U(...) \, +#define Z_IS_2058_EQ_2058(...) \, +#define Z_IS_2058U_EQ_2058(...) \, +#define Z_IS_2058_EQ_2058U(...) \, +#define Z_IS_2058U_EQ_2058U(...) \, +#define Z_IS_2059_EQ_2059(...) \, +#define Z_IS_2059U_EQ_2059(...) \, +#define Z_IS_2059_EQ_2059U(...) \, +#define Z_IS_2059U_EQ_2059U(...) \, +#define Z_IS_2060_EQ_2060(...) \, +#define Z_IS_2060U_EQ_2060(...) \, +#define Z_IS_2060_EQ_2060U(...) \, +#define Z_IS_2060U_EQ_2060U(...) \, +#define Z_IS_2061_EQ_2061(...) \, +#define Z_IS_2061U_EQ_2061(...) \, +#define Z_IS_2061_EQ_2061U(...) \, +#define Z_IS_2061U_EQ_2061U(...) \, +#define Z_IS_2062_EQ_2062(...) \, +#define Z_IS_2062U_EQ_2062(...) \, +#define Z_IS_2062_EQ_2062U(...) \, +#define Z_IS_2062U_EQ_2062U(...) \, +#define Z_IS_2063_EQ_2063(...) \, +#define Z_IS_2063U_EQ_2063(...) \, +#define Z_IS_2063_EQ_2063U(...) \, +#define Z_IS_2063U_EQ_2063U(...) \, +#define Z_IS_2064_EQ_2064(...) \, +#define Z_IS_2064U_EQ_2064(...) \, +#define Z_IS_2064_EQ_2064U(...) \, +#define Z_IS_2064U_EQ_2064U(...) \, +#define Z_IS_2065_EQ_2065(...) \, +#define Z_IS_2065U_EQ_2065(...) \, +#define Z_IS_2065_EQ_2065U(...) \, +#define Z_IS_2065U_EQ_2065U(...) \, +#define Z_IS_2066_EQ_2066(...) \, +#define Z_IS_2066U_EQ_2066(...) \, +#define Z_IS_2066_EQ_2066U(...) \, +#define Z_IS_2066U_EQ_2066U(...) \, +#define Z_IS_2067_EQ_2067(...) \, +#define Z_IS_2067U_EQ_2067(...) \, +#define Z_IS_2067_EQ_2067U(...) \, +#define Z_IS_2067U_EQ_2067U(...) \, +#define Z_IS_2068_EQ_2068(...) \, +#define Z_IS_2068U_EQ_2068(...) \, +#define Z_IS_2068_EQ_2068U(...) \, +#define Z_IS_2068U_EQ_2068U(...) \, +#define Z_IS_2069_EQ_2069(...) \, +#define Z_IS_2069U_EQ_2069(...) \, +#define Z_IS_2069_EQ_2069U(...) \, +#define Z_IS_2069U_EQ_2069U(...) \, +#define Z_IS_2070_EQ_2070(...) \, +#define Z_IS_2070U_EQ_2070(...) \, +#define Z_IS_2070_EQ_2070U(...) \, +#define Z_IS_2070U_EQ_2070U(...) \, +#define Z_IS_2071_EQ_2071(...) \, +#define Z_IS_2071U_EQ_2071(...) \, +#define Z_IS_2071_EQ_2071U(...) \, +#define Z_IS_2071U_EQ_2071U(...) \, +#define Z_IS_2072_EQ_2072(...) \, +#define Z_IS_2072U_EQ_2072(...) \, +#define Z_IS_2072_EQ_2072U(...) \, +#define Z_IS_2072U_EQ_2072U(...) \, +#define Z_IS_2073_EQ_2073(...) \, +#define Z_IS_2073U_EQ_2073(...) \, +#define Z_IS_2073_EQ_2073U(...) \, +#define Z_IS_2073U_EQ_2073U(...) \, +#define Z_IS_2074_EQ_2074(...) \, +#define Z_IS_2074U_EQ_2074(...) \, +#define Z_IS_2074_EQ_2074U(...) \, +#define Z_IS_2074U_EQ_2074U(...) \, +#define Z_IS_2075_EQ_2075(...) \, +#define Z_IS_2075U_EQ_2075(...) \, +#define Z_IS_2075_EQ_2075U(...) \, +#define Z_IS_2075U_EQ_2075U(...) \, +#define Z_IS_2076_EQ_2076(...) \, +#define Z_IS_2076U_EQ_2076(...) \, +#define Z_IS_2076_EQ_2076U(...) \, +#define Z_IS_2076U_EQ_2076U(...) \, +#define Z_IS_2077_EQ_2077(...) \, +#define Z_IS_2077U_EQ_2077(...) \, +#define Z_IS_2077_EQ_2077U(...) \, +#define Z_IS_2077U_EQ_2077U(...) \, +#define Z_IS_2078_EQ_2078(...) \, +#define Z_IS_2078U_EQ_2078(...) \, +#define Z_IS_2078_EQ_2078U(...) \, +#define Z_IS_2078U_EQ_2078U(...) \, +#define Z_IS_2079_EQ_2079(...) \, +#define Z_IS_2079U_EQ_2079(...) \, +#define Z_IS_2079_EQ_2079U(...) \, +#define Z_IS_2079U_EQ_2079U(...) \, +#define Z_IS_2080_EQ_2080(...) \, +#define Z_IS_2080U_EQ_2080(...) \, +#define Z_IS_2080_EQ_2080U(...) \, +#define Z_IS_2080U_EQ_2080U(...) \, +#define Z_IS_2081_EQ_2081(...) \, +#define Z_IS_2081U_EQ_2081(...) \, +#define Z_IS_2081_EQ_2081U(...) \, +#define Z_IS_2081U_EQ_2081U(...) \, +#define Z_IS_2082_EQ_2082(...) \, +#define Z_IS_2082U_EQ_2082(...) \, +#define Z_IS_2082_EQ_2082U(...) \, +#define Z_IS_2082U_EQ_2082U(...) \, +#define Z_IS_2083_EQ_2083(...) \, +#define Z_IS_2083U_EQ_2083(...) \, +#define Z_IS_2083_EQ_2083U(...) \, +#define Z_IS_2083U_EQ_2083U(...) \, +#define Z_IS_2084_EQ_2084(...) \, +#define Z_IS_2084U_EQ_2084(...) \, +#define Z_IS_2084_EQ_2084U(...) \, +#define Z_IS_2084U_EQ_2084U(...) \, +#define Z_IS_2085_EQ_2085(...) \, +#define Z_IS_2085U_EQ_2085(...) \, +#define Z_IS_2085_EQ_2085U(...) \, +#define Z_IS_2085U_EQ_2085U(...) \, +#define Z_IS_2086_EQ_2086(...) \, +#define Z_IS_2086U_EQ_2086(...) \, +#define Z_IS_2086_EQ_2086U(...) \, +#define Z_IS_2086U_EQ_2086U(...) \, +#define Z_IS_2087_EQ_2087(...) \, +#define Z_IS_2087U_EQ_2087(...) \, +#define Z_IS_2087_EQ_2087U(...) \, +#define Z_IS_2087U_EQ_2087U(...) \, +#define Z_IS_2088_EQ_2088(...) \, +#define Z_IS_2088U_EQ_2088(...) \, +#define Z_IS_2088_EQ_2088U(...) \, +#define Z_IS_2088U_EQ_2088U(...) \, +#define Z_IS_2089_EQ_2089(...) \, +#define Z_IS_2089U_EQ_2089(...) \, +#define Z_IS_2089_EQ_2089U(...) \, +#define Z_IS_2089U_EQ_2089U(...) \, +#define Z_IS_2090_EQ_2090(...) \, +#define Z_IS_2090U_EQ_2090(...) \, +#define Z_IS_2090_EQ_2090U(...) \, +#define Z_IS_2090U_EQ_2090U(...) \, +#define Z_IS_2091_EQ_2091(...) \, +#define Z_IS_2091U_EQ_2091(...) \, +#define Z_IS_2091_EQ_2091U(...) \, +#define Z_IS_2091U_EQ_2091U(...) \, +#define Z_IS_2092_EQ_2092(...) \, +#define Z_IS_2092U_EQ_2092(...) \, +#define Z_IS_2092_EQ_2092U(...) \, +#define Z_IS_2092U_EQ_2092U(...) \, +#define Z_IS_2093_EQ_2093(...) \, +#define Z_IS_2093U_EQ_2093(...) \, +#define Z_IS_2093_EQ_2093U(...) \, +#define Z_IS_2093U_EQ_2093U(...) \, +#define Z_IS_2094_EQ_2094(...) \, +#define Z_IS_2094U_EQ_2094(...) \, +#define Z_IS_2094_EQ_2094U(...) \, +#define Z_IS_2094U_EQ_2094U(...) \, +#define Z_IS_2095_EQ_2095(...) \, +#define Z_IS_2095U_EQ_2095(...) \, +#define Z_IS_2095_EQ_2095U(...) \, +#define Z_IS_2095U_EQ_2095U(...) \, +#define Z_IS_2096_EQ_2096(...) \, +#define Z_IS_2096U_EQ_2096(...) \, +#define Z_IS_2096_EQ_2096U(...) \, +#define Z_IS_2096U_EQ_2096U(...) \, +#define Z_IS_2097_EQ_2097(...) \, +#define Z_IS_2097U_EQ_2097(...) \, +#define Z_IS_2097_EQ_2097U(...) \, +#define Z_IS_2097U_EQ_2097U(...) \, +#define Z_IS_2098_EQ_2098(...) \, +#define Z_IS_2098U_EQ_2098(...) \, +#define Z_IS_2098_EQ_2098U(...) \, +#define Z_IS_2098U_EQ_2098U(...) \, +#define Z_IS_2099_EQ_2099(...) \, +#define Z_IS_2099U_EQ_2099(...) \, +#define Z_IS_2099_EQ_2099U(...) \, +#define Z_IS_2099U_EQ_2099U(...) \, +#define Z_IS_2100_EQ_2100(...) \, +#define Z_IS_2100U_EQ_2100(...) \, +#define Z_IS_2100_EQ_2100U(...) \, +#define Z_IS_2100U_EQ_2100U(...) \, +#define Z_IS_2101_EQ_2101(...) \, +#define Z_IS_2101U_EQ_2101(...) \, +#define Z_IS_2101_EQ_2101U(...) \, +#define Z_IS_2101U_EQ_2101U(...) \, +#define Z_IS_2102_EQ_2102(...) \, +#define Z_IS_2102U_EQ_2102(...) \, +#define Z_IS_2102_EQ_2102U(...) \, +#define Z_IS_2102U_EQ_2102U(...) \, +#define Z_IS_2103_EQ_2103(...) \, +#define Z_IS_2103U_EQ_2103(...) \, +#define Z_IS_2103_EQ_2103U(...) \, +#define Z_IS_2103U_EQ_2103U(...) \, +#define Z_IS_2104_EQ_2104(...) \, +#define Z_IS_2104U_EQ_2104(...) \, +#define Z_IS_2104_EQ_2104U(...) \, +#define Z_IS_2104U_EQ_2104U(...) \, +#define Z_IS_2105_EQ_2105(...) \, +#define Z_IS_2105U_EQ_2105(...) \, +#define Z_IS_2105_EQ_2105U(...) \, +#define Z_IS_2105U_EQ_2105U(...) \, +#define Z_IS_2106_EQ_2106(...) \, +#define Z_IS_2106U_EQ_2106(...) \, +#define Z_IS_2106_EQ_2106U(...) \, +#define Z_IS_2106U_EQ_2106U(...) \, +#define Z_IS_2107_EQ_2107(...) \, +#define Z_IS_2107U_EQ_2107(...) \, +#define Z_IS_2107_EQ_2107U(...) \, +#define Z_IS_2107U_EQ_2107U(...) \, +#define Z_IS_2108_EQ_2108(...) \, +#define Z_IS_2108U_EQ_2108(...) \, +#define Z_IS_2108_EQ_2108U(...) \, +#define Z_IS_2108U_EQ_2108U(...) \, +#define Z_IS_2109_EQ_2109(...) \, +#define Z_IS_2109U_EQ_2109(...) \, +#define Z_IS_2109_EQ_2109U(...) \, +#define Z_IS_2109U_EQ_2109U(...) \, +#define Z_IS_2110_EQ_2110(...) \, +#define Z_IS_2110U_EQ_2110(...) \, +#define Z_IS_2110_EQ_2110U(...) \, +#define Z_IS_2110U_EQ_2110U(...) \, +#define Z_IS_2111_EQ_2111(...) \, +#define Z_IS_2111U_EQ_2111(...) \, +#define Z_IS_2111_EQ_2111U(...) \, +#define Z_IS_2111U_EQ_2111U(...) \, +#define Z_IS_2112_EQ_2112(...) \, +#define Z_IS_2112U_EQ_2112(...) \, +#define Z_IS_2112_EQ_2112U(...) \, +#define Z_IS_2112U_EQ_2112U(...) \, +#define Z_IS_2113_EQ_2113(...) \, +#define Z_IS_2113U_EQ_2113(...) \, +#define Z_IS_2113_EQ_2113U(...) \, +#define Z_IS_2113U_EQ_2113U(...) \, +#define Z_IS_2114_EQ_2114(...) \, +#define Z_IS_2114U_EQ_2114(...) \, +#define Z_IS_2114_EQ_2114U(...) \, +#define Z_IS_2114U_EQ_2114U(...) \, +#define Z_IS_2115_EQ_2115(...) \, +#define Z_IS_2115U_EQ_2115(...) \, +#define Z_IS_2115_EQ_2115U(...) \, +#define Z_IS_2115U_EQ_2115U(...) \, +#define Z_IS_2116_EQ_2116(...) \, +#define Z_IS_2116U_EQ_2116(...) \, +#define Z_IS_2116_EQ_2116U(...) \, +#define Z_IS_2116U_EQ_2116U(...) \, +#define Z_IS_2117_EQ_2117(...) \, +#define Z_IS_2117U_EQ_2117(...) \, +#define Z_IS_2117_EQ_2117U(...) \, +#define Z_IS_2117U_EQ_2117U(...) \, +#define Z_IS_2118_EQ_2118(...) \, +#define Z_IS_2118U_EQ_2118(...) \, +#define Z_IS_2118_EQ_2118U(...) \, +#define Z_IS_2118U_EQ_2118U(...) \, +#define Z_IS_2119_EQ_2119(...) \, +#define Z_IS_2119U_EQ_2119(...) \, +#define Z_IS_2119_EQ_2119U(...) \, +#define Z_IS_2119U_EQ_2119U(...) \, +#define Z_IS_2120_EQ_2120(...) \, +#define Z_IS_2120U_EQ_2120(...) \, +#define Z_IS_2120_EQ_2120U(...) \, +#define Z_IS_2120U_EQ_2120U(...) \, +#define Z_IS_2121_EQ_2121(...) \, +#define Z_IS_2121U_EQ_2121(...) \, +#define Z_IS_2121_EQ_2121U(...) \, +#define Z_IS_2121U_EQ_2121U(...) \, +#define Z_IS_2122_EQ_2122(...) \, +#define Z_IS_2122U_EQ_2122(...) \, +#define Z_IS_2122_EQ_2122U(...) \, +#define Z_IS_2122U_EQ_2122U(...) \, +#define Z_IS_2123_EQ_2123(...) \, +#define Z_IS_2123U_EQ_2123(...) \, +#define Z_IS_2123_EQ_2123U(...) \, +#define Z_IS_2123U_EQ_2123U(...) \, +#define Z_IS_2124_EQ_2124(...) \, +#define Z_IS_2124U_EQ_2124(...) \, +#define Z_IS_2124_EQ_2124U(...) \, +#define Z_IS_2124U_EQ_2124U(...) \, +#define Z_IS_2125_EQ_2125(...) \, +#define Z_IS_2125U_EQ_2125(...) \, +#define Z_IS_2125_EQ_2125U(...) \, +#define Z_IS_2125U_EQ_2125U(...) \, +#define Z_IS_2126_EQ_2126(...) \, +#define Z_IS_2126U_EQ_2126(...) \, +#define Z_IS_2126_EQ_2126U(...) \, +#define Z_IS_2126U_EQ_2126U(...) \, +#define Z_IS_2127_EQ_2127(...) \, +#define Z_IS_2127U_EQ_2127(...) \, +#define Z_IS_2127_EQ_2127U(...) \, +#define Z_IS_2127U_EQ_2127U(...) \, +#define Z_IS_2128_EQ_2128(...) \, +#define Z_IS_2128U_EQ_2128(...) \, +#define Z_IS_2128_EQ_2128U(...) \, +#define Z_IS_2128U_EQ_2128U(...) \, +#define Z_IS_2129_EQ_2129(...) \, +#define Z_IS_2129U_EQ_2129(...) \, +#define Z_IS_2129_EQ_2129U(...) \, +#define Z_IS_2129U_EQ_2129U(...) \, +#define Z_IS_2130_EQ_2130(...) \, +#define Z_IS_2130U_EQ_2130(...) \, +#define Z_IS_2130_EQ_2130U(...) \, +#define Z_IS_2130U_EQ_2130U(...) \, +#define Z_IS_2131_EQ_2131(...) \, +#define Z_IS_2131U_EQ_2131(...) \, +#define Z_IS_2131_EQ_2131U(...) \, +#define Z_IS_2131U_EQ_2131U(...) \, +#define Z_IS_2132_EQ_2132(...) \, +#define Z_IS_2132U_EQ_2132(...) \, +#define Z_IS_2132_EQ_2132U(...) \, +#define Z_IS_2132U_EQ_2132U(...) \, +#define Z_IS_2133_EQ_2133(...) \, +#define Z_IS_2133U_EQ_2133(...) \, +#define Z_IS_2133_EQ_2133U(...) \, +#define Z_IS_2133U_EQ_2133U(...) \, +#define Z_IS_2134_EQ_2134(...) \, +#define Z_IS_2134U_EQ_2134(...) \, +#define Z_IS_2134_EQ_2134U(...) \, +#define Z_IS_2134U_EQ_2134U(...) \, +#define Z_IS_2135_EQ_2135(...) \, +#define Z_IS_2135U_EQ_2135(...) \, +#define Z_IS_2135_EQ_2135U(...) \, +#define Z_IS_2135U_EQ_2135U(...) \, +#define Z_IS_2136_EQ_2136(...) \, +#define Z_IS_2136U_EQ_2136(...) \, +#define Z_IS_2136_EQ_2136U(...) \, +#define Z_IS_2136U_EQ_2136U(...) \, +#define Z_IS_2137_EQ_2137(...) \, +#define Z_IS_2137U_EQ_2137(...) \, +#define Z_IS_2137_EQ_2137U(...) \, +#define Z_IS_2137U_EQ_2137U(...) \, +#define Z_IS_2138_EQ_2138(...) \, +#define Z_IS_2138U_EQ_2138(...) \, +#define Z_IS_2138_EQ_2138U(...) \, +#define Z_IS_2138U_EQ_2138U(...) \, +#define Z_IS_2139_EQ_2139(...) \, +#define Z_IS_2139U_EQ_2139(...) \, +#define Z_IS_2139_EQ_2139U(...) \, +#define Z_IS_2139U_EQ_2139U(...) \, +#define Z_IS_2140_EQ_2140(...) \, +#define Z_IS_2140U_EQ_2140(...) \, +#define Z_IS_2140_EQ_2140U(...) \, +#define Z_IS_2140U_EQ_2140U(...) \, +#define Z_IS_2141_EQ_2141(...) \, +#define Z_IS_2141U_EQ_2141(...) \, +#define Z_IS_2141_EQ_2141U(...) \, +#define Z_IS_2141U_EQ_2141U(...) \, +#define Z_IS_2142_EQ_2142(...) \, +#define Z_IS_2142U_EQ_2142(...) \, +#define Z_IS_2142_EQ_2142U(...) \, +#define Z_IS_2142U_EQ_2142U(...) \, +#define Z_IS_2143_EQ_2143(...) \, +#define Z_IS_2143U_EQ_2143(...) \, +#define Z_IS_2143_EQ_2143U(...) \, +#define Z_IS_2143U_EQ_2143U(...) \, +#define Z_IS_2144_EQ_2144(...) \, +#define Z_IS_2144U_EQ_2144(...) \, +#define Z_IS_2144_EQ_2144U(...) \, +#define Z_IS_2144U_EQ_2144U(...) \, +#define Z_IS_2145_EQ_2145(...) \, +#define Z_IS_2145U_EQ_2145(...) \, +#define Z_IS_2145_EQ_2145U(...) \, +#define Z_IS_2145U_EQ_2145U(...) \, +#define Z_IS_2146_EQ_2146(...) \, +#define Z_IS_2146U_EQ_2146(...) \, +#define Z_IS_2146_EQ_2146U(...) \, +#define Z_IS_2146U_EQ_2146U(...) \, +#define Z_IS_2147_EQ_2147(...) \, +#define Z_IS_2147U_EQ_2147(...) \, +#define Z_IS_2147_EQ_2147U(...) \, +#define Z_IS_2147U_EQ_2147U(...) \, +#define Z_IS_2148_EQ_2148(...) \, +#define Z_IS_2148U_EQ_2148(...) \, +#define Z_IS_2148_EQ_2148U(...) \, +#define Z_IS_2148U_EQ_2148U(...) \, +#define Z_IS_2149_EQ_2149(...) \, +#define Z_IS_2149U_EQ_2149(...) \, +#define Z_IS_2149_EQ_2149U(...) \, +#define Z_IS_2149U_EQ_2149U(...) \, +#define Z_IS_2150_EQ_2150(...) \, +#define Z_IS_2150U_EQ_2150(...) \, +#define Z_IS_2150_EQ_2150U(...) \, +#define Z_IS_2150U_EQ_2150U(...) \, +#define Z_IS_2151_EQ_2151(...) \, +#define Z_IS_2151U_EQ_2151(...) \, +#define Z_IS_2151_EQ_2151U(...) \, +#define Z_IS_2151U_EQ_2151U(...) \, +#define Z_IS_2152_EQ_2152(...) \, +#define Z_IS_2152U_EQ_2152(...) \, +#define Z_IS_2152_EQ_2152U(...) \, +#define Z_IS_2152U_EQ_2152U(...) \, +#define Z_IS_2153_EQ_2153(...) \, +#define Z_IS_2153U_EQ_2153(...) \, +#define Z_IS_2153_EQ_2153U(...) \, +#define Z_IS_2153U_EQ_2153U(...) \, +#define Z_IS_2154_EQ_2154(...) \, +#define Z_IS_2154U_EQ_2154(...) \, +#define Z_IS_2154_EQ_2154U(...) \, +#define Z_IS_2154U_EQ_2154U(...) \, +#define Z_IS_2155_EQ_2155(...) \, +#define Z_IS_2155U_EQ_2155(...) \, +#define Z_IS_2155_EQ_2155U(...) \, +#define Z_IS_2155U_EQ_2155U(...) \, +#define Z_IS_2156_EQ_2156(...) \, +#define Z_IS_2156U_EQ_2156(...) \, +#define Z_IS_2156_EQ_2156U(...) \, +#define Z_IS_2156U_EQ_2156U(...) \, +#define Z_IS_2157_EQ_2157(...) \, +#define Z_IS_2157U_EQ_2157(...) \, +#define Z_IS_2157_EQ_2157U(...) \, +#define Z_IS_2157U_EQ_2157U(...) \, +#define Z_IS_2158_EQ_2158(...) \, +#define Z_IS_2158U_EQ_2158(...) \, +#define Z_IS_2158_EQ_2158U(...) \, +#define Z_IS_2158U_EQ_2158U(...) \, +#define Z_IS_2159_EQ_2159(...) \, +#define Z_IS_2159U_EQ_2159(...) \, +#define Z_IS_2159_EQ_2159U(...) \, +#define Z_IS_2159U_EQ_2159U(...) \, +#define Z_IS_2160_EQ_2160(...) \, +#define Z_IS_2160U_EQ_2160(...) \, +#define Z_IS_2160_EQ_2160U(...) \, +#define Z_IS_2160U_EQ_2160U(...) \, +#define Z_IS_2161_EQ_2161(...) \, +#define Z_IS_2161U_EQ_2161(...) \, +#define Z_IS_2161_EQ_2161U(...) \, +#define Z_IS_2161U_EQ_2161U(...) \, +#define Z_IS_2162_EQ_2162(...) \, +#define Z_IS_2162U_EQ_2162(...) \, +#define Z_IS_2162_EQ_2162U(...) \, +#define Z_IS_2162U_EQ_2162U(...) \, +#define Z_IS_2163_EQ_2163(...) \, +#define Z_IS_2163U_EQ_2163(...) \, +#define Z_IS_2163_EQ_2163U(...) \, +#define Z_IS_2163U_EQ_2163U(...) \, +#define Z_IS_2164_EQ_2164(...) \, +#define Z_IS_2164U_EQ_2164(...) \, +#define Z_IS_2164_EQ_2164U(...) \, +#define Z_IS_2164U_EQ_2164U(...) \, +#define Z_IS_2165_EQ_2165(...) \, +#define Z_IS_2165U_EQ_2165(...) \, +#define Z_IS_2165_EQ_2165U(...) \, +#define Z_IS_2165U_EQ_2165U(...) \, +#define Z_IS_2166_EQ_2166(...) \, +#define Z_IS_2166U_EQ_2166(...) \, +#define Z_IS_2166_EQ_2166U(...) \, +#define Z_IS_2166U_EQ_2166U(...) \, +#define Z_IS_2167_EQ_2167(...) \, +#define Z_IS_2167U_EQ_2167(...) \, +#define Z_IS_2167_EQ_2167U(...) \, +#define Z_IS_2167U_EQ_2167U(...) \, +#define Z_IS_2168_EQ_2168(...) \, +#define Z_IS_2168U_EQ_2168(...) \, +#define Z_IS_2168_EQ_2168U(...) \, +#define Z_IS_2168U_EQ_2168U(...) \, +#define Z_IS_2169_EQ_2169(...) \, +#define Z_IS_2169U_EQ_2169(...) \, +#define Z_IS_2169_EQ_2169U(...) \, +#define Z_IS_2169U_EQ_2169U(...) \, +#define Z_IS_2170_EQ_2170(...) \, +#define Z_IS_2170U_EQ_2170(...) \, +#define Z_IS_2170_EQ_2170U(...) \, +#define Z_IS_2170U_EQ_2170U(...) \, +#define Z_IS_2171_EQ_2171(...) \, +#define Z_IS_2171U_EQ_2171(...) \, +#define Z_IS_2171_EQ_2171U(...) \, +#define Z_IS_2171U_EQ_2171U(...) \, +#define Z_IS_2172_EQ_2172(...) \, +#define Z_IS_2172U_EQ_2172(...) \, +#define Z_IS_2172_EQ_2172U(...) \, +#define Z_IS_2172U_EQ_2172U(...) \, +#define Z_IS_2173_EQ_2173(...) \, +#define Z_IS_2173U_EQ_2173(...) \, +#define Z_IS_2173_EQ_2173U(...) \, +#define Z_IS_2173U_EQ_2173U(...) \, +#define Z_IS_2174_EQ_2174(...) \, +#define Z_IS_2174U_EQ_2174(...) \, +#define Z_IS_2174_EQ_2174U(...) \, +#define Z_IS_2174U_EQ_2174U(...) \, +#define Z_IS_2175_EQ_2175(...) \, +#define Z_IS_2175U_EQ_2175(...) \, +#define Z_IS_2175_EQ_2175U(...) \, +#define Z_IS_2175U_EQ_2175U(...) \, +#define Z_IS_2176_EQ_2176(...) \, +#define Z_IS_2176U_EQ_2176(...) \, +#define Z_IS_2176_EQ_2176U(...) \, +#define Z_IS_2176U_EQ_2176U(...) \, +#define Z_IS_2177_EQ_2177(...) \, +#define Z_IS_2177U_EQ_2177(...) \, +#define Z_IS_2177_EQ_2177U(...) \, +#define Z_IS_2177U_EQ_2177U(...) \, +#define Z_IS_2178_EQ_2178(...) \, +#define Z_IS_2178U_EQ_2178(...) \, +#define Z_IS_2178_EQ_2178U(...) \, +#define Z_IS_2178U_EQ_2178U(...) \, +#define Z_IS_2179_EQ_2179(...) \, +#define Z_IS_2179U_EQ_2179(...) \, +#define Z_IS_2179_EQ_2179U(...) \, +#define Z_IS_2179U_EQ_2179U(...) \, +#define Z_IS_2180_EQ_2180(...) \, +#define Z_IS_2180U_EQ_2180(...) \, +#define Z_IS_2180_EQ_2180U(...) \, +#define Z_IS_2180U_EQ_2180U(...) \, +#define Z_IS_2181_EQ_2181(...) \, +#define Z_IS_2181U_EQ_2181(...) \, +#define Z_IS_2181_EQ_2181U(...) \, +#define Z_IS_2181U_EQ_2181U(...) \, +#define Z_IS_2182_EQ_2182(...) \, +#define Z_IS_2182U_EQ_2182(...) \, +#define Z_IS_2182_EQ_2182U(...) \, +#define Z_IS_2182U_EQ_2182U(...) \, +#define Z_IS_2183_EQ_2183(...) \, +#define Z_IS_2183U_EQ_2183(...) \, +#define Z_IS_2183_EQ_2183U(...) \, +#define Z_IS_2183U_EQ_2183U(...) \, +#define Z_IS_2184_EQ_2184(...) \, +#define Z_IS_2184U_EQ_2184(...) \, +#define Z_IS_2184_EQ_2184U(...) \, +#define Z_IS_2184U_EQ_2184U(...) \, +#define Z_IS_2185_EQ_2185(...) \, +#define Z_IS_2185U_EQ_2185(...) \, +#define Z_IS_2185_EQ_2185U(...) \, +#define Z_IS_2185U_EQ_2185U(...) \, +#define Z_IS_2186_EQ_2186(...) \, +#define Z_IS_2186U_EQ_2186(...) \, +#define Z_IS_2186_EQ_2186U(...) \, +#define Z_IS_2186U_EQ_2186U(...) \, +#define Z_IS_2187_EQ_2187(...) \, +#define Z_IS_2187U_EQ_2187(...) \, +#define Z_IS_2187_EQ_2187U(...) \, +#define Z_IS_2187U_EQ_2187U(...) \, +#define Z_IS_2188_EQ_2188(...) \, +#define Z_IS_2188U_EQ_2188(...) \, +#define Z_IS_2188_EQ_2188U(...) \, +#define Z_IS_2188U_EQ_2188U(...) \, +#define Z_IS_2189_EQ_2189(...) \, +#define Z_IS_2189U_EQ_2189(...) \, +#define Z_IS_2189_EQ_2189U(...) \, +#define Z_IS_2189U_EQ_2189U(...) \, +#define Z_IS_2190_EQ_2190(...) \, +#define Z_IS_2190U_EQ_2190(...) \, +#define Z_IS_2190_EQ_2190U(...) \, +#define Z_IS_2190U_EQ_2190U(...) \, +#define Z_IS_2191_EQ_2191(...) \, +#define Z_IS_2191U_EQ_2191(...) \, +#define Z_IS_2191_EQ_2191U(...) \, +#define Z_IS_2191U_EQ_2191U(...) \, +#define Z_IS_2192_EQ_2192(...) \, +#define Z_IS_2192U_EQ_2192(...) \, +#define Z_IS_2192_EQ_2192U(...) \, +#define Z_IS_2192U_EQ_2192U(...) \, +#define Z_IS_2193_EQ_2193(...) \, +#define Z_IS_2193U_EQ_2193(...) \, +#define Z_IS_2193_EQ_2193U(...) \, +#define Z_IS_2193U_EQ_2193U(...) \, +#define Z_IS_2194_EQ_2194(...) \, +#define Z_IS_2194U_EQ_2194(...) \, +#define Z_IS_2194_EQ_2194U(...) \, +#define Z_IS_2194U_EQ_2194U(...) \, +#define Z_IS_2195_EQ_2195(...) \, +#define Z_IS_2195U_EQ_2195(...) \, +#define Z_IS_2195_EQ_2195U(...) \, +#define Z_IS_2195U_EQ_2195U(...) \, +#define Z_IS_2196_EQ_2196(...) \, +#define Z_IS_2196U_EQ_2196(...) \, +#define Z_IS_2196_EQ_2196U(...) \, +#define Z_IS_2196U_EQ_2196U(...) \, +#define Z_IS_2197_EQ_2197(...) \, +#define Z_IS_2197U_EQ_2197(...) \, +#define Z_IS_2197_EQ_2197U(...) \, +#define Z_IS_2197U_EQ_2197U(...) \, +#define Z_IS_2198_EQ_2198(...) \, +#define Z_IS_2198U_EQ_2198(...) \, +#define Z_IS_2198_EQ_2198U(...) \, +#define Z_IS_2198U_EQ_2198U(...) \, +#define Z_IS_2199_EQ_2199(...) \, +#define Z_IS_2199U_EQ_2199(...) \, +#define Z_IS_2199_EQ_2199U(...) \, +#define Z_IS_2199U_EQ_2199U(...) \, +#define Z_IS_2200_EQ_2200(...) \, +#define Z_IS_2200U_EQ_2200(...) \, +#define Z_IS_2200_EQ_2200U(...) \, +#define Z_IS_2200U_EQ_2200U(...) \, +#define Z_IS_2201_EQ_2201(...) \, +#define Z_IS_2201U_EQ_2201(...) \, +#define Z_IS_2201_EQ_2201U(...) \, +#define Z_IS_2201U_EQ_2201U(...) \, +#define Z_IS_2202_EQ_2202(...) \, +#define Z_IS_2202U_EQ_2202(...) \, +#define Z_IS_2202_EQ_2202U(...) \, +#define Z_IS_2202U_EQ_2202U(...) \, +#define Z_IS_2203_EQ_2203(...) \, +#define Z_IS_2203U_EQ_2203(...) \, +#define Z_IS_2203_EQ_2203U(...) \, +#define Z_IS_2203U_EQ_2203U(...) \, +#define Z_IS_2204_EQ_2204(...) \, +#define Z_IS_2204U_EQ_2204(...) \, +#define Z_IS_2204_EQ_2204U(...) \, +#define Z_IS_2204U_EQ_2204U(...) \, +#define Z_IS_2205_EQ_2205(...) \, +#define Z_IS_2205U_EQ_2205(...) \, +#define Z_IS_2205_EQ_2205U(...) \, +#define Z_IS_2205U_EQ_2205U(...) \, +#define Z_IS_2206_EQ_2206(...) \, +#define Z_IS_2206U_EQ_2206(...) \, +#define Z_IS_2206_EQ_2206U(...) \, +#define Z_IS_2206U_EQ_2206U(...) \, +#define Z_IS_2207_EQ_2207(...) \, +#define Z_IS_2207U_EQ_2207(...) \, +#define Z_IS_2207_EQ_2207U(...) \, +#define Z_IS_2207U_EQ_2207U(...) \, +#define Z_IS_2208_EQ_2208(...) \, +#define Z_IS_2208U_EQ_2208(...) \, +#define Z_IS_2208_EQ_2208U(...) \, +#define Z_IS_2208U_EQ_2208U(...) \, +#define Z_IS_2209_EQ_2209(...) \, +#define Z_IS_2209U_EQ_2209(...) \, +#define Z_IS_2209_EQ_2209U(...) \, +#define Z_IS_2209U_EQ_2209U(...) \, +#define Z_IS_2210_EQ_2210(...) \, +#define Z_IS_2210U_EQ_2210(...) \, +#define Z_IS_2210_EQ_2210U(...) \, +#define Z_IS_2210U_EQ_2210U(...) \, +#define Z_IS_2211_EQ_2211(...) \, +#define Z_IS_2211U_EQ_2211(...) \, +#define Z_IS_2211_EQ_2211U(...) \, +#define Z_IS_2211U_EQ_2211U(...) \, +#define Z_IS_2212_EQ_2212(...) \, +#define Z_IS_2212U_EQ_2212(...) \, +#define Z_IS_2212_EQ_2212U(...) \, +#define Z_IS_2212U_EQ_2212U(...) \, +#define Z_IS_2213_EQ_2213(...) \, +#define Z_IS_2213U_EQ_2213(...) \, +#define Z_IS_2213_EQ_2213U(...) \, +#define Z_IS_2213U_EQ_2213U(...) \, +#define Z_IS_2214_EQ_2214(...) \, +#define Z_IS_2214U_EQ_2214(...) \, +#define Z_IS_2214_EQ_2214U(...) \, +#define Z_IS_2214U_EQ_2214U(...) \, +#define Z_IS_2215_EQ_2215(...) \, +#define Z_IS_2215U_EQ_2215(...) \, +#define Z_IS_2215_EQ_2215U(...) \, +#define Z_IS_2215U_EQ_2215U(...) \, +#define Z_IS_2216_EQ_2216(...) \, +#define Z_IS_2216U_EQ_2216(...) \, +#define Z_IS_2216_EQ_2216U(...) \, +#define Z_IS_2216U_EQ_2216U(...) \, +#define Z_IS_2217_EQ_2217(...) \, +#define Z_IS_2217U_EQ_2217(...) \, +#define Z_IS_2217_EQ_2217U(...) \, +#define Z_IS_2217U_EQ_2217U(...) \, +#define Z_IS_2218_EQ_2218(...) \, +#define Z_IS_2218U_EQ_2218(...) \, +#define Z_IS_2218_EQ_2218U(...) \, +#define Z_IS_2218U_EQ_2218U(...) \, +#define Z_IS_2219_EQ_2219(...) \, +#define Z_IS_2219U_EQ_2219(...) \, +#define Z_IS_2219_EQ_2219U(...) \, +#define Z_IS_2219U_EQ_2219U(...) \, +#define Z_IS_2220_EQ_2220(...) \, +#define Z_IS_2220U_EQ_2220(...) \, +#define Z_IS_2220_EQ_2220U(...) \, +#define Z_IS_2220U_EQ_2220U(...) \, +#define Z_IS_2221_EQ_2221(...) \, +#define Z_IS_2221U_EQ_2221(...) \, +#define Z_IS_2221_EQ_2221U(...) \, +#define Z_IS_2221U_EQ_2221U(...) \, +#define Z_IS_2222_EQ_2222(...) \, +#define Z_IS_2222U_EQ_2222(...) \, +#define Z_IS_2222_EQ_2222U(...) \, +#define Z_IS_2222U_EQ_2222U(...) \, +#define Z_IS_2223_EQ_2223(...) \, +#define Z_IS_2223U_EQ_2223(...) \, +#define Z_IS_2223_EQ_2223U(...) \, +#define Z_IS_2223U_EQ_2223U(...) \, +#define Z_IS_2224_EQ_2224(...) \, +#define Z_IS_2224U_EQ_2224(...) \, +#define Z_IS_2224_EQ_2224U(...) \, +#define Z_IS_2224U_EQ_2224U(...) \, +#define Z_IS_2225_EQ_2225(...) \, +#define Z_IS_2225U_EQ_2225(...) \, +#define Z_IS_2225_EQ_2225U(...) \, +#define Z_IS_2225U_EQ_2225U(...) \, +#define Z_IS_2226_EQ_2226(...) \, +#define Z_IS_2226U_EQ_2226(...) \, +#define Z_IS_2226_EQ_2226U(...) \, +#define Z_IS_2226U_EQ_2226U(...) \, +#define Z_IS_2227_EQ_2227(...) \, +#define Z_IS_2227U_EQ_2227(...) \, +#define Z_IS_2227_EQ_2227U(...) \, +#define Z_IS_2227U_EQ_2227U(...) \, +#define Z_IS_2228_EQ_2228(...) \, +#define Z_IS_2228U_EQ_2228(...) \, +#define Z_IS_2228_EQ_2228U(...) \, +#define Z_IS_2228U_EQ_2228U(...) \, +#define Z_IS_2229_EQ_2229(...) \, +#define Z_IS_2229U_EQ_2229(...) \, +#define Z_IS_2229_EQ_2229U(...) \, +#define Z_IS_2229U_EQ_2229U(...) \, +#define Z_IS_2230_EQ_2230(...) \, +#define Z_IS_2230U_EQ_2230(...) \, +#define Z_IS_2230_EQ_2230U(...) \, +#define Z_IS_2230U_EQ_2230U(...) \, +#define Z_IS_2231_EQ_2231(...) \, +#define Z_IS_2231U_EQ_2231(...) \, +#define Z_IS_2231_EQ_2231U(...) \, +#define Z_IS_2231U_EQ_2231U(...) \, +#define Z_IS_2232_EQ_2232(...) \, +#define Z_IS_2232U_EQ_2232(...) \, +#define Z_IS_2232_EQ_2232U(...) \, +#define Z_IS_2232U_EQ_2232U(...) \, +#define Z_IS_2233_EQ_2233(...) \, +#define Z_IS_2233U_EQ_2233(...) \, +#define Z_IS_2233_EQ_2233U(...) \, +#define Z_IS_2233U_EQ_2233U(...) \, +#define Z_IS_2234_EQ_2234(...) \, +#define Z_IS_2234U_EQ_2234(...) \, +#define Z_IS_2234_EQ_2234U(...) \, +#define Z_IS_2234U_EQ_2234U(...) \, +#define Z_IS_2235_EQ_2235(...) \, +#define Z_IS_2235U_EQ_2235(...) \, +#define Z_IS_2235_EQ_2235U(...) \, +#define Z_IS_2235U_EQ_2235U(...) \, +#define Z_IS_2236_EQ_2236(...) \, +#define Z_IS_2236U_EQ_2236(...) \, +#define Z_IS_2236_EQ_2236U(...) \, +#define Z_IS_2236U_EQ_2236U(...) \, +#define Z_IS_2237_EQ_2237(...) \, +#define Z_IS_2237U_EQ_2237(...) \, +#define Z_IS_2237_EQ_2237U(...) \, +#define Z_IS_2237U_EQ_2237U(...) \, +#define Z_IS_2238_EQ_2238(...) \, +#define Z_IS_2238U_EQ_2238(...) \, +#define Z_IS_2238_EQ_2238U(...) \, +#define Z_IS_2238U_EQ_2238U(...) \, +#define Z_IS_2239_EQ_2239(...) \, +#define Z_IS_2239U_EQ_2239(...) \, +#define Z_IS_2239_EQ_2239U(...) \, +#define Z_IS_2239U_EQ_2239U(...) \, +#define Z_IS_2240_EQ_2240(...) \, +#define Z_IS_2240U_EQ_2240(...) \, +#define Z_IS_2240_EQ_2240U(...) \, +#define Z_IS_2240U_EQ_2240U(...) \, +#define Z_IS_2241_EQ_2241(...) \, +#define Z_IS_2241U_EQ_2241(...) \, +#define Z_IS_2241_EQ_2241U(...) \, +#define Z_IS_2241U_EQ_2241U(...) \, +#define Z_IS_2242_EQ_2242(...) \, +#define Z_IS_2242U_EQ_2242(...) \, +#define Z_IS_2242_EQ_2242U(...) \, +#define Z_IS_2242U_EQ_2242U(...) \, +#define Z_IS_2243_EQ_2243(...) \, +#define Z_IS_2243U_EQ_2243(...) \, +#define Z_IS_2243_EQ_2243U(...) \, +#define Z_IS_2243U_EQ_2243U(...) \, +#define Z_IS_2244_EQ_2244(...) \, +#define Z_IS_2244U_EQ_2244(...) \, +#define Z_IS_2244_EQ_2244U(...) \, +#define Z_IS_2244U_EQ_2244U(...) \, +#define Z_IS_2245_EQ_2245(...) \, +#define Z_IS_2245U_EQ_2245(...) \, +#define Z_IS_2245_EQ_2245U(...) \, +#define Z_IS_2245U_EQ_2245U(...) \, +#define Z_IS_2246_EQ_2246(...) \, +#define Z_IS_2246U_EQ_2246(...) \, +#define Z_IS_2246_EQ_2246U(...) \, +#define Z_IS_2246U_EQ_2246U(...) \, +#define Z_IS_2247_EQ_2247(...) \, +#define Z_IS_2247U_EQ_2247(...) \, +#define Z_IS_2247_EQ_2247U(...) \, +#define Z_IS_2247U_EQ_2247U(...) \, +#define Z_IS_2248_EQ_2248(...) \, +#define Z_IS_2248U_EQ_2248(...) \, +#define Z_IS_2248_EQ_2248U(...) \, +#define Z_IS_2248U_EQ_2248U(...) \, +#define Z_IS_2249_EQ_2249(...) \, +#define Z_IS_2249U_EQ_2249(...) \, +#define Z_IS_2249_EQ_2249U(...) \, +#define Z_IS_2249U_EQ_2249U(...) \, +#define Z_IS_2250_EQ_2250(...) \, +#define Z_IS_2250U_EQ_2250(...) \, +#define Z_IS_2250_EQ_2250U(...) \, +#define Z_IS_2250U_EQ_2250U(...) \, +#define Z_IS_2251_EQ_2251(...) \, +#define Z_IS_2251U_EQ_2251(...) \, +#define Z_IS_2251_EQ_2251U(...) \, +#define Z_IS_2251U_EQ_2251U(...) \, +#define Z_IS_2252_EQ_2252(...) \, +#define Z_IS_2252U_EQ_2252(...) \, +#define Z_IS_2252_EQ_2252U(...) \, +#define Z_IS_2252U_EQ_2252U(...) \, +#define Z_IS_2253_EQ_2253(...) \, +#define Z_IS_2253U_EQ_2253(...) \, +#define Z_IS_2253_EQ_2253U(...) \, +#define Z_IS_2253U_EQ_2253U(...) \, +#define Z_IS_2254_EQ_2254(...) \, +#define Z_IS_2254U_EQ_2254(...) \, +#define Z_IS_2254_EQ_2254U(...) \, +#define Z_IS_2254U_EQ_2254U(...) \, +#define Z_IS_2255_EQ_2255(...) \, +#define Z_IS_2255U_EQ_2255(...) \, +#define Z_IS_2255_EQ_2255U(...) \, +#define Z_IS_2255U_EQ_2255U(...) \, +#define Z_IS_2256_EQ_2256(...) \, +#define Z_IS_2256U_EQ_2256(...) \, +#define Z_IS_2256_EQ_2256U(...) \, +#define Z_IS_2256U_EQ_2256U(...) \, +#define Z_IS_2257_EQ_2257(...) \, +#define Z_IS_2257U_EQ_2257(...) \, +#define Z_IS_2257_EQ_2257U(...) \, +#define Z_IS_2257U_EQ_2257U(...) \, +#define Z_IS_2258_EQ_2258(...) \, +#define Z_IS_2258U_EQ_2258(...) \, +#define Z_IS_2258_EQ_2258U(...) \, +#define Z_IS_2258U_EQ_2258U(...) \, +#define Z_IS_2259_EQ_2259(...) \, +#define Z_IS_2259U_EQ_2259(...) \, +#define Z_IS_2259_EQ_2259U(...) \, +#define Z_IS_2259U_EQ_2259U(...) \, +#define Z_IS_2260_EQ_2260(...) \, +#define Z_IS_2260U_EQ_2260(...) \, +#define Z_IS_2260_EQ_2260U(...) \, +#define Z_IS_2260U_EQ_2260U(...) \, +#define Z_IS_2261_EQ_2261(...) \, +#define Z_IS_2261U_EQ_2261(...) \, +#define Z_IS_2261_EQ_2261U(...) \, +#define Z_IS_2261U_EQ_2261U(...) \, +#define Z_IS_2262_EQ_2262(...) \, +#define Z_IS_2262U_EQ_2262(...) \, +#define Z_IS_2262_EQ_2262U(...) \, +#define Z_IS_2262U_EQ_2262U(...) \, +#define Z_IS_2263_EQ_2263(...) \, +#define Z_IS_2263U_EQ_2263(...) \, +#define Z_IS_2263_EQ_2263U(...) \, +#define Z_IS_2263U_EQ_2263U(...) \, +#define Z_IS_2264_EQ_2264(...) \, +#define Z_IS_2264U_EQ_2264(...) \, +#define Z_IS_2264_EQ_2264U(...) \, +#define Z_IS_2264U_EQ_2264U(...) \, +#define Z_IS_2265_EQ_2265(...) \, +#define Z_IS_2265U_EQ_2265(...) \, +#define Z_IS_2265_EQ_2265U(...) \, +#define Z_IS_2265U_EQ_2265U(...) \, +#define Z_IS_2266_EQ_2266(...) \, +#define Z_IS_2266U_EQ_2266(...) \, +#define Z_IS_2266_EQ_2266U(...) \, +#define Z_IS_2266U_EQ_2266U(...) \, +#define Z_IS_2267_EQ_2267(...) \, +#define Z_IS_2267U_EQ_2267(...) \, +#define Z_IS_2267_EQ_2267U(...) \, +#define Z_IS_2267U_EQ_2267U(...) \, +#define Z_IS_2268_EQ_2268(...) \, +#define Z_IS_2268U_EQ_2268(...) \, +#define Z_IS_2268_EQ_2268U(...) \, +#define Z_IS_2268U_EQ_2268U(...) \, +#define Z_IS_2269_EQ_2269(...) \, +#define Z_IS_2269U_EQ_2269(...) \, +#define Z_IS_2269_EQ_2269U(...) \, +#define Z_IS_2269U_EQ_2269U(...) \, +#define Z_IS_2270_EQ_2270(...) \, +#define Z_IS_2270U_EQ_2270(...) \, +#define Z_IS_2270_EQ_2270U(...) \, +#define Z_IS_2270U_EQ_2270U(...) \, +#define Z_IS_2271_EQ_2271(...) \, +#define Z_IS_2271U_EQ_2271(...) \, +#define Z_IS_2271_EQ_2271U(...) \, +#define Z_IS_2271U_EQ_2271U(...) \, +#define Z_IS_2272_EQ_2272(...) \, +#define Z_IS_2272U_EQ_2272(...) \, +#define Z_IS_2272_EQ_2272U(...) \, +#define Z_IS_2272U_EQ_2272U(...) \, +#define Z_IS_2273_EQ_2273(...) \, +#define Z_IS_2273U_EQ_2273(...) \, +#define Z_IS_2273_EQ_2273U(...) \, +#define Z_IS_2273U_EQ_2273U(...) \, +#define Z_IS_2274_EQ_2274(...) \, +#define Z_IS_2274U_EQ_2274(...) \, +#define Z_IS_2274_EQ_2274U(...) \, +#define Z_IS_2274U_EQ_2274U(...) \, +#define Z_IS_2275_EQ_2275(...) \, +#define Z_IS_2275U_EQ_2275(...) \, +#define Z_IS_2275_EQ_2275U(...) \, +#define Z_IS_2275U_EQ_2275U(...) \, +#define Z_IS_2276_EQ_2276(...) \, +#define Z_IS_2276U_EQ_2276(...) \, +#define Z_IS_2276_EQ_2276U(...) \, +#define Z_IS_2276U_EQ_2276U(...) \, +#define Z_IS_2277_EQ_2277(...) \, +#define Z_IS_2277U_EQ_2277(...) \, +#define Z_IS_2277_EQ_2277U(...) \, +#define Z_IS_2277U_EQ_2277U(...) \, +#define Z_IS_2278_EQ_2278(...) \, +#define Z_IS_2278U_EQ_2278(...) \, +#define Z_IS_2278_EQ_2278U(...) \, +#define Z_IS_2278U_EQ_2278U(...) \, +#define Z_IS_2279_EQ_2279(...) \, +#define Z_IS_2279U_EQ_2279(...) \, +#define Z_IS_2279_EQ_2279U(...) \, +#define Z_IS_2279U_EQ_2279U(...) \, +#define Z_IS_2280_EQ_2280(...) \, +#define Z_IS_2280U_EQ_2280(...) \, +#define Z_IS_2280_EQ_2280U(...) \, +#define Z_IS_2280U_EQ_2280U(...) \, +#define Z_IS_2281_EQ_2281(...) \, +#define Z_IS_2281U_EQ_2281(...) \, +#define Z_IS_2281_EQ_2281U(...) \, +#define Z_IS_2281U_EQ_2281U(...) \, +#define Z_IS_2282_EQ_2282(...) \, +#define Z_IS_2282U_EQ_2282(...) \, +#define Z_IS_2282_EQ_2282U(...) \, +#define Z_IS_2282U_EQ_2282U(...) \, +#define Z_IS_2283_EQ_2283(...) \, +#define Z_IS_2283U_EQ_2283(...) \, +#define Z_IS_2283_EQ_2283U(...) \, +#define Z_IS_2283U_EQ_2283U(...) \, +#define Z_IS_2284_EQ_2284(...) \, +#define Z_IS_2284U_EQ_2284(...) \, +#define Z_IS_2284_EQ_2284U(...) \, +#define Z_IS_2284U_EQ_2284U(...) \, +#define Z_IS_2285_EQ_2285(...) \, +#define Z_IS_2285U_EQ_2285(...) \, +#define Z_IS_2285_EQ_2285U(...) \, +#define Z_IS_2285U_EQ_2285U(...) \, +#define Z_IS_2286_EQ_2286(...) \, +#define Z_IS_2286U_EQ_2286(...) \, +#define Z_IS_2286_EQ_2286U(...) \, +#define Z_IS_2286U_EQ_2286U(...) \, +#define Z_IS_2287_EQ_2287(...) \, +#define Z_IS_2287U_EQ_2287(...) \, +#define Z_IS_2287_EQ_2287U(...) \, +#define Z_IS_2287U_EQ_2287U(...) \, +#define Z_IS_2288_EQ_2288(...) \, +#define Z_IS_2288U_EQ_2288(...) \, +#define Z_IS_2288_EQ_2288U(...) \, +#define Z_IS_2288U_EQ_2288U(...) \, +#define Z_IS_2289_EQ_2289(...) \, +#define Z_IS_2289U_EQ_2289(...) \, +#define Z_IS_2289_EQ_2289U(...) \, +#define Z_IS_2289U_EQ_2289U(...) \, +#define Z_IS_2290_EQ_2290(...) \, +#define Z_IS_2290U_EQ_2290(...) \, +#define Z_IS_2290_EQ_2290U(...) \, +#define Z_IS_2290U_EQ_2290U(...) \, +#define Z_IS_2291_EQ_2291(...) \, +#define Z_IS_2291U_EQ_2291(...) \, +#define Z_IS_2291_EQ_2291U(...) \, +#define Z_IS_2291U_EQ_2291U(...) \, +#define Z_IS_2292_EQ_2292(...) \, +#define Z_IS_2292U_EQ_2292(...) \, +#define Z_IS_2292_EQ_2292U(...) \, +#define Z_IS_2292U_EQ_2292U(...) \, +#define Z_IS_2293_EQ_2293(...) \, +#define Z_IS_2293U_EQ_2293(...) \, +#define Z_IS_2293_EQ_2293U(...) \, +#define Z_IS_2293U_EQ_2293U(...) \, +#define Z_IS_2294_EQ_2294(...) \, +#define Z_IS_2294U_EQ_2294(...) \, +#define Z_IS_2294_EQ_2294U(...) \, +#define Z_IS_2294U_EQ_2294U(...) \, +#define Z_IS_2295_EQ_2295(...) \, +#define Z_IS_2295U_EQ_2295(...) \, +#define Z_IS_2295_EQ_2295U(...) \, +#define Z_IS_2295U_EQ_2295U(...) \, +#define Z_IS_2296_EQ_2296(...) \, +#define Z_IS_2296U_EQ_2296(...) \, +#define Z_IS_2296_EQ_2296U(...) \, +#define Z_IS_2296U_EQ_2296U(...) \, +#define Z_IS_2297_EQ_2297(...) \, +#define Z_IS_2297U_EQ_2297(...) \, +#define Z_IS_2297_EQ_2297U(...) \, +#define Z_IS_2297U_EQ_2297U(...) \, +#define Z_IS_2298_EQ_2298(...) \, +#define Z_IS_2298U_EQ_2298(...) \, +#define Z_IS_2298_EQ_2298U(...) \, +#define Z_IS_2298U_EQ_2298U(...) \, +#define Z_IS_2299_EQ_2299(...) \, +#define Z_IS_2299U_EQ_2299(...) \, +#define Z_IS_2299_EQ_2299U(...) \, +#define Z_IS_2299U_EQ_2299U(...) \, +#define Z_IS_2300_EQ_2300(...) \, +#define Z_IS_2300U_EQ_2300(...) \, +#define Z_IS_2300_EQ_2300U(...) \, +#define Z_IS_2300U_EQ_2300U(...) \, +#define Z_IS_2301_EQ_2301(...) \, +#define Z_IS_2301U_EQ_2301(...) \, +#define Z_IS_2301_EQ_2301U(...) \, +#define Z_IS_2301U_EQ_2301U(...) \, +#define Z_IS_2302_EQ_2302(...) \, +#define Z_IS_2302U_EQ_2302(...) \, +#define Z_IS_2302_EQ_2302U(...) \, +#define Z_IS_2302U_EQ_2302U(...) \, +#define Z_IS_2303_EQ_2303(...) \, +#define Z_IS_2303U_EQ_2303(...) \, +#define Z_IS_2303_EQ_2303U(...) \, +#define Z_IS_2303U_EQ_2303U(...) \, +#define Z_IS_2304_EQ_2304(...) \, +#define Z_IS_2304U_EQ_2304(...) \, +#define Z_IS_2304_EQ_2304U(...) \, +#define Z_IS_2304U_EQ_2304U(...) \, +#define Z_IS_2305_EQ_2305(...) \, +#define Z_IS_2305U_EQ_2305(...) \, +#define Z_IS_2305_EQ_2305U(...) \, +#define Z_IS_2305U_EQ_2305U(...) \, +#define Z_IS_2306_EQ_2306(...) \, +#define Z_IS_2306U_EQ_2306(...) \, +#define Z_IS_2306_EQ_2306U(...) \, +#define Z_IS_2306U_EQ_2306U(...) \, +#define Z_IS_2307_EQ_2307(...) \, +#define Z_IS_2307U_EQ_2307(...) \, +#define Z_IS_2307_EQ_2307U(...) \, +#define Z_IS_2307U_EQ_2307U(...) \, +#define Z_IS_2308_EQ_2308(...) \, +#define Z_IS_2308U_EQ_2308(...) \, +#define Z_IS_2308_EQ_2308U(...) \, +#define Z_IS_2308U_EQ_2308U(...) \, +#define Z_IS_2309_EQ_2309(...) \, +#define Z_IS_2309U_EQ_2309(...) \, +#define Z_IS_2309_EQ_2309U(...) \, +#define Z_IS_2309U_EQ_2309U(...) \, +#define Z_IS_2310_EQ_2310(...) \, +#define Z_IS_2310U_EQ_2310(...) \, +#define Z_IS_2310_EQ_2310U(...) \, +#define Z_IS_2310U_EQ_2310U(...) \, +#define Z_IS_2311_EQ_2311(...) \, +#define Z_IS_2311U_EQ_2311(...) \, +#define Z_IS_2311_EQ_2311U(...) \, +#define Z_IS_2311U_EQ_2311U(...) \, +#define Z_IS_2312_EQ_2312(...) \, +#define Z_IS_2312U_EQ_2312(...) \, +#define Z_IS_2312_EQ_2312U(...) \, +#define Z_IS_2312U_EQ_2312U(...) \, +#define Z_IS_2313_EQ_2313(...) \, +#define Z_IS_2313U_EQ_2313(...) \, +#define Z_IS_2313_EQ_2313U(...) \, +#define Z_IS_2313U_EQ_2313U(...) \, +#define Z_IS_2314_EQ_2314(...) \, +#define Z_IS_2314U_EQ_2314(...) \, +#define Z_IS_2314_EQ_2314U(...) \, +#define Z_IS_2314U_EQ_2314U(...) \, +#define Z_IS_2315_EQ_2315(...) \, +#define Z_IS_2315U_EQ_2315(...) \, +#define Z_IS_2315_EQ_2315U(...) \, +#define Z_IS_2315U_EQ_2315U(...) \, +#define Z_IS_2316_EQ_2316(...) \, +#define Z_IS_2316U_EQ_2316(...) \, +#define Z_IS_2316_EQ_2316U(...) \, +#define Z_IS_2316U_EQ_2316U(...) \, +#define Z_IS_2317_EQ_2317(...) \, +#define Z_IS_2317U_EQ_2317(...) \, +#define Z_IS_2317_EQ_2317U(...) \, +#define Z_IS_2317U_EQ_2317U(...) \, +#define Z_IS_2318_EQ_2318(...) \, +#define Z_IS_2318U_EQ_2318(...) \, +#define Z_IS_2318_EQ_2318U(...) \, +#define Z_IS_2318U_EQ_2318U(...) \, +#define Z_IS_2319_EQ_2319(...) \, +#define Z_IS_2319U_EQ_2319(...) \, +#define Z_IS_2319_EQ_2319U(...) \, +#define Z_IS_2319U_EQ_2319U(...) \, +#define Z_IS_2320_EQ_2320(...) \, +#define Z_IS_2320U_EQ_2320(...) \, +#define Z_IS_2320_EQ_2320U(...) \, +#define Z_IS_2320U_EQ_2320U(...) \, +#define Z_IS_2321_EQ_2321(...) \, +#define Z_IS_2321U_EQ_2321(...) \, +#define Z_IS_2321_EQ_2321U(...) \, +#define Z_IS_2321U_EQ_2321U(...) \, +#define Z_IS_2322_EQ_2322(...) \, +#define Z_IS_2322U_EQ_2322(...) \, +#define Z_IS_2322_EQ_2322U(...) \, +#define Z_IS_2322U_EQ_2322U(...) \, +#define Z_IS_2323_EQ_2323(...) \, +#define Z_IS_2323U_EQ_2323(...) \, +#define Z_IS_2323_EQ_2323U(...) \, +#define Z_IS_2323U_EQ_2323U(...) \, +#define Z_IS_2324_EQ_2324(...) \, +#define Z_IS_2324U_EQ_2324(...) \, +#define Z_IS_2324_EQ_2324U(...) \, +#define Z_IS_2324U_EQ_2324U(...) \, +#define Z_IS_2325_EQ_2325(...) \, +#define Z_IS_2325U_EQ_2325(...) \, +#define Z_IS_2325_EQ_2325U(...) \, +#define Z_IS_2325U_EQ_2325U(...) \, +#define Z_IS_2326_EQ_2326(...) \, +#define Z_IS_2326U_EQ_2326(...) \, +#define Z_IS_2326_EQ_2326U(...) \, +#define Z_IS_2326U_EQ_2326U(...) \, +#define Z_IS_2327_EQ_2327(...) \, +#define Z_IS_2327U_EQ_2327(...) \, +#define Z_IS_2327_EQ_2327U(...) \, +#define Z_IS_2327U_EQ_2327U(...) \, +#define Z_IS_2328_EQ_2328(...) \, +#define Z_IS_2328U_EQ_2328(...) \, +#define Z_IS_2328_EQ_2328U(...) \, +#define Z_IS_2328U_EQ_2328U(...) \, +#define Z_IS_2329_EQ_2329(...) \, +#define Z_IS_2329U_EQ_2329(...) \, +#define Z_IS_2329_EQ_2329U(...) \, +#define Z_IS_2329U_EQ_2329U(...) \, +#define Z_IS_2330_EQ_2330(...) \, +#define Z_IS_2330U_EQ_2330(...) \, +#define Z_IS_2330_EQ_2330U(...) \, +#define Z_IS_2330U_EQ_2330U(...) \, +#define Z_IS_2331_EQ_2331(...) \, +#define Z_IS_2331U_EQ_2331(...) \, +#define Z_IS_2331_EQ_2331U(...) \, +#define Z_IS_2331U_EQ_2331U(...) \, +#define Z_IS_2332_EQ_2332(...) \, +#define Z_IS_2332U_EQ_2332(...) \, +#define Z_IS_2332_EQ_2332U(...) \, +#define Z_IS_2332U_EQ_2332U(...) \, +#define Z_IS_2333_EQ_2333(...) \, +#define Z_IS_2333U_EQ_2333(...) \, +#define Z_IS_2333_EQ_2333U(...) \, +#define Z_IS_2333U_EQ_2333U(...) \, +#define Z_IS_2334_EQ_2334(...) \, +#define Z_IS_2334U_EQ_2334(...) \, +#define Z_IS_2334_EQ_2334U(...) \, +#define Z_IS_2334U_EQ_2334U(...) \, +#define Z_IS_2335_EQ_2335(...) \, +#define Z_IS_2335U_EQ_2335(...) \, +#define Z_IS_2335_EQ_2335U(...) \, +#define Z_IS_2335U_EQ_2335U(...) \, +#define Z_IS_2336_EQ_2336(...) \, +#define Z_IS_2336U_EQ_2336(...) \, +#define Z_IS_2336_EQ_2336U(...) \, +#define Z_IS_2336U_EQ_2336U(...) \, +#define Z_IS_2337_EQ_2337(...) \, +#define Z_IS_2337U_EQ_2337(...) \, +#define Z_IS_2337_EQ_2337U(...) \, +#define Z_IS_2337U_EQ_2337U(...) \, +#define Z_IS_2338_EQ_2338(...) \, +#define Z_IS_2338U_EQ_2338(...) \, +#define Z_IS_2338_EQ_2338U(...) \, +#define Z_IS_2338U_EQ_2338U(...) \, +#define Z_IS_2339_EQ_2339(...) \, +#define Z_IS_2339U_EQ_2339(...) \, +#define Z_IS_2339_EQ_2339U(...) \, +#define Z_IS_2339U_EQ_2339U(...) \, +#define Z_IS_2340_EQ_2340(...) \, +#define Z_IS_2340U_EQ_2340(...) \, +#define Z_IS_2340_EQ_2340U(...) \, +#define Z_IS_2340U_EQ_2340U(...) \, +#define Z_IS_2341_EQ_2341(...) \, +#define Z_IS_2341U_EQ_2341(...) \, +#define Z_IS_2341_EQ_2341U(...) \, +#define Z_IS_2341U_EQ_2341U(...) \, +#define Z_IS_2342_EQ_2342(...) \, +#define Z_IS_2342U_EQ_2342(...) \, +#define Z_IS_2342_EQ_2342U(...) \, +#define Z_IS_2342U_EQ_2342U(...) \, +#define Z_IS_2343_EQ_2343(...) \, +#define Z_IS_2343U_EQ_2343(...) \, +#define Z_IS_2343_EQ_2343U(...) \, +#define Z_IS_2343U_EQ_2343U(...) \, +#define Z_IS_2344_EQ_2344(...) \, +#define Z_IS_2344U_EQ_2344(...) \, +#define Z_IS_2344_EQ_2344U(...) \, +#define Z_IS_2344U_EQ_2344U(...) \, +#define Z_IS_2345_EQ_2345(...) \, +#define Z_IS_2345U_EQ_2345(...) \, +#define Z_IS_2345_EQ_2345U(...) \, +#define Z_IS_2345U_EQ_2345U(...) \, +#define Z_IS_2346_EQ_2346(...) \, +#define Z_IS_2346U_EQ_2346(...) \, +#define Z_IS_2346_EQ_2346U(...) \, +#define Z_IS_2346U_EQ_2346U(...) \, +#define Z_IS_2347_EQ_2347(...) \, +#define Z_IS_2347U_EQ_2347(...) \, +#define Z_IS_2347_EQ_2347U(...) \, +#define Z_IS_2347U_EQ_2347U(...) \, +#define Z_IS_2348_EQ_2348(...) \, +#define Z_IS_2348U_EQ_2348(...) \, +#define Z_IS_2348_EQ_2348U(...) \, +#define Z_IS_2348U_EQ_2348U(...) \, +#define Z_IS_2349_EQ_2349(...) \, +#define Z_IS_2349U_EQ_2349(...) \, +#define Z_IS_2349_EQ_2349U(...) \, +#define Z_IS_2349U_EQ_2349U(...) \, +#define Z_IS_2350_EQ_2350(...) \, +#define Z_IS_2350U_EQ_2350(...) \, +#define Z_IS_2350_EQ_2350U(...) \, +#define Z_IS_2350U_EQ_2350U(...) \, +#define Z_IS_2351_EQ_2351(...) \, +#define Z_IS_2351U_EQ_2351(...) \, +#define Z_IS_2351_EQ_2351U(...) \, +#define Z_IS_2351U_EQ_2351U(...) \, +#define Z_IS_2352_EQ_2352(...) \, +#define Z_IS_2352U_EQ_2352(...) \, +#define Z_IS_2352_EQ_2352U(...) \, +#define Z_IS_2352U_EQ_2352U(...) \, +#define Z_IS_2353_EQ_2353(...) \, +#define Z_IS_2353U_EQ_2353(...) \, +#define Z_IS_2353_EQ_2353U(...) \, +#define Z_IS_2353U_EQ_2353U(...) \, +#define Z_IS_2354_EQ_2354(...) \, +#define Z_IS_2354U_EQ_2354(...) \, +#define Z_IS_2354_EQ_2354U(...) \, +#define Z_IS_2354U_EQ_2354U(...) \, +#define Z_IS_2355_EQ_2355(...) \, +#define Z_IS_2355U_EQ_2355(...) \, +#define Z_IS_2355_EQ_2355U(...) \, +#define Z_IS_2355U_EQ_2355U(...) \, +#define Z_IS_2356_EQ_2356(...) \, +#define Z_IS_2356U_EQ_2356(...) \, +#define Z_IS_2356_EQ_2356U(...) \, +#define Z_IS_2356U_EQ_2356U(...) \, +#define Z_IS_2357_EQ_2357(...) \, +#define Z_IS_2357U_EQ_2357(...) \, +#define Z_IS_2357_EQ_2357U(...) \, +#define Z_IS_2357U_EQ_2357U(...) \, +#define Z_IS_2358_EQ_2358(...) \, +#define Z_IS_2358U_EQ_2358(...) \, +#define Z_IS_2358_EQ_2358U(...) \, +#define Z_IS_2358U_EQ_2358U(...) \, +#define Z_IS_2359_EQ_2359(...) \, +#define Z_IS_2359U_EQ_2359(...) \, +#define Z_IS_2359_EQ_2359U(...) \, +#define Z_IS_2359U_EQ_2359U(...) \, +#define Z_IS_2360_EQ_2360(...) \, +#define Z_IS_2360U_EQ_2360(...) \, +#define Z_IS_2360_EQ_2360U(...) \, +#define Z_IS_2360U_EQ_2360U(...) \, +#define Z_IS_2361_EQ_2361(...) \, +#define Z_IS_2361U_EQ_2361(...) \, +#define Z_IS_2361_EQ_2361U(...) \, +#define Z_IS_2361U_EQ_2361U(...) \, +#define Z_IS_2362_EQ_2362(...) \, +#define Z_IS_2362U_EQ_2362(...) \, +#define Z_IS_2362_EQ_2362U(...) \, +#define Z_IS_2362U_EQ_2362U(...) \, +#define Z_IS_2363_EQ_2363(...) \, +#define Z_IS_2363U_EQ_2363(...) \, +#define Z_IS_2363_EQ_2363U(...) \, +#define Z_IS_2363U_EQ_2363U(...) \, +#define Z_IS_2364_EQ_2364(...) \, +#define Z_IS_2364U_EQ_2364(...) \, +#define Z_IS_2364_EQ_2364U(...) \, +#define Z_IS_2364U_EQ_2364U(...) \, +#define Z_IS_2365_EQ_2365(...) \, +#define Z_IS_2365U_EQ_2365(...) \, +#define Z_IS_2365_EQ_2365U(...) \, +#define Z_IS_2365U_EQ_2365U(...) \, +#define Z_IS_2366_EQ_2366(...) \, +#define Z_IS_2366U_EQ_2366(...) \, +#define Z_IS_2366_EQ_2366U(...) \, +#define Z_IS_2366U_EQ_2366U(...) \, +#define Z_IS_2367_EQ_2367(...) \, +#define Z_IS_2367U_EQ_2367(...) \, +#define Z_IS_2367_EQ_2367U(...) \, +#define Z_IS_2367U_EQ_2367U(...) \, +#define Z_IS_2368_EQ_2368(...) \, +#define Z_IS_2368U_EQ_2368(...) \, +#define Z_IS_2368_EQ_2368U(...) \, +#define Z_IS_2368U_EQ_2368U(...) \, +#define Z_IS_2369_EQ_2369(...) \, +#define Z_IS_2369U_EQ_2369(...) \, +#define Z_IS_2369_EQ_2369U(...) \, +#define Z_IS_2369U_EQ_2369U(...) \, +#define Z_IS_2370_EQ_2370(...) \, +#define Z_IS_2370U_EQ_2370(...) \, +#define Z_IS_2370_EQ_2370U(...) \, +#define Z_IS_2370U_EQ_2370U(...) \, +#define Z_IS_2371_EQ_2371(...) \, +#define Z_IS_2371U_EQ_2371(...) \, +#define Z_IS_2371_EQ_2371U(...) \, +#define Z_IS_2371U_EQ_2371U(...) \, +#define Z_IS_2372_EQ_2372(...) \, +#define Z_IS_2372U_EQ_2372(...) \, +#define Z_IS_2372_EQ_2372U(...) \, +#define Z_IS_2372U_EQ_2372U(...) \, +#define Z_IS_2373_EQ_2373(...) \, +#define Z_IS_2373U_EQ_2373(...) \, +#define Z_IS_2373_EQ_2373U(...) \, +#define Z_IS_2373U_EQ_2373U(...) \, +#define Z_IS_2374_EQ_2374(...) \, +#define Z_IS_2374U_EQ_2374(...) \, +#define Z_IS_2374_EQ_2374U(...) \, +#define Z_IS_2374U_EQ_2374U(...) \, +#define Z_IS_2375_EQ_2375(...) \, +#define Z_IS_2375U_EQ_2375(...) \, +#define Z_IS_2375_EQ_2375U(...) \, +#define Z_IS_2375U_EQ_2375U(...) \, +#define Z_IS_2376_EQ_2376(...) \, +#define Z_IS_2376U_EQ_2376(...) \, +#define Z_IS_2376_EQ_2376U(...) \, +#define Z_IS_2376U_EQ_2376U(...) \, +#define Z_IS_2377_EQ_2377(...) \, +#define Z_IS_2377U_EQ_2377(...) \, +#define Z_IS_2377_EQ_2377U(...) \, +#define Z_IS_2377U_EQ_2377U(...) \, +#define Z_IS_2378_EQ_2378(...) \, +#define Z_IS_2378U_EQ_2378(...) \, +#define Z_IS_2378_EQ_2378U(...) \, +#define Z_IS_2378U_EQ_2378U(...) \, +#define Z_IS_2379_EQ_2379(...) \, +#define Z_IS_2379U_EQ_2379(...) \, +#define Z_IS_2379_EQ_2379U(...) \, +#define Z_IS_2379U_EQ_2379U(...) \, +#define Z_IS_2380_EQ_2380(...) \, +#define Z_IS_2380U_EQ_2380(...) \, +#define Z_IS_2380_EQ_2380U(...) \, +#define Z_IS_2380U_EQ_2380U(...) \, +#define Z_IS_2381_EQ_2381(...) \, +#define Z_IS_2381U_EQ_2381(...) \, +#define Z_IS_2381_EQ_2381U(...) \, +#define Z_IS_2381U_EQ_2381U(...) \, +#define Z_IS_2382_EQ_2382(...) \, +#define Z_IS_2382U_EQ_2382(...) \, +#define Z_IS_2382_EQ_2382U(...) \, +#define Z_IS_2382U_EQ_2382U(...) \, +#define Z_IS_2383_EQ_2383(...) \, +#define Z_IS_2383U_EQ_2383(...) \, +#define Z_IS_2383_EQ_2383U(...) \, +#define Z_IS_2383U_EQ_2383U(...) \, +#define Z_IS_2384_EQ_2384(...) \, +#define Z_IS_2384U_EQ_2384(...) \, +#define Z_IS_2384_EQ_2384U(...) \, +#define Z_IS_2384U_EQ_2384U(...) \, +#define Z_IS_2385_EQ_2385(...) \, +#define Z_IS_2385U_EQ_2385(...) \, +#define Z_IS_2385_EQ_2385U(...) \, +#define Z_IS_2385U_EQ_2385U(...) \, +#define Z_IS_2386_EQ_2386(...) \, +#define Z_IS_2386U_EQ_2386(...) \, +#define Z_IS_2386_EQ_2386U(...) \, +#define Z_IS_2386U_EQ_2386U(...) \, +#define Z_IS_2387_EQ_2387(...) \, +#define Z_IS_2387U_EQ_2387(...) \, +#define Z_IS_2387_EQ_2387U(...) \, +#define Z_IS_2387U_EQ_2387U(...) \, +#define Z_IS_2388_EQ_2388(...) \, +#define Z_IS_2388U_EQ_2388(...) \, +#define Z_IS_2388_EQ_2388U(...) \, +#define Z_IS_2388U_EQ_2388U(...) \, +#define Z_IS_2389_EQ_2389(...) \, +#define Z_IS_2389U_EQ_2389(...) \, +#define Z_IS_2389_EQ_2389U(...) \, +#define Z_IS_2389U_EQ_2389U(...) \, +#define Z_IS_2390_EQ_2390(...) \, +#define Z_IS_2390U_EQ_2390(...) \, +#define Z_IS_2390_EQ_2390U(...) \, +#define Z_IS_2390U_EQ_2390U(...) \, +#define Z_IS_2391_EQ_2391(...) \, +#define Z_IS_2391U_EQ_2391(...) \, +#define Z_IS_2391_EQ_2391U(...) \, +#define Z_IS_2391U_EQ_2391U(...) \, +#define Z_IS_2392_EQ_2392(...) \, +#define Z_IS_2392U_EQ_2392(...) \, +#define Z_IS_2392_EQ_2392U(...) \, +#define Z_IS_2392U_EQ_2392U(...) \, +#define Z_IS_2393_EQ_2393(...) \, +#define Z_IS_2393U_EQ_2393(...) \, +#define Z_IS_2393_EQ_2393U(...) \, +#define Z_IS_2393U_EQ_2393U(...) \, +#define Z_IS_2394_EQ_2394(...) \, +#define Z_IS_2394U_EQ_2394(...) \, +#define Z_IS_2394_EQ_2394U(...) \, +#define Z_IS_2394U_EQ_2394U(...) \, +#define Z_IS_2395_EQ_2395(...) \, +#define Z_IS_2395U_EQ_2395(...) \, +#define Z_IS_2395_EQ_2395U(...) \, +#define Z_IS_2395U_EQ_2395U(...) \, +#define Z_IS_2396_EQ_2396(...) \, +#define Z_IS_2396U_EQ_2396(...) \, +#define Z_IS_2396_EQ_2396U(...) \, +#define Z_IS_2396U_EQ_2396U(...) \, +#define Z_IS_2397_EQ_2397(...) \, +#define Z_IS_2397U_EQ_2397(...) \, +#define Z_IS_2397_EQ_2397U(...) \, +#define Z_IS_2397U_EQ_2397U(...) \, +#define Z_IS_2398_EQ_2398(...) \, +#define Z_IS_2398U_EQ_2398(...) \, +#define Z_IS_2398_EQ_2398U(...) \, +#define Z_IS_2398U_EQ_2398U(...) \, +#define Z_IS_2399_EQ_2399(...) \, +#define Z_IS_2399U_EQ_2399(...) \, +#define Z_IS_2399_EQ_2399U(...) \, +#define Z_IS_2399U_EQ_2399U(...) \, +#define Z_IS_2400_EQ_2400(...) \, +#define Z_IS_2400U_EQ_2400(...) \, +#define Z_IS_2400_EQ_2400U(...) \, +#define Z_IS_2400U_EQ_2400U(...) \, +#define Z_IS_2401_EQ_2401(...) \, +#define Z_IS_2401U_EQ_2401(...) \, +#define Z_IS_2401_EQ_2401U(...) \, +#define Z_IS_2401U_EQ_2401U(...) \, +#define Z_IS_2402_EQ_2402(...) \, +#define Z_IS_2402U_EQ_2402(...) \, +#define Z_IS_2402_EQ_2402U(...) \, +#define Z_IS_2402U_EQ_2402U(...) \, +#define Z_IS_2403_EQ_2403(...) \, +#define Z_IS_2403U_EQ_2403(...) \, +#define Z_IS_2403_EQ_2403U(...) \, +#define Z_IS_2403U_EQ_2403U(...) \, +#define Z_IS_2404_EQ_2404(...) \, +#define Z_IS_2404U_EQ_2404(...) \, +#define Z_IS_2404_EQ_2404U(...) \, +#define Z_IS_2404U_EQ_2404U(...) \, +#define Z_IS_2405_EQ_2405(...) \, +#define Z_IS_2405U_EQ_2405(...) \, +#define Z_IS_2405_EQ_2405U(...) \, +#define Z_IS_2405U_EQ_2405U(...) \, +#define Z_IS_2406_EQ_2406(...) \, +#define Z_IS_2406U_EQ_2406(...) \, +#define Z_IS_2406_EQ_2406U(...) \, +#define Z_IS_2406U_EQ_2406U(...) \, +#define Z_IS_2407_EQ_2407(...) \, +#define Z_IS_2407U_EQ_2407(...) \, +#define Z_IS_2407_EQ_2407U(...) \, +#define Z_IS_2407U_EQ_2407U(...) \, +#define Z_IS_2408_EQ_2408(...) \, +#define Z_IS_2408U_EQ_2408(...) \, +#define Z_IS_2408_EQ_2408U(...) \, +#define Z_IS_2408U_EQ_2408U(...) \, +#define Z_IS_2409_EQ_2409(...) \, +#define Z_IS_2409U_EQ_2409(...) \, +#define Z_IS_2409_EQ_2409U(...) \, +#define Z_IS_2409U_EQ_2409U(...) \, +#define Z_IS_2410_EQ_2410(...) \, +#define Z_IS_2410U_EQ_2410(...) \, +#define Z_IS_2410_EQ_2410U(...) \, +#define Z_IS_2410U_EQ_2410U(...) \, +#define Z_IS_2411_EQ_2411(...) \, +#define Z_IS_2411U_EQ_2411(...) \, +#define Z_IS_2411_EQ_2411U(...) \, +#define Z_IS_2411U_EQ_2411U(...) \, +#define Z_IS_2412_EQ_2412(...) \, +#define Z_IS_2412U_EQ_2412(...) \, +#define Z_IS_2412_EQ_2412U(...) \, +#define Z_IS_2412U_EQ_2412U(...) \, +#define Z_IS_2413_EQ_2413(...) \, +#define Z_IS_2413U_EQ_2413(...) \, +#define Z_IS_2413_EQ_2413U(...) \, +#define Z_IS_2413U_EQ_2413U(...) \, +#define Z_IS_2414_EQ_2414(...) \, +#define Z_IS_2414U_EQ_2414(...) \, +#define Z_IS_2414_EQ_2414U(...) \, +#define Z_IS_2414U_EQ_2414U(...) \, +#define Z_IS_2415_EQ_2415(...) \, +#define Z_IS_2415U_EQ_2415(...) \, +#define Z_IS_2415_EQ_2415U(...) \, +#define Z_IS_2415U_EQ_2415U(...) \, +#define Z_IS_2416_EQ_2416(...) \, +#define Z_IS_2416U_EQ_2416(...) \, +#define Z_IS_2416_EQ_2416U(...) \, +#define Z_IS_2416U_EQ_2416U(...) \, +#define Z_IS_2417_EQ_2417(...) \, +#define Z_IS_2417U_EQ_2417(...) \, +#define Z_IS_2417_EQ_2417U(...) \, +#define Z_IS_2417U_EQ_2417U(...) \, +#define Z_IS_2418_EQ_2418(...) \, +#define Z_IS_2418U_EQ_2418(...) \, +#define Z_IS_2418_EQ_2418U(...) \, +#define Z_IS_2418U_EQ_2418U(...) \, +#define Z_IS_2419_EQ_2419(...) \, +#define Z_IS_2419U_EQ_2419(...) \, +#define Z_IS_2419_EQ_2419U(...) \, +#define Z_IS_2419U_EQ_2419U(...) \, +#define Z_IS_2420_EQ_2420(...) \, +#define Z_IS_2420U_EQ_2420(...) \, +#define Z_IS_2420_EQ_2420U(...) \, +#define Z_IS_2420U_EQ_2420U(...) \, +#define Z_IS_2421_EQ_2421(...) \, +#define Z_IS_2421U_EQ_2421(...) \, +#define Z_IS_2421_EQ_2421U(...) \, +#define Z_IS_2421U_EQ_2421U(...) \, +#define Z_IS_2422_EQ_2422(...) \, +#define Z_IS_2422U_EQ_2422(...) \, +#define Z_IS_2422_EQ_2422U(...) \, +#define Z_IS_2422U_EQ_2422U(...) \, +#define Z_IS_2423_EQ_2423(...) \, +#define Z_IS_2423U_EQ_2423(...) \, +#define Z_IS_2423_EQ_2423U(...) \, +#define Z_IS_2423U_EQ_2423U(...) \, +#define Z_IS_2424_EQ_2424(...) \, +#define Z_IS_2424U_EQ_2424(...) \, +#define Z_IS_2424_EQ_2424U(...) \, +#define Z_IS_2424U_EQ_2424U(...) \, +#define Z_IS_2425_EQ_2425(...) \, +#define Z_IS_2425U_EQ_2425(...) \, +#define Z_IS_2425_EQ_2425U(...) \, +#define Z_IS_2425U_EQ_2425U(...) \, +#define Z_IS_2426_EQ_2426(...) \, +#define Z_IS_2426U_EQ_2426(...) \, +#define Z_IS_2426_EQ_2426U(...) \, +#define Z_IS_2426U_EQ_2426U(...) \, +#define Z_IS_2427_EQ_2427(...) \, +#define Z_IS_2427U_EQ_2427(...) \, +#define Z_IS_2427_EQ_2427U(...) \, +#define Z_IS_2427U_EQ_2427U(...) \, +#define Z_IS_2428_EQ_2428(...) \, +#define Z_IS_2428U_EQ_2428(...) \, +#define Z_IS_2428_EQ_2428U(...) \, +#define Z_IS_2428U_EQ_2428U(...) \, +#define Z_IS_2429_EQ_2429(...) \, +#define Z_IS_2429U_EQ_2429(...) \, +#define Z_IS_2429_EQ_2429U(...) \, +#define Z_IS_2429U_EQ_2429U(...) \, +#define Z_IS_2430_EQ_2430(...) \, +#define Z_IS_2430U_EQ_2430(...) \, +#define Z_IS_2430_EQ_2430U(...) \, +#define Z_IS_2430U_EQ_2430U(...) \, +#define Z_IS_2431_EQ_2431(...) \, +#define Z_IS_2431U_EQ_2431(...) \, +#define Z_IS_2431_EQ_2431U(...) \, +#define Z_IS_2431U_EQ_2431U(...) \, +#define Z_IS_2432_EQ_2432(...) \, +#define Z_IS_2432U_EQ_2432(...) \, +#define Z_IS_2432_EQ_2432U(...) \, +#define Z_IS_2432U_EQ_2432U(...) \, +#define Z_IS_2433_EQ_2433(...) \, +#define Z_IS_2433U_EQ_2433(...) \, +#define Z_IS_2433_EQ_2433U(...) \, +#define Z_IS_2433U_EQ_2433U(...) \, +#define Z_IS_2434_EQ_2434(...) \, +#define Z_IS_2434U_EQ_2434(...) \, +#define Z_IS_2434_EQ_2434U(...) \, +#define Z_IS_2434U_EQ_2434U(...) \, +#define Z_IS_2435_EQ_2435(...) \, +#define Z_IS_2435U_EQ_2435(...) \, +#define Z_IS_2435_EQ_2435U(...) \, +#define Z_IS_2435U_EQ_2435U(...) \, +#define Z_IS_2436_EQ_2436(...) \, +#define Z_IS_2436U_EQ_2436(...) \, +#define Z_IS_2436_EQ_2436U(...) \, +#define Z_IS_2436U_EQ_2436U(...) \, +#define Z_IS_2437_EQ_2437(...) \, +#define Z_IS_2437U_EQ_2437(...) \, +#define Z_IS_2437_EQ_2437U(...) \, +#define Z_IS_2437U_EQ_2437U(...) \, +#define Z_IS_2438_EQ_2438(...) \, +#define Z_IS_2438U_EQ_2438(...) \, +#define Z_IS_2438_EQ_2438U(...) \, +#define Z_IS_2438U_EQ_2438U(...) \, +#define Z_IS_2439_EQ_2439(...) \, +#define Z_IS_2439U_EQ_2439(...) \, +#define Z_IS_2439_EQ_2439U(...) \, +#define Z_IS_2439U_EQ_2439U(...) \, +#define Z_IS_2440_EQ_2440(...) \, +#define Z_IS_2440U_EQ_2440(...) \, +#define Z_IS_2440_EQ_2440U(...) \, +#define Z_IS_2440U_EQ_2440U(...) \, +#define Z_IS_2441_EQ_2441(...) \, +#define Z_IS_2441U_EQ_2441(...) \, +#define Z_IS_2441_EQ_2441U(...) \, +#define Z_IS_2441U_EQ_2441U(...) \, +#define Z_IS_2442_EQ_2442(...) \, +#define Z_IS_2442U_EQ_2442(...) \, +#define Z_IS_2442_EQ_2442U(...) \, +#define Z_IS_2442U_EQ_2442U(...) \, +#define Z_IS_2443_EQ_2443(...) \, +#define Z_IS_2443U_EQ_2443(...) \, +#define Z_IS_2443_EQ_2443U(...) \, +#define Z_IS_2443U_EQ_2443U(...) \, +#define Z_IS_2444_EQ_2444(...) \, +#define Z_IS_2444U_EQ_2444(...) \, +#define Z_IS_2444_EQ_2444U(...) \, +#define Z_IS_2444U_EQ_2444U(...) \, +#define Z_IS_2445_EQ_2445(...) \, +#define Z_IS_2445U_EQ_2445(...) \, +#define Z_IS_2445_EQ_2445U(...) \, +#define Z_IS_2445U_EQ_2445U(...) \, +#define Z_IS_2446_EQ_2446(...) \, +#define Z_IS_2446U_EQ_2446(...) \, +#define Z_IS_2446_EQ_2446U(...) \, +#define Z_IS_2446U_EQ_2446U(...) \, +#define Z_IS_2447_EQ_2447(...) \, +#define Z_IS_2447U_EQ_2447(...) \, +#define Z_IS_2447_EQ_2447U(...) \, +#define Z_IS_2447U_EQ_2447U(...) \, +#define Z_IS_2448_EQ_2448(...) \, +#define Z_IS_2448U_EQ_2448(...) \, +#define Z_IS_2448_EQ_2448U(...) \, +#define Z_IS_2448U_EQ_2448U(...) \, +#define Z_IS_2449_EQ_2449(...) \, +#define Z_IS_2449U_EQ_2449(...) \, +#define Z_IS_2449_EQ_2449U(...) \, +#define Z_IS_2449U_EQ_2449U(...) \, +#define Z_IS_2450_EQ_2450(...) \, +#define Z_IS_2450U_EQ_2450(...) \, +#define Z_IS_2450_EQ_2450U(...) \, +#define Z_IS_2450U_EQ_2450U(...) \, +#define Z_IS_2451_EQ_2451(...) \, +#define Z_IS_2451U_EQ_2451(...) \, +#define Z_IS_2451_EQ_2451U(...) \, +#define Z_IS_2451U_EQ_2451U(...) \, +#define Z_IS_2452_EQ_2452(...) \, +#define Z_IS_2452U_EQ_2452(...) \, +#define Z_IS_2452_EQ_2452U(...) \, +#define Z_IS_2452U_EQ_2452U(...) \, +#define Z_IS_2453_EQ_2453(...) \, +#define Z_IS_2453U_EQ_2453(...) \, +#define Z_IS_2453_EQ_2453U(...) \, +#define Z_IS_2453U_EQ_2453U(...) \, +#define Z_IS_2454_EQ_2454(...) \, +#define Z_IS_2454U_EQ_2454(...) \, +#define Z_IS_2454_EQ_2454U(...) \, +#define Z_IS_2454U_EQ_2454U(...) \, +#define Z_IS_2455_EQ_2455(...) \, +#define Z_IS_2455U_EQ_2455(...) \, +#define Z_IS_2455_EQ_2455U(...) \, +#define Z_IS_2455U_EQ_2455U(...) \, +#define Z_IS_2456_EQ_2456(...) \, +#define Z_IS_2456U_EQ_2456(...) \, +#define Z_IS_2456_EQ_2456U(...) \, +#define Z_IS_2456U_EQ_2456U(...) \, +#define Z_IS_2457_EQ_2457(...) \, +#define Z_IS_2457U_EQ_2457(...) \, +#define Z_IS_2457_EQ_2457U(...) \, +#define Z_IS_2457U_EQ_2457U(...) \, +#define Z_IS_2458_EQ_2458(...) \, +#define Z_IS_2458U_EQ_2458(...) \, +#define Z_IS_2458_EQ_2458U(...) \, +#define Z_IS_2458U_EQ_2458U(...) \, +#define Z_IS_2459_EQ_2459(...) \, +#define Z_IS_2459U_EQ_2459(...) \, +#define Z_IS_2459_EQ_2459U(...) \, +#define Z_IS_2459U_EQ_2459U(...) \, +#define Z_IS_2460_EQ_2460(...) \, +#define Z_IS_2460U_EQ_2460(...) \, +#define Z_IS_2460_EQ_2460U(...) \, +#define Z_IS_2460U_EQ_2460U(...) \, +#define Z_IS_2461_EQ_2461(...) \, +#define Z_IS_2461U_EQ_2461(...) \, +#define Z_IS_2461_EQ_2461U(...) \, +#define Z_IS_2461U_EQ_2461U(...) \, +#define Z_IS_2462_EQ_2462(...) \, +#define Z_IS_2462U_EQ_2462(...) \, +#define Z_IS_2462_EQ_2462U(...) \, +#define Z_IS_2462U_EQ_2462U(...) \, +#define Z_IS_2463_EQ_2463(...) \, +#define Z_IS_2463U_EQ_2463(...) \, +#define Z_IS_2463_EQ_2463U(...) \, +#define Z_IS_2463U_EQ_2463U(...) \, +#define Z_IS_2464_EQ_2464(...) \, +#define Z_IS_2464U_EQ_2464(...) \, +#define Z_IS_2464_EQ_2464U(...) \, +#define Z_IS_2464U_EQ_2464U(...) \, +#define Z_IS_2465_EQ_2465(...) \, +#define Z_IS_2465U_EQ_2465(...) \, +#define Z_IS_2465_EQ_2465U(...) \, +#define Z_IS_2465U_EQ_2465U(...) \, +#define Z_IS_2466_EQ_2466(...) \, +#define Z_IS_2466U_EQ_2466(...) \, +#define Z_IS_2466_EQ_2466U(...) \, +#define Z_IS_2466U_EQ_2466U(...) \, +#define Z_IS_2467_EQ_2467(...) \, +#define Z_IS_2467U_EQ_2467(...) \, +#define Z_IS_2467_EQ_2467U(...) \, +#define Z_IS_2467U_EQ_2467U(...) \, +#define Z_IS_2468_EQ_2468(...) \, +#define Z_IS_2468U_EQ_2468(...) \, +#define Z_IS_2468_EQ_2468U(...) \, +#define Z_IS_2468U_EQ_2468U(...) \, +#define Z_IS_2469_EQ_2469(...) \, +#define Z_IS_2469U_EQ_2469(...) \, +#define Z_IS_2469_EQ_2469U(...) \, +#define Z_IS_2469U_EQ_2469U(...) \, +#define Z_IS_2470_EQ_2470(...) \, +#define Z_IS_2470U_EQ_2470(...) \, +#define Z_IS_2470_EQ_2470U(...) \, +#define Z_IS_2470U_EQ_2470U(...) \, +#define Z_IS_2471_EQ_2471(...) \, +#define Z_IS_2471U_EQ_2471(...) \, +#define Z_IS_2471_EQ_2471U(...) \, +#define Z_IS_2471U_EQ_2471U(...) \, +#define Z_IS_2472_EQ_2472(...) \, +#define Z_IS_2472U_EQ_2472(...) \, +#define Z_IS_2472_EQ_2472U(...) \, +#define Z_IS_2472U_EQ_2472U(...) \, +#define Z_IS_2473_EQ_2473(...) \, +#define Z_IS_2473U_EQ_2473(...) \, +#define Z_IS_2473_EQ_2473U(...) \, +#define Z_IS_2473U_EQ_2473U(...) \, +#define Z_IS_2474_EQ_2474(...) \, +#define Z_IS_2474U_EQ_2474(...) \, +#define Z_IS_2474_EQ_2474U(...) \, +#define Z_IS_2474U_EQ_2474U(...) \, +#define Z_IS_2475_EQ_2475(...) \, +#define Z_IS_2475U_EQ_2475(...) \, +#define Z_IS_2475_EQ_2475U(...) \, +#define Z_IS_2475U_EQ_2475U(...) \, +#define Z_IS_2476_EQ_2476(...) \, +#define Z_IS_2476U_EQ_2476(...) \, +#define Z_IS_2476_EQ_2476U(...) \, +#define Z_IS_2476U_EQ_2476U(...) \, +#define Z_IS_2477_EQ_2477(...) \, +#define Z_IS_2477U_EQ_2477(...) \, +#define Z_IS_2477_EQ_2477U(...) \, +#define Z_IS_2477U_EQ_2477U(...) \, +#define Z_IS_2478_EQ_2478(...) \, +#define Z_IS_2478U_EQ_2478(...) \, +#define Z_IS_2478_EQ_2478U(...) \, +#define Z_IS_2478U_EQ_2478U(...) \, +#define Z_IS_2479_EQ_2479(...) \, +#define Z_IS_2479U_EQ_2479(...) \, +#define Z_IS_2479_EQ_2479U(...) \, +#define Z_IS_2479U_EQ_2479U(...) \, +#define Z_IS_2480_EQ_2480(...) \, +#define Z_IS_2480U_EQ_2480(...) \, +#define Z_IS_2480_EQ_2480U(...) \, +#define Z_IS_2480U_EQ_2480U(...) \, +#define Z_IS_2481_EQ_2481(...) \, +#define Z_IS_2481U_EQ_2481(...) \, +#define Z_IS_2481_EQ_2481U(...) \, +#define Z_IS_2481U_EQ_2481U(...) \, +#define Z_IS_2482_EQ_2482(...) \, +#define Z_IS_2482U_EQ_2482(...) \, +#define Z_IS_2482_EQ_2482U(...) \, +#define Z_IS_2482U_EQ_2482U(...) \, +#define Z_IS_2483_EQ_2483(...) \, +#define Z_IS_2483U_EQ_2483(...) \, +#define Z_IS_2483_EQ_2483U(...) \, +#define Z_IS_2483U_EQ_2483U(...) \, +#define Z_IS_2484_EQ_2484(...) \, +#define Z_IS_2484U_EQ_2484(...) \, +#define Z_IS_2484_EQ_2484U(...) \, +#define Z_IS_2484U_EQ_2484U(...) \, +#define Z_IS_2485_EQ_2485(...) \, +#define Z_IS_2485U_EQ_2485(...) \, +#define Z_IS_2485_EQ_2485U(...) \, +#define Z_IS_2485U_EQ_2485U(...) \, +#define Z_IS_2486_EQ_2486(...) \, +#define Z_IS_2486U_EQ_2486(...) \, +#define Z_IS_2486_EQ_2486U(...) \, +#define Z_IS_2486U_EQ_2486U(...) \, +#define Z_IS_2487_EQ_2487(...) \, +#define Z_IS_2487U_EQ_2487(...) \, +#define Z_IS_2487_EQ_2487U(...) \, +#define Z_IS_2487U_EQ_2487U(...) \, +#define Z_IS_2488_EQ_2488(...) \, +#define Z_IS_2488U_EQ_2488(...) \, +#define Z_IS_2488_EQ_2488U(...) \, +#define Z_IS_2488U_EQ_2488U(...) \, +#define Z_IS_2489_EQ_2489(...) \, +#define Z_IS_2489U_EQ_2489(...) \, +#define Z_IS_2489_EQ_2489U(...) \, +#define Z_IS_2489U_EQ_2489U(...) \, +#define Z_IS_2490_EQ_2490(...) \, +#define Z_IS_2490U_EQ_2490(...) \, +#define Z_IS_2490_EQ_2490U(...) \, +#define Z_IS_2490U_EQ_2490U(...) \, +#define Z_IS_2491_EQ_2491(...) \, +#define Z_IS_2491U_EQ_2491(...) \, +#define Z_IS_2491_EQ_2491U(...) \, +#define Z_IS_2491U_EQ_2491U(...) \, +#define Z_IS_2492_EQ_2492(...) \, +#define Z_IS_2492U_EQ_2492(...) \, +#define Z_IS_2492_EQ_2492U(...) \, +#define Z_IS_2492U_EQ_2492U(...) \, +#define Z_IS_2493_EQ_2493(...) \, +#define Z_IS_2493U_EQ_2493(...) \, +#define Z_IS_2493_EQ_2493U(...) \, +#define Z_IS_2493U_EQ_2493U(...) \, +#define Z_IS_2494_EQ_2494(...) \, +#define Z_IS_2494U_EQ_2494(...) \, +#define Z_IS_2494_EQ_2494U(...) \, +#define Z_IS_2494U_EQ_2494U(...) \, +#define Z_IS_2495_EQ_2495(...) \, +#define Z_IS_2495U_EQ_2495(...) \, +#define Z_IS_2495_EQ_2495U(...) \, +#define Z_IS_2495U_EQ_2495U(...) \, +#define Z_IS_2496_EQ_2496(...) \, +#define Z_IS_2496U_EQ_2496(...) \, +#define Z_IS_2496_EQ_2496U(...) \, +#define Z_IS_2496U_EQ_2496U(...) \, +#define Z_IS_2497_EQ_2497(...) \, +#define Z_IS_2497U_EQ_2497(...) \, +#define Z_IS_2497_EQ_2497U(...) \, +#define Z_IS_2497U_EQ_2497U(...) \, +#define Z_IS_2498_EQ_2498(...) \, +#define Z_IS_2498U_EQ_2498(...) \, +#define Z_IS_2498_EQ_2498U(...) \, +#define Z_IS_2498U_EQ_2498U(...) \, +#define Z_IS_2499_EQ_2499(...) \, +#define Z_IS_2499U_EQ_2499(...) \, +#define Z_IS_2499_EQ_2499U(...) \, +#define Z_IS_2499U_EQ_2499U(...) \, +#define Z_IS_2500_EQ_2500(...) \, +#define Z_IS_2500U_EQ_2500(...) \, +#define Z_IS_2500_EQ_2500U(...) \, +#define Z_IS_2500U_EQ_2500U(...) \, +#define Z_IS_2501_EQ_2501(...) \, +#define Z_IS_2501U_EQ_2501(...) \, +#define Z_IS_2501_EQ_2501U(...) \, +#define Z_IS_2501U_EQ_2501U(...) \, +#define Z_IS_2502_EQ_2502(...) \, +#define Z_IS_2502U_EQ_2502(...) \, +#define Z_IS_2502_EQ_2502U(...) \, +#define Z_IS_2502U_EQ_2502U(...) \, +#define Z_IS_2503_EQ_2503(...) \, +#define Z_IS_2503U_EQ_2503(...) \, +#define Z_IS_2503_EQ_2503U(...) \, +#define Z_IS_2503U_EQ_2503U(...) \, +#define Z_IS_2504_EQ_2504(...) \, +#define Z_IS_2504U_EQ_2504(...) \, +#define Z_IS_2504_EQ_2504U(...) \, +#define Z_IS_2504U_EQ_2504U(...) \, +#define Z_IS_2505_EQ_2505(...) \, +#define Z_IS_2505U_EQ_2505(...) \, +#define Z_IS_2505_EQ_2505U(...) \, +#define Z_IS_2505U_EQ_2505U(...) \, +#define Z_IS_2506_EQ_2506(...) \, +#define Z_IS_2506U_EQ_2506(...) \, +#define Z_IS_2506_EQ_2506U(...) \, +#define Z_IS_2506U_EQ_2506U(...) \, +#define Z_IS_2507_EQ_2507(...) \, +#define Z_IS_2507U_EQ_2507(...) \, +#define Z_IS_2507_EQ_2507U(...) \, +#define Z_IS_2507U_EQ_2507U(...) \, +#define Z_IS_2508_EQ_2508(...) \, +#define Z_IS_2508U_EQ_2508(...) \, +#define Z_IS_2508_EQ_2508U(...) \, +#define Z_IS_2508U_EQ_2508U(...) \, +#define Z_IS_2509_EQ_2509(...) \, +#define Z_IS_2509U_EQ_2509(...) \, +#define Z_IS_2509_EQ_2509U(...) \, +#define Z_IS_2509U_EQ_2509U(...) \, +#define Z_IS_2510_EQ_2510(...) \, +#define Z_IS_2510U_EQ_2510(...) \, +#define Z_IS_2510_EQ_2510U(...) \, +#define Z_IS_2510U_EQ_2510U(...) \, +#define Z_IS_2511_EQ_2511(...) \, +#define Z_IS_2511U_EQ_2511(...) \, +#define Z_IS_2511_EQ_2511U(...) \, +#define Z_IS_2511U_EQ_2511U(...) \, +#define Z_IS_2512_EQ_2512(...) \, +#define Z_IS_2512U_EQ_2512(...) \, +#define Z_IS_2512_EQ_2512U(...) \, +#define Z_IS_2512U_EQ_2512U(...) \, +#define Z_IS_2513_EQ_2513(...) \, +#define Z_IS_2513U_EQ_2513(...) \, +#define Z_IS_2513_EQ_2513U(...) \, +#define Z_IS_2513U_EQ_2513U(...) \, +#define Z_IS_2514_EQ_2514(...) \, +#define Z_IS_2514U_EQ_2514(...) \, +#define Z_IS_2514_EQ_2514U(...) \, +#define Z_IS_2514U_EQ_2514U(...) \, +#define Z_IS_2515_EQ_2515(...) \, +#define Z_IS_2515U_EQ_2515(...) \, +#define Z_IS_2515_EQ_2515U(...) \, +#define Z_IS_2515U_EQ_2515U(...) \, +#define Z_IS_2516_EQ_2516(...) \, +#define Z_IS_2516U_EQ_2516(...) \, +#define Z_IS_2516_EQ_2516U(...) \, +#define Z_IS_2516U_EQ_2516U(...) \, +#define Z_IS_2517_EQ_2517(...) \, +#define Z_IS_2517U_EQ_2517(...) \, +#define Z_IS_2517_EQ_2517U(...) \, +#define Z_IS_2517U_EQ_2517U(...) \, +#define Z_IS_2518_EQ_2518(...) \, +#define Z_IS_2518U_EQ_2518(...) \, +#define Z_IS_2518_EQ_2518U(...) \, +#define Z_IS_2518U_EQ_2518U(...) \, +#define Z_IS_2519_EQ_2519(...) \, +#define Z_IS_2519U_EQ_2519(...) \, +#define Z_IS_2519_EQ_2519U(...) \, +#define Z_IS_2519U_EQ_2519U(...) \, +#define Z_IS_2520_EQ_2520(...) \, +#define Z_IS_2520U_EQ_2520(...) \, +#define Z_IS_2520_EQ_2520U(...) \, +#define Z_IS_2520U_EQ_2520U(...) \, +#define Z_IS_2521_EQ_2521(...) \, +#define Z_IS_2521U_EQ_2521(...) \, +#define Z_IS_2521_EQ_2521U(...) \, +#define Z_IS_2521U_EQ_2521U(...) \, +#define Z_IS_2522_EQ_2522(...) \, +#define Z_IS_2522U_EQ_2522(...) \, +#define Z_IS_2522_EQ_2522U(...) \, +#define Z_IS_2522U_EQ_2522U(...) \, +#define Z_IS_2523_EQ_2523(...) \, +#define Z_IS_2523U_EQ_2523(...) \, +#define Z_IS_2523_EQ_2523U(...) \, +#define Z_IS_2523U_EQ_2523U(...) \, +#define Z_IS_2524_EQ_2524(...) \, +#define Z_IS_2524U_EQ_2524(...) \, +#define Z_IS_2524_EQ_2524U(...) \, +#define Z_IS_2524U_EQ_2524U(...) \, +#define Z_IS_2525_EQ_2525(...) \, +#define Z_IS_2525U_EQ_2525(...) \, +#define Z_IS_2525_EQ_2525U(...) \, +#define Z_IS_2525U_EQ_2525U(...) \, +#define Z_IS_2526_EQ_2526(...) \, +#define Z_IS_2526U_EQ_2526(...) \, +#define Z_IS_2526_EQ_2526U(...) \, +#define Z_IS_2526U_EQ_2526U(...) \, +#define Z_IS_2527_EQ_2527(...) \, +#define Z_IS_2527U_EQ_2527(...) \, +#define Z_IS_2527_EQ_2527U(...) \, +#define Z_IS_2527U_EQ_2527U(...) \, +#define Z_IS_2528_EQ_2528(...) \, +#define Z_IS_2528U_EQ_2528(...) \, +#define Z_IS_2528_EQ_2528U(...) \, +#define Z_IS_2528U_EQ_2528U(...) \, +#define Z_IS_2529_EQ_2529(...) \, +#define Z_IS_2529U_EQ_2529(...) \, +#define Z_IS_2529_EQ_2529U(...) \, +#define Z_IS_2529U_EQ_2529U(...) \, +#define Z_IS_2530_EQ_2530(...) \, +#define Z_IS_2530U_EQ_2530(...) \, +#define Z_IS_2530_EQ_2530U(...) \, +#define Z_IS_2530U_EQ_2530U(...) \, +#define Z_IS_2531_EQ_2531(...) \, +#define Z_IS_2531U_EQ_2531(...) \, +#define Z_IS_2531_EQ_2531U(...) \, +#define Z_IS_2531U_EQ_2531U(...) \, +#define Z_IS_2532_EQ_2532(...) \, +#define Z_IS_2532U_EQ_2532(...) \, +#define Z_IS_2532_EQ_2532U(...) \, +#define Z_IS_2532U_EQ_2532U(...) \, +#define Z_IS_2533_EQ_2533(...) \, +#define Z_IS_2533U_EQ_2533(...) \, +#define Z_IS_2533_EQ_2533U(...) \, +#define Z_IS_2533U_EQ_2533U(...) \, +#define Z_IS_2534_EQ_2534(...) \, +#define Z_IS_2534U_EQ_2534(...) \, +#define Z_IS_2534_EQ_2534U(...) \, +#define Z_IS_2534U_EQ_2534U(...) \, +#define Z_IS_2535_EQ_2535(...) \, +#define Z_IS_2535U_EQ_2535(...) \, +#define Z_IS_2535_EQ_2535U(...) \, +#define Z_IS_2535U_EQ_2535U(...) \, +#define Z_IS_2536_EQ_2536(...) \, +#define Z_IS_2536U_EQ_2536(...) \, +#define Z_IS_2536_EQ_2536U(...) \, +#define Z_IS_2536U_EQ_2536U(...) \, +#define Z_IS_2537_EQ_2537(...) \, +#define Z_IS_2537U_EQ_2537(...) \, +#define Z_IS_2537_EQ_2537U(...) \, +#define Z_IS_2537U_EQ_2537U(...) \, +#define Z_IS_2538_EQ_2538(...) \, +#define Z_IS_2538U_EQ_2538(...) \, +#define Z_IS_2538_EQ_2538U(...) \, +#define Z_IS_2538U_EQ_2538U(...) \, +#define Z_IS_2539_EQ_2539(...) \, +#define Z_IS_2539U_EQ_2539(...) \, +#define Z_IS_2539_EQ_2539U(...) \, +#define Z_IS_2539U_EQ_2539U(...) \, +#define Z_IS_2540_EQ_2540(...) \, +#define Z_IS_2540U_EQ_2540(...) \, +#define Z_IS_2540_EQ_2540U(...) \, +#define Z_IS_2540U_EQ_2540U(...) \, +#define Z_IS_2541_EQ_2541(...) \, +#define Z_IS_2541U_EQ_2541(...) \, +#define Z_IS_2541_EQ_2541U(...) \, +#define Z_IS_2541U_EQ_2541U(...) \, +#define Z_IS_2542_EQ_2542(...) \, +#define Z_IS_2542U_EQ_2542(...) \, +#define Z_IS_2542_EQ_2542U(...) \, +#define Z_IS_2542U_EQ_2542U(...) \, +#define Z_IS_2543_EQ_2543(...) \, +#define Z_IS_2543U_EQ_2543(...) \, +#define Z_IS_2543_EQ_2543U(...) \, +#define Z_IS_2543U_EQ_2543U(...) \, +#define Z_IS_2544_EQ_2544(...) \, +#define Z_IS_2544U_EQ_2544(...) \, +#define Z_IS_2544_EQ_2544U(...) \, +#define Z_IS_2544U_EQ_2544U(...) \, +#define Z_IS_2545_EQ_2545(...) \, +#define Z_IS_2545U_EQ_2545(...) \, +#define Z_IS_2545_EQ_2545U(...) \, +#define Z_IS_2545U_EQ_2545U(...) \, +#define Z_IS_2546_EQ_2546(...) \, +#define Z_IS_2546U_EQ_2546(...) \, +#define Z_IS_2546_EQ_2546U(...) \, +#define Z_IS_2546U_EQ_2546U(...) \, +#define Z_IS_2547_EQ_2547(...) \, +#define Z_IS_2547U_EQ_2547(...) \, +#define Z_IS_2547_EQ_2547U(...) \, +#define Z_IS_2547U_EQ_2547U(...) \, +#define Z_IS_2548_EQ_2548(...) \, +#define Z_IS_2548U_EQ_2548(...) \, +#define Z_IS_2548_EQ_2548U(...) \, +#define Z_IS_2548U_EQ_2548U(...) \, +#define Z_IS_2549_EQ_2549(...) \, +#define Z_IS_2549U_EQ_2549(...) \, +#define Z_IS_2549_EQ_2549U(...) \, +#define Z_IS_2549U_EQ_2549U(...) \, +#define Z_IS_2550_EQ_2550(...) \, +#define Z_IS_2550U_EQ_2550(...) \, +#define Z_IS_2550_EQ_2550U(...) \, +#define Z_IS_2550U_EQ_2550U(...) \, +#define Z_IS_2551_EQ_2551(...) \, +#define Z_IS_2551U_EQ_2551(...) \, +#define Z_IS_2551_EQ_2551U(...) \, +#define Z_IS_2551U_EQ_2551U(...) \, +#define Z_IS_2552_EQ_2552(...) \, +#define Z_IS_2552U_EQ_2552(...) \, +#define Z_IS_2552_EQ_2552U(...) \, +#define Z_IS_2552U_EQ_2552U(...) \, +#define Z_IS_2553_EQ_2553(...) \, +#define Z_IS_2553U_EQ_2553(...) \, +#define Z_IS_2553_EQ_2553U(...) \, +#define Z_IS_2553U_EQ_2553U(...) \, +#define Z_IS_2554_EQ_2554(...) \, +#define Z_IS_2554U_EQ_2554(...) \, +#define Z_IS_2554_EQ_2554U(...) \, +#define Z_IS_2554U_EQ_2554U(...) \, +#define Z_IS_2555_EQ_2555(...) \, +#define Z_IS_2555U_EQ_2555(...) \, +#define Z_IS_2555_EQ_2555U(...) \, +#define Z_IS_2555U_EQ_2555U(...) \, +#define Z_IS_2556_EQ_2556(...) \, +#define Z_IS_2556U_EQ_2556(...) \, +#define Z_IS_2556_EQ_2556U(...) \, +#define Z_IS_2556U_EQ_2556U(...) \, +#define Z_IS_2557_EQ_2557(...) \, +#define Z_IS_2557U_EQ_2557(...) \, +#define Z_IS_2557_EQ_2557U(...) \, +#define Z_IS_2557U_EQ_2557U(...) \, +#define Z_IS_2558_EQ_2558(...) \, +#define Z_IS_2558U_EQ_2558(...) \, +#define Z_IS_2558_EQ_2558U(...) \, +#define Z_IS_2558U_EQ_2558U(...) \, +#define Z_IS_2559_EQ_2559(...) \, +#define Z_IS_2559U_EQ_2559(...) \, +#define Z_IS_2559_EQ_2559U(...) \, +#define Z_IS_2559U_EQ_2559U(...) \, +#define Z_IS_2560_EQ_2560(...) \, +#define Z_IS_2560U_EQ_2560(...) \, +#define Z_IS_2560_EQ_2560U(...) \, +#define Z_IS_2560U_EQ_2560U(...) \, +#define Z_IS_2561_EQ_2561(...) \, +#define Z_IS_2561U_EQ_2561(...) \, +#define Z_IS_2561_EQ_2561U(...) \, +#define Z_IS_2561U_EQ_2561U(...) \, +#define Z_IS_2562_EQ_2562(...) \, +#define Z_IS_2562U_EQ_2562(...) \, +#define Z_IS_2562_EQ_2562U(...) \, +#define Z_IS_2562U_EQ_2562U(...) \, +#define Z_IS_2563_EQ_2563(...) \, +#define Z_IS_2563U_EQ_2563(...) \, +#define Z_IS_2563_EQ_2563U(...) \, +#define Z_IS_2563U_EQ_2563U(...) \, +#define Z_IS_2564_EQ_2564(...) \, +#define Z_IS_2564U_EQ_2564(...) \, +#define Z_IS_2564_EQ_2564U(...) \, +#define Z_IS_2564U_EQ_2564U(...) \, +#define Z_IS_2565_EQ_2565(...) \, +#define Z_IS_2565U_EQ_2565(...) \, +#define Z_IS_2565_EQ_2565U(...) \, +#define Z_IS_2565U_EQ_2565U(...) \, +#define Z_IS_2566_EQ_2566(...) \, +#define Z_IS_2566U_EQ_2566(...) \, +#define Z_IS_2566_EQ_2566U(...) \, +#define Z_IS_2566U_EQ_2566U(...) \, +#define Z_IS_2567_EQ_2567(...) \, +#define Z_IS_2567U_EQ_2567(...) \, +#define Z_IS_2567_EQ_2567U(...) \, +#define Z_IS_2567U_EQ_2567U(...) \, +#define Z_IS_2568_EQ_2568(...) \, +#define Z_IS_2568U_EQ_2568(...) \, +#define Z_IS_2568_EQ_2568U(...) \, +#define Z_IS_2568U_EQ_2568U(...) \, +#define Z_IS_2569_EQ_2569(...) \, +#define Z_IS_2569U_EQ_2569(...) \, +#define Z_IS_2569_EQ_2569U(...) \, +#define Z_IS_2569U_EQ_2569U(...) \, +#define Z_IS_2570_EQ_2570(...) \, +#define Z_IS_2570U_EQ_2570(...) \, +#define Z_IS_2570_EQ_2570U(...) \, +#define Z_IS_2570U_EQ_2570U(...) \, +#define Z_IS_2571_EQ_2571(...) \, +#define Z_IS_2571U_EQ_2571(...) \, +#define Z_IS_2571_EQ_2571U(...) \, +#define Z_IS_2571U_EQ_2571U(...) \, +#define Z_IS_2572_EQ_2572(...) \, +#define Z_IS_2572U_EQ_2572(...) \, +#define Z_IS_2572_EQ_2572U(...) \, +#define Z_IS_2572U_EQ_2572U(...) \, +#define Z_IS_2573_EQ_2573(...) \, +#define Z_IS_2573U_EQ_2573(...) \, +#define Z_IS_2573_EQ_2573U(...) \, +#define Z_IS_2573U_EQ_2573U(...) \, +#define Z_IS_2574_EQ_2574(...) \, +#define Z_IS_2574U_EQ_2574(...) \, +#define Z_IS_2574_EQ_2574U(...) \, +#define Z_IS_2574U_EQ_2574U(...) \, +#define Z_IS_2575_EQ_2575(...) \, +#define Z_IS_2575U_EQ_2575(...) \, +#define Z_IS_2575_EQ_2575U(...) \, +#define Z_IS_2575U_EQ_2575U(...) \, +#define Z_IS_2576_EQ_2576(...) \, +#define Z_IS_2576U_EQ_2576(...) \, +#define Z_IS_2576_EQ_2576U(...) \, +#define Z_IS_2576U_EQ_2576U(...) \, +#define Z_IS_2577_EQ_2577(...) \, +#define Z_IS_2577U_EQ_2577(...) \, +#define Z_IS_2577_EQ_2577U(...) \, +#define Z_IS_2577U_EQ_2577U(...) \, +#define Z_IS_2578_EQ_2578(...) \, +#define Z_IS_2578U_EQ_2578(...) \, +#define Z_IS_2578_EQ_2578U(...) \, +#define Z_IS_2578U_EQ_2578U(...) \, +#define Z_IS_2579_EQ_2579(...) \, +#define Z_IS_2579U_EQ_2579(...) \, +#define Z_IS_2579_EQ_2579U(...) \, +#define Z_IS_2579U_EQ_2579U(...) \, +#define Z_IS_2580_EQ_2580(...) \, +#define Z_IS_2580U_EQ_2580(...) \, +#define Z_IS_2580_EQ_2580U(...) \, +#define Z_IS_2580U_EQ_2580U(...) \, +#define Z_IS_2581_EQ_2581(...) \, +#define Z_IS_2581U_EQ_2581(...) \, +#define Z_IS_2581_EQ_2581U(...) \, +#define Z_IS_2581U_EQ_2581U(...) \, +#define Z_IS_2582_EQ_2582(...) \, +#define Z_IS_2582U_EQ_2582(...) \, +#define Z_IS_2582_EQ_2582U(...) \, +#define Z_IS_2582U_EQ_2582U(...) \, +#define Z_IS_2583_EQ_2583(...) \, +#define Z_IS_2583U_EQ_2583(...) \, +#define Z_IS_2583_EQ_2583U(...) \, +#define Z_IS_2583U_EQ_2583U(...) \, +#define Z_IS_2584_EQ_2584(...) \, +#define Z_IS_2584U_EQ_2584(...) \, +#define Z_IS_2584_EQ_2584U(...) \, +#define Z_IS_2584U_EQ_2584U(...) \, +#define Z_IS_2585_EQ_2585(...) \, +#define Z_IS_2585U_EQ_2585(...) \, +#define Z_IS_2585_EQ_2585U(...) \, +#define Z_IS_2585U_EQ_2585U(...) \, +#define Z_IS_2586_EQ_2586(...) \, +#define Z_IS_2586U_EQ_2586(...) \, +#define Z_IS_2586_EQ_2586U(...) \, +#define Z_IS_2586U_EQ_2586U(...) \, +#define Z_IS_2587_EQ_2587(...) \, +#define Z_IS_2587U_EQ_2587(...) \, +#define Z_IS_2587_EQ_2587U(...) \, +#define Z_IS_2587U_EQ_2587U(...) \, +#define Z_IS_2588_EQ_2588(...) \, +#define Z_IS_2588U_EQ_2588(...) \, +#define Z_IS_2588_EQ_2588U(...) \, +#define Z_IS_2588U_EQ_2588U(...) \, +#define Z_IS_2589_EQ_2589(...) \, +#define Z_IS_2589U_EQ_2589(...) \, +#define Z_IS_2589_EQ_2589U(...) \, +#define Z_IS_2589U_EQ_2589U(...) \, +#define Z_IS_2590_EQ_2590(...) \, +#define Z_IS_2590U_EQ_2590(...) \, +#define Z_IS_2590_EQ_2590U(...) \, +#define Z_IS_2590U_EQ_2590U(...) \, +#define Z_IS_2591_EQ_2591(...) \, +#define Z_IS_2591U_EQ_2591(...) \, +#define Z_IS_2591_EQ_2591U(...) \, +#define Z_IS_2591U_EQ_2591U(...) \, +#define Z_IS_2592_EQ_2592(...) \, +#define Z_IS_2592U_EQ_2592(...) \, +#define Z_IS_2592_EQ_2592U(...) \, +#define Z_IS_2592U_EQ_2592U(...) \, +#define Z_IS_2593_EQ_2593(...) \, +#define Z_IS_2593U_EQ_2593(...) \, +#define Z_IS_2593_EQ_2593U(...) \, +#define Z_IS_2593U_EQ_2593U(...) \, +#define Z_IS_2594_EQ_2594(...) \, +#define Z_IS_2594U_EQ_2594(...) \, +#define Z_IS_2594_EQ_2594U(...) \, +#define Z_IS_2594U_EQ_2594U(...) \, +#define Z_IS_2595_EQ_2595(...) \, +#define Z_IS_2595U_EQ_2595(...) \, +#define Z_IS_2595_EQ_2595U(...) \, +#define Z_IS_2595U_EQ_2595U(...) \, +#define Z_IS_2596_EQ_2596(...) \, +#define Z_IS_2596U_EQ_2596(...) \, +#define Z_IS_2596_EQ_2596U(...) \, +#define Z_IS_2596U_EQ_2596U(...) \, +#define Z_IS_2597_EQ_2597(...) \, +#define Z_IS_2597U_EQ_2597(...) \, +#define Z_IS_2597_EQ_2597U(...) \, +#define Z_IS_2597U_EQ_2597U(...) \, +#define Z_IS_2598_EQ_2598(...) \, +#define Z_IS_2598U_EQ_2598(...) \, +#define Z_IS_2598_EQ_2598U(...) \, +#define Z_IS_2598U_EQ_2598U(...) \, +#define Z_IS_2599_EQ_2599(...) \, +#define Z_IS_2599U_EQ_2599(...) \, +#define Z_IS_2599_EQ_2599U(...) \, +#define Z_IS_2599U_EQ_2599U(...) \, +#define Z_IS_2600_EQ_2600(...) \, +#define Z_IS_2600U_EQ_2600(...) \, +#define Z_IS_2600_EQ_2600U(...) \, +#define Z_IS_2600U_EQ_2600U(...) \, +#define Z_IS_2601_EQ_2601(...) \, +#define Z_IS_2601U_EQ_2601(...) \, +#define Z_IS_2601_EQ_2601U(...) \, +#define Z_IS_2601U_EQ_2601U(...) \, +#define Z_IS_2602_EQ_2602(...) \, +#define Z_IS_2602U_EQ_2602(...) \, +#define Z_IS_2602_EQ_2602U(...) \, +#define Z_IS_2602U_EQ_2602U(...) \, +#define Z_IS_2603_EQ_2603(...) \, +#define Z_IS_2603U_EQ_2603(...) \, +#define Z_IS_2603_EQ_2603U(...) \, +#define Z_IS_2603U_EQ_2603U(...) \, +#define Z_IS_2604_EQ_2604(...) \, +#define Z_IS_2604U_EQ_2604(...) \, +#define Z_IS_2604_EQ_2604U(...) \, +#define Z_IS_2604U_EQ_2604U(...) \, +#define Z_IS_2605_EQ_2605(...) \, +#define Z_IS_2605U_EQ_2605(...) \, +#define Z_IS_2605_EQ_2605U(...) \, +#define Z_IS_2605U_EQ_2605U(...) \, +#define Z_IS_2606_EQ_2606(...) \, +#define Z_IS_2606U_EQ_2606(...) \, +#define Z_IS_2606_EQ_2606U(...) \, +#define Z_IS_2606U_EQ_2606U(...) \, +#define Z_IS_2607_EQ_2607(...) \, +#define Z_IS_2607U_EQ_2607(...) \, +#define Z_IS_2607_EQ_2607U(...) \, +#define Z_IS_2607U_EQ_2607U(...) \, +#define Z_IS_2608_EQ_2608(...) \, +#define Z_IS_2608U_EQ_2608(...) \, +#define Z_IS_2608_EQ_2608U(...) \, +#define Z_IS_2608U_EQ_2608U(...) \, +#define Z_IS_2609_EQ_2609(...) \, +#define Z_IS_2609U_EQ_2609(...) \, +#define Z_IS_2609_EQ_2609U(...) \, +#define Z_IS_2609U_EQ_2609U(...) \, +#define Z_IS_2610_EQ_2610(...) \, +#define Z_IS_2610U_EQ_2610(...) \, +#define Z_IS_2610_EQ_2610U(...) \, +#define Z_IS_2610U_EQ_2610U(...) \, +#define Z_IS_2611_EQ_2611(...) \, +#define Z_IS_2611U_EQ_2611(...) \, +#define Z_IS_2611_EQ_2611U(...) \, +#define Z_IS_2611U_EQ_2611U(...) \, +#define Z_IS_2612_EQ_2612(...) \, +#define Z_IS_2612U_EQ_2612(...) \, +#define Z_IS_2612_EQ_2612U(...) \, +#define Z_IS_2612U_EQ_2612U(...) \, +#define Z_IS_2613_EQ_2613(...) \, +#define Z_IS_2613U_EQ_2613(...) \, +#define Z_IS_2613_EQ_2613U(...) \, +#define Z_IS_2613U_EQ_2613U(...) \, +#define Z_IS_2614_EQ_2614(...) \, +#define Z_IS_2614U_EQ_2614(...) \, +#define Z_IS_2614_EQ_2614U(...) \, +#define Z_IS_2614U_EQ_2614U(...) \, +#define Z_IS_2615_EQ_2615(...) \, +#define Z_IS_2615U_EQ_2615(...) \, +#define Z_IS_2615_EQ_2615U(...) \, +#define Z_IS_2615U_EQ_2615U(...) \, +#define Z_IS_2616_EQ_2616(...) \, +#define Z_IS_2616U_EQ_2616(...) \, +#define Z_IS_2616_EQ_2616U(...) \, +#define Z_IS_2616U_EQ_2616U(...) \, +#define Z_IS_2617_EQ_2617(...) \, +#define Z_IS_2617U_EQ_2617(...) \, +#define Z_IS_2617_EQ_2617U(...) \, +#define Z_IS_2617U_EQ_2617U(...) \, +#define Z_IS_2618_EQ_2618(...) \, +#define Z_IS_2618U_EQ_2618(...) \, +#define Z_IS_2618_EQ_2618U(...) \, +#define Z_IS_2618U_EQ_2618U(...) \, +#define Z_IS_2619_EQ_2619(...) \, +#define Z_IS_2619U_EQ_2619(...) \, +#define Z_IS_2619_EQ_2619U(...) \, +#define Z_IS_2619U_EQ_2619U(...) \, +#define Z_IS_2620_EQ_2620(...) \, +#define Z_IS_2620U_EQ_2620(...) \, +#define Z_IS_2620_EQ_2620U(...) \, +#define Z_IS_2620U_EQ_2620U(...) \, +#define Z_IS_2621_EQ_2621(...) \, +#define Z_IS_2621U_EQ_2621(...) \, +#define Z_IS_2621_EQ_2621U(...) \, +#define Z_IS_2621U_EQ_2621U(...) \, +#define Z_IS_2622_EQ_2622(...) \, +#define Z_IS_2622U_EQ_2622(...) \, +#define Z_IS_2622_EQ_2622U(...) \, +#define Z_IS_2622U_EQ_2622U(...) \, +#define Z_IS_2623_EQ_2623(...) \, +#define Z_IS_2623U_EQ_2623(...) \, +#define Z_IS_2623_EQ_2623U(...) \, +#define Z_IS_2623U_EQ_2623U(...) \, +#define Z_IS_2624_EQ_2624(...) \, +#define Z_IS_2624U_EQ_2624(...) \, +#define Z_IS_2624_EQ_2624U(...) \, +#define Z_IS_2624U_EQ_2624U(...) \, +#define Z_IS_2625_EQ_2625(...) \, +#define Z_IS_2625U_EQ_2625(...) \, +#define Z_IS_2625_EQ_2625U(...) \, +#define Z_IS_2625U_EQ_2625U(...) \, +#define Z_IS_2626_EQ_2626(...) \, +#define Z_IS_2626U_EQ_2626(...) \, +#define Z_IS_2626_EQ_2626U(...) \, +#define Z_IS_2626U_EQ_2626U(...) \, +#define Z_IS_2627_EQ_2627(...) \, +#define Z_IS_2627U_EQ_2627(...) \, +#define Z_IS_2627_EQ_2627U(...) \, +#define Z_IS_2627U_EQ_2627U(...) \, +#define Z_IS_2628_EQ_2628(...) \, +#define Z_IS_2628U_EQ_2628(...) \, +#define Z_IS_2628_EQ_2628U(...) \, +#define Z_IS_2628U_EQ_2628U(...) \, +#define Z_IS_2629_EQ_2629(...) \, +#define Z_IS_2629U_EQ_2629(...) \, +#define Z_IS_2629_EQ_2629U(...) \, +#define Z_IS_2629U_EQ_2629U(...) \, +#define Z_IS_2630_EQ_2630(...) \, +#define Z_IS_2630U_EQ_2630(...) \, +#define Z_IS_2630_EQ_2630U(...) \, +#define Z_IS_2630U_EQ_2630U(...) \, +#define Z_IS_2631_EQ_2631(...) \, +#define Z_IS_2631U_EQ_2631(...) \, +#define Z_IS_2631_EQ_2631U(...) \, +#define Z_IS_2631U_EQ_2631U(...) \, +#define Z_IS_2632_EQ_2632(...) \, +#define Z_IS_2632U_EQ_2632(...) \, +#define Z_IS_2632_EQ_2632U(...) \, +#define Z_IS_2632U_EQ_2632U(...) \, +#define Z_IS_2633_EQ_2633(...) \, +#define Z_IS_2633U_EQ_2633(...) \, +#define Z_IS_2633_EQ_2633U(...) \, +#define Z_IS_2633U_EQ_2633U(...) \, +#define Z_IS_2634_EQ_2634(...) \, +#define Z_IS_2634U_EQ_2634(...) \, +#define Z_IS_2634_EQ_2634U(...) \, +#define Z_IS_2634U_EQ_2634U(...) \, +#define Z_IS_2635_EQ_2635(...) \, +#define Z_IS_2635U_EQ_2635(...) \, +#define Z_IS_2635_EQ_2635U(...) \, +#define Z_IS_2635U_EQ_2635U(...) \, +#define Z_IS_2636_EQ_2636(...) \, +#define Z_IS_2636U_EQ_2636(...) \, +#define Z_IS_2636_EQ_2636U(...) \, +#define Z_IS_2636U_EQ_2636U(...) \, +#define Z_IS_2637_EQ_2637(...) \, +#define Z_IS_2637U_EQ_2637(...) \, +#define Z_IS_2637_EQ_2637U(...) \, +#define Z_IS_2637U_EQ_2637U(...) \, +#define Z_IS_2638_EQ_2638(...) \, +#define Z_IS_2638U_EQ_2638(...) \, +#define Z_IS_2638_EQ_2638U(...) \, +#define Z_IS_2638U_EQ_2638U(...) \, +#define Z_IS_2639_EQ_2639(...) \, +#define Z_IS_2639U_EQ_2639(...) \, +#define Z_IS_2639_EQ_2639U(...) \, +#define Z_IS_2639U_EQ_2639U(...) \, +#define Z_IS_2640_EQ_2640(...) \, +#define Z_IS_2640U_EQ_2640(...) \, +#define Z_IS_2640_EQ_2640U(...) \, +#define Z_IS_2640U_EQ_2640U(...) \, +#define Z_IS_2641_EQ_2641(...) \, +#define Z_IS_2641U_EQ_2641(...) \, +#define Z_IS_2641_EQ_2641U(...) \, +#define Z_IS_2641U_EQ_2641U(...) \, +#define Z_IS_2642_EQ_2642(...) \, +#define Z_IS_2642U_EQ_2642(...) \, +#define Z_IS_2642_EQ_2642U(...) \, +#define Z_IS_2642U_EQ_2642U(...) \, +#define Z_IS_2643_EQ_2643(...) \, +#define Z_IS_2643U_EQ_2643(...) \, +#define Z_IS_2643_EQ_2643U(...) \, +#define Z_IS_2643U_EQ_2643U(...) \, +#define Z_IS_2644_EQ_2644(...) \, +#define Z_IS_2644U_EQ_2644(...) \, +#define Z_IS_2644_EQ_2644U(...) \, +#define Z_IS_2644U_EQ_2644U(...) \, +#define Z_IS_2645_EQ_2645(...) \, +#define Z_IS_2645U_EQ_2645(...) \, +#define Z_IS_2645_EQ_2645U(...) \, +#define Z_IS_2645U_EQ_2645U(...) \, +#define Z_IS_2646_EQ_2646(...) \, +#define Z_IS_2646U_EQ_2646(...) \, +#define Z_IS_2646_EQ_2646U(...) \, +#define Z_IS_2646U_EQ_2646U(...) \, +#define Z_IS_2647_EQ_2647(...) \, +#define Z_IS_2647U_EQ_2647(...) \, +#define Z_IS_2647_EQ_2647U(...) \, +#define Z_IS_2647U_EQ_2647U(...) \, +#define Z_IS_2648_EQ_2648(...) \, +#define Z_IS_2648U_EQ_2648(...) \, +#define Z_IS_2648_EQ_2648U(...) \, +#define Z_IS_2648U_EQ_2648U(...) \, +#define Z_IS_2649_EQ_2649(...) \, +#define Z_IS_2649U_EQ_2649(...) \, +#define Z_IS_2649_EQ_2649U(...) \, +#define Z_IS_2649U_EQ_2649U(...) \, +#define Z_IS_2650_EQ_2650(...) \, +#define Z_IS_2650U_EQ_2650(...) \, +#define Z_IS_2650_EQ_2650U(...) \, +#define Z_IS_2650U_EQ_2650U(...) \, +#define Z_IS_2651_EQ_2651(...) \, +#define Z_IS_2651U_EQ_2651(...) \, +#define Z_IS_2651_EQ_2651U(...) \, +#define Z_IS_2651U_EQ_2651U(...) \, +#define Z_IS_2652_EQ_2652(...) \, +#define Z_IS_2652U_EQ_2652(...) \, +#define Z_IS_2652_EQ_2652U(...) \, +#define Z_IS_2652U_EQ_2652U(...) \, +#define Z_IS_2653_EQ_2653(...) \, +#define Z_IS_2653U_EQ_2653(...) \, +#define Z_IS_2653_EQ_2653U(...) \, +#define Z_IS_2653U_EQ_2653U(...) \, +#define Z_IS_2654_EQ_2654(...) \, +#define Z_IS_2654U_EQ_2654(...) \, +#define Z_IS_2654_EQ_2654U(...) \, +#define Z_IS_2654U_EQ_2654U(...) \, +#define Z_IS_2655_EQ_2655(...) \, +#define Z_IS_2655U_EQ_2655(...) \, +#define Z_IS_2655_EQ_2655U(...) \, +#define Z_IS_2655U_EQ_2655U(...) \, +#define Z_IS_2656_EQ_2656(...) \, +#define Z_IS_2656U_EQ_2656(...) \, +#define Z_IS_2656_EQ_2656U(...) \, +#define Z_IS_2656U_EQ_2656U(...) \, +#define Z_IS_2657_EQ_2657(...) \, +#define Z_IS_2657U_EQ_2657(...) \, +#define Z_IS_2657_EQ_2657U(...) \, +#define Z_IS_2657U_EQ_2657U(...) \, +#define Z_IS_2658_EQ_2658(...) \, +#define Z_IS_2658U_EQ_2658(...) \, +#define Z_IS_2658_EQ_2658U(...) \, +#define Z_IS_2658U_EQ_2658U(...) \, +#define Z_IS_2659_EQ_2659(...) \, +#define Z_IS_2659U_EQ_2659(...) \, +#define Z_IS_2659_EQ_2659U(...) \, +#define Z_IS_2659U_EQ_2659U(...) \, +#define Z_IS_2660_EQ_2660(...) \, +#define Z_IS_2660U_EQ_2660(...) \, +#define Z_IS_2660_EQ_2660U(...) \, +#define Z_IS_2660U_EQ_2660U(...) \, +#define Z_IS_2661_EQ_2661(...) \, +#define Z_IS_2661U_EQ_2661(...) \, +#define Z_IS_2661_EQ_2661U(...) \, +#define Z_IS_2661U_EQ_2661U(...) \, +#define Z_IS_2662_EQ_2662(...) \, +#define Z_IS_2662U_EQ_2662(...) \, +#define Z_IS_2662_EQ_2662U(...) \, +#define Z_IS_2662U_EQ_2662U(...) \, +#define Z_IS_2663_EQ_2663(...) \, +#define Z_IS_2663U_EQ_2663(...) \, +#define Z_IS_2663_EQ_2663U(...) \, +#define Z_IS_2663U_EQ_2663U(...) \, +#define Z_IS_2664_EQ_2664(...) \, +#define Z_IS_2664U_EQ_2664(...) \, +#define Z_IS_2664_EQ_2664U(...) \, +#define Z_IS_2664U_EQ_2664U(...) \, +#define Z_IS_2665_EQ_2665(...) \, +#define Z_IS_2665U_EQ_2665(...) \, +#define Z_IS_2665_EQ_2665U(...) \, +#define Z_IS_2665U_EQ_2665U(...) \, +#define Z_IS_2666_EQ_2666(...) \, +#define Z_IS_2666U_EQ_2666(...) \, +#define Z_IS_2666_EQ_2666U(...) \, +#define Z_IS_2666U_EQ_2666U(...) \, +#define Z_IS_2667_EQ_2667(...) \, +#define Z_IS_2667U_EQ_2667(...) \, +#define Z_IS_2667_EQ_2667U(...) \, +#define Z_IS_2667U_EQ_2667U(...) \, +#define Z_IS_2668_EQ_2668(...) \, +#define Z_IS_2668U_EQ_2668(...) \, +#define Z_IS_2668_EQ_2668U(...) \, +#define Z_IS_2668U_EQ_2668U(...) \, +#define Z_IS_2669_EQ_2669(...) \, +#define Z_IS_2669U_EQ_2669(...) \, +#define Z_IS_2669_EQ_2669U(...) \, +#define Z_IS_2669U_EQ_2669U(...) \, +#define Z_IS_2670_EQ_2670(...) \, +#define Z_IS_2670U_EQ_2670(...) \, +#define Z_IS_2670_EQ_2670U(...) \, +#define Z_IS_2670U_EQ_2670U(...) \, +#define Z_IS_2671_EQ_2671(...) \, +#define Z_IS_2671U_EQ_2671(...) \, +#define Z_IS_2671_EQ_2671U(...) \, +#define Z_IS_2671U_EQ_2671U(...) \, +#define Z_IS_2672_EQ_2672(...) \, +#define Z_IS_2672U_EQ_2672(...) \, +#define Z_IS_2672_EQ_2672U(...) \, +#define Z_IS_2672U_EQ_2672U(...) \, +#define Z_IS_2673_EQ_2673(...) \, +#define Z_IS_2673U_EQ_2673(...) \, +#define Z_IS_2673_EQ_2673U(...) \, +#define Z_IS_2673U_EQ_2673U(...) \, +#define Z_IS_2674_EQ_2674(...) \, +#define Z_IS_2674U_EQ_2674(...) \, +#define Z_IS_2674_EQ_2674U(...) \, +#define Z_IS_2674U_EQ_2674U(...) \, +#define Z_IS_2675_EQ_2675(...) \, +#define Z_IS_2675U_EQ_2675(...) \, +#define Z_IS_2675_EQ_2675U(...) \, +#define Z_IS_2675U_EQ_2675U(...) \, +#define Z_IS_2676_EQ_2676(...) \, +#define Z_IS_2676U_EQ_2676(...) \, +#define Z_IS_2676_EQ_2676U(...) \, +#define Z_IS_2676U_EQ_2676U(...) \, +#define Z_IS_2677_EQ_2677(...) \, +#define Z_IS_2677U_EQ_2677(...) \, +#define Z_IS_2677_EQ_2677U(...) \, +#define Z_IS_2677U_EQ_2677U(...) \, +#define Z_IS_2678_EQ_2678(...) \, +#define Z_IS_2678U_EQ_2678(...) \, +#define Z_IS_2678_EQ_2678U(...) \, +#define Z_IS_2678U_EQ_2678U(...) \, +#define Z_IS_2679_EQ_2679(...) \, +#define Z_IS_2679U_EQ_2679(...) \, +#define Z_IS_2679_EQ_2679U(...) \, +#define Z_IS_2679U_EQ_2679U(...) \, +#define Z_IS_2680_EQ_2680(...) \, +#define Z_IS_2680U_EQ_2680(...) \, +#define Z_IS_2680_EQ_2680U(...) \, +#define Z_IS_2680U_EQ_2680U(...) \, +#define Z_IS_2681_EQ_2681(...) \, +#define Z_IS_2681U_EQ_2681(...) \, +#define Z_IS_2681_EQ_2681U(...) \, +#define Z_IS_2681U_EQ_2681U(...) \, +#define Z_IS_2682_EQ_2682(...) \, +#define Z_IS_2682U_EQ_2682(...) \, +#define Z_IS_2682_EQ_2682U(...) \, +#define Z_IS_2682U_EQ_2682U(...) \, +#define Z_IS_2683_EQ_2683(...) \, +#define Z_IS_2683U_EQ_2683(...) \, +#define Z_IS_2683_EQ_2683U(...) \, +#define Z_IS_2683U_EQ_2683U(...) \, +#define Z_IS_2684_EQ_2684(...) \, +#define Z_IS_2684U_EQ_2684(...) \, +#define Z_IS_2684_EQ_2684U(...) \, +#define Z_IS_2684U_EQ_2684U(...) \, +#define Z_IS_2685_EQ_2685(...) \, +#define Z_IS_2685U_EQ_2685(...) \, +#define Z_IS_2685_EQ_2685U(...) \, +#define Z_IS_2685U_EQ_2685U(...) \, +#define Z_IS_2686_EQ_2686(...) \, +#define Z_IS_2686U_EQ_2686(...) \, +#define Z_IS_2686_EQ_2686U(...) \, +#define Z_IS_2686U_EQ_2686U(...) \, +#define Z_IS_2687_EQ_2687(...) \, +#define Z_IS_2687U_EQ_2687(...) \, +#define Z_IS_2687_EQ_2687U(...) \, +#define Z_IS_2687U_EQ_2687U(...) \, +#define Z_IS_2688_EQ_2688(...) \, +#define Z_IS_2688U_EQ_2688(...) \, +#define Z_IS_2688_EQ_2688U(...) \, +#define Z_IS_2688U_EQ_2688U(...) \, +#define Z_IS_2689_EQ_2689(...) \, +#define Z_IS_2689U_EQ_2689(...) \, +#define Z_IS_2689_EQ_2689U(...) \, +#define Z_IS_2689U_EQ_2689U(...) \, +#define Z_IS_2690_EQ_2690(...) \, +#define Z_IS_2690U_EQ_2690(...) \, +#define Z_IS_2690_EQ_2690U(...) \, +#define Z_IS_2690U_EQ_2690U(...) \, +#define Z_IS_2691_EQ_2691(...) \, +#define Z_IS_2691U_EQ_2691(...) \, +#define Z_IS_2691_EQ_2691U(...) \, +#define Z_IS_2691U_EQ_2691U(...) \, +#define Z_IS_2692_EQ_2692(...) \, +#define Z_IS_2692U_EQ_2692(...) \, +#define Z_IS_2692_EQ_2692U(...) \, +#define Z_IS_2692U_EQ_2692U(...) \, +#define Z_IS_2693_EQ_2693(...) \, +#define Z_IS_2693U_EQ_2693(...) \, +#define Z_IS_2693_EQ_2693U(...) \, +#define Z_IS_2693U_EQ_2693U(...) \, +#define Z_IS_2694_EQ_2694(...) \, +#define Z_IS_2694U_EQ_2694(...) \, +#define Z_IS_2694_EQ_2694U(...) \, +#define Z_IS_2694U_EQ_2694U(...) \, +#define Z_IS_2695_EQ_2695(...) \, +#define Z_IS_2695U_EQ_2695(...) \, +#define Z_IS_2695_EQ_2695U(...) \, +#define Z_IS_2695U_EQ_2695U(...) \, +#define Z_IS_2696_EQ_2696(...) \, +#define Z_IS_2696U_EQ_2696(...) \, +#define Z_IS_2696_EQ_2696U(...) \, +#define Z_IS_2696U_EQ_2696U(...) \, +#define Z_IS_2697_EQ_2697(...) \, +#define Z_IS_2697U_EQ_2697(...) \, +#define Z_IS_2697_EQ_2697U(...) \, +#define Z_IS_2697U_EQ_2697U(...) \, +#define Z_IS_2698_EQ_2698(...) \, +#define Z_IS_2698U_EQ_2698(...) \, +#define Z_IS_2698_EQ_2698U(...) \, +#define Z_IS_2698U_EQ_2698U(...) \, +#define Z_IS_2699_EQ_2699(...) \, +#define Z_IS_2699U_EQ_2699(...) \, +#define Z_IS_2699_EQ_2699U(...) \, +#define Z_IS_2699U_EQ_2699U(...) \, +#define Z_IS_2700_EQ_2700(...) \, +#define Z_IS_2700U_EQ_2700(...) \, +#define Z_IS_2700_EQ_2700U(...) \, +#define Z_IS_2700U_EQ_2700U(...) \, +#define Z_IS_2701_EQ_2701(...) \, +#define Z_IS_2701U_EQ_2701(...) \, +#define Z_IS_2701_EQ_2701U(...) \, +#define Z_IS_2701U_EQ_2701U(...) \, +#define Z_IS_2702_EQ_2702(...) \, +#define Z_IS_2702U_EQ_2702(...) \, +#define Z_IS_2702_EQ_2702U(...) \, +#define Z_IS_2702U_EQ_2702U(...) \, +#define Z_IS_2703_EQ_2703(...) \, +#define Z_IS_2703U_EQ_2703(...) \, +#define Z_IS_2703_EQ_2703U(...) \, +#define Z_IS_2703U_EQ_2703U(...) \, +#define Z_IS_2704_EQ_2704(...) \, +#define Z_IS_2704U_EQ_2704(...) \, +#define Z_IS_2704_EQ_2704U(...) \, +#define Z_IS_2704U_EQ_2704U(...) \, +#define Z_IS_2705_EQ_2705(...) \, +#define Z_IS_2705U_EQ_2705(...) \, +#define Z_IS_2705_EQ_2705U(...) \, +#define Z_IS_2705U_EQ_2705U(...) \, +#define Z_IS_2706_EQ_2706(...) \, +#define Z_IS_2706U_EQ_2706(...) \, +#define Z_IS_2706_EQ_2706U(...) \, +#define Z_IS_2706U_EQ_2706U(...) \, +#define Z_IS_2707_EQ_2707(...) \, +#define Z_IS_2707U_EQ_2707(...) \, +#define Z_IS_2707_EQ_2707U(...) \, +#define Z_IS_2707U_EQ_2707U(...) \, +#define Z_IS_2708_EQ_2708(...) \, +#define Z_IS_2708U_EQ_2708(...) \, +#define Z_IS_2708_EQ_2708U(...) \, +#define Z_IS_2708U_EQ_2708U(...) \, +#define Z_IS_2709_EQ_2709(...) \, +#define Z_IS_2709U_EQ_2709(...) \, +#define Z_IS_2709_EQ_2709U(...) \, +#define Z_IS_2709U_EQ_2709U(...) \, +#define Z_IS_2710_EQ_2710(...) \, +#define Z_IS_2710U_EQ_2710(...) \, +#define Z_IS_2710_EQ_2710U(...) \, +#define Z_IS_2710U_EQ_2710U(...) \, +#define Z_IS_2711_EQ_2711(...) \, +#define Z_IS_2711U_EQ_2711(...) \, +#define Z_IS_2711_EQ_2711U(...) \, +#define Z_IS_2711U_EQ_2711U(...) \, +#define Z_IS_2712_EQ_2712(...) \, +#define Z_IS_2712U_EQ_2712(...) \, +#define Z_IS_2712_EQ_2712U(...) \, +#define Z_IS_2712U_EQ_2712U(...) \, +#define Z_IS_2713_EQ_2713(...) \, +#define Z_IS_2713U_EQ_2713(...) \, +#define Z_IS_2713_EQ_2713U(...) \, +#define Z_IS_2713U_EQ_2713U(...) \, +#define Z_IS_2714_EQ_2714(...) \, +#define Z_IS_2714U_EQ_2714(...) \, +#define Z_IS_2714_EQ_2714U(...) \, +#define Z_IS_2714U_EQ_2714U(...) \, +#define Z_IS_2715_EQ_2715(...) \, +#define Z_IS_2715U_EQ_2715(...) \, +#define Z_IS_2715_EQ_2715U(...) \, +#define Z_IS_2715U_EQ_2715U(...) \, +#define Z_IS_2716_EQ_2716(...) \, +#define Z_IS_2716U_EQ_2716(...) \, +#define Z_IS_2716_EQ_2716U(...) \, +#define Z_IS_2716U_EQ_2716U(...) \, +#define Z_IS_2717_EQ_2717(...) \, +#define Z_IS_2717U_EQ_2717(...) \, +#define Z_IS_2717_EQ_2717U(...) \, +#define Z_IS_2717U_EQ_2717U(...) \, +#define Z_IS_2718_EQ_2718(...) \, +#define Z_IS_2718U_EQ_2718(...) \, +#define Z_IS_2718_EQ_2718U(...) \, +#define Z_IS_2718U_EQ_2718U(...) \, +#define Z_IS_2719_EQ_2719(...) \, +#define Z_IS_2719U_EQ_2719(...) \, +#define Z_IS_2719_EQ_2719U(...) \, +#define Z_IS_2719U_EQ_2719U(...) \, +#define Z_IS_2720_EQ_2720(...) \, +#define Z_IS_2720U_EQ_2720(...) \, +#define Z_IS_2720_EQ_2720U(...) \, +#define Z_IS_2720U_EQ_2720U(...) \, +#define Z_IS_2721_EQ_2721(...) \, +#define Z_IS_2721U_EQ_2721(...) \, +#define Z_IS_2721_EQ_2721U(...) \, +#define Z_IS_2721U_EQ_2721U(...) \, +#define Z_IS_2722_EQ_2722(...) \, +#define Z_IS_2722U_EQ_2722(...) \, +#define Z_IS_2722_EQ_2722U(...) \, +#define Z_IS_2722U_EQ_2722U(...) \, +#define Z_IS_2723_EQ_2723(...) \, +#define Z_IS_2723U_EQ_2723(...) \, +#define Z_IS_2723_EQ_2723U(...) \, +#define Z_IS_2723U_EQ_2723U(...) \, +#define Z_IS_2724_EQ_2724(...) \, +#define Z_IS_2724U_EQ_2724(...) \, +#define Z_IS_2724_EQ_2724U(...) \, +#define Z_IS_2724U_EQ_2724U(...) \, +#define Z_IS_2725_EQ_2725(...) \, +#define Z_IS_2725U_EQ_2725(...) \, +#define Z_IS_2725_EQ_2725U(...) \, +#define Z_IS_2725U_EQ_2725U(...) \, +#define Z_IS_2726_EQ_2726(...) \, +#define Z_IS_2726U_EQ_2726(...) \, +#define Z_IS_2726_EQ_2726U(...) \, +#define Z_IS_2726U_EQ_2726U(...) \, +#define Z_IS_2727_EQ_2727(...) \, +#define Z_IS_2727U_EQ_2727(...) \, +#define Z_IS_2727_EQ_2727U(...) \, +#define Z_IS_2727U_EQ_2727U(...) \, +#define Z_IS_2728_EQ_2728(...) \, +#define Z_IS_2728U_EQ_2728(...) \, +#define Z_IS_2728_EQ_2728U(...) \, +#define Z_IS_2728U_EQ_2728U(...) \, +#define Z_IS_2729_EQ_2729(...) \, +#define Z_IS_2729U_EQ_2729(...) \, +#define Z_IS_2729_EQ_2729U(...) \, +#define Z_IS_2729U_EQ_2729U(...) \, +#define Z_IS_2730_EQ_2730(...) \, +#define Z_IS_2730U_EQ_2730(...) \, +#define Z_IS_2730_EQ_2730U(...) \, +#define Z_IS_2730U_EQ_2730U(...) \, +#define Z_IS_2731_EQ_2731(...) \, +#define Z_IS_2731U_EQ_2731(...) \, +#define Z_IS_2731_EQ_2731U(...) \, +#define Z_IS_2731U_EQ_2731U(...) \, +#define Z_IS_2732_EQ_2732(...) \, +#define Z_IS_2732U_EQ_2732(...) \, +#define Z_IS_2732_EQ_2732U(...) \, +#define Z_IS_2732U_EQ_2732U(...) \, +#define Z_IS_2733_EQ_2733(...) \, +#define Z_IS_2733U_EQ_2733(...) \, +#define Z_IS_2733_EQ_2733U(...) \, +#define Z_IS_2733U_EQ_2733U(...) \, +#define Z_IS_2734_EQ_2734(...) \, +#define Z_IS_2734U_EQ_2734(...) \, +#define Z_IS_2734_EQ_2734U(...) \, +#define Z_IS_2734U_EQ_2734U(...) \, +#define Z_IS_2735_EQ_2735(...) \, +#define Z_IS_2735U_EQ_2735(...) \, +#define Z_IS_2735_EQ_2735U(...) \, +#define Z_IS_2735U_EQ_2735U(...) \, +#define Z_IS_2736_EQ_2736(...) \, +#define Z_IS_2736U_EQ_2736(...) \, +#define Z_IS_2736_EQ_2736U(...) \, +#define Z_IS_2736U_EQ_2736U(...) \, +#define Z_IS_2737_EQ_2737(...) \, +#define Z_IS_2737U_EQ_2737(...) \, +#define Z_IS_2737_EQ_2737U(...) \, +#define Z_IS_2737U_EQ_2737U(...) \, +#define Z_IS_2738_EQ_2738(...) \, +#define Z_IS_2738U_EQ_2738(...) \, +#define Z_IS_2738_EQ_2738U(...) \, +#define Z_IS_2738U_EQ_2738U(...) \, +#define Z_IS_2739_EQ_2739(...) \, +#define Z_IS_2739U_EQ_2739(...) \, +#define Z_IS_2739_EQ_2739U(...) \, +#define Z_IS_2739U_EQ_2739U(...) \, +#define Z_IS_2740_EQ_2740(...) \, +#define Z_IS_2740U_EQ_2740(...) \, +#define Z_IS_2740_EQ_2740U(...) \, +#define Z_IS_2740U_EQ_2740U(...) \, +#define Z_IS_2741_EQ_2741(...) \, +#define Z_IS_2741U_EQ_2741(...) \, +#define Z_IS_2741_EQ_2741U(...) \, +#define Z_IS_2741U_EQ_2741U(...) \, +#define Z_IS_2742_EQ_2742(...) \, +#define Z_IS_2742U_EQ_2742(...) \, +#define Z_IS_2742_EQ_2742U(...) \, +#define Z_IS_2742U_EQ_2742U(...) \, +#define Z_IS_2743_EQ_2743(...) \, +#define Z_IS_2743U_EQ_2743(...) \, +#define Z_IS_2743_EQ_2743U(...) \, +#define Z_IS_2743U_EQ_2743U(...) \, +#define Z_IS_2744_EQ_2744(...) \, +#define Z_IS_2744U_EQ_2744(...) \, +#define Z_IS_2744_EQ_2744U(...) \, +#define Z_IS_2744U_EQ_2744U(...) \, +#define Z_IS_2745_EQ_2745(...) \, +#define Z_IS_2745U_EQ_2745(...) \, +#define Z_IS_2745_EQ_2745U(...) \, +#define Z_IS_2745U_EQ_2745U(...) \, +#define Z_IS_2746_EQ_2746(...) \, +#define Z_IS_2746U_EQ_2746(...) \, +#define Z_IS_2746_EQ_2746U(...) \, +#define Z_IS_2746U_EQ_2746U(...) \, +#define Z_IS_2747_EQ_2747(...) \, +#define Z_IS_2747U_EQ_2747(...) \, +#define Z_IS_2747_EQ_2747U(...) \, +#define Z_IS_2747U_EQ_2747U(...) \, +#define Z_IS_2748_EQ_2748(...) \, +#define Z_IS_2748U_EQ_2748(...) \, +#define Z_IS_2748_EQ_2748U(...) \, +#define Z_IS_2748U_EQ_2748U(...) \, +#define Z_IS_2749_EQ_2749(...) \, +#define Z_IS_2749U_EQ_2749(...) \, +#define Z_IS_2749_EQ_2749U(...) \, +#define Z_IS_2749U_EQ_2749U(...) \, +#define Z_IS_2750_EQ_2750(...) \, +#define Z_IS_2750U_EQ_2750(...) \, +#define Z_IS_2750_EQ_2750U(...) \, +#define Z_IS_2750U_EQ_2750U(...) \, +#define Z_IS_2751_EQ_2751(...) \, +#define Z_IS_2751U_EQ_2751(...) \, +#define Z_IS_2751_EQ_2751U(...) \, +#define Z_IS_2751U_EQ_2751U(...) \, +#define Z_IS_2752_EQ_2752(...) \, +#define Z_IS_2752U_EQ_2752(...) \, +#define Z_IS_2752_EQ_2752U(...) \, +#define Z_IS_2752U_EQ_2752U(...) \, +#define Z_IS_2753_EQ_2753(...) \, +#define Z_IS_2753U_EQ_2753(...) \, +#define Z_IS_2753_EQ_2753U(...) \, +#define Z_IS_2753U_EQ_2753U(...) \, +#define Z_IS_2754_EQ_2754(...) \, +#define Z_IS_2754U_EQ_2754(...) \, +#define Z_IS_2754_EQ_2754U(...) \, +#define Z_IS_2754U_EQ_2754U(...) \, +#define Z_IS_2755_EQ_2755(...) \, +#define Z_IS_2755U_EQ_2755(...) \, +#define Z_IS_2755_EQ_2755U(...) \, +#define Z_IS_2755U_EQ_2755U(...) \, +#define Z_IS_2756_EQ_2756(...) \, +#define Z_IS_2756U_EQ_2756(...) \, +#define Z_IS_2756_EQ_2756U(...) \, +#define Z_IS_2756U_EQ_2756U(...) \, +#define Z_IS_2757_EQ_2757(...) \, +#define Z_IS_2757U_EQ_2757(...) \, +#define Z_IS_2757_EQ_2757U(...) \, +#define Z_IS_2757U_EQ_2757U(...) \, +#define Z_IS_2758_EQ_2758(...) \, +#define Z_IS_2758U_EQ_2758(...) \, +#define Z_IS_2758_EQ_2758U(...) \, +#define Z_IS_2758U_EQ_2758U(...) \, +#define Z_IS_2759_EQ_2759(...) \, +#define Z_IS_2759U_EQ_2759(...) \, +#define Z_IS_2759_EQ_2759U(...) \, +#define Z_IS_2759U_EQ_2759U(...) \, +#define Z_IS_2760_EQ_2760(...) \, +#define Z_IS_2760U_EQ_2760(...) \, +#define Z_IS_2760_EQ_2760U(...) \, +#define Z_IS_2760U_EQ_2760U(...) \, +#define Z_IS_2761_EQ_2761(...) \, +#define Z_IS_2761U_EQ_2761(...) \, +#define Z_IS_2761_EQ_2761U(...) \, +#define Z_IS_2761U_EQ_2761U(...) \, +#define Z_IS_2762_EQ_2762(...) \, +#define Z_IS_2762U_EQ_2762(...) \, +#define Z_IS_2762_EQ_2762U(...) \, +#define Z_IS_2762U_EQ_2762U(...) \, +#define Z_IS_2763_EQ_2763(...) \, +#define Z_IS_2763U_EQ_2763(...) \, +#define Z_IS_2763_EQ_2763U(...) \, +#define Z_IS_2763U_EQ_2763U(...) \, +#define Z_IS_2764_EQ_2764(...) \, +#define Z_IS_2764U_EQ_2764(...) \, +#define Z_IS_2764_EQ_2764U(...) \, +#define Z_IS_2764U_EQ_2764U(...) \, +#define Z_IS_2765_EQ_2765(...) \, +#define Z_IS_2765U_EQ_2765(...) \, +#define Z_IS_2765_EQ_2765U(...) \, +#define Z_IS_2765U_EQ_2765U(...) \, +#define Z_IS_2766_EQ_2766(...) \, +#define Z_IS_2766U_EQ_2766(...) \, +#define Z_IS_2766_EQ_2766U(...) \, +#define Z_IS_2766U_EQ_2766U(...) \, +#define Z_IS_2767_EQ_2767(...) \, +#define Z_IS_2767U_EQ_2767(...) \, +#define Z_IS_2767_EQ_2767U(...) \, +#define Z_IS_2767U_EQ_2767U(...) \, +#define Z_IS_2768_EQ_2768(...) \, +#define Z_IS_2768U_EQ_2768(...) \, +#define Z_IS_2768_EQ_2768U(...) \, +#define Z_IS_2768U_EQ_2768U(...) \, +#define Z_IS_2769_EQ_2769(...) \, +#define Z_IS_2769U_EQ_2769(...) \, +#define Z_IS_2769_EQ_2769U(...) \, +#define Z_IS_2769U_EQ_2769U(...) \, +#define Z_IS_2770_EQ_2770(...) \, +#define Z_IS_2770U_EQ_2770(...) \, +#define Z_IS_2770_EQ_2770U(...) \, +#define Z_IS_2770U_EQ_2770U(...) \, +#define Z_IS_2771_EQ_2771(...) \, +#define Z_IS_2771U_EQ_2771(...) \, +#define Z_IS_2771_EQ_2771U(...) \, +#define Z_IS_2771U_EQ_2771U(...) \, +#define Z_IS_2772_EQ_2772(...) \, +#define Z_IS_2772U_EQ_2772(...) \, +#define Z_IS_2772_EQ_2772U(...) \, +#define Z_IS_2772U_EQ_2772U(...) \, +#define Z_IS_2773_EQ_2773(...) \, +#define Z_IS_2773U_EQ_2773(...) \, +#define Z_IS_2773_EQ_2773U(...) \, +#define Z_IS_2773U_EQ_2773U(...) \, +#define Z_IS_2774_EQ_2774(...) \, +#define Z_IS_2774U_EQ_2774(...) \, +#define Z_IS_2774_EQ_2774U(...) \, +#define Z_IS_2774U_EQ_2774U(...) \, +#define Z_IS_2775_EQ_2775(...) \, +#define Z_IS_2775U_EQ_2775(...) \, +#define Z_IS_2775_EQ_2775U(...) \, +#define Z_IS_2775U_EQ_2775U(...) \, +#define Z_IS_2776_EQ_2776(...) \, +#define Z_IS_2776U_EQ_2776(...) \, +#define Z_IS_2776_EQ_2776U(...) \, +#define Z_IS_2776U_EQ_2776U(...) \, +#define Z_IS_2777_EQ_2777(...) \, +#define Z_IS_2777U_EQ_2777(...) \, +#define Z_IS_2777_EQ_2777U(...) \, +#define Z_IS_2777U_EQ_2777U(...) \, +#define Z_IS_2778_EQ_2778(...) \, +#define Z_IS_2778U_EQ_2778(...) \, +#define Z_IS_2778_EQ_2778U(...) \, +#define Z_IS_2778U_EQ_2778U(...) \, +#define Z_IS_2779_EQ_2779(...) \, +#define Z_IS_2779U_EQ_2779(...) \, +#define Z_IS_2779_EQ_2779U(...) \, +#define Z_IS_2779U_EQ_2779U(...) \, +#define Z_IS_2780_EQ_2780(...) \, +#define Z_IS_2780U_EQ_2780(...) \, +#define Z_IS_2780_EQ_2780U(...) \, +#define Z_IS_2780U_EQ_2780U(...) \, +#define Z_IS_2781_EQ_2781(...) \, +#define Z_IS_2781U_EQ_2781(...) \, +#define Z_IS_2781_EQ_2781U(...) \, +#define Z_IS_2781U_EQ_2781U(...) \, +#define Z_IS_2782_EQ_2782(...) \, +#define Z_IS_2782U_EQ_2782(...) \, +#define Z_IS_2782_EQ_2782U(...) \, +#define Z_IS_2782U_EQ_2782U(...) \, +#define Z_IS_2783_EQ_2783(...) \, +#define Z_IS_2783U_EQ_2783(...) \, +#define Z_IS_2783_EQ_2783U(...) \, +#define Z_IS_2783U_EQ_2783U(...) \, +#define Z_IS_2784_EQ_2784(...) \, +#define Z_IS_2784U_EQ_2784(...) \, +#define Z_IS_2784_EQ_2784U(...) \, +#define Z_IS_2784U_EQ_2784U(...) \, +#define Z_IS_2785_EQ_2785(...) \, +#define Z_IS_2785U_EQ_2785(...) \, +#define Z_IS_2785_EQ_2785U(...) \, +#define Z_IS_2785U_EQ_2785U(...) \, +#define Z_IS_2786_EQ_2786(...) \, +#define Z_IS_2786U_EQ_2786(...) \, +#define Z_IS_2786_EQ_2786U(...) \, +#define Z_IS_2786U_EQ_2786U(...) \, +#define Z_IS_2787_EQ_2787(...) \, +#define Z_IS_2787U_EQ_2787(...) \, +#define Z_IS_2787_EQ_2787U(...) \, +#define Z_IS_2787U_EQ_2787U(...) \, +#define Z_IS_2788_EQ_2788(...) \, +#define Z_IS_2788U_EQ_2788(...) \, +#define Z_IS_2788_EQ_2788U(...) \, +#define Z_IS_2788U_EQ_2788U(...) \, +#define Z_IS_2789_EQ_2789(...) \, +#define Z_IS_2789U_EQ_2789(...) \, +#define Z_IS_2789_EQ_2789U(...) \, +#define Z_IS_2789U_EQ_2789U(...) \, +#define Z_IS_2790_EQ_2790(...) \, +#define Z_IS_2790U_EQ_2790(...) \, +#define Z_IS_2790_EQ_2790U(...) \, +#define Z_IS_2790U_EQ_2790U(...) \, +#define Z_IS_2791_EQ_2791(...) \, +#define Z_IS_2791U_EQ_2791(...) \, +#define Z_IS_2791_EQ_2791U(...) \, +#define Z_IS_2791U_EQ_2791U(...) \, +#define Z_IS_2792_EQ_2792(...) \, +#define Z_IS_2792U_EQ_2792(...) \, +#define Z_IS_2792_EQ_2792U(...) \, +#define Z_IS_2792U_EQ_2792U(...) \, +#define Z_IS_2793_EQ_2793(...) \, +#define Z_IS_2793U_EQ_2793(...) \, +#define Z_IS_2793_EQ_2793U(...) \, +#define Z_IS_2793U_EQ_2793U(...) \, +#define Z_IS_2794_EQ_2794(...) \, +#define Z_IS_2794U_EQ_2794(...) \, +#define Z_IS_2794_EQ_2794U(...) \, +#define Z_IS_2794U_EQ_2794U(...) \, +#define Z_IS_2795_EQ_2795(...) \, +#define Z_IS_2795U_EQ_2795(...) \, +#define Z_IS_2795_EQ_2795U(...) \, +#define Z_IS_2795U_EQ_2795U(...) \, +#define Z_IS_2796_EQ_2796(...) \, +#define Z_IS_2796U_EQ_2796(...) \, +#define Z_IS_2796_EQ_2796U(...) \, +#define Z_IS_2796U_EQ_2796U(...) \, +#define Z_IS_2797_EQ_2797(...) \, +#define Z_IS_2797U_EQ_2797(...) \, +#define Z_IS_2797_EQ_2797U(...) \, +#define Z_IS_2797U_EQ_2797U(...) \, +#define Z_IS_2798_EQ_2798(...) \, +#define Z_IS_2798U_EQ_2798(...) \, +#define Z_IS_2798_EQ_2798U(...) \, +#define Z_IS_2798U_EQ_2798U(...) \, +#define Z_IS_2799_EQ_2799(...) \, +#define Z_IS_2799U_EQ_2799(...) \, +#define Z_IS_2799_EQ_2799U(...) \, +#define Z_IS_2799U_EQ_2799U(...) \, +#define Z_IS_2800_EQ_2800(...) \, +#define Z_IS_2800U_EQ_2800(...) \, +#define Z_IS_2800_EQ_2800U(...) \, +#define Z_IS_2800U_EQ_2800U(...) \, +#define Z_IS_2801_EQ_2801(...) \, +#define Z_IS_2801U_EQ_2801(...) \, +#define Z_IS_2801_EQ_2801U(...) \, +#define Z_IS_2801U_EQ_2801U(...) \, +#define Z_IS_2802_EQ_2802(...) \, +#define Z_IS_2802U_EQ_2802(...) \, +#define Z_IS_2802_EQ_2802U(...) \, +#define Z_IS_2802U_EQ_2802U(...) \, +#define Z_IS_2803_EQ_2803(...) \, +#define Z_IS_2803U_EQ_2803(...) \, +#define Z_IS_2803_EQ_2803U(...) \, +#define Z_IS_2803U_EQ_2803U(...) \, +#define Z_IS_2804_EQ_2804(...) \, +#define Z_IS_2804U_EQ_2804(...) \, +#define Z_IS_2804_EQ_2804U(...) \, +#define Z_IS_2804U_EQ_2804U(...) \, +#define Z_IS_2805_EQ_2805(...) \, +#define Z_IS_2805U_EQ_2805(...) \, +#define Z_IS_2805_EQ_2805U(...) \, +#define Z_IS_2805U_EQ_2805U(...) \, +#define Z_IS_2806_EQ_2806(...) \, +#define Z_IS_2806U_EQ_2806(...) \, +#define Z_IS_2806_EQ_2806U(...) \, +#define Z_IS_2806U_EQ_2806U(...) \, +#define Z_IS_2807_EQ_2807(...) \, +#define Z_IS_2807U_EQ_2807(...) \, +#define Z_IS_2807_EQ_2807U(...) \, +#define Z_IS_2807U_EQ_2807U(...) \, +#define Z_IS_2808_EQ_2808(...) \, +#define Z_IS_2808U_EQ_2808(...) \, +#define Z_IS_2808_EQ_2808U(...) \, +#define Z_IS_2808U_EQ_2808U(...) \, +#define Z_IS_2809_EQ_2809(...) \, +#define Z_IS_2809U_EQ_2809(...) \, +#define Z_IS_2809_EQ_2809U(...) \, +#define Z_IS_2809U_EQ_2809U(...) \, +#define Z_IS_2810_EQ_2810(...) \, +#define Z_IS_2810U_EQ_2810(...) \, +#define Z_IS_2810_EQ_2810U(...) \, +#define Z_IS_2810U_EQ_2810U(...) \, +#define Z_IS_2811_EQ_2811(...) \, +#define Z_IS_2811U_EQ_2811(...) \, +#define Z_IS_2811_EQ_2811U(...) \, +#define Z_IS_2811U_EQ_2811U(...) \, +#define Z_IS_2812_EQ_2812(...) \, +#define Z_IS_2812U_EQ_2812(...) \, +#define Z_IS_2812_EQ_2812U(...) \, +#define Z_IS_2812U_EQ_2812U(...) \, +#define Z_IS_2813_EQ_2813(...) \, +#define Z_IS_2813U_EQ_2813(...) \, +#define Z_IS_2813_EQ_2813U(...) \, +#define Z_IS_2813U_EQ_2813U(...) \, +#define Z_IS_2814_EQ_2814(...) \, +#define Z_IS_2814U_EQ_2814(...) \, +#define Z_IS_2814_EQ_2814U(...) \, +#define Z_IS_2814U_EQ_2814U(...) \, +#define Z_IS_2815_EQ_2815(...) \, +#define Z_IS_2815U_EQ_2815(...) \, +#define Z_IS_2815_EQ_2815U(...) \, +#define Z_IS_2815U_EQ_2815U(...) \, +#define Z_IS_2816_EQ_2816(...) \, +#define Z_IS_2816U_EQ_2816(...) \, +#define Z_IS_2816_EQ_2816U(...) \, +#define Z_IS_2816U_EQ_2816U(...) \, +#define Z_IS_2817_EQ_2817(...) \, +#define Z_IS_2817U_EQ_2817(...) \, +#define Z_IS_2817_EQ_2817U(...) \, +#define Z_IS_2817U_EQ_2817U(...) \, +#define Z_IS_2818_EQ_2818(...) \, +#define Z_IS_2818U_EQ_2818(...) \, +#define Z_IS_2818_EQ_2818U(...) \, +#define Z_IS_2818U_EQ_2818U(...) \, +#define Z_IS_2819_EQ_2819(...) \, +#define Z_IS_2819U_EQ_2819(...) \, +#define Z_IS_2819_EQ_2819U(...) \, +#define Z_IS_2819U_EQ_2819U(...) \, +#define Z_IS_2820_EQ_2820(...) \, +#define Z_IS_2820U_EQ_2820(...) \, +#define Z_IS_2820_EQ_2820U(...) \, +#define Z_IS_2820U_EQ_2820U(...) \, +#define Z_IS_2821_EQ_2821(...) \, +#define Z_IS_2821U_EQ_2821(...) \, +#define Z_IS_2821_EQ_2821U(...) \, +#define Z_IS_2821U_EQ_2821U(...) \, +#define Z_IS_2822_EQ_2822(...) \, +#define Z_IS_2822U_EQ_2822(...) \, +#define Z_IS_2822_EQ_2822U(...) \, +#define Z_IS_2822U_EQ_2822U(...) \, +#define Z_IS_2823_EQ_2823(...) \, +#define Z_IS_2823U_EQ_2823(...) \, +#define Z_IS_2823_EQ_2823U(...) \, +#define Z_IS_2823U_EQ_2823U(...) \, +#define Z_IS_2824_EQ_2824(...) \, +#define Z_IS_2824U_EQ_2824(...) \, +#define Z_IS_2824_EQ_2824U(...) \, +#define Z_IS_2824U_EQ_2824U(...) \, +#define Z_IS_2825_EQ_2825(...) \, +#define Z_IS_2825U_EQ_2825(...) \, +#define Z_IS_2825_EQ_2825U(...) \, +#define Z_IS_2825U_EQ_2825U(...) \, +#define Z_IS_2826_EQ_2826(...) \, +#define Z_IS_2826U_EQ_2826(...) \, +#define Z_IS_2826_EQ_2826U(...) \, +#define Z_IS_2826U_EQ_2826U(...) \, +#define Z_IS_2827_EQ_2827(...) \, +#define Z_IS_2827U_EQ_2827(...) \, +#define Z_IS_2827_EQ_2827U(...) \, +#define Z_IS_2827U_EQ_2827U(...) \, +#define Z_IS_2828_EQ_2828(...) \, +#define Z_IS_2828U_EQ_2828(...) \, +#define Z_IS_2828_EQ_2828U(...) \, +#define Z_IS_2828U_EQ_2828U(...) \, +#define Z_IS_2829_EQ_2829(...) \, +#define Z_IS_2829U_EQ_2829(...) \, +#define Z_IS_2829_EQ_2829U(...) \, +#define Z_IS_2829U_EQ_2829U(...) \, +#define Z_IS_2830_EQ_2830(...) \, +#define Z_IS_2830U_EQ_2830(...) \, +#define Z_IS_2830_EQ_2830U(...) \, +#define Z_IS_2830U_EQ_2830U(...) \, +#define Z_IS_2831_EQ_2831(...) \, +#define Z_IS_2831U_EQ_2831(...) \, +#define Z_IS_2831_EQ_2831U(...) \, +#define Z_IS_2831U_EQ_2831U(...) \, +#define Z_IS_2832_EQ_2832(...) \, +#define Z_IS_2832U_EQ_2832(...) \, +#define Z_IS_2832_EQ_2832U(...) \, +#define Z_IS_2832U_EQ_2832U(...) \, +#define Z_IS_2833_EQ_2833(...) \, +#define Z_IS_2833U_EQ_2833(...) \, +#define Z_IS_2833_EQ_2833U(...) \, +#define Z_IS_2833U_EQ_2833U(...) \, +#define Z_IS_2834_EQ_2834(...) \, +#define Z_IS_2834U_EQ_2834(...) \, +#define Z_IS_2834_EQ_2834U(...) \, +#define Z_IS_2834U_EQ_2834U(...) \, +#define Z_IS_2835_EQ_2835(...) \, +#define Z_IS_2835U_EQ_2835(...) \, +#define Z_IS_2835_EQ_2835U(...) \, +#define Z_IS_2835U_EQ_2835U(...) \, +#define Z_IS_2836_EQ_2836(...) \, +#define Z_IS_2836U_EQ_2836(...) \, +#define Z_IS_2836_EQ_2836U(...) \, +#define Z_IS_2836U_EQ_2836U(...) \, +#define Z_IS_2837_EQ_2837(...) \, +#define Z_IS_2837U_EQ_2837(...) \, +#define Z_IS_2837_EQ_2837U(...) \, +#define Z_IS_2837U_EQ_2837U(...) \, +#define Z_IS_2838_EQ_2838(...) \, +#define Z_IS_2838U_EQ_2838(...) \, +#define Z_IS_2838_EQ_2838U(...) \, +#define Z_IS_2838U_EQ_2838U(...) \, +#define Z_IS_2839_EQ_2839(...) \, +#define Z_IS_2839U_EQ_2839(...) \, +#define Z_IS_2839_EQ_2839U(...) \, +#define Z_IS_2839U_EQ_2839U(...) \, +#define Z_IS_2840_EQ_2840(...) \, +#define Z_IS_2840U_EQ_2840(...) \, +#define Z_IS_2840_EQ_2840U(...) \, +#define Z_IS_2840U_EQ_2840U(...) \, +#define Z_IS_2841_EQ_2841(...) \, +#define Z_IS_2841U_EQ_2841(...) \, +#define Z_IS_2841_EQ_2841U(...) \, +#define Z_IS_2841U_EQ_2841U(...) \, +#define Z_IS_2842_EQ_2842(...) \, +#define Z_IS_2842U_EQ_2842(...) \, +#define Z_IS_2842_EQ_2842U(...) \, +#define Z_IS_2842U_EQ_2842U(...) \, +#define Z_IS_2843_EQ_2843(...) \, +#define Z_IS_2843U_EQ_2843(...) \, +#define Z_IS_2843_EQ_2843U(...) \, +#define Z_IS_2843U_EQ_2843U(...) \, +#define Z_IS_2844_EQ_2844(...) \, +#define Z_IS_2844U_EQ_2844(...) \, +#define Z_IS_2844_EQ_2844U(...) \, +#define Z_IS_2844U_EQ_2844U(...) \, +#define Z_IS_2845_EQ_2845(...) \, +#define Z_IS_2845U_EQ_2845(...) \, +#define Z_IS_2845_EQ_2845U(...) \, +#define Z_IS_2845U_EQ_2845U(...) \, +#define Z_IS_2846_EQ_2846(...) \, +#define Z_IS_2846U_EQ_2846(...) \, +#define Z_IS_2846_EQ_2846U(...) \, +#define Z_IS_2846U_EQ_2846U(...) \, +#define Z_IS_2847_EQ_2847(...) \, +#define Z_IS_2847U_EQ_2847(...) \, +#define Z_IS_2847_EQ_2847U(...) \, +#define Z_IS_2847U_EQ_2847U(...) \, +#define Z_IS_2848_EQ_2848(...) \, +#define Z_IS_2848U_EQ_2848(...) \, +#define Z_IS_2848_EQ_2848U(...) \, +#define Z_IS_2848U_EQ_2848U(...) \, +#define Z_IS_2849_EQ_2849(...) \, +#define Z_IS_2849U_EQ_2849(...) \, +#define Z_IS_2849_EQ_2849U(...) \, +#define Z_IS_2849U_EQ_2849U(...) \, +#define Z_IS_2850_EQ_2850(...) \, +#define Z_IS_2850U_EQ_2850(...) \, +#define Z_IS_2850_EQ_2850U(...) \, +#define Z_IS_2850U_EQ_2850U(...) \, +#define Z_IS_2851_EQ_2851(...) \, +#define Z_IS_2851U_EQ_2851(...) \, +#define Z_IS_2851_EQ_2851U(...) \, +#define Z_IS_2851U_EQ_2851U(...) \, +#define Z_IS_2852_EQ_2852(...) \, +#define Z_IS_2852U_EQ_2852(...) \, +#define Z_IS_2852_EQ_2852U(...) \, +#define Z_IS_2852U_EQ_2852U(...) \, +#define Z_IS_2853_EQ_2853(...) \, +#define Z_IS_2853U_EQ_2853(...) \, +#define Z_IS_2853_EQ_2853U(...) \, +#define Z_IS_2853U_EQ_2853U(...) \, +#define Z_IS_2854_EQ_2854(...) \, +#define Z_IS_2854U_EQ_2854(...) \, +#define Z_IS_2854_EQ_2854U(...) \, +#define Z_IS_2854U_EQ_2854U(...) \, +#define Z_IS_2855_EQ_2855(...) \, +#define Z_IS_2855U_EQ_2855(...) \, +#define Z_IS_2855_EQ_2855U(...) \, +#define Z_IS_2855U_EQ_2855U(...) \, +#define Z_IS_2856_EQ_2856(...) \, +#define Z_IS_2856U_EQ_2856(...) \, +#define Z_IS_2856_EQ_2856U(...) \, +#define Z_IS_2856U_EQ_2856U(...) \, +#define Z_IS_2857_EQ_2857(...) \, +#define Z_IS_2857U_EQ_2857(...) \, +#define Z_IS_2857_EQ_2857U(...) \, +#define Z_IS_2857U_EQ_2857U(...) \, +#define Z_IS_2858_EQ_2858(...) \, +#define Z_IS_2858U_EQ_2858(...) \, +#define Z_IS_2858_EQ_2858U(...) \, +#define Z_IS_2858U_EQ_2858U(...) \, +#define Z_IS_2859_EQ_2859(...) \, +#define Z_IS_2859U_EQ_2859(...) \, +#define Z_IS_2859_EQ_2859U(...) \, +#define Z_IS_2859U_EQ_2859U(...) \, +#define Z_IS_2860_EQ_2860(...) \, +#define Z_IS_2860U_EQ_2860(...) \, +#define Z_IS_2860_EQ_2860U(...) \, +#define Z_IS_2860U_EQ_2860U(...) \, +#define Z_IS_2861_EQ_2861(...) \, +#define Z_IS_2861U_EQ_2861(...) \, +#define Z_IS_2861_EQ_2861U(...) \, +#define Z_IS_2861U_EQ_2861U(...) \, +#define Z_IS_2862_EQ_2862(...) \, +#define Z_IS_2862U_EQ_2862(...) \, +#define Z_IS_2862_EQ_2862U(...) \, +#define Z_IS_2862U_EQ_2862U(...) \, +#define Z_IS_2863_EQ_2863(...) \, +#define Z_IS_2863U_EQ_2863(...) \, +#define Z_IS_2863_EQ_2863U(...) \, +#define Z_IS_2863U_EQ_2863U(...) \, +#define Z_IS_2864_EQ_2864(...) \, +#define Z_IS_2864U_EQ_2864(...) \, +#define Z_IS_2864_EQ_2864U(...) \, +#define Z_IS_2864U_EQ_2864U(...) \, +#define Z_IS_2865_EQ_2865(...) \, +#define Z_IS_2865U_EQ_2865(...) \, +#define Z_IS_2865_EQ_2865U(...) \, +#define Z_IS_2865U_EQ_2865U(...) \, +#define Z_IS_2866_EQ_2866(...) \, +#define Z_IS_2866U_EQ_2866(...) \, +#define Z_IS_2866_EQ_2866U(...) \, +#define Z_IS_2866U_EQ_2866U(...) \, +#define Z_IS_2867_EQ_2867(...) \, +#define Z_IS_2867U_EQ_2867(...) \, +#define Z_IS_2867_EQ_2867U(...) \, +#define Z_IS_2867U_EQ_2867U(...) \, +#define Z_IS_2868_EQ_2868(...) \, +#define Z_IS_2868U_EQ_2868(...) \, +#define Z_IS_2868_EQ_2868U(...) \, +#define Z_IS_2868U_EQ_2868U(...) \, +#define Z_IS_2869_EQ_2869(...) \, +#define Z_IS_2869U_EQ_2869(...) \, +#define Z_IS_2869_EQ_2869U(...) \, +#define Z_IS_2869U_EQ_2869U(...) \, +#define Z_IS_2870_EQ_2870(...) \, +#define Z_IS_2870U_EQ_2870(...) \, +#define Z_IS_2870_EQ_2870U(...) \, +#define Z_IS_2870U_EQ_2870U(...) \, +#define Z_IS_2871_EQ_2871(...) \, +#define Z_IS_2871U_EQ_2871(...) \, +#define Z_IS_2871_EQ_2871U(...) \, +#define Z_IS_2871U_EQ_2871U(...) \, +#define Z_IS_2872_EQ_2872(...) \, +#define Z_IS_2872U_EQ_2872(...) \, +#define Z_IS_2872_EQ_2872U(...) \, +#define Z_IS_2872U_EQ_2872U(...) \, +#define Z_IS_2873_EQ_2873(...) \, +#define Z_IS_2873U_EQ_2873(...) \, +#define Z_IS_2873_EQ_2873U(...) \, +#define Z_IS_2873U_EQ_2873U(...) \, +#define Z_IS_2874_EQ_2874(...) \, +#define Z_IS_2874U_EQ_2874(...) \, +#define Z_IS_2874_EQ_2874U(...) \, +#define Z_IS_2874U_EQ_2874U(...) \, +#define Z_IS_2875_EQ_2875(...) \, +#define Z_IS_2875U_EQ_2875(...) \, +#define Z_IS_2875_EQ_2875U(...) \, +#define Z_IS_2875U_EQ_2875U(...) \, +#define Z_IS_2876_EQ_2876(...) \, +#define Z_IS_2876U_EQ_2876(...) \, +#define Z_IS_2876_EQ_2876U(...) \, +#define Z_IS_2876U_EQ_2876U(...) \, +#define Z_IS_2877_EQ_2877(...) \, +#define Z_IS_2877U_EQ_2877(...) \, +#define Z_IS_2877_EQ_2877U(...) \, +#define Z_IS_2877U_EQ_2877U(...) \, +#define Z_IS_2878_EQ_2878(...) \, +#define Z_IS_2878U_EQ_2878(...) \, +#define Z_IS_2878_EQ_2878U(...) \, +#define Z_IS_2878U_EQ_2878U(...) \, +#define Z_IS_2879_EQ_2879(...) \, +#define Z_IS_2879U_EQ_2879(...) \, +#define Z_IS_2879_EQ_2879U(...) \, +#define Z_IS_2879U_EQ_2879U(...) \, +#define Z_IS_2880_EQ_2880(...) \, +#define Z_IS_2880U_EQ_2880(...) \, +#define Z_IS_2880_EQ_2880U(...) \, +#define Z_IS_2880U_EQ_2880U(...) \, +#define Z_IS_2881_EQ_2881(...) \, +#define Z_IS_2881U_EQ_2881(...) \, +#define Z_IS_2881_EQ_2881U(...) \, +#define Z_IS_2881U_EQ_2881U(...) \, +#define Z_IS_2882_EQ_2882(...) \, +#define Z_IS_2882U_EQ_2882(...) \, +#define Z_IS_2882_EQ_2882U(...) \, +#define Z_IS_2882U_EQ_2882U(...) \, +#define Z_IS_2883_EQ_2883(...) \, +#define Z_IS_2883U_EQ_2883(...) \, +#define Z_IS_2883_EQ_2883U(...) \, +#define Z_IS_2883U_EQ_2883U(...) \, +#define Z_IS_2884_EQ_2884(...) \, +#define Z_IS_2884U_EQ_2884(...) \, +#define Z_IS_2884_EQ_2884U(...) \, +#define Z_IS_2884U_EQ_2884U(...) \, +#define Z_IS_2885_EQ_2885(...) \, +#define Z_IS_2885U_EQ_2885(...) \, +#define Z_IS_2885_EQ_2885U(...) \, +#define Z_IS_2885U_EQ_2885U(...) \, +#define Z_IS_2886_EQ_2886(...) \, +#define Z_IS_2886U_EQ_2886(...) \, +#define Z_IS_2886_EQ_2886U(...) \, +#define Z_IS_2886U_EQ_2886U(...) \, +#define Z_IS_2887_EQ_2887(...) \, +#define Z_IS_2887U_EQ_2887(...) \, +#define Z_IS_2887_EQ_2887U(...) \, +#define Z_IS_2887U_EQ_2887U(...) \, +#define Z_IS_2888_EQ_2888(...) \, +#define Z_IS_2888U_EQ_2888(...) \, +#define Z_IS_2888_EQ_2888U(...) \, +#define Z_IS_2888U_EQ_2888U(...) \, +#define Z_IS_2889_EQ_2889(...) \, +#define Z_IS_2889U_EQ_2889(...) \, +#define Z_IS_2889_EQ_2889U(...) \, +#define Z_IS_2889U_EQ_2889U(...) \, +#define Z_IS_2890_EQ_2890(...) \, +#define Z_IS_2890U_EQ_2890(...) \, +#define Z_IS_2890_EQ_2890U(...) \, +#define Z_IS_2890U_EQ_2890U(...) \, +#define Z_IS_2891_EQ_2891(...) \, +#define Z_IS_2891U_EQ_2891(...) \, +#define Z_IS_2891_EQ_2891U(...) \, +#define Z_IS_2891U_EQ_2891U(...) \, +#define Z_IS_2892_EQ_2892(...) \, +#define Z_IS_2892U_EQ_2892(...) \, +#define Z_IS_2892_EQ_2892U(...) \, +#define Z_IS_2892U_EQ_2892U(...) \, +#define Z_IS_2893_EQ_2893(...) \, +#define Z_IS_2893U_EQ_2893(...) \, +#define Z_IS_2893_EQ_2893U(...) \, +#define Z_IS_2893U_EQ_2893U(...) \, +#define Z_IS_2894_EQ_2894(...) \, +#define Z_IS_2894U_EQ_2894(...) \, +#define Z_IS_2894_EQ_2894U(...) \, +#define Z_IS_2894U_EQ_2894U(...) \, +#define Z_IS_2895_EQ_2895(...) \, +#define Z_IS_2895U_EQ_2895(...) \, +#define Z_IS_2895_EQ_2895U(...) \, +#define Z_IS_2895U_EQ_2895U(...) \, +#define Z_IS_2896_EQ_2896(...) \, +#define Z_IS_2896U_EQ_2896(...) \, +#define Z_IS_2896_EQ_2896U(...) \, +#define Z_IS_2896U_EQ_2896U(...) \, +#define Z_IS_2897_EQ_2897(...) \, +#define Z_IS_2897U_EQ_2897(...) \, +#define Z_IS_2897_EQ_2897U(...) \, +#define Z_IS_2897U_EQ_2897U(...) \, +#define Z_IS_2898_EQ_2898(...) \, +#define Z_IS_2898U_EQ_2898(...) \, +#define Z_IS_2898_EQ_2898U(...) \, +#define Z_IS_2898U_EQ_2898U(...) \, +#define Z_IS_2899_EQ_2899(...) \, +#define Z_IS_2899U_EQ_2899(...) \, +#define Z_IS_2899_EQ_2899U(...) \, +#define Z_IS_2899U_EQ_2899U(...) \, +#define Z_IS_2900_EQ_2900(...) \, +#define Z_IS_2900U_EQ_2900(...) \, +#define Z_IS_2900_EQ_2900U(...) \, +#define Z_IS_2900U_EQ_2900U(...) \, +#define Z_IS_2901_EQ_2901(...) \, +#define Z_IS_2901U_EQ_2901(...) \, +#define Z_IS_2901_EQ_2901U(...) \, +#define Z_IS_2901U_EQ_2901U(...) \, +#define Z_IS_2902_EQ_2902(...) \, +#define Z_IS_2902U_EQ_2902(...) \, +#define Z_IS_2902_EQ_2902U(...) \, +#define Z_IS_2902U_EQ_2902U(...) \, +#define Z_IS_2903_EQ_2903(...) \, +#define Z_IS_2903U_EQ_2903(...) \, +#define Z_IS_2903_EQ_2903U(...) \, +#define Z_IS_2903U_EQ_2903U(...) \, +#define Z_IS_2904_EQ_2904(...) \, +#define Z_IS_2904U_EQ_2904(...) \, +#define Z_IS_2904_EQ_2904U(...) \, +#define Z_IS_2904U_EQ_2904U(...) \, +#define Z_IS_2905_EQ_2905(...) \, +#define Z_IS_2905U_EQ_2905(...) \, +#define Z_IS_2905_EQ_2905U(...) \, +#define Z_IS_2905U_EQ_2905U(...) \, +#define Z_IS_2906_EQ_2906(...) \, +#define Z_IS_2906U_EQ_2906(...) \, +#define Z_IS_2906_EQ_2906U(...) \, +#define Z_IS_2906U_EQ_2906U(...) \, +#define Z_IS_2907_EQ_2907(...) \, +#define Z_IS_2907U_EQ_2907(...) \, +#define Z_IS_2907_EQ_2907U(...) \, +#define Z_IS_2907U_EQ_2907U(...) \, +#define Z_IS_2908_EQ_2908(...) \, +#define Z_IS_2908U_EQ_2908(...) \, +#define Z_IS_2908_EQ_2908U(...) \, +#define Z_IS_2908U_EQ_2908U(...) \, +#define Z_IS_2909_EQ_2909(...) \, +#define Z_IS_2909U_EQ_2909(...) \, +#define Z_IS_2909_EQ_2909U(...) \, +#define Z_IS_2909U_EQ_2909U(...) \, +#define Z_IS_2910_EQ_2910(...) \, +#define Z_IS_2910U_EQ_2910(...) \, +#define Z_IS_2910_EQ_2910U(...) \, +#define Z_IS_2910U_EQ_2910U(...) \, +#define Z_IS_2911_EQ_2911(...) \, +#define Z_IS_2911U_EQ_2911(...) \, +#define Z_IS_2911_EQ_2911U(...) \, +#define Z_IS_2911U_EQ_2911U(...) \, +#define Z_IS_2912_EQ_2912(...) \, +#define Z_IS_2912U_EQ_2912(...) \, +#define Z_IS_2912_EQ_2912U(...) \, +#define Z_IS_2912U_EQ_2912U(...) \, +#define Z_IS_2913_EQ_2913(...) \, +#define Z_IS_2913U_EQ_2913(...) \, +#define Z_IS_2913_EQ_2913U(...) \, +#define Z_IS_2913U_EQ_2913U(...) \, +#define Z_IS_2914_EQ_2914(...) \, +#define Z_IS_2914U_EQ_2914(...) \, +#define Z_IS_2914_EQ_2914U(...) \, +#define Z_IS_2914U_EQ_2914U(...) \, +#define Z_IS_2915_EQ_2915(...) \, +#define Z_IS_2915U_EQ_2915(...) \, +#define Z_IS_2915_EQ_2915U(...) \, +#define Z_IS_2915U_EQ_2915U(...) \, +#define Z_IS_2916_EQ_2916(...) \, +#define Z_IS_2916U_EQ_2916(...) \, +#define Z_IS_2916_EQ_2916U(...) \, +#define Z_IS_2916U_EQ_2916U(...) \, +#define Z_IS_2917_EQ_2917(...) \, +#define Z_IS_2917U_EQ_2917(...) \, +#define Z_IS_2917_EQ_2917U(...) \, +#define Z_IS_2917U_EQ_2917U(...) \, +#define Z_IS_2918_EQ_2918(...) \, +#define Z_IS_2918U_EQ_2918(...) \, +#define Z_IS_2918_EQ_2918U(...) \, +#define Z_IS_2918U_EQ_2918U(...) \, +#define Z_IS_2919_EQ_2919(...) \, +#define Z_IS_2919U_EQ_2919(...) \, +#define Z_IS_2919_EQ_2919U(...) \, +#define Z_IS_2919U_EQ_2919U(...) \, +#define Z_IS_2920_EQ_2920(...) \, +#define Z_IS_2920U_EQ_2920(...) \, +#define Z_IS_2920_EQ_2920U(...) \, +#define Z_IS_2920U_EQ_2920U(...) \, +#define Z_IS_2921_EQ_2921(...) \, +#define Z_IS_2921U_EQ_2921(...) \, +#define Z_IS_2921_EQ_2921U(...) \, +#define Z_IS_2921U_EQ_2921U(...) \, +#define Z_IS_2922_EQ_2922(...) \, +#define Z_IS_2922U_EQ_2922(...) \, +#define Z_IS_2922_EQ_2922U(...) \, +#define Z_IS_2922U_EQ_2922U(...) \, +#define Z_IS_2923_EQ_2923(...) \, +#define Z_IS_2923U_EQ_2923(...) \, +#define Z_IS_2923_EQ_2923U(...) \, +#define Z_IS_2923U_EQ_2923U(...) \, +#define Z_IS_2924_EQ_2924(...) \, +#define Z_IS_2924U_EQ_2924(...) \, +#define Z_IS_2924_EQ_2924U(...) \, +#define Z_IS_2924U_EQ_2924U(...) \, +#define Z_IS_2925_EQ_2925(...) \, +#define Z_IS_2925U_EQ_2925(...) \, +#define Z_IS_2925_EQ_2925U(...) \, +#define Z_IS_2925U_EQ_2925U(...) \, +#define Z_IS_2926_EQ_2926(...) \, +#define Z_IS_2926U_EQ_2926(...) \, +#define Z_IS_2926_EQ_2926U(...) \, +#define Z_IS_2926U_EQ_2926U(...) \, +#define Z_IS_2927_EQ_2927(...) \, +#define Z_IS_2927U_EQ_2927(...) \, +#define Z_IS_2927_EQ_2927U(...) \, +#define Z_IS_2927U_EQ_2927U(...) \, +#define Z_IS_2928_EQ_2928(...) \, +#define Z_IS_2928U_EQ_2928(...) \, +#define Z_IS_2928_EQ_2928U(...) \, +#define Z_IS_2928U_EQ_2928U(...) \, +#define Z_IS_2929_EQ_2929(...) \, +#define Z_IS_2929U_EQ_2929(...) \, +#define Z_IS_2929_EQ_2929U(...) \, +#define Z_IS_2929U_EQ_2929U(...) \, +#define Z_IS_2930_EQ_2930(...) \, +#define Z_IS_2930U_EQ_2930(...) \, +#define Z_IS_2930_EQ_2930U(...) \, +#define Z_IS_2930U_EQ_2930U(...) \, +#define Z_IS_2931_EQ_2931(...) \, +#define Z_IS_2931U_EQ_2931(...) \, +#define Z_IS_2931_EQ_2931U(...) \, +#define Z_IS_2931U_EQ_2931U(...) \, +#define Z_IS_2932_EQ_2932(...) \, +#define Z_IS_2932U_EQ_2932(...) \, +#define Z_IS_2932_EQ_2932U(...) \, +#define Z_IS_2932U_EQ_2932U(...) \, +#define Z_IS_2933_EQ_2933(...) \, +#define Z_IS_2933U_EQ_2933(...) \, +#define Z_IS_2933_EQ_2933U(...) \, +#define Z_IS_2933U_EQ_2933U(...) \, +#define Z_IS_2934_EQ_2934(...) \, +#define Z_IS_2934U_EQ_2934(...) \, +#define Z_IS_2934_EQ_2934U(...) \, +#define Z_IS_2934U_EQ_2934U(...) \, +#define Z_IS_2935_EQ_2935(...) \, +#define Z_IS_2935U_EQ_2935(...) \, +#define Z_IS_2935_EQ_2935U(...) \, +#define Z_IS_2935U_EQ_2935U(...) \, +#define Z_IS_2936_EQ_2936(...) \, +#define Z_IS_2936U_EQ_2936(...) \, +#define Z_IS_2936_EQ_2936U(...) \, +#define Z_IS_2936U_EQ_2936U(...) \, +#define Z_IS_2937_EQ_2937(...) \, +#define Z_IS_2937U_EQ_2937(...) \, +#define Z_IS_2937_EQ_2937U(...) \, +#define Z_IS_2937U_EQ_2937U(...) \, +#define Z_IS_2938_EQ_2938(...) \, +#define Z_IS_2938U_EQ_2938(...) \, +#define Z_IS_2938_EQ_2938U(...) \, +#define Z_IS_2938U_EQ_2938U(...) \, +#define Z_IS_2939_EQ_2939(...) \, +#define Z_IS_2939U_EQ_2939(...) \, +#define Z_IS_2939_EQ_2939U(...) \, +#define Z_IS_2939U_EQ_2939U(...) \, +#define Z_IS_2940_EQ_2940(...) \, +#define Z_IS_2940U_EQ_2940(...) \, +#define Z_IS_2940_EQ_2940U(...) \, +#define Z_IS_2940U_EQ_2940U(...) \, +#define Z_IS_2941_EQ_2941(...) \, +#define Z_IS_2941U_EQ_2941(...) \, +#define Z_IS_2941_EQ_2941U(...) \, +#define Z_IS_2941U_EQ_2941U(...) \, +#define Z_IS_2942_EQ_2942(...) \, +#define Z_IS_2942U_EQ_2942(...) \, +#define Z_IS_2942_EQ_2942U(...) \, +#define Z_IS_2942U_EQ_2942U(...) \, +#define Z_IS_2943_EQ_2943(...) \, +#define Z_IS_2943U_EQ_2943(...) \, +#define Z_IS_2943_EQ_2943U(...) \, +#define Z_IS_2943U_EQ_2943U(...) \, +#define Z_IS_2944_EQ_2944(...) \, +#define Z_IS_2944U_EQ_2944(...) \, +#define Z_IS_2944_EQ_2944U(...) \, +#define Z_IS_2944U_EQ_2944U(...) \, +#define Z_IS_2945_EQ_2945(...) \, +#define Z_IS_2945U_EQ_2945(...) \, +#define Z_IS_2945_EQ_2945U(...) \, +#define Z_IS_2945U_EQ_2945U(...) \, +#define Z_IS_2946_EQ_2946(...) \, +#define Z_IS_2946U_EQ_2946(...) \, +#define Z_IS_2946_EQ_2946U(...) \, +#define Z_IS_2946U_EQ_2946U(...) \, +#define Z_IS_2947_EQ_2947(...) \, +#define Z_IS_2947U_EQ_2947(...) \, +#define Z_IS_2947_EQ_2947U(...) \, +#define Z_IS_2947U_EQ_2947U(...) \, +#define Z_IS_2948_EQ_2948(...) \, +#define Z_IS_2948U_EQ_2948(...) \, +#define Z_IS_2948_EQ_2948U(...) \, +#define Z_IS_2948U_EQ_2948U(...) \, +#define Z_IS_2949_EQ_2949(...) \, +#define Z_IS_2949U_EQ_2949(...) \, +#define Z_IS_2949_EQ_2949U(...) \, +#define Z_IS_2949U_EQ_2949U(...) \, +#define Z_IS_2950_EQ_2950(...) \, +#define Z_IS_2950U_EQ_2950(...) \, +#define Z_IS_2950_EQ_2950U(...) \, +#define Z_IS_2950U_EQ_2950U(...) \, +#define Z_IS_2951_EQ_2951(...) \, +#define Z_IS_2951U_EQ_2951(...) \, +#define Z_IS_2951_EQ_2951U(...) \, +#define Z_IS_2951U_EQ_2951U(...) \, +#define Z_IS_2952_EQ_2952(...) \, +#define Z_IS_2952U_EQ_2952(...) \, +#define Z_IS_2952_EQ_2952U(...) \, +#define Z_IS_2952U_EQ_2952U(...) \, +#define Z_IS_2953_EQ_2953(...) \, +#define Z_IS_2953U_EQ_2953(...) \, +#define Z_IS_2953_EQ_2953U(...) \, +#define Z_IS_2953U_EQ_2953U(...) \, +#define Z_IS_2954_EQ_2954(...) \, +#define Z_IS_2954U_EQ_2954(...) \, +#define Z_IS_2954_EQ_2954U(...) \, +#define Z_IS_2954U_EQ_2954U(...) \, +#define Z_IS_2955_EQ_2955(...) \, +#define Z_IS_2955U_EQ_2955(...) \, +#define Z_IS_2955_EQ_2955U(...) \, +#define Z_IS_2955U_EQ_2955U(...) \, +#define Z_IS_2956_EQ_2956(...) \, +#define Z_IS_2956U_EQ_2956(...) \, +#define Z_IS_2956_EQ_2956U(...) \, +#define Z_IS_2956U_EQ_2956U(...) \, +#define Z_IS_2957_EQ_2957(...) \, +#define Z_IS_2957U_EQ_2957(...) \, +#define Z_IS_2957_EQ_2957U(...) \, +#define Z_IS_2957U_EQ_2957U(...) \, +#define Z_IS_2958_EQ_2958(...) \, +#define Z_IS_2958U_EQ_2958(...) \, +#define Z_IS_2958_EQ_2958U(...) \, +#define Z_IS_2958U_EQ_2958U(...) \, +#define Z_IS_2959_EQ_2959(...) \, +#define Z_IS_2959U_EQ_2959(...) \, +#define Z_IS_2959_EQ_2959U(...) \, +#define Z_IS_2959U_EQ_2959U(...) \, +#define Z_IS_2960_EQ_2960(...) \, +#define Z_IS_2960U_EQ_2960(...) \, +#define Z_IS_2960_EQ_2960U(...) \, +#define Z_IS_2960U_EQ_2960U(...) \, +#define Z_IS_2961_EQ_2961(...) \, +#define Z_IS_2961U_EQ_2961(...) \, +#define Z_IS_2961_EQ_2961U(...) \, +#define Z_IS_2961U_EQ_2961U(...) \, +#define Z_IS_2962_EQ_2962(...) \, +#define Z_IS_2962U_EQ_2962(...) \, +#define Z_IS_2962_EQ_2962U(...) \, +#define Z_IS_2962U_EQ_2962U(...) \, +#define Z_IS_2963_EQ_2963(...) \, +#define Z_IS_2963U_EQ_2963(...) \, +#define Z_IS_2963_EQ_2963U(...) \, +#define Z_IS_2963U_EQ_2963U(...) \, +#define Z_IS_2964_EQ_2964(...) \, +#define Z_IS_2964U_EQ_2964(...) \, +#define Z_IS_2964_EQ_2964U(...) \, +#define Z_IS_2964U_EQ_2964U(...) \, +#define Z_IS_2965_EQ_2965(...) \, +#define Z_IS_2965U_EQ_2965(...) \, +#define Z_IS_2965_EQ_2965U(...) \, +#define Z_IS_2965U_EQ_2965U(...) \, +#define Z_IS_2966_EQ_2966(...) \, +#define Z_IS_2966U_EQ_2966(...) \, +#define Z_IS_2966_EQ_2966U(...) \, +#define Z_IS_2966U_EQ_2966U(...) \, +#define Z_IS_2967_EQ_2967(...) \, +#define Z_IS_2967U_EQ_2967(...) \, +#define Z_IS_2967_EQ_2967U(...) \, +#define Z_IS_2967U_EQ_2967U(...) \, +#define Z_IS_2968_EQ_2968(...) \, +#define Z_IS_2968U_EQ_2968(...) \, +#define Z_IS_2968_EQ_2968U(...) \, +#define Z_IS_2968U_EQ_2968U(...) \, +#define Z_IS_2969_EQ_2969(...) \, +#define Z_IS_2969U_EQ_2969(...) \, +#define Z_IS_2969_EQ_2969U(...) \, +#define Z_IS_2969U_EQ_2969U(...) \, +#define Z_IS_2970_EQ_2970(...) \, +#define Z_IS_2970U_EQ_2970(...) \, +#define Z_IS_2970_EQ_2970U(...) \, +#define Z_IS_2970U_EQ_2970U(...) \, +#define Z_IS_2971_EQ_2971(...) \, +#define Z_IS_2971U_EQ_2971(...) \, +#define Z_IS_2971_EQ_2971U(...) \, +#define Z_IS_2971U_EQ_2971U(...) \, +#define Z_IS_2972_EQ_2972(...) \, +#define Z_IS_2972U_EQ_2972(...) \, +#define Z_IS_2972_EQ_2972U(...) \, +#define Z_IS_2972U_EQ_2972U(...) \, +#define Z_IS_2973_EQ_2973(...) \, +#define Z_IS_2973U_EQ_2973(...) \, +#define Z_IS_2973_EQ_2973U(...) \, +#define Z_IS_2973U_EQ_2973U(...) \, +#define Z_IS_2974_EQ_2974(...) \, +#define Z_IS_2974U_EQ_2974(...) \, +#define Z_IS_2974_EQ_2974U(...) \, +#define Z_IS_2974U_EQ_2974U(...) \, +#define Z_IS_2975_EQ_2975(...) \, +#define Z_IS_2975U_EQ_2975(...) \, +#define Z_IS_2975_EQ_2975U(...) \, +#define Z_IS_2975U_EQ_2975U(...) \, +#define Z_IS_2976_EQ_2976(...) \, +#define Z_IS_2976U_EQ_2976(...) \, +#define Z_IS_2976_EQ_2976U(...) \, +#define Z_IS_2976U_EQ_2976U(...) \, +#define Z_IS_2977_EQ_2977(...) \, +#define Z_IS_2977U_EQ_2977(...) \, +#define Z_IS_2977_EQ_2977U(...) \, +#define Z_IS_2977U_EQ_2977U(...) \, +#define Z_IS_2978_EQ_2978(...) \, +#define Z_IS_2978U_EQ_2978(...) \, +#define Z_IS_2978_EQ_2978U(...) \, +#define Z_IS_2978U_EQ_2978U(...) \, +#define Z_IS_2979_EQ_2979(...) \, +#define Z_IS_2979U_EQ_2979(...) \, +#define Z_IS_2979_EQ_2979U(...) \, +#define Z_IS_2979U_EQ_2979U(...) \, +#define Z_IS_2980_EQ_2980(...) \, +#define Z_IS_2980U_EQ_2980(...) \, +#define Z_IS_2980_EQ_2980U(...) \, +#define Z_IS_2980U_EQ_2980U(...) \, +#define Z_IS_2981_EQ_2981(...) \, +#define Z_IS_2981U_EQ_2981(...) \, +#define Z_IS_2981_EQ_2981U(...) \, +#define Z_IS_2981U_EQ_2981U(...) \, +#define Z_IS_2982_EQ_2982(...) \, +#define Z_IS_2982U_EQ_2982(...) \, +#define Z_IS_2982_EQ_2982U(...) \, +#define Z_IS_2982U_EQ_2982U(...) \, +#define Z_IS_2983_EQ_2983(...) \, +#define Z_IS_2983U_EQ_2983(...) \, +#define Z_IS_2983_EQ_2983U(...) \, +#define Z_IS_2983U_EQ_2983U(...) \, +#define Z_IS_2984_EQ_2984(...) \, +#define Z_IS_2984U_EQ_2984(...) \, +#define Z_IS_2984_EQ_2984U(...) \, +#define Z_IS_2984U_EQ_2984U(...) \, +#define Z_IS_2985_EQ_2985(...) \, +#define Z_IS_2985U_EQ_2985(...) \, +#define Z_IS_2985_EQ_2985U(...) \, +#define Z_IS_2985U_EQ_2985U(...) \, +#define Z_IS_2986_EQ_2986(...) \, +#define Z_IS_2986U_EQ_2986(...) \, +#define Z_IS_2986_EQ_2986U(...) \, +#define Z_IS_2986U_EQ_2986U(...) \, +#define Z_IS_2987_EQ_2987(...) \, +#define Z_IS_2987U_EQ_2987(...) \, +#define Z_IS_2987_EQ_2987U(...) \, +#define Z_IS_2987U_EQ_2987U(...) \, +#define Z_IS_2988_EQ_2988(...) \, +#define Z_IS_2988U_EQ_2988(...) \, +#define Z_IS_2988_EQ_2988U(...) \, +#define Z_IS_2988U_EQ_2988U(...) \, +#define Z_IS_2989_EQ_2989(...) \, +#define Z_IS_2989U_EQ_2989(...) \, +#define Z_IS_2989_EQ_2989U(...) \, +#define Z_IS_2989U_EQ_2989U(...) \, +#define Z_IS_2990_EQ_2990(...) \, +#define Z_IS_2990U_EQ_2990(...) \, +#define Z_IS_2990_EQ_2990U(...) \, +#define Z_IS_2990U_EQ_2990U(...) \, +#define Z_IS_2991_EQ_2991(...) \, +#define Z_IS_2991U_EQ_2991(...) \, +#define Z_IS_2991_EQ_2991U(...) \, +#define Z_IS_2991U_EQ_2991U(...) \, +#define Z_IS_2992_EQ_2992(...) \, +#define Z_IS_2992U_EQ_2992(...) \, +#define Z_IS_2992_EQ_2992U(...) \, +#define Z_IS_2992U_EQ_2992U(...) \, +#define Z_IS_2993_EQ_2993(...) \, +#define Z_IS_2993U_EQ_2993(...) \, +#define Z_IS_2993_EQ_2993U(...) \, +#define Z_IS_2993U_EQ_2993U(...) \, +#define Z_IS_2994_EQ_2994(...) \, +#define Z_IS_2994U_EQ_2994(...) \, +#define Z_IS_2994_EQ_2994U(...) \, +#define Z_IS_2994U_EQ_2994U(...) \, +#define Z_IS_2995_EQ_2995(...) \, +#define Z_IS_2995U_EQ_2995(...) \, +#define Z_IS_2995_EQ_2995U(...) \, +#define Z_IS_2995U_EQ_2995U(...) \, +#define Z_IS_2996_EQ_2996(...) \, +#define Z_IS_2996U_EQ_2996(...) \, +#define Z_IS_2996_EQ_2996U(...) \, +#define Z_IS_2996U_EQ_2996U(...) \, +#define Z_IS_2997_EQ_2997(...) \, +#define Z_IS_2997U_EQ_2997(...) \, +#define Z_IS_2997_EQ_2997U(...) \, +#define Z_IS_2997U_EQ_2997U(...) \, +#define Z_IS_2998_EQ_2998(...) \, +#define Z_IS_2998U_EQ_2998(...) \, +#define Z_IS_2998_EQ_2998U(...) \, +#define Z_IS_2998U_EQ_2998U(...) \, +#define Z_IS_2999_EQ_2999(...) \, +#define Z_IS_2999U_EQ_2999(...) \, +#define Z_IS_2999_EQ_2999U(...) \, +#define Z_IS_2999U_EQ_2999U(...) \, +#define Z_IS_3000_EQ_3000(...) \, +#define Z_IS_3000U_EQ_3000(...) \, +#define Z_IS_3000_EQ_3000U(...) \, +#define Z_IS_3000U_EQ_3000U(...) \, +#define Z_IS_3001_EQ_3001(...) \, +#define Z_IS_3001U_EQ_3001(...) \, +#define Z_IS_3001_EQ_3001U(...) \, +#define Z_IS_3001U_EQ_3001U(...) \, +#define Z_IS_3002_EQ_3002(...) \, +#define Z_IS_3002U_EQ_3002(...) \, +#define Z_IS_3002_EQ_3002U(...) \, +#define Z_IS_3002U_EQ_3002U(...) \, +#define Z_IS_3003_EQ_3003(...) \, +#define Z_IS_3003U_EQ_3003(...) \, +#define Z_IS_3003_EQ_3003U(...) \, +#define Z_IS_3003U_EQ_3003U(...) \, +#define Z_IS_3004_EQ_3004(...) \, +#define Z_IS_3004U_EQ_3004(...) \, +#define Z_IS_3004_EQ_3004U(...) \, +#define Z_IS_3004U_EQ_3004U(...) \, +#define Z_IS_3005_EQ_3005(...) \, +#define Z_IS_3005U_EQ_3005(...) \, +#define Z_IS_3005_EQ_3005U(...) \, +#define Z_IS_3005U_EQ_3005U(...) \, +#define Z_IS_3006_EQ_3006(...) \, +#define Z_IS_3006U_EQ_3006(...) \, +#define Z_IS_3006_EQ_3006U(...) \, +#define Z_IS_3006U_EQ_3006U(...) \, +#define Z_IS_3007_EQ_3007(...) \, +#define Z_IS_3007U_EQ_3007(...) \, +#define Z_IS_3007_EQ_3007U(...) \, +#define Z_IS_3007U_EQ_3007U(...) \, +#define Z_IS_3008_EQ_3008(...) \, +#define Z_IS_3008U_EQ_3008(...) \, +#define Z_IS_3008_EQ_3008U(...) \, +#define Z_IS_3008U_EQ_3008U(...) \, +#define Z_IS_3009_EQ_3009(...) \, +#define Z_IS_3009U_EQ_3009(...) \, +#define Z_IS_3009_EQ_3009U(...) \, +#define Z_IS_3009U_EQ_3009U(...) \, +#define Z_IS_3010_EQ_3010(...) \, +#define Z_IS_3010U_EQ_3010(...) \, +#define Z_IS_3010_EQ_3010U(...) \, +#define Z_IS_3010U_EQ_3010U(...) \, +#define Z_IS_3011_EQ_3011(...) \, +#define Z_IS_3011U_EQ_3011(...) \, +#define Z_IS_3011_EQ_3011U(...) \, +#define Z_IS_3011U_EQ_3011U(...) \, +#define Z_IS_3012_EQ_3012(...) \, +#define Z_IS_3012U_EQ_3012(...) \, +#define Z_IS_3012_EQ_3012U(...) \, +#define Z_IS_3012U_EQ_3012U(...) \, +#define Z_IS_3013_EQ_3013(...) \, +#define Z_IS_3013U_EQ_3013(...) \, +#define Z_IS_3013_EQ_3013U(...) \, +#define Z_IS_3013U_EQ_3013U(...) \, +#define Z_IS_3014_EQ_3014(...) \, +#define Z_IS_3014U_EQ_3014(...) \, +#define Z_IS_3014_EQ_3014U(...) \, +#define Z_IS_3014U_EQ_3014U(...) \, +#define Z_IS_3015_EQ_3015(...) \, +#define Z_IS_3015U_EQ_3015(...) \, +#define Z_IS_3015_EQ_3015U(...) \, +#define Z_IS_3015U_EQ_3015U(...) \, +#define Z_IS_3016_EQ_3016(...) \, +#define Z_IS_3016U_EQ_3016(...) \, +#define Z_IS_3016_EQ_3016U(...) \, +#define Z_IS_3016U_EQ_3016U(...) \, +#define Z_IS_3017_EQ_3017(...) \, +#define Z_IS_3017U_EQ_3017(...) \, +#define Z_IS_3017_EQ_3017U(...) \, +#define Z_IS_3017U_EQ_3017U(...) \, +#define Z_IS_3018_EQ_3018(...) \, +#define Z_IS_3018U_EQ_3018(...) \, +#define Z_IS_3018_EQ_3018U(...) \, +#define Z_IS_3018U_EQ_3018U(...) \, +#define Z_IS_3019_EQ_3019(...) \, +#define Z_IS_3019U_EQ_3019(...) \, +#define Z_IS_3019_EQ_3019U(...) \, +#define Z_IS_3019U_EQ_3019U(...) \, +#define Z_IS_3020_EQ_3020(...) \, +#define Z_IS_3020U_EQ_3020(...) \, +#define Z_IS_3020_EQ_3020U(...) \, +#define Z_IS_3020U_EQ_3020U(...) \, +#define Z_IS_3021_EQ_3021(...) \, +#define Z_IS_3021U_EQ_3021(...) \, +#define Z_IS_3021_EQ_3021U(...) \, +#define Z_IS_3021U_EQ_3021U(...) \, +#define Z_IS_3022_EQ_3022(...) \, +#define Z_IS_3022U_EQ_3022(...) \, +#define Z_IS_3022_EQ_3022U(...) \, +#define Z_IS_3022U_EQ_3022U(...) \, +#define Z_IS_3023_EQ_3023(...) \, +#define Z_IS_3023U_EQ_3023(...) \, +#define Z_IS_3023_EQ_3023U(...) \, +#define Z_IS_3023U_EQ_3023U(...) \, +#define Z_IS_3024_EQ_3024(...) \, +#define Z_IS_3024U_EQ_3024(...) \, +#define Z_IS_3024_EQ_3024U(...) \, +#define Z_IS_3024U_EQ_3024U(...) \, +#define Z_IS_3025_EQ_3025(...) \, +#define Z_IS_3025U_EQ_3025(...) \, +#define Z_IS_3025_EQ_3025U(...) \, +#define Z_IS_3025U_EQ_3025U(...) \, +#define Z_IS_3026_EQ_3026(...) \, +#define Z_IS_3026U_EQ_3026(...) \, +#define Z_IS_3026_EQ_3026U(...) \, +#define Z_IS_3026U_EQ_3026U(...) \, +#define Z_IS_3027_EQ_3027(...) \, +#define Z_IS_3027U_EQ_3027(...) \, +#define Z_IS_3027_EQ_3027U(...) \, +#define Z_IS_3027U_EQ_3027U(...) \, +#define Z_IS_3028_EQ_3028(...) \, +#define Z_IS_3028U_EQ_3028(...) \, +#define Z_IS_3028_EQ_3028U(...) \, +#define Z_IS_3028U_EQ_3028U(...) \, +#define Z_IS_3029_EQ_3029(...) \, +#define Z_IS_3029U_EQ_3029(...) \, +#define Z_IS_3029_EQ_3029U(...) \, +#define Z_IS_3029U_EQ_3029U(...) \, +#define Z_IS_3030_EQ_3030(...) \, +#define Z_IS_3030U_EQ_3030(...) \, +#define Z_IS_3030_EQ_3030U(...) \, +#define Z_IS_3030U_EQ_3030U(...) \, +#define Z_IS_3031_EQ_3031(...) \, +#define Z_IS_3031U_EQ_3031(...) \, +#define Z_IS_3031_EQ_3031U(...) \, +#define Z_IS_3031U_EQ_3031U(...) \, +#define Z_IS_3032_EQ_3032(...) \, +#define Z_IS_3032U_EQ_3032(...) \, +#define Z_IS_3032_EQ_3032U(...) \, +#define Z_IS_3032U_EQ_3032U(...) \, +#define Z_IS_3033_EQ_3033(...) \, +#define Z_IS_3033U_EQ_3033(...) \, +#define Z_IS_3033_EQ_3033U(...) \, +#define Z_IS_3033U_EQ_3033U(...) \, +#define Z_IS_3034_EQ_3034(...) \, +#define Z_IS_3034U_EQ_3034(...) \, +#define Z_IS_3034_EQ_3034U(...) \, +#define Z_IS_3034U_EQ_3034U(...) \, +#define Z_IS_3035_EQ_3035(...) \, +#define Z_IS_3035U_EQ_3035(...) \, +#define Z_IS_3035_EQ_3035U(...) \, +#define Z_IS_3035U_EQ_3035U(...) \, +#define Z_IS_3036_EQ_3036(...) \, +#define Z_IS_3036U_EQ_3036(...) \, +#define Z_IS_3036_EQ_3036U(...) \, +#define Z_IS_3036U_EQ_3036U(...) \, +#define Z_IS_3037_EQ_3037(...) \, +#define Z_IS_3037U_EQ_3037(...) \, +#define Z_IS_3037_EQ_3037U(...) \, +#define Z_IS_3037U_EQ_3037U(...) \, +#define Z_IS_3038_EQ_3038(...) \, +#define Z_IS_3038U_EQ_3038(...) \, +#define Z_IS_3038_EQ_3038U(...) \, +#define Z_IS_3038U_EQ_3038U(...) \, +#define Z_IS_3039_EQ_3039(...) \, +#define Z_IS_3039U_EQ_3039(...) \, +#define Z_IS_3039_EQ_3039U(...) \, +#define Z_IS_3039U_EQ_3039U(...) \, +#define Z_IS_3040_EQ_3040(...) \, +#define Z_IS_3040U_EQ_3040(...) \, +#define Z_IS_3040_EQ_3040U(...) \, +#define Z_IS_3040U_EQ_3040U(...) \, +#define Z_IS_3041_EQ_3041(...) \, +#define Z_IS_3041U_EQ_3041(...) \, +#define Z_IS_3041_EQ_3041U(...) \, +#define Z_IS_3041U_EQ_3041U(...) \, +#define Z_IS_3042_EQ_3042(...) \, +#define Z_IS_3042U_EQ_3042(...) \, +#define Z_IS_3042_EQ_3042U(...) \, +#define Z_IS_3042U_EQ_3042U(...) \, +#define Z_IS_3043_EQ_3043(...) \, +#define Z_IS_3043U_EQ_3043(...) \, +#define Z_IS_3043_EQ_3043U(...) \, +#define Z_IS_3043U_EQ_3043U(...) \, +#define Z_IS_3044_EQ_3044(...) \, +#define Z_IS_3044U_EQ_3044(...) \, +#define Z_IS_3044_EQ_3044U(...) \, +#define Z_IS_3044U_EQ_3044U(...) \, +#define Z_IS_3045_EQ_3045(...) \, +#define Z_IS_3045U_EQ_3045(...) \, +#define Z_IS_3045_EQ_3045U(...) \, +#define Z_IS_3045U_EQ_3045U(...) \, +#define Z_IS_3046_EQ_3046(...) \, +#define Z_IS_3046U_EQ_3046(...) \, +#define Z_IS_3046_EQ_3046U(...) \, +#define Z_IS_3046U_EQ_3046U(...) \, +#define Z_IS_3047_EQ_3047(...) \, +#define Z_IS_3047U_EQ_3047(...) \, +#define Z_IS_3047_EQ_3047U(...) \, +#define Z_IS_3047U_EQ_3047U(...) \, +#define Z_IS_3048_EQ_3048(...) \, +#define Z_IS_3048U_EQ_3048(...) \, +#define Z_IS_3048_EQ_3048U(...) \, +#define Z_IS_3048U_EQ_3048U(...) \, +#define Z_IS_3049_EQ_3049(...) \, +#define Z_IS_3049U_EQ_3049(...) \, +#define Z_IS_3049_EQ_3049U(...) \, +#define Z_IS_3049U_EQ_3049U(...) \, +#define Z_IS_3050_EQ_3050(...) \, +#define Z_IS_3050U_EQ_3050(...) \, +#define Z_IS_3050_EQ_3050U(...) \, +#define Z_IS_3050U_EQ_3050U(...) \, +#define Z_IS_3051_EQ_3051(...) \, +#define Z_IS_3051U_EQ_3051(...) \, +#define Z_IS_3051_EQ_3051U(...) \, +#define Z_IS_3051U_EQ_3051U(...) \, +#define Z_IS_3052_EQ_3052(...) \, +#define Z_IS_3052U_EQ_3052(...) \, +#define Z_IS_3052_EQ_3052U(...) \, +#define Z_IS_3052U_EQ_3052U(...) \, +#define Z_IS_3053_EQ_3053(...) \, +#define Z_IS_3053U_EQ_3053(...) \, +#define Z_IS_3053_EQ_3053U(...) \, +#define Z_IS_3053U_EQ_3053U(...) \, +#define Z_IS_3054_EQ_3054(...) \, +#define Z_IS_3054U_EQ_3054(...) \, +#define Z_IS_3054_EQ_3054U(...) \, +#define Z_IS_3054U_EQ_3054U(...) \, +#define Z_IS_3055_EQ_3055(...) \, +#define Z_IS_3055U_EQ_3055(...) \, +#define Z_IS_3055_EQ_3055U(...) \, +#define Z_IS_3055U_EQ_3055U(...) \, +#define Z_IS_3056_EQ_3056(...) \, +#define Z_IS_3056U_EQ_3056(...) \, +#define Z_IS_3056_EQ_3056U(...) \, +#define Z_IS_3056U_EQ_3056U(...) \, +#define Z_IS_3057_EQ_3057(...) \, +#define Z_IS_3057U_EQ_3057(...) \, +#define Z_IS_3057_EQ_3057U(...) \, +#define Z_IS_3057U_EQ_3057U(...) \, +#define Z_IS_3058_EQ_3058(...) \, +#define Z_IS_3058U_EQ_3058(...) \, +#define Z_IS_3058_EQ_3058U(...) \, +#define Z_IS_3058U_EQ_3058U(...) \, +#define Z_IS_3059_EQ_3059(...) \, +#define Z_IS_3059U_EQ_3059(...) \, +#define Z_IS_3059_EQ_3059U(...) \, +#define Z_IS_3059U_EQ_3059U(...) \, +#define Z_IS_3060_EQ_3060(...) \, +#define Z_IS_3060U_EQ_3060(...) \, +#define Z_IS_3060_EQ_3060U(...) \, +#define Z_IS_3060U_EQ_3060U(...) \, +#define Z_IS_3061_EQ_3061(...) \, +#define Z_IS_3061U_EQ_3061(...) \, +#define Z_IS_3061_EQ_3061U(...) \, +#define Z_IS_3061U_EQ_3061U(...) \, +#define Z_IS_3062_EQ_3062(...) \, +#define Z_IS_3062U_EQ_3062(...) \, +#define Z_IS_3062_EQ_3062U(...) \, +#define Z_IS_3062U_EQ_3062U(...) \, +#define Z_IS_3063_EQ_3063(...) \, +#define Z_IS_3063U_EQ_3063(...) \, +#define Z_IS_3063_EQ_3063U(...) \, +#define Z_IS_3063U_EQ_3063U(...) \, +#define Z_IS_3064_EQ_3064(...) \, +#define Z_IS_3064U_EQ_3064(...) \, +#define Z_IS_3064_EQ_3064U(...) \, +#define Z_IS_3064U_EQ_3064U(...) \, +#define Z_IS_3065_EQ_3065(...) \, +#define Z_IS_3065U_EQ_3065(...) \, +#define Z_IS_3065_EQ_3065U(...) \, +#define Z_IS_3065U_EQ_3065U(...) \, +#define Z_IS_3066_EQ_3066(...) \, +#define Z_IS_3066U_EQ_3066(...) \, +#define Z_IS_3066_EQ_3066U(...) \, +#define Z_IS_3066U_EQ_3066U(...) \, +#define Z_IS_3067_EQ_3067(...) \, +#define Z_IS_3067U_EQ_3067(...) \, +#define Z_IS_3067_EQ_3067U(...) \, +#define Z_IS_3067U_EQ_3067U(...) \, +#define Z_IS_3068_EQ_3068(...) \, +#define Z_IS_3068U_EQ_3068(...) \, +#define Z_IS_3068_EQ_3068U(...) \, +#define Z_IS_3068U_EQ_3068U(...) \, +#define Z_IS_3069_EQ_3069(...) \, +#define Z_IS_3069U_EQ_3069(...) \, +#define Z_IS_3069_EQ_3069U(...) \, +#define Z_IS_3069U_EQ_3069U(...) \, +#define Z_IS_3070_EQ_3070(...) \, +#define Z_IS_3070U_EQ_3070(...) \, +#define Z_IS_3070_EQ_3070U(...) \, +#define Z_IS_3070U_EQ_3070U(...) \, +#define Z_IS_3071_EQ_3071(...) \, +#define Z_IS_3071U_EQ_3071(...) \, +#define Z_IS_3071_EQ_3071U(...) \, +#define Z_IS_3071U_EQ_3071U(...) \, +#define Z_IS_3072_EQ_3072(...) \, +#define Z_IS_3072U_EQ_3072(...) \, +#define Z_IS_3072_EQ_3072U(...) \, +#define Z_IS_3072U_EQ_3072U(...) \, +#define Z_IS_3073_EQ_3073(...) \, +#define Z_IS_3073U_EQ_3073(...) \, +#define Z_IS_3073_EQ_3073U(...) \, +#define Z_IS_3073U_EQ_3073U(...) \, +#define Z_IS_3074_EQ_3074(...) \, +#define Z_IS_3074U_EQ_3074(...) \, +#define Z_IS_3074_EQ_3074U(...) \, +#define Z_IS_3074U_EQ_3074U(...) \, +#define Z_IS_3075_EQ_3075(...) \, +#define Z_IS_3075U_EQ_3075(...) \, +#define Z_IS_3075_EQ_3075U(...) \, +#define Z_IS_3075U_EQ_3075U(...) \, +#define Z_IS_3076_EQ_3076(...) \, +#define Z_IS_3076U_EQ_3076(...) \, +#define Z_IS_3076_EQ_3076U(...) \, +#define Z_IS_3076U_EQ_3076U(...) \, +#define Z_IS_3077_EQ_3077(...) \, +#define Z_IS_3077U_EQ_3077(...) \, +#define Z_IS_3077_EQ_3077U(...) \, +#define Z_IS_3077U_EQ_3077U(...) \, +#define Z_IS_3078_EQ_3078(...) \, +#define Z_IS_3078U_EQ_3078(...) \, +#define Z_IS_3078_EQ_3078U(...) \, +#define Z_IS_3078U_EQ_3078U(...) \, +#define Z_IS_3079_EQ_3079(...) \, +#define Z_IS_3079U_EQ_3079(...) \, +#define Z_IS_3079_EQ_3079U(...) \, +#define Z_IS_3079U_EQ_3079U(...) \, +#define Z_IS_3080_EQ_3080(...) \, +#define Z_IS_3080U_EQ_3080(...) \, +#define Z_IS_3080_EQ_3080U(...) \, +#define Z_IS_3080U_EQ_3080U(...) \, +#define Z_IS_3081_EQ_3081(...) \, +#define Z_IS_3081U_EQ_3081(...) \, +#define Z_IS_3081_EQ_3081U(...) \, +#define Z_IS_3081U_EQ_3081U(...) \, +#define Z_IS_3082_EQ_3082(...) \, +#define Z_IS_3082U_EQ_3082(...) \, +#define Z_IS_3082_EQ_3082U(...) \, +#define Z_IS_3082U_EQ_3082U(...) \, +#define Z_IS_3083_EQ_3083(...) \, +#define Z_IS_3083U_EQ_3083(...) \, +#define Z_IS_3083_EQ_3083U(...) \, +#define Z_IS_3083U_EQ_3083U(...) \, +#define Z_IS_3084_EQ_3084(...) \, +#define Z_IS_3084U_EQ_3084(...) \, +#define Z_IS_3084_EQ_3084U(...) \, +#define Z_IS_3084U_EQ_3084U(...) \, +#define Z_IS_3085_EQ_3085(...) \, +#define Z_IS_3085U_EQ_3085(...) \, +#define Z_IS_3085_EQ_3085U(...) \, +#define Z_IS_3085U_EQ_3085U(...) \, +#define Z_IS_3086_EQ_3086(...) \, +#define Z_IS_3086U_EQ_3086(...) \, +#define Z_IS_3086_EQ_3086U(...) \, +#define Z_IS_3086U_EQ_3086U(...) \, +#define Z_IS_3087_EQ_3087(...) \, +#define Z_IS_3087U_EQ_3087(...) \, +#define Z_IS_3087_EQ_3087U(...) \, +#define Z_IS_3087U_EQ_3087U(...) \, +#define Z_IS_3088_EQ_3088(...) \, +#define Z_IS_3088U_EQ_3088(...) \, +#define Z_IS_3088_EQ_3088U(...) \, +#define Z_IS_3088U_EQ_3088U(...) \, +#define Z_IS_3089_EQ_3089(...) \, +#define Z_IS_3089U_EQ_3089(...) \, +#define Z_IS_3089_EQ_3089U(...) \, +#define Z_IS_3089U_EQ_3089U(...) \, +#define Z_IS_3090_EQ_3090(...) \, +#define Z_IS_3090U_EQ_3090(...) \, +#define Z_IS_3090_EQ_3090U(...) \, +#define Z_IS_3090U_EQ_3090U(...) \, +#define Z_IS_3091_EQ_3091(...) \, +#define Z_IS_3091U_EQ_3091(...) \, +#define Z_IS_3091_EQ_3091U(...) \, +#define Z_IS_3091U_EQ_3091U(...) \, +#define Z_IS_3092_EQ_3092(...) \, +#define Z_IS_3092U_EQ_3092(...) \, +#define Z_IS_3092_EQ_3092U(...) \, +#define Z_IS_3092U_EQ_3092U(...) \, +#define Z_IS_3093_EQ_3093(...) \, +#define Z_IS_3093U_EQ_3093(...) \, +#define Z_IS_3093_EQ_3093U(...) \, +#define Z_IS_3093U_EQ_3093U(...) \, +#define Z_IS_3094_EQ_3094(...) \, +#define Z_IS_3094U_EQ_3094(...) \, +#define Z_IS_3094_EQ_3094U(...) \, +#define Z_IS_3094U_EQ_3094U(...) \, +#define Z_IS_3095_EQ_3095(...) \, +#define Z_IS_3095U_EQ_3095(...) \, +#define Z_IS_3095_EQ_3095U(...) \, +#define Z_IS_3095U_EQ_3095U(...) \, +#define Z_IS_3096_EQ_3096(...) \, +#define Z_IS_3096U_EQ_3096(...) \, +#define Z_IS_3096_EQ_3096U(...) \, +#define Z_IS_3096U_EQ_3096U(...) \, +#define Z_IS_3097_EQ_3097(...) \, +#define Z_IS_3097U_EQ_3097(...) \, +#define Z_IS_3097_EQ_3097U(...) \, +#define Z_IS_3097U_EQ_3097U(...) \, +#define Z_IS_3098_EQ_3098(...) \, +#define Z_IS_3098U_EQ_3098(...) \, +#define Z_IS_3098_EQ_3098U(...) \, +#define Z_IS_3098U_EQ_3098U(...) \, +#define Z_IS_3099_EQ_3099(...) \, +#define Z_IS_3099U_EQ_3099(...) \, +#define Z_IS_3099_EQ_3099U(...) \, +#define Z_IS_3099U_EQ_3099U(...) \, +#define Z_IS_3100_EQ_3100(...) \, +#define Z_IS_3100U_EQ_3100(...) \, +#define Z_IS_3100_EQ_3100U(...) \, +#define Z_IS_3100U_EQ_3100U(...) \, +#define Z_IS_3101_EQ_3101(...) \, +#define Z_IS_3101U_EQ_3101(...) \, +#define Z_IS_3101_EQ_3101U(...) \, +#define Z_IS_3101U_EQ_3101U(...) \, +#define Z_IS_3102_EQ_3102(...) \, +#define Z_IS_3102U_EQ_3102(...) \, +#define Z_IS_3102_EQ_3102U(...) \, +#define Z_IS_3102U_EQ_3102U(...) \, +#define Z_IS_3103_EQ_3103(...) \, +#define Z_IS_3103U_EQ_3103(...) \, +#define Z_IS_3103_EQ_3103U(...) \, +#define Z_IS_3103U_EQ_3103U(...) \, +#define Z_IS_3104_EQ_3104(...) \, +#define Z_IS_3104U_EQ_3104(...) \, +#define Z_IS_3104_EQ_3104U(...) \, +#define Z_IS_3104U_EQ_3104U(...) \, +#define Z_IS_3105_EQ_3105(...) \, +#define Z_IS_3105U_EQ_3105(...) \, +#define Z_IS_3105_EQ_3105U(...) \, +#define Z_IS_3105U_EQ_3105U(...) \, +#define Z_IS_3106_EQ_3106(...) \, +#define Z_IS_3106U_EQ_3106(...) \, +#define Z_IS_3106_EQ_3106U(...) \, +#define Z_IS_3106U_EQ_3106U(...) \, +#define Z_IS_3107_EQ_3107(...) \, +#define Z_IS_3107U_EQ_3107(...) \, +#define Z_IS_3107_EQ_3107U(...) \, +#define Z_IS_3107U_EQ_3107U(...) \, +#define Z_IS_3108_EQ_3108(...) \, +#define Z_IS_3108U_EQ_3108(...) \, +#define Z_IS_3108_EQ_3108U(...) \, +#define Z_IS_3108U_EQ_3108U(...) \, +#define Z_IS_3109_EQ_3109(...) \, +#define Z_IS_3109U_EQ_3109(...) \, +#define Z_IS_3109_EQ_3109U(...) \, +#define Z_IS_3109U_EQ_3109U(...) \, +#define Z_IS_3110_EQ_3110(...) \, +#define Z_IS_3110U_EQ_3110(...) \, +#define Z_IS_3110_EQ_3110U(...) \, +#define Z_IS_3110U_EQ_3110U(...) \, +#define Z_IS_3111_EQ_3111(...) \, +#define Z_IS_3111U_EQ_3111(...) \, +#define Z_IS_3111_EQ_3111U(...) \, +#define Z_IS_3111U_EQ_3111U(...) \, +#define Z_IS_3112_EQ_3112(...) \, +#define Z_IS_3112U_EQ_3112(...) \, +#define Z_IS_3112_EQ_3112U(...) \, +#define Z_IS_3112U_EQ_3112U(...) \, +#define Z_IS_3113_EQ_3113(...) \, +#define Z_IS_3113U_EQ_3113(...) \, +#define Z_IS_3113_EQ_3113U(...) \, +#define Z_IS_3113U_EQ_3113U(...) \, +#define Z_IS_3114_EQ_3114(...) \, +#define Z_IS_3114U_EQ_3114(...) \, +#define Z_IS_3114_EQ_3114U(...) \, +#define Z_IS_3114U_EQ_3114U(...) \, +#define Z_IS_3115_EQ_3115(...) \, +#define Z_IS_3115U_EQ_3115(...) \, +#define Z_IS_3115_EQ_3115U(...) \, +#define Z_IS_3115U_EQ_3115U(...) \, +#define Z_IS_3116_EQ_3116(...) \, +#define Z_IS_3116U_EQ_3116(...) \, +#define Z_IS_3116_EQ_3116U(...) \, +#define Z_IS_3116U_EQ_3116U(...) \, +#define Z_IS_3117_EQ_3117(...) \, +#define Z_IS_3117U_EQ_3117(...) \, +#define Z_IS_3117_EQ_3117U(...) \, +#define Z_IS_3117U_EQ_3117U(...) \, +#define Z_IS_3118_EQ_3118(...) \, +#define Z_IS_3118U_EQ_3118(...) \, +#define Z_IS_3118_EQ_3118U(...) \, +#define Z_IS_3118U_EQ_3118U(...) \, +#define Z_IS_3119_EQ_3119(...) \, +#define Z_IS_3119U_EQ_3119(...) \, +#define Z_IS_3119_EQ_3119U(...) \, +#define Z_IS_3119U_EQ_3119U(...) \, +#define Z_IS_3120_EQ_3120(...) \, +#define Z_IS_3120U_EQ_3120(...) \, +#define Z_IS_3120_EQ_3120U(...) \, +#define Z_IS_3120U_EQ_3120U(...) \, +#define Z_IS_3121_EQ_3121(...) \, +#define Z_IS_3121U_EQ_3121(...) \, +#define Z_IS_3121_EQ_3121U(...) \, +#define Z_IS_3121U_EQ_3121U(...) \, +#define Z_IS_3122_EQ_3122(...) \, +#define Z_IS_3122U_EQ_3122(...) \, +#define Z_IS_3122_EQ_3122U(...) \, +#define Z_IS_3122U_EQ_3122U(...) \, +#define Z_IS_3123_EQ_3123(...) \, +#define Z_IS_3123U_EQ_3123(...) \, +#define Z_IS_3123_EQ_3123U(...) \, +#define Z_IS_3123U_EQ_3123U(...) \, +#define Z_IS_3124_EQ_3124(...) \, +#define Z_IS_3124U_EQ_3124(...) \, +#define Z_IS_3124_EQ_3124U(...) \, +#define Z_IS_3124U_EQ_3124U(...) \, +#define Z_IS_3125_EQ_3125(...) \, +#define Z_IS_3125U_EQ_3125(...) \, +#define Z_IS_3125_EQ_3125U(...) \, +#define Z_IS_3125U_EQ_3125U(...) \, +#define Z_IS_3126_EQ_3126(...) \, +#define Z_IS_3126U_EQ_3126(...) \, +#define Z_IS_3126_EQ_3126U(...) \, +#define Z_IS_3126U_EQ_3126U(...) \, +#define Z_IS_3127_EQ_3127(...) \, +#define Z_IS_3127U_EQ_3127(...) \, +#define Z_IS_3127_EQ_3127U(...) \, +#define Z_IS_3127U_EQ_3127U(...) \, +#define Z_IS_3128_EQ_3128(...) \, +#define Z_IS_3128U_EQ_3128(...) \, +#define Z_IS_3128_EQ_3128U(...) \, +#define Z_IS_3128U_EQ_3128U(...) \, +#define Z_IS_3129_EQ_3129(...) \, +#define Z_IS_3129U_EQ_3129(...) \, +#define Z_IS_3129_EQ_3129U(...) \, +#define Z_IS_3129U_EQ_3129U(...) \, +#define Z_IS_3130_EQ_3130(...) \, +#define Z_IS_3130U_EQ_3130(...) \, +#define Z_IS_3130_EQ_3130U(...) \, +#define Z_IS_3130U_EQ_3130U(...) \, +#define Z_IS_3131_EQ_3131(...) \, +#define Z_IS_3131U_EQ_3131(...) \, +#define Z_IS_3131_EQ_3131U(...) \, +#define Z_IS_3131U_EQ_3131U(...) \, +#define Z_IS_3132_EQ_3132(...) \, +#define Z_IS_3132U_EQ_3132(...) \, +#define Z_IS_3132_EQ_3132U(...) \, +#define Z_IS_3132U_EQ_3132U(...) \, +#define Z_IS_3133_EQ_3133(...) \, +#define Z_IS_3133U_EQ_3133(...) \, +#define Z_IS_3133_EQ_3133U(...) \, +#define Z_IS_3133U_EQ_3133U(...) \, +#define Z_IS_3134_EQ_3134(...) \, +#define Z_IS_3134U_EQ_3134(...) \, +#define Z_IS_3134_EQ_3134U(...) \, +#define Z_IS_3134U_EQ_3134U(...) \, +#define Z_IS_3135_EQ_3135(...) \, +#define Z_IS_3135U_EQ_3135(...) \, +#define Z_IS_3135_EQ_3135U(...) \, +#define Z_IS_3135U_EQ_3135U(...) \, +#define Z_IS_3136_EQ_3136(...) \, +#define Z_IS_3136U_EQ_3136(...) \, +#define Z_IS_3136_EQ_3136U(...) \, +#define Z_IS_3136U_EQ_3136U(...) \, +#define Z_IS_3137_EQ_3137(...) \, +#define Z_IS_3137U_EQ_3137(...) \, +#define Z_IS_3137_EQ_3137U(...) \, +#define Z_IS_3137U_EQ_3137U(...) \, +#define Z_IS_3138_EQ_3138(...) \, +#define Z_IS_3138U_EQ_3138(...) \, +#define Z_IS_3138_EQ_3138U(...) \, +#define Z_IS_3138U_EQ_3138U(...) \, +#define Z_IS_3139_EQ_3139(...) \, +#define Z_IS_3139U_EQ_3139(...) \, +#define Z_IS_3139_EQ_3139U(...) \, +#define Z_IS_3139U_EQ_3139U(...) \, +#define Z_IS_3140_EQ_3140(...) \, +#define Z_IS_3140U_EQ_3140(...) \, +#define Z_IS_3140_EQ_3140U(...) \, +#define Z_IS_3140U_EQ_3140U(...) \, +#define Z_IS_3141_EQ_3141(...) \, +#define Z_IS_3141U_EQ_3141(...) \, +#define Z_IS_3141_EQ_3141U(...) \, +#define Z_IS_3141U_EQ_3141U(...) \, +#define Z_IS_3142_EQ_3142(...) \, +#define Z_IS_3142U_EQ_3142(...) \, +#define Z_IS_3142_EQ_3142U(...) \, +#define Z_IS_3142U_EQ_3142U(...) \, +#define Z_IS_3143_EQ_3143(...) \, +#define Z_IS_3143U_EQ_3143(...) \, +#define Z_IS_3143_EQ_3143U(...) \, +#define Z_IS_3143U_EQ_3143U(...) \, +#define Z_IS_3144_EQ_3144(...) \, +#define Z_IS_3144U_EQ_3144(...) \, +#define Z_IS_3144_EQ_3144U(...) \, +#define Z_IS_3144U_EQ_3144U(...) \, +#define Z_IS_3145_EQ_3145(...) \, +#define Z_IS_3145U_EQ_3145(...) \, +#define Z_IS_3145_EQ_3145U(...) \, +#define Z_IS_3145U_EQ_3145U(...) \, +#define Z_IS_3146_EQ_3146(...) \, +#define Z_IS_3146U_EQ_3146(...) \, +#define Z_IS_3146_EQ_3146U(...) \, +#define Z_IS_3146U_EQ_3146U(...) \, +#define Z_IS_3147_EQ_3147(...) \, +#define Z_IS_3147U_EQ_3147(...) \, +#define Z_IS_3147_EQ_3147U(...) \, +#define Z_IS_3147U_EQ_3147U(...) \, +#define Z_IS_3148_EQ_3148(...) \, +#define Z_IS_3148U_EQ_3148(...) \, +#define Z_IS_3148_EQ_3148U(...) \, +#define Z_IS_3148U_EQ_3148U(...) \, +#define Z_IS_3149_EQ_3149(...) \, +#define Z_IS_3149U_EQ_3149(...) \, +#define Z_IS_3149_EQ_3149U(...) \, +#define Z_IS_3149U_EQ_3149U(...) \, +#define Z_IS_3150_EQ_3150(...) \, +#define Z_IS_3150U_EQ_3150(...) \, +#define Z_IS_3150_EQ_3150U(...) \, +#define Z_IS_3150U_EQ_3150U(...) \, +#define Z_IS_3151_EQ_3151(...) \, +#define Z_IS_3151U_EQ_3151(...) \, +#define Z_IS_3151_EQ_3151U(...) \, +#define Z_IS_3151U_EQ_3151U(...) \, +#define Z_IS_3152_EQ_3152(...) \, +#define Z_IS_3152U_EQ_3152(...) \, +#define Z_IS_3152_EQ_3152U(...) \, +#define Z_IS_3152U_EQ_3152U(...) \, +#define Z_IS_3153_EQ_3153(...) \, +#define Z_IS_3153U_EQ_3153(...) \, +#define Z_IS_3153_EQ_3153U(...) \, +#define Z_IS_3153U_EQ_3153U(...) \, +#define Z_IS_3154_EQ_3154(...) \, +#define Z_IS_3154U_EQ_3154(...) \, +#define Z_IS_3154_EQ_3154U(...) \, +#define Z_IS_3154U_EQ_3154U(...) \, +#define Z_IS_3155_EQ_3155(...) \, +#define Z_IS_3155U_EQ_3155(...) \, +#define Z_IS_3155_EQ_3155U(...) \, +#define Z_IS_3155U_EQ_3155U(...) \, +#define Z_IS_3156_EQ_3156(...) \, +#define Z_IS_3156U_EQ_3156(...) \, +#define Z_IS_3156_EQ_3156U(...) \, +#define Z_IS_3156U_EQ_3156U(...) \, +#define Z_IS_3157_EQ_3157(...) \, +#define Z_IS_3157U_EQ_3157(...) \, +#define Z_IS_3157_EQ_3157U(...) \, +#define Z_IS_3157U_EQ_3157U(...) \, +#define Z_IS_3158_EQ_3158(...) \, +#define Z_IS_3158U_EQ_3158(...) \, +#define Z_IS_3158_EQ_3158U(...) \, +#define Z_IS_3158U_EQ_3158U(...) \, +#define Z_IS_3159_EQ_3159(...) \, +#define Z_IS_3159U_EQ_3159(...) \, +#define Z_IS_3159_EQ_3159U(...) \, +#define Z_IS_3159U_EQ_3159U(...) \, +#define Z_IS_3160_EQ_3160(...) \, +#define Z_IS_3160U_EQ_3160(...) \, +#define Z_IS_3160_EQ_3160U(...) \, +#define Z_IS_3160U_EQ_3160U(...) \, +#define Z_IS_3161_EQ_3161(...) \, +#define Z_IS_3161U_EQ_3161(...) \, +#define Z_IS_3161_EQ_3161U(...) \, +#define Z_IS_3161U_EQ_3161U(...) \, +#define Z_IS_3162_EQ_3162(...) \, +#define Z_IS_3162U_EQ_3162(...) \, +#define Z_IS_3162_EQ_3162U(...) \, +#define Z_IS_3162U_EQ_3162U(...) \, +#define Z_IS_3163_EQ_3163(...) \, +#define Z_IS_3163U_EQ_3163(...) \, +#define Z_IS_3163_EQ_3163U(...) \, +#define Z_IS_3163U_EQ_3163U(...) \, +#define Z_IS_3164_EQ_3164(...) \, +#define Z_IS_3164U_EQ_3164(...) \, +#define Z_IS_3164_EQ_3164U(...) \, +#define Z_IS_3164U_EQ_3164U(...) \, +#define Z_IS_3165_EQ_3165(...) \, +#define Z_IS_3165U_EQ_3165(...) \, +#define Z_IS_3165_EQ_3165U(...) \, +#define Z_IS_3165U_EQ_3165U(...) \, +#define Z_IS_3166_EQ_3166(...) \, +#define Z_IS_3166U_EQ_3166(...) \, +#define Z_IS_3166_EQ_3166U(...) \, +#define Z_IS_3166U_EQ_3166U(...) \, +#define Z_IS_3167_EQ_3167(...) \, +#define Z_IS_3167U_EQ_3167(...) \, +#define Z_IS_3167_EQ_3167U(...) \, +#define Z_IS_3167U_EQ_3167U(...) \, +#define Z_IS_3168_EQ_3168(...) \, +#define Z_IS_3168U_EQ_3168(...) \, +#define Z_IS_3168_EQ_3168U(...) \, +#define Z_IS_3168U_EQ_3168U(...) \, +#define Z_IS_3169_EQ_3169(...) \, +#define Z_IS_3169U_EQ_3169(...) \, +#define Z_IS_3169_EQ_3169U(...) \, +#define Z_IS_3169U_EQ_3169U(...) \, +#define Z_IS_3170_EQ_3170(...) \, +#define Z_IS_3170U_EQ_3170(...) \, +#define Z_IS_3170_EQ_3170U(...) \, +#define Z_IS_3170U_EQ_3170U(...) \, +#define Z_IS_3171_EQ_3171(...) \, +#define Z_IS_3171U_EQ_3171(...) \, +#define Z_IS_3171_EQ_3171U(...) \, +#define Z_IS_3171U_EQ_3171U(...) \, +#define Z_IS_3172_EQ_3172(...) \, +#define Z_IS_3172U_EQ_3172(...) \, +#define Z_IS_3172_EQ_3172U(...) \, +#define Z_IS_3172U_EQ_3172U(...) \, +#define Z_IS_3173_EQ_3173(...) \, +#define Z_IS_3173U_EQ_3173(...) \, +#define Z_IS_3173_EQ_3173U(...) \, +#define Z_IS_3173U_EQ_3173U(...) \, +#define Z_IS_3174_EQ_3174(...) \, +#define Z_IS_3174U_EQ_3174(...) \, +#define Z_IS_3174_EQ_3174U(...) \, +#define Z_IS_3174U_EQ_3174U(...) \, +#define Z_IS_3175_EQ_3175(...) \, +#define Z_IS_3175U_EQ_3175(...) \, +#define Z_IS_3175_EQ_3175U(...) \, +#define Z_IS_3175U_EQ_3175U(...) \, +#define Z_IS_3176_EQ_3176(...) \, +#define Z_IS_3176U_EQ_3176(...) \, +#define Z_IS_3176_EQ_3176U(...) \, +#define Z_IS_3176U_EQ_3176U(...) \, +#define Z_IS_3177_EQ_3177(...) \, +#define Z_IS_3177U_EQ_3177(...) \, +#define Z_IS_3177_EQ_3177U(...) \, +#define Z_IS_3177U_EQ_3177U(...) \, +#define Z_IS_3178_EQ_3178(...) \, +#define Z_IS_3178U_EQ_3178(...) \, +#define Z_IS_3178_EQ_3178U(...) \, +#define Z_IS_3178U_EQ_3178U(...) \, +#define Z_IS_3179_EQ_3179(...) \, +#define Z_IS_3179U_EQ_3179(...) \, +#define Z_IS_3179_EQ_3179U(...) \, +#define Z_IS_3179U_EQ_3179U(...) \, +#define Z_IS_3180_EQ_3180(...) \, +#define Z_IS_3180U_EQ_3180(...) \, +#define Z_IS_3180_EQ_3180U(...) \, +#define Z_IS_3180U_EQ_3180U(...) \, +#define Z_IS_3181_EQ_3181(...) \, +#define Z_IS_3181U_EQ_3181(...) \, +#define Z_IS_3181_EQ_3181U(...) \, +#define Z_IS_3181U_EQ_3181U(...) \, +#define Z_IS_3182_EQ_3182(...) \, +#define Z_IS_3182U_EQ_3182(...) \, +#define Z_IS_3182_EQ_3182U(...) \, +#define Z_IS_3182U_EQ_3182U(...) \, +#define Z_IS_3183_EQ_3183(...) \, +#define Z_IS_3183U_EQ_3183(...) \, +#define Z_IS_3183_EQ_3183U(...) \, +#define Z_IS_3183U_EQ_3183U(...) \, +#define Z_IS_3184_EQ_3184(...) \, +#define Z_IS_3184U_EQ_3184(...) \, +#define Z_IS_3184_EQ_3184U(...) \, +#define Z_IS_3184U_EQ_3184U(...) \, +#define Z_IS_3185_EQ_3185(...) \, +#define Z_IS_3185U_EQ_3185(...) \, +#define Z_IS_3185_EQ_3185U(...) \, +#define Z_IS_3185U_EQ_3185U(...) \, +#define Z_IS_3186_EQ_3186(...) \, +#define Z_IS_3186U_EQ_3186(...) \, +#define Z_IS_3186_EQ_3186U(...) \, +#define Z_IS_3186U_EQ_3186U(...) \, +#define Z_IS_3187_EQ_3187(...) \, +#define Z_IS_3187U_EQ_3187(...) \, +#define Z_IS_3187_EQ_3187U(...) \, +#define Z_IS_3187U_EQ_3187U(...) \, +#define Z_IS_3188_EQ_3188(...) \, +#define Z_IS_3188U_EQ_3188(...) \, +#define Z_IS_3188_EQ_3188U(...) \, +#define Z_IS_3188U_EQ_3188U(...) \, +#define Z_IS_3189_EQ_3189(...) \, +#define Z_IS_3189U_EQ_3189(...) \, +#define Z_IS_3189_EQ_3189U(...) \, +#define Z_IS_3189U_EQ_3189U(...) \, +#define Z_IS_3190_EQ_3190(...) \, +#define Z_IS_3190U_EQ_3190(...) \, +#define Z_IS_3190_EQ_3190U(...) \, +#define Z_IS_3190U_EQ_3190U(...) \, +#define Z_IS_3191_EQ_3191(...) \, +#define Z_IS_3191U_EQ_3191(...) \, +#define Z_IS_3191_EQ_3191U(...) \, +#define Z_IS_3191U_EQ_3191U(...) \, +#define Z_IS_3192_EQ_3192(...) \, +#define Z_IS_3192U_EQ_3192(...) \, +#define Z_IS_3192_EQ_3192U(...) \, +#define Z_IS_3192U_EQ_3192U(...) \, +#define Z_IS_3193_EQ_3193(...) \, +#define Z_IS_3193U_EQ_3193(...) \, +#define Z_IS_3193_EQ_3193U(...) \, +#define Z_IS_3193U_EQ_3193U(...) \, +#define Z_IS_3194_EQ_3194(...) \, +#define Z_IS_3194U_EQ_3194(...) \, +#define Z_IS_3194_EQ_3194U(...) \, +#define Z_IS_3194U_EQ_3194U(...) \, +#define Z_IS_3195_EQ_3195(...) \, +#define Z_IS_3195U_EQ_3195(...) \, +#define Z_IS_3195_EQ_3195U(...) \, +#define Z_IS_3195U_EQ_3195U(...) \, +#define Z_IS_3196_EQ_3196(...) \, +#define Z_IS_3196U_EQ_3196(...) \, +#define Z_IS_3196_EQ_3196U(...) \, +#define Z_IS_3196U_EQ_3196U(...) \, +#define Z_IS_3197_EQ_3197(...) \, +#define Z_IS_3197U_EQ_3197(...) \, +#define Z_IS_3197_EQ_3197U(...) \, +#define Z_IS_3197U_EQ_3197U(...) \, +#define Z_IS_3198_EQ_3198(...) \, +#define Z_IS_3198U_EQ_3198(...) \, +#define Z_IS_3198_EQ_3198U(...) \, +#define Z_IS_3198U_EQ_3198U(...) \, +#define Z_IS_3199_EQ_3199(...) \, +#define Z_IS_3199U_EQ_3199(...) \, +#define Z_IS_3199_EQ_3199U(...) \, +#define Z_IS_3199U_EQ_3199U(...) \, +#define Z_IS_3200_EQ_3200(...) \, +#define Z_IS_3200U_EQ_3200(...) \, +#define Z_IS_3200_EQ_3200U(...) \, +#define Z_IS_3200U_EQ_3200U(...) \, +#define Z_IS_3201_EQ_3201(...) \, +#define Z_IS_3201U_EQ_3201(...) \, +#define Z_IS_3201_EQ_3201U(...) \, +#define Z_IS_3201U_EQ_3201U(...) \, +#define Z_IS_3202_EQ_3202(...) \, +#define Z_IS_3202U_EQ_3202(...) \, +#define Z_IS_3202_EQ_3202U(...) \, +#define Z_IS_3202U_EQ_3202U(...) \, +#define Z_IS_3203_EQ_3203(...) \, +#define Z_IS_3203U_EQ_3203(...) \, +#define Z_IS_3203_EQ_3203U(...) \, +#define Z_IS_3203U_EQ_3203U(...) \, +#define Z_IS_3204_EQ_3204(...) \, +#define Z_IS_3204U_EQ_3204(...) \, +#define Z_IS_3204_EQ_3204U(...) \, +#define Z_IS_3204U_EQ_3204U(...) \, +#define Z_IS_3205_EQ_3205(...) \, +#define Z_IS_3205U_EQ_3205(...) \, +#define Z_IS_3205_EQ_3205U(...) \, +#define Z_IS_3205U_EQ_3205U(...) \, +#define Z_IS_3206_EQ_3206(...) \, +#define Z_IS_3206U_EQ_3206(...) \, +#define Z_IS_3206_EQ_3206U(...) \, +#define Z_IS_3206U_EQ_3206U(...) \, +#define Z_IS_3207_EQ_3207(...) \, +#define Z_IS_3207U_EQ_3207(...) \, +#define Z_IS_3207_EQ_3207U(...) \, +#define Z_IS_3207U_EQ_3207U(...) \, +#define Z_IS_3208_EQ_3208(...) \, +#define Z_IS_3208U_EQ_3208(...) \, +#define Z_IS_3208_EQ_3208U(...) \, +#define Z_IS_3208U_EQ_3208U(...) \, +#define Z_IS_3209_EQ_3209(...) \, +#define Z_IS_3209U_EQ_3209(...) \, +#define Z_IS_3209_EQ_3209U(...) \, +#define Z_IS_3209U_EQ_3209U(...) \, +#define Z_IS_3210_EQ_3210(...) \, +#define Z_IS_3210U_EQ_3210(...) \, +#define Z_IS_3210_EQ_3210U(...) \, +#define Z_IS_3210U_EQ_3210U(...) \, +#define Z_IS_3211_EQ_3211(...) \, +#define Z_IS_3211U_EQ_3211(...) \, +#define Z_IS_3211_EQ_3211U(...) \, +#define Z_IS_3211U_EQ_3211U(...) \, +#define Z_IS_3212_EQ_3212(...) \, +#define Z_IS_3212U_EQ_3212(...) \, +#define Z_IS_3212_EQ_3212U(...) \, +#define Z_IS_3212U_EQ_3212U(...) \, +#define Z_IS_3213_EQ_3213(...) \, +#define Z_IS_3213U_EQ_3213(...) \, +#define Z_IS_3213_EQ_3213U(...) \, +#define Z_IS_3213U_EQ_3213U(...) \, +#define Z_IS_3214_EQ_3214(...) \, +#define Z_IS_3214U_EQ_3214(...) \, +#define Z_IS_3214_EQ_3214U(...) \, +#define Z_IS_3214U_EQ_3214U(...) \, +#define Z_IS_3215_EQ_3215(...) \, +#define Z_IS_3215U_EQ_3215(...) \, +#define Z_IS_3215_EQ_3215U(...) \, +#define Z_IS_3215U_EQ_3215U(...) \, +#define Z_IS_3216_EQ_3216(...) \, +#define Z_IS_3216U_EQ_3216(...) \, +#define Z_IS_3216_EQ_3216U(...) \, +#define Z_IS_3216U_EQ_3216U(...) \, +#define Z_IS_3217_EQ_3217(...) \, +#define Z_IS_3217U_EQ_3217(...) \, +#define Z_IS_3217_EQ_3217U(...) \, +#define Z_IS_3217U_EQ_3217U(...) \, +#define Z_IS_3218_EQ_3218(...) \, +#define Z_IS_3218U_EQ_3218(...) \, +#define Z_IS_3218_EQ_3218U(...) \, +#define Z_IS_3218U_EQ_3218U(...) \, +#define Z_IS_3219_EQ_3219(...) \, +#define Z_IS_3219U_EQ_3219(...) \, +#define Z_IS_3219_EQ_3219U(...) \, +#define Z_IS_3219U_EQ_3219U(...) \, +#define Z_IS_3220_EQ_3220(...) \, +#define Z_IS_3220U_EQ_3220(...) \, +#define Z_IS_3220_EQ_3220U(...) \, +#define Z_IS_3220U_EQ_3220U(...) \, +#define Z_IS_3221_EQ_3221(...) \, +#define Z_IS_3221U_EQ_3221(...) \, +#define Z_IS_3221_EQ_3221U(...) \, +#define Z_IS_3221U_EQ_3221U(...) \, +#define Z_IS_3222_EQ_3222(...) \, +#define Z_IS_3222U_EQ_3222(...) \, +#define Z_IS_3222_EQ_3222U(...) \, +#define Z_IS_3222U_EQ_3222U(...) \, +#define Z_IS_3223_EQ_3223(...) \, +#define Z_IS_3223U_EQ_3223(...) \, +#define Z_IS_3223_EQ_3223U(...) \, +#define Z_IS_3223U_EQ_3223U(...) \, +#define Z_IS_3224_EQ_3224(...) \, +#define Z_IS_3224U_EQ_3224(...) \, +#define Z_IS_3224_EQ_3224U(...) \, +#define Z_IS_3224U_EQ_3224U(...) \, +#define Z_IS_3225_EQ_3225(...) \, +#define Z_IS_3225U_EQ_3225(...) \, +#define Z_IS_3225_EQ_3225U(...) \, +#define Z_IS_3225U_EQ_3225U(...) \, +#define Z_IS_3226_EQ_3226(...) \, +#define Z_IS_3226U_EQ_3226(...) \, +#define Z_IS_3226_EQ_3226U(...) \, +#define Z_IS_3226U_EQ_3226U(...) \, +#define Z_IS_3227_EQ_3227(...) \, +#define Z_IS_3227U_EQ_3227(...) \, +#define Z_IS_3227_EQ_3227U(...) \, +#define Z_IS_3227U_EQ_3227U(...) \, +#define Z_IS_3228_EQ_3228(...) \, +#define Z_IS_3228U_EQ_3228(...) \, +#define Z_IS_3228_EQ_3228U(...) \, +#define Z_IS_3228U_EQ_3228U(...) \, +#define Z_IS_3229_EQ_3229(...) \, +#define Z_IS_3229U_EQ_3229(...) \, +#define Z_IS_3229_EQ_3229U(...) \, +#define Z_IS_3229U_EQ_3229U(...) \, +#define Z_IS_3230_EQ_3230(...) \, +#define Z_IS_3230U_EQ_3230(...) \, +#define Z_IS_3230_EQ_3230U(...) \, +#define Z_IS_3230U_EQ_3230U(...) \, +#define Z_IS_3231_EQ_3231(...) \, +#define Z_IS_3231U_EQ_3231(...) \, +#define Z_IS_3231_EQ_3231U(...) \, +#define Z_IS_3231U_EQ_3231U(...) \, +#define Z_IS_3232_EQ_3232(...) \, +#define Z_IS_3232U_EQ_3232(...) \, +#define Z_IS_3232_EQ_3232U(...) \, +#define Z_IS_3232U_EQ_3232U(...) \, +#define Z_IS_3233_EQ_3233(...) \, +#define Z_IS_3233U_EQ_3233(...) \, +#define Z_IS_3233_EQ_3233U(...) \, +#define Z_IS_3233U_EQ_3233U(...) \, +#define Z_IS_3234_EQ_3234(...) \, +#define Z_IS_3234U_EQ_3234(...) \, +#define Z_IS_3234_EQ_3234U(...) \, +#define Z_IS_3234U_EQ_3234U(...) \, +#define Z_IS_3235_EQ_3235(...) \, +#define Z_IS_3235U_EQ_3235(...) \, +#define Z_IS_3235_EQ_3235U(...) \, +#define Z_IS_3235U_EQ_3235U(...) \, +#define Z_IS_3236_EQ_3236(...) \, +#define Z_IS_3236U_EQ_3236(...) \, +#define Z_IS_3236_EQ_3236U(...) \, +#define Z_IS_3236U_EQ_3236U(...) \, +#define Z_IS_3237_EQ_3237(...) \, +#define Z_IS_3237U_EQ_3237(...) \, +#define Z_IS_3237_EQ_3237U(...) \, +#define Z_IS_3237U_EQ_3237U(...) \, +#define Z_IS_3238_EQ_3238(...) \, +#define Z_IS_3238U_EQ_3238(...) \, +#define Z_IS_3238_EQ_3238U(...) \, +#define Z_IS_3238U_EQ_3238U(...) \, +#define Z_IS_3239_EQ_3239(...) \, +#define Z_IS_3239U_EQ_3239(...) \, +#define Z_IS_3239_EQ_3239U(...) \, +#define Z_IS_3239U_EQ_3239U(...) \, +#define Z_IS_3240_EQ_3240(...) \, +#define Z_IS_3240U_EQ_3240(...) \, +#define Z_IS_3240_EQ_3240U(...) \, +#define Z_IS_3240U_EQ_3240U(...) \, +#define Z_IS_3241_EQ_3241(...) \, +#define Z_IS_3241U_EQ_3241(...) \, +#define Z_IS_3241_EQ_3241U(...) \, +#define Z_IS_3241U_EQ_3241U(...) \, +#define Z_IS_3242_EQ_3242(...) \, +#define Z_IS_3242U_EQ_3242(...) \, +#define Z_IS_3242_EQ_3242U(...) \, +#define Z_IS_3242U_EQ_3242U(...) \, +#define Z_IS_3243_EQ_3243(...) \, +#define Z_IS_3243U_EQ_3243(...) \, +#define Z_IS_3243_EQ_3243U(...) \, +#define Z_IS_3243U_EQ_3243U(...) \, +#define Z_IS_3244_EQ_3244(...) \, +#define Z_IS_3244U_EQ_3244(...) \, +#define Z_IS_3244_EQ_3244U(...) \, +#define Z_IS_3244U_EQ_3244U(...) \, +#define Z_IS_3245_EQ_3245(...) \, +#define Z_IS_3245U_EQ_3245(...) \, +#define Z_IS_3245_EQ_3245U(...) \, +#define Z_IS_3245U_EQ_3245U(...) \, +#define Z_IS_3246_EQ_3246(...) \, +#define Z_IS_3246U_EQ_3246(...) \, +#define Z_IS_3246_EQ_3246U(...) \, +#define Z_IS_3246U_EQ_3246U(...) \, +#define Z_IS_3247_EQ_3247(...) \, +#define Z_IS_3247U_EQ_3247(...) \, +#define Z_IS_3247_EQ_3247U(...) \, +#define Z_IS_3247U_EQ_3247U(...) \, +#define Z_IS_3248_EQ_3248(...) \, +#define Z_IS_3248U_EQ_3248(...) \, +#define Z_IS_3248_EQ_3248U(...) \, +#define Z_IS_3248U_EQ_3248U(...) \, +#define Z_IS_3249_EQ_3249(...) \, +#define Z_IS_3249U_EQ_3249(...) \, +#define Z_IS_3249_EQ_3249U(...) \, +#define Z_IS_3249U_EQ_3249U(...) \, +#define Z_IS_3250_EQ_3250(...) \, +#define Z_IS_3250U_EQ_3250(...) \, +#define Z_IS_3250_EQ_3250U(...) \, +#define Z_IS_3250U_EQ_3250U(...) \, +#define Z_IS_3251_EQ_3251(...) \, +#define Z_IS_3251U_EQ_3251(...) \, +#define Z_IS_3251_EQ_3251U(...) \, +#define Z_IS_3251U_EQ_3251U(...) \, +#define Z_IS_3252_EQ_3252(...) \, +#define Z_IS_3252U_EQ_3252(...) \, +#define Z_IS_3252_EQ_3252U(...) \, +#define Z_IS_3252U_EQ_3252U(...) \, +#define Z_IS_3253_EQ_3253(...) \, +#define Z_IS_3253U_EQ_3253(...) \, +#define Z_IS_3253_EQ_3253U(...) \, +#define Z_IS_3253U_EQ_3253U(...) \, +#define Z_IS_3254_EQ_3254(...) \, +#define Z_IS_3254U_EQ_3254(...) \, +#define Z_IS_3254_EQ_3254U(...) \, +#define Z_IS_3254U_EQ_3254U(...) \, +#define Z_IS_3255_EQ_3255(...) \, +#define Z_IS_3255U_EQ_3255(...) \, +#define Z_IS_3255_EQ_3255U(...) \, +#define Z_IS_3255U_EQ_3255U(...) \, +#define Z_IS_3256_EQ_3256(...) \, +#define Z_IS_3256U_EQ_3256(...) \, +#define Z_IS_3256_EQ_3256U(...) \, +#define Z_IS_3256U_EQ_3256U(...) \, +#define Z_IS_3257_EQ_3257(...) \, +#define Z_IS_3257U_EQ_3257(...) \, +#define Z_IS_3257_EQ_3257U(...) \, +#define Z_IS_3257U_EQ_3257U(...) \, +#define Z_IS_3258_EQ_3258(...) \, +#define Z_IS_3258U_EQ_3258(...) \, +#define Z_IS_3258_EQ_3258U(...) \, +#define Z_IS_3258U_EQ_3258U(...) \, +#define Z_IS_3259_EQ_3259(...) \, +#define Z_IS_3259U_EQ_3259(...) \, +#define Z_IS_3259_EQ_3259U(...) \, +#define Z_IS_3259U_EQ_3259U(...) \, +#define Z_IS_3260_EQ_3260(...) \, +#define Z_IS_3260U_EQ_3260(...) \, +#define Z_IS_3260_EQ_3260U(...) \, +#define Z_IS_3260U_EQ_3260U(...) \, +#define Z_IS_3261_EQ_3261(...) \, +#define Z_IS_3261U_EQ_3261(...) \, +#define Z_IS_3261_EQ_3261U(...) \, +#define Z_IS_3261U_EQ_3261U(...) \, +#define Z_IS_3262_EQ_3262(...) \, +#define Z_IS_3262U_EQ_3262(...) \, +#define Z_IS_3262_EQ_3262U(...) \, +#define Z_IS_3262U_EQ_3262U(...) \, +#define Z_IS_3263_EQ_3263(...) \, +#define Z_IS_3263U_EQ_3263(...) \, +#define Z_IS_3263_EQ_3263U(...) \, +#define Z_IS_3263U_EQ_3263U(...) \, +#define Z_IS_3264_EQ_3264(...) \, +#define Z_IS_3264U_EQ_3264(...) \, +#define Z_IS_3264_EQ_3264U(...) \, +#define Z_IS_3264U_EQ_3264U(...) \, +#define Z_IS_3265_EQ_3265(...) \, +#define Z_IS_3265U_EQ_3265(...) \, +#define Z_IS_3265_EQ_3265U(...) \, +#define Z_IS_3265U_EQ_3265U(...) \, +#define Z_IS_3266_EQ_3266(...) \, +#define Z_IS_3266U_EQ_3266(...) \, +#define Z_IS_3266_EQ_3266U(...) \, +#define Z_IS_3266U_EQ_3266U(...) \, +#define Z_IS_3267_EQ_3267(...) \, +#define Z_IS_3267U_EQ_3267(...) \, +#define Z_IS_3267_EQ_3267U(...) \, +#define Z_IS_3267U_EQ_3267U(...) \, +#define Z_IS_3268_EQ_3268(...) \, +#define Z_IS_3268U_EQ_3268(...) \, +#define Z_IS_3268_EQ_3268U(...) \, +#define Z_IS_3268U_EQ_3268U(...) \, +#define Z_IS_3269_EQ_3269(...) \, +#define Z_IS_3269U_EQ_3269(...) \, +#define Z_IS_3269_EQ_3269U(...) \, +#define Z_IS_3269U_EQ_3269U(...) \, +#define Z_IS_3270_EQ_3270(...) \, +#define Z_IS_3270U_EQ_3270(...) \, +#define Z_IS_3270_EQ_3270U(...) \, +#define Z_IS_3270U_EQ_3270U(...) \, +#define Z_IS_3271_EQ_3271(...) \, +#define Z_IS_3271U_EQ_3271(...) \, +#define Z_IS_3271_EQ_3271U(...) \, +#define Z_IS_3271U_EQ_3271U(...) \, +#define Z_IS_3272_EQ_3272(...) \, +#define Z_IS_3272U_EQ_3272(...) \, +#define Z_IS_3272_EQ_3272U(...) \, +#define Z_IS_3272U_EQ_3272U(...) \, +#define Z_IS_3273_EQ_3273(...) \, +#define Z_IS_3273U_EQ_3273(...) \, +#define Z_IS_3273_EQ_3273U(...) \, +#define Z_IS_3273U_EQ_3273U(...) \, +#define Z_IS_3274_EQ_3274(...) \, +#define Z_IS_3274U_EQ_3274(...) \, +#define Z_IS_3274_EQ_3274U(...) \, +#define Z_IS_3274U_EQ_3274U(...) \, +#define Z_IS_3275_EQ_3275(...) \, +#define Z_IS_3275U_EQ_3275(...) \, +#define Z_IS_3275_EQ_3275U(...) \, +#define Z_IS_3275U_EQ_3275U(...) \, +#define Z_IS_3276_EQ_3276(...) \, +#define Z_IS_3276U_EQ_3276(...) \, +#define Z_IS_3276_EQ_3276U(...) \, +#define Z_IS_3276U_EQ_3276U(...) \, +#define Z_IS_3277_EQ_3277(...) \, +#define Z_IS_3277U_EQ_3277(...) \, +#define Z_IS_3277_EQ_3277U(...) \, +#define Z_IS_3277U_EQ_3277U(...) \, +#define Z_IS_3278_EQ_3278(...) \, +#define Z_IS_3278U_EQ_3278(...) \, +#define Z_IS_3278_EQ_3278U(...) \, +#define Z_IS_3278U_EQ_3278U(...) \, +#define Z_IS_3279_EQ_3279(...) \, +#define Z_IS_3279U_EQ_3279(...) \, +#define Z_IS_3279_EQ_3279U(...) \, +#define Z_IS_3279U_EQ_3279U(...) \, +#define Z_IS_3280_EQ_3280(...) \, +#define Z_IS_3280U_EQ_3280(...) \, +#define Z_IS_3280_EQ_3280U(...) \, +#define Z_IS_3280U_EQ_3280U(...) \, +#define Z_IS_3281_EQ_3281(...) \, +#define Z_IS_3281U_EQ_3281(...) \, +#define Z_IS_3281_EQ_3281U(...) \, +#define Z_IS_3281U_EQ_3281U(...) \, +#define Z_IS_3282_EQ_3282(...) \, +#define Z_IS_3282U_EQ_3282(...) \, +#define Z_IS_3282_EQ_3282U(...) \, +#define Z_IS_3282U_EQ_3282U(...) \, +#define Z_IS_3283_EQ_3283(...) \, +#define Z_IS_3283U_EQ_3283(...) \, +#define Z_IS_3283_EQ_3283U(...) \, +#define Z_IS_3283U_EQ_3283U(...) \, +#define Z_IS_3284_EQ_3284(...) \, +#define Z_IS_3284U_EQ_3284(...) \, +#define Z_IS_3284_EQ_3284U(...) \, +#define Z_IS_3284U_EQ_3284U(...) \, +#define Z_IS_3285_EQ_3285(...) \, +#define Z_IS_3285U_EQ_3285(...) \, +#define Z_IS_3285_EQ_3285U(...) \, +#define Z_IS_3285U_EQ_3285U(...) \, +#define Z_IS_3286_EQ_3286(...) \, +#define Z_IS_3286U_EQ_3286(...) \, +#define Z_IS_3286_EQ_3286U(...) \, +#define Z_IS_3286U_EQ_3286U(...) \, +#define Z_IS_3287_EQ_3287(...) \, +#define Z_IS_3287U_EQ_3287(...) \, +#define Z_IS_3287_EQ_3287U(...) \, +#define Z_IS_3287U_EQ_3287U(...) \, +#define Z_IS_3288_EQ_3288(...) \, +#define Z_IS_3288U_EQ_3288(...) \, +#define Z_IS_3288_EQ_3288U(...) \, +#define Z_IS_3288U_EQ_3288U(...) \, +#define Z_IS_3289_EQ_3289(...) \, +#define Z_IS_3289U_EQ_3289(...) \, +#define Z_IS_3289_EQ_3289U(...) \, +#define Z_IS_3289U_EQ_3289U(...) \, +#define Z_IS_3290_EQ_3290(...) \, +#define Z_IS_3290U_EQ_3290(...) \, +#define Z_IS_3290_EQ_3290U(...) \, +#define Z_IS_3290U_EQ_3290U(...) \, +#define Z_IS_3291_EQ_3291(...) \, +#define Z_IS_3291U_EQ_3291(...) \, +#define Z_IS_3291_EQ_3291U(...) \, +#define Z_IS_3291U_EQ_3291U(...) \, +#define Z_IS_3292_EQ_3292(...) \, +#define Z_IS_3292U_EQ_3292(...) \, +#define Z_IS_3292_EQ_3292U(...) \, +#define Z_IS_3292U_EQ_3292U(...) \, +#define Z_IS_3293_EQ_3293(...) \, +#define Z_IS_3293U_EQ_3293(...) \, +#define Z_IS_3293_EQ_3293U(...) \, +#define Z_IS_3293U_EQ_3293U(...) \, +#define Z_IS_3294_EQ_3294(...) \, +#define Z_IS_3294U_EQ_3294(...) \, +#define Z_IS_3294_EQ_3294U(...) \, +#define Z_IS_3294U_EQ_3294U(...) \, +#define Z_IS_3295_EQ_3295(...) \, +#define Z_IS_3295U_EQ_3295(...) \, +#define Z_IS_3295_EQ_3295U(...) \, +#define Z_IS_3295U_EQ_3295U(...) \, +#define Z_IS_3296_EQ_3296(...) \, +#define Z_IS_3296U_EQ_3296(...) \, +#define Z_IS_3296_EQ_3296U(...) \, +#define Z_IS_3296U_EQ_3296U(...) \, +#define Z_IS_3297_EQ_3297(...) \, +#define Z_IS_3297U_EQ_3297(...) \, +#define Z_IS_3297_EQ_3297U(...) \, +#define Z_IS_3297U_EQ_3297U(...) \, +#define Z_IS_3298_EQ_3298(...) \, +#define Z_IS_3298U_EQ_3298(...) \, +#define Z_IS_3298_EQ_3298U(...) \, +#define Z_IS_3298U_EQ_3298U(...) \, +#define Z_IS_3299_EQ_3299(...) \, +#define Z_IS_3299U_EQ_3299(...) \, +#define Z_IS_3299_EQ_3299U(...) \, +#define Z_IS_3299U_EQ_3299U(...) \, +#define Z_IS_3300_EQ_3300(...) \, +#define Z_IS_3300U_EQ_3300(...) \, +#define Z_IS_3300_EQ_3300U(...) \, +#define Z_IS_3300U_EQ_3300U(...) \, +#define Z_IS_3301_EQ_3301(...) \, +#define Z_IS_3301U_EQ_3301(...) \, +#define Z_IS_3301_EQ_3301U(...) \, +#define Z_IS_3301U_EQ_3301U(...) \, +#define Z_IS_3302_EQ_3302(...) \, +#define Z_IS_3302U_EQ_3302(...) \, +#define Z_IS_3302_EQ_3302U(...) \, +#define Z_IS_3302U_EQ_3302U(...) \, +#define Z_IS_3303_EQ_3303(...) \, +#define Z_IS_3303U_EQ_3303(...) \, +#define Z_IS_3303_EQ_3303U(...) \, +#define Z_IS_3303U_EQ_3303U(...) \, +#define Z_IS_3304_EQ_3304(...) \, +#define Z_IS_3304U_EQ_3304(...) \, +#define Z_IS_3304_EQ_3304U(...) \, +#define Z_IS_3304U_EQ_3304U(...) \, +#define Z_IS_3305_EQ_3305(...) \, +#define Z_IS_3305U_EQ_3305(...) \, +#define Z_IS_3305_EQ_3305U(...) \, +#define Z_IS_3305U_EQ_3305U(...) \, +#define Z_IS_3306_EQ_3306(...) \, +#define Z_IS_3306U_EQ_3306(...) \, +#define Z_IS_3306_EQ_3306U(...) \, +#define Z_IS_3306U_EQ_3306U(...) \, +#define Z_IS_3307_EQ_3307(...) \, +#define Z_IS_3307U_EQ_3307(...) \, +#define Z_IS_3307_EQ_3307U(...) \, +#define Z_IS_3307U_EQ_3307U(...) \, +#define Z_IS_3308_EQ_3308(...) \, +#define Z_IS_3308U_EQ_3308(...) \, +#define Z_IS_3308_EQ_3308U(...) \, +#define Z_IS_3308U_EQ_3308U(...) \, +#define Z_IS_3309_EQ_3309(...) \, +#define Z_IS_3309U_EQ_3309(...) \, +#define Z_IS_3309_EQ_3309U(...) \, +#define Z_IS_3309U_EQ_3309U(...) \, +#define Z_IS_3310_EQ_3310(...) \, +#define Z_IS_3310U_EQ_3310(...) \, +#define Z_IS_3310_EQ_3310U(...) \, +#define Z_IS_3310U_EQ_3310U(...) \, +#define Z_IS_3311_EQ_3311(...) \, +#define Z_IS_3311U_EQ_3311(...) \, +#define Z_IS_3311_EQ_3311U(...) \, +#define Z_IS_3311U_EQ_3311U(...) \, +#define Z_IS_3312_EQ_3312(...) \, +#define Z_IS_3312U_EQ_3312(...) \, +#define Z_IS_3312_EQ_3312U(...) \, +#define Z_IS_3312U_EQ_3312U(...) \, +#define Z_IS_3313_EQ_3313(...) \, +#define Z_IS_3313U_EQ_3313(...) \, +#define Z_IS_3313_EQ_3313U(...) \, +#define Z_IS_3313U_EQ_3313U(...) \, +#define Z_IS_3314_EQ_3314(...) \, +#define Z_IS_3314U_EQ_3314(...) \, +#define Z_IS_3314_EQ_3314U(...) \, +#define Z_IS_3314U_EQ_3314U(...) \, +#define Z_IS_3315_EQ_3315(...) \, +#define Z_IS_3315U_EQ_3315(...) \, +#define Z_IS_3315_EQ_3315U(...) \, +#define Z_IS_3315U_EQ_3315U(...) \, +#define Z_IS_3316_EQ_3316(...) \, +#define Z_IS_3316U_EQ_3316(...) \, +#define Z_IS_3316_EQ_3316U(...) \, +#define Z_IS_3316U_EQ_3316U(...) \, +#define Z_IS_3317_EQ_3317(...) \, +#define Z_IS_3317U_EQ_3317(...) \, +#define Z_IS_3317_EQ_3317U(...) \, +#define Z_IS_3317U_EQ_3317U(...) \, +#define Z_IS_3318_EQ_3318(...) \, +#define Z_IS_3318U_EQ_3318(...) \, +#define Z_IS_3318_EQ_3318U(...) \, +#define Z_IS_3318U_EQ_3318U(...) \, +#define Z_IS_3319_EQ_3319(...) \, +#define Z_IS_3319U_EQ_3319(...) \, +#define Z_IS_3319_EQ_3319U(...) \, +#define Z_IS_3319U_EQ_3319U(...) \, +#define Z_IS_3320_EQ_3320(...) \, +#define Z_IS_3320U_EQ_3320(...) \, +#define Z_IS_3320_EQ_3320U(...) \, +#define Z_IS_3320U_EQ_3320U(...) \, +#define Z_IS_3321_EQ_3321(...) \, +#define Z_IS_3321U_EQ_3321(...) \, +#define Z_IS_3321_EQ_3321U(...) \, +#define Z_IS_3321U_EQ_3321U(...) \, +#define Z_IS_3322_EQ_3322(...) \, +#define Z_IS_3322U_EQ_3322(...) \, +#define Z_IS_3322_EQ_3322U(...) \, +#define Z_IS_3322U_EQ_3322U(...) \, +#define Z_IS_3323_EQ_3323(...) \, +#define Z_IS_3323U_EQ_3323(...) \, +#define Z_IS_3323_EQ_3323U(...) \, +#define Z_IS_3323U_EQ_3323U(...) \, +#define Z_IS_3324_EQ_3324(...) \, +#define Z_IS_3324U_EQ_3324(...) \, +#define Z_IS_3324_EQ_3324U(...) \, +#define Z_IS_3324U_EQ_3324U(...) \, +#define Z_IS_3325_EQ_3325(...) \, +#define Z_IS_3325U_EQ_3325(...) \, +#define Z_IS_3325_EQ_3325U(...) \, +#define Z_IS_3325U_EQ_3325U(...) \, +#define Z_IS_3326_EQ_3326(...) \, +#define Z_IS_3326U_EQ_3326(...) \, +#define Z_IS_3326_EQ_3326U(...) \, +#define Z_IS_3326U_EQ_3326U(...) \, +#define Z_IS_3327_EQ_3327(...) \, +#define Z_IS_3327U_EQ_3327(...) \, +#define Z_IS_3327_EQ_3327U(...) \, +#define Z_IS_3327U_EQ_3327U(...) \, +#define Z_IS_3328_EQ_3328(...) \, +#define Z_IS_3328U_EQ_3328(...) \, +#define Z_IS_3328_EQ_3328U(...) \, +#define Z_IS_3328U_EQ_3328U(...) \, +#define Z_IS_3329_EQ_3329(...) \, +#define Z_IS_3329U_EQ_3329(...) \, +#define Z_IS_3329_EQ_3329U(...) \, +#define Z_IS_3329U_EQ_3329U(...) \, +#define Z_IS_3330_EQ_3330(...) \, +#define Z_IS_3330U_EQ_3330(...) \, +#define Z_IS_3330_EQ_3330U(...) \, +#define Z_IS_3330U_EQ_3330U(...) \, +#define Z_IS_3331_EQ_3331(...) \, +#define Z_IS_3331U_EQ_3331(...) \, +#define Z_IS_3331_EQ_3331U(...) \, +#define Z_IS_3331U_EQ_3331U(...) \, +#define Z_IS_3332_EQ_3332(...) \, +#define Z_IS_3332U_EQ_3332(...) \, +#define Z_IS_3332_EQ_3332U(...) \, +#define Z_IS_3332U_EQ_3332U(...) \, +#define Z_IS_3333_EQ_3333(...) \, +#define Z_IS_3333U_EQ_3333(...) \, +#define Z_IS_3333_EQ_3333U(...) \, +#define Z_IS_3333U_EQ_3333U(...) \, +#define Z_IS_3334_EQ_3334(...) \, +#define Z_IS_3334U_EQ_3334(...) \, +#define Z_IS_3334_EQ_3334U(...) \, +#define Z_IS_3334U_EQ_3334U(...) \, +#define Z_IS_3335_EQ_3335(...) \, +#define Z_IS_3335U_EQ_3335(...) \, +#define Z_IS_3335_EQ_3335U(...) \, +#define Z_IS_3335U_EQ_3335U(...) \, +#define Z_IS_3336_EQ_3336(...) \, +#define Z_IS_3336U_EQ_3336(...) \, +#define Z_IS_3336_EQ_3336U(...) \, +#define Z_IS_3336U_EQ_3336U(...) \, +#define Z_IS_3337_EQ_3337(...) \, +#define Z_IS_3337U_EQ_3337(...) \, +#define Z_IS_3337_EQ_3337U(...) \, +#define Z_IS_3337U_EQ_3337U(...) \, +#define Z_IS_3338_EQ_3338(...) \, +#define Z_IS_3338U_EQ_3338(...) \, +#define Z_IS_3338_EQ_3338U(...) \, +#define Z_IS_3338U_EQ_3338U(...) \, +#define Z_IS_3339_EQ_3339(...) \, +#define Z_IS_3339U_EQ_3339(...) \, +#define Z_IS_3339_EQ_3339U(...) \, +#define Z_IS_3339U_EQ_3339U(...) \, +#define Z_IS_3340_EQ_3340(...) \, +#define Z_IS_3340U_EQ_3340(...) \, +#define Z_IS_3340_EQ_3340U(...) \, +#define Z_IS_3340U_EQ_3340U(...) \, +#define Z_IS_3341_EQ_3341(...) \, +#define Z_IS_3341U_EQ_3341(...) \, +#define Z_IS_3341_EQ_3341U(...) \, +#define Z_IS_3341U_EQ_3341U(...) \, +#define Z_IS_3342_EQ_3342(...) \, +#define Z_IS_3342U_EQ_3342(...) \, +#define Z_IS_3342_EQ_3342U(...) \, +#define Z_IS_3342U_EQ_3342U(...) \, +#define Z_IS_3343_EQ_3343(...) \, +#define Z_IS_3343U_EQ_3343(...) \, +#define Z_IS_3343_EQ_3343U(...) \, +#define Z_IS_3343U_EQ_3343U(...) \, +#define Z_IS_3344_EQ_3344(...) \, +#define Z_IS_3344U_EQ_3344(...) \, +#define Z_IS_3344_EQ_3344U(...) \, +#define Z_IS_3344U_EQ_3344U(...) \, +#define Z_IS_3345_EQ_3345(...) \, +#define Z_IS_3345U_EQ_3345(...) \, +#define Z_IS_3345_EQ_3345U(...) \, +#define Z_IS_3345U_EQ_3345U(...) \, +#define Z_IS_3346_EQ_3346(...) \, +#define Z_IS_3346U_EQ_3346(...) \, +#define Z_IS_3346_EQ_3346U(...) \, +#define Z_IS_3346U_EQ_3346U(...) \, +#define Z_IS_3347_EQ_3347(...) \, +#define Z_IS_3347U_EQ_3347(...) \, +#define Z_IS_3347_EQ_3347U(...) \, +#define Z_IS_3347U_EQ_3347U(...) \, +#define Z_IS_3348_EQ_3348(...) \, +#define Z_IS_3348U_EQ_3348(...) \, +#define Z_IS_3348_EQ_3348U(...) \, +#define Z_IS_3348U_EQ_3348U(...) \, +#define Z_IS_3349_EQ_3349(...) \, +#define Z_IS_3349U_EQ_3349(...) \, +#define Z_IS_3349_EQ_3349U(...) \, +#define Z_IS_3349U_EQ_3349U(...) \, +#define Z_IS_3350_EQ_3350(...) \, +#define Z_IS_3350U_EQ_3350(...) \, +#define Z_IS_3350_EQ_3350U(...) \, +#define Z_IS_3350U_EQ_3350U(...) \, +#define Z_IS_3351_EQ_3351(...) \, +#define Z_IS_3351U_EQ_3351(...) \, +#define Z_IS_3351_EQ_3351U(...) \, +#define Z_IS_3351U_EQ_3351U(...) \, +#define Z_IS_3352_EQ_3352(...) \, +#define Z_IS_3352U_EQ_3352(...) \, +#define Z_IS_3352_EQ_3352U(...) \, +#define Z_IS_3352U_EQ_3352U(...) \, +#define Z_IS_3353_EQ_3353(...) \, +#define Z_IS_3353U_EQ_3353(...) \, +#define Z_IS_3353_EQ_3353U(...) \, +#define Z_IS_3353U_EQ_3353U(...) \, +#define Z_IS_3354_EQ_3354(...) \, +#define Z_IS_3354U_EQ_3354(...) \, +#define Z_IS_3354_EQ_3354U(...) \, +#define Z_IS_3354U_EQ_3354U(...) \, +#define Z_IS_3355_EQ_3355(...) \, +#define Z_IS_3355U_EQ_3355(...) \, +#define Z_IS_3355_EQ_3355U(...) \, +#define Z_IS_3355U_EQ_3355U(...) \, +#define Z_IS_3356_EQ_3356(...) \, +#define Z_IS_3356U_EQ_3356(...) \, +#define Z_IS_3356_EQ_3356U(...) \, +#define Z_IS_3356U_EQ_3356U(...) \, +#define Z_IS_3357_EQ_3357(...) \, +#define Z_IS_3357U_EQ_3357(...) \, +#define Z_IS_3357_EQ_3357U(...) \, +#define Z_IS_3357U_EQ_3357U(...) \, +#define Z_IS_3358_EQ_3358(...) \, +#define Z_IS_3358U_EQ_3358(...) \, +#define Z_IS_3358_EQ_3358U(...) \, +#define Z_IS_3358U_EQ_3358U(...) \, +#define Z_IS_3359_EQ_3359(...) \, +#define Z_IS_3359U_EQ_3359(...) \, +#define Z_IS_3359_EQ_3359U(...) \, +#define Z_IS_3359U_EQ_3359U(...) \, +#define Z_IS_3360_EQ_3360(...) \, +#define Z_IS_3360U_EQ_3360(...) \, +#define Z_IS_3360_EQ_3360U(...) \, +#define Z_IS_3360U_EQ_3360U(...) \, +#define Z_IS_3361_EQ_3361(...) \, +#define Z_IS_3361U_EQ_3361(...) \, +#define Z_IS_3361_EQ_3361U(...) \, +#define Z_IS_3361U_EQ_3361U(...) \, +#define Z_IS_3362_EQ_3362(...) \, +#define Z_IS_3362U_EQ_3362(...) \, +#define Z_IS_3362_EQ_3362U(...) \, +#define Z_IS_3362U_EQ_3362U(...) \, +#define Z_IS_3363_EQ_3363(...) \, +#define Z_IS_3363U_EQ_3363(...) \, +#define Z_IS_3363_EQ_3363U(...) \, +#define Z_IS_3363U_EQ_3363U(...) \, +#define Z_IS_3364_EQ_3364(...) \, +#define Z_IS_3364U_EQ_3364(...) \, +#define Z_IS_3364_EQ_3364U(...) \, +#define Z_IS_3364U_EQ_3364U(...) \, +#define Z_IS_3365_EQ_3365(...) \, +#define Z_IS_3365U_EQ_3365(...) \, +#define Z_IS_3365_EQ_3365U(...) \, +#define Z_IS_3365U_EQ_3365U(...) \, +#define Z_IS_3366_EQ_3366(...) \, +#define Z_IS_3366U_EQ_3366(...) \, +#define Z_IS_3366_EQ_3366U(...) \, +#define Z_IS_3366U_EQ_3366U(...) \, +#define Z_IS_3367_EQ_3367(...) \, +#define Z_IS_3367U_EQ_3367(...) \, +#define Z_IS_3367_EQ_3367U(...) \, +#define Z_IS_3367U_EQ_3367U(...) \, +#define Z_IS_3368_EQ_3368(...) \, +#define Z_IS_3368U_EQ_3368(...) \, +#define Z_IS_3368_EQ_3368U(...) \, +#define Z_IS_3368U_EQ_3368U(...) \, +#define Z_IS_3369_EQ_3369(...) \, +#define Z_IS_3369U_EQ_3369(...) \, +#define Z_IS_3369_EQ_3369U(...) \, +#define Z_IS_3369U_EQ_3369U(...) \, +#define Z_IS_3370_EQ_3370(...) \, +#define Z_IS_3370U_EQ_3370(...) \, +#define Z_IS_3370_EQ_3370U(...) \, +#define Z_IS_3370U_EQ_3370U(...) \, +#define Z_IS_3371_EQ_3371(...) \, +#define Z_IS_3371U_EQ_3371(...) \, +#define Z_IS_3371_EQ_3371U(...) \, +#define Z_IS_3371U_EQ_3371U(...) \, +#define Z_IS_3372_EQ_3372(...) \, +#define Z_IS_3372U_EQ_3372(...) \, +#define Z_IS_3372_EQ_3372U(...) \, +#define Z_IS_3372U_EQ_3372U(...) \, +#define Z_IS_3373_EQ_3373(...) \, +#define Z_IS_3373U_EQ_3373(...) \, +#define Z_IS_3373_EQ_3373U(...) \, +#define Z_IS_3373U_EQ_3373U(...) \, +#define Z_IS_3374_EQ_3374(...) \, +#define Z_IS_3374U_EQ_3374(...) \, +#define Z_IS_3374_EQ_3374U(...) \, +#define Z_IS_3374U_EQ_3374U(...) \, +#define Z_IS_3375_EQ_3375(...) \, +#define Z_IS_3375U_EQ_3375(...) \, +#define Z_IS_3375_EQ_3375U(...) \, +#define Z_IS_3375U_EQ_3375U(...) \, +#define Z_IS_3376_EQ_3376(...) \, +#define Z_IS_3376U_EQ_3376(...) \, +#define Z_IS_3376_EQ_3376U(...) \, +#define Z_IS_3376U_EQ_3376U(...) \, +#define Z_IS_3377_EQ_3377(...) \, +#define Z_IS_3377U_EQ_3377(...) \, +#define Z_IS_3377_EQ_3377U(...) \, +#define Z_IS_3377U_EQ_3377U(...) \, +#define Z_IS_3378_EQ_3378(...) \, +#define Z_IS_3378U_EQ_3378(...) \, +#define Z_IS_3378_EQ_3378U(...) \, +#define Z_IS_3378U_EQ_3378U(...) \, +#define Z_IS_3379_EQ_3379(...) \, +#define Z_IS_3379U_EQ_3379(...) \, +#define Z_IS_3379_EQ_3379U(...) \, +#define Z_IS_3379U_EQ_3379U(...) \, +#define Z_IS_3380_EQ_3380(...) \, +#define Z_IS_3380U_EQ_3380(...) \, +#define Z_IS_3380_EQ_3380U(...) \, +#define Z_IS_3380U_EQ_3380U(...) \, +#define Z_IS_3381_EQ_3381(...) \, +#define Z_IS_3381U_EQ_3381(...) \, +#define Z_IS_3381_EQ_3381U(...) \, +#define Z_IS_3381U_EQ_3381U(...) \, +#define Z_IS_3382_EQ_3382(...) \, +#define Z_IS_3382U_EQ_3382(...) \, +#define Z_IS_3382_EQ_3382U(...) \, +#define Z_IS_3382U_EQ_3382U(...) \, +#define Z_IS_3383_EQ_3383(...) \, +#define Z_IS_3383U_EQ_3383(...) \, +#define Z_IS_3383_EQ_3383U(...) \, +#define Z_IS_3383U_EQ_3383U(...) \, +#define Z_IS_3384_EQ_3384(...) \, +#define Z_IS_3384U_EQ_3384(...) \, +#define Z_IS_3384_EQ_3384U(...) \, +#define Z_IS_3384U_EQ_3384U(...) \, +#define Z_IS_3385_EQ_3385(...) \, +#define Z_IS_3385U_EQ_3385(...) \, +#define Z_IS_3385_EQ_3385U(...) \, +#define Z_IS_3385U_EQ_3385U(...) \, +#define Z_IS_3386_EQ_3386(...) \, +#define Z_IS_3386U_EQ_3386(...) \, +#define Z_IS_3386_EQ_3386U(...) \, +#define Z_IS_3386U_EQ_3386U(...) \, +#define Z_IS_3387_EQ_3387(...) \, +#define Z_IS_3387U_EQ_3387(...) \, +#define Z_IS_3387_EQ_3387U(...) \, +#define Z_IS_3387U_EQ_3387U(...) \, +#define Z_IS_3388_EQ_3388(...) \, +#define Z_IS_3388U_EQ_3388(...) \, +#define Z_IS_3388_EQ_3388U(...) \, +#define Z_IS_3388U_EQ_3388U(...) \, +#define Z_IS_3389_EQ_3389(...) \, +#define Z_IS_3389U_EQ_3389(...) \, +#define Z_IS_3389_EQ_3389U(...) \, +#define Z_IS_3389U_EQ_3389U(...) \, +#define Z_IS_3390_EQ_3390(...) \, +#define Z_IS_3390U_EQ_3390(...) \, +#define Z_IS_3390_EQ_3390U(...) \, +#define Z_IS_3390U_EQ_3390U(...) \, +#define Z_IS_3391_EQ_3391(...) \, +#define Z_IS_3391U_EQ_3391(...) \, +#define Z_IS_3391_EQ_3391U(...) \, +#define Z_IS_3391U_EQ_3391U(...) \, +#define Z_IS_3392_EQ_3392(...) \, +#define Z_IS_3392U_EQ_3392(...) \, +#define Z_IS_3392_EQ_3392U(...) \, +#define Z_IS_3392U_EQ_3392U(...) \, +#define Z_IS_3393_EQ_3393(...) \, +#define Z_IS_3393U_EQ_3393(...) \, +#define Z_IS_3393_EQ_3393U(...) \, +#define Z_IS_3393U_EQ_3393U(...) \, +#define Z_IS_3394_EQ_3394(...) \, +#define Z_IS_3394U_EQ_3394(...) \, +#define Z_IS_3394_EQ_3394U(...) \, +#define Z_IS_3394U_EQ_3394U(...) \, +#define Z_IS_3395_EQ_3395(...) \, +#define Z_IS_3395U_EQ_3395(...) \, +#define Z_IS_3395_EQ_3395U(...) \, +#define Z_IS_3395U_EQ_3395U(...) \, +#define Z_IS_3396_EQ_3396(...) \, +#define Z_IS_3396U_EQ_3396(...) \, +#define Z_IS_3396_EQ_3396U(...) \, +#define Z_IS_3396U_EQ_3396U(...) \, +#define Z_IS_3397_EQ_3397(...) \, +#define Z_IS_3397U_EQ_3397(...) \, +#define Z_IS_3397_EQ_3397U(...) \, +#define Z_IS_3397U_EQ_3397U(...) \, +#define Z_IS_3398_EQ_3398(...) \, +#define Z_IS_3398U_EQ_3398(...) \, +#define Z_IS_3398_EQ_3398U(...) \, +#define Z_IS_3398U_EQ_3398U(...) \, +#define Z_IS_3399_EQ_3399(...) \, +#define Z_IS_3399U_EQ_3399(...) \, +#define Z_IS_3399_EQ_3399U(...) \, +#define Z_IS_3399U_EQ_3399U(...) \, +#define Z_IS_3400_EQ_3400(...) \, +#define Z_IS_3400U_EQ_3400(...) \, +#define Z_IS_3400_EQ_3400U(...) \, +#define Z_IS_3400U_EQ_3400U(...) \, +#define Z_IS_3401_EQ_3401(...) \, +#define Z_IS_3401U_EQ_3401(...) \, +#define Z_IS_3401_EQ_3401U(...) \, +#define Z_IS_3401U_EQ_3401U(...) \, +#define Z_IS_3402_EQ_3402(...) \, +#define Z_IS_3402U_EQ_3402(...) \, +#define Z_IS_3402_EQ_3402U(...) \, +#define Z_IS_3402U_EQ_3402U(...) \, +#define Z_IS_3403_EQ_3403(...) \, +#define Z_IS_3403U_EQ_3403(...) \, +#define Z_IS_3403_EQ_3403U(...) \, +#define Z_IS_3403U_EQ_3403U(...) \, +#define Z_IS_3404_EQ_3404(...) \, +#define Z_IS_3404U_EQ_3404(...) \, +#define Z_IS_3404_EQ_3404U(...) \, +#define Z_IS_3404U_EQ_3404U(...) \, +#define Z_IS_3405_EQ_3405(...) \, +#define Z_IS_3405U_EQ_3405(...) \, +#define Z_IS_3405_EQ_3405U(...) \, +#define Z_IS_3405U_EQ_3405U(...) \, +#define Z_IS_3406_EQ_3406(...) \, +#define Z_IS_3406U_EQ_3406(...) \, +#define Z_IS_3406_EQ_3406U(...) \, +#define Z_IS_3406U_EQ_3406U(...) \, +#define Z_IS_3407_EQ_3407(...) \, +#define Z_IS_3407U_EQ_3407(...) \, +#define Z_IS_3407_EQ_3407U(...) \, +#define Z_IS_3407U_EQ_3407U(...) \, +#define Z_IS_3408_EQ_3408(...) \, +#define Z_IS_3408U_EQ_3408(...) \, +#define Z_IS_3408_EQ_3408U(...) \, +#define Z_IS_3408U_EQ_3408U(...) \, +#define Z_IS_3409_EQ_3409(...) \, +#define Z_IS_3409U_EQ_3409(...) \, +#define Z_IS_3409_EQ_3409U(...) \, +#define Z_IS_3409U_EQ_3409U(...) \, +#define Z_IS_3410_EQ_3410(...) \, +#define Z_IS_3410U_EQ_3410(...) \, +#define Z_IS_3410_EQ_3410U(...) \, +#define Z_IS_3410U_EQ_3410U(...) \, +#define Z_IS_3411_EQ_3411(...) \, +#define Z_IS_3411U_EQ_3411(...) \, +#define Z_IS_3411_EQ_3411U(...) \, +#define Z_IS_3411U_EQ_3411U(...) \, +#define Z_IS_3412_EQ_3412(...) \, +#define Z_IS_3412U_EQ_3412(...) \, +#define Z_IS_3412_EQ_3412U(...) \, +#define Z_IS_3412U_EQ_3412U(...) \, +#define Z_IS_3413_EQ_3413(...) \, +#define Z_IS_3413U_EQ_3413(...) \, +#define Z_IS_3413_EQ_3413U(...) \, +#define Z_IS_3413U_EQ_3413U(...) \, +#define Z_IS_3414_EQ_3414(...) \, +#define Z_IS_3414U_EQ_3414(...) \, +#define Z_IS_3414_EQ_3414U(...) \, +#define Z_IS_3414U_EQ_3414U(...) \, +#define Z_IS_3415_EQ_3415(...) \, +#define Z_IS_3415U_EQ_3415(...) \, +#define Z_IS_3415_EQ_3415U(...) \, +#define Z_IS_3415U_EQ_3415U(...) \, +#define Z_IS_3416_EQ_3416(...) \, +#define Z_IS_3416U_EQ_3416(...) \, +#define Z_IS_3416_EQ_3416U(...) \, +#define Z_IS_3416U_EQ_3416U(...) \, +#define Z_IS_3417_EQ_3417(...) \, +#define Z_IS_3417U_EQ_3417(...) \, +#define Z_IS_3417_EQ_3417U(...) \, +#define Z_IS_3417U_EQ_3417U(...) \, +#define Z_IS_3418_EQ_3418(...) \, +#define Z_IS_3418U_EQ_3418(...) \, +#define Z_IS_3418_EQ_3418U(...) \, +#define Z_IS_3418U_EQ_3418U(...) \, +#define Z_IS_3419_EQ_3419(...) \, +#define Z_IS_3419U_EQ_3419(...) \, +#define Z_IS_3419_EQ_3419U(...) \, +#define Z_IS_3419U_EQ_3419U(...) \, +#define Z_IS_3420_EQ_3420(...) \, +#define Z_IS_3420U_EQ_3420(...) \, +#define Z_IS_3420_EQ_3420U(...) \, +#define Z_IS_3420U_EQ_3420U(...) \, +#define Z_IS_3421_EQ_3421(...) \, +#define Z_IS_3421U_EQ_3421(...) \, +#define Z_IS_3421_EQ_3421U(...) \, +#define Z_IS_3421U_EQ_3421U(...) \, +#define Z_IS_3422_EQ_3422(...) \, +#define Z_IS_3422U_EQ_3422(...) \, +#define Z_IS_3422_EQ_3422U(...) \, +#define Z_IS_3422U_EQ_3422U(...) \, +#define Z_IS_3423_EQ_3423(...) \, +#define Z_IS_3423U_EQ_3423(...) \, +#define Z_IS_3423_EQ_3423U(...) \, +#define Z_IS_3423U_EQ_3423U(...) \, +#define Z_IS_3424_EQ_3424(...) \, +#define Z_IS_3424U_EQ_3424(...) \, +#define Z_IS_3424_EQ_3424U(...) \, +#define Z_IS_3424U_EQ_3424U(...) \, +#define Z_IS_3425_EQ_3425(...) \, +#define Z_IS_3425U_EQ_3425(...) \, +#define Z_IS_3425_EQ_3425U(...) \, +#define Z_IS_3425U_EQ_3425U(...) \, +#define Z_IS_3426_EQ_3426(...) \, +#define Z_IS_3426U_EQ_3426(...) \, +#define Z_IS_3426_EQ_3426U(...) \, +#define Z_IS_3426U_EQ_3426U(...) \, +#define Z_IS_3427_EQ_3427(...) \, +#define Z_IS_3427U_EQ_3427(...) \, +#define Z_IS_3427_EQ_3427U(...) \, +#define Z_IS_3427U_EQ_3427U(...) \, +#define Z_IS_3428_EQ_3428(...) \, +#define Z_IS_3428U_EQ_3428(...) \, +#define Z_IS_3428_EQ_3428U(...) \, +#define Z_IS_3428U_EQ_3428U(...) \, +#define Z_IS_3429_EQ_3429(...) \, +#define Z_IS_3429U_EQ_3429(...) \, +#define Z_IS_3429_EQ_3429U(...) \, +#define Z_IS_3429U_EQ_3429U(...) \, +#define Z_IS_3430_EQ_3430(...) \, +#define Z_IS_3430U_EQ_3430(...) \, +#define Z_IS_3430_EQ_3430U(...) \, +#define Z_IS_3430U_EQ_3430U(...) \, +#define Z_IS_3431_EQ_3431(...) \, +#define Z_IS_3431U_EQ_3431(...) \, +#define Z_IS_3431_EQ_3431U(...) \, +#define Z_IS_3431U_EQ_3431U(...) \, +#define Z_IS_3432_EQ_3432(...) \, +#define Z_IS_3432U_EQ_3432(...) \, +#define Z_IS_3432_EQ_3432U(...) \, +#define Z_IS_3432U_EQ_3432U(...) \, +#define Z_IS_3433_EQ_3433(...) \, +#define Z_IS_3433U_EQ_3433(...) \, +#define Z_IS_3433_EQ_3433U(...) \, +#define Z_IS_3433U_EQ_3433U(...) \, +#define Z_IS_3434_EQ_3434(...) \, +#define Z_IS_3434U_EQ_3434(...) \, +#define Z_IS_3434_EQ_3434U(...) \, +#define Z_IS_3434U_EQ_3434U(...) \, +#define Z_IS_3435_EQ_3435(...) \, +#define Z_IS_3435U_EQ_3435(...) \, +#define Z_IS_3435_EQ_3435U(...) \, +#define Z_IS_3435U_EQ_3435U(...) \, +#define Z_IS_3436_EQ_3436(...) \, +#define Z_IS_3436U_EQ_3436(...) \, +#define Z_IS_3436_EQ_3436U(...) \, +#define Z_IS_3436U_EQ_3436U(...) \, +#define Z_IS_3437_EQ_3437(...) \, +#define Z_IS_3437U_EQ_3437(...) \, +#define Z_IS_3437_EQ_3437U(...) \, +#define Z_IS_3437U_EQ_3437U(...) \, +#define Z_IS_3438_EQ_3438(...) \, +#define Z_IS_3438U_EQ_3438(...) \, +#define Z_IS_3438_EQ_3438U(...) \, +#define Z_IS_3438U_EQ_3438U(...) \, +#define Z_IS_3439_EQ_3439(...) \, +#define Z_IS_3439U_EQ_3439(...) \, +#define Z_IS_3439_EQ_3439U(...) \, +#define Z_IS_3439U_EQ_3439U(...) \, +#define Z_IS_3440_EQ_3440(...) \, +#define Z_IS_3440U_EQ_3440(...) \, +#define Z_IS_3440_EQ_3440U(...) \, +#define Z_IS_3440U_EQ_3440U(...) \, +#define Z_IS_3441_EQ_3441(...) \, +#define Z_IS_3441U_EQ_3441(...) \, +#define Z_IS_3441_EQ_3441U(...) \, +#define Z_IS_3441U_EQ_3441U(...) \, +#define Z_IS_3442_EQ_3442(...) \, +#define Z_IS_3442U_EQ_3442(...) \, +#define Z_IS_3442_EQ_3442U(...) \, +#define Z_IS_3442U_EQ_3442U(...) \, +#define Z_IS_3443_EQ_3443(...) \, +#define Z_IS_3443U_EQ_3443(...) \, +#define Z_IS_3443_EQ_3443U(...) \, +#define Z_IS_3443U_EQ_3443U(...) \, +#define Z_IS_3444_EQ_3444(...) \, +#define Z_IS_3444U_EQ_3444(...) \, +#define Z_IS_3444_EQ_3444U(...) \, +#define Z_IS_3444U_EQ_3444U(...) \, +#define Z_IS_3445_EQ_3445(...) \, +#define Z_IS_3445U_EQ_3445(...) \, +#define Z_IS_3445_EQ_3445U(...) \, +#define Z_IS_3445U_EQ_3445U(...) \, +#define Z_IS_3446_EQ_3446(...) \, +#define Z_IS_3446U_EQ_3446(...) \, +#define Z_IS_3446_EQ_3446U(...) \, +#define Z_IS_3446U_EQ_3446U(...) \, +#define Z_IS_3447_EQ_3447(...) \, +#define Z_IS_3447U_EQ_3447(...) \, +#define Z_IS_3447_EQ_3447U(...) \, +#define Z_IS_3447U_EQ_3447U(...) \, +#define Z_IS_3448_EQ_3448(...) \, +#define Z_IS_3448U_EQ_3448(...) \, +#define Z_IS_3448_EQ_3448U(...) \, +#define Z_IS_3448U_EQ_3448U(...) \, +#define Z_IS_3449_EQ_3449(...) \, +#define Z_IS_3449U_EQ_3449(...) \, +#define Z_IS_3449_EQ_3449U(...) \, +#define Z_IS_3449U_EQ_3449U(...) \, +#define Z_IS_3450_EQ_3450(...) \, +#define Z_IS_3450U_EQ_3450(...) \, +#define Z_IS_3450_EQ_3450U(...) \, +#define Z_IS_3450U_EQ_3450U(...) \, +#define Z_IS_3451_EQ_3451(...) \, +#define Z_IS_3451U_EQ_3451(...) \, +#define Z_IS_3451_EQ_3451U(...) \, +#define Z_IS_3451U_EQ_3451U(...) \, +#define Z_IS_3452_EQ_3452(...) \, +#define Z_IS_3452U_EQ_3452(...) \, +#define Z_IS_3452_EQ_3452U(...) \, +#define Z_IS_3452U_EQ_3452U(...) \, +#define Z_IS_3453_EQ_3453(...) \, +#define Z_IS_3453U_EQ_3453(...) \, +#define Z_IS_3453_EQ_3453U(...) \, +#define Z_IS_3453U_EQ_3453U(...) \, +#define Z_IS_3454_EQ_3454(...) \, +#define Z_IS_3454U_EQ_3454(...) \, +#define Z_IS_3454_EQ_3454U(...) \, +#define Z_IS_3454U_EQ_3454U(...) \, +#define Z_IS_3455_EQ_3455(...) \, +#define Z_IS_3455U_EQ_3455(...) \, +#define Z_IS_3455_EQ_3455U(...) \, +#define Z_IS_3455U_EQ_3455U(...) \, +#define Z_IS_3456_EQ_3456(...) \, +#define Z_IS_3456U_EQ_3456(...) \, +#define Z_IS_3456_EQ_3456U(...) \, +#define Z_IS_3456U_EQ_3456U(...) \, +#define Z_IS_3457_EQ_3457(...) \, +#define Z_IS_3457U_EQ_3457(...) \, +#define Z_IS_3457_EQ_3457U(...) \, +#define Z_IS_3457U_EQ_3457U(...) \, +#define Z_IS_3458_EQ_3458(...) \, +#define Z_IS_3458U_EQ_3458(...) \, +#define Z_IS_3458_EQ_3458U(...) \, +#define Z_IS_3458U_EQ_3458U(...) \, +#define Z_IS_3459_EQ_3459(...) \, +#define Z_IS_3459U_EQ_3459(...) \, +#define Z_IS_3459_EQ_3459U(...) \, +#define Z_IS_3459U_EQ_3459U(...) \, +#define Z_IS_3460_EQ_3460(...) \, +#define Z_IS_3460U_EQ_3460(...) \, +#define Z_IS_3460_EQ_3460U(...) \, +#define Z_IS_3460U_EQ_3460U(...) \, +#define Z_IS_3461_EQ_3461(...) \, +#define Z_IS_3461U_EQ_3461(...) \, +#define Z_IS_3461_EQ_3461U(...) \, +#define Z_IS_3461U_EQ_3461U(...) \, +#define Z_IS_3462_EQ_3462(...) \, +#define Z_IS_3462U_EQ_3462(...) \, +#define Z_IS_3462_EQ_3462U(...) \, +#define Z_IS_3462U_EQ_3462U(...) \, +#define Z_IS_3463_EQ_3463(...) \, +#define Z_IS_3463U_EQ_3463(...) \, +#define Z_IS_3463_EQ_3463U(...) \, +#define Z_IS_3463U_EQ_3463U(...) \, +#define Z_IS_3464_EQ_3464(...) \, +#define Z_IS_3464U_EQ_3464(...) \, +#define Z_IS_3464_EQ_3464U(...) \, +#define Z_IS_3464U_EQ_3464U(...) \, +#define Z_IS_3465_EQ_3465(...) \, +#define Z_IS_3465U_EQ_3465(...) \, +#define Z_IS_3465_EQ_3465U(...) \, +#define Z_IS_3465U_EQ_3465U(...) \, +#define Z_IS_3466_EQ_3466(...) \, +#define Z_IS_3466U_EQ_3466(...) \, +#define Z_IS_3466_EQ_3466U(...) \, +#define Z_IS_3466U_EQ_3466U(...) \, +#define Z_IS_3467_EQ_3467(...) \, +#define Z_IS_3467U_EQ_3467(...) \, +#define Z_IS_3467_EQ_3467U(...) \, +#define Z_IS_3467U_EQ_3467U(...) \, +#define Z_IS_3468_EQ_3468(...) \, +#define Z_IS_3468U_EQ_3468(...) \, +#define Z_IS_3468_EQ_3468U(...) \, +#define Z_IS_3468U_EQ_3468U(...) \, +#define Z_IS_3469_EQ_3469(...) \, +#define Z_IS_3469U_EQ_3469(...) \, +#define Z_IS_3469_EQ_3469U(...) \, +#define Z_IS_3469U_EQ_3469U(...) \, +#define Z_IS_3470_EQ_3470(...) \, +#define Z_IS_3470U_EQ_3470(...) \, +#define Z_IS_3470_EQ_3470U(...) \, +#define Z_IS_3470U_EQ_3470U(...) \, +#define Z_IS_3471_EQ_3471(...) \, +#define Z_IS_3471U_EQ_3471(...) \, +#define Z_IS_3471_EQ_3471U(...) \, +#define Z_IS_3471U_EQ_3471U(...) \, +#define Z_IS_3472_EQ_3472(...) \, +#define Z_IS_3472U_EQ_3472(...) \, +#define Z_IS_3472_EQ_3472U(...) \, +#define Z_IS_3472U_EQ_3472U(...) \, +#define Z_IS_3473_EQ_3473(...) \, +#define Z_IS_3473U_EQ_3473(...) \, +#define Z_IS_3473_EQ_3473U(...) \, +#define Z_IS_3473U_EQ_3473U(...) \, +#define Z_IS_3474_EQ_3474(...) \, +#define Z_IS_3474U_EQ_3474(...) \, +#define Z_IS_3474_EQ_3474U(...) \, +#define Z_IS_3474U_EQ_3474U(...) \, +#define Z_IS_3475_EQ_3475(...) \, +#define Z_IS_3475U_EQ_3475(...) \, +#define Z_IS_3475_EQ_3475U(...) \, +#define Z_IS_3475U_EQ_3475U(...) \, +#define Z_IS_3476_EQ_3476(...) \, +#define Z_IS_3476U_EQ_3476(...) \, +#define Z_IS_3476_EQ_3476U(...) \, +#define Z_IS_3476U_EQ_3476U(...) \, +#define Z_IS_3477_EQ_3477(...) \, +#define Z_IS_3477U_EQ_3477(...) \, +#define Z_IS_3477_EQ_3477U(...) \, +#define Z_IS_3477U_EQ_3477U(...) \, +#define Z_IS_3478_EQ_3478(...) \, +#define Z_IS_3478U_EQ_3478(...) \, +#define Z_IS_3478_EQ_3478U(...) \, +#define Z_IS_3478U_EQ_3478U(...) \, +#define Z_IS_3479_EQ_3479(...) \, +#define Z_IS_3479U_EQ_3479(...) \, +#define Z_IS_3479_EQ_3479U(...) \, +#define Z_IS_3479U_EQ_3479U(...) \, +#define Z_IS_3480_EQ_3480(...) \, +#define Z_IS_3480U_EQ_3480(...) \, +#define Z_IS_3480_EQ_3480U(...) \, +#define Z_IS_3480U_EQ_3480U(...) \, +#define Z_IS_3481_EQ_3481(...) \, +#define Z_IS_3481U_EQ_3481(...) \, +#define Z_IS_3481_EQ_3481U(...) \, +#define Z_IS_3481U_EQ_3481U(...) \, +#define Z_IS_3482_EQ_3482(...) \, +#define Z_IS_3482U_EQ_3482(...) \, +#define Z_IS_3482_EQ_3482U(...) \, +#define Z_IS_3482U_EQ_3482U(...) \, +#define Z_IS_3483_EQ_3483(...) \, +#define Z_IS_3483U_EQ_3483(...) \, +#define Z_IS_3483_EQ_3483U(...) \, +#define Z_IS_3483U_EQ_3483U(...) \, +#define Z_IS_3484_EQ_3484(...) \, +#define Z_IS_3484U_EQ_3484(...) \, +#define Z_IS_3484_EQ_3484U(...) \, +#define Z_IS_3484U_EQ_3484U(...) \, +#define Z_IS_3485_EQ_3485(...) \, +#define Z_IS_3485U_EQ_3485(...) \, +#define Z_IS_3485_EQ_3485U(...) \, +#define Z_IS_3485U_EQ_3485U(...) \, +#define Z_IS_3486_EQ_3486(...) \, +#define Z_IS_3486U_EQ_3486(...) \, +#define Z_IS_3486_EQ_3486U(...) \, +#define Z_IS_3486U_EQ_3486U(...) \, +#define Z_IS_3487_EQ_3487(...) \, +#define Z_IS_3487U_EQ_3487(...) \, +#define Z_IS_3487_EQ_3487U(...) \, +#define Z_IS_3487U_EQ_3487U(...) \, +#define Z_IS_3488_EQ_3488(...) \, +#define Z_IS_3488U_EQ_3488(...) \, +#define Z_IS_3488_EQ_3488U(...) \, +#define Z_IS_3488U_EQ_3488U(...) \, +#define Z_IS_3489_EQ_3489(...) \, +#define Z_IS_3489U_EQ_3489(...) \, +#define Z_IS_3489_EQ_3489U(...) \, +#define Z_IS_3489U_EQ_3489U(...) \, +#define Z_IS_3490_EQ_3490(...) \, +#define Z_IS_3490U_EQ_3490(...) \, +#define Z_IS_3490_EQ_3490U(...) \, +#define Z_IS_3490U_EQ_3490U(...) \, +#define Z_IS_3491_EQ_3491(...) \, +#define Z_IS_3491U_EQ_3491(...) \, +#define Z_IS_3491_EQ_3491U(...) \, +#define Z_IS_3491U_EQ_3491U(...) \, +#define Z_IS_3492_EQ_3492(...) \, +#define Z_IS_3492U_EQ_3492(...) \, +#define Z_IS_3492_EQ_3492U(...) \, +#define Z_IS_3492U_EQ_3492U(...) \, +#define Z_IS_3493_EQ_3493(...) \, +#define Z_IS_3493U_EQ_3493(...) \, +#define Z_IS_3493_EQ_3493U(...) \, +#define Z_IS_3493U_EQ_3493U(...) \, +#define Z_IS_3494_EQ_3494(...) \, +#define Z_IS_3494U_EQ_3494(...) \, +#define Z_IS_3494_EQ_3494U(...) \, +#define Z_IS_3494U_EQ_3494U(...) \, +#define Z_IS_3495_EQ_3495(...) \, +#define Z_IS_3495U_EQ_3495(...) \, +#define Z_IS_3495_EQ_3495U(...) \, +#define Z_IS_3495U_EQ_3495U(...) \, +#define Z_IS_3496_EQ_3496(...) \, +#define Z_IS_3496U_EQ_3496(...) \, +#define Z_IS_3496_EQ_3496U(...) \, +#define Z_IS_3496U_EQ_3496U(...) \, +#define Z_IS_3497_EQ_3497(...) \, +#define Z_IS_3497U_EQ_3497(...) \, +#define Z_IS_3497_EQ_3497U(...) \, +#define Z_IS_3497U_EQ_3497U(...) \, +#define Z_IS_3498_EQ_3498(...) \, +#define Z_IS_3498U_EQ_3498(...) \, +#define Z_IS_3498_EQ_3498U(...) \, +#define Z_IS_3498U_EQ_3498U(...) \, +#define Z_IS_3499_EQ_3499(...) \, +#define Z_IS_3499U_EQ_3499(...) \, +#define Z_IS_3499_EQ_3499U(...) \, +#define Z_IS_3499U_EQ_3499U(...) \, +#define Z_IS_3500_EQ_3500(...) \, +#define Z_IS_3500U_EQ_3500(...) \, +#define Z_IS_3500_EQ_3500U(...) \, +#define Z_IS_3500U_EQ_3500U(...) \, +#define Z_IS_3501_EQ_3501(...) \, +#define Z_IS_3501U_EQ_3501(...) \, +#define Z_IS_3501_EQ_3501U(...) \, +#define Z_IS_3501U_EQ_3501U(...) \, +#define Z_IS_3502_EQ_3502(...) \, +#define Z_IS_3502U_EQ_3502(...) \, +#define Z_IS_3502_EQ_3502U(...) \, +#define Z_IS_3502U_EQ_3502U(...) \, +#define Z_IS_3503_EQ_3503(...) \, +#define Z_IS_3503U_EQ_3503(...) \, +#define Z_IS_3503_EQ_3503U(...) \, +#define Z_IS_3503U_EQ_3503U(...) \, +#define Z_IS_3504_EQ_3504(...) \, +#define Z_IS_3504U_EQ_3504(...) \, +#define Z_IS_3504_EQ_3504U(...) \, +#define Z_IS_3504U_EQ_3504U(...) \, +#define Z_IS_3505_EQ_3505(...) \, +#define Z_IS_3505U_EQ_3505(...) \, +#define Z_IS_3505_EQ_3505U(...) \, +#define Z_IS_3505U_EQ_3505U(...) \, +#define Z_IS_3506_EQ_3506(...) \, +#define Z_IS_3506U_EQ_3506(...) \, +#define Z_IS_3506_EQ_3506U(...) \, +#define Z_IS_3506U_EQ_3506U(...) \, +#define Z_IS_3507_EQ_3507(...) \, +#define Z_IS_3507U_EQ_3507(...) \, +#define Z_IS_3507_EQ_3507U(...) \, +#define Z_IS_3507U_EQ_3507U(...) \, +#define Z_IS_3508_EQ_3508(...) \, +#define Z_IS_3508U_EQ_3508(...) \, +#define Z_IS_3508_EQ_3508U(...) \, +#define Z_IS_3508U_EQ_3508U(...) \, +#define Z_IS_3509_EQ_3509(...) \, +#define Z_IS_3509U_EQ_3509(...) \, +#define Z_IS_3509_EQ_3509U(...) \, +#define Z_IS_3509U_EQ_3509U(...) \, +#define Z_IS_3510_EQ_3510(...) \, +#define Z_IS_3510U_EQ_3510(...) \, +#define Z_IS_3510_EQ_3510U(...) \, +#define Z_IS_3510U_EQ_3510U(...) \, +#define Z_IS_3511_EQ_3511(...) \, +#define Z_IS_3511U_EQ_3511(...) \, +#define Z_IS_3511_EQ_3511U(...) \, +#define Z_IS_3511U_EQ_3511U(...) \, +#define Z_IS_3512_EQ_3512(...) \, +#define Z_IS_3512U_EQ_3512(...) \, +#define Z_IS_3512_EQ_3512U(...) \, +#define Z_IS_3512U_EQ_3512U(...) \, +#define Z_IS_3513_EQ_3513(...) \, +#define Z_IS_3513U_EQ_3513(...) \, +#define Z_IS_3513_EQ_3513U(...) \, +#define Z_IS_3513U_EQ_3513U(...) \, +#define Z_IS_3514_EQ_3514(...) \, +#define Z_IS_3514U_EQ_3514(...) \, +#define Z_IS_3514_EQ_3514U(...) \, +#define Z_IS_3514U_EQ_3514U(...) \, +#define Z_IS_3515_EQ_3515(...) \, +#define Z_IS_3515U_EQ_3515(...) \, +#define Z_IS_3515_EQ_3515U(...) \, +#define Z_IS_3515U_EQ_3515U(...) \, +#define Z_IS_3516_EQ_3516(...) \, +#define Z_IS_3516U_EQ_3516(...) \, +#define Z_IS_3516_EQ_3516U(...) \, +#define Z_IS_3516U_EQ_3516U(...) \, +#define Z_IS_3517_EQ_3517(...) \, +#define Z_IS_3517U_EQ_3517(...) \, +#define Z_IS_3517_EQ_3517U(...) \, +#define Z_IS_3517U_EQ_3517U(...) \, +#define Z_IS_3518_EQ_3518(...) \, +#define Z_IS_3518U_EQ_3518(...) \, +#define Z_IS_3518_EQ_3518U(...) \, +#define Z_IS_3518U_EQ_3518U(...) \, +#define Z_IS_3519_EQ_3519(...) \, +#define Z_IS_3519U_EQ_3519(...) \, +#define Z_IS_3519_EQ_3519U(...) \, +#define Z_IS_3519U_EQ_3519U(...) \, +#define Z_IS_3520_EQ_3520(...) \, +#define Z_IS_3520U_EQ_3520(...) \, +#define Z_IS_3520_EQ_3520U(...) \, +#define Z_IS_3520U_EQ_3520U(...) \, +#define Z_IS_3521_EQ_3521(...) \, +#define Z_IS_3521U_EQ_3521(...) \, +#define Z_IS_3521_EQ_3521U(...) \, +#define Z_IS_3521U_EQ_3521U(...) \, +#define Z_IS_3522_EQ_3522(...) \, +#define Z_IS_3522U_EQ_3522(...) \, +#define Z_IS_3522_EQ_3522U(...) \, +#define Z_IS_3522U_EQ_3522U(...) \, +#define Z_IS_3523_EQ_3523(...) \, +#define Z_IS_3523U_EQ_3523(...) \, +#define Z_IS_3523_EQ_3523U(...) \, +#define Z_IS_3523U_EQ_3523U(...) \, +#define Z_IS_3524_EQ_3524(...) \, +#define Z_IS_3524U_EQ_3524(...) \, +#define Z_IS_3524_EQ_3524U(...) \, +#define Z_IS_3524U_EQ_3524U(...) \, +#define Z_IS_3525_EQ_3525(...) \, +#define Z_IS_3525U_EQ_3525(...) \, +#define Z_IS_3525_EQ_3525U(...) \, +#define Z_IS_3525U_EQ_3525U(...) \, +#define Z_IS_3526_EQ_3526(...) \, +#define Z_IS_3526U_EQ_3526(...) \, +#define Z_IS_3526_EQ_3526U(...) \, +#define Z_IS_3526U_EQ_3526U(...) \, +#define Z_IS_3527_EQ_3527(...) \, +#define Z_IS_3527U_EQ_3527(...) \, +#define Z_IS_3527_EQ_3527U(...) \, +#define Z_IS_3527U_EQ_3527U(...) \, +#define Z_IS_3528_EQ_3528(...) \, +#define Z_IS_3528U_EQ_3528(...) \, +#define Z_IS_3528_EQ_3528U(...) \, +#define Z_IS_3528U_EQ_3528U(...) \, +#define Z_IS_3529_EQ_3529(...) \, +#define Z_IS_3529U_EQ_3529(...) \, +#define Z_IS_3529_EQ_3529U(...) \, +#define Z_IS_3529U_EQ_3529U(...) \, +#define Z_IS_3530_EQ_3530(...) \, +#define Z_IS_3530U_EQ_3530(...) \, +#define Z_IS_3530_EQ_3530U(...) \, +#define Z_IS_3530U_EQ_3530U(...) \, +#define Z_IS_3531_EQ_3531(...) \, +#define Z_IS_3531U_EQ_3531(...) \, +#define Z_IS_3531_EQ_3531U(...) \, +#define Z_IS_3531U_EQ_3531U(...) \, +#define Z_IS_3532_EQ_3532(...) \, +#define Z_IS_3532U_EQ_3532(...) \, +#define Z_IS_3532_EQ_3532U(...) \, +#define Z_IS_3532U_EQ_3532U(...) \, +#define Z_IS_3533_EQ_3533(...) \, +#define Z_IS_3533U_EQ_3533(...) \, +#define Z_IS_3533_EQ_3533U(...) \, +#define Z_IS_3533U_EQ_3533U(...) \, +#define Z_IS_3534_EQ_3534(...) \, +#define Z_IS_3534U_EQ_3534(...) \, +#define Z_IS_3534_EQ_3534U(...) \, +#define Z_IS_3534U_EQ_3534U(...) \, +#define Z_IS_3535_EQ_3535(...) \, +#define Z_IS_3535U_EQ_3535(...) \, +#define Z_IS_3535_EQ_3535U(...) \, +#define Z_IS_3535U_EQ_3535U(...) \, +#define Z_IS_3536_EQ_3536(...) \, +#define Z_IS_3536U_EQ_3536(...) \, +#define Z_IS_3536_EQ_3536U(...) \, +#define Z_IS_3536U_EQ_3536U(...) \, +#define Z_IS_3537_EQ_3537(...) \, +#define Z_IS_3537U_EQ_3537(...) \, +#define Z_IS_3537_EQ_3537U(...) \, +#define Z_IS_3537U_EQ_3537U(...) \, +#define Z_IS_3538_EQ_3538(...) \, +#define Z_IS_3538U_EQ_3538(...) \, +#define Z_IS_3538_EQ_3538U(...) \, +#define Z_IS_3538U_EQ_3538U(...) \, +#define Z_IS_3539_EQ_3539(...) \, +#define Z_IS_3539U_EQ_3539(...) \, +#define Z_IS_3539_EQ_3539U(...) \, +#define Z_IS_3539U_EQ_3539U(...) \, +#define Z_IS_3540_EQ_3540(...) \, +#define Z_IS_3540U_EQ_3540(...) \, +#define Z_IS_3540_EQ_3540U(...) \, +#define Z_IS_3540U_EQ_3540U(...) \, +#define Z_IS_3541_EQ_3541(...) \, +#define Z_IS_3541U_EQ_3541(...) \, +#define Z_IS_3541_EQ_3541U(...) \, +#define Z_IS_3541U_EQ_3541U(...) \, +#define Z_IS_3542_EQ_3542(...) \, +#define Z_IS_3542U_EQ_3542(...) \, +#define Z_IS_3542_EQ_3542U(...) \, +#define Z_IS_3542U_EQ_3542U(...) \, +#define Z_IS_3543_EQ_3543(...) \, +#define Z_IS_3543U_EQ_3543(...) \, +#define Z_IS_3543_EQ_3543U(...) \, +#define Z_IS_3543U_EQ_3543U(...) \, +#define Z_IS_3544_EQ_3544(...) \, +#define Z_IS_3544U_EQ_3544(...) \, +#define Z_IS_3544_EQ_3544U(...) \, +#define Z_IS_3544U_EQ_3544U(...) \, +#define Z_IS_3545_EQ_3545(...) \, +#define Z_IS_3545U_EQ_3545(...) \, +#define Z_IS_3545_EQ_3545U(...) \, +#define Z_IS_3545U_EQ_3545U(...) \, +#define Z_IS_3546_EQ_3546(...) \, +#define Z_IS_3546U_EQ_3546(...) \, +#define Z_IS_3546_EQ_3546U(...) \, +#define Z_IS_3546U_EQ_3546U(...) \, +#define Z_IS_3547_EQ_3547(...) \, +#define Z_IS_3547U_EQ_3547(...) \, +#define Z_IS_3547_EQ_3547U(...) \, +#define Z_IS_3547U_EQ_3547U(...) \, +#define Z_IS_3548_EQ_3548(...) \, +#define Z_IS_3548U_EQ_3548(...) \, +#define Z_IS_3548_EQ_3548U(...) \, +#define Z_IS_3548U_EQ_3548U(...) \, +#define Z_IS_3549_EQ_3549(...) \, +#define Z_IS_3549U_EQ_3549(...) \, +#define Z_IS_3549_EQ_3549U(...) \, +#define Z_IS_3549U_EQ_3549U(...) \, +#define Z_IS_3550_EQ_3550(...) \, +#define Z_IS_3550U_EQ_3550(...) \, +#define Z_IS_3550_EQ_3550U(...) \, +#define Z_IS_3550U_EQ_3550U(...) \, +#define Z_IS_3551_EQ_3551(...) \, +#define Z_IS_3551U_EQ_3551(...) \, +#define Z_IS_3551_EQ_3551U(...) \, +#define Z_IS_3551U_EQ_3551U(...) \, +#define Z_IS_3552_EQ_3552(...) \, +#define Z_IS_3552U_EQ_3552(...) \, +#define Z_IS_3552_EQ_3552U(...) \, +#define Z_IS_3552U_EQ_3552U(...) \, +#define Z_IS_3553_EQ_3553(...) \, +#define Z_IS_3553U_EQ_3553(...) \, +#define Z_IS_3553_EQ_3553U(...) \, +#define Z_IS_3553U_EQ_3553U(...) \, +#define Z_IS_3554_EQ_3554(...) \, +#define Z_IS_3554U_EQ_3554(...) \, +#define Z_IS_3554_EQ_3554U(...) \, +#define Z_IS_3554U_EQ_3554U(...) \, +#define Z_IS_3555_EQ_3555(...) \, +#define Z_IS_3555U_EQ_3555(...) \, +#define Z_IS_3555_EQ_3555U(...) \, +#define Z_IS_3555U_EQ_3555U(...) \, +#define Z_IS_3556_EQ_3556(...) \, +#define Z_IS_3556U_EQ_3556(...) \, +#define Z_IS_3556_EQ_3556U(...) \, +#define Z_IS_3556U_EQ_3556U(...) \, +#define Z_IS_3557_EQ_3557(...) \, +#define Z_IS_3557U_EQ_3557(...) \, +#define Z_IS_3557_EQ_3557U(...) \, +#define Z_IS_3557U_EQ_3557U(...) \, +#define Z_IS_3558_EQ_3558(...) \, +#define Z_IS_3558U_EQ_3558(...) \, +#define Z_IS_3558_EQ_3558U(...) \, +#define Z_IS_3558U_EQ_3558U(...) \, +#define Z_IS_3559_EQ_3559(...) \, +#define Z_IS_3559U_EQ_3559(...) \, +#define Z_IS_3559_EQ_3559U(...) \, +#define Z_IS_3559U_EQ_3559U(...) \, +#define Z_IS_3560_EQ_3560(...) \, +#define Z_IS_3560U_EQ_3560(...) \, +#define Z_IS_3560_EQ_3560U(...) \, +#define Z_IS_3560U_EQ_3560U(...) \, +#define Z_IS_3561_EQ_3561(...) \, +#define Z_IS_3561U_EQ_3561(...) \, +#define Z_IS_3561_EQ_3561U(...) \, +#define Z_IS_3561U_EQ_3561U(...) \, +#define Z_IS_3562_EQ_3562(...) \, +#define Z_IS_3562U_EQ_3562(...) \, +#define Z_IS_3562_EQ_3562U(...) \, +#define Z_IS_3562U_EQ_3562U(...) \, +#define Z_IS_3563_EQ_3563(...) \, +#define Z_IS_3563U_EQ_3563(...) \, +#define Z_IS_3563_EQ_3563U(...) \, +#define Z_IS_3563U_EQ_3563U(...) \, +#define Z_IS_3564_EQ_3564(...) \, +#define Z_IS_3564U_EQ_3564(...) \, +#define Z_IS_3564_EQ_3564U(...) \, +#define Z_IS_3564U_EQ_3564U(...) \, +#define Z_IS_3565_EQ_3565(...) \, +#define Z_IS_3565U_EQ_3565(...) \, +#define Z_IS_3565_EQ_3565U(...) \, +#define Z_IS_3565U_EQ_3565U(...) \, +#define Z_IS_3566_EQ_3566(...) \, +#define Z_IS_3566U_EQ_3566(...) \, +#define Z_IS_3566_EQ_3566U(...) \, +#define Z_IS_3566U_EQ_3566U(...) \, +#define Z_IS_3567_EQ_3567(...) \, +#define Z_IS_3567U_EQ_3567(...) \, +#define Z_IS_3567_EQ_3567U(...) \, +#define Z_IS_3567U_EQ_3567U(...) \, +#define Z_IS_3568_EQ_3568(...) \, +#define Z_IS_3568U_EQ_3568(...) \, +#define Z_IS_3568_EQ_3568U(...) \, +#define Z_IS_3568U_EQ_3568U(...) \, +#define Z_IS_3569_EQ_3569(...) \, +#define Z_IS_3569U_EQ_3569(...) \, +#define Z_IS_3569_EQ_3569U(...) \, +#define Z_IS_3569U_EQ_3569U(...) \, +#define Z_IS_3570_EQ_3570(...) \, +#define Z_IS_3570U_EQ_3570(...) \, +#define Z_IS_3570_EQ_3570U(...) \, +#define Z_IS_3570U_EQ_3570U(...) \, +#define Z_IS_3571_EQ_3571(...) \, +#define Z_IS_3571U_EQ_3571(...) \, +#define Z_IS_3571_EQ_3571U(...) \, +#define Z_IS_3571U_EQ_3571U(...) \, +#define Z_IS_3572_EQ_3572(...) \, +#define Z_IS_3572U_EQ_3572(...) \, +#define Z_IS_3572_EQ_3572U(...) \, +#define Z_IS_3572U_EQ_3572U(...) \, +#define Z_IS_3573_EQ_3573(...) \, +#define Z_IS_3573U_EQ_3573(...) \, +#define Z_IS_3573_EQ_3573U(...) \, +#define Z_IS_3573U_EQ_3573U(...) \, +#define Z_IS_3574_EQ_3574(...) \, +#define Z_IS_3574U_EQ_3574(...) \, +#define Z_IS_3574_EQ_3574U(...) \, +#define Z_IS_3574U_EQ_3574U(...) \, +#define Z_IS_3575_EQ_3575(...) \, +#define Z_IS_3575U_EQ_3575(...) \, +#define Z_IS_3575_EQ_3575U(...) \, +#define Z_IS_3575U_EQ_3575U(...) \, +#define Z_IS_3576_EQ_3576(...) \, +#define Z_IS_3576U_EQ_3576(...) \, +#define Z_IS_3576_EQ_3576U(...) \, +#define Z_IS_3576U_EQ_3576U(...) \, +#define Z_IS_3577_EQ_3577(...) \, +#define Z_IS_3577U_EQ_3577(...) \, +#define Z_IS_3577_EQ_3577U(...) \, +#define Z_IS_3577U_EQ_3577U(...) \, +#define Z_IS_3578_EQ_3578(...) \, +#define Z_IS_3578U_EQ_3578(...) \, +#define Z_IS_3578_EQ_3578U(...) \, +#define Z_IS_3578U_EQ_3578U(...) \, +#define Z_IS_3579_EQ_3579(...) \, +#define Z_IS_3579U_EQ_3579(...) \, +#define Z_IS_3579_EQ_3579U(...) \, +#define Z_IS_3579U_EQ_3579U(...) \, +#define Z_IS_3580_EQ_3580(...) \, +#define Z_IS_3580U_EQ_3580(...) \, +#define Z_IS_3580_EQ_3580U(...) \, +#define Z_IS_3580U_EQ_3580U(...) \, +#define Z_IS_3581_EQ_3581(...) \, +#define Z_IS_3581U_EQ_3581(...) \, +#define Z_IS_3581_EQ_3581U(...) \, +#define Z_IS_3581U_EQ_3581U(...) \, +#define Z_IS_3582_EQ_3582(...) \, +#define Z_IS_3582U_EQ_3582(...) \, +#define Z_IS_3582_EQ_3582U(...) \, +#define Z_IS_3582U_EQ_3582U(...) \, +#define Z_IS_3583_EQ_3583(...) \, +#define Z_IS_3583U_EQ_3583(...) \, +#define Z_IS_3583_EQ_3583U(...) \, +#define Z_IS_3583U_EQ_3583U(...) \, +#define Z_IS_3584_EQ_3584(...) \, +#define Z_IS_3584U_EQ_3584(...) \, +#define Z_IS_3584_EQ_3584U(...) \, +#define Z_IS_3584U_EQ_3584U(...) \, +#define Z_IS_3585_EQ_3585(...) \, +#define Z_IS_3585U_EQ_3585(...) \, +#define Z_IS_3585_EQ_3585U(...) \, +#define Z_IS_3585U_EQ_3585U(...) \, +#define Z_IS_3586_EQ_3586(...) \, +#define Z_IS_3586U_EQ_3586(...) \, +#define Z_IS_3586_EQ_3586U(...) \, +#define Z_IS_3586U_EQ_3586U(...) \, +#define Z_IS_3587_EQ_3587(...) \, +#define Z_IS_3587U_EQ_3587(...) \, +#define Z_IS_3587_EQ_3587U(...) \, +#define Z_IS_3587U_EQ_3587U(...) \, +#define Z_IS_3588_EQ_3588(...) \, +#define Z_IS_3588U_EQ_3588(...) \, +#define Z_IS_3588_EQ_3588U(...) \, +#define Z_IS_3588U_EQ_3588U(...) \, +#define Z_IS_3589_EQ_3589(...) \, +#define Z_IS_3589U_EQ_3589(...) \, +#define Z_IS_3589_EQ_3589U(...) \, +#define Z_IS_3589U_EQ_3589U(...) \, +#define Z_IS_3590_EQ_3590(...) \, +#define Z_IS_3590U_EQ_3590(...) \, +#define Z_IS_3590_EQ_3590U(...) \, +#define Z_IS_3590U_EQ_3590U(...) \, +#define Z_IS_3591_EQ_3591(...) \, +#define Z_IS_3591U_EQ_3591(...) \, +#define Z_IS_3591_EQ_3591U(...) \, +#define Z_IS_3591U_EQ_3591U(...) \, +#define Z_IS_3592_EQ_3592(...) \, +#define Z_IS_3592U_EQ_3592(...) \, +#define Z_IS_3592_EQ_3592U(...) \, +#define Z_IS_3592U_EQ_3592U(...) \, +#define Z_IS_3593_EQ_3593(...) \, +#define Z_IS_3593U_EQ_3593(...) \, +#define Z_IS_3593_EQ_3593U(...) \, +#define Z_IS_3593U_EQ_3593U(...) \, +#define Z_IS_3594_EQ_3594(...) \, +#define Z_IS_3594U_EQ_3594(...) \, +#define Z_IS_3594_EQ_3594U(...) \, +#define Z_IS_3594U_EQ_3594U(...) \, +#define Z_IS_3595_EQ_3595(...) \, +#define Z_IS_3595U_EQ_3595(...) \, +#define Z_IS_3595_EQ_3595U(...) \, +#define Z_IS_3595U_EQ_3595U(...) \, +#define Z_IS_3596_EQ_3596(...) \, +#define Z_IS_3596U_EQ_3596(...) \, +#define Z_IS_3596_EQ_3596U(...) \, +#define Z_IS_3596U_EQ_3596U(...) \, +#define Z_IS_3597_EQ_3597(...) \, +#define Z_IS_3597U_EQ_3597(...) \, +#define Z_IS_3597_EQ_3597U(...) \, +#define Z_IS_3597U_EQ_3597U(...) \, +#define Z_IS_3598_EQ_3598(...) \, +#define Z_IS_3598U_EQ_3598(...) \, +#define Z_IS_3598_EQ_3598U(...) \, +#define Z_IS_3598U_EQ_3598U(...) \, +#define Z_IS_3599_EQ_3599(...) \, +#define Z_IS_3599U_EQ_3599(...) \, +#define Z_IS_3599_EQ_3599U(...) \, +#define Z_IS_3599U_EQ_3599U(...) \, +#define Z_IS_3600_EQ_3600(...) \, +#define Z_IS_3600U_EQ_3600(...) \, +#define Z_IS_3600_EQ_3600U(...) \, +#define Z_IS_3600U_EQ_3600U(...) \, +#define Z_IS_3601_EQ_3601(...) \, +#define Z_IS_3601U_EQ_3601(...) \, +#define Z_IS_3601_EQ_3601U(...) \, +#define Z_IS_3601U_EQ_3601U(...) \, +#define Z_IS_3602_EQ_3602(...) \, +#define Z_IS_3602U_EQ_3602(...) \, +#define Z_IS_3602_EQ_3602U(...) \, +#define Z_IS_3602U_EQ_3602U(...) \, +#define Z_IS_3603_EQ_3603(...) \, +#define Z_IS_3603U_EQ_3603(...) \, +#define Z_IS_3603_EQ_3603U(...) \, +#define Z_IS_3603U_EQ_3603U(...) \, +#define Z_IS_3604_EQ_3604(...) \, +#define Z_IS_3604U_EQ_3604(...) \, +#define Z_IS_3604_EQ_3604U(...) \, +#define Z_IS_3604U_EQ_3604U(...) \, +#define Z_IS_3605_EQ_3605(...) \, +#define Z_IS_3605U_EQ_3605(...) \, +#define Z_IS_3605_EQ_3605U(...) \, +#define Z_IS_3605U_EQ_3605U(...) \, +#define Z_IS_3606_EQ_3606(...) \, +#define Z_IS_3606U_EQ_3606(...) \, +#define Z_IS_3606_EQ_3606U(...) \, +#define Z_IS_3606U_EQ_3606U(...) \, +#define Z_IS_3607_EQ_3607(...) \, +#define Z_IS_3607U_EQ_3607(...) \, +#define Z_IS_3607_EQ_3607U(...) \, +#define Z_IS_3607U_EQ_3607U(...) \, +#define Z_IS_3608_EQ_3608(...) \, +#define Z_IS_3608U_EQ_3608(...) \, +#define Z_IS_3608_EQ_3608U(...) \, +#define Z_IS_3608U_EQ_3608U(...) \, +#define Z_IS_3609_EQ_3609(...) \, +#define Z_IS_3609U_EQ_3609(...) \, +#define Z_IS_3609_EQ_3609U(...) \, +#define Z_IS_3609U_EQ_3609U(...) \, +#define Z_IS_3610_EQ_3610(...) \, +#define Z_IS_3610U_EQ_3610(...) \, +#define Z_IS_3610_EQ_3610U(...) \, +#define Z_IS_3610U_EQ_3610U(...) \, +#define Z_IS_3611_EQ_3611(...) \, +#define Z_IS_3611U_EQ_3611(...) \, +#define Z_IS_3611_EQ_3611U(...) \, +#define Z_IS_3611U_EQ_3611U(...) \, +#define Z_IS_3612_EQ_3612(...) \, +#define Z_IS_3612U_EQ_3612(...) \, +#define Z_IS_3612_EQ_3612U(...) \, +#define Z_IS_3612U_EQ_3612U(...) \, +#define Z_IS_3613_EQ_3613(...) \, +#define Z_IS_3613U_EQ_3613(...) \, +#define Z_IS_3613_EQ_3613U(...) \, +#define Z_IS_3613U_EQ_3613U(...) \, +#define Z_IS_3614_EQ_3614(...) \, +#define Z_IS_3614U_EQ_3614(...) \, +#define Z_IS_3614_EQ_3614U(...) \, +#define Z_IS_3614U_EQ_3614U(...) \, +#define Z_IS_3615_EQ_3615(...) \, +#define Z_IS_3615U_EQ_3615(...) \, +#define Z_IS_3615_EQ_3615U(...) \, +#define Z_IS_3615U_EQ_3615U(...) \, +#define Z_IS_3616_EQ_3616(...) \, +#define Z_IS_3616U_EQ_3616(...) \, +#define Z_IS_3616_EQ_3616U(...) \, +#define Z_IS_3616U_EQ_3616U(...) \, +#define Z_IS_3617_EQ_3617(...) \, +#define Z_IS_3617U_EQ_3617(...) \, +#define Z_IS_3617_EQ_3617U(...) \, +#define Z_IS_3617U_EQ_3617U(...) \, +#define Z_IS_3618_EQ_3618(...) \, +#define Z_IS_3618U_EQ_3618(...) \, +#define Z_IS_3618_EQ_3618U(...) \, +#define Z_IS_3618U_EQ_3618U(...) \, +#define Z_IS_3619_EQ_3619(...) \, +#define Z_IS_3619U_EQ_3619(...) \, +#define Z_IS_3619_EQ_3619U(...) \, +#define Z_IS_3619U_EQ_3619U(...) \, +#define Z_IS_3620_EQ_3620(...) \, +#define Z_IS_3620U_EQ_3620(...) \, +#define Z_IS_3620_EQ_3620U(...) \, +#define Z_IS_3620U_EQ_3620U(...) \, +#define Z_IS_3621_EQ_3621(...) \, +#define Z_IS_3621U_EQ_3621(...) \, +#define Z_IS_3621_EQ_3621U(...) \, +#define Z_IS_3621U_EQ_3621U(...) \, +#define Z_IS_3622_EQ_3622(...) \, +#define Z_IS_3622U_EQ_3622(...) \, +#define Z_IS_3622_EQ_3622U(...) \, +#define Z_IS_3622U_EQ_3622U(...) \, +#define Z_IS_3623_EQ_3623(...) \, +#define Z_IS_3623U_EQ_3623(...) \, +#define Z_IS_3623_EQ_3623U(...) \, +#define Z_IS_3623U_EQ_3623U(...) \, +#define Z_IS_3624_EQ_3624(...) \, +#define Z_IS_3624U_EQ_3624(...) \, +#define Z_IS_3624_EQ_3624U(...) \, +#define Z_IS_3624U_EQ_3624U(...) \, +#define Z_IS_3625_EQ_3625(...) \, +#define Z_IS_3625U_EQ_3625(...) \, +#define Z_IS_3625_EQ_3625U(...) \, +#define Z_IS_3625U_EQ_3625U(...) \, +#define Z_IS_3626_EQ_3626(...) \, +#define Z_IS_3626U_EQ_3626(...) \, +#define Z_IS_3626_EQ_3626U(...) \, +#define Z_IS_3626U_EQ_3626U(...) \, +#define Z_IS_3627_EQ_3627(...) \, +#define Z_IS_3627U_EQ_3627(...) \, +#define Z_IS_3627_EQ_3627U(...) \, +#define Z_IS_3627U_EQ_3627U(...) \, +#define Z_IS_3628_EQ_3628(...) \, +#define Z_IS_3628U_EQ_3628(...) \, +#define Z_IS_3628_EQ_3628U(...) \, +#define Z_IS_3628U_EQ_3628U(...) \, +#define Z_IS_3629_EQ_3629(...) \, +#define Z_IS_3629U_EQ_3629(...) \, +#define Z_IS_3629_EQ_3629U(...) \, +#define Z_IS_3629U_EQ_3629U(...) \, +#define Z_IS_3630_EQ_3630(...) \, +#define Z_IS_3630U_EQ_3630(...) \, +#define Z_IS_3630_EQ_3630U(...) \, +#define Z_IS_3630U_EQ_3630U(...) \, +#define Z_IS_3631_EQ_3631(...) \, +#define Z_IS_3631U_EQ_3631(...) \, +#define Z_IS_3631_EQ_3631U(...) \, +#define Z_IS_3631U_EQ_3631U(...) \, +#define Z_IS_3632_EQ_3632(...) \, +#define Z_IS_3632U_EQ_3632(...) \, +#define Z_IS_3632_EQ_3632U(...) \, +#define Z_IS_3632U_EQ_3632U(...) \, +#define Z_IS_3633_EQ_3633(...) \, +#define Z_IS_3633U_EQ_3633(...) \, +#define Z_IS_3633_EQ_3633U(...) \, +#define Z_IS_3633U_EQ_3633U(...) \, +#define Z_IS_3634_EQ_3634(...) \, +#define Z_IS_3634U_EQ_3634(...) \, +#define Z_IS_3634_EQ_3634U(...) \, +#define Z_IS_3634U_EQ_3634U(...) \, +#define Z_IS_3635_EQ_3635(...) \, +#define Z_IS_3635U_EQ_3635(...) \, +#define Z_IS_3635_EQ_3635U(...) \, +#define Z_IS_3635U_EQ_3635U(...) \, +#define Z_IS_3636_EQ_3636(...) \, +#define Z_IS_3636U_EQ_3636(...) \, +#define Z_IS_3636_EQ_3636U(...) \, +#define Z_IS_3636U_EQ_3636U(...) \, +#define Z_IS_3637_EQ_3637(...) \, +#define Z_IS_3637U_EQ_3637(...) \, +#define Z_IS_3637_EQ_3637U(...) \, +#define Z_IS_3637U_EQ_3637U(...) \, +#define Z_IS_3638_EQ_3638(...) \, +#define Z_IS_3638U_EQ_3638(...) \, +#define Z_IS_3638_EQ_3638U(...) \, +#define Z_IS_3638U_EQ_3638U(...) \, +#define Z_IS_3639_EQ_3639(...) \, +#define Z_IS_3639U_EQ_3639(...) \, +#define Z_IS_3639_EQ_3639U(...) \, +#define Z_IS_3639U_EQ_3639U(...) \, +#define Z_IS_3640_EQ_3640(...) \, +#define Z_IS_3640U_EQ_3640(...) \, +#define Z_IS_3640_EQ_3640U(...) \, +#define Z_IS_3640U_EQ_3640U(...) \, +#define Z_IS_3641_EQ_3641(...) \, +#define Z_IS_3641U_EQ_3641(...) \, +#define Z_IS_3641_EQ_3641U(...) \, +#define Z_IS_3641U_EQ_3641U(...) \, +#define Z_IS_3642_EQ_3642(...) \, +#define Z_IS_3642U_EQ_3642(...) \, +#define Z_IS_3642_EQ_3642U(...) \, +#define Z_IS_3642U_EQ_3642U(...) \, +#define Z_IS_3643_EQ_3643(...) \, +#define Z_IS_3643U_EQ_3643(...) \, +#define Z_IS_3643_EQ_3643U(...) \, +#define Z_IS_3643U_EQ_3643U(...) \, +#define Z_IS_3644_EQ_3644(...) \, +#define Z_IS_3644U_EQ_3644(...) \, +#define Z_IS_3644_EQ_3644U(...) \, +#define Z_IS_3644U_EQ_3644U(...) \, +#define Z_IS_3645_EQ_3645(...) \, +#define Z_IS_3645U_EQ_3645(...) \, +#define Z_IS_3645_EQ_3645U(...) \, +#define Z_IS_3645U_EQ_3645U(...) \, +#define Z_IS_3646_EQ_3646(...) \, +#define Z_IS_3646U_EQ_3646(...) \, +#define Z_IS_3646_EQ_3646U(...) \, +#define Z_IS_3646U_EQ_3646U(...) \, +#define Z_IS_3647_EQ_3647(...) \, +#define Z_IS_3647U_EQ_3647(...) \, +#define Z_IS_3647_EQ_3647U(...) \, +#define Z_IS_3647U_EQ_3647U(...) \, +#define Z_IS_3648_EQ_3648(...) \, +#define Z_IS_3648U_EQ_3648(...) \, +#define Z_IS_3648_EQ_3648U(...) \, +#define Z_IS_3648U_EQ_3648U(...) \, +#define Z_IS_3649_EQ_3649(...) \, +#define Z_IS_3649U_EQ_3649(...) \, +#define Z_IS_3649_EQ_3649U(...) \, +#define Z_IS_3649U_EQ_3649U(...) \, +#define Z_IS_3650_EQ_3650(...) \, +#define Z_IS_3650U_EQ_3650(...) \, +#define Z_IS_3650_EQ_3650U(...) \, +#define Z_IS_3650U_EQ_3650U(...) \, +#define Z_IS_3651_EQ_3651(...) \, +#define Z_IS_3651U_EQ_3651(...) \, +#define Z_IS_3651_EQ_3651U(...) \, +#define Z_IS_3651U_EQ_3651U(...) \, +#define Z_IS_3652_EQ_3652(...) \, +#define Z_IS_3652U_EQ_3652(...) \, +#define Z_IS_3652_EQ_3652U(...) \, +#define Z_IS_3652U_EQ_3652U(...) \, +#define Z_IS_3653_EQ_3653(...) \, +#define Z_IS_3653U_EQ_3653(...) \, +#define Z_IS_3653_EQ_3653U(...) \, +#define Z_IS_3653U_EQ_3653U(...) \, +#define Z_IS_3654_EQ_3654(...) \, +#define Z_IS_3654U_EQ_3654(...) \, +#define Z_IS_3654_EQ_3654U(...) \, +#define Z_IS_3654U_EQ_3654U(...) \, +#define Z_IS_3655_EQ_3655(...) \, +#define Z_IS_3655U_EQ_3655(...) \, +#define Z_IS_3655_EQ_3655U(...) \, +#define Z_IS_3655U_EQ_3655U(...) \, +#define Z_IS_3656_EQ_3656(...) \, +#define Z_IS_3656U_EQ_3656(...) \, +#define Z_IS_3656_EQ_3656U(...) \, +#define Z_IS_3656U_EQ_3656U(...) \, +#define Z_IS_3657_EQ_3657(...) \, +#define Z_IS_3657U_EQ_3657(...) \, +#define Z_IS_3657_EQ_3657U(...) \, +#define Z_IS_3657U_EQ_3657U(...) \, +#define Z_IS_3658_EQ_3658(...) \, +#define Z_IS_3658U_EQ_3658(...) \, +#define Z_IS_3658_EQ_3658U(...) \, +#define Z_IS_3658U_EQ_3658U(...) \, +#define Z_IS_3659_EQ_3659(...) \, +#define Z_IS_3659U_EQ_3659(...) \, +#define Z_IS_3659_EQ_3659U(...) \, +#define Z_IS_3659U_EQ_3659U(...) \, +#define Z_IS_3660_EQ_3660(...) \, +#define Z_IS_3660U_EQ_3660(...) \, +#define Z_IS_3660_EQ_3660U(...) \, +#define Z_IS_3660U_EQ_3660U(...) \, +#define Z_IS_3661_EQ_3661(...) \, +#define Z_IS_3661U_EQ_3661(...) \, +#define Z_IS_3661_EQ_3661U(...) \, +#define Z_IS_3661U_EQ_3661U(...) \, +#define Z_IS_3662_EQ_3662(...) \, +#define Z_IS_3662U_EQ_3662(...) \, +#define Z_IS_3662_EQ_3662U(...) \, +#define Z_IS_3662U_EQ_3662U(...) \, +#define Z_IS_3663_EQ_3663(...) \, +#define Z_IS_3663U_EQ_3663(...) \, +#define Z_IS_3663_EQ_3663U(...) \, +#define Z_IS_3663U_EQ_3663U(...) \, +#define Z_IS_3664_EQ_3664(...) \, +#define Z_IS_3664U_EQ_3664(...) \, +#define Z_IS_3664_EQ_3664U(...) \, +#define Z_IS_3664U_EQ_3664U(...) \, +#define Z_IS_3665_EQ_3665(...) \, +#define Z_IS_3665U_EQ_3665(...) \, +#define Z_IS_3665_EQ_3665U(...) \, +#define Z_IS_3665U_EQ_3665U(...) \, +#define Z_IS_3666_EQ_3666(...) \, +#define Z_IS_3666U_EQ_3666(...) \, +#define Z_IS_3666_EQ_3666U(...) \, +#define Z_IS_3666U_EQ_3666U(...) \, +#define Z_IS_3667_EQ_3667(...) \, +#define Z_IS_3667U_EQ_3667(...) \, +#define Z_IS_3667_EQ_3667U(...) \, +#define Z_IS_3667U_EQ_3667U(...) \, +#define Z_IS_3668_EQ_3668(...) \, +#define Z_IS_3668U_EQ_3668(...) \, +#define Z_IS_3668_EQ_3668U(...) \, +#define Z_IS_3668U_EQ_3668U(...) \, +#define Z_IS_3669_EQ_3669(...) \, +#define Z_IS_3669U_EQ_3669(...) \, +#define Z_IS_3669_EQ_3669U(...) \, +#define Z_IS_3669U_EQ_3669U(...) \, +#define Z_IS_3670_EQ_3670(...) \, +#define Z_IS_3670U_EQ_3670(...) \, +#define Z_IS_3670_EQ_3670U(...) \, +#define Z_IS_3670U_EQ_3670U(...) \, +#define Z_IS_3671_EQ_3671(...) \, +#define Z_IS_3671U_EQ_3671(...) \, +#define Z_IS_3671_EQ_3671U(...) \, +#define Z_IS_3671U_EQ_3671U(...) \, +#define Z_IS_3672_EQ_3672(...) \, +#define Z_IS_3672U_EQ_3672(...) \, +#define Z_IS_3672_EQ_3672U(...) \, +#define Z_IS_3672U_EQ_3672U(...) \, +#define Z_IS_3673_EQ_3673(...) \, +#define Z_IS_3673U_EQ_3673(...) \, +#define Z_IS_3673_EQ_3673U(...) \, +#define Z_IS_3673U_EQ_3673U(...) \, +#define Z_IS_3674_EQ_3674(...) \, +#define Z_IS_3674U_EQ_3674(...) \, +#define Z_IS_3674_EQ_3674U(...) \, +#define Z_IS_3674U_EQ_3674U(...) \, +#define Z_IS_3675_EQ_3675(...) \, +#define Z_IS_3675U_EQ_3675(...) \, +#define Z_IS_3675_EQ_3675U(...) \, +#define Z_IS_3675U_EQ_3675U(...) \, +#define Z_IS_3676_EQ_3676(...) \, +#define Z_IS_3676U_EQ_3676(...) \, +#define Z_IS_3676_EQ_3676U(...) \, +#define Z_IS_3676U_EQ_3676U(...) \, +#define Z_IS_3677_EQ_3677(...) \, +#define Z_IS_3677U_EQ_3677(...) \, +#define Z_IS_3677_EQ_3677U(...) \, +#define Z_IS_3677U_EQ_3677U(...) \, +#define Z_IS_3678_EQ_3678(...) \, +#define Z_IS_3678U_EQ_3678(...) \, +#define Z_IS_3678_EQ_3678U(...) \, +#define Z_IS_3678U_EQ_3678U(...) \, +#define Z_IS_3679_EQ_3679(...) \, +#define Z_IS_3679U_EQ_3679(...) \, +#define Z_IS_3679_EQ_3679U(...) \, +#define Z_IS_3679U_EQ_3679U(...) \, +#define Z_IS_3680_EQ_3680(...) \, +#define Z_IS_3680U_EQ_3680(...) \, +#define Z_IS_3680_EQ_3680U(...) \, +#define Z_IS_3680U_EQ_3680U(...) \, +#define Z_IS_3681_EQ_3681(...) \, +#define Z_IS_3681U_EQ_3681(...) \, +#define Z_IS_3681_EQ_3681U(...) \, +#define Z_IS_3681U_EQ_3681U(...) \, +#define Z_IS_3682_EQ_3682(...) \, +#define Z_IS_3682U_EQ_3682(...) \, +#define Z_IS_3682_EQ_3682U(...) \, +#define Z_IS_3682U_EQ_3682U(...) \, +#define Z_IS_3683_EQ_3683(...) \, +#define Z_IS_3683U_EQ_3683(...) \, +#define Z_IS_3683_EQ_3683U(...) \, +#define Z_IS_3683U_EQ_3683U(...) \, +#define Z_IS_3684_EQ_3684(...) \, +#define Z_IS_3684U_EQ_3684(...) \, +#define Z_IS_3684_EQ_3684U(...) \, +#define Z_IS_3684U_EQ_3684U(...) \, +#define Z_IS_3685_EQ_3685(...) \, +#define Z_IS_3685U_EQ_3685(...) \, +#define Z_IS_3685_EQ_3685U(...) \, +#define Z_IS_3685U_EQ_3685U(...) \, +#define Z_IS_3686_EQ_3686(...) \, +#define Z_IS_3686U_EQ_3686(...) \, +#define Z_IS_3686_EQ_3686U(...) \, +#define Z_IS_3686U_EQ_3686U(...) \, +#define Z_IS_3687_EQ_3687(...) \, +#define Z_IS_3687U_EQ_3687(...) \, +#define Z_IS_3687_EQ_3687U(...) \, +#define Z_IS_3687U_EQ_3687U(...) \, +#define Z_IS_3688_EQ_3688(...) \, +#define Z_IS_3688U_EQ_3688(...) \, +#define Z_IS_3688_EQ_3688U(...) \, +#define Z_IS_3688U_EQ_3688U(...) \, +#define Z_IS_3689_EQ_3689(...) \, +#define Z_IS_3689U_EQ_3689(...) \, +#define Z_IS_3689_EQ_3689U(...) \, +#define Z_IS_3689U_EQ_3689U(...) \, +#define Z_IS_3690_EQ_3690(...) \, +#define Z_IS_3690U_EQ_3690(...) \, +#define Z_IS_3690_EQ_3690U(...) \, +#define Z_IS_3690U_EQ_3690U(...) \, +#define Z_IS_3691_EQ_3691(...) \, +#define Z_IS_3691U_EQ_3691(...) \, +#define Z_IS_3691_EQ_3691U(...) \, +#define Z_IS_3691U_EQ_3691U(...) \, +#define Z_IS_3692_EQ_3692(...) \, +#define Z_IS_3692U_EQ_3692(...) \, +#define Z_IS_3692_EQ_3692U(...) \, +#define Z_IS_3692U_EQ_3692U(...) \, +#define Z_IS_3693_EQ_3693(...) \, +#define Z_IS_3693U_EQ_3693(...) \, +#define Z_IS_3693_EQ_3693U(...) \, +#define Z_IS_3693U_EQ_3693U(...) \, +#define Z_IS_3694_EQ_3694(...) \, +#define Z_IS_3694U_EQ_3694(...) \, +#define Z_IS_3694_EQ_3694U(...) \, +#define Z_IS_3694U_EQ_3694U(...) \, +#define Z_IS_3695_EQ_3695(...) \, +#define Z_IS_3695U_EQ_3695(...) \, +#define Z_IS_3695_EQ_3695U(...) \, +#define Z_IS_3695U_EQ_3695U(...) \, +#define Z_IS_3696_EQ_3696(...) \, +#define Z_IS_3696U_EQ_3696(...) \, +#define Z_IS_3696_EQ_3696U(...) \, +#define Z_IS_3696U_EQ_3696U(...) \, +#define Z_IS_3697_EQ_3697(...) \, +#define Z_IS_3697U_EQ_3697(...) \, +#define Z_IS_3697_EQ_3697U(...) \, +#define Z_IS_3697U_EQ_3697U(...) \, +#define Z_IS_3698_EQ_3698(...) \, +#define Z_IS_3698U_EQ_3698(...) \, +#define Z_IS_3698_EQ_3698U(...) \, +#define Z_IS_3698U_EQ_3698U(...) \, +#define Z_IS_3699_EQ_3699(...) \, +#define Z_IS_3699U_EQ_3699(...) \, +#define Z_IS_3699_EQ_3699U(...) \, +#define Z_IS_3699U_EQ_3699U(...) \, +#define Z_IS_3700_EQ_3700(...) \, +#define Z_IS_3700U_EQ_3700(...) \, +#define Z_IS_3700_EQ_3700U(...) \, +#define Z_IS_3700U_EQ_3700U(...) \, +#define Z_IS_3701_EQ_3701(...) \, +#define Z_IS_3701U_EQ_3701(...) \, +#define Z_IS_3701_EQ_3701U(...) \, +#define Z_IS_3701U_EQ_3701U(...) \, +#define Z_IS_3702_EQ_3702(...) \, +#define Z_IS_3702U_EQ_3702(...) \, +#define Z_IS_3702_EQ_3702U(...) \, +#define Z_IS_3702U_EQ_3702U(...) \, +#define Z_IS_3703_EQ_3703(...) \, +#define Z_IS_3703U_EQ_3703(...) \, +#define Z_IS_3703_EQ_3703U(...) \, +#define Z_IS_3703U_EQ_3703U(...) \, +#define Z_IS_3704_EQ_3704(...) \, +#define Z_IS_3704U_EQ_3704(...) \, +#define Z_IS_3704_EQ_3704U(...) \, +#define Z_IS_3704U_EQ_3704U(...) \, +#define Z_IS_3705_EQ_3705(...) \, +#define Z_IS_3705U_EQ_3705(...) \, +#define Z_IS_3705_EQ_3705U(...) \, +#define Z_IS_3705U_EQ_3705U(...) \, +#define Z_IS_3706_EQ_3706(...) \, +#define Z_IS_3706U_EQ_3706(...) \, +#define Z_IS_3706_EQ_3706U(...) \, +#define Z_IS_3706U_EQ_3706U(...) \, +#define Z_IS_3707_EQ_3707(...) \, +#define Z_IS_3707U_EQ_3707(...) \, +#define Z_IS_3707_EQ_3707U(...) \, +#define Z_IS_3707U_EQ_3707U(...) \, +#define Z_IS_3708_EQ_3708(...) \, +#define Z_IS_3708U_EQ_3708(...) \, +#define Z_IS_3708_EQ_3708U(...) \, +#define Z_IS_3708U_EQ_3708U(...) \, +#define Z_IS_3709_EQ_3709(...) \, +#define Z_IS_3709U_EQ_3709(...) \, +#define Z_IS_3709_EQ_3709U(...) \, +#define Z_IS_3709U_EQ_3709U(...) \, +#define Z_IS_3710_EQ_3710(...) \, +#define Z_IS_3710U_EQ_3710(...) \, +#define Z_IS_3710_EQ_3710U(...) \, +#define Z_IS_3710U_EQ_3710U(...) \, +#define Z_IS_3711_EQ_3711(...) \, +#define Z_IS_3711U_EQ_3711(...) \, +#define Z_IS_3711_EQ_3711U(...) \, +#define Z_IS_3711U_EQ_3711U(...) \, +#define Z_IS_3712_EQ_3712(...) \, +#define Z_IS_3712U_EQ_3712(...) \, +#define Z_IS_3712_EQ_3712U(...) \, +#define Z_IS_3712U_EQ_3712U(...) \, +#define Z_IS_3713_EQ_3713(...) \, +#define Z_IS_3713U_EQ_3713(...) \, +#define Z_IS_3713_EQ_3713U(...) \, +#define Z_IS_3713U_EQ_3713U(...) \, +#define Z_IS_3714_EQ_3714(...) \, +#define Z_IS_3714U_EQ_3714(...) \, +#define Z_IS_3714_EQ_3714U(...) \, +#define Z_IS_3714U_EQ_3714U(...) \, +#define Z_IS_3715_EQ_3715(...) \, +#define Z_IS_3715U_EQ_3715(...) \, +#define Z_IS_3715_EQ_3715U(...) \, +#define Z_IS_3715U_EQ_3715U(...) \, +#define Z_IS_3716_EQ_3716(...) \, +#define Z_IS_3716U_EQ_3716(...) \, +#define Z_IS_3716_EQ_3716U(...) \, +#define Z_IS_3716U_EQ_3716U(...) \, +#define Z_IS_3717_EQ_3717(...) \, +#define Z_IS_3717U_EQ_3717(...) \, +#define Z_IS_3717_EQ_3717U(...) \, +#define Z_IS_3717U_EQ_3717U(...) \, +#define Z_IS_3718_EQ_3718(...) \, +#define Z_IS_3718U_EQ_3718(...) \, +#define Z_IS_3718_EQ_3718U(...) \, +#define Z_IS_3718U_EQ_3718U(...) \, +#define Z_IS_3719_EQ_3719(...) \, +#define Z_IS_3719U_EQ_3719(...) \, +#define Z_IS_3719_EQ_3719U(...) \, +#define Z_IS_3719U_EQ_3719U(...) \, +#define Z_IS_3720_EQ_3720(...) \, +#define Z_IS_3720U_EQ_3720(...) \, +#define Z_IS_3720_EQ_3720U(...) \, +#define Z_IS_3720U_EQ_3720U(...) \, +#define Z_IS_3721_EQ_3721(...) \, +#define Z_IS_3721U_EQ_3721(...) \, +#define Z_IS_3721_EQ_3721U(...) \, +#define Z_IS_3721U_EQ_3721U(...) \, +#define Z_IS_3722_EQ_3722(...) \, +#define Z_IS_3722U_EQ_3722(...) \, +#define Z_IS_3722_EQ_3722U(...) \, +#define Z_IS_3722U_EQ_3722U(...) \, +#define Z_IS_3723_EQ_3723(...) \, +#define Z_IS_3723U_EQ_3723(...) \, +#define Z_IS_3723_EQ_3723U(...) \, +#define Z_IS_3723U_EQ_3723U(...) \, +#define Z_IS_3724_EQ_3724(...) \, +#define Z_IS_3724U_EQ_3724(...) \, +#define Z_IS_3724_EQ_3724U(...) \, +#define Z_IS_3724U_EQ_3724U(...) \, +#define Z_IS_3725_EQ_3725(...) \, +#define Z_IS_3725U_EQ_3725(...) \, +#define Z_IS_3725_EQ_3725U(...) \, +#define Z_IS_3725U_EQ_3725U(...) \, +#define Z_IS_3726_EQ_3726(...) \, +#define Z_IS_3726U_EQ_3726(...) \, +#define Z_IS_3726_EQ_3726U(...) \, +#define Z_IS_3726U_EQ_3726U(...) \, +#define Z_IS_3727_EQ_3727(...) \, +#define Z_IS_3727U_EQ_3727(...) \, +#define Z_IS_3727_EQ_3727U(...) \, +#define Z_IS_3727U_EQ_3727U(...) \, +#define Z_IS_3728_EQ_3728(...) \, +#define Z_IS_3728U_EQ_3728(...) \, +#define Z_IS_3728_EQ_3728U(...) \, +#define Z_IS_3728U_EQ_3728U(...) \, +#define Z_IS_3729_EQ_3729(...) \, +#define Z_IS_3729U_EQ_3729(...) \, +#define Z_IS_3729_EQ_3729U(...) \, +#define Z_IS_3729U_EQ_3729U(...) \, +#define Z_IS_3730_EQ_3730(...) \, +#define Z_IS_3730U_EQ_3730(...) \, +#define Z_IS_3730_EQ_3730U(...) \, +#define Z_IS_3730U_EQ_3730U(...) \, +#define Z_IS_3731_EQ_3731(...) \, +#define Z_IS_3731U_EQ_3731(...) \, +#define Z_IS_3731_EQ_3731U(...) \, +#define Z_IS_3731U_EQ_3731U(...) \, +#define Z_IS_3732_EQ_3732(...) \, +#define Z_IS_3732U_EQ_3732(...) \, +#define Z_IS_3732_EQ_3732U(...) \, +#define Z_IS_3732U_EQ_3732U(...) \, +#define Z_IS_3733_EQ_3733(...) \, +#define Z_IS_3733U_EQ_3733(...) \, +#define Z_IS_3733_EQ_3733U(...) \, +#define Z_IS_3733U_EQ_3733U(...) \, +#define Z_IS_3734_EQ_3734(...) \, +#define Z_IS_3734U_EQ_3734(...) \, +#define Z_IS_3734_EQ_3734U(...) \, +#define Z_IS_3734U_EQ_3734U(...) \, +#define Z_IS_3735_EQ_3735(...) \, +#define Z_IS_3735U_EQ_3735(...) \, +#define Z_IS_3735_EQ_3735U(...) \, +#define Z_IS_3735U_EQ_3735U(...) \, +#define Z_IS_3736_EQ_3736(...) \, +#define Z_IS_3736U_EQ_3736(...) \, +#define Z_IS_3736_EQ_3736U(...) \, +#define Z_IS_3736U_EQ_3736U(...) \, +#define Z_IS_3737_EQ_3737(...) \, +#define Z_IS_3737U_EQ_3737(...) \, +#define Z_IS_3737_EQ_3737U(...) \, +#define Z_IS_3737U_EQ_3737U(...) \, +#define Z_IS_3738_EQ_3738(...) \, +#define Z_IS_3738U_EQ_3738(...) \, +#define Z_IS_3738_EQ_3738U(...) \, +#define Z_IS_3738U_EQ_3738U(...) \, +#define Z_IS_3739_EQ_3739(...) \, +#define Z_IS_3739U_EQ_3739(...) \, +#define Z_IS_3739_EQ_3739U(...) \, +#define Z_IS_3739U_EQ_3739U(...) \, +#define Z_IS_3740_EQ_3740(...) \, +#define Z_IS_3740U_EQ_3740(...) \, +#define Z_IS_3740_EQ_3740U(...) \, +#define Z_IS_3740U_EQ_3740U(...) \, +#define Z_IS_3741_EQ_3741(...) \, +#define Z_IS_3741U_EQ_3741(...) \, +#define Z_IS_3741_EQ_3741U(...) \, +#define Z_IS_3741U_EQ_3741U(...) \, +#define Z_IS_3742_EQ_3742(...) \, +#define Z_IS_3742U_EQ_3742(...) \, +#define Z_IS_3742_EQ_3742U(...) \, +#define Z_IS_3742U_EQ_3742U(...) \, +#define Z_IS_3743_EQ_3743(...) \, +#define Z_IS_3743U_EQ_3743(...) \, +#define Z_IS_3743_EQ_3743U(...) \, +#define Z_IS_3743U_EQ_3743U(...) \, +#define Z_IS_3744_EQ_3744(...) \, +#define Z_IS_3744U_EQ_3744(...) \, +#define Z_IS_3744_EQ_3744U(...) \, +#define Z_IS_3744U_EQ_3744U(...) \, +#define Z_IS_3745_EQ_3745(...) \, +#define Z_IS_3745U_EQ_3745(...) \, +#define Z_IS_3745_EQ_3745U(...) \, +#define Z_IS_3745U_EQ_3745U(...) \, +#define Z_IS_3746_EQ_3746(...) \, +#define Z_IS_3746U_EQ_3746(...) \, +#define Z_IS_3746_EQ_3746U(...) \, +#define Z_IS_3746U_EQ_3746U(...) \, +#define Z_IS_3747_EQ_3747(...) \, +#define Z_IS_3747U_EQ_3747(...) \, +#define Z_IS_3747_EQ_3747U(...) \, +#define Z_IS_3747U_EQ_3747U(...) \, +#define Z_IS_3748_EQ_3748(...) \, +#define Z_IS_3748U_EQ_3748(...) \, +#define Z_IS_3748_EQ_3748U(...) \, +#define Z_IS_3748U_EQ_3748U(...) \, +#define Z_IS_3749_EQ_3749(...) \, +#define Z_IS_3749U_EQ_3749(...) \, +#define Z_IS_3749_EQ_3749U(...) \, +#define Z_IS_3749U_EQ_3749U(...) \, +#define Z_IS_3750_EQ_3750(...) \, +#define Z_IS_3750U_EQ_3750(...) \, +#define Z_IS_3750_EQ_3750U(...) \, +#define Z_IS_3750U_EQ_3750U(...) \, +#define Z_IS_3751_EQ_3751(...) \, +#define Z_IS_3751U_EQ_3751(...) \, +#define Z_IS_3751_EQ_3751U(...) \, +#define Z_IS_3751U_EQ_3751U(...) \, +#define Z_IS_3752_EQ_3752(...) \, +#define Z_IS_3752U_EQ_3752(...) \, +#define Z_IS_3752_EQ_3752U(...) \, +#define Z_IS_3752U_EQ_3752U(...) \, +#define Z_IS_3753_EQ_3753(...) \, +#define Z_IS_3753U_EQ_3753(...) \, +#define Z_IS_3753_EQ_3753U(...) \, +#define Z_IS_3753U_EQ_3753U(...) \, +#define Z_IS_3754_EQ_3754(...) \, +#define Z_IS_3754U_EQ_3754(...) \, +#define Z_IS_3754_EQ_3754U(...) \, +#define Z_IS_3754U_EQ_3754U(...) \, +#define Z_IS_3755_EQ_3755(...) \, +#define Z_IS_3755U_EQ_3755(...) \, +#define Z_IS_3755_EQ_3755U(...) \, +#define Z_IS_3755U_EQ_3755U(...) \, +#define Z_IS_3756_EQ_3756(...) \, +#define Z_IS_3756U_EQ_3756(...) \, +#define Z_IS_3756_EQ_3756U(...) \, +#define Z_IS_3756U_EQ_3756U(...) \, +#define Z_IS_3757_EQ_3757(...) \, +#define Z_IS_3757U_EQ_3757(...) \, +#define Z_IS_3757_EQ_3757U(...) \, +#define Z_IS_3757U_EQ_3757U(...) \, +#define Z_IS_3758_EQ_3758(...) \, +#define Z_IS_3758U_EQ_3758(...) \, +#define Z_IS_3758_EQ_3758U(...) \, +#define Z_IS_3758U_EQ_3758U(...) \, +#define Z_IS_3759_EQ_3759(...) \, +#define Z_IS_3759U_EQ_3759(...) \, +#define Z_IS_3759_EQ_3759U(...) \, +#define Z_IS_3759U_EQ_3759U(...) \, +#define Z_IS_3760_EQ_3760(...) \, +#define Z_IS_3760U_EQ_3760(...) \, +#define Z_IS_3760_EQ_3760U(...) \, +#define Z_IS_3760U_EQ_3760U(...) \, +#define Z_IS_3761_EQ_3761(...) \, +#define Z_IS_3761U_EQ_3761(...) \, +#define Z_IS_3761_EQ_3761U(...) \, +#define Z_IS_3761U_EQ_3761U(...) \, +#define Z_IS_3762_EQ_3762(...) \, +#define Z_IS_3762U_EQ_3762(...) \, +#define Z_IS_3762_EQ_3762U(...) \, +#define Z_IS_3762U_EQ_3762U(...) \, +#define Z_IS_3763_EQ_3763(...) \, +#define Z_IS_3763U_EQ_3763(...) \, +#define Z_IS_3763_EQ_3763U(...) \, +#define Z_IS_3763U_EQ_3763U(...) \, +#define Z_IS_3764_EQ_3764(...) \, +#define Z_IS_3764U_EQ_3764(...) \, +#define Z_IS_3764_EQ_3764U(...) \, +#define Z_IS_3764U_EQ_3764U(...) \, +#define Z_IS_3765_EQ_3765(...) \, +#define Z_IS_3765U_EQ_3765(...) \, +#define Z_IS_3765_EQ_3765U(...) \, +#define Z_IS_3765U_EQ_3765U(...) \, +#define Z_IS_3766_EQ_3766(...) \, +#define Z_IS_3766U_EQ_3766(...) \, +#define Z_IS_3766_EQ_3766U(...) \, +#define Z_IS_3766U_EQ_3766U(...) \, +#define Z_IS_3767_EQ_3767(...) \, +#define Z_IS_3767U_EQ_3767(...) \, +#define Z_IS_3767_EQ_3767U(...) \, +#define Z_IS_3767U_EQ_3767U(...) \, +#define Z_IS_3768_EQ_3768(...) \, +#define Z_IS_3768U_EQ_3768(...) \, +#define Z_IS_3768_EQ_3768U(...) \, +#define Z_IS_3768U_EQ_3768U(...) \, +#define Z_IS_3769_EQ_3769(...) \, +#define Z_IS_3769U_EQ_3769(...) \, +#define Z_IS_3769_EQ_3769U(...) \, +#define Z_IS_3769U_EQ_3769U(...) \, +#define Z_IS_3770_EQ_3770(...) \, +#define Z_IS_3770U_EQ_3770(...) \, +#define Z_IS_3770_EQ_3770U(...) \, +#define Z_IS_3770U_EQ_3770U(...) \, +#define Z_IS_3771_EQ_3771(...) \, +#define Z_IS_3771U_EQ_3771(...) \, +#define Z_IS_3771_EQ_3771U(...) \, +#define Z_IS_3771U_EQ_3771U(...) \, +#define Z_IS_3772_EQ_3772(...) \, +#define Z_IS_3772U_EQ_3772(...) \, +#define Z_IS_3772_EQ_3772U(...) \, +#define Z_IS_3772U_EQ_3772U(...) \, +#define Z_IS_3773_EQ_3773(...) \, +#define Z_IS_3773U_EQ_3773(...) \, +#define Z_IS_3773_EQ_3773U(...) \, +#define Z_IS_3773U_EQ_3773U(...) \, +#define Z_IS_3774_EQ_3774(...) \, +#define Z_IS_3774U_EQ_3774(...) \, +#define Z_IS_3774_EQ_3774U(...) \, +#define Z_IS_3774U_EQ_3774U(...) \, +#define Z_IS_3775_EQ_3775(...) \, +#define Z_IS_3775U_EQ_3775(...) \, +#define Z_IS_3775_EQ_3775U(...) \, +#define Z_IS_3775U_EQ_3775U(...) \, +#define Z_IS_3776_EQ_3776(...) \, +#define Z_IS_3776U_EQ_3776(...) \, +#define Z_IS_3776_EQ_3776U(...) \, +#define Z_IS_3776U_EQ_3776U(...) \, +#define Z_IS_3777_EQ_3777(...) \, +#define Z_IS_3777U_EQ_3777(...) \, +#define Z_IS_3777_EQ_3777U(...) \, +#define Z_IS_3777U_EQ_3777U(...) \, +#define Z_IS_3778_EQ_3778(...) \, +#define Z_IS_3778U_EQ_3778(...) \, +#define Z_IS_3778_EQ_3778U(...) \, +#define Z_IS_3778U_EQ_3778U(...) \, +#define Z_IS_3779_EQ_3779(...) \, +#define Z_IS_3779U_EQ_3779(...) \, +#define Z_IS_3779_EQ_3779U(...) \, +#define Z_IS_3779U_EQ_3779U(...) \, +#define Z_IS_3780_EQ_3780(...) \, +#define Z_IS_3780U_EQ_3780(...) \, +#define Z_IS_3780_EQ_3780U(...) \, +#define Z_IS_3780U_EQ_3780U(...) \, +#define Z_IS_3781_EQ_3781(...) \, +#define Z_IS_3781U_EQ_3781(...) \, +#define Z_IS_3781_EQ_3781U(...) \, +#define Z_IS_3781U_EQ_3781U(...) \, +#define Z_IS_3782_EQ_3782(...) \, +#define Z_IS_3782U_EQ_3782(...) \, +#define Z_IS_3782_EQ_3782U(...) \, +#define Z_IS_3782U_EQ_3782U(...) \, +#define Z_IS_3783_EQ_3783(...) \, +#define Z_IS_3783U_EQ_3783(...) \, +#define Z_IS_3783_EQ_3783U(...) \, +#define Z_IS_3783U_EQ_3783U(...) \, +#define Z_IS_3784_EQ_3784(...) \, +#define Z_IS_3784U_EQ_3784(...) \, +#define Z_IS_3784_EQ_3784U(...) \, +#define Z_IS_3784U_EQ_3784U(...) \, +#define Z_IS_3785_EQ_3785(...) \, +#define Z_IS_3785U_EQ_3785(...) \, +#define Z_IS_3785_EQ_3785U(...) \, +#define Z_IS_3785U_EQ_3785U(...) \, +#define Z_IS_3786_EQ_3786(...) \, +#define Z_IS_3786U_EQ_3786(...) \, +#define Z_IS_3786_EQ_3786U(...) \, +#define Z_IS_3786U_EQ_3786U(...) \, +#define Z_IS_3787_EQ_3787(...) \, +#define Z_IS_3787U_EQ_3787(...) \, +#define Z_IS_3787_EQ_3787U(...) \, +#define Z_IS_3787U_EQ_3787U(...) \, +#define Z_IS_3788_EQ_3788(...) \, +#define Z_IS_3788U_EQ_3788(...) \, +#define Z_IS_3788_EQ_3788U(...) \, +#define Z_IS_3788U_EQ_3788U(...) \, +#define Z_IS_3789_EQ_3789(...) \, +#define Z_IS_3789U_EQ_3789(...) \, +#define Z_IS_3789_EQ_3789U(...) \, +#define Z_IS_3789U_EQ_3789U(...) \, +#define Z_IS_3790_EQ_3790(...) \, +#define Z_IS_3790U_EQ_3790(...) \, +#define Z_IS_3790_EQ_3790U(...) \, +#define Z_IS_3790U_EQ_3790U(...) \, +#define Z_IS_3791_EQ_3791(...) \, +#define Z_IS_3791U_EQ_3791(...) \, +#define Z_IS_3791_EQ_3791U(...) \, +#define Z_IS_3791U_EQ_3791U(...) \, +#define Z_IS_3792_EQ_3792(...) \, +#define Z_IS_3792U_EQ_3792(...) \, +#define Z_IS_3792_EQ_3792U(...) \, +#define Z_IS_3792U_EQ_3792U(...) \, +#define Z_IS_3793_EQ_3793(...) \, +#define Z_IS_3793U_EQ_3793(...) \, +#define Z_IS_3793_EQ_3793U(...) \, +#define Z_IS_3793U_EQ_3793U(...) \, +#define Z_IS_3794_EQ_3794(...) \, +#define Z_IS_3794U_EQ_3794(...) \, +#define Z_IS_3794_EQ_3794U(...) \, +#define Z_IS_3794U_EQ_3794U(...) \, +#define Z_IS_3795_EQ_3795(...) \, +#define Z_IS_3795U_EQ_3795(...) \, +#define Z_IS_3795_EQ_3795U(...) \, +#define Z_IS_3795U_EQ_3795U(...) \, +#define Z_IS_3796_EQ_3796(...) \, +#define Z_IS_3796U_EQ_3796(...) \, +#define Z_IS_3796_EQ_3796U(...) \, +#define Z_IS_3796U_EQ_3796U(...) \, +#define Z_IS_3797_EQ_3797(...) \, +#define Z_IS_3797U_EQ_3797(...) \, +#define Z_IS_3797_EQ_3797U(...) \, +#define Z_IS_3797U_EQ_3797U(...) \, +#define Z_IS_3798_EQ_3798(...) \, +#define Z_IS_3798U_EQ_3798(...) \, +#define Z_IS_3798_EQ_3798U(...) \, +#define Z_IS_3798U_EQ_3798U(...) \, +#define Z_IS_3799_EQ_3799(...) \, +#define Z_IS_3799U_EQ_3799(...) \, +#define Z_IS_3799_EQ_3799U(...) \, +#define Z_IS_3799U_EQ_3799U(...) \, +#define Z_IS_3800_EQ_3800(...) \, +#define Z_IS_3800U_EQ_3800(...) \, +#define Z_IS_3800_EQ_3800U(...) \, +#define Z_IS_3800U_EQ_3800U(...) \, +#define Z_IS_3801_EQ_3801(...) \, +#define Z_IS_3801U_EQ_3801(...) \, +#define Z_IS_3801_EQ_3801U(...) \, +#define Z_IS_3801U_EQ_3801U(...) \, +#define Z_IS_3802_EQ_3802(...) \, +#define Z_IS_3802U_EQ_3802(...) \, +#define Z_IS_3802_EQ_3802U(...) \, +#define Z_IS_3802U_EQ_3802U(...) \, +#define Z_IS_3803_EQ_3803(...) \, +#define Z_IS_3803U_EQ_3803(...) \, +#define Z_IS_3803_EQ_3803U(...) \, +#define Z_IS_3803U_EQ_3803U(...) \, +#define Z_IS_3804_EQ_3804(...) \, +#define Z_IS_3804U_EQ_3804(...) \, +#define Z_IS_3804_EQ_3804U(...) \, +#define Z_IS_3804U_EQ_3804U(...) \, +#define Z_IS_3805_EQ_3805(...) \, +#define Z_IS_3805U_EQ_3805(...) \, +#define Z_IS_3805_EQ_3805U(...) \, +#define Z_IS_3805U_EQ_3805U(...) \, +#define Z_IS_3806_EQ_3806(...) \, +#define Z_IS_3806U_EQ_3806(...) \, +#define Z_IS_3806_EQ_3806U(...) \, +#define Z_IS_3806U_EQ_3806U(...) \, +#define Z_IS_3807_EQ_3807(...) \, +#define Z_IS_3807U_EQ_3807(...) \, +#define Z_IS_3807_EQ_3807U(...) \, +#define Z_IS_3807U_EQ_3807U(...) \, +#define Z_IS_3808_EQ_3808(...) \, +#define Z_IS_3808U_EQ_3808(...) \, +#define Z_IS_3808_EQ_3808U(...) \, +#define Z_IS_3808U_EQ_3808U(...) \, +#define Z_IS_3809_EQ_3809(...) \, +#define Z_IS_3809U_EQ_3809(...) \, +#define Z_IS_3809_EQ_3809U(...) \, +#define Z_IS_3809U_EQ_3809U(...) \, +#define Z_IS_3810_EQ_3810(...) \, +#define Z_IS_3810U_EQ_3810(...) \, +#define Z_IS_3810_EQ_3810U(...) \, +#define Z_IS_3810U_EQ_3810U(...) \, +#define Z_IS_3811_EQ_3811(...) \, +#define Z_IS_3811U_EQ_3811(...) \, +#define Z_IS_3811_EQ_3811U(...) \, +#define Z_IS_3811U_EQ_3811U(...) \, +#define Z_IS_3812_EQ_3812(...) \, +#define Z_IS_3812U_EQ_3812(...) \, +#define Z_IS_3812_EQ_3812U(...) \, +#define Z_IS_3812U_EQ_3812U(...) \, +#define Z_IS_3813_EQ_3813(...) \, +#define Z_IS_3813U_EQ_3813(...) \, +#define Z_IS_3813_EQ_3813U(...) \, +#define Z_IS_3813U_EQ_3813U(...) \, +#define Z_IS_3814_EQ_3814(...) \, +#define Z_IS_3814U_EQ_3814(...) \, +#define Z_IS_3814_EQ_3814U(...) \, +#define Z_IS_3814U_EQ_3814U(...) \, +#define Z_IS_3815_EQ_3815(...) \, +#define Z_IS_3815U_EQ_3815(...) \, +#define Z_IS_3815_EQ_3815U(...) \, +#define Z_IS_3815U_EQ_3815U(...) \, +#define Z_IS_3816_EQ_3816(...) \, +#define Z_IS_3816U_EQ_3816(...) \, +#define Z_IS_3816_EQ_3816U(...) \, +#define Z_IS_3816U_EQ_3816U(...) \, +#define Z_IS_3817_EQ_3817(...) \, +#define Z_IS_3817U_EQ_3817(...) \, +#define Z_IS_3817_EQ_3817U(...) \, +#define Z_IS_3817U_EQ_3817U(...) \, +#define Z_IS_3818_EQ_3818(...) \, +#define Z_IS_3818U_EQ_3818(...) \, +#define Z_IS_3818_EQ_3818U(...) \, +#define Z_IS_3818U_EQ_3818U(...) \, +#define Z_IS_3819_EQ_3819(...) \, +#define Z_IS_3819U_EQ_3819(...) \, +#define Z_IS_3819_EQ_3819U(...) \, +#define Z_IS_3819U_EQ_3819U(...) \, +#define Z_IS_3820_EQ_3820(...) \, +#define Z_IS_3820U_EQ_3820(...) \, +#define Z_IS_3820_EQ_3820U(...) \, +#define Z_IS_3820U_EQ_3820U(...) \, +#define Z_IS_3821_EQ_3821(...) \, +#define Z_IS_3821U_EQ_3821(...) \, +#define Z_IS_3821_EQ_3821U(...) \, +#define Z_IS_3821U_EQ_3821U(...) \, +#define Z_IS_3822_EQ_3822(...) \, +#define Z_IS_3822U_EQ_3822(...) \, +#define Z_IS_3822_EQ_3822U(...) \, +#define Z_IS_3822U_EQ_3822U(...) \, +#define Z_IS_3823_EQ_3823(...) \, +#define Z_IS_3823U_EQ_3823(...) \, +#define Z_IS_3823_EQ_3823U(...) \, +#define Z_IS_3823U_EQ_3823U(...) \, +#define Z_IS_3824_EQ_3824(...) \, +#define Z_IS_3824U_EQ_3824(...) \, +#define Z_IS_3824_EQ_3824U(...) \, +#define Z_IS_3824U_EQ_3824U(...) \, +#define Z_IS_3825_EQ_3825(...) \, +#define Z_IS_3825U_EQ_3825(...) \, +#define Z_IS_3825_EQ_3825U(...) \, +#define Z_IS_3825U_EQ_3825U(...) \, +#define Z_IS_3826_EQ_3826(...) \, +#define Z_IS_3826U_EQ_3826(...) \, +#define Z_IS_3826_EQ_3826U(...) \, +#define Z_IS_3826U_EQ_3826U(...) \, +#define Z_IS_3827_EQ_3827(...) \, +#define Z_IS_3827U_EQ_3827(...) \, +#define Z_IS_3827_EQ_3827U(...) \, +#define Z_IS_3827U_EQ_3827U(...) \, +#define Z_IS_3828_EQ_3828(...) \, +#define Z_IS_3828U_EQ_3828(...) \, +#define Z_IS_3828_EQ_3828U(...) \, +#define Z_IS_3828U_EQ_3828U(...) \, +#define Z_IS_3829_EQ_3829(...) \, +#define Z_IS_3829U_EQ_3829(...) \, +#define Z_IS_3829_EQ_3829U(...) \, +#define Z_IS_3829U_EQ_3829U(...) \, +#define Z_IS_3830_EQ_3830(...) \, +#define Z_IS_3830U_EQ_3830(...) \, +#define Z_IS_3830_EQ_3830U(...) \, +#define Z_IS_3830U_EQ_3830U(...) \, +#define Z_IS_3831_EQ_3831(...) \, +#define Z_IS_3831U_EQ_3831(...) \, +#define Z_IS_3831_EQ_3831U(...) \, +#define Z_IS_3831U_EQ_3831U(...) \, +#define Z_IS_3832_EQ_3832(...) \, +#define Z_IS_3832U_EQ_3832(...) \, +#define Z_IS_3832_EQ_3832U(...) \, +#define Z_IS_3832U_EQ_3832U(...) \, +#define Z_IS_3833_EQ_3833(...) \, +#define Z_IS_3833U_EQ_3833(...) \, +#define Z_IS_3833_EQ_3833U(...) \, +#define Z_IS_3833U_EQ_3833U(...) \, +#define Z_IS_3834_EQ_3834(...) \, +#define Z_IS_3834U_EQ_3834(...) \, +#define Z_IS_3834_EQ_3834U(...) \, +#define Z_IS_3834U_EQ_3834U(...) \, +#define Z_IS_3835_EQ_3835(...) \, +#define Z_IS_3835U_EQ_3835(...) \, +#define Z_IS_3835_EQ_3835U(...) \, +#define Z_IS_3835U_EQ_3835U(...) \, +#define Z_IS_3836_EQ_3836(...) \, +#define Z_IS_3836U_EQ_3836(...) \, +#define Z_IS_3836_EQ_3836U(...) \, +#define Z_IS_3836U_EQ_3836U(...) \, +#define Z_IS_3837_EQ_3837(...) \, +#define Z_IS_3837U_EQ_3837(...) \, +#define Z_IS_3837_EQ_3837U(...) \, +#define Z_IS_3837U_EQ_3837U(...) \, +#define Z_IS_3838_EQ_3838(...) \, +#define Z_IS_3838U_EQ_3838(...) \, +#define Z_IS_3838_EQ_3838U(...) \, +#define Z_IS_3838U_EQ_3838U(...) \, +#define Z_IS_3839_EQ_3839(...) \, +#define Z_IS_3839U_EQ_3839(...) \, +#define Z_IS_3839_EQ_3839U(...) \, +#define Z_IS_3839U_EQ_3839U(...) \, +#define Z_IS_3840_EQ_3840(...) \, +#define Z_IS_3840U_EQ_3840(...) \, +#define Z_IS_3840_EQ_3840U(...) \, +#define Z_IS_3840U_EQ_3840U(...) \, +#define Z_IS_3841_EQ_3841(...) \, +#define Z_IS_3841U_EQ_3841(...) \, +#define Z_IS_3841_EQ_3841U(...) \, +#define Z_IS_3841U_EQ_3841U(...) \, +#define Z_IS_3842_EQ_3842(...) \, +#define Z_IS_3842U_EQ_3842(...) \, +#define Z_IS_3842_EQ_3842U(...) \, +#define Z_IS_3842U_EQ_3842U(...) \, +#define Z_IS_3843_EQ_3843(...) \, +#define Z_IS_3843U_EQ_3843(...) \, +#define Z_IS_3843_EQ_3843U(...) \, +#define Z_IS_3843U_EQ_3843U(...) \, +#define Z_IS_3844_EQ_3844(...) \, +#define Z_IS_3844U_EQ_3844(...) \, +#define Z_IS_3844_EQ_3844U(...) \, +#define Z_IS_3844U_EQ_3844U(...) \, +#define Z_IS_3845_EQ_3845(...) \, +#define Z_IS_3845U_EQ_3845(...) \, +#define Z_IS_3845_EQ_3845U(...) \, +#define Z_IS_3845U_EQ_3845U(...) \, +#define Z_IS_3846_EQ_3846(...) \, +#define Z_IS_3846U_EQ_3846(...) \, +#define Z_IS_3846_EQ_3846U(...) \, +#define Z_IS_3846U_EQ_3846U(...) \, +#define Z_IS_3847_EQ_3847(...) \, +#define Z_IS_3847U_EQ_3847(...) \, +#define Z_IS_3847_EQ_3847U(...) \, +#define Z_IS_3847U_EQ_3847U(...) \, +#define Z_IS_3848_EQ_3848(...) \, +#define Z_IS_3848U_EQ_3848(...) \, +#define Z_IS_3848_EQ_3848U(...) \, +#define Z_IS_3848U_EQ_3848U(...) \, +#define Z_IS_3849_EQ_3849(...) \, +#define Z_IS_3849U_EQ_3849(...) \, +#define Z_IS_3849_EQ_3849U(...) \, +#define Z_IS_3849U_EQ_3849U(...) \, +#define Z_IS_3850_EQ_3850(...) \, +#define Z_IS_3850U_EQ_3850(...) \, +#define Z_IS_3850_EQ_3850U(...) \, +#define Z_IS_3850U_EQ_3850U(...) \, +#define Z_IS_3851_EQ_3851(...) \, +#define Z_IS_3851U_EQ_3851(...) \, +#define Z_IS_3851_EQ_3851U(...) \, +#define Z_IS_3851U_EQ_3851U(...) \, +#define Z_IS_3852_EQ_3852(...) \, +#define Z_IS_3852U_EQ_3852(...) \, +#define Z_IS_3852_EQ_3852U(...) \, +#define Z_IS_3852U_EQ_3852U(...) \, +#define Z_IS_3853_EQ_3853(...) \, +#define Z_IS_3853U_EQ_3853(...) \, +#define Z_IS_3853_EQ_3853U(...) \, +#define Z_IS_3853U_EQ_3853U(...) \, +#define Z_IS_3854_EQ_3854(...) \, +#define Z_IS_3854U_EQ_3854(...) \, +#define Z_IS_3854_EQ_3854U(...) \, +#define Z_IS_3854U_EQ_3854U(...) \, +#define Z_IS_3855_EQ_3855(...) \, +#define Z_IS_3855U_EQ_3855(...) \, +#define Z_IS_3855_EQ_3855U(...) \, +#define Z_IS_3855U_EQ_3855U(...) \, +#define Z_IS_3856_EQ_3856(...) \, +#define Z_IS_3856U_EQ_3856(...) \, +#define Z_IS_3856_EQ_3856U(...) \, +#define Z_IS_3856U_EQ_3856U(...) \, +#define Z_IS_3857_EQ_3857(...) \, +#define Z_IS_3857U_EQ_3857(...) \, +#define Z_IS_3857_EQ_3857U(...) \, +#define Z_IS_3857U_EQ_3857U(...) \, +#define Z_IS_3858_EQ_3858(...) \, +#define Z_IS_3858U_EQ_3858(...) \, +#define Z_IS_3858_EQ_3858U(...) \, +#define Z_IS_3858U_EQ_3858U(...) \, +#define Z_IS_3859_EQ_3859(...) \, +#define Z_IS_3859U_EQ_3859(...) \, +#define Z_IS_3859_EQ_3859U(...) \, +#define Z_IS_3859U_EQ_3859U(...) \, +#define Z_IS_3860_EQ_3860(...) \, +#define Z_IS_3860U_EQ_3860(...) \, +#define Z_IS_3860_EQ_3860U(...) \, +#define Z_IS_3860U_EQ_3860U(...) \, +#define Z_IS_3861_EQ_3861(...) \, +#define Z_IS_3861U_EQ_3861(...) \, +#define Z_IS_3861_EQ_3861U(...) \, +#define Z_IS_3861U_EQ_3861U(...) \, +#define Z_IS_3862_EQ_3862(...) \, +#define Z_IS_3862U_EQ_3862(...) \, +#define Z_IS_3862_EQ_3862U(...) \, +#define Z_IS_3862U_EQ_3862U(...) \, +#define Z_IS_3863_EQ_3863(...) \, +#define Z_IS_3863U_EQ_3863(...) \, +#define Z_IS_3863_EQ_3863U(...) \, +#define Z_IS_3863U_EQ_3863U(...) \, +#define Z_IS_3864_EQ_3864(...) \, +#define Z_IS_3864U_EQ_3864(...) \, +#define Z_IS_3864_EQ_3864U(...) \, +#define Z_IS_3864U_EQ_3864U(...) \, +#define Z_IS_3865_EQ_3865(...) \, +#define Z_IS_3865U_EQ_3865(...) \, +#define Z_IS_3865_EQ_3865U(...) \, +#define Z_IS_3865U_EQ_3865U(...) \, +#define Z_IS_3866_EQ_3866(...) \, +#define Z_IS_3866U_EQ_3866(...) \, +#define Z_IS_3866_EQ_3866U(...) \, +#define Z_IS_3866U_EQ_3866U(...) \, +#define Z_IS_3867_EQ_3867(...) \, +#define Z_IS_3867U_EQ_3867(...) \, +#define Z_IS_3867_EQ_3867U(...) \, +#define Z_IS_3867U_EQ_3867U(...) \, +#define Z_IS_3868_EQ_3868(...) \, +#define Z_IS_3868U_EQ_3868(...) \, +#define Z_IS_3868_EQ_3868U(...) \, +#define Z_IS_3868U_EQ_3868U(...) \, +#define Z_IS_3869_EQ_3869(...) \, +#define Z_IS_3869U_EQ_3869(...) \, +#define Z_IS_3869_EQ_3869U(...) \, +#define Z_IS_3869U_EQ_3869U(...) \, +#define Z_IS_3870_EQ_3870(...) \, +#define Z_IS_3870U_EQ_3870(...) \, +#define Z_IS_3870_EQ_3870U(...) \, +#define Z_IS_3870U_EQ_3870U(...) \, +#define Z_IS_3871_EQ_3871(...) \, +#define Z_IS_3871U_EQ_3871(...) \, +#define Z_IS_3871_EQ_3871U(...) \, +#define Z_IS_3871U_EQ_3871U(...) \, +#define Z_IS_3872_EQ_3872(...) \, +#define Z_IS_3872U_EQ_3872(...) \, +#define Z_IS_3872_EQ_3872U(...) \, +#define Z_IS_3872U_EQ_3872U(...) \, +#define Z_IS_3873_EQ_3873(...) \, +#define Z_IS_3873U_EQ_3873(...) \, +#define Z_IS_3873_EQ_3873U(...) \, +#define Z_IS_3873U_EQ_3873U(...) \, +#define Z_IS_3874_EQ_3874(...) \, +#define Z_IS_3874U_EQ_3874(...) \, +#define Z_IS_3874_EQ_3874U(...) \, +#define Z_IS_3874U_EQ_3874U(...) \, +#define Z_IS_3875_EQ_3875(...) \, +#define Z_IS_3875U_EQ_3875(...) \, +#define Z_IS_3875_EQ_3875U(...) \, +#define Z_IS_3875U_EQ_3875U(...) \, +#define Z_IS_3876_EQ_3876(...) \, +#define Z_IS_3876U_EQ_3876(...) \, +#define Z_IS_3876_EQ_3876U(...) \, +#define Z_IS_3876U_EQ_3876U(...) \, +#define Z_IS_3877_EQ_3877(...) \, +#define Z_IS_3877U_EQ_3877(...) \, +#define Z_IS_3877_EQ_3877U(...) \, +#define Z_IS_3877U_EQ_3877U(...) \, +#define Z_IS_3878_EQ_3878(...) \, +#define Z_IS_3878U_EQ_3878(...) \, +#define Z_IS_3878_EQ_3878U(...) \, +#define Z_IS_3878U_EQ_3878U(...) \, +#define Z_IS_3879_EQ_3879(...) \, +#define Z_IS_3879U_EQ_3879(...) \, +#define Z_IS_3879_EQ_3879U(...) \, +#define Z_IS_3879U_EQ_3879U(...) \, +#define Z_IS_3880_EQ_3880(...) \, +#define Z_IS_3880U_EQ_3880(...) \, +#define Z_IS_3880_EQ_3880U(...) \, +#define Z_IS_3880U_EQ_3880U(...) \, +#define Z_IS_3881_EQ_3881(...) \, +#define Z_IS_3881U_EQ_3881(...) \, +#define Z_IS_3881_EQ_3881U(...) \, +#define Z_IS_3881U_EQ_3881U(...) \, +#define Z_IS_3882_EQ_3882(...) \, +#define Z_IS_3882U_EQ_3882(...) \, +#define Z_IS_3882_EQ_3882U(...) \, +#define Z_IS_3882U_EQ_3882U(...) \, +#define Z_IS_3883_EQ_3883(...) \, +#define Z_IS_3883U_EQ_3883(...) \, +#define Z_IS_3883_EQ_3883U(...) \, +#define Z_IS_3883U_EQ_3883U(...) \, +#define Z_IS_3884_EQ_3884(...) \, +#define Z_IS_3884U_EQ_3884(...) \, +#define Z_IS_3884_EQ_3884U(...) \, +#define Z_IS_3884U_EQ_3884U(...) \, +#define Z_IS_3885_EQ_3885(...) \, +#define Z_IS_3885U_EQ_3885(...) \, +#define Z_IS_3885_EQ_3885U(...) \, +#define Z_IS_3885U_EQ_3885U(...) \, +#define Z_IS_3886_EQ_3886(...) \, +#define Z_IS_3886U_EQ_3886(...) \, +#define Z_IS_3886_EQ_3886U(...) \, +#define Z_IS_3886U_EQ_3886U(...) \, +#define Z_IS_3887_EQ_3887(...) \, +#define Z_IS_3887U_EQ_3887(...) \, +#define Z_IS_3887_EQ_3887U(...) \, +#define Z_IS_3887U_EQ_3887U(...) \, +#define Z_IS_3888_EQ_3888(...) \, +#define Z_IS_3888U_EQ_3888(...) \, +#define Z_IS_3888_EQ_3888U(...) \, +#define Z_IS_3888U_EQ_3888U(...) \, +#define Z_IS_3889_EQ_3889(...) \, +#define Z_IS_3889U_EQ_3889(...) \, +#define Z_IS_3889_EQ_3889U(...) \, +#define Z_IS_3889U_EQ_3889U(...) \, +#define Z_IS_3890_EQ_3890(...) \, +#define Z_IS_3890U_EQ_3890(...) \, +#define Z_IS_3890_EQ_3890U(...) \, +#define Z_IS_3890U_EQ_3890U(...) \, +#define Z_IS_3891_EQ_3891(...) \, +#define Z_IS_3891U_EQ_3891(...) \, +#define Z_IS_3891_EQ_3891U(...) \, +#define Z_IS_3891U_EQ_3891U(...) \, +#define Z_IS_3892_EQ_3892(...) \, +#define Z_IS_3892U_EQ_3892(...) \, +#define Z_IS_3892_EQ_3892U(...) \, +#define Z_IS_3892U_EQ_3892U(...) \, +#define Z_IS_3893_EQ_3893(...) \, +#define Z_IS_3893U_EQ_3893(...) \, +#define Z_IS_3893_EQ_3893U(...) \, +#define Z_IS_3893U_EQ_3893U(...) \, +#define Z_IS_3894_EQ_3894(...) \, +#define Z_IS_3894U_EQ_3894(...) \, +#define Z_IS_3894_EQ_3894U(...) \, +#define Z_IS_3894U_EQ_3894U(...) \, +#define Z_IS_3895_EQ_3895(...) \, +#define Z_IS_3895U_EQ_3895(...) \, +#define Z_IS_3895_EQ_3895U(...) \, +#define Z_IS_3895U_EQ_3895U(...) \, +#define Z_IS_3896_EQ_3896(...) \, +#define Z_IS_3896U_EQ_3896(...) \, +#define Z_IS_3896_EQ_3896U(...) \, +#define Z_IS_3896U_EQ_3896U(...) \, +#define Z_IS_3897_EQ_3897(...) \, +#define Z_IS_3897U_EQ_3897(...) \, +#define Z_IS_3897_EQ_3897U(...) \, +#define Z_IS_3897U_EQ_3897U(...) \, +#define Z_IS_3898_EQ_3898(...) \, +#define Z_IS_3898U_EQ_3898(...) \, +#define Z_IS_3898_EQ_3898U(...) \, +#define Z_IS_3898U_EQ_3898U(...) \, +#define Z_IS_3899_EQ_3899(...) \, +#define Z_IS_3899U_EQ_3899(...) \, +#define Z_IS_3899_EQ_3899U(...) \, +#define Z_IS_3899U_EQ_3899U(...) \, +#define Z_IS_3900_EQ_3900(...) \, +#define Z_IS_3900U_EQ_3900(...) \, +#define Z_IS_3900_EQ_3900U(...) \, +#define Z_IS_3900U_EQ_3900U(...) \, +#define Z_IS_3901_EQ_3901(...) \, +#define Z_IS_3901U_EQ_3901(...) \, +#define Z_IS_3901_EQ_3901U(...) \, +#define Z_IS_3901U_EQ_3901U(...) \, +#define Z_IS_3902_EQ_3902(...) \, +#define Z_IS_3902U_EQ_3902(...) \, +#define Z_IS_3902_EQ_3902U(...) \, +#define Z_IS_3902U_EQ_3902U(...) \, +#define Z_IS_3903_EQ_3903(...) \, +#define Z_IS_3903U_EQ_3903(...) \, +#define Z_IS_3903_EQ_3903U(...) \, +#define Z_IS_3903U_EQ_3903U(...) \, +#define Z_IS_3904_EQ_3904(...) \, +#define Z_IS_3904U_EQ_3904(...) \, +#define Z_IS_3904_EQ_3904U(...) \, +#define Z_IS_3904U_EQ_3904U(...) \, +#define Z_IS_3905_EQ_3905(...) \, +#define Z_IS_3905U_EQ_3905(...) \, +#define Z_IS_3905_EQ_3905U(...) \, +#define Z_IS_3905U_EQ_3905U(...) \, +#define Z_IS_3906_EQ_3906(...) \, +#define Z_IS_3906U_EQ_3906(...) \, +#define Z_IS_3906_EQ_3906U(...) \, +#define Z_IS_3906U_EQ_3906U(...) \, +#define Z_IS_3907_EQ_3907(...) \, +#define Z_IS_3907U_EQ_3907(...) \, +#define Z_IS_3907_EQ_3907U(...) \, +#define Z_IS_3907U_EQ_3907U(...) \, +#define Z_IS_3908_EQ_3908(...) \, +#define Z_IS_3908U_EQ_3908(...) \, +#define Z_IS_3908_EQ_3908U(...) \, +#define Z_IS_3908U_EQ_3908U(...) \, +#define Z_IS_3909_EQ_3909(...) \, +#define Z_IS_3909U_EQ_3909(...) \, +#define Z_IS_3909_EQ_3909U(...) \, +#define Z_IS_3909U_EQ_3909U(...) \, +#define Z_IS_3910_EQ_3910(...) \, +#define Z_IS_3910U_EQ_3910(...) \, +#define Z_IS_3910_EQ_3910U(...) \, +#define Z_IS_3910U_EQ_3910U(...) \, +#define Z_IS_3911_EQ_3911(...) \, +#define Z_IS_3911U_EQ_3911(...) \, +#define Z_IS_3911_EQ_3911U(...) \, +#define Z_IS_3911U_EQ_3911U(...) \, +#define Z_IS_3912_EQ_3912(...) \, +#define Z_IS_3912U_EQ_3912(...) \, +#define Z_IS_3912_EQ_3912U(...) \, +#define Z_IS_3912U_EQ_3912U(...) \, +#define Z_IS_3913_EQ_3913(...) \, +#define Z_IS_3913U_EQ_3913(...) \, +#define Z_IS_3913_EQ_3913U(...) \, +#define Z_IS_3913U_EQ_3913U(...) \, +#define Z_IS_3914_EQ_3914(...) \, +#define Z_IS_3914U_EQ_3914(...) \, +#define Z_IS_3914_EQ_3914U(...) \, +#define Z_IS_3914U_EQ_3914U(...) \, +#define Z_IS_3915_EQ_3915(...) \, +#define Z_IS_3915U_EQ_3915(...) \, +#define Z_IS_3915_EQ_3915U(...) \, +#define Z_IS_3915U_EQ_3915U(...) \, +#define Z_IS_3916_EQ_3916(...) \, +#define Z_IS_3916U_EQ_3916(...) \, +#define Z_IS_3916_EQ_3916U(...) \, +#define Z_IS_3916U_EQ_3916U(...) \, +#define Z_IS_3917_EQ_3917(...) \, +#define Z_IS_3917U_EQ_3917(...) \, +#define Z_IS_3917_EQ_3917U(...) \, +#define Z_IS_3917U_EQ_3917U(...) \, +#define Z_IS_3918_EQ_3918(...) \, +#define Z_IS_3918U_EQ_3918(...) \, +#define Z_IS_3918_EQ_3918U(...) \, +#define Z_IS_3918U_EQ_3918U(...) \, +#define Z_IS_3919_EQ_3919(...) \, +#define Z_IS_3919U_EQ_3919(...) \, +#define Z_IS_3919_EQ_3919U(...) \, +#define Z_IS_3919U_EQ_3919U(...) \, +#define Z_IS_3920_EQ_3920(...) \, +#define Z_IS_3920U_EQ_3920(...) \, +#define Z_IS_3920_EQ_3920U(...) \, +#define Z_IS_3920U_EQ_3920U(...) \, +#define Z_IS_3921_EQ_3921(...) \, +#define Z_IS_3921U_EQ_3921(...) \, +#define Z_IS_3921_EQ_3921U(...) \, +#define Z_IS_3921U_EQ_3921U(...) \, +#define Z_IS_3922_EQ_3922(...) \, +#define Z_IS_3922U_EQ_3922(...) \, +#define Z_IS_3922_EQ_3922U(...) \, +#define Z_IS_3922U_EQ_3922U(...) \, +#define Z_IS_3923_EQ_3923(...) \, +#define Z_IS_3923U_EQ_3923(...) \, +#define Z_IS_3923_EQ_3923U(...) \, +#define Z_IS_3923U_EQ_3923U(...) \, +#define Z_IS_3924_EQ_3924(...) \, +#define Z_IS_3924U_EQ_3924(...) \, +#define Z_IS_3924_EQ_3924U(...) \, +#define Z_IS_3924U_EQ_3924U(...) \, +#define Z_IS_3925_EQ_3925(...) \, +#define Z_IS_3925U_EQ_3925(...) \, +#define Z_IS_3925_EQ_3925U(...) \, +#define Z_IS_3925U_EQ_3925U(...) \, +#define Z_IS_3926_EQ_3926(...) \, +#define Z_IS_3926U_EQ_3926(...) \, +#define Z_IS_3926_EQ_3926U(...) \, +#define Z_IS_3926U_EQ_3926U(...) \, +#define Z_IS_3927_EQ_3927(...) \, +#define Z_IS_3927U_EQ_3927(...) \, +#define Z_IS_3927_EQ_3927U(...) \, +#define Z_IS_3927U_EQ_3927U(...) \, +#define Z_IS_3928_EQ_3928(...) \, +#define Z_IS_3928U_EQ_3928(...) \, +#define Z_IS_3928_EQ_3928U(...) \, +#define Z_IS_3928U_EQ_3928U(...) \, +#define Z_IS_3929_EQ_3929(...) \, +#define Z_IS_3929U_EQ_3929(...) \, +#define Z_IS_3929_EQ_3929U(...) \, +#define Z_IS_3929U_EQ_3929U(...) \, +#define Z_IS_3930_EQ_3930(...) \, +#define Z_IS_3930U_EQ_3930(...) \, +#define Z_IS_3930_EQ_3930U(...) \, +#define Z_IS_3930U_EQ_3930U(...) \, +#define Z_IS_3931_EQ_3931(...) \, +#define Z_IS_3931U_EQ_3931(...) \, +#define Z_IS_3931_EQ_3931U(...) \, +#define Z_IS_3931U_EQ_3931U(...) \, +#define Z_IS_3932_EQ_3932(...) \, +#define Z_IS_3932U_EQ_3932(...) \, +#define Z_IS_3932_EQ_3932U(...) \, +#define Z_IS_3932U_EQ_3932U(...) \, +#define Z_IS_3933_EQ_3933(...) \, +#define Z_IS_3933U_EQ_3933(...) \, +#define Z_IS_3933_EQ_3933U(...) \, +#define Z_IS_3933U_EQ_3933U(...) \, +#define Z_IS_3934_EQ_3934(...) \, +#define Z_IS_3934U_EQ_3934(...) \, +#define Z_IS_3934_EQ_3934U(...) \, +#define Z_IS_3934U_EQ_3934U(...) \, +#define Z_IS_3935_EQ_3935(...) \, +#define Z_IS_3935U_EQ_3935(...) \, +#define Z_IS_3935_EQ_3935U(...) \, +#define Z_IS_3935U_EQ_3935U(...) \, +#define Z_IS_3936_EQ_3936(...) \, +#define Z_IS_3936U_EQ_3936(...) \, +#define Z_IS_3936_EQ_3936U(...) \, +#define Z_IS_3936U_EQ_3936U(...) \, +#define Z_IS_3937_EQ_3937(...) \, +#define Z_IS_3937U_EQ_3937(...) \, +#define Z_IS_3937_EQ_3937U(...) \, +#define Z_IS_3937U_EQ_3937U(...) \, +#define Z_IS_3938_EQ_3938(...) \, +#define Z_IS_3938U_EQ_3938(...) \, +#define Z_IS_3938_EQ_3938U(...) \, +#define Z_IS_3938U_EQ_3938U(...) \, +#define Z_IS_3939_EQ_3939(...) \, +#define Z_IS_3939U_EQ_3939(...) \, +#define Z_IS_3939_EQ_3939U(...) \, +#define Z_IS_3939U_EQ_3939U(...) \, +#define Z_IS_3940_EQ_3940(...) \, +#define Z_IS_3940U_EQ_3940(...) \, +#define Z_IS_3940_EQ_3940U(...) \, +#define Z_IS_3940U_EQ_3940U(...) \, +#define Z_IS_3941_EQ_3941(...) \, +#define Z_IS_3941U_EQ_3941(...) \, +#define Z_IS_3941_EQ_3941U(...) \, +#define Z_IS_3941U_EQ_3941U(...) \, +#define Z_IS_3942_EQ_3942(...) \, +#define Z_IS_3942U_EQ_3942(...) \, +#define Z_IS_3942_EQ_3942U(...) \, +#define Z_IS_3942U_EQ_3942U(...) \, +#define Z_IS_3943_EQ_3943(...) \, +#define Z_IS_3943U_EQ_3943(...) \, +#define Z_IS_3943_EQ_3943U(...) \, +#define Z_IS_3943U_EQ_3943U(...) \, +#define Z_IS_3944_EQ_3944(...) \, +#define Z_IS_3944U_EQ_3944(...) \, +#define Z_IS_3944_EQ_3944U(...) \, +#define Z_IS_3944U_EQ_3944U(...) \, +#define Z_IS_3945_EQ_3945(...) \, +#define Z_IS_3945U_EQ_3945(...) \, +#define Z_IS_3945_EQ_3945U(...) \, +#define Z_IS_3945U_EQ_3945U(...) \, +#define Z_IS_3946_EQ_3946(...) \, +#define Z_IS_3946U_EQ_3946(...) \, +#define Z_IS_3946_EQ_3946U(...) \, +#define Z_IS_3946U_EQ_3946U(...) \, +#define Z_IS_3947_EQ_3947(...) \, +#define Z_IS_3947U_EQ_3947(...) \, +#define Z_IS_3947_EQ_3947U(...) \, +#define Z_IS_3947U_EQ_3947U(...) \, +#define Z_IS_3948_EQ_3948(...) \, +#define Z_IS_3948U_EQ_3948(...) \, +#define Z_IS_3948_EQ_3948U(...) \, +#define Z_IS_3948U_EQ_3948U(...) \, +#define Z_IS_3949_EQ_3949(...) \, +#define Z_IS_3949U_EQ_3949(...) \, +#define Z_IS_3949_EQ_3949U(...) \, +#define Z_IS_3949U_EQ_3949U(...) \, +#define Z_IS_3950_EQ_3950(...) \, +#define Z_IS_3950U_EQ_3950(...) \, +#define Z_IS_3950_EQ_3950U(...) \, +#define Z_IS_3950U_EQ_3950U(...) \, +#define Z_IS_3951_EQ_3951(...) \, +#define Z_IS_3951U_EQ_3951(...) \, +#define Z_IS_3951_EQ_3951U(...) \, +#define Z_IS_3951U_EQ_3951U(...) \, +#define Z_IS_3952_EQ_3952(...) \, +#define Z_IS_3952U_EQ_3952(...) \, +#define Z_IS_3952_EQ_3952U(...) \, +#define Z_IS_3952U_EQ_3952U(...) \, +#define Z_IS_3953_EQ_3953(...) \, +#define Z_IS_3953U_EQ_3953(...) \, +#define Z_IS_3953_EQ_3953U(...) \, +#define Z_IS_3953U_EQ_3953U(...) \, +#define Z_IS_3954_EQ_3954(...) \, +#define Z_IS_3954U_EQ_3954(...) \, +#define Z_IS_3954_EQ_3954U(...) \, +#define Z_IS_3954U_EQ_3954U(...) \, +#define Z_IS_3955_EQ_3955(...) \, +#define Z_IS_3955U_EQ_3955(...) \, +#define Z_IS_3955_EQ_3955U(...) \, +#define Z_IS_3955U_EQ_3955U(...) \, +#define Z_IS_3956_EQ_3956(...) \, +#define Z_IS_3956U_EQ_3956(...) \, +#define Z_IS_3956_EQ_3956U(...) \, +#define Z_IS_3956U_EQ_3956U(...) \, +#define Z_IS_3957_EQ_3957(...) \, +#define Z_IS_3957U_EQ_3957(...) \, +#define Z_IS_3957_EQ_3957U(...) \, +#define Z_IS_3957U_EQ_3957U(...) \, +#define Z_IS_3958_EQ_3958(...) \, +#define Z_IS_3958U_EQ_3958(...) \, +#define Z_IS_3958_EQ_3958U(...) \, +#define Z_IS_3958U_EQ_3958U(...) \, +#define Z_IS_3959_EQ_3959(...) \, +#define Z_IS_3959U_EQ_3959(...) \, +#define Z_IS_3959_EQ_3959U(...) \, +#define Z_IS_3959U_EQ_3959U(...) \, +#define Z_IS_3960_EQ_3960(...) \, +#define Z_IS_3960U_EQ_3960(...) \, +#define Z_IS_3960_EQ_3960U(...) \, +#define Z_IS_3960U_EQ_3960U(...) \, +#define Z_IS_3961_EQ_3961(...) \, +#define Z_IS_3961U_EQ_3961(...) \, +#define Z_IS_3961_EQ_3961U(...) \, +#define Z_IS_3961U_EQ_3961U(...) \, +#define Z_IS_3962_EQ_3962(...) \, +#define Z_IS_3962U_EQ_3962(...) \, +#define Z_IS_3962_EQ_3962U(...) \, +#define Z_IS_3962U_EQ_3962U(...) \, +#define Z_IS_3963_EQ_3963(...) \, +#define Z_IS_3963U_EQ_3963(...) \, +#define Z_IS_3963_EQ_3963U(...) \, +#define Z_IS_3963U_EQ_3963U(...) \, +#define Z_IS_3964_EQ_3964(...) \, +#define Z_IS_3964U_EQ_3964(...) \, +#define Z_IS_3964_EQ_3964U(...) \, +#define Z_IS_3964U_EQ_3964U(...) \, +#define Z_IS_3965_EQ_3965(...) \, +#define Z_IS_3965U_EQ_3965(...) \, +#define Z_IS_3965_EQ_3965U(...) \, +#define Z_IS_3965U_EQ_3965U(...) \, +#define Z_IS_3966_EQ_3966(...) \, +#define Z_IS_3966U_EQ_3966(...) \, +#define Z_IS_3966_EQ_3966U(...) \, +#define Z_IS_3966U_EQ_3966U(...) \, +#define Z_IS_3967_EQ_3967(...) \, +#define Z_IS_3967U_EQ_3967(...) \, +#define Z_IS_3967_EQ_3967U(...) \, +#define Z_IS_3967U_EQ_3967U(...) \, +#define Z_IS_3968_EQ_3968(...) \, +#define Z_IS_3968U_EQ_3968(...) \, +#define Z_IS_3968_EQ_3968U(...) \, +#define Z_IS_3968U_EQ_3968U(...) \, +#define Z_IS_3969_EQ_3969(...) \, +#define Z_IS_3969U_EQ_3969(...) \, +#define Z_IS_3969_EQ_3969U(...) \, +#define Z_IS_3969U_EQ_3969U(...) \, +#define Z_IS_3970_EQ_3970(...) \, +#define Z_IS_3970U_EQ_3970(...) \, +#define Z_IS_3970_EQ_3970U(...) \, +#define Z_IS_3970U_EQ_3970U(...) \, +#define Z_IS_3971_EQ_3971(...) \, +#define Z_IS_3971U_EQ_3971(...) \, +#define Z_IS_3971_EQ_3971U(...) \, +#define Z_IS_3971U_EQ_3971U(...) \, +#define Z_IS_3972_EQ_3972(...) \, +#define Z_IS_3972U_EQ_3972(...) \, +#define Z_IS_3972_EQ_3972U(...) \, +#define Z_IS_3972U_EQ_3972U(...) \, +#define Z_IS_3973_EQ_3973(...) \, +#define Z_IS_3973U_EQ_3973(...) \, +#define Z_IS_3973_EQ_3973U(...) \, +#define Z_IS_3973U_EQ_3973U(...) \, +#define Z_IS_3974_EQ_3974(...) \, +#define Z_IS_3974U_EQ_3974(...) \, +#define Z_IS_3974_EQ_3974U(...) \, +#define Z_IS_3974U_EQ_3974U(...) \, +#define Z_IS_3975_EQ_3975(...) \, +#define Z_IS_3975U_EQ_3975(...) \, +#define Z_IS_3975_EQ_3975U(...) \, +#define Z_IS_3975U_EQ_3975U(...) \, +#define Z_IS_3976_EQ_3976(...) \, +#define Z_IS_3976U_EQ_3976(...) \, +#define Z_IS_3976_EQ_3976U(...) \, +#define Z_IS_3976U_EQ_3976U(...) \, +#define Z_IS_3977_EQ_3977(...) \, +#define Z_IS_3977U_EQ_3977(...) \, +#define Z_IS_3977_EQ_3977U(...) \, +#define Z_IS_3977U_EQ_3977U(...) \, +#define Z_IS_3978_EQ_3978(...) \, +#define Z_IS_3978U_EQ_3978(...) \, +#define Z_IS_3978_EQ_3978U(...) \, +#define Z_IS_3978U_EQ_3978U(...) \, +#define Z_IS_3979_EQ_3979(...) \, +#define Z_IS_3979U_EQ_3979(...) \, +#define Z_IS_3979_EQ_3979U(...) \, +#define Z_IS_3979U_EQ_3979U(...) \, +#define Z_IS_3980_EQ_3980(...) \, +#define Z_IS_3980U_EQ_3980(...) \, +#define Z_IS_3980_EQ_3980U(...) \, +#define Z_IS_3980U_EQ_3980U(...) \, +#define Z_IS_3981_EQ_3981(...) \, +#define Z_IS_3981U_EQ_3981(...) \, +#define Z_IS_3981_EQ_3981U(...) \, +#define Z_IS_3981U_EQ_3981U(...) \, +#define Z_IS_3982_EQ_3982(...) \, +#define Z_IS_3982U_EQ_3982(...) \, +#define Z_IS_3982_EQ_3982U(...) \, +#define Z_IS_3982U_EQ_3982U(...) \, +#define Z_IS_3983_EQ_3983(...) \, +#define Z_IS_3983U_EQ_3983(...) \, +#define Z_IS_3983_EQ_3983U(...) \, +#define Z_IS_3983U_EQ_3983U(...) \, +#define Z_IS_3984_EQ_3984(...) \, +#define Z_IS_3984U_EQ_3984(...) \, +#define Z_IS_3984_EQ_3984U(...) \, +#define Z_IS_3984U_EQ_3984U(...) \, +#define Z_IS_3985_EQ_3985(...) \, +#define Z_IS_3985U_EQ_3985(...) \, +#define Z_IS_3985_EQ_3985U(...) \, +#define Z_IS_3985U_EQ_3985U(...) \, +#define Z_IS_3986_EQ_3986(...) \, +#define Z_IS_3986U_EQ_3986(...) \, +#define Z_IS_3986_EQ_3986U(...) \, +#define Z_IS_3986U_EQ_3986U(...) \, +#define Z_IS_3987_EQ_3987(...) \, +#define Z_IS_3987U_EQ_3987(...) \, +#define Z_IS_3987_EQ_3987U(...) \, +#define Z_IS_3987U_EQ_3987U(...) \, +#define Z_IS_3988_EQ_3988(...) \, +#define Z_IS_3988U_EQ_3988(...) \, +#define Z_IS_3988_EQ_3988U(...) \, +#define Z_IS_3988U_EQ_3988U(...) \, +#define Z_IS_3989_EQ_3989(...) \, +#define Z_IS_3989U_EQ_3989(...) \, +#define Z_IS_3989_EQ_3989U(...) \, +#define Z_IS_3989U_EQ_3989U(...) \, +#define Z_IS_3990_EQ_3990(...) \, +#define Z_IS_3990U_EQ_3990(...) \, +#define Z_IS_3990_EQ_3990U(...) \, +#define Z_IS_3990U_EQ_3990U(...) \, +#define Z_IS_3991_EQ_3991(...) \, +#define Z_IS_3991U_EQ_3991(...) \, +#define Z_IS_3991_EQ_3991U(...) \, +#define Z_IS_3991U_EQ_3991U(...) \, +#define Z_IS_3992_EQ_3992(...) \, +#define Z_IS_3992U_EQ_3992(...) \, +#define Z_IS_3992_EQ_3992U(...) \, +#define Z_IS_3992U_EQ_3992U(...) \, +#define Z_IS_3993_EQ_3993(...) \, +#define Z_IS_3993U_EQ_3993(...) \, +#define Z_IS_3993_EQ_3993U(...) \, +#define Z_IS_3993U_EQ_3993U(...) \, +#define Z_IS_3994_EQ_3994(...) \, +#define Z_IS_3994U_EQ_3994(...) \, +#define Z_IS_3994_EQ_3994U(...) \, +#define Z_IS_3994U_EQ_3994U(...) \, +#define Z_IS_3995_EQ_3995(...) \, +#define Z_IS_3995U_EQ_3995(...) \, +#define Z_IS_3995_EQ_3995U(...) \, +#define Z_IS_3995U_EQ_3995U(...) \, +#define Z_IS_3996_EQ_3996(...) \, +#define Z_IS_3996U_EQ_3996(...) \, +#define Z_IS_3996_EQ_3996U(...) \, +#define Z_IS_3996U_EQ_3996U(...) \, +#define Z_IS_3997_EQ_3997(...) \, +#define Z_IS_3997U_EQ_3997(...) \, +#define Z_IS_3997_EQ_3997U(...) \, +#define Z_IS_3997U_EQ_3997U(...) \, +#define Z_IS_3998_EQ_3998(...) \, +#define Z_IS_3998U_EQ_3998(...) \, +#define Z_IS_3998_EQ_3998U(...) \, +#define Z_IS_3998U_EQ_3998U(...) \, +#define Z_IS_3999_EQ_3999(...) \, +#define Z_IS_3999U_EQ_3999(...) \, +#define Z_IS_3999_EQ_3999U(...) \, +#define Z_IS_3999U_EQ_3999U(...) \, +#define Z_IS_4000_EQ_4000(...) \, +#define Z_IS_4000U_EQ_4000(...) \, +#define Z_IS_4000_EQ_4000U(...) \, +#define Z_IS_4000U_EQ_4000U(...) \, +#define Z_IS_4001_EQ_4001(...) \, +#define Z_IS_4001U_EQ_4001(...) \, +#define Z_IS_4001_EQ_4001U(...) \, +#define Z_IS_4001U_EQ_4001U(...) \, +#define Z_IS_4002_EQ_4002(...) \, +#define Z_IS_4002U_EQ_4002(...) \, +#define Z_IS_4002_EQ_4002U(...) \, +#define Z_IS_4002U_EQ_4002U(...) \, +#define Z_IS_4003_EQ_4003(...) \, +#define Z_IS_4003U_EQ_4003(...) \, +#define Z_IS_4003_EQ_4003U(...) \, +#define Z_IS_4003U_EQ_4003U(...) \, +#define Z_IS_4004_EQ_4004(...) \, +#define Z_IS_4004U_EQ_4004(...) \, +#define Z_IS_4004_EQ_4004U(...) \, +#define Z_IS_4004U_EQ_4004U(...) \, +#define Z_IS_4005_EQ_4005(...) \, +#define Z_IS_4005U_EQ_4005(...) \, +#define Z_IS_4005_EQ_4005U(...) \, +#define Z_IS_4005U_EQ_4005U(...) \, +#define Z_IS_4006_EQ_4006(...) \, +#define Z_IS_4006U_EQ_4006(...) \, +#define Z_IS_4006_EQ_4006U(...) \, +#define Z_IS_4006U_EQ_4006U(...) \, +#define Z_IS_4007_EQ_4007(...) \, +#define Z_IS_4007U_EQ_4007(...) \, +#define Z_IS_4007_EQ_4007U(...) \, +#define Z_IS_4007U_EQ_4007U(...) \, +#define Z_IS_4008_EQ_4008(...) \, +#define Z_IS_4008U_EQ_4008(...) \, +#define Z_IS_4008_EQ_4008U(...) \, +#define Z_IS_4008U_EQ_4008U(...) \, +#define Z_IS_4009_EQ_4009(...) \, +#define Z_IS_4009U_EQ_4009(...) \, +#define Z_IS_4009_EQ_4009U(...) \, +#define Z_IS_4009U_EQ_4009U(...) \, +#define Z_IS_4010_EQ_4010(...) \, +#define Z_IS_4010U_EQ_4010(...) \, +#define Z_IS_4010_EQ_4010U(...) \, +#define Z_IS_4010U_EQ_4010U(...) \, +#define Z_IS_4011_EQ_4011(...) \, +#define Z_IS_4011U_EQ_4011(...) \, +#define Z_IS_4011_EQ_4011U(...) \, +#define Z_IS_4011U_EQ_4011U(...) \, +#define Z_IS_4012_EQ_4012(...) \, +#define Z_IS_4012U_EQ_4012(...) \, +#define Z_IS_4012_EQ_4012U(...) \, +#define Z_IS_4012U_EQ_4012U(...) \, +#define Z_IS_4013_EQ_4013(...) \, +#define Z_IS_4013U_EQ_4013(...) \, +#define Z_IS_4013_EQ_4013U(...) \, +#define Z_IS_4013U_EQ_4013U(...) \, +#define Z_IS_4014_EQ_4014(...) \, +#define Z_IS_4014U_EQ_4014(...) \, +#define Z_IS_4014_EQ_4014U(...) \, +#define Z_IS_4014U_EQ_4014U(...) \, +#define Z_IS_4015_EQ_4015(...) \, +#define Z_IS_4015U_EQ_4015(...) \, +#define Z_IS_4015_EQ_4015U(...) \, +#define Z_IS_4015U_EQ_4015U(...) \, +#define Z_IS_4016_EQ_4016(...) \, +#define Z_IS_4016U_EQ_4016(...) \, +#define Z_IS_4016_EQ_4016U(...) \, +#define Z_IS_4016U_EQ_4016U(...) \, +#define Z_IS_4017_EQ_4017(...) \, +#define Z_IS_4017U_EQ_4017(...) \, +#define Z_IS_4017_EQ_4017U(...) \, +#define Z_IS_4017U_EQ_4017U(...) \, +#define Z_IS_4018_EQ_4018(...) \, +#define Z_IS_4018U_EQ_4018(...) \, +#define Z_IS_4018_EQ_4018U(...) \, +#define Z_IS_4018U_EQ_4018U(...) \, +#define Z_IS_4019_EQ_4019(...) \, +#define Z_IS_4019U_EQ_4019(...) \, +#define Z_IS_4019_EQ_4019U(...) \, +#define Z_IS_4019U_EQ_4019U(...) \, +#define Z_IS_4020_EQ_4020(...) \, +#define Z_IS_4020U_EQ_4020(...) \, +#define Z_IS_4020_EQ_4020U(...) \, +#define Z_IS_4020U_EQ_4020U(...) \, +#define Z_IS_4021_EQ_4021(...) \, +#define Z_IS_4021U_EQ_4021(...) \, +#define Z_IS_4021_EQ_4021U(...) \, +#define Z_IS_4021U_EQ_4021U(...) \, +#define Z_IS_4022_EQ_4022(...) \, +#define Z_IS_4022U_EQ_4022(...) \, +#define Z_IS_4022_EQ_4022U(...) \, +#define Z_IS_4022U_EQ_4022U(...) \, +#define Z_IS_4023_EQ_4023(...) \, +#define Z_IS_4023U_EQ_4023(...) \, +#define Z_IS_4023_EQ_4023U(...) \, +#define Z_IS_4023U_EQ_4023U(...) \, +#define Z_IS_4024_EQ_4024(...) \, +#define Z_IS_4024U_EQ_4024(...) \, +#define Z_IS_4024_EQ_4024U(...) \, +#define Z_IS_4024U_EQ_4024U(...) \, +#define Z_IS_4025_EQ_4025(...) \, +#define Z_IS_4025U_EQ_4025(...) \, +#define Z_IS_4025_EQ_4025U(...) \, +#define Z_IS_4025U_EQ_4025U(...) \, +#define Z_IS_4026_EQ_4026(...) \, +#define Z_IS_4026U_EQ_4026(...) \, +#define Z_IS_4026_EQ_4026U(...) \, +#define Z_IS_4026U_EQ_4026U(...) \, +#define Z_IS_4027_EQ_4027(...) \, +#define Z_IS_4027U_EQ_4027(...) \, +#define Z_IS_4027_EQ_4027U(...) \, +#define Z_IS_4027U_EQ_4027U(...) \, +#define Z_IS_4028_EQ_4028(...) \, +#define Z_IS_4028U_EQ_4028(...) \, +#define Z_IS_4028_EQ_4028U(...) \, +#define Z_IS_4028U_EQ_4028U(...) \, +#define Z_IS_4029_EQ_4029(...) \, +#define Z_IS_4029U_EQ_4029(...) \, +#define Z_IS_4029_EQ_4029U(...) \, +#define Z_IS_4029U_EQ_4029U(...) \, +#define Z_IS_4030_EQ_4030(...) \, +#define Z_IS_4030U_EQ_4030(...) \, +#define Z_IS_4030_EQ_4030U(...) \, +#define Z_IS_4030U_EQ_4030U(...) \, +#define Z_IS_4031_EQ_4031(...) \, +#define Z_IS_4031U_EQ_4031(...) \, +#define Z_IS_4031_EQ_4031U(...) \, +#define Z_IS_4031U_EQ_4031U(...) \, +#define Z_IS_4032_EQ_4032(...) \, +#define Z_IS_4032U_EQ_4032(...) \, +#define Z_IS_4032_EQ_4032U(...) \, +#define Z_IS_4032U_EQ_4032U(...) \, +#define Z_IS_4033_EQ_4033(...) \, +#define Z_IS_4033U_EQ_4033(...) \, +#define Z_IS_4033_EQ_4033U(...) \, +#define Z_IS_4033U_EQ_4033U(...) \, +#define Z_IS_4034_EQ_4034(...) \, +#define Z_IS_4034U_EQ_4034(...) \, +#define Z_IS_4034_EQ_4034U(...) \, +#define Z_IS_4034U_EQ_4034U(...) \, +#define Z_IS_4035_EQ_4035(...) \, +#define Z_IS_4035U_EQ_4035(...) \, +#define Z_IS_4035_EQ_4035U(...) \, +#define Z_IS_4035U_EQ_4035U(...) \, +#define Z_IS_4036_EQ_4036(...) \, +#define Z_IS_4036U_EQ_4036(...) \, +#define Z_IS_4036_EQ_4036U(...) \, +#define Z_IS_4036U_EQ_4036U(...) \, +#define Z_IS_4037_EQ_4037(...) \, +#define Z_IS_4037U_EQ_4037(...) \, +#define Z_IS_4037_EQ_4037U(...) \, +#define Z_IS_4037U_EQ_4037U(...) \, +#define Z_IS_4038_EQ_4038(...) \, +#define Z_IS_4038U_EQ_4038(...) \, +#define Z_IS_4038_EQ_4038U(...) \, +#define Z_IS_4038U_EQ_4038U(...) \, +#define Z_IS_4039_EQ_4039(...) \, +#define Z_IS_4039U_EQ_4039(...) \, +#define Z_IS_4039_EQ_4039U(...) \, +#define Z_IS_4039U_EQ_4039U(...) \, +#define Z_IS_4040_EQ_4040(...) \, +#define Z_IS_4040U_EQ_4040(...) \, +#define Z_IS_4040_EQ_4040U(...) \, +#define Z_IS_4040U_EQ_4040U(...) \, +#define Z_IS_4041_EQ_4041(...) \, +#define Z_IS_4041U_EQ_4041(...) \, +#define Z_IS_4041_EQ_4041U(...) \, +#define Z_IS_4041U_EQ_4041U(...) \, +#define Z_IS_4042_EQ_4042(...) \, +#define Z_IS_4042U_EQ_4042(...) \, +#define Z_IS_4042_EQ_4042U(...) \, +#define Z_IS_4042U_EQ_4042U(...) \, +#define Z_IS_4043_EQ_4043(...) \, +#define Z_IS_4043U_EQ_4043(...) \, +#define Z_IS_4043_EQ_4043U(...) \, +#define Z_IS_4043U_EQ_4043U(...) \, +#define Z_IS_4044_EQ_4044(...) \, +#define Z_IS_4044U_EQ_4044(...) \, +#define Z_IS_4044_EQ_4044U(...) \, +#define Z_IS_4044U_EQ_4044U(...) \, +#define Z_IS_4045_EQ_4045(...) \, +#define Z_IS_4045U_EQ_4045(...) \, +#define Z_IS_4045_EQ_4045U(...) \, +#define Z_IS_4045U_EQ_4045U(...) \, +#define Z_IS_4046_EQ_4046(...) \, +#define Z_IS_4046U_EQ_4046(...) \, +#define Z_IS_4046_EQ_4046U(...) \, +#define Z_IS_4046U_EQ_4046U(...) \, +#define Z_IS_4047_EQ_4047(...) \, +#define Z_IS_4047U_EQ_4047(...) \, +#define Z_IS_4047_EQ_4047U(...) \, +#define Z_IS_4047U_EQ_4047U(...) \, +#define Z_IS_4048_EQ_4048(...) \, +#define Z_IS_4048U_EQ_4048(...) \, +#define Z_IS_4048_EQ_4048U(...) \, +#define Z_IS_4048U_EQ_4048U(...) \, +#define Z_IS_4049_EQ_4049(...) \, +#define Z_IS_4049U_EQ_4049(...) \, +#define Z_IS_4049_EQ_4049U(...) \, +#define Z_IS_4049U_EQ_4049U(...) \, +#define Z_IS_4050_EQ_4050(...) \, +#define Z_IS_4050U_EQ_4050(...) \, +#define Z_IS_4050_EQ_4050U(...) \, +#define Z_IS_4050U_EQ_4050U(...) \, +#define Z_IS_4051_EQ_4051(...) \, +#define Z_IS_4051U_EQ_4051(...) \, +#define Z_IS_4051_EQ_4051U(...) \, +#define Z_IS_4051U_EQ_4051U(...) \, +#define Z_IS_4052_EQ_4052(...) \, +#define Z_IS_4052U_EQ_4052(...) \, +#define Z_IS_4052_EQ_4052U(...) \, +#define Z_IS_4052U_EQ_4052U(...) \, +#define Z_IS_4053_EQ_4053(...) \, +#define Z_IS_4053U_EQ_4053(...) \, +#define Z_IS_4053_EQ_4053U(...) \, +#define Z_IS_4053U_EQ_4053U(...) \, +#define Z_IS_4054_EQ_4054(...) \, +#define Z_IS_4054U_EQ_4054(...) \, +#define Z_IS_4054_EQ_4054U(...) \, +#define Z_IS_4054U_EQ_4054U(...) \, +#define Z_IS_4055_EQ_4055(...) \, +#define Z_IS_4055U_EQ_4055(...) \, +#define Z_IS_4055_EQ_4055U(...) \, +#define Z_IS_4055U_EQ_4055U(...) \, +#define Z_IS_4056_EQ_4056(...) \, +#define Z_IS_4056U_EQ_4056(...) \, +#define Z_IS_4056_EQ_4056U(...) \, +#define Z_IS_4056U_EQ_4056U(...) \, +#define Z_IS_4057_EQ_4057(...) \, +#define Z_IS_4057U_EQ_4057(...) \, +#define Z_IS_4057_EQ_4057U(...) \, +#define Z_IS_4057U_EQ_4057U(...) \, +#define Z_IS_4058_EQ_4058(...) \, +#define Z_IS_4058U_EQ_4058(...) \, +#define Z_IS_4058_EQ_4058U(...) \, +#define Z_IS_4058U_EQ_4058U(...) \, +#define Z_IS_4059_EQ_4059(...) \, +#define Z_IS_4059U_EQ_4059(...) \, +#define Z_IS_4059_EQ_4059U(...) \, +#define Z_IS_4059U_EQ_4059U(...) \, +#define Z_IS_4060_EQ_4060(...) \, +#define Z_IS_4060U_EQ_4060(...) \, +#define Z_IS_4060_EQ_4060U(...) \, +#define Z_IS_4060U_EQ_4060U(...) \, +#define Z_IS_4061_EQ_4061(...) \, +#define Z_IS_4061U_EQ_4061(...) \, +#define Z_IS_4061_EQ_4061U(...) \, +#define Z_IS_4061U_EQ_4061U(...) \, +#define Z_IS_4062_EQ_4062(...) \, +#define Z_IS_4062U_EQ_4062(...) \, +#define Z_IS_4062_EQ_4062U(...) \, +#define Z_IS_4062U_EQ_4062U(...) \, +#define Z_IS_4063_EQ_4063(...) \, +#define Z_IS_4063U_EQ_4063(...) \, +#define Z_IS_4063_EQ_4063U(...) \, +#define Z_IS_4063U_EQ_4063U(...) \, +#define Z_IS_4064_EQ_4064(...) \, +#define Z_IS_4064U_EQ_4064(...) \, +#define Z_IS_4064_EQ_4064U(...) \, +#define Z_IS_4064U_EQ_4064U(...) \, +#define Z_IS_4065_EQ_4065(...) \, +#define Z_IS_4065U_EQ_4065(...) \, +#define Z_IS_4065_EQ_4065U(...) \, +#define Z_IS_4065U_EQ_4065U(...) \, +#define Z_IS_4066_EQ_4066(...) \, +#define Z_IS_4066U_EQ_4066(...) \, +#define Z_IS_4066_EQ_4066U(...) \, +#define Z_IS_4066U_EQ_4066U(...) \, +#define Z_IS_4067_EQ_4067(...) \, +#define Z_IS_4067U_EQ_4067(...) \, +#define Z_IS_4067_EQ_4067U(...) \, +#define Z_IS_4067U_EQ_4067U(...) \, +#define Z_IS_4068_EQ_4068(...) \, +#define Z_IS_4068U_EQ_4068(...) \, +#define Z_IS_4068_EQ_4068U(...) \, +#define Z_IS_4068U_EQ_4068U(...) \, +#define Z_IS_4069_EQ_4069(...) \, +#define Z_IS_4069U_EQ_4069(...) \, +#define Z_IS_4069_EQ_4069U(...) \, +#define Z_IS_4069U_EQ_4069U(...) \, +#define Z_IS_4070_EQ_4070(...) \, +#define Z_IS_4070U_EQ_4070(...) \, +#define Z_IS_4070_EQ_4070U(...) \, +#define Z_IS_4070U_EQ_4070U(...) \, +#define Z_IS_4071_EQ_4071(...) \, +#define Z_IS_4071U_EQ_4071(...) \, +#define Z_IS_4071_EQ_4071U(...) \, +#define Z_IS_4071U_EQ_4071U(...) \, +#define Z_IS_4072_EQ_4072(...) \, +#define Z_IS_4072U_EQ_4072(...) \, +#define Z_IS_4072_EQ_4072U(...) \, +#define Z_IS_4072U_EQ_4072U(...) \, +#define Z_IS_4073_EQ_4073(...) \, +#define Z_IS_4073U_EQ_4073(...) \, +#define Z_IS_4073_EQ_4073U(...) \, +#define Z_IS_4073U_EQ_4073U(...) \, +#define Z_IS_4074_EQ_4074(...) \, +#define Z_IS_4074U_EQ_4074(...) \, +#define Z_IS_4074_EQ_4074U(...) \, +#define Z_IS_4074U_EQ_4074U(...) \, +#define Z_IS_4075_EQ_4075(...) \, +#define Z_IS_4075U_EQ_4075(...) \, +#define Z_IS_4075_EQ_4075U(...) \, +#define Z_IS_4075U_EQ_4075U(...) \, +#define Z_IS_4076_EQ_4076(...) \, +#define Z_IS_4076U_EQ_4076(...) \, +#define Z_IS_4076_EQ_4076U(...) \, +#define Z_IS_4076U_EQ_4076U(...) \, +#define Z_IS_4077_EQ_4077(...) \, +#define Z_IS_4077U_EQ_4077(...) \, +#define Z_IS_4077_EQ_4077U(...) \, +#define Z_IS_4077U_EQ_4077U(...) \, +#define Z_IS_4078_EQ_4078(...) \, +#define Z_IS_4078U_EQ_4078(...) \, +#define Z_IS_4078_EQ_4078U(...) \, +#define Z_IS_4078U_EQ_4078U(...) \, +#define Z_IS_4079_EQ_4079(...) \, +#define Z_IS_4079U_EQ_4079(...) \, +#define Z_IS_4079_EQ_4079U(...) \, +#define Z_IS_4079U_EQ_4079U(...) \, +#define Z_IS_4080_EQ_4080(...) \, +#define Z_IS_4080U_EQ_4080(...) \, +#define Z_IS_4080_EQ_4080U(...) \, +#define Z_IS_4080U_EQ_4080U(...) \, +#define Z_IS_4081_EQ_4081(...) \, +#define Z_IS_4081U_EQ_4081(...) \, +#define Z_IS_4081_EQ_4081U(...) \, +#define Z_IS_4081U_EQ_4081U(...) \, +#define Z_IS_4082_EQ_4082(...) \, +#define Z_IS_4082U_EQ_4082(...) \, +#define Z_IS_4082_EQ_4082U(...) \, +#define Z_IS_4082U_EQ_4082U(...) \, +#define Z_IS_4083_EQ_4083(...) \, +#define Z_IS_4083U_EQ_4083(...) \, +#define Z_IS_4083_EQ_4083U(...) \, +#define Z_IS_4083U_EQ_4083U(...) \, +#define Z_IS_4084_EQ_4084(...) \, +#define Z_IS_4084U_EQ_4084(...) \, +#define Z_IS_4084_EQ_4084U(...) \, +#define Z_IS_4084U_EQ_4084U(...) \, +#define Z_IS_4085_EQ_4085(...) \, +#define Z_IS_4085U_EQ_4085(...) \, +#define Z_IS_4085_EQ_4085U(...) \, +#define Z_IS_4085U_EQ_4085U(...) \, +#define Z_IS_4086_EQ_4086(...) \, +#define Z_IS_4086U_EQ_4086(...) \, +#define Z_IS_4086_EQ_4086U(...) \, +#define Z_IS_4086U_EQ_4086U(...) \, +#define Z_IS_4087_EQ_4087(...) \, +#define Z_IS_4087U_EQ_4087(...) \, +#define Z_IS_4087_EQ_4087U(...) \, +#define Z_IS_4087U_EQ_4087U(...) \, +#define Z_IS_4088_EQ_4088(...) \, +#define Z_IS_4088U_EQ_4088(...) \, +#define Z_IS_4088_EQ_4088U(...) \, +#define Z_IS_4088U_EQ_4088U(...) \, +#define Z_IS_4089_EQ_4089(...) \, +#define Z_IS_4089U_EQ_4089(...) \, +#define Z_IS_4089_EQ_4089U(...) \, +#define Z_IS_4089U_EQ_4089U(...) \, +#define Z_IS_4090_EQ_4090(...) \, +#define Z_IS_4090U_EQ_4090(...) \, +#define Z_IS_4090_EQ_4090U(...) \, +#define Z_IS_4090U_EQ_4090U(...) \, +#define Z_IS_4091_EQ_4091(...) \, +#define Z_IS_4091U_EQ_4091(...) \, +#define Z_IS_4091_EQ_4091U(...) \, +#define Z_IS_4091U_EQ_4091U(...) \, +#define Z_IS_4092_EQ_4092(...) \, +#define Z_IS_4092U_EQ_4092(...) \, +#define Z_IS_4092_EQ_4092U(...) \, +#define Z_IS_4092U_EQ_4092U(...) \, +#define Z_IS_4093_EQ_4093(...) \, +#define Z_IS_4093U_EQ_4093(...) \, +#define Z_IS_4093_EQ_4093U(...) \, +#define Z_IS_4093U_EQ_4093U(...) \, +#define Z_IS_4094_EQ_4094(...) \, +#define Z_IS_4094U_EQ_4094(...) \, +#define Z_IS_4094_EQ_4094U(...) \, +#define Z_IS_4094U_EQ_4094U(...) \, +#define Z_IS_4095_EQ_4095(...) \, +#define Z_IS_4095U_EQ_4095(...) \, +#define Z_IS_4095_EQ_4095U(...) \, +#define Z_IS_4095U_EQ_4095U(...) \, +#define Z_IS_4096_EQ_4096(...) \, +#define Z_IS_4096U_EQ_4096(...) \, +#define Z_IS_4096_EQ_4096U(...) \, +#define Z_IS_4096U_EQ_4096U(...) \, #endif /* ZEPHYR_INCLUDE_SYS_UTIL_INTERNAL_IS_EQ_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_macro.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_macro.h index 5b3864d2..4a3767bf 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_macro.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys/util_macro.h @@ -93,6 +93,22 @@ extern "C" { */ #define IS_BIT_MASK(m) IS_SHIFTED_BIT_MASK(m, 0) +/** @brief Extract the Least Significant Bit from @p value. */ +#define LSB_GET(value) ((value) & -(value)) + +/** + * @brief Extract a bitfield element from @p value corresponding to + * the field mask @p mask. + */ +#define FIELD_GET(mask, value) (((value) & (mask)) / LSB_GET(mask)) + +/** + * @brief Prepare a bitfield element using @p value with @p mask representing + * its field position and width. The result should be combined + * with other fields using a logical OR. + */ +#define FIELD_PREP(mask, value) (((value) * LSB_GET(mask)) & (mask)) + /** * @brief Check for macro definition in compiler-visible expressions * @@ -280,7 +296,19 @@ extern "C" { * @brief Like a == b, but does evaluation and * short-circuiting at C preprocessor time. * - * This however only works for integer literal from 0 to 4095. + * This however only works for integer literal from 0 to 4096 (literals with U suffix, + * e.g. 0U are also included). + * + * Examples: + * + * IS_EQ(1, 1) -> 1 + * IS_EQ(1U, 1U) -> 1 + * IS_EQ(1U, 1) -> 1 + * IS_EQ(1, 1U) -> 1 + * IS_EQ(1, 0) -> 0 + * + * @param a Integer literal (can be with U suffix) + * @param b Integer literal * */ #define IS_EQ(a, b) Z_IS_EQ(a, b) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys_clock.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys_clock.h index e43b539f..36abcff9 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys_clock.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/sys_clock.h @@ -94,6 +94,12 @@ typedef struct { /** number of seconds per minute */ #define SEC_PER_MIN 60U +/** number of seconds per hour */ +#define SEC_PER_HOUR 3600U + +/** number of seconds per day */ +#define SEC_PER_DAY 86400U + /** number of minutes per hour */ #define MIN_PER_HOUR 60U @@ -251,21 +257,6 @@ k_timepoint_t sys_timepoint_calc(k_timeout_t timeout); */ k_timeout_t sys_timepoint_timeout(k_timepoint_t timepoint); -/** - * @brief Provided for backward compatibility. - * - * This is deprecated. Consider `sys_timepoint_calc()` instead. - * - * @see sys_timepoint_calc() - */ -__deprecated -static inline uint64_t sys_clock_timeout_end_calc(k_timeout_t timeout) -{ - k_timepoint_t tp = sys_timepoint_calc(timeout); - - return tp.tick; -} - /** * @brief Compare two timepoint values. * diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/task_wdt/task_wdt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/task_wdt/task_wdt.h index e14ef581..91cc9798 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/task_wdt/task_wdt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/task_wdt/task_wdt.h @@ -14,8 +14,8 @@ * threads. It can be used together with a hardware watchdog as a fallback. */ -#ifndef TASK_WDT_H_ -#define TASK_WDT_H_ +#ifndef ZEPHYR_INCLUDE_TASK_WDT_H_ +#define ZEPHYR_INCLUDE_TASK_WDT_H_ #include #include @@ -110,4 +110,4 @@ int task_wdt_feed(int channel_id); * @} */ -#endif /* TASK_WDT_H_ */ +#endif /* ZEPHYR_INCLUDE_TASK_WDT_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/gcc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/gcc.h index 9af23fb2..bb55d50a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/gcc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/gcc.h @@ -186,10 +186,14 @@ do { \ "." Z_STRINGIFY(c)))) #define __in_section(a, b, c) ___in_section(a, b, c) +#ifndef __in_section_unique #define __in_section_unique(seg) ___in_section(seg, __FILE__, __COUNTER__) +#endif +#ifndef __in_section_unique_named #define __in_section_unique_named(seg, name) \ ___in_section(seg, __FILE__, name) +#endif /* When using XIP, using '__ramfunc' places a function into RAM instead * of FLASH. Make sure '__ramfunc' is defined only when @@ -225,6 +229,10 @@ do { \ #define __aligned(x) __attribute__((__aligned__(x))) #endif +#ifndef __noinline +#define __noinline __attribute__((noinline)) +#endif + #define __may_alias __attribute__((__may_alias__)) #ifndef __printf_like @@ -250,6 +258,9 @@ do { \ #ifndef __deprecated #define __deprecated __attribute__((deprecated)) +/* When adding this, remember to follow the instructions in + * https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated + */ #endif #ifndef __attribute_const__ @@ -312,6 +323,9 @@ do { \ /* Generic message */ #ifndef __DEPRECATED_MACRO #define __DEPRECATED_MACRO __WARN("Macro is deprecated") +/* When adding this, remember to follow the instructions in + * https://docs.zephyrproject.org/latest/develop/api/api_lifecycle.html#deprecated + */ #endif /* These macros allow having ARM asm functions callable from thumb */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/mwdt.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/mwdt.h index 48ce1b69..715c34bd 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/mwdt.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/mwdt.h @@ -114,16 +114,6 @@ #else /* defined(_ASMLANGUAGE) */ -/* MWDT toolchain misses ssize_t definition which is used by Zephyr */ -#ifndef _SSIZE_T_DEFINED -#define _SSIZE_T_DEFINED -#ifdef CONFIG_64BIT - typedef long ssize_t; -#else - typedef int ssize_t; -#endif -#endif /* _SSIZE_T_DEFINED */ - #ifdef CONFIG_NEWLIB_LIBC #error "ARC MWDT doesn't support building with CONFIG_NEWLIB_LIBC as it doesn't have newlib" #endif /* CONFIG_NEWLIB_LIBC */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/xcc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/xcc.h index ae4bb811..4078556e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/xcc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/toolchain/xcc.h @@ -11,6 +11,20 @@ #error Please do not include toolchain-specific headers directly, use instead #endif +/* + * XCC does not support using deprecated attribute in enum, + * so just nullify it here to avoid compilation errors. + */ +#define __deprecated + +#define __in_section_unique(seg) \ + __attribute__((section("." STRINGIFY(seg) "." STRINGIFY(__COUNTER__)))) + +#define __in_section_unique_named(seg, name) \ + __attribute__((section("." STRINGIFY(seg) \ + "." STRINGIFY(__COUNTER__) \ + "." STRINGIFY(name)))) + /* toolchain/gcc.h errors out if __BYTE_ORDER__ cannot be determined * there. However, __BYTE_ORDER__ is actually being defined later in * this file. So define __BYTE_ORDER__ to skip the check in gcc.h @@ -121,16 +135,6 @@ #define __COUNTER__ __LINE__ #endif -#undef __in_section_unique -#define __in_section_unique(seg) \ - __attribute__((section("." STRINGIFY(seg) "." STRINGIFY(__COUNTER__)))) - -#undef __in_section_unique_named -#define __in_section_unique_named(seg, name) \ - __attribute__((section("." STRINGIFY(seg) \ - "." STRINGIFY(__COUNTER__) \ - "." STRINGIFY(name)))) - #ifndef __GCC_LINKER_CMD__ #include @@ -155,13 +159,4 @@ #define __sync_synchronize() do { __asm__ __volatile__ ("" ::: "memory"); } \ while (false) -#ifdef __deprecated -/* - * XCC does not support using deprecated attribute in enum, - * so just nullify it here to avoid compilation errors. - */ -#undef __deprecated -#define __deprecated -#endif - #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing.h index 3e1f998c..68a453a8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing.h @@ -427,6 +427,28 @@ */ #define sys_port_trace_k_work_queue_start_exit(queue) +/** + * @brief Trace stop of a Work Queue call entry + * @param queue Work Queue structure + * @param timeout Timeout period + */ +#define sys_port_trace_k_work_queue_stop_enter(queue, timeout) + +/** + * @brief Trace stop of a Work Queue call blocking + * @param queue Work Queue structure + * @param timeout Timeout period + */ +#define sys_port_trace_k_work_queue_stop_blocking(queue, timeout) + +/** + * @brief Trace stop of a Work Queue call exit + * @param queue Work Queue structure + * @param timeout Timeout period + * @param ret Return value + */ +#define sys_port_trace_k_work_queue_stop_exit(queue, timeout, ret) + /** * @brief Trace Work Queue drain call entry * @param queue Work Queue structure @@ -2028,6 +2050,56 @@ /** @} */ /* end of subsys_tracing_apis_pm_device_runtime */ +/** + * @brief Network Core Tracing APIs + * @defgroup subsys_tracing_apis_net Network Core Tracing APIs + * @{ + */ + +/** + * @brief Trace network data receive + * @param iface Network interface + * @param pkt Received network packet + */ +#define sys_port_trace_net_recv_data_enter(iface, pkt) + +/** + * @brief Trace network data receive attempt + * @param iface Network interface + * @param pkt Received network packet + * @param ret Return value + */ +#define sys_port_trace_net_recv_data_exit(iface, pkt, ret) + +/** + * @brief Trace network data send + * @param pkt Network packet to send + */ +#define sys_port_trace_net_send_data_enter(pkt) + +/** + * @brief Trace network data send attempt + * @param pkt Received network packet + * @param ret Return value + */ +#define sys_port_trace_net_send_data_exit(pkt, ret) + +/** + * @brief Trace network data receive time + * @param pkt Received network packet + * @param end_time When the RX processing stopped for this pkt (in ticks) + */ +#define sys_port_trace_net_rx_time(pkt, end_time) + +/** + * @brief Trace network data sent time + * @param pkt Sent network packet + * @param end_time When the TX processing stopped for this pkt (in ticks) + */ +#define sys_port_trace_net_tx_time(pkt, end_time) + +/** @} */ /* end of subsys_tracing_apis_net */ + /** * @brief Network Socket Tracing APIs * @defgroup subsys_tracing_apis_socket Network Socket Tracing APIs @@ -2326,6 +2398,237 @@ /** @} */ /* end of subsys_tracing_apis_socket */ +/** + * @brief Named Tracing APIs + * @defgroup subsys_tracing_apis_named Named tracing APIs + * @{ + */ + +/* + * @brief Called by user to generate named events + * + * @param name name of event. Tracing subsystems may place a limit on + * the length of this string + * @param arg0 arbitrary user-provided data for this event + * @param arg1 arbitrary user-provided data for this event + */ +#define sys_trace_named_event(name, arg0, arg1) + +/** @} */ /* end of subsys_tracing_apis_named */ + +/** + * @brief GPIO Tracing APIs + * @defgroup subsys_tracing_apis_gpio GPIO Tracing APIs + * @{ + */ + +/** + * @brief Trace GPIO pin interrupt configure enter call + * @param port Pointer to device structure for the driver instance + * @param pin GPIO pin number + * @param flags Interrupt configuration flags as defined by GPIO_INT_* + */ +#define sys_port_trace_gpio_pin_interrupt_configure_enter(port, pin, flags) + +/** + * @brief Trace GPIO pin interrupt configure exit call + * @param port Pointer to device structure for the driver instance + * @param pin GPIO pin number + * @param ret Return value + */ +#define sys_port_trace_gpio_pin_interrupt_configure_exit(port, pin, ret) + +/** + * @brief Trace GPIO single pin configure enter call + * @param port Pointer to device structure for the driver instance + * @param pin GPIO pin number to configure + * @param flags GPIO pin configuration flags + */ +#define sys_port_trace_gpio_pin_configure_enter(port, pin, flags) + +/** + * @brief Trace GPIO single pin configure exit call + * @param port Pointer to device structure for the driver instance + * @param pin GPIO pin number to configure + * @param ret Return value + */ +#define sys_port_trace_gpio_pin_configure_exit(port, pin, ret) + +/** + * @brief Trace GPIO port get direction enter call + * @param port Pointer to device structure for the driver instance + * @param map Bitmap of pin directions to query + * @param inputs Pointer to a variable where input directions will be stored + * @param outputs Pointer to a variable where output directions will be stored + */ +#define sys_port_trace_gpio_port_get_direction_enter(port, map, inputs, outputs) + +/** + * @brief Trace GPIO port get direction exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_port_get_direction_exit(port, ret) + +/** + * @brief Trace GPIO pin gent config enter call + * @param port Pointer to device structure for the driver instance + * @param pin GPIO pin number to configure + * @param flags GPIO pin configuration flags + */ +#define sys_port_trace_gpio_pin_get_config_enter(port, pin, flags) + +/** + * @brief Trace GPIO pin get config exit call + * @param port Pointer to device structure for the driver instance + * @param pin GPIO pin number to configure + * @param ret Return value + */ +#define sys_port_trace_gpio_pin_get_config_exit(port, pin, ret) + +/** + * @brief Trace GPIO port get raw enter call + * @param port Pointer to device structure for the driver instance + * @param value Pointer to a variable where the raw value will be stored + */ +#define sys_port_trace_gpio_port_get_raw_enter(port, value) + +/** + * @brief Trace GPIO port get raw exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_port_get_raw_exit(port, ret) + +/** + * @brief Trace GPIO port set masked raw enter call + * @param port Pointer to device structure for the driver instance + * @param mask Mask indicating which pins will be modified + * @param value Value to be written to the output pins + */ +#define sys_port_trace_gpio_port_set_masked_raw_enter(port, mask, value) + +/** + * @brief Trace GPIO port set masked raw exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_port_set_masked_raw_exit(port, ret) + +/** + * @brief Trace GPIO port set bits raw enter call + * @param port Pointer to device structure for the driver instance + * @param pins Value indicating which pins will be modified + */ +#define sys_port_trace_gpio_port_set_bits_raw_enter(port, pins) + +/** + * @brief Trace GPIO port set bits raw exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_port_set_bits_raw_exit(port, ret) + +/** + * @brief Trace GPIO port clear bits raw enter call + * @param port Pointer to device structure for the driver instance + * @param pins Value indicating which pins will be modified + */ +#define sys_port_trace_gpio_port_clear_bits_raw_enter(port, pins) + +/** + * @brief Trace GPIO port clear bits raw exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_port_clear_bits_raw_exit(port, ret) + +/** + * @brief Trace GPIO port toggle bits enter call + * @param port Pointer to device structure for the driver instance + * @param pins Value indicating which pins will be modified + */ +#define sys_port_trace_gpio_port_toggle_bits_enter(port, pins) + +/** + * @brief Trace GPIO port toggle bits exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_port_toggle_bits_exit(port, ret) + +/** + * @brief Trace GPIO init callback enter call + * @param callback A valid application's callback structure pointer + * @param handler A valid handler function pointer + * @param pin_mask A bit mask of relevant pins for the handler + */ +#define sys_port_trace_gpio_init_callback_enter(callback, handler, pin_mask) + +/** + * @brief Trace GPIO init callback exit call + * @param callback A valid application's callback structure pointer + */ +#define sys_port_trace_gpio_init_callback_exit(callback) + +/** + * @brief Trace GPIO add callback enter call + * @param port Pointer to device structure for the driver instance + * @param callback A valid application's callback structure pointer + */ +#define sys_port_trace_gpio_add_callback_enter(port, callback) + +/** + * @brief Trace GPIO add callback exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_add_callback_exit(port, ret) + +/** + * @brief Trace GPIO remove callback enter call + * @param port Pointer to device structure for the driver instance + * @param callback A valid application's callback structure pointer + */ +#define sys_port_trace_gpio_remove_callback_enter(port, callback) + +/** + * @brief Trace GPIO remove callback exit call + * @param port Pointer to device structure for the driver instance + * @param ret Return value + */ +#define sys_port_trace_gpio_remove_callback_exit(port, ret) + +/** + * @brief Trace GPIO get pending interrupt enter call + * @param dev Pointer to the device structure for the device instance + */ +#define sys_port_trace_gpio_get_pending_int_enter(dev) + +/** + * @brief Trace GPIO get pending interrupt exit call + * @param dev Pointer to the device structure for the device instance + * @param ret Return value + */ +#define sys_port_trace_gpio_get_pending_int_exit(dev, ret) + +/** + * @brief + * @param list @ref sys_slist_t representing gpio_callback pointers + * @param port @ref device representing the GPIO port + * @param pins @ref gpio_pin_t representing the pins + */ +#define sys_port_trace_gpio_fire_callbacks_enter(list, port, pins) + +/** + * @brief + * @param port @ref device representing the GPIO port + * @param callback @ref gpio_callback a valid Application's callback structure pointer + */ +#define sys_port_trace_gpio_fire_callback(port, callback) + +/** @} */ /* end of subsys_tracing_apis_gpio */ + #if defined(CONFIG_PERCEPIO_TRACERECORDER) #include "tracing_tracerecorder.h" #else diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing_macros.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing_macros.h index 80eed3d0..7e6c8d7b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing_macros.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/tracing/tracing_macros.h @@ -185,12 +185,18 @@ #define sys_port_trace_pm_is_disabled 1 #endif -#if defined(CONFIG_TRACING_NETWORKING) +#if defined(CONFIG_TRACING_NET_SOCKETS) #define sys_port_trace_type_mask_socket(trace_call) trace_call #else #define sys_port_trace_type_mask_socket(trace_call) #endif +#if defined(CONFIG_TRACING_NET_CORE) + #define sys_port_trace_type_mask_net(trace_call) trace_call +#else + #define sys_port_trace_type_mask_net(trace_call) +#endif + /* * We cannot positively enumerate all traced APIs, as applications may trace * arbitrary custom APIs we know nothing about. Therefore we demand that tracing diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/types.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/types.h index 7e5e87b2..145957da 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/types.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/types.h @@ -29,6 +29,24 @@ typedef union { void (*thepfunc)(void); } z_max_align_t; +/* + * Thread local variables are declared with different keywords depending on + * which C/C++ standard that is used. C++11 and C23 uses "thread_local" whilst + * C11 uses "_Thread_local". Previously the GNU "__thread" keyword was used + * which is the same in both gcc and g++. + */ +#ifndef Z_THREAD_LOCAL +#if defined(__cplusplus) && (__cplusplus) >= 201103L /* C++11 */ +#define Z_THREAD_LOCAL thread_local +#elif defined(__STDC_VERSION__) && (__STDC_VERSION__) >= 202311L /* C23 */ +#define Z_THREAD_LOCAL thread_local +#elif defined(__STDC_VERSION__) && (__STDC_VERSION__) >= 201112L /* C11 */ +#define Z_THREAD_LOCAL _Thread_local +#else /* Default back to old behavior which used the GNU keyword. */ +#define Z_THREAD_LOCAL __thread +#endif +#endif /* Z_THREAD_LOCAL */ + #ifdef __cplusplus /* Zephyr requires an int main(void) signature with C linkage for the application main if present */ extern int main(void); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/bos.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/bos.h index f73e7c06..79dd802b 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/bos.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/bos.h @@ -14,6 +14,8 @@ * @brief USB Binary Device Object Store support * @defgroup usb_bos USB BOS support * @ingroup usb + * @since 1.13 + * @version 1.0.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/hid.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/hid.h index b8888068..96bb8271 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/hid.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/hid.h @@ -24,6 +24,8 @@ extern "C" { * @brief hid.h API * @defgroup usb_hid_definitions USB HID common definitions * @ingroup usb + * @since 1.11 + * @version 1.0.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_audio.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_audio.h index 9062af37..4c1c4db5 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_audio.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_audio.h @@ -23,7 +23,7 @@ #include #include -#include +#include #include /** Audio Interface Subclass Codes. diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_cdc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_cdc.h index e0232aa7..06b8d806 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_cdc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_cdc.h @@ -28,11 +28,13 @@ #define ACM_SUBCLASS 0x02 #define ECM_SUBCLASS 0x06 #define EEM_SUBCLASS 0x0c +#define NCM_SUBCLASS 0x0d /** Communications Class Protocol Codes */ #define AT_CMD_V250_PROTOCOL 0x01 #define EEM_PROTOCOL 0x07 #define ACM_VENDOR_PROTOCOL 0xFF +#define NCM_DATA_PROTOCOL 0x01 /** * @brief Data Class Interface Codes @@ -50,6 +52,7 @@ #define ACM_FUNC_DESC 0x02 #define UNION_FUNC_DESC 0x06 #define ETHERNET_FUNC_DESC 0x0F +#define ETHERNET_FUNC_DESC_NCM 0x1a /** * @brief PSTN Subclass Specific Requests @@ -139,6 +142,22 @@ #define SET_ETHERNET_PACKET_FILTER 0x43 #define GET_ETHERNET_STATISTIC 0x44 +/** + * @brief Class-Specific Request Codes for NCM subclass + * @note NCM100.pdf, 6.2, Table 6-2 + */ +#define GET_NTB_PARAMETERS 0x80 +#define GET_NET_ADDRESS 0x81 +#define SET_NET_ADDRESS 0x82 +#define GET_NTB_FORMAT 0x83 +#define SET_NTB_FORMAT 0x84 +#define GET_NTB_INPUT_SIZE 0x85 +#define SET_NTB_INPUT_SIZE 0x86 +#define GET_MAX_DATAGRAM_SIZE 0x87 +#define SET_MAX_DATAGRAM_SIZE 0x88 +#define GET_CRC_MODE 0x89 +#define SET_CRC_MODE 0x8A + /** Ethernet Packet Filter Bitmap */ #define PACKET_TYPE_MULTICAST 0x10 #define PACKET_TYPE_BROADCAST 0x08 @@ -210,4 +229,13 @@ struct cdc_ecm_descriptor { uint8_t bNumberPowerFilters; } __packed; +/** Ethernet Network Control Model (NCM) Descriptor */ +struct cdc_ncm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdNcmVersion; + uint8_t bmNetworkCapabilities; +} __packed; + #endif /* ZEPHYR_INCLUDE_USB_CLASS_USB_CDC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_hid.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_hid.h index f15d0526..39e869fa 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_hid.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usb_hid.h @@ -24,6 +24,8 @@ extern "C" { * @brief usb_hid.h API * @defgroup usb_hid_class USB HID class API * @ingroup usb + * @since 1.11 + * @version 1.0.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_hid.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_hid.h index 7e992107..db2d55b6 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_hid.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_hid.h @@ -24,6 +24,8 @@ extern "C" { * @brief USBD HID Device API * @defgroup usbd_hid_device USBD HID device API * @ingroup usb + * @since 3.7 + * @version 0.1.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_msc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_msc.h index 9b0b1322..c38fc5fb 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_msc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_msc.h @@ -27,6 +27,8 @@ struct usbd_msc_lun { * @brief USB Mass Storage Class device API * @defgroup usbd_msc_device USB Mass Storage Class device API * @ingroup usb + * @since 3.4 + * @version 0.1.0 * @{ */ @@ -37,17 +39,18 @@ struct usbd_msc_lun { * Up to `CONFIG_USBD_MSC_LUNS_PER_INSTANCE` disks can be registered on single * USB MSC instance. Currently only one USB MSC instance is supported. * + * @param id Identifier by which the linker sorts registered LUNs * @param disk_name Disk name as used in @ref disk_access_interface * @param t10_vendor T10 Vendor Indetification * @param t10_product T10 Product Identification * @param t10_revision T10 Product Revision Level */ -#define USBD_DEFINE_MSC_LUN(disk_name, t10_vendor, t10_product, t10_revision) \ - STRUCT_SECTION_ITERABLE(usbd_msc_lun, usbd_msc_lun_##disk_name) = { \ - .disk = STRINGIFY(disk_name), \ - .vendor = t10_vendor, \ - .product = t10_product, \ - .revision = t10_revision, \ +#define USBD_DEFINE_MSC_LUN(id, disk_name, t10_vendor, t10_product, t10_revision) \ + static const STRUCT_SECTION_ITERABLE(usbd_msc_lun, usbd_msc_lun_##id) = { \ + .disk = disk_name, \ + .vendor = t10_vendor, \ + .product = t10_product, \ + .revision = t10_revision, \ } /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_uac2.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_uac2.h index 22b599a2..271d9dd0 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_uac2.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/class/usbd_uac2.h @@ -23,6 +23,8 @@ * @brief USB Audio Class 2 device API * @defgroup uac2_device USB Audio Class 2 device API * @ingroup usb + * @since 3.6 + * @version 0.1.0 * @{ */ @@ -123,6 +125,39 @@ struct uac2_ops { */ uint32_t (*feedback_cb)(const struct device *dev, uint8_t terminal, void *user_data); + /** + * @brief Get active sample rate + * + * USB stack calls this function when the host asks for active sample + * rate if the Clock Source entity supports more than one sample rate. + * This function won't ever be called (should be NULL) if all Clock + * Source entities support only one sample rate. + * + * @param dev USB Audio 2 device + * @param clock_id Clock Source ID whose sample rate should be returned + * @param user_data Opaque user data pointer + * + * @return Active sample rate in Hz + */ + uint32_t (*get_sample_rate)(const struct device *dev, uint8_t clock_id, + void *user_data); + /** + * @brief Set active sample rate + * + * USB stack calls this function when the host sets active sample rate. + * This callback may be NULL if all Clock Source entities have only one + * sample rate. USB stack sanitizes the sample rate to closest valid + * rate for given Clock Source entity. + * + * @param dev USB Audio 2 device + * @param clock_id Clock Source ID whose sample rate should be set + * @param rate Sample rate in Hz + * @param user_data Opaque user data pointer + * + * @return 0 on success, negative value on error + */ + int (*set_sample_rate)(const struct device *dev, uint8_t clock_id, + uint32_t rate, void *user_data); }; /** diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/msos_desc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/msos_desc.h index 372c8aa5..895675db 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/msos_desc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/msos_desc.h @@ -99,4 +99,33 @@ struct msosv2_guids_property { 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, \ 'D', 0x00, 's', 0x00, 0x00, 0x00 +/* Microsoft OS 2.0 minimum USB resume time descriptor */ +struct msosv2_resume_time { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t bResumeRecoveryTime; + uint8_t bResumeSignalingTime; +} __packed; + +/* Microsoft OS 2.0 model ID descriptor */ +struct msosv2_model_id { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t ModelID[16]; +} __packed; + +/* Microsoft OS 2.0 CCGP device descriptor */ +struct msosv2_ccgp_device { + uint16_t wLength; + uint16_t wDescriptorType; +} __packed; + +/* Microsoft OS 2.0 vendor revision descriptor */ +struct msosv2_vendor_revision { + uint16_t wLength; + uint16_t wDescriptorType; + uint16_t VendorRevision; +} __packed; + + #endif /* ZEPHYR_INCLUDE_USB_MSOS_DESC_H */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_ch9.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_ch9.h index dccc7445..3f1ad5b8 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_ch9.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_ch9.h @@ -283,7 +283,12 @@ struct usb_association_descriptor { /** Macro to obtain descriptor index from USB_SREQ_GET_DESCRIPTOR request */ #define USB_GET_DESCRIPTOR_INDEX(wValue) ((uint8_t)(wValue)) -/** USB Control Endpoints maximum packet size (MPS) */ +/** + * USB Control Endpoints maximum packet size (MPS) + * + * This value may not be correct for devices operating at speeds other than + * high speed. + */ #define USB_CONTROL_EP_MPS 64U /** USB endpoint direction mask */ @@ -348,6 +353,35 @@ struct usb_association_descriptor { /** Calculate high speed isochronous endpoint bInterval from a value in microseconds */ #define USB_HS_ISO_EP_INTERVAL(us) CLAMP((ilog2((us) / 125U) + 1U), 1U, 16U) +/** Get endpoint size field from Max Packet Size value */ +#define USB_MPS_EP_SIZE(mps) ((mps) & BIT_MASK(11)) + +/** Get number of additional transactions per microframe from Max Packet Size value */ +#define USB_MPS_ADDITIONAL_TRANSACTIONS(mps) (((mps) & 0x1800) >> 11) + +/** Calculate total payload length from Max Packet Size value */ +#define USB_MPS_TO_TPL(mps) \ + ((1 + USB_MPS_ADDITIONAL_TRANSACTIONS(mps)) * USB_MPS_EP_SIZE(mps)) + +/** Calculate Max Packet Size value from total payload length */ +#define USB_TPL_TO_MPS(tpl) \ + (((tpl) > 2048) ? ((2 << 11) | ((tpl) / 3)) : \ + ((tpl) > 1024) ? ((1 << 11) | ((tpl) / 2)) : \ + (tpl)) + +/** Round up total payload length to next valid value */ +#define USB_TPL_ROUND_UP(tpl) \ + (((tpl) > 2048) ? ROUND_UP(tpl, 3) : \ + ((tpl) > 1024) ? ROUND_UP(tpl, 2) : \ + (tpl)) + +/** Determine whether total payload length value is valid according to USB 2.0 */ +#define USB_TPL_IS_VALID(tpl) \ + (((tpl) > 3072) ? false : \ + ((tpl) > 2048) ? ((tpl) % 3 == 0) : \ + ((tpl) > 1024) ? ((tpl) % 2 == 0) : \ + ((tpl) >= 0)) + #ifdef __cplusplus } #endif diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_device.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_device.h index 59c3db1c..e596555e 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_device.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usb_device.h @@ -92,6 +92,8 @@ extern "C" { /** * @brief USB Device Core Layer API * @defgroup _usb_device_core_api USB Device Core API + * @since 1.5 + * @version 1.0.0 * @{ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd.h index 77784ac1..b588d708 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd.h @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include @@ -32,6 +32,8 @@ extern "C" { * @brief New USB device stack core API * @defgroup usbd_api USB device core API * @ingroup usb + * @since 3.3 + * @version 0.1.0 * @{ */ @@ -59,6 +61,8 @@ extern "C" { */ #define USB_STRING_DESCRIPTOR_LENGTH(s) (sizeof(s) * 2) +struct usbd_context; + /** Used internally to keep descriptors in order * @cond INTERNAL_HIDDEN */ @@ -67,11 +71,13 @@ enum usbd_str_desc_utype { USBD_DUT_STRING_MANUFACTURER, USBD_DUT_STRING_PRODUCT, USBD_DUT_STRING_SERIAL_NUMBER, + USBD_DUT_STRING_CONFIG, USBD_DUT_STRING_INTERFACE, }; enum usbd_bos_desc_utype { USBD_DUT_BOS_NONE, + USBD_DUT_BOS_VREQ, }; /** @endcond */ @@ -89,12 +95,63 @@ struct usbd_str_desc_data { unsigned int use_hwinfo : 1; }; +/** + * USBD vendor request node + * + * Vendor request node is identified by the vendor code and is used to register + * callbacks to handle the vendor request with the receiving device. + * When the device stack receives a request with type Vendor and recipient + * Device, and bRequest value equal to the vendor request code, it will call + * the vendor callbacks depending on the direction of the request. + * + * Example callback code fragment: + * + * @code{.c} + * static int foo_to_host_cb(const struct usbd_context *const ctx, + * const struct usb_setup_packet *const setup, + * struct net_buf *const buf) + * { + * if (setup->wIndex == WEBUSB_REQ_GET_URL) { + * uint8_t index = USB_GET_DESCRIPTOR_INDEX(setup->wValue); + * + * if (index != SAMPLE_WEBUSB_LANDING_PAGE) { + * return -ENOTSUP; + * } + * + * net_buf_add_mem(buf, &webusb_origin_url, + * MIN(net_buf_tailroom(buf), sizeof(webusb_origin_url))); + * + * return 0; + * } + * + * return -ENOTSUP; + * } + * @endcode + */ +struct usbd_vreq_node { + /** Node information for the dlist */ + sys_dnode_t node; + /** Vendor code (bRequest value) */ + const uint8_t code; + /** Vendor request callback for device-to-host direction */ + int (*to_host)(const struct usbd_context *const ctx, + const struct usb_setup_packet *const setup, + struct net_buf *const buf); + /** Vendor request callback for host-to-device direction */ + int (*to_dev)(const struct usbd_context *const ctx, + const struct usb_setup_packet *const setup, + const struct net_buf *const buf); +}; + /** * USBD BOS Device Capability descriptor data */ struct usbd_bos_desc_data { /** Descriptor usage type (not bDescriptorType) */ enum usbd_bos_desc_utype utype : 8; + union { + struct usbd_vreq_node *const vreq_nd; + }; }; /** @@ -131,6 +188,8 @@ struct usbd_config_node { sys_snode_t node; /** Pointer to configuration descriptor */ void *desc; + /** Optional pointer to string descriptor node */ + struct usbd_desc_node *str_desc_nd; /** List of registered classes (functions) */ sys_slist_t class_list; }; @@ -199,8 +258,6 @@ struct usbd_status { enum usbd_speed speed : 2; }; -struct usbd_context; - /** * @brief Callback type definition for USB device message delivery * @@ -238,6 +295,8 @@ struct usbd_context { sys_slist_t fs_configs; /** slist to manage High-Speed device configurations */ sys_slist_t hs_configs; + /** dlist to manage vendor requests with recipient device */ + sys_dlist_t vreqs; /** Status of the USB device support */ struct usbd_status status; /** Pointer to Full-Speed device descriptor */ @@ -463,8 +522,11 @@ static inline void *usbd_class_get_private(const struct usbd_class_data *const c * with usbd_config_attrib_rwup() and usbd_config_attrib_self() * @param power bMaxPower value in 2 mA units. This value can also be set with * usbd_config_maxpower() + * @param desc_nd Address of the string descriptor node used to describe the + * configuration, see USBD_DESC_CONFIG_DEFINE(). + * String descriptors are optional and the parameter can be NULL. */ -#define USBD_CONFIGURATION_DEFINE(name, attrib, power) \ +#define USBD_CONFIGURATION_DEFINE(name, attrib, power, desc_nd) \ static struct usb_cfg_descriptor \ cfg_desc_##name = { \ .bLength = sizeof(struct usb_cfg_descriptor), \ @@ -479,6 +541,7 @@ static inline void *usbd_class_get_private(const struct usbd_class_data *const c BUILD_ASSERT((power) < 256, "Too much power"); \ static struct usbd_config_node name = { \ .desc = &cfg_desc_##name, \ + .str_desc_nd = desc_nd, \ } /** @@ -497,13 +560,13 @@ static inline void *usbd_class_get_private(const struct usbd_class_data *const c #define USBD_DESC_LANG_DEFINE(name) \ static uint16_t langid_##name = sys_cpu_to_le16(0x0409); \ static struct usbd_desc_node name = { \ - .bLength = sizeof(struct usb_string_descriptor), \ - .bDescriptorType = USB_DESC_STRING, \ .str = { \ .idx = 0, \ .utype = USBD_DUT_STRING_LANG, \ }, \ .ptr = &langid_##name, \ + .bLength = sizeof(struct usb_string_descriptor), \ + .bDescriptorType = USB_DESC_STRING, \ } /** @@ -524,9 +587,9 @@ static inline void *usbd_class_get_private(const struct usbd_class_data *const c .utype = d_utype, \ .ascii7 = true, \ }, \ + .ptr = &ascii_##d_name, \ .bLength = USB_STRING_DESCRIPTOR_LENGTH(d_string), \ .bDescriptorType = USB_DESC_STRING, \ - .ptr = &ascii_##d_name, \ } /** @@ -577,6 +640,18 @@ static inline void *usbd_class_get_private(const struct usbd_class_data *const c .bDescriptorType = USB_DESC_STRING, \ } +/** + * @brief Create a string descriptor node for configuration descriptor + * + * This macro defines a descriptor node whose address can be used as an + * argument for the USBD_CONFIGURATION_DEFINE() macro. + * + * @param d_name String descriptor node identifier. + * @param d_string ASCII7 encoded configuration description string literal + */ +#define USBD_DESC_CONFIG_DEFINE(d_name, d_string) \ + USBD_DESC_STRING_DEFINE(d_name, d_string, USBD_DUT_STRING_CONFIG) + /** * @brief Define BOS Device Capability descriptor node * @@ -597,6 +672,49 @@ static inline void *usbd_class_get_private(const struct usbd_class_data *const c .bDescriptorType = USB_DESC_BOS, \ } +/** + * @brief Define a vendor request with recipient device + * + * @param name Vendor request identifier + * @param vcode Vendor request code + * @param vto_host Vendor callback for to-host direction request + * @param vto_dev Vendor callback for to-device direction request + */ +#define USBD_VREQUEST_DEFINE(name, vcode, vto_host, vto_dev) \ + static struct usbd_vreq_node name = { \ + .code = vcode, \ + .to_host = vto_host, \ + .to_dev = vto_dev, \ + } + +/** + * @brief Define BOS Device Capability descriptor node with vendor request + * + * This macro defines a BOS descriptor, usually a platform capability, with a + * vendor request node. + * + * USBD_DESC_BOS_VREQ_DEFINE(bos_vreq_webusb, sizeof(bos_cap_webusb), &bos_cap_webusb, + * SAMPLE_WEBUSB_VENDOR_CODE, webusb_to_host_cb, NULL); + * + * @param name Descriptor node identifier + * @param len Device Capability descriptor length + * @param subset Pointer to a Device Capability descriptor + * @param vcode Vendor request code + * @param vto_host Vendor callback for to-host direction request + * @param vto_dev Vendor callback for to-device direction request + */ +#define USBD_DESC_BOS_VREQ_DEFINE(name, len, subset, vcode, vto_host, vto_dev) \ + USBD_VREQUEST_DEFINE(vreq_nd_##name, vcode, vto_host, vto_dev); \ + static struct usbd_desc_node name = { \ + .bos = { \ + .utype = USBD_DUT_BOS_VREQ, \ + .vreq_nd = &vreq_nd_##name, \ + }, \ + .ptr = subset, \ + .bLength = len, \ + .bDescriptorType = USB_DESC_BOS, \ + } + /** * @brief Define USB device support class data * @@ -959,8 +1077,8 @@ enum usbd_speed usbd_caps_speed(const struct usbd_context *const uds_ctx); * * @return 0 on success, other values on fail. */ -int usbd_device_set_bcd(struct usbd_context *const uds_ctx, - const enum usbd_speed speed, const uint16_t bcd); +int usbd_device_set_bcd_usb(struct usbd_context *const uds_ctx, + const enum usbd_speed speed, const uint16_t bcd); /** * @brief Set USB device descriptor value idVendor @@ -984,6 +1102,17 @@ int usbd_device_set_vid(struct usbd_context *const uds_ctx, int usbd_device_set_pid(struct usbd_context *const uds_ctx, const uint16_t pid); +/** + * @brief Set USB device descriptor value bcdDevice + * + * @param[in] uds_ctx Pointer to USB device support context + * @param[in] bcd bcdDevice value + * + * @return 0 on success, other values on fail. + */ +int usbd_device_set_bcd_device(struct usbd_context *const uds_ctx, + const uint16_t bcd); + /** * @brief Set USB device descriptor code triple Base Class, SubClass, and Protocol * @@ -1056,6 +1185,20 @@ int usbd_config_maxpower(struct usbd_context *const uds_ctx, */ bool usbd_can_detect_vbus(struct usbd_context *const uds_ctx); +/** + * @brief Register an USB vendor request with recipient device + * + * The vendor request with the recipient device applies to all configurations + * within the device. + * + * @param[in] uds_ctx Pointer to USB device support context + * @param[in] vreq_nd Pointer to vendor request node + * + * @return 0 on success, other values on fail. + */ +int usbd_device_register_vreq(struct usbd_context *const uds_ctx, + struct usbd_vreq_node *const vreq_nd); + /** * @} */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd_msg.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd_msg.h index 13d0f01e..b9e99d00 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd_msg.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbd_msg.h @@ -21,6 +21,8 @@ extern "C" { /** * @defgroup usbd_msg_api USB device core API * @ingroup usb + * @since 3.7 + * @version 0.1.0 * @{ */ @@ -40,6 +42,8 @@ enum usbd_msg_type { USBD_MSG_SUSPEND, /** Bus reset detected */ USBD_MSG_RESET, + /** Device changed configuration */ + USBD_MSG_CONFIGURATION, /** Non-correctable UDC error message */ USBD_MSG_UDC_ERROR, /** Unrecoverable device stack error message */ @@ -61,6 +65,7 @@ static const char *const usbd_msg_type_list[] = { "Device resumed", "Device suspended", "Bus reset", + "New device configuration", "Controller error", "Stack error", "CDC ACM line coding", diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbh.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbh.h index 66ba4307..869f3007 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbh.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb/usbh.h @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include #include diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb_c/tcpci.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb_c/tcpci.h new file mode 100644 index 00000000..ff36219d --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/usb_c/tcpci.h @@ -0,0 +1,788 @@ +/* + * Copyright 2024 Google LLC + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_USB_C_TCPCI_H_ +#define ZEPHYR_INCLUDE_USB_C_TCPCI_H_ + +/** + * @file + * @brief Registers and fields definitions for TypeC Port Controller Interface + * + * This file contains register addresses, fields and masks used to retrieve specific data from + * registry values. They may be used by all TCPC drivers compliant to the TCPCI specification. + * Registers and fields are compliant to the Type-C Port Controller Interface + * Specification Revision 2.0, Version 1.3. + */ + +/** Register address - vendor id */ +#define TCPC_REG_VENDOR_ID 0x0 + +/** Register address - product id */ +#define TCPC_REG_PRODUCT_ID 0x2 + +/** Register address - version of TCPC */ +#define TCPC_REG_BCD_DEV 0x4 + +/** Register address - USB TypeC version */ +#define TCPC_REG_TC_REV 0x6 +/** Mask for major part of type-c release supported */ +#define TCPC_REG_TC_REV_MAJOR_MASK GENMASK(7, 4) +/** Macro to extract the major part of type-c release supported */ +#define TCPC_REG_TC_REV_MAJOR(reg) (((reg) & TCPC_REG_TC_REV_MAJOR_MASK) >> 4) +/** Mask for minor part of type-c release supported */ +#define TCPC_REG_TC_REV_MINOR_MASK GENMASK(3, 0) +/** Macro to extract the minor part of type-c release supported */ +#define TCPC_REG_TC_REV_MINOR(reg) ((reg) & TCPC_REG_TC_REV_MINOR_MASK) + +/** Register address - Power delivery revision */ +#define TCPC_REG_PD_REV 0x8 +/** Mask for major part of USB PD revision supported */ +#define TCPC_REG_PD_REV_REV_MAJOR_MASK GENMASK(15, 12) +/** Macro to extract the major part of USB PD revision supported */ +#define TCPC_REG_PD_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MAJOR_MASK) >> 12) +/** Mask for minor part of USB PD revision supported */ +#define TCPC_REG_PD_REV_REV_MINOR_MASK GENMASK(11, 8) +/** Macro to extract the minor part of USB PD revision supported */ +#define TCPC_REG_PD_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MINOR_MASK) >> 8) +/** Mask for major part of USB PD version supported */ +#define TCPC_REG_PD_REV_VER_MAJOR_MASK GENMASK(7, 4) +/** Macro to extract the major part of USB PD version supported */ +#define TCPC_REG_PD_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_VER_MAJOR_MASK) >> 4) +/** Mask for minor part of USB PD version supported */ +#define TCPC_REG_PD_REV_VER_MINOR_MASK GENMASK(3, 0) +/** Macro to extract the minor part of USB PD version supported */ +#define TCPC_REG_PD_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_REV_VER_VER_MINOR_MASK) + +/** Register address - interface revision and version */ +#define TCPC_REG_PD_INT_REV 0xa +/** Mask for major part of USB Port Controller Interface revision supported */ +#define TCPC_REG_PD_INT_REV_REV_MAJOR_MASK GENMASK(15, 12) +/** Macro to extract the major part of USB Port Controller Interface revision supported */ +#define TCPC_REG_PD_INT_REV_REV_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MAJOR_MASK) >> 12) +/** Mask for minor part of USB Port Controller Interface revision supported */ +#define TCPC_REG_PD_INT_REV_REV_MINOR_MASK GENMASK(11, 8) +/** Macro to extract the minor part of USB Port Controller Interface revision supported */ +#define TCPC_REG_PD_INT_REV_REV_MINOR(reg) (((reg) & TCPC_REG_PD_REV_VER_REV_MINOR_MASK) >> 8) +/** Mask for major part of USB Port Controller Interface version supported */ +#define TCPC_REG_PD_INT_REV_VER_MAJOR_MASK GENMASK(7, 4) +/** Macro to extract the major part of USB Port Controller Interface version supported */ +#define TCPC_REG_PD_INT_REV_VER_MAJOR(reg) (((reg) & TCPC_REG_PD_REV_VER_VER_MAJOR_MASK) >> 4) +/** Mask for minor part of USB Port Controller Interface version supported */ +#define TCPC_REG_PD_INT_REV_VER_MINOR_MASK GENMASK(3, 0) +/** Macro to extract the minor part of USB Port Controller Interface version supported */ +#define TCPC_REG_PD_INT_REV_VER_MINOR(reg) ((reg) & TCPC_REG_PD_REV_VER_VER_MINOR_MASK) + +/** Register address - alert */ +#define TCPC_REG_ALERT 0x10 +/** Value for clear alert */ +#define TCPC_REG_ALERT_NONE 0x0000 +/** Value mask for all alert bits */ +#define TCPC_REG_ALERT_MASK_ALL 0xffff +/** Bit for vendor defined alert */ +#define TCPC_REG_ALERT_VENDOR_DEF BIT(15) +/** Bit for extended alert */ +#define TCPC_REG_ALERT_ALERT_EXT BIT(14) +/** Bit for extended status alert */ +#define TCPC_REG_ALERT_EXT_STATUS BIT(13) +/** Bit for beginning of data receive */ +#define TCPC_REG_ALERT_RX_BEGINNING BIT(12) +/** Bit for vbus disconnection alert */ +#define TCPC_REG_ALERT_VBUS_DISCNCT BIT(11) +/** Bit for receive buffer overflow alert */ +#define TCPC_REG_ALERT_RX_BUF_OVF BIT(10) +/** Bit for fault alert */ +#define TCPC_REG_ALERT_FAULT BIT(9) +/** Bit for low vbus alarm */ +#define TCPC_REG_ALERT_V_ALARM_LO BIT(8) +/** Bit for high vbus alarm */ +#define TCPC_REG_ALERT_V_ALARM_HI BIT(7) +/** Bit for transmission success */ +#define TCPC_REG_ALERT_TX_SUCCESS BIT(6) +/** Bit for transmission discard alert */ +#define TCPC_REG_ALERT_TX_DISCARDED BIT(5) +/** Bit for transmission fail alert */ +#define TCPC_REG_ALERT_TX_FAILED BIT(4) +/** Bit for received hard reset alert */ +#define TCPC_REG_ALERT_RX_HARD_RST BIT(3) +/** Bit for data received alert */ +#define TCPC_REG_ALERT_RX_STATUS BIT(2) +/** Bit for power status alert */ +#define TCPC_REG_ALERT_POWER_STATUS BIT(1) +/** Bit for CC lines status alert */ +#define TCPC_REG_ALERT_CC_STATUS BIT(0) +/** Bits for any of transmission status alert */ +#define TCPC_REG_ALERT_TX_COMPLETE \ + (TCPC_REG_ALERT_TX_SUCCESS | TCPC_REG_ALERT_TX_DISCARDED | TCPC_REG_ALERT_TX_FAILED) + +/** + * Register address - alert mask + * The bits for specific masks are on the same positions as for the @see TCPC_REG_ALERT register. + */ +#define TCPC_REG_ALERT_MASK 0x12 + +/** + * Register address - power status mask + * The bits for specific masks are on the same positions as for the @see TCPC_REG_POWER_STATUS + * register. + */ +#define TCPC_REG_POWER_STATUS_MASK 0x14 + +/** + * Register address - fault status mask + * The bits for specific masks are on the same positions as for the @see TCPC_REG_FAULT_STATUS + * register. + */ +#define TCPC_REG_FAULT_STATUS_MASK 0x15 + +/** + * Register address - extended status mask + * The bits for specific masks are on the same positions as for the @see TCPC_REG_EXT_STATUS + * register. + */ +#define TCPC_REG_EXT_STATUS_MASK 0x16 + +/** + * Register address - extended alert mask + * The bits for specific masks are on the same positions as for the @see TCPC_REG_ALERT_EXT + * register. + */ +#define TCPC_REG_ALERT_EXT_MASK 0x17 + +/** Register address - configure standard output */ +#define TCPC_REG_CONFIG_STD_OUTPUT 0x18 +/** Bit for high impedance outputs */ +#define TCPC_REG_CONFIG_STD_OUTPUT_HIGH_Z BIT(7) +/** Bit for debug accessory connected# */ +#define TCPC_REG_CONFIG_STD_OUTPUT_DBG_ACC_CONN_N BIT(6) +/** Bit for audio accessory connected# */ +#define TCPC_REG_CONFIG_STD_OUTPUT_AUDIO_CONN_N BIT(5) +/** Bit for active cable */ +#define TCPC_REG_CONFIG_STD_OUTPUT_ACTIVE_CABLE BIT(4) +/** Value mask for mux control */ +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_MASK (3 << 2) +/** Value for mux - no connection */ +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_NONE (0 << 2) +/** Value for mux - USB3.1 connected */ +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB (1 << 2) +/** Value for mux - DP alternate mode with 4 lanes */ +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_DP (2 << 2) +/** Value for mux - USB3.1 + DP 0&1 lines */ +#define TCPC_REG_CONFIG_STD_OUTPUT_MUX_USB_DP (3 << 2) +/** Bit for connection present */ +#define TCPC_REG_CONFIG_STD_OUTPUT_CONN_PRESENT BIT(1) +/** Bit for connector orientation */ +#define TCPC_REG_CONFIG_STD_OUTPUT_CONNECTOR_FLIPPED BIT(0) + +/** Register address - TCPC control */ +#define TCPC_REG_TCPC_CTRL 0x19 +/** Bit for SMBus PEC enabled */ +#define TCPC_REG_TCPC_CTRL_SMBUS_PEC BIT(7) +/** Bit for enabling the alert assertion when a connection is found */ +#define TCPC_REG_TCPC_CTRL_EN_LOOK4CONNECTION_ALERT BIT(6) +/** Bit for watchdog monitoring */ +#define TCPC_REG_TCPC_CTRL_WATCHDOG_TIMER BIT(5) +/** Bit for enable debug accessory control by TCPM */ +#define TCPC_REG_TCPC_CTRL_DEBUG_ACC_CONTROL BIT(4) +/** Mask*/ +#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_MASK GENMASK(3, 2) +/** Value for clock stretching disabled */ +#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_DISABLED 0 +/** Value for limited clock stretching enabled */ +#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_ALWAYS (2 << 2) +/** Value for clock stretching enabled only when alert is NOT asserted */ +#define TCPC_REG_TCPC_CTRL_CLOCK_STRETCH_EN_NO_ALERT (3 << 2) +/** Bit for BIST test mode enabled */ +#define TCPC_REG_TCPC_CTRL_BIST_TEST_MODE BIT(1) +/** Bit for plug orientation and vconn destination */ +#define TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION BIT(0) + +/** Register address - role control */ +#define TCPC_REG_ROLE_CTRL 0x1a +/** Bit for dual-role port */ +#define TCPC_REG_ROLE_CTRL_DRP_MASK BIT(6) +/** Mask to extract the RP value from register value */ +#define TCPC_REG_ROLE_CTRL_RP_MASK GENMASK(5, 4) +/** Mask to extract the CC2 pull value from register value */ +#define TCPC_REG_ROLE_CTRL_CC2_MASK GENMASK(3, 2) +/** Mask to extract the CC! pull value from register value */ +#define TCPC_REG_ROLE_CTRL_CC1_MASK GENMASK(1, 0) +/** Macro to set the register value from drp, rp and CC lines values */ +#define TCPC_REG_ROLE_CTRL_SET(drp, rp, cc1, cc2) \ + ((((drp) << 6) & TCPC_REG_ROLE_CTRL_DRP_MASK) | \ + (((rp) << 4) & TCPC_REG_ROLE_CTRL_RP_MASK) | \ + (((cc2) << 2) & TCPC_REG_ROLE_CTRL_CC2_MASK) | ((cc1) & TCPC_REG_ROLE_CTRL_CC1_MASK)) +#define TCPC_REG_ROLE_CTRL_DRP(reg) (((reg) & TCPC_REG_ROLE_CTRL_DRP_MASK) >> 6) +/** Macro to extract the enum tc_rp_value from register value */ +#define TCPC_REG_ROLE_CTRL_RP(reg) (((reg) & TCPC_REG_ROLE_CTRL_RP_MASK) >> 4) +/** Macro to extract the enum tc_cc_pull for CC2 from register value */ +#define TCPC_REG_ROLE_CTRL_CC2(reg) (((reg) & TCPC_REG_ROLE_CTRL_CC2_MASK) >> 2) +/** Macro to extract the enum tc_cc_pull for CC1 from register value */ +#define TCPC_REG_ROLE_CTRL_CC1(reg) ((reg) & TCPC_REG_ROLE_CTRL_CC1_MASK) + +/** Register address - fault control */ +#define TCPC_REG_FAULT_CTRL 0x1b +/** Bit for block the standard input signal force off vbus control */ +#define TCPC_REG_FAULT_CTRL_VBUS_FORCE_OFF BIT(4) +/** Bit for disabling the vbus discharge fault detection timer */ +#define TCPC_REG_FAULT_CTRL_VBUS_DISCHARGE_FAULT BIT(3) +/** Bit for disabling the vbus over current detection */ +#define TCPC_REG_FAULT_CTRL_VBUS_OCP_FAULT_DIS BIT(2) +/** Bit for disabling the vbus over voltage detection */ +#define TCPC_REG_FAULT_CTRL_VBUS_OVP_FAULT_DIS BIT(1) +/** Bit for disabling the vconn over current detection */ +#define TCPC_REG_FAULT_CTRL_VCONN_OCP_FAULT_DIS BIT(0) + +/** Register address - power control */ +#define TCPC_REG_POWER_CTRL 0x1c +/** Bit for fast role swap enable */ +#define TCPC_REG_POWER_CTRL_FRS_ENABLE BIT(7) +/** Bit for disabling the vbus voltage monitoring */ +#define TCPC_REG_POWER_CTRL_VBUS_VOL_MONITOR_DIS BIT(6) +/** Bit for disabling the voltage alarms */ +#define TCPC_REG_POWER_CTRL_VOLT_ALARM_DIS BIT(5) +/** Bit for enabling the automatic vbus discharge based on the vbus voltage */ +#define TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT BIT(4) +/** Bit for enabling the bleed discharge of vbus */ +#define TCPC_REG_POWER_CTRL_BLEED_DISCHARGE BIT(3) +/** Bit for enabling the forced vbus discharge */ +#define TCPC_REG_POWER_CTRL_FORCE_DISCHARGE BIT(2) +/** + * Bit for enabling the vconn power supported. + * If set, the TCPC will deliver at least the power indicated in the vconn power supported in + * device capabilities register to the vconn. + * If unset, at least 1W of power will be delivered to vconn. + */ +#define TCPC_REG_POWER_CTRL_VCONN_SUPP BIT(1) +/** Bit for enabling the vconn sourcing to CC line */ +#define TCPC_REG_POWER_CTRL_VCONN_EN BIT(0) + +/** Register address - CC lines status */ +#define TCPC_REG_CC_STATUS 0x1d +/** Bit for active looking for a connection by TCPC, both DRP and sink/source only */ +#define TCPC_REG_CC_STATUS_LOOK4CONNECTION BIT(5) +/** Bit for connection result, set if presenting Rd, unset if presenting Rp*/ +#define TCPC_REG_CC_STATUS_CONNECT_RESULT BIT(4) +/** Mask for CC2 line state */ +#define TCPC_REG_CC_STATUS_CC2_STATE_MASK GENMASK(3, 2) +/** + * Macro to extract the status value of CC2 line. Interpretation of this value depends on the + * value of CC2 configuration in Role Control register and on the connect result in this register. + * For value interpretation look at the CC_STATUS Register Definition in the TCPCI specification. + */ +#define TCPC_REG_CC_STATUS_CC2_STATE(reg) (((reg) & TCPC_REG_CC_STATUS_CC2_STATE_MASK) >> 2) +/** Mask for CC1 line state */ +#define TCPC_REG_CC_STATUS_CC1_STATE_MASK GENMASK(1, 0) +/** Macto to extract the status value of CC1 line. Look at the information about the CC2 macro. */ +#define TCPC_REG_CC_STATUS_CC1_STATE(reg) ((reg) & TCPC_REG_CC_STATUS_CC1_STATE_MASK) + +/** Register address - power status */ +#define TCPC_REG_POWER_STATUS 0x1e +/** Bit for debug accessory connected */ +#define TCPC_REG_POWER_STATUS_DEBUG_ACC_CON BIT(7) +/** Bit for internal initialization in-progress. If set, only registers 00-0F contain valid data. */ +#define TCPC_REG_POWER_STATUS_UNINIT BIT(6) +/** Bit for sourcing high voltage. If set, the voltage sourced is above the vSafe5V. */ +#define TCPC_REG_POWER_STATUS_SOURCING_HV BIT(5) +/** Bit for sourcing vbus. If set, sourcing vbus is enabled. */ +#define TCPC_REG_POWER_STATUS_SOURCING_VBUS BIT(4) +/** Bit for vbus detection enabled. */ +#define TCPC_REG_POWER_STATUS_VBUS_DET BIT(3) +/** + * Bit for vbus present. + * If set, the vbus shall be above 4V. If unset, the vbus shall be below 3.5V. + */ +#define TCPC_REG_POWER_STATUS_VBUS_PRES BIT(2) +/** Bit for vconn present. Set if vconn is present on CC1 or CC2, threshold is fixed at 2.4V. */ +#define TCPC_REG_POWER_STATUS_VCONN_PRES BIT(1) +/** Bit for sinking vbus. If set, the TCPC is sinking vbus to the system load. */ +#define TCPC_REG_POWER_STATUS_SINKING_VBUS BIT(0) + +/** Register address - fault status */ +#define TCPC_REG_FAULT_STATUS 0x1f +/** Bit for all registers reset to default */ +#define TCPC_REG_FAULT_STATUS_ALL_REGS_RESET BIT(7) +/** Bit for force vbus off due to external fault */ +#define TCPC_REG_FAULT_STATUS_FORCE_OFF_VBUS BIT(6) +/** Bit for auto discharge failed */ +#define TCPC_REG_FAULT_STATUS_AUTO_DISCHARGE_FAIL BIT(5) +/** Bit for force discharge failed */ +#define TCPC_REG_FAULT_STATUS_FORCE_DISCHARGE_FAIL BIT(4) +/** Bit for internal or external vbus over current */ +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_CURRENT BIT(3) +/** Bit for internal or external vbus over voltage */ +#define TCPC_REG_FAULT_STATUS_VBUS_OVER_VOLTAGE BIT(2) +/** Bit for vconn over current */ +#define TCPC_REG_FAULT_STATUS_VCONN_OVER_CURRENT BIT(1) +/** Bit for I2C interface error */ +#define TCPC_REG_FAULT_STATUS_I2C_INTERFACE_ERR BIT(0) + +/** Register address - extended status */ +#define TCPC_REG_EXT_STATUS 0x20 +/** Bit for vbus at vSafe0V. Set when the TCPC detects that VBUS is below 0.8V. */ +#define TCPC_REG_EXT_STATUS_SAFE0V BIT(0) + +/** Register address - alert extended */ +#define TCPC_REG_ALERT_EXT 0x21 +/** Bit for timer expired */ +#define TCPC_REG_ALERT_EXT_TIMER_EXPIRED BIT(2) +/** Bit for source fast role swap. Set when FRS signal sent due to standard input being low. */ +#define TCPC_REG_ALERT_EXT_SRC_FRS BIT(1) +/** Bit for sink fast role swap. If set, the fast role swap signal was received. */ +#define TCPC_REG_ALERT_EXT_SNK_FRS BIT(0) + +/** Register address - command */ +#define TCPC_REG_COMMAND 0x23 +/** Value for wake i2c command */ +#define TCPC_REG_COMMAND_WAKE_I2C 0x11 +/** Value for disable vbus detect command - disable vbus present and vSafe0V detection */ +#define TCPC_REG_COMMAND_DISABLE_VBUS_DETECT 0x22 +/** Value for enable vbus detect command - enable vbus present and vSafe0V detection */ +#define TCPC_REG_COMMAND_ENABLE_VBUS_DETECT 0x33 +/** Value for disable sink vbus - disable sinking power over vbus */ +#define TCPC_REG_COMMAND_SNK_CTRL_LOW 0x44 +/** Value for sink vbus - enable sinking power over vbus and vbus present detection */ +#define TCPC_REG_COMMAND_SNK_CTRL_HIGH 0x55 +/** Value for disable source vbus - disable sourcing power over vbus */ +#define TCPC_REG_COMMAND_SRC_CTRL_LOW 0x66 +/** Value for source vbus default voltage - enable sourcing vSafe5V over vbus */ +#define TCPC_REG_COMMAND_SRC_CTRL_DEF 0x77 +/** Value for source vbus high voltage - enable sourcing high voltage over vbus */ +#define TCPC_REG_COMMAND_SRC_CTRL_HV 0x88 +/** Value for look for connection - start DRP toggling if DRP role is set */ +#define TCPC_REG_COMMAND_LOOK4CONNECTION 0x99 +/** + * Value for rx one more + * Configure receiver to automatically clear the receive_detect register after sending next GoodCRC. + */ +#define TCPC_REG_COMMAND_RX_ONE_MORE 0xAA +/** + * Value for send fast role swap signal + * Send FRS if TCPC is source with FRS enabled in power control register + */ +#define TCPC_REG_COMMAND_SEND_FRS_SIGNAL 0xCC +/** Value for reset transmit buffer - TCPC resets the pointer of transmit buffer to offset 1 */ +#define TCPC_REG_COMMAND_RESET_TRANSMIT_BUF 0xDD +/** + * Value for reset receive buffer + * If buffer pointer is at 132 or less, it is reset to 1, otherwise it is reset to 133. + */ +#define TCPC_REG_COMMAND_RESET_RECEIVE_BUF 0xEE +/** Value for i2c idle */ +#define TCPC_REG_COMMAND_I2CIDLE 0xFF + +/** Register address - device capabilities 1 */ +#define TCPC_REG_DEV_CAP_1 0x24 +/** Bit for vbus high voltage target - if set, VBUS_HV_TARGET register is implemented */ +#define TCPC_REG_DEV_CAP_1_VBUS_NONDEFAULT_TARGET BIT(15) +/** Bit for vbus over current reporting - if set, vbus over current is reported by TCPC */ +#define TCPC_REG_DEV_CAP_1_VBUS_OCP_REPORTING BIT(14) +/** Bit for vbus over voltage reporting - if set, vbus over voltage is reported by TCPC */ +#define TCPC_REG_DEV_CAP_1_VBUS_OVP_REPORTING BIT(13) +/** Bit for bleed discharge - if set, bleed discharge is implemented in TCPC */ +#define TCPC_REG_DEV_CAP_1_BLEED_DISCHARGE BIT(12) +/** Bit for force discharge - if set, force discharge is implemented in TCPC */ +#define TCPC_REG_DEV_CAP_1_FORCE_DISCHARGE BIT(11) +/** + * Bit for vbus measurement and alarm capable + * If set, TCPC supports vbus voltage measurement and vbus voltage alarms + */ +#define TCPC_REG_DEV_CAP_1_VBUS_MEASURE_ALARM_CAPABLE BIT(10) +/** Mask for source resistor supported */ +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK GENMASK(9, 8) +/** + * Macro to extract the supported source resistors from register value + * The value can be cast to enum tc_rp_value and value can be treated as highest amperage supported + * since the TCPC has also to support lower values than specified. + */ +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR(reg) \ + (((reg) & TCPC_REG_DEV_CAP_1_SRC_RESISTOR_MASK) >> 8) +/** Value for Rp default only - only default amperage is supported */ +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_DEF 0 +/** Value for Rp 1.5A and default - support for 1.5A and for default amperage*/ +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_1P5_DEF 1 +/** Value for Rp 3.0A, 1.5A and default - support for 3.0A, 1.5A and default amperage */ +#define TCPC_REG_DEV_CAP_1_SRC_RESISTOR_RP_3P0_1P5_DEF 2 +/** Mask for power roles supported */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK GENMASK(7, 5) +#define TCPC_REG_DEV_CAP_1_POWER_ROLE(reg) \ + (((reg) & TCPC_REG_DEV_CAP_1_POWER_ROLE_MASK) >> 5) +/** Value for support both source and sink only (no DRP) */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_OR_SNK 0 +/** Value for support source role only */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC 1 +/** Value for support sink role only */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK 2 +/** Value for support sink role with accessory */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SNK_ACC 3 +/** Value for support dual-role port only */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_DRP 4 +/** Value for support source, sink, dual-role port, adapter and cable */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP_ADPT_CBL 5 +/** Value for support source, sink and dual-role port */ +#define TCPC_REG_DEV_CAP_1_POWER_ROLE_SRC_SNK_DRP 6 +/** Bit for debug SOP' and SOP'' support - if set, all SOP* messages are supported */ +#define TCPC_REG_DEV_CAP_1_ALL_SOP_STAR_MSGS_SUPPORTED BIT(4) +/** Bit for source vconn - if set, TCPC is capable of switching the vconn source */ +#define TCPC_REG_DEV_CAP_1_SOURCE_VCONN BIT(3) +/** Bit for sink vbus - if set, TCPC is capable of controling the sink path to the system load */ +#define TCPC_REG_DEV_CAP_1_SINK_VBUS BIT(2) +/** + * Bit for source high voltage vbus. + * If set, TCPC can control the source high voltage path to vbus + */ +#define TCPC_REG_DEV_CAP_1_SOURCE_HV_VBUS BIT(1) +/** Bit for source vbus - if set, TCPC is capable of controlling the source path to vbus */ +#define TCPC_REG_DEV_CAP_1_SOURCE_VBUS BIT(0) + +/** Register address - device capabilities 2 */ +#define TCPC_REG_DEV_CAP_2 0x26 +/** Bit for device capabilities 3 support */ +#define TCPC_REG_DEV_CAP_2_CAP_3_SUPPORTED BIT(15) +/** Bit for message disable disconnect */ +#define TCPC_REG_DEV_CAP_2_MSG_DISABLE_DISCONNECT BIT(14) +/** Bit for generic timer support */ +#define TCPC_REG_DEV_CAP_2_GENERIC_TIMER BIT(13) +/** + * Bit for long message support + * If set, the TCPC supports up to 264 bytes content of the SOP*. + * One I2C transaction can write up to 132 bytes. + * If unset, the TCPC support only 30 bytes content of the SOP* message. + */ +#define TCPC_REG_DEV_CAP_2_LONG_MSG BIT(12) +/** Bit for SMBus PEC support. If set, SMBus PEC can be enabled in the TCPC control register. */ +#define TCPC_REG_DEV_CAP_2_SMBUS_PEC BIT(11) +/** Bit for source fast-role swap support. If set, TCPC is capable of sending FRS as source. */ +#define TCPC_REG_DEV_CAP_2_SRC_FRS BIT(10) +/** Bit for sink fast-role swap support. If set, TCPC is capable of sending FRS as sink. */ +#define TCPC_REG_DEV_CAP_2_SNK_FRS BIT(9) +/** Bit for watchdog timer support. If set, watchdog can be enabled in the TCPC control register. */ +#define TCPC_REG_DEV_CAP_2_WATCHDOG_TIMER BIT(8) +/** + * Bit for sink disconnect detection. + * If set, the sink disconnect threshold can be set. Otherwise, the vbus present value from + * status register will be used to indicate the sink disconnection. + */ +#define TCPC_REG_DEV_CAP_2_SNK_DISC_DET BIT(7) +/** + * Bit for stop discharge threshold. If set, the TCPM can set the voltage threshold at which + * the forced vbus discharge will be disabled, into the vbus stop discharge threshold register. + */ +#define TCPC_REG_DEV_CAP_2_STOP_DISCHARGE_THRESH BIT(6) +/** Mask for resolution of voltage alarm */ +#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK GENMASK(5, 4) +/** Macro to extract the voltage alarm resolution from the register value */ +#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM(reg) \ + (((reg) & TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_MASK) >> 4) +/** Value for 25mV resolution of voltage alarm, all 10 bits of voltage alarm registers are used. */ +#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_25MV 0 +/** Value for 50mV resolution of voltage alarm, only 9 bits of voltage alarm registers are used. */ +#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_50MV 1 +/** Value for 100mV resolution of voltage alarm, only 8 bits of voltage alarm registers are used. */ +#define TCPC_REG_DEV_CAP_2_VBUS_VOLTAGE_ALARM_100MV 2 +/** Mask for vconn power supported */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK GENMASK(3, 1) +/** Macro to extract the vconn power supported from the register value */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED(reg) \ + (((reg) & TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_MASK) >> 1) +/** Value for vconn power supported of 1.0W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_0W 0 +/** Value for vconn power supported of 1.5W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_1_5W 1 +/** Value for vconn power supported of 2.0W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_2_0W 2 +/** Value for vconn power supported of 3.0W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_3_0W 3 +/** Value for vconn power supported of 4.0W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_4_0W 4 +/** Value for vconn power supported of 5.0W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_5_0W 5 +/** Value for vconn power supported of 6.0W */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_6_0W 6 +/** Value for external vconn power supported */ +#define TCPC_REG_DEV_CAP_2_VCONN_POWER_SUPPORTED_EXTERNAL 7 +/** Bit for vconn overcurrent fault capable - if set, TCPC can detect the vconn over current */ +#define TCPC_REG_DEV_CAP_2_VCONN_OVC_FAULT BIT(0) + +/** Register address - standard input capabilities */ +#define TCPC_REG_STD_INPUT_CAP 0x28 +/** Mask for source fast role swap */ +#define TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK GENMASK(4, 3) +/** Macro to extract the source fast role swap from register value */ +#define TCPC_REG_STD_INPUT_CAP_SRC_FRS(reg) (((reg) & TCPC_REG_STD_INPUT_CAP_SRC_FRS_MASK) >> 3) +/** Value for no source fast role swap pin present in TCPC */ +#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_NONE 0 +/** Value for source fast role swap input only pin present in TCPC */ +#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_INPUT 1 +/** Value for source fast role swap both input and output pin present in TCPC */ +#define TCPC_REG_STD_INTPU_CAP_SRC_FRS_BOTH 2 +/** Bit for vbus external over voltage fault. If set, input pin is present in TCPC. */ +#define TCPC_REG_STD_INPUT_CAP_EXT_OVP BIT(2) +/** Bit for vbus external over current fault. If set, input pin is present in TCPC. */ +#define TCPC_REG_STD_INPUT_CAP_EXT_OCP BIT(1) +/** Bit for force off vbus present. If set, input pin is present in TCPC. */ +#define TCPC_REG_STD_INPUT_CAP_FORCE_OFF_VBUS BIT(0) + +/** Register address - standard output capabilities */ +#define TCPC_REG_STD_OUTPUT_CAP 0x29 +/** Bit for vbus sink disconnect detect indicator */ +#define TCPC_REG_STD_OUTPUT_CAP_SNK_DISC_DET BIT(7) +/** Bit for debug accessory indicator */ +#define TCPC_REG_STD_OUTPUT_CAP_DBG_ACCESSORY BIT(6) +/** Bit for vbus present monitor */ +#define TCPC_REG_STD_OUTPUT_CAP_VBUS_PRESENT_MON BIT(5) +/** Bit for audio adapter accessory indicator */ +#define TCPC_REG_STD_OUTPUT_CAP_AUDIO_ACCESSORY BIT(4) +/** Bit for active cable indicator */ +#define TCPC_REG_STD_OUTPUT_CAP_ACTIVE_CABLE BIT(3) +/** Bit for mux configuration control */ +#define TCPC_REG_STD_OUTPUT_CAP_MUX_CFG_CTRL BIT(2) +/** Bit for connection present */ +#define TCPC_REG_STD_OUTPUT_CAP_CONN_PRESENT BIT(1) +/** Bit for connector orientation */ +#define TCPC_REG_STD_OUTPUT_CAP_CONN_ORIENTATION BIT(0) + +/** Register address - configure extended 1 */ +#define TCPC_REG_CONFIG_EXT_1 0x2A +/** + * Bit for fr swap bidirectional pin. + * If set, the bidirectional FR swap pin is configured as standard output signal. + * If unset, it's configured as standard input signal. + */ +#define TCPC_REG_CONFIG_EXT_1_FRS_SNK_DIR BIT(1) +/** + * Bit for standard input source FR swap. + * If set, blocks the source fast role swap input signal from triggering the sending of + * fast role swap signal. + * If unset, allow the input signal to trigger sending the fast role swap signal. + */ +#define TCPC_REG_CONFIG_EXT_1_STD_IN_SRC_FRS BIT(0) + +/** + * Register address - generic timer + * Available only if generic timer bit is set in device capabilities 2 register. + * This register is 16-bit wide and has a resolution of 0.1ms. + */ +#define TCPC_REG_GENERIC_TIMER 0x2c + +/** Register address - message header info */ +#define TCPC_REG_MSG_HDR_INFO 0x2e +/** Bit for cable plug. If set, the message originated from a cable plug. */ +#define TCPC_REG_MSG_HDR_INFO_CABLE_PLUG BIT(4) +/** Mask for data role */ +#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK BIT(3) +/** Macro to extract the data role from register value */ +#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE(reg) (((reg) & TCPC_REG_MSG_HDR_INFO_DATA_ROLE_MASK) >> 3) +/** Value for data role set as UFP */ +#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_UFP 0 +/** Value for data role set as DFP */ +#define TCPC_REG_MSG_HDR_INFO_DATA_ROLE_DFP 1 +/** Mask for Power Delivery Specification Revision */ +#define TCPC_REG_MSG_HDR_INFO_PD_REV_MASK GENMASK(2, 1) +/** Macro to extract the Power Delivery Specification Revision from register value */ +#define TCPC_REG_MSG_HDR_INFO_PD_REV(reg) (((reg) & TCPC_REG_MSG_HDR_INFO_PD_REV_MASK) >> 1) +/** Value for Power Delivery Specification Revision 1.0 */ +#define TCPC_REG_MSG_HDR_INFO_PD_REV_1_0 0 +/** Value for Power Delivery Specification Revision 2.0 */ +#define TCPC_REG_MSG_HDR_INFO_PD_REV_2_0 1 +/** Value for Power Delivery Specification Revision 3.0 */ +#define TCPC_REG_MSG_HDR_INFO_PD_REV_3_0 2 +/** Mask for power role */ +#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK BIT(0) +/** Macro to extract the power role from register value */ +#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE(reg) ((reg) & TCPC_REG_MSG_HDR_INFO_POWER_ROLE_MASK) +/** Value for power role set as sink */ +#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SNK 0 +/** Value for power role set as source */ +#define TCPC_REG_MSG_HDR_INFO_POWER_ROLE_SRC 1 +/** + * Macro to set the register value with pd revision, data and power role from parameter and as + * non-cable plug + */ +#define TCPC_REG_MSG_HDR_INFO_SET(pd_rev_type, drole, prole) \ + ((drole) << 3 | (pd_rev_type << 1) | (prole)) +/** Mask for PD revision and power and data role */ +#define TCPC_REG_MSG_HDR_INFO_ROLES_MASK (TCPC_REG_MSG_HDR_INFO_SET(3, 1, 1)) + +/** Register address - receive detect */ +#define TCPC_REG_RX_DETECT 0x2f +/** + * Bit for message disable disconnect. + * If set, the TCPC set as sink shall disable the PD message delivery when the SNK.Open state + * is detected for debounce time specified in specification. + * If unset, sink TCPC disables the PD message delivery when vbus sink disconnect detected in + * alert register is asserted. + */ +#define TCPC_REG_RX_DETECT_MSG_DISABLE_DISCONNECT BIT(7) +/** Bit for enable cable reset. If set, TCPC will detect the cable reset signal. */ +#define TCPC_REG_RX_DETECT_CABLE_RST BIT(6) +/** Bit for enable hard reset. If set, TCPC will detect the hard reset signal. */ +#define TCPC_REG_RX_DETECT_HRST BIT(5) +/** Bit for enable SOP_DBG'' message. If set, TCPC will detect the SOP_DBG'' messages. */ +#define TCPC_REG_RX_DETECT_SOPPP_DBG BIT(4) +/** Bit for enable SOP_DBG' message. If set, TCPC will detect the SOP_DBG' messages. */ +#define TCPC_REG_RX_DETECT_SOPP_DBG BIT(3) +/** Bit for enable SOP'' message. If set, TCPC will detect the SOP'' messages. */ +#define TCPC_REG_RX_DETECT_SOPPP BIT(2) +/** Bit for enable SOP' message. If set, TCPC will detect the SOP' messages. */ +#define TCPC_REG_RX_DETECT_SOPP BIT(1) +/** Bit for enable SOP message. If set, TCPC will detect the SOP messages. */ +#define TCPC_REG_RX_DETECT_SOP BIT(0) +/** Mask for detecting the SOP messages and hard reset signals */ +#define TCPC_REG_RX_DETECT_SOP_HRST_MASK (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_HRST) +/** Mask for detecting the SOP, SOP' and SOP'' messages and hard reset signals */ +#define TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK \ + (TCPC_REG_RX_DETECT_SOP | TCPC_REG_RX_DETECT_SOPP | TCPC_REG_RX_DETECT_SOPPP | \ + TCPC_REG_RX_DETECT_HRST) + +/** + * Register address - receive buffer (readable byte count, rx buf frame type, rx buf byte x) + * In TCPC Rev 2.0, the RECEIVE_BUFFER is comprised of three sets of registers: + * READABLE_BYTE_COUNT, RX_BUF_FRAME_TYPE and RX_BUF_BYTE_x. These registers can + * only be accessed by reading at a common register address 30h. + */ +#define TCPC_REG_RX_BUFFER 0x30 + +/** Register address - transmit */ +#define TCPC_REG_TRANSMIT 0x50 +/** Macro to set the transmit register with message type and retries count */ +#define TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, type) ((retries) << 4 | (type)) +/** Macro to set the transmit register with message type and without retries */ +#define TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(type) (type) +/** Value for transmit SOP type message */ +#define TCPC_REG_TRANSMIT_TYPE_SOP 0 +/** Value for transmit SOP' type message */ +#define TCPC_REG_TRANSMIT_TYPE_SOPP 1 +/** Value for transmit SOP'' type message */ +#define TCPC_REG_TRANSMIT_TYPE_SOPPP 2 +/** Value for transmit SOP_DBG' type message */ +#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_P 3 +/** Value for transmit SOP_DBG'' type message */ +#define TCPC_REG_TRANSMIT_TYPE_SOP_DBG_PP 4 +/** Value for transmit hard reset signal */ +#define TCPC_REG_TRANSMIT_TYPE_HRST 5 +/** Value for transmit cable reset signal */ +#define TCPC_REG_TRANSMIT_TYPE_CABLE_RST 6 +/** Value for transmit BIST carrier mode 2 */ +#define TCPC_REG_TRANSMIT_TYPE_BIST 7 + +/** + * Register address - transmit buffer + * In TCPC Rev 2.0, the TRANSMIT_BUFFER holds the I2C_WRITE_BYTE_COUNT and the + * portion of the SOP* USB PD message payload (including the header and/or the + * data bytes) most recently written by the TCPM in TX_BUF_BYTE_x. TX_BUF_BYTE_x + * is “hidden” and can only be accessed by writing to register address 51h + */ +#define TCPC_REG_TX_BUFFER 0x51 + +/** Register address - vbus voltage */ +#define TCPC_REG_VBUS_VOLTAGE 0x70 +/** Mask for vbus voltage measurement */ +#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK GENMASK(9, 0) +/** Macro to extract the vbus measurement from the register value */ +#define TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(reg) ((reg) & TCPC_REG_VBUS_VOLTAGE_MEASUREMENT_MASK) +/** Mask for scale factor */ +#define TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK GENMASK(11, 10) +/** Macro to extract the vbus voltage scale from the register value */ +#define TCPC_REG_VBUS_VOLTAGE_SCALE(reg) \ + (1 << (((reg) & TCPC_REG_VBUS_VOLTAGE_SCALE_FACTOR_MASK) >> 10)) +/** Resolution of vbus voltage measurement. It's specified as 25mV. */ +#define TCPC_REG_VBUS_VOLTAGE_LSB 25 +/** + * Macro to convert the register value into real voltage measurement taking scale + * factor into account + */ +#define TCPC_REG_VBUS_VOLTAGE_VBUS(x) \ + (TCPC_REG_VBUS_VOLTAGE_SCALE(x) * TCPC_REG_VBUS_VOLTAGE_MEASUREMENT(x) * \ + TCPC_REG_VBUS_VOLTAGE_LSB) + +/** Register address - vbus sink disconnect threshold */ +#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH 0x72 +/** + * Resolution of the value stored in register. + * Value read from register must be multiplied by this value to get a real voltage in mV. + * Voltage in mV written to register must be divided by this constant. + * Specification defines it as 25mV + */ +#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_LSB 25 +/** Mask for the valid bits of voltage trip point */ +#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_MASK GENMASK(11, 0) +/** Default value for vbus sink disconnect threshold */ +#define TCPC_REG_VBUS_SINK_DISCONNECT_THRESH_DEFAULT 0x008C /* 3.5 V */ + +/** Register address - vbus sink disconnect threshold */ +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH 0x74 +/** + * Resolution of the value stored in register. + * Value read from register must be multiplied by this value to get a real voltage in mV. + * Voltage in mV written to register must be divided by this constant. + * Specification defines it as 25mV. + */ +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_LSB 25 +/** Mask for the valid bits of voltage trip point */ +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_MASK GENMASK(11, 0) +/** Default value for vbus stop discharge threshold */ +#define TCPC_REG_VBUS_STOP_DISCHARGE_THRESH_DEFAULT 0x0020 /* 0.8 V */ + +/** Register address - vbus voltage alarm - high */ +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +/** + * Resolution of the value stored in register. + * Value read from register must be multiplied by this value to get a real voltage in mV. + * Voltage in mV written to register must be divided by this constant. + * Specification defines it as 25mV + */ +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_LSB 25 +/** Mask for the valid bits of voltage trip point */ +#define TCPC_REG_VBUS_VOLTAGE_ALARM_HI_CFG_MASK GENMASK(11, 0) + +/** Register address - vbus voltage alarm - low */ +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 +/** + * Resolution of the value stored in register. + * Value read from register must be multiplied by this value to get a real voltage in mV. + * Voltage in mV written to register must be divided by this constant. + * Specification defines it as 25mV + */ +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_LSB 25 +/** Mask for the valid bits of voltage trip point */ +#define TCPC_REG_VBUS_VOLTAGE_ALARM_LO_CFG_MASK GENMASK(11, 0) + +/** + * Register address - vbus nondefault target + * Available only if vbus nondefault target is asserted in device capabilities 1 register. + * Purpose of this register is to provide value for nondefault voltage over vbus when sending + * the source vbus nondefault voltage command to command register. + */ +#define TCPC_REG_VBUS_NONDEFAULT_TARGET 0x7a +/** + * Resolution of the value stored in register. + * Value read from register must be multiplied by this value to get a real voltage in mV. + * Voltage in mV written to register must be divided by this constant. + * Specification defines it as 20mV + */ +#define TCPC_REG_VBUS_NONDEFAULT_TARGET_LSB 20 + +/** Register address - device capabilities 3 */ +#define TCPC_REG_DEV_CAP_3 0x7c +/** Mask for vbus voltage support */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK GENMASK(2, 0) +/** Macro to extract the vbus voltage support from register value */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX(reg) ((reg) & TCPC_REG_DEV_CAP_3_VBUS_MAX_MASK) +/** Value for nominal voltage supported of 5V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_5V 0 +/** Value for nominal voltage supported of 9V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_9V 1 +/** Value for nominal voltage supported of 15V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_15V 2 +/** Value for nominal voltage supported of 20V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_20V 3 +/** Value for nominal voltage supported of 28V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_28V 4 +/** Value for nominal voltage supported of 36V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_36V 5 +/** Value for nominal voltage supported of 48V */ +#define TCPC_REG_DEV_CAP_3_VBUS_MAX_48V 6 + +#endif /* ZEPHYR_INCLUDE_USB_C_TCPCI_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/grant_table.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/grant_table.h index 55162391..0124046d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/grant_table.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/grant_table.h @@ -126,7 +126,7 @@ typedef uint32_t grant_ref_t; * Version 1 of the grant table entry structure is maintained purely * for backwards compatibility. New guests should use version 2. */ -#if __XEN_INTERFACE_VERSION__ < 0x0003020a +#if CONFIG_XEN_INTERFACE_VERSION < 0x0003020a #define grant_entry_v1 grant_entry #define grant_entry_v1_t grant_entry_t #endif @@ -232,13 +232,13 @@ typedef struct grant_entry_v1 grant_entry_v1_t; #define GNTTABOP_copy 5 #define GNTTABOP_query_size 6 #define GNTTABOP_unmap_and_replace 7 -#if __XEN_INTERFACE_VERSION__ >= 0x0003020a +#if CONFIG_XEN_INTERFACE_VERSION >= 0x0003020a #define GNTTABOP_set_version 8 #define GNTTABOP_get_status_frames 9 #define GNTTABOP_get_version 10 #define GNTTABOP_swap_grant_ref 11 #define GNTTABOP_cache_flush 12 -#endif /* __XEN_INTERFACE_VERSION__ */ +#endif /* CONFIG_XEN_INTERFACE_VERSION */ /* ` } */ /* @@ -315,7 +315,7 @@ struct gnttab_setup_table { /* OUT parameters. */ int16_t status; /* => enum grant_status */ -#if __XEN_INTERFACE_VERSION__ < 0x00040300 +#if CONFIG_XEN_INTERFACE_VERSION < 0x00040300 XEN_GUEST_HANDLE(ulong) frame_list; #else XEN_GUEST_HANDLE(xen_pfn_t) frame_list; diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/memory.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/memory.h index 513b3273..2baf69ef 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/memory.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/memory.h @@ -53,7 +53,7 @@ struct xen_memory_reservation { xen_ulong_t nr_extents; unsigned int extent_order; -#if __XEN_INTERFACE_VERSION__ >= 0x00030209 +#if CONFIG_XEN_INTERFACE_VERSION >= 0x00030209 /* XENMEMF flags. */ unsigned int mem_flags; #else @@ -80,7 +80,7 @@ struct xen_add_to_physmap_batch { /* Number of pages to go through */ uint16_t size; -#if __XEN_INTERFACE_VERSION__ < 0x00040700 +#if CONFIG_XEN_INTERFACE_VERSION < 0x00040700 domid_t foreign_domid; /* IFF gmfn_foreign. Should be 0 for other spaces. */ #else union xen_add_to_physmap_batch_extra { diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/xen.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/xen.h index f8a5b6eb..3018a92d 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/xen.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/xen/public/xen.h @@ -41,7 +41,7 @@ DEFINE_XEN_GUEST_HANDLE(char); __DEFINE_XEN_GUEST_HANDLE(uchar, unsigned char); DEFINE_XEN_GUEST_HANDLE(int); __DEFINE_XEN_GUEST_HANDLE(uint, unsigned int); -#if __XEN_INTERFACE_VERSION__ < 0x00040300 +#if CONFIG_XEN_INTERFACE_VERSION < 0x00040300 DEFINE_XEN_GUEST_HANDLE(long); __DEFINE_XEN_GUEST_HANDLE(ulong, unsigned long); #endif @@ -216,7 +216,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_ulong_t); typedef uint16_t domid_t; -#if __XEN_INTERFACE_VERSION__ < 0x00040400 +#if CONFIG_XEN_INTERFACE_VERSION < 0x00040400 /* * Event channel endpoints per domain (when using the 2-level ABI): * 1024 if a long is 32 bits; 4096 if a long is 64 bits. @@ -248,7 +248,7 @@ struct vcpu_time_info { */ uint32_t tsc_to_system_mul; int8_t tsc_shift; -#if __XEN_INTERFACE_VERSION__ > 0x040600 +#if CONFIG_XEN_INTERFACE_VERSION > 0x040600 uint8_t flags; uint8_t pad1[2]; #else diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/zbus/zbus.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/zbus/zbus.h index 40774da5..e5657c0a 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/zbus/zbus.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/include/zephyr/zbus/zbus.h @@ -62,6 +62,13 @@ struct zbus_channel_data { */ struct net_buf_pool *msg_subscriber_pool; #endif /* ZBUS_MSG_SUBSCRIBER_NET_BUF_POOL_ISOLATION */ + +#if defined(CONFIG_ZBUS_CHANNEL_PUBLISH_STATS) || defined(__DOXYGEN__) + /** Kernel timestamp of the last publish action on this channel */ + k_ticks_t publish_timestamp; + /** Number of times data has been published to this channel */ + uint32_t publish_count; +#endif /* CONFIG_ZBUS_CHANNEL_PUBLISH_STATS */ }; /** @@ -73,29 +80,29 @@ struct zbus_channel_data { struct zbus_channel { #if defined(CONFIG_ZBUS_CHANNEL_NAME) || defined(__DOXYGEN__) /** Channel name. */ - const char *const name; + const char *name; #endif /** Message reference. Represents the message's reference that points to the actual * shared memory region. */ - void *const message; + void *message; /** Message size. Represents the channel's message size. */ - const size_t message_size; + size_t message_size; /** User data available to extend zbus features. The channel must be claimed before * using this field. */ - void *const user_data; + void *user_data; /** Message validator. Stores the reference to the function to check the message * validity before actually performing the publishing. No invalid messages can be * published. Every message is valid when this field is empty. */ - bool (*const validator)(const void *msg, size_t msg_size); + bool (*validator)(const void *msg, size_t msg_size); /** Mutable channel data struct. */ - struct zbus_channel_data *const data; + struct zbus_channel_data *data; }; /** @@ -137,26 +144,26 @@ struct zbus_observer_data { struct zbus_observer { #if defined(CONFIG_ZBUS_OBSERVER_NAME) || defined(__DOXYGEN__) /** Observer name. */ - const char *const name; + const char *name; #endif /** Type indication. */ enum zbus_observer_type type; /** Mutable observer data struct. */ - struct zbus_observer_data *const data; + struct zbus_observer_data *data; union { /** Observer message queue. It turns the observer into a subscriber. */ - struct k_msgq *const queue; + struct k_msgq *queue; /** Observer callback function. It turns the observer into a listener. */ - void (*const callback)(const struct zbus_channel *chan); + void (*callback)(const struct zbus_channel *chan); #if defined(CONFIG_ZBUS_MSG_SUBSCRIBER) || defined(__DOXYGEN__) /** Observer message FIFO. It turns the observer into a message subscriber. It only * exists if the @kconfig{CONFIG_ZBUS_MSG_SUBSCRIBER} is enabled. */ - struct k_fifo *const message_fifo; + struct k_fifo *message_fifo; #endif /* CONFIG_ZBUS_MSG_SUBSCRIBER */ }; }; @@ -167,8 +174,8 @@ struct zbus_channel_observation_mask { }; struct zbus_channel_observation { - const struct zbus_channel *const chan; - const struct zbus_observer *const obs; + const struct zbus_channel *chan; + const struct zbus_observer *obs; }; #ifdef __cplusplus @@ -217,7 +224,7 @@ struct zbus_channel_observation { #define ZBUS_RUNTIME_OBSERVERS_LIST_INIT(_slist_name) /* No runtime observers */ #endif -#define _ZBUS_OBS_EXTERN(_name) extern struct zbus_observer _name +#define _ZBUS_OBS_EXTERN(_name) extern const struct zbus_observer _name #define _ZBUS_CHAN_EXTERN(_name) extern const struct zbus_channel _name @@ -259,8 +266,9 @@ struct zbus_channel_observation { /** @endcond */ /* clang-format off */ + /** - * @brief Add a static channel observervation. + * @brief Add a static channel observation. * * This macro initializes a channel observation by receiving the * channel and the observer. @@ -282,7 +290,7 @@ struct zbus_channel_observation { /* clang-format on */ /** - * @brief Add a static channel observervation. + * @brief Add a static channel observation. * * This macro initializes a channel observation by receiving the * channel and the observer. @@ -321,6 +329,7 @@ struct zbus_channel_observation { #define ZBUS_OBSERVERS(...) __VA_ARGS__ /* clang-format off */ + /** * @brief Zbus channel definition. * @@ -342,13 +351,13 @@ struct zbus_channel_observation { .observers_start_idx = -1, \ .observers_end_idx = -1, \ .sem = Z_SEM_INITIALIZER(_CONCAT(_zbus_chan_data_, _name).sem, 1, 1), \ + IF_ENABLED(CONFIG_ZBUS_PRIORITY_BOOST, ( \ + .highest_observer_priority = ZBUS_MIN_THREAD_PRIORITY, \ + )) \ IF_ENABLED(CONFIG_ZBUS_RUNTIME_OBSERVERS, ( \ .observers = SYS_SLIST_STATIC_INIT( \ &_CONCAT(_zbus_chan_data_, _name).observers), \ )) \ - IF_ENABLED(CONFIG_ZBUS_PRIORITY_BOOST, ( \ - .highest_observer_priority = ZBUS_MIN_THREAD_PRIORITY, \ - )) \ }; \ static K_MUTEX_DEFINE(_CONCAT(_zbus_mutex_, _name)); \ _ZBUS_CPP_EXTERN const STRUCT_SECTION_ITERABLE(zbus_channel, _name) = { \ @@ -383,6 +392,7 @@ struct zbus_channel_observation { } /* clang-format off */ + /** * @brief Define and initialize a subscriber. * @@ -396,8 +406,8 @@ struct zbus_channel_observation { */ #define ZBUS_SUBSCRIBER_DEFINE_WITH_ENABLE(_name, _queue_size, _enable) \ K_MSGQ_DEFINE(_zbus_observer_queue_##_name, \ - sizeof(const struct zbus_channel *), \ - _queue_size, sizeof(const struct zbus_channel *) \ + sizeof(struct zbus_channel *), \ + _queue_size, sizeof(struct zbus_channel *) \ ); \ static struct zbus_observer_data _CONCAT(_zbus_obs_data_, _name) = { \ .enabled = _enable, \ @@ -405,7 +415,7 @@ struct zbus_channel_observation { .priority = ZBUS_MIN_THREAD_PRIORITY, \ )) \ }; \ - STRUCT_SECTION_ITERABLE(zbus_observer, _name) = { \ + _ZBUS_CPP_EXTERN const STRUCT_SECTION_ITERABLE(zbus_observer, _name) = { \ ZBUS_OBSERVER_NAME_INIT(_name) /* Name field */ \ .type = ZBUS_OBSERVER_SUBSCRIBER_TYPE, \ .data = &_CONCAT(_zbus_obs_data_, _name), \ @@ -428,6 +438,7 @@ struct zbus_channel_observation { ZBUS_SUBSCRIBER_DEFINE_WITH_ENABLE(_name, _queue_size, true) /* clang-format off */ + /** * @brief Define and initialize a listener. * @@ -446,7 +457,7 @@ struct zbus_channel_observation { .priority = ZBUS_MIN_THREAD_PRIORITY, \ )) \ }; \ - STRUCT_SECTION_ITERABLE(zbus_observer, _name) = { \ + _ZBUS_CPP_EXTERN const STRUCT_SECTION_ITERABLE(zbus_observer, _name) = { \ ZBUS_OBSERVER_NAME_INIT(_name) /* Name field */ \ .type = ZBUS_OBSERVER_LISTENER_TYPE, \ .data = &_CONCAT(_zbus_obs_data_, _name), \ @@ -467,6 +478,7 @@ struct zbus_channel_observation { #define ZBUS_LISTENER_DEFINE(_name, _cb) ZBUS_LISTENER_DEFINE_WITH_ENABLE(_name, _cb, true) /* clang-format off */ + /** * @brief Define and initialize a message subscriber. * @@ -485,7 +497,7 @@ struct zbus_channel_observation { .priority = ZBUS_MIN_THREAD_PRIORITY, \ )) \ }; \ - STRUCT_SECTION_ITERABLE(zbus_observer, _name) = { \ + _ZBUS_CPP_EXTERN const STRUCT_SECTION_ITERABLE(zbus_observer, _name) = { \ ZBUS_OBSERVER_NAME_INIT(_name) /* Name field */ \ .type = ZBUS_OBSERVER_MSG_SUBSCRIBER_TYPE, \ .data = &_CONCAT(_zbus_obs_data_, _name), \ @@ -717,6 +729,89 @@ static inline void zbus_chan_set_msg_sub_pool(const struct zbus_channel *chan, #endif /* ZBUS_MSG_SUBSCRIBER_NET_BUF_POOL_ISOLATION */ +#if defined(CONFIG_ZBUS_CHANNEL_PUBLISH_STATS) || defined(__DOXYGEN__) + +/** + * @brief Update the publishing statistics for a channel + * + * This function updates the publishing statistics for the @ref zbus_chan_claim -> + * @ref zbus_chan_finish workflow, which cannot automatically determine whether + * new data has been published or not. + * + * @warning This function must only be used directly for already locked channels. + * + * @param chan The channel's reference. + */ +static inline void zbus_chan_pub_stats_update(const struct zbus_channel *chan) +{ + __ASSERT(chan != NULL, "chan is required"); + + chan->data->publish_timestamp = k_uptime_ticks(); + chan->data->publish_count += 1; +} + +/** + * @brief Get the time a channel was last published to. + * + * @note Will return 0 if channel has not yet been published to. + * + * @param chan The channel's reference. + * + * @return The kernel timestamp of the last publishing action. + */ +static inline k_ticks_t zbus_chan_pub_stats_last_time(const struct zbus_channel *chan) +{ + __ASSERT(chan != NULL, "chan is required"); + + return chan->data->publish_timestamp; +} + +/** + * @brief Get the number of times a channel has been published to. + * + * @note Will return 0 if channel has not yet been published to. + * + * @param chan The channel's reference. + * + * @return The number of times a channel has been published to. + */ +static inline uint32_t zbus_chan_pub_stats_count(const struct zbus_channel *chan) +{ + __ASSERT(chan != NULL, "chan is required"); + + return chan->data->publish_count; +} + +/** + * @brief Get the average period between publishes to a channel. + * + * @note Will return 0 if channel has not yet been published to. + * + * @param chan The channel's reference. + * + * @return Average duration in milliseconds between publishes. + */ +static inline uint32_t zbus_chan_pub_stats_avg_period(const struct zbus_channel *chan) +{ + __ASSERT(chan != NULL, "chan is required"); + + /* Not yet published, period = 0ms */ + if (chan->data->publish_count == 0) { + return 0; + } + /* Average period across application runtime */ + return k_uptime_get() / chan->data->publish_count; +} + +#else + +static inline void zbus_chan_pub_stats_update(const struct zbus_channel *chan) +{ + (void)chan; +} + +#endif /* CONFIG_ZBUS_CHANNEL_PUBLISH_STATS */ + #if defined(CONFIG_ZBUS_RUNTIME_OBSERVERS) || defined(__DOXYGEN__) /** @@ -782,7 +877,7 @@ struct zbus_observer_node { * @retval -EFAULT A parameter is incorrect, or the function context is invalid (inside an ISR). The * function only returns this value when the @kconfig{CONFIG_ZBUS_ASSERT_MOCK} is enabled. */ -int zbus_obs_set_enable(struct zbus_observer *obs, bool enabled); +int zbus_obs_set_enable(const struct zbus_observer *obs, bool enabled); /** * @brief Get the observer state. @@ -794,7 +889,7 @@ int zbus_obs_set_enable(struct zbus_observer *obs, bool enabled); * * @return Observer state. */ -static inline int zbus_obs_is_enabled(struct zbus_observer *obs, bool *enable) +static inline int zbus_obs_is_enabled(const struct zbus_observer *obs, bool *enable) { _ZBUS_ASSERT(obs != NULL, "obs is required"); _ZBUS_ASSERT(enable != NULL, "enable is required"); diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/modules/cmsis/cmsis_core_a_r.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/modules/cmsis/cmsis_core_a_r.h index 9f4514ed..bef0f602 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/modules/cmsis/cmsis_core_a_r.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/modules/cmsis/cmsis_core_a_r.h @@ -46,6 +46,8 @@ extern "C" { #include #elif defined(CONFIG_CPU_CORTEX_R7) #include +#elif defined(CONFIG_CPU_CORTEX_R8) +#include #elif defined(CONFIG_CPU_CORTEX_R52) #include #elif defined(CONFIG_CPU_AARCH32_CORTEX_A) diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32u0x/soc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32u0x/soc.h new file mode 100644 index 00000000..48261403 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32u0x/soc.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32U0 family processors. + * + */ + + +#ifndef _STM32U0_SOC_H_ +#define _STM32U0_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32U0_SOC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wb0x/soc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wb0x/soc.h new file mode 100644 index 00000000..8361f725 --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wb0x/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2024 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the STM32WB0 family processors. + * + */ + + +#ifndef _STM32WB0_SOC_H_ +#define _STM32WB0_SOC_H_ + +#ifndef _ASMLANGUAGE + +#include + +/** SMPS modes */ +#define STM32WB0_SMPS_MODE_OFF 0 +#define STM32WB0_SMPS_MODE_PRECHARGE 1 +#define STM32WB0_SMPS_MODE_RUN 2 + +/** Active SMPS mode (provided here for usage in drivers) */ +#define SMPS_MODE _CONCAT(STM32WB0_SMPS_MODE_, \ + DT_STRING_UNQUOTED( \ + DT_INST(0, st_stm32wb0_pwr), \ + smps_mode)) + +#endif /* !_ASMLANGUAGE */ + +#endif /* _STM32WB0_SOC_H_ */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wbax/soc.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wbax/soc.h index 0c337ea9..be7e08e7 100644 --- a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wbax/soc.h +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/soc/st/stm32/stm32wbax/soc.h @@ -17,8 +17,11 @@ #include + /* function exported to the soc power.c */ -int stm32wba_init(void); +void stm32wba_init(void); + +void stm32_power_init(void); #endif /* !_ASMLANGUAGE */ diff --git a/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/subsys/shell/modules/kernel_service/kernel_shell.h b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/subsys/shell/modules/kernel_service/kernel_shell.h new file mode 100644 index 00000000..ca0523ad --- /dev/null +++ b/variants/arduino_giga_r1_m7/llext-edk/include/zephyr/subsys/shell/modules/kernel_service/kernel_shell.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_SHELL_MODULES_KERNEL_SERVICE_KERNEL_SHELL_H_ +#define ZEPHYR_SUBSYS_SHELL_MODULES_KERNEL_SERVICE_KERNEL_SHELL_H_ + +#include + +/* Add command to the set of kernel subcommands, see `SHELL_SUBCMD_ADD` */ +#define KERNEL_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, _mand, _opt) \ + SHELL_SUBCMD_ADD((kernel), _syntax, _subcmd, _help, _handler, _mand, _opt); + +#define KERNEL_CMD_ADD(_syntax, _subcmd, _help, _handler) \ + KERNEL_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, 0, 0); + +/* Add command to the set of `kernel thread` subcommands */ +#define KERNEL_THREAD_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, _mand, _opt) \ + SHELL_SUBCMD_ADD((thread), _syntax, _subcmd, _help, _handler, _mand, _opt); + +#define KERNEL_THREAD_CMD_ADD(_syntax, _subcmd, _help, _handler) \ + KERNEL_THREAD_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, 0, 0); + +/* Internal function to check if a thread pointer is valid */ +bool z_thread_is_valid(const struct k_thread *thread); + +#endif /* ZEPHYR_SUBSYS_SHELL_MODULES_KERNEL_SERVICE_KERNEL_SHELL_H_ */ diff --git a/variants/arduino_nano_33_ble_sense/llext-edk/include/zephyr/subsys/bluetooth/host/classic/at.h b/variants/arduino_nano_33_ble_sense/llext-edk/include/zephyr/subsys/bluetooth/host/classic/at.h index ae2c7f95..b9059626 100644 --- a/variants/arduino_nano_33_ble_sense/llext-edk/include/zephyr/subsys/bluetooth/host/classic/at.h +++ b/variants/arduino_nano_33_ble_sense/llext-edk/include/zephyr/subsys/bluetooth/host/classic/at.h @@ -15,7 +15,7 @@ enum at_result { }; enum at_cme { - CME_ERROR_AG_FAILURE = 0, + CME_ERPOR_AG_FAILURE = 0, CME_ERROR_NO_CONNECTION_TO_PHONE = 1, CME_ERROR_OPERATION_NOT_ALLOWED = 3, CME_ERROR_OPERATION_NOT_SUPPORTED = 4,

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