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34 | 34 | #define CONFIG_FLASH_FILL_BUFFER_SIZE 32
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35 | 35 | #define CONFIG_GPIO 1
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36 | 36 | #define CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS 1
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| 37 | +#define CONFIG_MEMC 1 |
37 | 38 | #define CONFIG_KERNEL_ENTRY "__start"
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38 | 39 | #define CONFIG_CACHE 1
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39 | 40 | #define CONFIG_DCACHE 1
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71 | 72 | #define CONFIG_DT_HAS_GPIO_LEDS_ENABLED 1
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72 | 73 | #define CONFIG_DT_HAS_INFINEON_CYW43XXX_BT_HCI_ENABLED 1
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73 | 74 | #define CONFIG_DT_HAS_MMIO_SRAM_ENABLED 1
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| 75 | +#define CONFIG_DT_HAS_OVTI_OV7670_ENABLED 1 |
| 76 | +#define CONFIG_DT_HAS_PWM_CLOCK_ENABLED 1 |
74 | 77 | #define CONFIG_DT_HAS_SOC_NV_FLASH_ENABLED 1
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75 | 78 | #define CONFIG_DT_HAS_ST_MBOX_STM32_HSEM_ENABLED 1
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76 | 79 | #define CONFIG_DT_HAS_ST_STM32_ADC_ENABLED 1
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77 | 80 | #define CONFIG_DT_HAS_ST_STM32_DAC_ENABLED 1
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| 81 | +#define CONFIG_DT_HAS_ST_STM32_DCMI_ENABLED 1 |
| 82 | +#define CONFIG_DT_HAS_ST_STM32_DMA_V1_ENABLED 1 |
| 83 | +#define CONFIG_DT_HAS_ST_STM32_DMAMUX_ENABLED 1 |
78 | 84 | #define CONFIG_DT_HAS_ST_STM32_EXTI_ENABLED 1
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79 | 85 | #define CONFIG_DT_HAS_ST_STM32_FLASH_CONTROLLER_ENABLED 1
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80 | 86 | #define CONFIG_DT_HAS_ST_STM32_FMC_SDRAM_ENABLED 1
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86 | 92 | #define CONFIG_DT_HAS_ST_STM32_NV_FLASH_ENABLED 1
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87 | 93 | #define CONFIG_DT_HAS_ST_STM32_OTGFS_ENABLED 1
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88 | 94 | #define CONFIG_DT_HAS_ST_STM32_PINCTRL_ENABLED 1
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| 95 | +#define CONFIG_DT_HAS_ST_STM32_PWM_ENABLED 1 |
89 | 96 | #define CONFIG_DT_HAS_ST_STM32_QSPI_ENABLED 1
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90 | 97 | #define CONFIG_DT_HAS_ST_STM32_QSPI_NOR_ENABLED 1
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91 | 98 | #define CONFIG_DT_HAS_ST_STM32_RCC_RCTL_ENABLED 1
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92 | 99 | #define CONFIG_DT_HAS_ST_STM32_RNG_ENABLED 1
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93 | 100 | #define CONFIG_DT_HAS_ST_STM32_SPI_ENABLED 1
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94 | 101 | #define CONFIG_DT_HAS_ST_STM32_SPI_FIFO_ENABLED 1
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| 102 | +#define CONFIG_DT_HAS_ST_STM32_TIMERS_ENABLED 1 |
95 | 103 | #define CONFIG_DT_HAS_ST_STM32_UART_ENABLED 1
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96 | 104 | #define CONFIG_DT_HAS_ST_STM32_USART_ENABLED 1
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97 | 105 | #define CONFIG_DT_HAS_ST_STM32H7_FDCAN_ENABLED 1
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101 | 109 | #define CONFIG_DT_HAS_ST_STM32H7_RCC_ENABLED 1
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102 | 110 | #define CONFIG_DT_HAS_ST_STM32H7_SPI_ENABLED 1
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103 | 111 | #define CONFIG_DT_HAS_USB_NOP_XCEIV_ENABLED 1
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| 112 | +#define CONFIG_DT_HAS_VND_GPIO_ENABLED 1 |
104 | 113 | #define CONFIG_DT_HAS_ZEPHYR_BT_HCI_UART_ENABLED 1
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105 | 114 | #define CONFIG_DT_HAS_ZEPHYR_CDC_ACM_UART_ENABLED 1
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106 | 115 | #define CONFIG_DT_HAS_ZEPHYR_MEMORY_REGION_ENABLED 1
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129 | 138 | #define CONFIG_USE_STM32_HAL_PCD 1
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130 | 139 | #define CONFIG_USE_STM32_HAL_PCD_EX 1
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131 | 140 | #define CONFIG_USE_STM32_HAL_QSPI 1
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| 141 | +#define CONFIG_USE_STM32_HAL_SDRAM 1 |
| 142 | +#define CONFIG_USE_STM32_LL_DMA 1 |
| 143 | +#define CONFIG_USE_STM32_LL_FMC 1 |
132 | 144 | #define CONFIG_USE_STM32_LL_I2C 1
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133 | 145 | #define CONFIG_USE_STM32_LL_RCC 1
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134 | 146 | #define CONFIG_USE_STM32_LL_SPI 1
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| 147 | +#define CONFIG_USE_STM32_LL_TIM 1 |
135 | 148 | #define CONFIG_USE_STM32_LL_USB 1
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136 | 149 | #define CONFIG_USE_STM32_LL_UTILS 1
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137 | 150 | #define CONFIG_BOARD "arduino_giga_r1"
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262 | 275 | #define CONFIG_CLOCK_STM32_HSE_CLOCK 16000000
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263 | 276 | #define CONFIG_CLOCK_STM32_MCO1_SRC_NOCLOCK 1
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264 | 277 | #define CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK 1
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| 278 | +#define CONFIG_CLOCK_CONTROL_PWM 1 |
| 279 | +#define CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY 51 |
265 | 280 | #define CONFIG_CONSOLE_INPUT_MAX_LINE_LEN 128
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266 | 281 | #define CONFIG_CONSOLE_HAS_DRIVER 1
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267 | 282 | #define CONFIG_CONSOLE_INIT_PRIORITY 60
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268 | 283 | #define CONFIG_UART_CONSOLE 1
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269 | 284 | #define CONFIG_UART_CONSOLE_LOG_LEVEL_DEFAULT 1
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270 | 285 | #define CONFIG_UART_CONSOLE_LOG_LEVEL 3
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| 286 | +#define CONFIG_DMA 1 |
| 287 | +#define CONFIG_DMA_INIT_PRIORITY 40 |
| 288 | +#define CONFIG_DMA_LOG_LEVEL_DEFAULT 1 |
| 289 | +#define CONFIG_DMA_LOG_LEVEL 3 |
| 290 | +#define CONFIG_DMA_STM32 1 |
| 291 | +#define CONFIG_DMA_STM32_V1 1 |
| 292 | +#define CONFIG_DMAMUX_STM32 1 |
| 293 | +#define CONFIG_DMAMUX_STM32_INIT_PRIORITY 41 |
271 | 294 | #define CONFIG_FLASH_HAS_DRIVER_ENABLED 1
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272 | 295 | #define CONFIG_FLASH_HAS_EXPLICIT_ERASE 1
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273 | 296 | #define CONFIG_FLASH_HAS_PAGE_LAYOUT 1
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280 | 303 | #define CONFIG_GPIO_LOG_LEVEL_DEFAULT 1
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281 | 304 | #define CONFIG_GPIO_LOG_LEVEL 3
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282 | 305 | #define CONFIG_GPIO_STM32 1
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| 306 | +#define CONFIG_GPIO_TEST 1 |
283 | 307 | #define CONFIG_HWINFO 1
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284 | 308 | #define CONFIG_HWINFO_LOG_LEVEL_DEFAULT 1
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285 | 309 | #define CONFIG_HWINFO_LOG_LEVEL 3
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294 | 318 | #define CONFIG_INTC_LOG_LEVEL_DEFAULT 1
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295 | 319 | #define CONFIG_INTC_LOG_LEVEL 3
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296 | 320 | #define CONFIG_EXTI_STM32 1
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| 321 | +#define CONFIG_MEMC_LOG_LEVEL_DEFAULT 1 |
| 322 | +#define CONFIG_MEMC_LOG_LEVEL 3 |
| 323 | +#define CONFIG_MEMC_INIT_PRIORITY 0 |
| 324 | +#define CONFIG_MEMC_STM32 1 |
| 325 | +#define CONFIG_MEMC_STM32_SDRAM 1 |
297 | 326 | #define CONFIG_PINCTRL_LOG_LEVEL_DEFAULT 1
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298 | 327 | #define CONFIG_PINCTRL_LOG_LEVEL 3
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299 | 328 | #define CONFIG_PINCTRL_STM32 1
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302 | 331 | #define CONFIG_PWM_LOG_LEVEL_DEFAULT 1
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303 | 332 | #define CONFIG_PWM_LOG_LEVEL 3
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304 | 333 | #define CONFIG_PWM_INIT_PRIORITY 50
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| 334 | +#define CONFIG_PWM_STM32 1 |
305 | 335 | #define CONFIG_RESET_INIT_PRIORITY 35
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306 | 336 | #define CONFIG_RESET_STM32 1
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307 | 337 | #define CONFIG_SERIAL_HAS_DRIVER 1
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| 338 | +#define CONFIG_SERIAL_SUPPORT_ASYNC 1 |
308 | 339 | #define CONFIG_SERIAL_SUPPORT_INTERRUPT 1
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309 | 340 | #define CONFIG_UART_LOG_LEVEL_DEFAULT 1
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310 | 341 | #define CONFIG_UART_LOG_LEVEL 3
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508 | 539 | #define CONFIG_BUILD_OUTPUT_STRIP_PATHS 1
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509 | 540 | #define CONFIG_CHECK_INIT_PRIORITIES 1
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510 | 541 | #define CONFIG_WARN_DEPRECATED 1
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| 542 | +#define CONFIG_EXPERIMENTAL 1 |
511 | 543 | #define CONFIG_ENFORCE_ZEPHYR_STDINT 1
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512 | 544 | #define CONFIG_LEGACY_GENERATED_INCLUDE_PATH 1
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