@@ -58,12 +58,14 @@ void UART::WrapperCallback(uart_callback_args_t *p_args) {
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{
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break ;
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}
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- case UART_EVENT_TX_COMPLETE:
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- case UART_EVENT_TX_DATA_EMPTY:
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+ case UART_EVENT_TX_COMPLETE: // This is call when the transmission is complete
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{
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- // uint8_t to_enqueue = uart_ptr->txBuffer.available() < uart_ptr->uart_ctrl.fifo_depth ? uart_ptr->txBuffer.available() : uart_ptr->uart_ctrl.fifo_depth;
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- // while (to_enqueue) {
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- uart_ptr->tx_done = true ;
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+ uart_ptr->tx_complete = true ;
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+ break ;
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+ }
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+ case UART_EVENT_TX_DATA_EMPTY: // This is called when the buffer is empty
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+ { // Last byte is transmitting, but ready for more data
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+ uart_ptr->tx_empty = true ;
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break ;
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}
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case UART_EVENT_RX_CHAR:
@@ -109,9 +111,10 @@ bool UART::setUpUartIrqs(uart_cfg_t &cfg) {
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size_t UART::write (uint8_t c) {
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/* -------------------------------------------------------------------------- */
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if (init_ok) {
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- tx_done = false ;
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+ tx_empty = false ;
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+ tx_complete = false ;
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R_SCI_UART_Write (&uart_ctrl, &c, 1 );
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- while (!tx_done ) {}
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+ while (!tx_empty ) {}
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return 1 ;
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}
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else {
@@ -121,9 +124,10 @@ size_t UART::write(uint8_t c) {
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size_t UART::write (uint8_t * c, size_t len) {
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if (init_ok) {
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- tx_done = false ;
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+ tx_empty = false ;
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+ tx_complete = false ;
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R_SCI_UART_Write (&uart_ctrl, c, len);
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- while (!tx_done ) {}
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+ while (!tx_empty ) {}
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return len;
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}
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else {
@@ -322,7 +326,7 @@ int UART::read() {
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/* -------------------------------------------------------------------------- */
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void UART::flush () {
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/* -------------------------------------------------------------------------- */
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- while (txBuffer. available () );
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+ while (!tx_complete );
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}
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/* -------------------------------------------------------------------------- */
@@ -335,4 +339,4 @@ size_t UART::write_raw(uint8_t* c, size_t len) {
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i++;
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}
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return len;
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- }
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+ }
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