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Update Himax driver.
* Fix default registers. * Set default registers on reset/boot.
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‎libraries/Himax_HM01B0/himax.cpp

Lines changed: 94 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -77,93 +77,94 @@ memory mounted on GAPUINO board.
7777
/** @defgroup GAPUINO_HIMAX_Private_Variables I2C Private Variables
7878
* @{
7979
*/
80+
#define HIMAX_LINE_LEN_PCK 0x172
81+
#define HIMAX_FRAME_LENGTH 0x232
82+
8083
static regval_list_t himax_default_regs[] = {
81-
{BLC_TGT, 0x08}, // BLC target :8 at 8 bit mode
82-
{BLC2_TGT, 0x08}, // BLI target :8 at 8 bit mode
83-
{0x3044, 0x0A}, // Increase CDS time for settling
84-
{0x3045, 0x00}, // Make symetric for cds_tg and rst_tg
85-
{0x3047, 0x0A}, // Increase CDS time for settling
86-
{0x3050, 0xC0}, // Make negative offset up to 4x
87-
{0x3051, 0x42},
88-
{0x3052, 0x50},
89-
{0x3053, 0x00},
90-
{0x3054, 0x03}, // tuning sf sig clamping as lowest
91-
{0x3055, 0xF7}, // tuning dsun
92-
{0x3056, 0xF8}, // increase adc nonoverlap clk
93-
{0x3057, 0x29}, // increase adc pwr for missing code
94-
{0x3058, 0x1F}, // turn on dsun
95-
{0x3059, 0x1E},
96-
{0x3064, 0x00},
97-
{0x3065, 0x04}, // pad pull 0
98-
99-
{BLC_CFG, 0x43}, // BLC_on, IIR
100-
101-
{0x1001, 0x43}, // BLC dithering en
102-
{0x1002, 0x43}, // blc_darkpixel_thd
103-
{0x0350, 0x00}, // Dgain Control
104-
{BLI_EN, 0x01}, // BLI enable
105-
{0x1003, 0x00}, // BLI Target [Def: 0x20]
106-
107-
{DPC_CTRL, 0x01}, // DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2
108-
{0x1009, 0xA0}, // cluster hot pixel th
109-
{0x100A, 0x60}, // cluster cold pixel th
110-
{SINGLE_THR_HOT, 0x90}, // single hot pixel th
111-
{SINGLE_THR_COLD, 0x40}, // single cold pixel th
112-
{0x1012, 0x00}, // Sync. shift disable
113-
{0x2000, 0x07},
114-
{0x2003, 0x00},
115-
{0x2004, 0x1C},
116-
{0x2007, 0x00},
117-
{0x2008, 0x58},
118-
{0x200B, 0x00},
119-
{0x200C, 0x7A},
120-
{0x200F, 0x00},
121-
{0x2010, 0xB8},
122-
{0x2013, 0x00},
123-
{0x2014, 0x58},
124-
{0x2017, 0x00},
125-
{0x2018, 0x9B},
126-
127-
{AE_CTRL, 0x01}, //Automatic Exposure
128-
{AE_TARGET_MEAN, 0x3C}, //AE target mean [Def: 0x3C]
129-
{AE_MIN_MEAN, 0x0A}, //AE min target mean [Def: 0x0A]
130-
131-
{INTEGRATION_H, 0x01}, //Integration H [Def: 0x01]
132-
{INTEGRATION_L, 0x08}, //Integration L [Def: 0x08]
133-
{ANALOG_GAIN, 0x00}, //Analog Global Gain [Def: 0x00]
134-
{DAMPING_FACTOR, 0x20}, //Damping Factor [Def: 0x20]
135-
{DIGITAL_GAIN_H, 0x01}, //Digital Gain High [Def: 0x01]
136-
{DIGITAL_GAIN_L, 0x00}, //Digital Gain Low [Def: 0x00]
137-
138-
{CONVERGE_IN_TH, 0x03}, //Converge in threshold [Def: 0x03]
139-
{CONVERGE_OUT_TH, 0x05}, //Converge out threshold [Def: 0x05]
140-
{MAX_INTG_H, 0x01}, //Maximum INTG High Byte [Def: 0x01]
141-
{MAX_INTG_L, 0x54}, //Maximum INTG Low Byte [Def: 0x54]
142-
{MAX_AGAIN_FULL, 0x03}, //Maximum Analog gain in full frame mode [Def: 0x03]
143-
{MAX_AGAIN_BIN2, 0x04}, //Maximum Analog gain in bin2 mode [Def: 0x04]
144-
145-
{0x210B, 0xC0},
146-
{0x210E, 0x00}, //Flicker Control
147-
{0x210F, 0x00},
148-
{0x2110, 0x3C},
149-
{0x2111, 0x00},
150-
{0x2112, 0x32},
151-
152-
{0x2150, 0x30},
153-
{0x0340, 0x02},
154-
{0x0341, 0x16},
155-
{0x0342, 0x01},
156-
{0x0343, 0x78},
157-
{0x3010, 0x01}, // 324 x 244 pixel
158-
{0x0383, 0x01},
159-
{0x0387, 0x01},
160-
{0x0390, 0x03},
161-
{0x3011, 0x70},
162-
{0x3059, 0x02},
163-
{0x3060, 0x00},
164-
//{0x0601, 0x01},
165-
{IMG_ORIENTATION, 0x00},
166-
{0x0104, 0x01}
84+
{BLC_TGT, 0x08}, // BLC target :8 at 8 bit mode
85+
{BLC2_TGT, 0x08}, // BLI target :8 at 8 bit mode
86+
{0x3044, 0x0A}, // Increase CDS time for settling
87+
{0x3045, 0x00}, // Make symetric for cds_tg and rst_tg
88+
{0x3047, 0x0A}, // Increase CDS time for settling
89+
{0x3050, 0xC0}, // Make negative offset up to 4x
90+
{0x3051, 0x42},
91+
{0x3052, 0x50},
92+
{0x3053, 0x00},
93+
{0x3054, 0x03}, // tuning sf sig clamping as lowest
94+
{0x3055, 0xF7}, // tuning dsun
95+
{0x3056, 0xF8}, // increase adc nonoverlap clk
96+
{0x3057, 0x29}, // increase adc pwr for missing code
97+
{0x3058, 0x1F}, // turn on dsun
98+
{0x3059, 0x1E},
99+
{0x3064, 0x00},
100+
{0x3065, 0x04}, // pad pull 0
101+
102+
{BLC_CFG, 0x43}, // BLC_on, IIR
103+
{0x1001, 0x43}, // BLC dithering en
104+
{0x1002, 0x43}, // blc_darkpixel_thd
105+
{0x0350, 0x7F}, // Dgain Control
106+
{BLI_EN, 0x01}, // BLI enable
107+
{0x1003, 0x00}, // BLI Target [Def: 0x20]
108+
109+
{DPC_CTRL, 0x01}, // DPC option 0: DPC off 1 : mono 3 : bayer1 5 : bayer2
110+
{0x1009, 0xA0}, // cluster hot pixel th
111+
{0x100A, 0x60}, // cluster cold pixel th
112+
{SINGLE_THR_HOT, 0x90}, // single hot pixel th
113+
{SINGLE_THR_COLD, 0x40}, // single cold pixel th
114+
{0x1012, 0x00}, // Sync. shift disable
115+
{0x2000, 0x07},
116+
{0x2003, 0x00},
117+
{0x2004, 0x1C},
118+
{0x2007, 0x00},
119+
{0x2008, 0x58},
120+
{0x200B, 0x00},
121+
{0x200C, 0x7A},
122+
{0x200F, 0x00},
123+
{0x2010, 0xB8},
124+
{0x2013, 0x00},
125+
{0x2014, 0x58},
126+
{0x2017, 0x00},
127+
{0x2018, 0x9B},
128+
129+
{AE_CTRL, 0x01}, //Automatic Exposure
130+
{AE_TARGET_MEAN, 0x3C}, //AE target mean [Def: 0x3C]
131+
{AE_MIN_MEAN, 0x0A}, //AE min target mean [Def: 0x0A]
132+
{CONVERGE_IN_TH, 0x03}, //Converge in threshold [Def: 0x03]
133+
{CONVERGE_OUT_TH, 0x05}, //Converge out threshold [Def: 0x05]
134+
{MAX_INTG_H, 0x01}, //Maximum INTG High Byte [Def: 0x01]
135+
{MAX_INTG_L, 0x54}, //Maximum INTG Low Byte [Def: 0x54]
136+
{MAX_AGAIN_FULL, 0x03}, //Maximum Analog gain in full frame mode [Def: 0x03]
137+
{MAX_AGAIN_BIN2, 0x04}, //Maximum Analog gain in bin2 mode [Def: 0x04]
138+
{MAX_DGAIN, 0xC0},
139+
140+
{INTEGRATION_H, 0x01}, //Integration H [Def: 0x01]
141+
{INTEGRATION_L, 0x08}, //Integration L [Def: 0x08]
142+
{ANALOG_GAIN, 0x00}, //Analog Global Gain [Def: 0x00]
143+
{DAMPING_FACTOR, 0x20}, //Damping Factor [Def: 0x20]
144+
{DIGITAL_GAIN_H, 0x01}, //Digital Gain High [Def: 0x01]
145+
{DIGITAL_GAIN_L, 0x00}, //Digital Gain Low [Def: 0x00]
146+
147+
{FS_CTRL, 0x00}, //Flicker Control
148+
149+
{FS_60HZ_H, 0x00},
150+
{FS_60HZ_L, 0x3C},
151+
{FS_50HZ_H, 0x00},
152+
{FS_50HZ_L, 0x32},
153+
154+
{MD_CTRL, 0x30},
155+
{FRAME_LEN_LINES_H, HIMAX_FRAME_LENGTH>>8},
156+
{FRAME_LEN_LINES_L, HIMAX_FRAME_LENGTH&0xFF},
157+
{LINE_LEN_PCK_H, HIMAX_LINE_LEN_PCK>>8},
158+
{LINE_LEN_PCK_L, HIMAX_LINE_LEN_PCK&0xFF},
159+
{0x3010, 0x00}, // no full frame
160+
{0x0383, 0x01},
161+
{0x0387, 0x01},
162+
{0x0390, 0x00},
163+
{0x3011, 0x70},
164+
{0x3059, 0x02},
165+
{0x3060, 0x0B},
166+
{IMG_ORIENTATION, 0x00}, // change the orientation
167+
{0x0104, 0x01},
167168
};
168169

169170
/* SPI transfer command sequence array */
@@ -207,8 +208,11 @@ uint8_t HIMAX_Open(void)
207208

208209
//printf("Model: %x:%x\n", HIMAX_RegRead(MODEL_ID_H), HIMAX_RegRead(MODEL_ID_L));
209210

210-
if (HIMAX_Reset()!=0) return -1;
211-
//HIMAX_Boot();
211+
if (HIMAX_Reset()!=0) {
212+
return -1;
213+
}
214+
215+
HIMAX_Boot();
212216
//For debugging camera Configuration
213217
//HIMAX_PrintReg();
214218
HAL_Delay(200);
@@ -284,13 +288,12 @@ static uint8_t HIMAX_Boot()
284288
uint32_t i;
285289

286290
for(i = 0; i < (sizeof(himax_default_regs) / sizeof(regval_list_t)); i++) {
287-
//printf("%d\n", i);
288291
HIMAX_RegWrite(himax_default_regs[i].reg_num, himax_default_regs[i].value);
289-
//delay(1);
290292
}
291293

292294
HIMAX_RegWrite(PCLK_POLARITY, (0x20 | PCLK_FALLING_EDGE));
293295

296+
HIMAX_RegWrite(MODE_SELECT, HIMAX_Standby);
294297
return 0;
295298
}
296299

@@ -354,4 +357,4 @@ static uint8_t HIMAX_PrintReg()
354357

355358
/**
356359
* @}
357-
*/
360+
*/

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