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cmagliecmaglie
committed
Merge branch 'sam-usart-mode-fix' into ide-1.5.x
2 parents 07d1abf + 00f23d3 commit 0e01340

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4 files changed

+133
-50
lines changed

4 files changed

+133
-50
lines changed

‎hardware/arduino/sam/cores/arduino/UARTClass.cpp

+10-4
Original file line numberDiff line numberDiff line change
@@ -35,12 +35,18 @@ UARTClass::UARTClass( Uart *pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer *p
3535

3636
// Public Methods //////////////////////////////////////////////////////////////
3737

38-
void UARTClass::begin( const uint32_t dwBaudRate )
38+
void UARTClass::begin(const uint32_t dwBaudRate)
3939
{
40-
begin( dwBaudRate, UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL );
40+
begin(dwBaudRate, Mode_8N1);
4141
}
4242

43-
void UARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
43+
void UARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)
44+
{
45+
uint32_t modeReg = static_cast<uint32_t>(config) & 0x00000E00;
46+
init(dwBaudRate, modeReg | UART_MR_CHMODE_NORMAL);
47+
}
48+
49+
void UARTClass::init(const uint32_t dwBaudRate, const uint32_t modeReg)
4450
{
4551
// Configure PMC
4652
pmc_enable_periph_clk( _dwId );
@@ -52,7 +58,7 @@ void UARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
5258
_pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
5359

5460
// Configure mode
55-
_pUart->UART_MR = config;
61+
_pUart->UART_MR = modeReg;
5662

5763
// Configure baudrate (asynchronous, no oversampling)
5864
_pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4;

‎hardware/arduino/sam/cores/arduino/UARTClass.h

+26-10
Original file line numberDiff line numberDiff line change
@@ -25,22 +25,27 @@
2525
// Includes Atmel CMSIS
2626
#include <chip.h>
2727

28-
class UARTClass : public HardwareSerial
29-
{
30-
protected:
31-
RingBuffer *_rx_buffer;
32-
RingBuffer *_tx_buffer;
28+
#define SERIAL_8N1 UARTClass::Mode_8N1
29+
#define SERIAL_8E1 UARTClass::Mode_8E1
30+
#define SERIAL_8O1 UARTClass::Mode_8O1
31+
#define SERIAL_8M1 UARTClass::Mode_8M1
32+
#define SERIAL_8S1 UARTClass::Mode_8S1
3333

34-
protected:
35-
Uart* _pUart;
36-
IRQn_Type _dwIrq;
37-
uint32_t _dwId;
3834

35+
class UARTClass : public HardwareSerial
36+
{
3937
public:
38+
enum UARTModes {
39+
Mode_8N1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO,
40+
Mode_8E1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_EVEN,
41+
Mode_8O1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_ODD,
42+
Mode_8M1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_MARK,
43+
Mode_8S1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_SPACE,
44+
};
4045
UARTClass(Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
4146

4247
void begin(const uint32_t dwBaudRate);
43-
void begin(const uint32_t dwBaudRate, const uint32_t config);
48+
void begin(const uint32_t dwBaudRate, const UARTModes config);
4449
void end(void);
4550
int available(void);
4651
int availableForWrite(void);
@@ -56,6 +61,17 @@ class UARTClass : public HardwareSerial
5661
void IrqHandler(void);
5762

5863
operator bool() { return true; }; // UART always active
64+
65+
protected:
66+
void init(const uint32_t dwBaudRate, const uint32_t config);
67+
68+
RingBuffer *_rx_buffer;
69+
RingBuffer *_tx_buffer;
70+
71+
Uart* _pUart;
72+
IRQn_Type _dwIrq;
73+
uint32_t _dwId;
74+
5975
};
6076

6177
#endif // _UART_CLASS_

‎hardware/arduino/sam/cores/arduino/USARTClass.cpp

+16-2
Original file line numberDiff line numberDiff line change
@@ -32,8 +32,22 @@ USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffe
3232

3333
// Public Methods //////////////////////////////////////////////////////////////
3434

35-
void USARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
35+
void USARTClass::begin(const uint32_t dwBaudRate)
3636
{
37-
UARTClass::begin(dwBaudRate, config);
37+
begin(dwBaudRate, Mode_8N1);
38+
}
39+
40+
void USARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)
41+
{
42+
uint32_t modeReg = static_cast<uint32_t>(config);
43+
modeReg |= US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHMODE_NORMAL;
44+
init(dwBaudRate, modeReg);
45+
}
46+
47+
void USARTClass::begin(const uint32_t dwBaudRate, const USARTModes config)
48+
{
49+
uint32_t modeReg = static_cast<uint32_t>(config);
50+
modeReg |= US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHMODE_NORMAL;
51+
init(dwBaudRate, modeReg);
3852
}
3953

‎hardware/arduino/sam/cores/arduino/USARTClass.h

+81-34
Original file line numberDiff line numberDiff line change
@@ -26,46 +26,93 @@
2626
#include <chip.h>
2727

2828
// Define config for Serial.begin(baud, config);
29-
#define SERIAL_5N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
30-
#define SERIAL_6N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
31-
#define SERIAL_7N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
32-
#define SERIAL_8N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
29+
#define SERIAL_5N1 USARTClass::Mode_5N1
30+
#define SERIAL_6N1 USARTClass::Mode_6N1
31+
#define SERIAL_7N1 USARTClass::Mode_7N1
32+
#define SERIAL_5N2 USARTClass::Mode_5N2
33+
#define SERIAL_6N2 USARTClass::Mode_6N2
34+
#define SERIAL_7N2 USARTClass::Mode_7N2
35+
#define SERIAL_8N2 USARTClass::Mode_8N2
36+
#define SERIAL_5E1 USARTClass::Mode_5E1
37+
#define SERIAL_6E1 USARTClass::Mode_6E1
38+
#define SERIAL_7E1 USARTClass::Mode_7E1
39+
#define SERIAL_5E2 USARTClass::Mode_5E2
40+
#define SERIAL_6E2 USARTClass::Mode_6E2
41+
#define SERIAL_7E2 USARTClass::Mode_7E2
42+
#define SERIAL_8E2 USARTClass::Mode_8E2
43+
#define SERIAL_5O1 USARTClass::Mode_5O1
44+
#define SERIAL_6O1 USARTClass::Mode_6O1
45+
#define SERIAL_7O1 USARTClass::Mode_7O1
46+
#define SERIAL_5O2 USARTClass::Mode_5O2
47+
#define SERIAL_6O2 USARTClass::Mode_6O2
48+
#define SERIAL_7O2 USARTClass::Mode_7O2
49+
#define SERIAL_8O2 USARTClass::Mode_8O2
50+
#define SERIAL_5M1 USARTClass::Mode_5M1
51+
#define SERIAL_6M1 USARTClass::Mode_6M1
52+
#define SERIAL_7M1 USARTClass::Mode_7M1
53+
#define SERIAL_5M2 USARTClass::Mode_5M2
54+
#define SERIAL_6M2 USARTClass::Mode_6M2
55+
#define SERIAL_7M2 USARTClass::Mode_7M2
56+
#define SERIAL_8M2 USARTClass::Mode_8M2
57+
#define SERIAL_5S1 USARTClass::Mode_5S1
58+
#define SERIAL_6S1 USARTClass::Mode_6S1
59+
#define SERIAL_7S1 USARTClass::Mode_7S1
60+
#define SERIAL_5S2 USARTClass::Mode_5S2
61+
#define SERIAL_6S2 USARTClass::Mode_6S2
62+
#define SERIAL_7S2 USARTClass::Mode_7S2
63+
#define SERIAL_8S2 USARTClass::Mode_8S2
3364

34-
#define SERIAL_5N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
35-
#define SERIAL_6N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
36-
#define SERIAL_7N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
37-
#define SERIAL_8N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
38-
39-
#define SERIAL_5E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
40-
#define SERIAL_6E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
41-
#define SERIAL_7E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
42-
#define SERIAL_8E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
43-
44-
#define SERIAL_5E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
45-
#define SERIAL_6E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
46-
#define SERIAL_7E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
47-
#define SERIAL_8E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
48-
49-
#define SERIAL_5O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
50-
#define SERIAL_6O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
51-
#define SERIAL_7O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
52-
#define SERIAL_8O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
53-
54-
#define SERIAL_5O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
55-
#define SERIAL_6O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
56-
#define SERIAL_7O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
57-
#define SERIAL_8O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
5865

5966
class USARTClass : public UARTClass
6067
{
61-
protected:
62-
Usart* _pUsart;
63-
6468
public:
65-
USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer );
69+
// 8x1 bit modes are inherited from UARTClass
70+
enum USARTModes {
71+
Mode_5N1 = US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
72+
Mode_6N1 = US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
73+
Mode_7N1 = US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
74+
Mode_5N2 = US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
75+
Mode_6N2 = US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
76+
Mode_7N2 = US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
77+
Mode_8N2 = US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
78+
Mode_5E1 = US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
79+
Mode_6E1 = US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
80+
Mode_7E1 = US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
81+
Mode_5E2 = US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
82+
Mode_6E2 = US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
83+
Mode_7E2 = US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
84+
Mode_8E2 = US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
85+
Mode_5O1 = US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
86+
Mode_6O1 = US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
87+
Mode_7O1 = US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
88+
Mode_5O2 = US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
89+
Mode_6O2 = US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
90+
Mode_7O2 = US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
91+
Mode_8O2 = US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
92+
Mode_5M1 = US_MR_CHRL_5_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
93+
Mode_6M1 = US_MR_CHRL_6_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
94+
Mode_7M1 = US_MR_CHRL_7_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
95+
Mode_5M2 = US_MR_CHRL_5_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
96+
Mode_6M2 = US_MR_CHRL_6_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
97+
Mode_7M2 = US_MR_CHRL_7_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
98+
Mode_8M2 = US_MR_CHRL_8_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
99+
Mode_5S1 = US_MR_CHRL_5_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
100+
Mode_6S1 = US_MR_CHRL_6_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
101+
Mode_7S1 = US_MR_CHRL_7_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
102+
Mode_5S2 = US_MR_CHRL_5_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
103+
Mode_6S2 = US_MR_CHRL_6_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
104+
Mode_7S2 = US_MR_CHRL_7_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
105+
Mode_8S2 = US_MR_CHRL_8_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
106+
};
107+
108+
USARTClass(Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
109+
110+
void begin(const uint32_t dwBaudRate);
111+
void begin(const uint32_t dwBaudRate, const USARTModes config);
112+
void begin(const uint32_t dwBaudRate, const UARTModes config);
66113

67-
void begin( const uint32_t dwBaudRate , const uint32_t config );
68-
using UARTClass::begin; // Needed only for polymorphic methods
114+
protected:
115+
Usart* _pUsart;
69116
};
70117

71118
#endif // _USART_CLASS_

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