From ea3adafeb2acc8bdd2e0e3d0262140853cff144e Mon Sep 17 00:00:00 2001 From: Seyed Alireza Damghani Date: Tue, 8 Jun 2021 19:15:22 -0300 Subject: [PATCH] [Flow]: Adding verilog header files to run Koios design with and without complex_dsp macro definition Signed-off-by: Seyed Alireza Damghani --- .../koios/attention_layer_complex_dsp.vh | 7 +++ .../verilog/koios/conv_layer_complex_dsp.vh | 28 +++++++++ .../koios/dla_like.medium_complex_dsp.vh | 60 +++++++++++++++++++ .../koios/dla_like.small_complex_dsp.vh | 36 +++++++++++ .../koios/eltwise_layer_complex_dsp.vh | 7 +++ .../verilog/koios/gemm_layer_complex_dsp.vh | 7 +++ .../{ => generic_circuits}/attention_layer.v | 1 - .../koios/{ => generic_circuits}/bnn.v | 0 .../{ => generic_circuits}/clstm_like.large.v | 0 .../clstm_like.medium.v | 0 .../{ => generic_circuits}/clstm_like.small.v | 0 .../koios/{ => generic_circuits}/conv_layer.v | 0 .../{ => generic_circuits}/conv_layer_hls.v | 23 ------- .../{ => generic_circuits}/dla_like.medium.v | 55 ----------------- .../{ => generic_circuits}/dla_like.small.v | 31 ---------- .../{ => generic_circuits}/eltwise_layer.v | 1 - .../koios/{ => generic_circuits}/gemm_layer.v | 1 - .../koios/{ => generic_circuits}/lstm.v | 0 .../{ => generic_circuits}/reduction_layer.v | 0 .../koios/{ => generic_circuits}/robot_rl.v | 0 .../koios/{ => generic_circuits}/softmax.v | 1 - .../koios/{ => generic_circuits}/spmv.v | 0 .../tiny_darknet_like.medium.v | 0 .../tiny_darknet_like.small.v | 12 ---- .../{ => generic_circuits}/tpu_like.medium.v | 0 .../{ => generic_circuits}/tpu_like.small.v | 0 .../verilog/koios/robot_rl_complex_dsp.vh | 7 +++ .../verilog/koios/softmax_complex_dsp.vh | 7 +++ .../tiny_darknet_like.small_complex_dsp.vh | 18 ++++++ .../{ => DSP_slice_arch}/config/config.txt | 16 ++--- .../config/golden_results.txt | 0 .../koios/flagship_arch/config/config.txt | 34 +++++++++++ .../flagship_arch/config/golden_results.txt | 8 +++ .../koios_multi_arch/config/config.txt | 2 +- .../vtr_reg_nightly/task_list.txt | 3 +- .../vtr_reg_strong/koios/config/config.txt | 10 ++-- .../vtr_reg_weekly/koios/config/config.txt | 16 ++--- 37 files changed, 244 insertions(+), 147 deletions(-) create mode 100644 vtr_flow/benchmarks/verilog/koios/attention_layer_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/conv_layer_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/dla_like.medium_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/dla_like.small_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/eltwise_layer_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/gemm_layer_complex_dsp.vh rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/attention_layer.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/bnn.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/clstm_like.large.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/clstm_like.medium.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/clstm_like.small.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/conv_layer.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/conv_layer_hls.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/dla_like.medium.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/dla_like.small.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/eltwise_layer.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/gemm_layer.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/lstm.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/reduction_layer.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/robot_rl.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/softmax.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/spmv.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/tiny_darknet_like.medium.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/tiny_darknet_like.small.v (99%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/tpu_like.medium.v (100%) rename vtr_flow/benchmarks/verilog/koios/{ => generic_circuits}/tpu_like.small.v (100%) create mode 100644 vtr_flow/benchmarks/verilog/koios/robot_rl_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/softmax_complex_dsp.vh create mode 100644 vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small_complex_dsp.vh rename vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/{ => DSP_slice_arch}/config/config.txt (65%) rename vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/{ => DSP_slice_arch}/config/golden_results.txt (100%) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/golden_results.txt diff --git a/vtr_flow/benchmarks/verilog/koios/attention_layer_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/attention_layer_complex_dsp.vh new file mode 100644 index 00000000000..f6b0f4d9633 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/attention_layer_complex_dsp.vh @@ -0,0 +1,7 @@ +/* + * attention_layer design including complex dsp definition +*/ + +`define complex_dsp + +`include "./generic_circuits/attention_layer.v" diff --git a/vtr_flow/benchmarks/verilog/koios/conv_layer_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/conv_layer_complex_dsp.vh new file mode 100644 index 00000000000..f2ceb02e93e --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/conv_layer_complex_dsp.vh @@ -0,0 +1,28 @@ +/* + * conv_layer_hls design including complex dsp definition +*/ + +`define complex_dsp +module dpram ( + +    clk, + +    address_a, + +    address_b, + +    wren_a, + +    wren_b, + +    data_a, + +    data_b, + +    out_a, + +    out_b + +); + +`include "./generic_circuits/conv_layer_hls.v" diff --git a/vtr_flow/benchmarks/verilog/koios/dla_like.medium_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/dla_like.medium_complex_dsp.vh new file mode 100644 index 00000000000..d88d7f1a3f6 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/dla_like.medium_complex_dsp.vh @@ -0,0 +1,60 @@ +/* + * dla_like.medium design including complex dsp definition +*/ + +`define complex_dsp +module DLA ( + input clk, + input i_reset, + input [15:0] i_ddr_0_0, + output o_dummy_out_0_0, + input [15:0] i_ddr_0_1, + output o_dummy_out_0_1, + input [15:0] i_ddr_0_2, + output o_dummy_out_0_2, + input [15:0] i_ddr_0_3, + output o_dummy_out_0_3, + input [15:0] i_ddr_1_0, + output o_dummy_out_1_0, + input [15:0] i_ddr_1_1, + output o_dummy_out_1_1, + input [15:0] i_ddr_1_2, + output o_dummy_out_1_2, + input [15:0] i_ddr_1_3, + output o_dummy_out_1_3, + input [15:0] i_ddr_2_0, + output o_dummy_out_2_0, + input [15:0] i_ddr_2_1, + output o_dummy_out_2_1, + input [15:0] i_ddr_2_2, + output o_dummy_out_2_2, + input [15:0] i_ddr_2_3, + output o_dummy_out_2_3, + input [15:0] i_ddr_3_0, + output o_dummy_out_3_0, + input [15:0] i_ddr_3_1, + output o_dummy_out_3_1, + input [15:0] i_ddr_3_2, + output o_dummy_out_3_2, + input [15:0] i_ddr_3_3, + output o_dummy_out_3_3, + input [15:0] i_ddr_4_0, + output o_dummy_out_4_0, + input [15:0] i_ddr_4_1, + output o_dummy_out_4_1, + input [15:0] i_ddr_4_2, + output o_dummy_out_4_2, + input [15:0] i_ddr_4_3, + output o_dummy_out_4_3, + input [15:0] i_ddr_5_0, + output o_dummy_out_5_0, + input [15:0] i_ddr_5_1, + output o_dummy_out_5_1, + input [15:0] i_ddr_5_2, + output o_dummy_out_5_2, + input [15:0] i_ddr_5_3, + output o_dummy_out_5_3, + output o_valid +); + +`include "./generic_circuits/dla_like.medium.v" diff --git a/vtr_flow/benchmarks/verilog/koios/dla_like.small_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/dla_like.small_complex_dsp.vh new file mode 100644 index 00000000000..5fe349a7b74 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/dla_like.small_complex_dsp.vh @@ -0,0 +1,36 @@ +/* + * dla_like.small design including complex dsp definition +*/ + +`define complex_dsp +module DLA ( + input clk, + input i_reset, + input [15:0] i_ddr_0_0, + output o_dummy_out_0_0, + input [15:0] i_ddr_0_1, + output o_dummy_out_0_1, + input [15:0] i_ddr_1_0, + output o_dummy_out_1_0, + input [15:0] i_ddr_1_1, + output o_dummy_out_1_1, + input [15:0] i_ddr_2_0, + output o_dummy_out_2_0, + input [15:0] i_ddr_2_1, + output o_dummy_out_2_1, + input [15:0] i_ddr_3_0, + output o_dummy_out_3_0, + input [15:0] i_ddr_3_1, + output o_dummy_out_3_1, + input [15:0] i_ddr_4_0, + output o_dummy_out_4_0, + input [15:0] i_ddr_4_1, + output o_dummy_out_4_1, + input [15:0] i_ddr_5_0, + output o_dummy_out_5_0, + input [15:0] i_ddr_5_1, + output o_dummy_out_5_1, + output o_valid +); + +`include "./generic_circuits/dla_like.small.v" diff --git a/vtr_flow/benchmarks/verilog/koios/eltwise_layer_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/eltwise_layer_complex_dsp.vh new file mode 100644 index 00000000000..5cca745fb66 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/eltwise_layer_complex_dsp.vh @@ -0,0 +1,7 @@ +/* + * eltwise_layer design including complex dsp definition +*/ + +`define complex_dsp + +`include "./generic_circuits/eltwise_layer.v" diff --git a/vtr_flow/benchmarks/verilog/koios/gemm_layer_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/gemm_layer_complex_dsp.vh new file mode 100644 index 00000000000..34841e2d024 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/gemm_layer_complex_dsp.vh @@ -0,0 +1,7 @@ +/* + * gemm_layer design including complex dsp definition +*/ + +`define complex_dsp + +`include "./generic_circuits/gemm_layer.v" diff --git a/vtr_flow/benchmarks/verilog/koios/attention_layer.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/attention_layer.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/attention_layer.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/attention_layer.v index 46019c0c26f..0a0dfc18cc8 100644 --- a/vtr_flow/benchmarks/verilog/koios/attention_layer.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/attention_layer.v @@ -4,7 +4,6 @@ //`define SIMULATION_MEMORY //`define SIMULATION_addfp -`define complex_dsp `define VECTOR_DEPTH 64 //Q,K,V vector size `define DATA_WIDTH 16 `define VECTOR_BITS 1024 // 16 bit each (16x64) diff --git a/vtr_flow/benchmarks/verilog/koios/bnn.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/bnn.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/bnn.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/bnn.v diff --git a/vtr_flow/benchmarks/verilog/koios/clstm_like.large.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/clstm_like.large.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/clstm_like.large.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/clstm_like.large.v diff --git a/vtr_flow/benchmarks/verilog/koios/clstm_like.medium.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/clstm_like.medium.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/clstm_like.medium.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/clstm_like.medium.v diff --git a/vtr_flow/benchmarks/verilog/koios/clstm_like.small.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/clstm_like.small.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/clstm_like.small.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/clstm_like.small.v diff --git a/vtr_flow/benchmarks/verilog/koios/conv_layer.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/conv_layer.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/conv_layer.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/conv_layer.v diff --git a/vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/conv_layer_hls.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/conv_layer_hls.v index fb87a4e6ff7..02b2bd748d2 100644 --- a/vtr_flow/benchmarks/verilog/koios/conv_layer_hls.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/conv_layer_hls.v @@ -18,29 +18,6 @@ // Abridged for VTR by: Daniel Rauch ////////////////////////////////////////////////////////////////////////////// -`define complex_dsp -module dpram ( - -    clk, - -    address_a, - -    address_b, - -    wren_a, - -    wren_b, - -    data_a, - -    data_b, - -    out_a, - -    out_b - -); - parameter AWIDTH=10; parameter NUM_WORDS=1024; diff --git a/vtr_flow/benchmarks/verilog/koios/dla_like.medium.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.medium.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/dla_like.medium.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.medium.v index 160e8f540bb..3d848881dda 100644 --- a/vtr_flow/benchmarks/verilog/koios/dla_like.medium.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.medium.v @@ -15,61 +15,6 @@ //4. Double-buffering after each layer. /////////////////////////////////////////////////////////////////////////////// -`define complex_dsp -module DLA ( - input clk, - input i_reset, - input [15:0] i_ddr_0_0, - output o_dummy_out_0_0, - input [15:0] i_ddr_0_1, - output o_dummy_out_0_1, - input [15:0] i_ddr_0_2, - output o_dummy_out_0_2, - input [15:0] i_ddr_0_3, - output o_dummy_out_0_3, - input [15:0] i_ddr_1_0, - output o_dummy_out_1_0, - input [15:0] i_ddr_1_1, - output o_dummy_out_1_1, - input [15:0] i_ddr_1_2, - output o_dummy_out_1_2, - input [15:0] i_ddr_1_3, - output o_dummy_out_1_3, - input [15:0] i_ddr_2_0, - output o_dummy_out_2_0, - input [15:0] i_ddr_2_1, - output o_dummy_out_2_1, - input [15:0] i_ddr_2_2, - output o_dummy_out_2_2, - input [15:0] i_ddr_2_3, - output o_dummy_out_2_3, - input [15:0] i_ddr_3_0, - output o_dummy_out_3_0, - input [15:0] i_ddr_3_1, - output o_dummy_out_3_1, - input [15:0] i_ddr_3_2, - output o_dummy_out_3_2, - input [15:0] i_ddr_3_3, - output o_dummy_out_3_3, - input [15:0] i_ddr_4_0, - output o_dummy_out_4_0, - input [15:0] i_ddr_4_1, - output o_dummy_out_4_1, - input [15:0] i_ddr_4_2, - output o_dummy_out_4_2, - input [15:0] i_ddr_4_3, - output o_dummy_out_4_3, - input [15:0] i_ddr_5_0, - output o_dummy_out_5_0, - input [15:0] i_ddr_5_1, - output o_dummy_out_5_1, - input [15:0] i_ddr_5_2, - output o_dummy_out_5_2, - input [15:0] i_ddr_5_3, - output o_dummy_out_5_3, - output o_valid -); - wire [15:0] f_buffer_pe_0_0; wire valid_buff_0_0; wire [15:0] f_buffer_pe_0_1; diff --git a/vtr_flow/benchmarks/verilog/koios/dla_like.small.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.small.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/dla_like.small.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.small.v index e7ff1dce971..21ab9815637 100644 --- a/vtr_flow/benchmarks/verilog/koios/dla_like.small.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/dla_like.small.v @@ -15,37 +15,6 @@ //4. Double-buffering after each layer. /////////////////////////////////////////////////////////////////////////////// -`define complex_dsp -module DLA ( - input clk, - input i_reset, - input [15:0] i_ddr_0_0, - output o_dummy_out_0_0, - input [15:0] i_ddr_0_1, - output o_dummy_out_0_1, - input [15:0] i_ddr_1_0, - output o_dummy_out_1_0, - input [15:0] i_ddr_1_1, - output o_dummy_out_1_1, - input [15:0] i_ddr_2_0, - output o_dummy_out_2_0, - input [15:0] i_ddr_2_1, - output o_dummy_out_2_1, - input [15:0] i_ddr_3_0, - output o_dummy_out_3_0, - input [15:0] i_ddr_3_1, - output o_dummy_out_3_1, - input [15:0] i_ddr_4_0, - output o_dummy_out_4_0, - input [15:0] i_ddr_4_1, - output o_dummy_out_4_1, - input [15:0] i_ddr_5_0, - output o_dummy_out_5_0, - input [15:0] i_ddr_5_1, - output o_dummy_out_5_1, - output o_valid -); - wire [15:0] f_buffer_pe_0_0; wire valid_buff_0_0; wire [15:0] f_buffer_pe_0_1; diff --git a/vtr_flow/benchmarks/verilog/koios/eltwise_layer.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/eltwise_layer.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/eltwise_layer.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/eltwise_layer.v index 0b745ea8b0b..5151cd394a3 100644 --- a/vtr_flow/benchmarks/verilog/koios/eltwise_layer.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/eltwise_layer.v @@ -56,7 +56,6 @@ //section by section. The number of rows will be programmed //in the "iterations" register in the design. -`define complex_dsp `define BFLOAT16 // IEEE Half Precision => EXPONENT = 5, MANTISSA = 10 diff --git a/vtr_flow/benchmarks/verilog/koios/gemm_layer.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/gemm_layer.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/gemm_layer.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/gemm_layer.v index 70911f25983..ebb25a4011a 100644 --- a/vtr_flow/benchmarks/verilog/koios/gemm_layer.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/gemm_layer.v @@ -19,7 +19,6 @@ // with a simpler DSP (just a fixed point multiplier) like in the // flagship arch timing/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ///////////////////////////////////////////////////////////////////////// -`define complex_dsp `define BFLOAT16 // IEEE Half Precision => EXPONENT = 5, MANTISSA = 10 diff --git a/vtr_flow/benchmarks/verilog/koios/lstm.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/lstm.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/lstm.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/lstm.v diff --git a/vtr_flow/benchmarks/verilog/koios/reduction_layer.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/reduction_layer.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/reduction_layer.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/reduction_layer.v diff --git a/vtr_flow/benchmarks/verilog/koios/robot_rl.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/robot_rl.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/robot_rl.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/robot_rl.v diff --git a/vtr_flow/benchmarks/verilog/koios/softmax.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/softmax.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/softmax.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/softmax.v index 6a27414fd09..3544ce56fbb 100644 --- a/vtr_flow/benchmarks/verilog/koios/softmax.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/softmax.v @@ -14,7 +14,6 @@ ////////////////////////////////////////////////////////////////////////////// //softmax_p8_smem_rfloat16_alut_v512_b2_-0.1_0.1.v -`define complex_dsp `ifndef DEFINES_DONE `define DEFINES_DONE `define EXPONENT 5 diff --git a/vtr_flow/benchmarks/verilog/koios/spmv.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/spmv.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/spmv.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/spmv.v diff --git a/vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.medium.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/tiny_darknet_like.medium.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.medium.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/tiny_darknet_like.medium.v diff --git a/vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/tiny_darknet_like.small.v similarity index 99% rename from vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/tiny_darknet_like.small.v index 2b27c3e044c..99def6f7ac5 100644 --- a/vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small.v +++ b/vtr_flow/benchmarks/verilog/koios/generic_circuits/tiny_darknet_like.small.v @@ -16,18 +16,6 @@ ////////////////////////////////////////////////////////////////////////////// `timescale 1 ns / 1 ps -`define complex_dsp -module td_fused_top_Block_entry_proc_proc392 ( - ap_clk, - ap_rst, - ap_start, - ap_done, - ap_continue, - ap_idle, - ap_ready, - tmp, - ap_return -); parameter ap_ST_fsm_state1 = 1'd1; diff --git a/vtr_flow/benchmarks/verilog/koios/tpu_like.medium.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/tpu_like.medium.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/tpu_like.medium.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/tpu_like.medium.v diff --git a/vtr_flow/benchmarks/verilog/koios/tpu_like.small.v b/vtr_flow/benchmarks/verilog/koios/generic_circuits/tpu_like.small.v similarity index 100% rename from vtr_flow/benchmarks/verilog/koios/tpu_like.small.v rename to vtr_flow/benchmarks/verilog/koios/generic_circuits/tpu_like.small.v diff --git a/vtr_flow/benchmarks/verilog/koios/robot_rl_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/robot_rl_complex_dsp.vh new file mode 100644 index 00000000000..537edf31ecb --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/robot_rl_complex_dsp.vh @@ -0,0 +1,7 @@ +/* + * robot_rl design including complex dsp definition +*/ + +`define complex_dsp + +`include "./generic_circuits/robot_rl.v" diff --git a/vtr_flow/benchmarks/verilog/koios/softmax_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/softmax_complex_dsp.vh new file mode 100644 index 00000000000..e131e0584b1 --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/softmax_complex_dsp.vh @@ -0,0 +1,7 @@ +/* + * softmax design including complex dsp definition +*/ + +`define complex_dsp + +`include "./generic_circuits/softmax.v" diff --git a/vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small_complex_dsp.vh b/vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small_complex_dsp.vh new file mode 100644 index 00000000000..c8f1de0781b --- /dev/null +++ b/vtr_flow/benchmarks/verilog/koios/tiny_darknet_like.small_complex_dsp.vh @@ -0,0 +1,18 @@ +/* + * tiny_darknet_like.small design including complex dsp definition +*/ + +`define complex_dsp +module td_fused_top_Block_entry_proc_proc392 ( + ap_clk, + ap_rst, + ap_start, + ap_done, + ap_continue, + ap_idle, + ap_ready, + tmp, + ap_return +); + +`include "./generic_circuits/tiny_darknet_like.small.v" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/DSP_slice_arch/config/config.txt similarity index 65% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/DSP_slice_arch/config/config.txt index a49f020056d..22f808f02ef 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/DSP_slice_arch/config/config.txt @@ -10,13 +10,15 @@ circuits_dir=benchmarks/verilog/koios archs_dir=arch/COFFE_22nm # Add circuits to list to sweep -circuit_list_add=tpu_like.small.v -circuit_list_add=dla_like.small.v -circuit_list_add=bnn.v -circuit_list_add=attention_layer.v -circuit_list_add=conv_layer_hls.v -circuit_list_add=conv_layer.v -circuit_list_add=gemm_layer.v +circuit_list_add=attention_layer_complex_dsp.vh +circuit_list_add=conv_layer_complex_dsp.vh +circuit_list_add=dla_like.medium_complex_dsp.vh +circuit_list_add=dla_like.small_complex_dsp.vh +circuit_list_add=eltwise_layer_complex_dsp.vh +circuit_list_add=gemm_layer_complex_dsp.vh +circuit_list_add=softmax_complex_dsp.vh +circuit_list_add=tiny_darknet_like.small_complex_dsp.vh + # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/DSP_slice_arch/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/DSP_slice_arch/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/config.txt new file mode 100644 index 00000000000..a41914b2688 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/config.txt @@ -0,0 +1,34 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/verilog/koios + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=generic_circuits/tpu_like.small.v +circuit_list_add=generic_circuits/dla_like.small.v +circuit_list_add=generic_circuits/bnn.v +circuit_list_add=generic_circuits/attention_layer.v +circuit_list_add=generic_circuits/conv_layer_hls.v +circuit_list_add=generic_circuits/conv_layer.v +circuit_list_add=generic_circuits/gemm_layer.v + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-track_memory_usage -crit_path_router_iterations 100 --route_chan_width 300 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/golden_results.txt new file mode 100644 index 00000000000..8ab32757805 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios/flagship_arch/config/golden_results.txt @@ -0,0 +1,8 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml tpu_like.small.v common 2871.10 9.36 235096 5 619.21 -1 -1 159760 -1 -1 1119 355 14 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 2568860 355 289 50215 41827 2 23224 2053 136 136 18496 dsp_top auto 1233.72 457725 91.70 0.38 7.24742 -105267 -7.24742 2.59789 14.13 0.101267 0.0738583 24.91 18.6865 -1 561916 17 5.92627e+08 1.03195e+08 4.09037e+08 22114.9 16.37 32.3744 25.1979 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml dla_like.small.v common 7527.41 42.24 729876 5 3941.31 -1 -1 630244 -1 -1 5545 194 828 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 4409476 194 13 217044 174718 1 91037 6708 164 164 26896 memory auto 1604.22 969627 663.41 2.84 5.61569 -424718 -5.61569 5.61569 21.49 0.584073 0.385993 104.796 73.1698 -1 1450542 14 8.6211e+08 3.01197e+08 5.93540e+08 22068.0 53.97 132.203 96.049 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml bnn.v common 2028.52 40.37 577472 3 240.94 -1 -1 513656 -1 -1 5695 260 0 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 2195980 260 122 231647 179602 1 86181 6140 83 83 6889 clb auto 613.32 940951 503.35 2.87 6.4402 -131403 -6.4402 6.4402 5.41 0.753268 0.564332 85.331 60.8639 -1 1224690 16 2.13666e+08 1.74902e+08 1.51359e+08 21971.1 50.49 114.382 84.8538 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml attention_layer.v common 1330.99 11.83 1095592 7 59.16 -1 -1 560612 -1 -1 1248 1058 161 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 1180420 1058 16 47407 39134 1 26605 2588 86 86 7396 dsp_top auto 728.70 234151 118.11 0.71 5.89837 -78343.6 -5.89837 5.89837 6.64 0.181478 0.146942 31.9659 24.5807 -1 366899 17 2.32446e+08 8.36361e+07 1.62201e+08 21930.9 16.25 40.6352 32.1556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer_hls.v common 1683.16 192.83 9143400 3 149.94 -1 -1 4553192 -1 -1 1716 1016 21 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 1513348 1016 2283 12850 14308 1 7250 5048 106 106 11236 io auto 181.40 79576 74.59 0.58 5.03442 -17693.7 -5.03442 5.03442 8.28 0.127234 0.120402 24.6886 23.0123 -1 106054 14 3.5748e+08 5.382e+07 2.47132e+08 21994.6 6.16 29.6431 27.7556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml conv_layer.v common 867.30 13.62 227552 4 518.46 -1 -1 124284 -1 -1 1183 91 56 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 897640 91 65 45593 38091 2 19386 1479 72 72 5184 dsp_top auto 81.63 212937 61.22 0.39 5.55252 -117084 -5.55252 2.23623 2.48 0.11604 0.082594 17.7564 12.8384 -1 297947 17 1.63139e+08 6.20375e+07 1.13191e+08 21834.7 14.48 23.8235 18.0154 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml gemm_layer.v common 2006.31 16.47 230016 4 1261.81 -1 -1 156292 -1 -1 2017 691 0 -1 success v8.0.0-4161-g8f4b3e9ca release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-124-generic x86_64 2021-05-28T23:09:34 jupiter0 /export/aman/vtr_aman/vtr-verilog-to-routing/vtr_flow/tasks 2033612 691 1088 58313 53279 1 21351 3996 118 118 13924 dsp_top auto 32.28 652505 167.05 2.15 4.75844 -113972 -4.75844 4.75844 12.55 0.183273 0.140578 37.5874 29.6831 -1 785995 13 4.42318e+08 1.07038e+08 3.07460e+08 22081.3 25.57 45.8144 37.0299 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios_multi_arch/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios_multi_arch/config/config.txt index b2e37c5acdb..17b17ede4bb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios_multi_arch/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/koios_multi_arch/config/config.txt @@ -10,7 +10,7 @@ circuits_dir=benchmarks/verilog/koios archs_dir=arch/COFFE_22nm # Add circuits to list to sweep -circuit_list_add=conv_layer.v +circuit_list_add=conv_layer_complex_dsp.vh # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt index 2bc88878037..c70183c0201 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/task_list.txt @@ -15,5 +15,6 @@ regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check regression_tests/vtr_reg_nightly/vtr_timing_update_diff regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan regression_tests/vtr_reg_nightly/symbiflow -regression_tests/vtr_reg_nightly/koios +regression_tests/vtr_reg_nightly/koios/DSP_slice_arch +regression_tests/vtr_reg_nightly/koios/flagship_arch regression_tests/vtr_reg_nightly/koios_multi_arch diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt index 369baeba795..6f8f5b54136 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/koios/config/config.txt @@ -10,11 +10,11 @@ circuits_dir=benchmarks/verilog/koios archs_dir=arch/COFFE_22nm # Add circuits to list to sweep -circuit_list_add=eltwise_layer.v -circuit_list_add=robot_rl.v -circuit_list_add=softmax.v -circuit_list_add=reduction_layer.v -circuit_list_add=spmv.v +circuit_list_add=eltwise_layer_complex_dsp.vh +circuit_list_add=generic_circuits/robot_rl.v +circuit_list_add=softmax_complex_dsp.vh +circuit_list_add=generic_circuits/reduction_layer.v +circuit_list_add=generic_circuits/spmv.v # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt index 49e489aff0b..98fc6f57d1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_weekly/koios/config/config.txt @@ -10,14 +10,14 @@ circuits_dir=benchmarks/verilog/koios archs_dir=arch/COFFE_22nm # Add circuits to list to sweep -circuit_list_add=clstm_like.small.v -circuit_list_add=clstm_like.medium.v -circuit_list_add=clstm_like.large.v -circuit_list_add=lstm.v -circuit_list_add=tpu_like.medium.v -circuit_list_add=tiny_darknet_like.small.v -circuit_list_add=tiny_darknet_like.medium.v -circuit_list_add=dla_like.medium.v +circuit_list_add=generic_circuits/clstm_like.small.v +circuit_list_add=generic_circuits/clstm_like.medium.v +circuit_list_add=generic_circuits/clstm_like.large.v +circuit_list_add=generic_circuits/lstm.v +circuit_list_add=generic_circuits/tpu_like.medium.v +circuit_list_add=tiny_darknet_like.small_complex_dsp.vh +circuit_list_add=generic_circuits/tiny_darknet_like.medium.v +circuit_list_add=dla_like.medium_complex_dsp.vh # Add architectures to list to sweep arch_list_add=k6FracN10LB_mem20K_complexDSP_customSB_22nm.xml