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Revert "[MLIR][XeGPU] Adding XeGPU 2d block operators (llvm#84692)" (llvm#85653)
This reverts commit daebe5c. This commit causes the following asan issue: ``` <snip>/llvm-project/build/bin/mlir-opt <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir | <snip>/llvm-project/build/bin/FileCheck <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir # executed command: <snip>/llvm-project/build/bin/mlir-opt <snip>/llvm-project/mlir/test/Dialect/XeGPU/XeGPUOps.mlir # .---command stderr------------ # | ================================================================= # | ==2772558==ERROR: AddressSanitizer: stack-use-after-return on address 0x7fd2c2c42b90 at pc 0x55e406d54614 bp 0x7ffc810e4070 sp 0x7ffc810e4068 # | READ of size 8 at 0x7fd2c2c42b90 thread T0 # | #0 0x55e406d54613 in operator()<long int const*> /usr/include/c++/13/bits/predefined_ops.h:318 # | rust-lang#1 0x55e406d54613 in __count_if<long int const*, __gnu_cxx::__ops::_Iter_pred<mlir::verifyListOfOperandsOrIntegers(Operation*, llvm::StringRef, unsigned int, llvm::ArrayRef<long int>, ValueRange)::<lambda(int64_t)> > > /usr/include/c++/13/bits/stl_algobase.h:2125 # | rust-lang#2 0x55e406d54613 in count_if<long int const*, mlir::verifyListOfOperandsOrIntegers(Operation*, ... ```
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‎mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h

+1-6
Original file line numberDiff line numberDiff line change
@@ -9,12 +9,7 @@
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#ifndef MLIR_DIALECT_XEGPU_IR_XEGPU_H
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#define MLIR_DIALECT_XEGPU_IR_XEGPU_H
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#include "mlir/Bytecode/BytecodeOpInterface.h"
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#include "mlir/IR/BuiltinTypes.h"
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#include "mlir/IR/Dialect.h"
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#include "mlir/Interfaces/ShapedOpInterfaces.h"
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#include "mlir/Interfaces/SideEffectInterfaces.h"
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#include "mlir/Interfaces/ViewLikeInterface.h"
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#include <mlir/IR/Dialect.h>
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namespace mlir {
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namespace xegpu {

‎mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td

-61
Original file line numberDiff line numberDiff line change
@@ -10,72 +10,11 @@
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#define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD
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include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td"
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include "mlir/IR/EnumAttr.td"
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class XeGPUAttr<string name, string attrMnemonic, list<Trait> traits = [],
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string baseCppClass = "::mlir::Attribute">
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: AttrDef<XeGPU_Dialect, name, traits, baseCppClass> {
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let mnemonic = attrMnemonic;
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}
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def XeGPU_TensorDescAttr: XeGPUAttr<"TensorDesc", "tdesc_attr"> {
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let parameters = (ins
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OptionalParameter<"MemoryScopeAttr">: $memory_scope,
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OptionalParameter<"IntegerAttr", "1">: $array_length,
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OptionalParameter<"BoolAttr", "true">: $boundary_check
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);
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let builders = [
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AttrBuilder<(ins
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CArg<"xegpu::MemoryScope", "xegpu::MemoryScope::Global">:$memory_scope,
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CArg<"int", "1">:$array_length,
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CArg<"bool", "true">: $boundary_check
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)>
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];
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let assemblyFormat = "`<` struct(params) `>`";
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}
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//===----------------------------------------------------------------------===//
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// XeGPU Memory Scope Enums.
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//===----------------------------------------------------------------------===//
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def XeGPU_MemoryScopeGlobal: I32EnumAttrCase<"Global", 0, "global">;
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def XeGPU_MemoryScopeShared: I32EnumAttrCase<"SLM", 1, "slm">;
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def XeGPU_MemoryScope: I32EnumAttr<"MemoryScope",
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"The address space of the memory the tensor descritor is created for",
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[XeGPU_MemoryScopeGlobal, XeGPU_MemoryScopeShared]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::xegpu";
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}
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def XeGPU_MemoryScopeAttr:
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EnumAttr<XeGPU_Dialect, XeGPU_MemoryScope, "memory_scope"> {
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let assemblyFormat = "$value";
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}
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//===----------------------------------------------------------------------===//
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// XeGPU Cache Enums.
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//===----------------------------------------------------------------------===//
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def XeGPU_CachePolicyCached: I32EnumAttrCase<"CACHED", 0, "cached">; // valid for read and write
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def XeGPU_CachePolicyUncached: I32EnumAttrCase<"UNCACHED", 1, "uncached">; // valid for read and write
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def XeGPU_CachePolicyStreaming: I32EnumAttrCase<"STREAMING", 2, "streaming">; // valid for read only
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def XeGPU_CachePolicyInvalid: I32EnumAttrCase<"READ_INVALIDATE", 3, "read_invalidate">; // valid for read only
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def XeGPU_CachePolicyWriteBack: I32EnumAttrCase<"WRITE_BACK", 4, "write_back">; // valid for write only
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def XeGPU_CachePolicyWriteThrough: I32EnumAttrCase<"WRITE_THROUGH", 5, "write_through">; // valid for write only
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def XeGPU_CachePolicyEnums : I32EnumAttr<"CachePolicy", "Cache policy",
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[XeGPU_CachePolicyCached, XeGPU_CachePolicyUncached,
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XeGPU_CachePolicyStreaming, XeGPU_CachePolicyInvalid,
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XeGPU_CachePolicyWriteBack, XeGPU_CachePolicyWriteThrough]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::xegpu";
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}
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def XeGPU_CacheHintAttr
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: EnumAttr<XeGPU_Dialect, XeGPU_CachePolicyEnums, "cache_hint"> {
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let assemblyFormat = "`<` $value `>`";
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}
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#endif // MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD

‎mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td

+2-2
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,8 @@ def XeGPU_Dialect : Dialect {
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the lower-level GPU compiler.
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}];
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let useDefaultTypePrinterParser = true;
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let useDefaultAttributePrinterParser = true;
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// let useDefaultTypePrinterParser = true;
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// let useDefaultAttributePrinterParser = true;
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}
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#endif // MLIR_DIALECT_XEGPU_IR_XEGPUDIALECT_TD

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