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cpldcpucpldcpu
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general clean up
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-162
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5 files changed

+16
-162
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‎20_SYNTH/discrete_YG_logic_liberty.lib

-60
This file was deleted.

‎20_SYNTH/flow_discrete_YG.ys

-40
This file was deleted.

‎30_PLACE/PCBPlace.py

+2-52
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,7 @@ def insertLTLNOTb(self,x, y, netin, netbase, netout, cellname="void", rload=True
120120
supply nets are VCC and GND."""
121121

122122
n_elements = self.n_board.find('elements')
123-
et.SubElement(n_elements, 'element', name = "Q"+cellname, library="discrete_logic_components", package="SOT23", value="PMBT2369", x=str(x+1.65), y=str(y+1.4))
123+
et.SubElement(n_elements, 'element', name = "Q"+cellname, library="discrete_logic_components", package="SOT23", value="PMBT2369", x=str(x+1.55), y=str(y+1.4))
124124
et.SubElement(n_elements, 'element', name = "L"+cellname, library="discrete_logic_components", package="LED0603", value="LEDW", x=str(x+1.17), y=str(y+3.63) ,rot="R270")
125125
self.countcomponent("npn transistor")
126126
self.countcomponent("led")
@@ -495,16 +495,6 @@ def outputtoboard(self, board, pitchx = 5, pitchy = 7):
495495
# LED
496496
elif celltype == 'LED':
497497
board.insertLED(val.y*pitchx,val.x*pitchy,val.pin[0],key)
498-
# NE555
499-
# def insertNE555tbuf(self,x, y, netenable, netin, netout, cellname="void"):
500-
elif celltype == 'ne_NOT':
501-
board.insertNE555not(val.y*pitchx,val.x*pitchy,val.pin[0],val.pin[1],key)
502-
elif celltype == 'ne_ANDN2':
503-
board.insertNE555andn2(val.y*pitchx,val.x*pitchy,val.pin[0],val.pin[1],val.pin[2],key)
504-
elif celltype == 'ne_WAND1' or celltype == 'ne_WAND2' or celltype == 'ne_WAND3' or celltype == 'ne_WAND4':
505-
board.insertNE555wand(val.y*pitchx,val.x*pitchy, val.pin[:-1], val.pin[-1], key)
506-
elif celltype == 'ne_TBUF':
507-
board.insertNE555tbuf(val.y*pitchx,val.x*pitchy,val.pin[0],val.pin[1],val.pin[2],key)
508498
# LTL
509499
elif celltype == 'ltl_NOTo':
510500
board.insertLTLNOTo(val.y*pitchx,val.x*pitchy,val.pin[0],val.pin[1],key)
@@ -617,10 +607,6 @@ def addlogiccell(self,name,celltype, nets):
617607
self.insertcell(name+"d","rt_NOT", [name+"CI", name+"CNI"]) # clock inversion
618608
self.addlogiccell(name+"a","PHLATCH", [name+"CI" , nets[1] , name+"DI"]) # pin order: E, D, Q
619609
self.addlogiccell(name+"b","PHLATCH", [name+"CNI", name+"DI", nets[2] ]) # pin order: E, D, Q
620-
# elif celltype == "DFF7T": # pin order: C, D, Q
621-
# self.insertcell(name+"c","rt_NOT", [nets[0], name+"CI"]) # clock inversion
622-
# self.addlogiccell(name+"a","LATCH3Tn", [name+"CI", nets[1], name+"DI"]) # pin order: E, D, Q
623-
# self.addlogiccell(name+"b","LATCH3Tn", [nets[0], name+"DI", nets[2]]) # pin order: E, D, Q
624610
elif celltype == "PHLATCH": # pin order: E, D, Q
625611
self.insertcell(name+"I","rt_NOT", [nets[0], name+"CI"]) # clock inversion (cannot be shared in DFF due to tpd requirements)
626612
self.addlogiccell(name+"X1","rt_NOR2", [name+"CI" , nets[1] , name+"X1o"]) # X1: D,CI,X1o
@@ -806,26 +792,6 @@ def addlogiccell(self,name,celltype, nets):
806792
self.peephole.append(["DFF_with_Qn", nets[4], nets[3] ])
807793
# e = Qn, f = Q
808794

809-
# Experimental 5T PH Latch. Requires tuning gate speeds, which does not work in this framework
810-
# elif celltype == "nm_5TLATCH": # pin order: E, D, Q
811-
# self.addlogiccell(name+"X1","nm_NOR2" ,[nets[0] , nets[2] , name+"X1o"])
812-
# self.addlogiccell(name+"X2","nm_AOI1_2",[name+"X1o" , nets[0] , nets[1] , nets[2]])
813-
# Hybrid gates (bipolar pass gate + nmos )
814-
# def insertTBUF(self,x, y, netenable, netin, netout, cellname="void"):
815-
# def insertNMOSinvg(self,x, y, netin, netgate, netdrain, cellname="void"):
816-
817-
# elif celltype == "hy_XOR2":
818-
# self.addlogiccell(name+"a","TBUFe" , [nets[0] , nets[1] , name+"x!" ])
819-
# self.addlogiccell(name+"b","TBUFe" , [nets[1] , nets[0] , name+"x!" ])
820-
# self.addlogiccell(name+"c","nm_NOT", [name+"x!" , nets[2]] )
821-
# elif celltype == "hy_DFF7T": # pin order: C, D, Q
822-
# self.addlogiccell(name+"c","nm_NOT", [nets[0], name+"CI"]) # clock inversion
823-
# self.addlogiccell(name+"a","hy_LATCH3Tn", [name+"CI", nets[1] , name+"DI"]) # pin order: E, D, Q
824-
# self.addlogiccell(name+"b","hy_LATCH3Tn", [nets[0] , name+"DI", nets[2] ]) # pin order: E, D, Q
825-
# elif celltype == "hy_LATCH3Tn": # pin order: E, D, Q
826-
# self.addlogiccell(name+"X1","TBUFe" , [nets[0] , nets[1] , name+"X1o" ])
827-
# self.addlogiccell(name+"X2","NMg" , [name+"X3o", name+"X1o", nets[2] ])
828-
# self.addlogiccell(name+"X3","nm_NOT", [nets[2] , name+"X3o" ])
829795
# LTL
830796
elif celltype == "ltl_NOT":
831797
self.insertcell(name+"a" ,"ltl_WAND1" , [nets[0] , name+"i!" ])
@@ -839,30 +805,14 @@ def addlogiccell(self,name,celltype, nets):
839805
elif celltype == "ltl_NAND4":
840806
self.insertcell(name+"a" ,"ltl_WAND4" , [nets[0] , nets[1] , nets[2] , nets[3] , name+"i!" ])
841807
self.insertcell(name+"b" ,"ltl_NOTs" , [name+"i!", nets[4] ])
842-
elif celltype == "ltl_LATCH3Tn": # pin order: E, D, Q
843-
self.addlogiccell(name+"a","TBUFc" , [nets[0] , nets[1] , name+"X1o!" ])
844-
self.addlogiccell(name+"b","ltl_NOTb" , [name+"X3o!", name+"X1o!", nets[2] ])
845-
self.addlogiccell(name+"c","ltl_NOTs" , [nets[2] , name+"X3o!" ])
846-
# elif celltype == "ltl_DFF": # pin order: C, D, Q
847-
# self.addlogiccell(name+"c","ltl_NOT", [nets[0], name+"CI"]) # clock inversion
848-
# self.addlogiccell(name+"a","ltl_LATCH3Tn", [name+"CI", nets[1], name+"DI"]) # pin order: E, D, Q
849-
# self.addlogiccell(name+"b","ltl_LATCH3Tn", [nets[0], name+"DI", nets[2]]) # pin order: E, D, Q
850808
elif celltype == "ltl_DFFNP": # pin order: C, D, Q, Qn
851-
# self.addlogiccell(name+"a","ltl_NAND2" , [nets[1] , name+"b" , name+"a" ])
852-
# self.addlogiccell(name+"b","ltl_NAND3" , [name+"a" , nets[0] , name+"c", name+"b" ])
853-
# self.addlogiccell(name+"c","ltl_NAND2" , [nets[0] , name+"d" , name+"c" ])
854-
# self.addlogiccell(name+"d","ltl_NAND2" , [name+"c" , name+"a" , name+"d" ])
855-
# self.addlogiccell(name+"e","ltl_NAND2" , [name+"b" , nets[2] , nets[3] ])
856-
# self.addlogiccell(name+"f","ltl_NAND2" , [nets[3] , name+"c" , nets[2] ])
857-
809+
# self.addlogiccell(name+"a","ltl_NAND2" , [nets[1] , name+"b" , name+"a" ]) # pure LTL version fail simulation, but works in circuit
858810
self.addlogiccell(name+"a","nm_NAND2" , [nets[1] , name+"b" , name+"a" ])
859811
self.addlogiccell(name+"b","ltl_NAND3" , [name+"a" , nets[0] , name+"c", name+"b" ])
860812
self.addlogiccell(name+"c","ltl_NAND2" , [nets[0] , name+"d" , name+"c" ])
861813
self.addlogiccell(name+"d","ltl_NAND2" , [name+"c" , name+"a" , name+"d" ])
862814
self.addlogiccell(name+"e","ltl_NAND2" , [name+"b" , nets[2] , nets[3] ])
863815
self.addlogiccell(name+"f","ltl_NAND2" , [nets[3] , name+"c" , nets[2] ])
864-
865-
866816
# self.peephole.append(["DFF_with_Qn", nets[2], nets[3] ])
867817
# self.peephole.append(["DFF_with_Qn", nets[3], nets[2] ])
868818
# e = Qn, f = Q

‎Docs/Technologies.md

+14-8
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
- Latch: CDC6600-Style Polarity hold latch
1313
- DFF: Master-Slave DFF based on PH-Latch
1414
- DFF: 6x NOR DFF_PN
15-
- Minimum Cell size: 0.15" x 0.25"
15+
- Cell size: 0.15" x 0.25"
1616
- Recommended components: PMBT2369, RL=3.3k, RB=3.3k, Cp=22p for 5V.
1717

1818
### Post Layout Simulation of counter.vhd
@@ -43,7 +43,7 @@
4343
- Achieves 300-500kHz with MMBT3904 clones (e.g. CJ)
4444
- Supported gates: NOT, NOR2, NOR3, NOR4, XOR2
4545
- Flip-Flop: 3T master slave FF with pass gate
46-
- Minimum cell size: 0.15" x 0.25"
46+
- Cell size: 0.15" x 0.25"
4747
- Recommended Components: MMBT3904, Rl=3.3k, Rb=10k for 5V (FOmax=4). **Attention**: PMBT2369 will not work in this logic style due to too low reverse beta
4848

4949
### Post Layout Simulation of counter.vhd
@@ -73,9 +73,9 @@
7373

7474
- NMOS logic based on power mosfet supporting wide number of gate types at low component count. Relatively robust, but slow.
7575
- Can achive 500kHz-2 MHz with counter depending on transitor type
76-
- Supported gates: NOT, NOR2, NOR3, NAND2,NAND3, AOI2_2, AOI1_2, AOI2_2_2
76+
- Supported gates: NOT, NOR2, NOR3, NAND2, NAND3, AOI2_2, AOI1_2, AOI2_2_2
7777
- Flip-Flop: 6x NAND with clear
78-
- Minimum cell size: 0.15" x 0.25"
78+
- Cell size: 0.15" x 0.25"
7979
- Recommended Components:
8080
- low cost: 2N7002, Rl=1k,
8181
- High speed: FDV301/DMG301, Rl=1K
@@ -94,9 +94,7 @@
9494
- clock-to-out0 delay rise: 65.3 ns fall: 67.9 ns
9595

9696
### TODO
97-
- Move RL to output -> done
9897
- Clock distribution
99-
- Double check DFF implementation -> done
10098

10199
---
102100
# LTL - LED Transistor Logic
@@ -114,6 +112,12 @@
114112
- Functional: Pass
115113
- Fmax: 1.17 MHZ @ 66.6 mA (RL=2.2k: Fmax=0.55 MHz@30 mA)
116114
- clock-to-out0 delay rise: 77.8 ns fall: 183 ns
115+
116+
### TODO
117+
- Fix and validate LED spice models for post layout simulation
118+
- Clock distribution
119+
120+
---
117121
# amux - analog multiplexer logic
118122

119123
### TODO
@@ -126,17 +130,19 @@
126130
## 74LVC - 74LVC single gate logic
127131

128132
- Using single gate logic: 74LVC1G175 and 74LVC1G57 multi gates. Very versatile and area efficient, however 1G57 is not always easy to obtain and expensive. Rather use amux logic. Not PCB proven yet
133+
-
129134

130135
## YG - YG strip logic
131136

132137
- not finished
133-
138+
- removed to clean up before refactoring
134139
## NE - NE555 logic
135140

136-
- Don't use, this is more of a joke. It works, but is slow, large, expensive and power hungry.
141+
- More of a joke
137142
- Removed to declutter source
138143

139144
## hybrid - hybrid nmos/bipolar logic
140145

141146
- Nasty logic level, neither fast nor stable. Don't use.
147+
- Removed to declutter before refactoring
142148

‎run_20_Synthesis.sh

-2
Original file line numberDiff line numberDiff line change
@@ -42,8 +42,6 @@ elif [ "$APP" == "amux" ]; then
4242
echo "Synthesizing to analog multiplexer logic"
4343
elif [ "$APP" == "74LVC" ]; then
4444
echo "Synthesizing to single gate TTL logic (74LVC)"
45-
elif [ "$APP" == "YG" ]; then
46-
echo "Synthesizing to YG strip logic"
4745
elif [ "$APP" == "LTL" ]; then
4846
echo "Synthesizing to LED²-Transistor-Logic"
4947
else

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