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cfallincfallin
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Merge pull request bytecodealliance#3044 from akirilov-arm/simd_i32x4_trunc_sat_f64x2
Enable the simd_i32x4_trunc_sat_f64x2 test for AArch64
2 parents b9985fe + 330f02a commit f2d2f3a

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11 files changed

+491
-160
lines changed

11 files changed

+491
-160
lines changed

‎build.rs

-1
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,6 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
233233
| ("simd", "simd_i16x8_extmul_i8x16")
234234
| ("simd", "simd_i32x4_extadd_pairwise_i16x8")
235235
| ("simd", "simd_i32x4_extmul_i16x8")
236-
| ("simd", "simd_i32x4_trunc_sat_f64x2")
237236
| ("simd", "simd_i64x2_extmul_i32x4") => return true,
238237

239238
_ => {}

‎cranelift/codegen/meta/src/shared/instructions.rs

+27-8
Original file line numberDiff line numberDiff line change
@@ -3985,19 +3985,19 @@ pub(crate) fn define(
39853985
.constraints(vec![WiderOrEq(Int.clone(), IntTo.clone())]),
39863986
);
39873987

3988-
let I16or32xN = &TypeVar::new(
3989-
"I16or32xN",
3990-
"A SIMD vector type containing integer lanes 16 or 32 bits wide",
3988+
let I16or32or64xN = &TypeVar::new(
3989+
"I16or32or64xN",
3990+
"A SIMD vector type containing integer lanes 16, 32, or 64 bits wide",
39913991
TypeSetBuilder::new()
3992-
.ints(16..32)
3993-
.simd_lanes(4..8)
3992+
.ints(16..64)
3993+
.simd_lanes(2..8)
39943994
.includes_scalars(false)
39953995
.build(),
39963996
);
39973997

3998-
let x = &Operand::new("x", I16or32xN);
3999-
let y = &Operand::new("y", I16or32xN);
4000-
let a = &Operand::new("a", &I16or32xN.split_lanes());
3998+
let x = &Operand::new("x", I16or32or64xN);
3999+
let y = &Operand::new("y", I16or32or64xN);
4000+
let a = &Operand::new("a", &I16or32or64xN.split_lanes());
40014001

40024002
ig.push(
40034003
Inst::new(
@@ -4036,6 +4036,25 @@ pub(crate) fn define(
40364036
.operands_out(vec![a]),
40374037
);
40384038

4039+
ig.push(
4040+
Inst::new(
4041+
"uunarrow",
4042+
r#"
4043+
Combine `x` and `y` into a vector with twice the lanes but half the integer width while
4044+
saturating overflowing values to the unsigned maximum and minimum.
4045+
4046+
Note that all input lanes are considered unsigned.
4047+
4048+
The lanes will be concatenated after narrowing. For example, when `x` and `y` are `i32x4`
4049+
and `x = [x3, x2, x1, x0]` and `y = [y3, y2, y1, y0]`, then after narrowing the value
4050+
returned is an `i16x8`: `a = [y3', y2', y1', y0', x3', x2', x1', x0']`.
4051+
"#,
4052+
&formats.binary,
4053+
)
4054+
.operands_in(vec![x, y])
4055+
.operands_out(vec![a]),
4056+
);
4057+
40394058
let I8or16or32xN = &TypeVar::new(
40404059
"I8or16or32xN",
40414060
"A SIMD vector type containing integer lanes 8, 16, or 32 bits wide.",

‎cranelift/codegen/src/isa/aarch64/inst/emit.rs

+36-16
Original file line numberDiff line numberDiff line change
@@ -1677,11 +1677,6 @@ impl MachInstEmit for Inst {
16771677
debug_assert_ne!(VectorSize::Size64x2, size);
16781678
(0b0, 0b00000, enc_size)
16791679
}
1680-
VecMisc2::Shll => {
1681-
debug_assert_ne!(VectorSize::Size64x2, size);
1682-
debug_assert!(!size.is_128bits());
1683-
(0b1, 0b10011, enc_size)
1684-
}
16851680
VecMisc2::Fcvtzs => {
16861681
debug_assert!(size == VectorSize::Size32x4 || size == VectorSize::Size64x2);
16871682
(0b0, 0b11011, enc_size)
@@ -2092,24 +2087,49 @@ impl MachInstEmit for Inst {
20922087
| machreg_to_vec(rd.to_reg()),
20932088
);
20942089
}
2095-
&Inst::VecMiscNarrow {
2090+
&Inst::VecRRLong {
20962091
op,
20972092
rd,
20982093
rn,
2099-
size,
21002094
high_half,
21012095
} => {
2102-
let size = match size.lane_size() {
2103-
ScalarSize::Size8 => 0b00,
2104-
ScalarSize::Size16 => 0b01,
2105-
ScalarSize::Size32 => 0b10,
2106-
_ => panic!("Unexpected vector operand lane size!"),
2096+
let (u, size, bits_12_16) = match op {
2097+
VecRRLongOp::Fcvtl16 => (0b0, 0b00, 0b10111),
2098+
VecRRLongOp::Fcvtl32 => (0b0, 0b01, 0b10111),
2099+
VecRRLongOp::Shll8 => (0b1, 0b00, 0b10011),
2100+
VecRRLongOp::Shll16 => (0b1, 0b01, 0b10011),
2101+
VecRRLongOp::Shll32 => (0b1, 0b10, 0b10011),
21072102
};
2108-
let (u, bits_12_16) = match op {
2109-
VecMiscNarrowOp::Xtn => (0b0, 0b10010),
2110-
VecMiscNarrowOp::Sqxtn => (0b0, 0b10100),
2111-
VecMiscNarrowOp::Sqxtun => (0b1, 0b10010),
2103+
2104+
sink.put4(enc_vec_rr_misc(
2105+
((high_half as u32) << 1) | u,
2106+
size,
2107+
bits_12_16,
2108+
rd,
2109+
rn,
2110+
));
2111+
}
2112+
&Inst::VecRRNarrow {
2113+
op,
2114+
rd,
2115+
rn,
2116+
high_half,
2117+
} => {
2118+
let (u, size, bits_12_16) = match op {
2119+
VecRRNarrowOp::Xtn16 => (0b0, 0b00, 0b10010),
2120+
VecRRNarrowOp::Xtn32 => (0b0, 0b01, 0b10010),
2121+
VecRRNarrowOp::Xtn64 => (0b0, 0b10, 0b10010),
2122+
VecRRNarrowOp::Sqxtn16 => (0b0, 0b00, 0b10100),
2123+
VecRRNarrowOp::Sqxtn32 => (0b0, 0b01, 0b10100),
2124+
VecRRNarrowOp::Sqxtn64 => (0b0, 0b10, 0b10100),
2125+
VecRRNarrowOp::Sqxtun16 => (0b1, 0b00, 0b10010),
2126+
VecRRNarrowOp::Sqxtun32 => (0b1, 0b01, 0b10010),
2127+
VecRRNarrowOp::Sqxtun64 => (0b1, 0b10, 0b10010),
2128+
VecRRNarrowOp::Uqxtn16 => (0b1, 0b00, 0b10100),
2129+
VecRRNarrowOp::Uqxtn32 => (0b1, 0b01, 0b10100),
2130+
VecRRNarrowOp::Uqxtn64 => (0b1, 0b10, 0b10100),
21122131
};
2132+
21132133
sink.put4(enc_vec_rr_misc(
21142134
((high_half as u32) << 1) | u,
21152135
size,

‎cranelift/codegen/src/isa/aarch64/inst/emit_tests.rs

+160-42
Original file line numberDiff line numberDiff line change
@@ -2425,41 +2425,192 @@ fn test_aarch64_binemit() {
24252425
));
24262426

24272427
insns.push((
2428-
Inst::VecMiscNarrow {
2429-
op: VecMiscNarrowOp::Xtn,
2428+
Inst::VecRRLong {
2429+
op: VecRRLongOp::Fcvtl16,
2430+
rd: writable_vreg(0),
2431+
rn: vreg(30),
2432+
high_half: false,
2433+
},
2434+
"C07B210E",
2435+
"fcvtl v0.4s, v30.4h",
2436+
));
2437+
2438+
insns.push((
2439+
Inst::VecRRLong {
2440+
op: VecRRLongOp::Fcvtl32,
2441+
rd: writable_vreg(16),
2442+
rn: vreg(1),
2443+
high_half: true,
2444+
},
2445+
"3078614E",
2446+
"fcvtl2 v16.2d, v1.4s",
2447+
));
2448+
2449+
insns.push((
2450+
Inst::VecRRLong {
2451+
op: VecRRLongOp::Shll8,
2452+
rd: writable_vreg(12),
2453+
rn: vreg(5),
2454+
high_half: false,
2455+
},
2456+
"AC38212E",
2457+
"shll v12.8h, v5.8b, #8",
2458+
));
2459+
2460+
insns.push((
2461+
Inst::VecRRLong {
2462+
op: VecRRLongOp::Shll16,
2463+
rd: writable_vreg(9),
2464+
rn: vreg(1),
2465+
high_half: true,
2466+
},
2467+
"2938616E",
2468+
"shll2 v9.4s, v1.8h, #16",
2469+
));
2470+
2471+
insns.push((
2472+
Inst::VecRRLong {
2473+
op: VecRRLongOp::Shll32,
2474+
rd: writable_vreg(1),
2475+
rn: vreg(10),
2476+
high_half: false,
2477+
},
2478+
"4139A12E",
2479+
"shll v1.2d, v10.2s, #32",
2480+
));
2481+
2482+
insns.push((
2483+
Inst::VecRRNarrow {
2484+
op: VecRRNarrowOp::Xtn16,
2485+
rd: writable_vreg(25),
2486+
rn: vreg(17),
2487+
high_half: false,
2488+
},
2489+
"392A210E",
2490+
"xtn v25.8b, v17.8h",
2491+
));
2492+
2493+
insns.push((
2494+
Inst::VecRRNarrow {
2495+
op: VecRRNarrowOp::Xtn32,
2496+
rd: writable_vreg(3),
2497+
rn: vreg(10),
2498+
high_half: true,
2499+
},
2500+
"4329614E",
2501+
"xtn2 v3.8h, v10.4s",
2502+
));
2503+
2504+
insns.push((
2505+
Inst::VecRRNarrow {
2506+
op: VecRRNarrowOp::Xtn64,
24302507
rd: writable_vreg(22),
24312508
rn: vreg(8),
2432-
size: VectorSize::Size32x2,
24332509
high_half: false,
24342510
},
24352511
"1629A10E",
24362512
"xtn v22.2s, v8.2d",
24372513
));
24382514

24392515
insns.push((
2440-
Inst::VecMiscNarrow {
2441-
op: VecMiscNarrowOp::Sqxtn,
2516+
Inst::VecRRNarrow {
2517+
op: VecRRNarrowOp::Sqxtn16,
2518+
rd: writable_vreg(7),
2519+
rn: vreg(22),
2520+
high_half: true,
2521+
},
2522+
"C74A214E",
2523+
"sqxtn2 v7.16b, v22.8h",
2524+
));
2525+
2526+
insns.push((
2527+
Inst::VecRRNarrow {
2528+
op: VecRRNarrowOp::Sqxtn32,
24422529
rd: writable_vreg(31),
24432530
rn: vreg(0),
2444-
size: VectorSize::Size16x8,
24452531
high_half: true,
24462532
},
24472533
"1F48614E",
24482534
"sqxtn2 v31.8h, v0.4s",
24492535
));
24502536

24512537
insns.push((
2452-
Inst::VecMiscNarrow {
2453-
op: VecMiscNarrowOp::Sqxtun,
2538+
Inst::VecRRNarrow {
2539+
op: VecRRNarrowOp::Sqxtn64,
2540+
rd: writable_vreg(14),
2541+
rn: vreg(20),
2542+
high_half: false,
2543+
},
2544+
"8E4AA10E",
2545+
"sqxtn v14.2s, v20.2d",
2546+
));
2547+
2548+
insns.push((
2549+
Inst::VecRRNarrow {
2550+
op: VecRRNarrowOp::Sqxtun16,
24542551
rd: writable_vreg(16),
24552552
rn: vreg(23),
2456-
size: VectorSize::Size8x16,
24572553
high_half: false,
24582554
},
24592555
"F02A212E",
24602556
"sqxtun v16.8b, v23.8h",
24612557
));
24622558

2559+
insns.push((
2560+
Inst::VecRRNarrow {
2561+
op: VecRRNarrowOp::Sqxtun32,
2562+
rd: writable_vreg(28),
2563+
rn: vreg(9),
2564+
high_half: true,
2565+
},
2566+
"3C29616E",
2567+
"sqxtun2 v28.8h, v9.4s",
2568+
));
2569+
2570+
insns.push((
2571+
Inst::VecRRNarrow {
2572+
op: VecRRNarrowOp::Sqxtun64,
2573+
rd: writable_vreg(15),
2574+
rn: vreg(15),
2575+
high_half: false,
2576+
},
2577+
"EF29A12E",
2578+
"sqxtun v15.2s, v15.2d",
2579+
));
2580+
2581+
insns.push((
2582+
Inst::VecRRNarrow {
2583+
op: VecRRNarrowOp::Uqxtn16,
2584+
rd: writable_vreg(21),
2585+
rn: vreg(4),
2586+
high_half: true,
2587+
},
2588+
"9548216E",
2589+
"uqxtn2 v21.16b, v4.8h",
2590+
));
2591+
2592+
insns.push((
2593+
Inst::VecRRNarrow {
2594+
op: VecRRNarrowOp::Uqxtn32,
2595+
rd: writable_vreg(31),
2596+
rn: vreg(31),
2597+
high_half: false,
2598+
},
2599+
"FF4B612E",
2600+
"uqxtn v31.4h, v31.4s",
2601+
));
2602+
2603+
insns.push((
2604+
Inst::VecRRNarrow {
2605+
op: VecRRNarrowOp::Uqxtn64,
2606+
rd: writable_vreg(11),
2607+
rn: vreg(12),
2608+
high_half: true,
2609+
},
2610+
"8B49A16E",
2611+
"uqxtn2 v11.4s, v12.2d",
2612+
));
2613+
24632614
insns.push((
24642615
Inst::VecRRPair {
24652616
op: VecPairOp::Addp,
@@ -3810,39 +3961,6 @@ fn test_aarch64_binemit() {
38103961
"rev64 v1.4s, v10.4s",
38113962
));
38123963

3813-
insns.push((
3814-
Inst::VecMisc {
3815-
op: VecMisc2::Shll,
3816-
rd: writable_vreg(12),
3817-
rn: vreg(5),
3818-
size: VectorSize::Size8x8,
3819-
},
3820-
"AC38212E",
3821-
"shll v12.8h, v5.8b, #8",
3822-
));
3823-
3824-
insns.push((
3825-
Inst::VecMisc {
3826-
op: VecMisc2::Shll,
3827-
rd: writable_vreg(9),
3828-
rn: vreg(1),
3829-
size: VectorSize::Size16x4,
3830-
},
3831-
"2938612E",
3832-
"shll v9.4s, v1.4h, #16",
3833-
));
3834-
3835-
insns.push((
3836-
Inst::VecMisc {
3837-
op: VecMisc2::Shll,
3838-
rd: writable_vreg(1),
3839-
rn: vreg(10),
3840-
size: VectorSize::Size32x2,
3841-
},
3842-
"4139A12E",
3843-
"shll v1.2d, v10.2s, #32",
3844-
));
3845-
38463964
insns.push((
38473965
Inst::VecMisc {
38483966
op: VecMisc2::Fcvtzs,

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