@@ -155,7 +155,7 @@ static uint8_t remoteWakeCountdown; // When wake is requested
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// into the stack.
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static void handle_bus_reset (uint8_t rhport );
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static void dcd_transmit_packet (xfer_ctl_t * xfer , uint16_t ep_ix );
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- static bool edpt_xfer (uint8_t rhport , uint8_t ep_num , uint8_t dir );
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+ static bool edpt_xfer (uint8_t rhport , uint8_t ep_num , tusb_dir_t dir );
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// PMA allocation/access
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static uint16_t ep_buf_ptr ; ///< Points to first free memory location
@@ -275,7 +275,6 @@ static void handle_bus_reset(uint8_t rhport) {
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// Handle CTR interrupt for the TX/IN direction
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static void handle_ctr_tx (uint32_t ep_id ) {
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uint32_t ep_reg = ep_read (ep_id ) | USB_EP_CTR_TX | USB_EP_CTR_RX ;
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- ep_reg &= USB_EPREG_MASK ;
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uint8_t const ep_num = ep_reg & USB_EPADDR_FIELD ;
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , TUSB_DIR_IN );
@@ -345,12 +344,14 @@ static void handle_ctr_rx(uint32_t ep_id) {
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if ((rx_count < xfer -> max_packet_size ) || (xfer -> queued_len >= xfer -> total_len )) {
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// all bytes received or short packet
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- dcd_event_xfer_complete (0 , ep_num , xfer -> queued_len , XFER_RESULT_SUCCESS , true);
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// For ch32v203: reset rx bufsize to mps to prevent race condition to cause PMAOVR (occurs with msc write10)
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- // also ch32 seems to unconditionally accept ZLP on EP0 OUT, which can incorrectly use queued_len of previous
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- // transfer. So reset total_len and queued_len to 0.
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btable_set_rx_bufsize (ep_id , BTABLE_BUF_RX , xfer -> max_packet_size );
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+
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+ dcd_event_xfer_complete (0 , ep_num , xfer -> queued_len , XFER_RESULT_SUCCESS , true);
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+
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+ // ch32 seems to unconditionally accept ZLP on EP0 OUT, which can incorrectly use queued_len of previous
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+ // transfer. So reset total_len and queued_len to 0.
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xfer -> total_len = xfer -> queued_len = 0 ;
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} else {
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// Set endpoint active again for receiving more data. Note that isochronous endpoints stay active always
@@ -412,11 +413,6 @@ void dcd_int_handler(uint8_t rhport) {
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FSDEV_REG -> ISTR = (fsdev_bus_t )~USB_ISTR_ESOF ;
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}
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- if (int_status & USB_ISTR_PMAOVR ) {
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- TU_BREAKPOINT ();
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- FSDEV_REG -> ISTR = (fsdev_bus_t )~USB_ISTR_PMAOVR ;
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- }
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-
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// loop to handle all pending CTR interrupts
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while (FSDEV_REG -> ISTR & USB_ISTR_CTR ) {
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// skip DIR bit, and use CTR TX/RX instead, since there is chance we have both TX/RX completed in one interrupt
@@ -459,6 +455,11 @@ void dcd_int_handler(uint8_t rhport) {
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handle_ctr_tx (ep_id );
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}
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}
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+
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+ if (int_status & USB_ISTR_PMAOVR ) {
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+ TU_BREAKPOINT ();
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+ FSDEV_REG -> ISTR = (fsdev_bus_t )~USB_ISTR_PMAOVR ;
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+ }
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}
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//--------------------------------------------------------------------+
@@ -576,7 +577,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
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(void )rhport ;
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uint8_t const ep_addr = desc_ep -> bEndpointAddress ;
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const dir = tu_edpt_dir (ep_addr );
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+ tusb_dir_t const dir = tu_edpt_dir (ep_addr );
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const uint16_t packet_size = tu_edpt_packet_size (desc_ep );
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uint8_t const ep_idx = dcd_ep_alloc (ep_addr , desc_ep -> bmAttributes .xfer );
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TU_ASSERT (ep_idx < FSDEV_EP_COUNT );
@@ -649,10 +650,11 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet
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/* Create a packet memory buffer area. Enable double buffering for devices with 2048 bytes PMA,
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for smaller devices double buffering occupy too much space. */
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- uint32_t pma_addr = dcd_pma_alloc (largest_packet_size , true);
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#if FSDEV_PMA_SIZE > 1024u
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+ uint32_t pma_addr = dcd_pma_alloc (largest_packet_size , true);
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uint16_t pma_addr2 = pma_addr >> 16 ;
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#else
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+ uint32_t pma_addr = dcd_pma_alloc (largest_packet_size , false);
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uint16_t pma_addr2 = pma_addr ;
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#endif
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@@ -669,7 +671,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
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(void )rhport ;
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uint8_t const ep_addr = desc_ep -> bEndpointAddress ;
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const dir = tu_edpt_dir (ep_addr );
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+ tusb_dir_t const dir = tu_edpt_dir (ep_addr );
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , dir );
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uint8_t const ep_idx = xfer -> ep_idx ;
@@ -681,7 +683,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
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ep_change_status (& ep_reg , TUSB_DIR_IN , EP_STAT_DISABLED );
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ep_change_status (& ep_reg , TUSB_DIR_OUT , EP_STAT_DISABLED );
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ep_change_dtog (& ep_reg , dir , 0 );
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- ep_change_dtog (& ep_reg , 1 - dir , 1 );
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+ ep_change_dtog (& ep_reg , ( tusb_dir_t )( 1 - dir ) , 1 );
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ep_write (ep_idx , ep_reg , true);
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@@ -692,7 +694,6 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
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static void dcd_transmit_packet (xfer_ctl_t * xfer , uint16_t ep_ix ) {
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uint16_t len = tu_min16 (xfer -> total_len - xfer -> queued_len , xfer -> max_packet_size );
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uint32_t ep_reg = ep_read (ep_ix ) | USB_EP_CTR_TX | USB_EP_CTR_RX ; // reserve CTR
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- ep_reg &= USB_EPREG_MASK | EP_STAT_MASK (TUSB_DIR_IN ); // only change TX Status, reserve other toggle bits
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bool const is_iso = ep_is_iso (ep_reg );
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@@ -717,10 +718,11 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
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if (is_iso ) {
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xfer -> iso_in_sending = true;
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}
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+ ep_reg &= USB_EPREG_MASK | EP_STAT_MASK (TUSB_DIR_IN ); // only change TX Status, reserve other toggle bits
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ep_write (ep_ix , ep_reg , true);
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}
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- static bool edpt_xfer (uint8_t rhport , uint8_t ep_num , uint8_t dir ) {
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+ static bool edpt_xfer (uint8_t rhport , uint8_t ep_num , tusb_dir_t dir ) {
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(void ) rhport ;
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , dir );
@@ -750,7 +752,7 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_num, uint8_t dir) {
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bool dcd_edpt_xfer (uint8_t rhport , uint8_t ep_addr , uint8_t * buffer , uint16_t total_bytes ) {
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const dir = tu_edpt_dir (ep_addr );
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+ tusb_dir_t const dir = tu_edpt_dir (ep_addr );
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , dir );
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xfer -> buffer = buffer ;
@@ -763,7 +765,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
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bool dcd_edpt_xfer_fifo (uint8_t rhport , uint8_t ep_addr , tu_fifo_t * ff , uint16_t total_bytes ) {
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const dir = tu_edpt_dir (ep_addr );
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+ tusb_dir_t const dir = tu_edpt_dir (ep_addr );
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , dir );
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xfer -> buffer = NULL ;
@@ -777,7 +779,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t
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void dcd_edpt_stall (uint8_t rhport , uint8_t ep_addr ) {
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(void )rhport ;
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const dir = tu_edpt_dir (ep_addr );
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+ tusb_dir_t const dir = tu_edpt_dir (ep_addr );
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , dir );
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uint8_t const ep_idx = xfer -> ep_idx ;
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@@ -792,7 +794,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
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(void )rhport ;
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uint8_t const ep_num = tu_edpt_number (ep_addr );
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- uint8_t const dir = tu_edpt_dir (ep_addr );
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+ tusb_dir_t const dir = tu_edpt_dir (ep_addr );
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xfer_ctl_t * xfer = xfer_ctl_ptr (ep_num , dir );
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uint8_t const ep_idx = xfer -> ep_idx ;
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@@ -806,6 +808,10 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
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ep_write (ep_idx , ep_reg , true);
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}
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+ //--------------------------------------------------------------------+
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+ // PMA read/write
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+ //--------------------------------------------------------------------+
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+
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// Write to packet memory area (PMA) from user memory
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// - Packet memory must be either strictly 16-bit or 32-bit depending on FSDEV_BUS_32BIT
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// - Uses unaligned for RAM (since M0 cannot access unaligned address)
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