From 0ac8d2c163b57041b4a76486df01ba5a2b7b3b56 Mon Sep 17 00:00:00 2001 From: thefloe1 Date: Wed, 31 Mar 2021 10:20:20 +0200 Subject: [PATCH] Fix multisynth divider range in function configure_integer and configure_fractional of the _Clock class --- adafruit_si5351.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/adafruit_si5351.py b/adafruit_si5351.py index 986a1ee..3133488 100644 --- a/adafruit_si5351.py +++ b/adafruit_si5351.py @@ -306,7 +306,7 @@ def configure_integer(self, pll, divider): divider. This is the most accurate way to set the clock output frequency but supports less of a range of values. """ - assert 3 < divider < 901 + assert 3 < divider < 2049 divider = int(divider) # Make sure the PLL is configured (has a frequency set). assert pll.frequency is not None @@ -331,7 +331,7 @@ def configure_fractional(self, pll, divider, numerator, denominator): fractional divider with numerator/denominator. Again this is less accurate but has a wider range of output frequencies. """ - assert 3 < divider < 901 + assert 3 < divider < 2049 assert 0 < denominator <= 0xFFFFF # Prevent divide by zero. assert 0 <= numerator < 0xFFFFF divider = int(divider)