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removing assert statements
1 parent 9a7123b commit 23f725b

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+31
-12
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1 file changed

+31
-12
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adafruit_si5351.py

Lines changed: 31 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -169,10 +169,11 @@ def _configure_registers(self, p1, p2, p3):
169169
self._si5351._write_u8(_SI5351_REGISTER_177_PLL_RESET, (1 << 7) | (1 << 5))
170170

171171
def configure_integer(self, multiplier):
172-
"""Configure the PLL with a simple integer mulitplier for the most
172+
"""Configure the PLL with a simple integer multiplier for the most
173173
accurate (but more limited) PLL frequency generation.
174174
"""
175-
assert 14 < multiplier < 91
175+
if multiplier > 91 or multiplier < 14:
176+
raise Exception("multiplier must be between 14 and 91")
176177
multiplier = int(multiplier)
177178
# Compute register values and configure them.
178179
p1 = 128 * multiplier - 512
@@ -192,9 +193,16 @@ def configure_fractional(self, multiplier, numerator, denominator):
192193
multiplier and numerator/denominator. This is less accurate and
193194
susceptible to jitter but allows a larger range of PLL frequencies.
194195
"""
195-
assert 14 < multiplier < 91
196-
assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
197-
assert 0 <= numerator < 0xFFFFF
196+
if multiplier > 91 or multiplier < 14:
197+
raise Exception("multiplier must be between 14 and 91")
198+
if denominator > 0xFFFFF or denominator <= 0: # Prevent divide by zero.
199+
raise Exception(
200+
"denominator must be greater than 0 and lower than 0xFFFFF"
201+
)
202+
if numerator > 0xFFFFF or numerator < 0:
203+
raise Exception(
204+
"numerator must be greater than 0 and lower than 0xFFFFF"
205+
)
198206
multiplier = int(multiplier)
199207
numerator = int(numerator)
200208
denominator = int(denominator)
@@ -279,7 +287,8 @@ def r_divider(self):
279287

280288
@r_divider.setter
281289
def r_divider(self, divider):
282-
assert 0 <= divider <= 7
290+
if divider > 7 or divider < 0:
291+
raise Exception("divider must be between 0 and 7")
283292
reg_value = self._si5351._read_u8(self._r)
284293
reg_value &= 0x0F
285294
divider &= 0x07
@@ -306,10 +315,12 @@ def configure_integer(self, pll, divider):
306315
divider. This is the most accurate way to set the clock output
307316
frequency but supports less of a range of values.
308317
"""
309-
assert 3 < divider < 2049
318+
if divider >= 2049 or divider <= 3:
319+
raise Exception("divider must be between 3 and 2049")
310320
divider = int(divider)
311321
# Make sure the PLL is configured (has a frequency set).
312-
assert pll.frequency is not None
322+
if pll.frequency is None:
323+
raise Exception("PLL must be configured")
313324
# Compute MSx register values.
314325
p1 = 128 * divider - 512
315326
p2 = 0
@@ -331,14 +342,22 @@ def configure_fractional(self, pll, divider, numerator, denominator):
331342
fractional divider with numerator/denominator. Again this is less
332343
accurate but has a wider range of output frequencies.
333344
"""
334-
assert 3 < divider < 2049
335-
assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
336-
assert 0 <= numerator < 0xFFFFF
345+
if divider >= 2049 or divider <= 3:
346+
raise Exception("divider must be between 3 and 2049")
347+
if denominator > 0xFFFFF or denominator <= 0: # Prevent divide by zero.
348+
raise Exception(
349+
"denominator must be greater than 0 and lower than 0xFFFFF"
350+
)
351+
if numerator > 0xFFFFF or numerator < 0:
352+
raise Exception(
353+
"numerator must be greater than 0 and lower than 0xFFFFF"
354+
)
337355
divider = int(divider)
338356
numerator = int(numerator)
339357
denominator = int(denominator)
340358
# Make sure the PLL is configured (has a frequency set).
341-
assert pll.frequency is not None
359+
if pll.frequency is None:
360+
raise Exception("PLL must be configured")
342361
# Compute MSx register values.
343362
p1 = int(128 * divider + math.floor(128 * (numerator / denominator)) - 512)
344363
p2 = int(

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