@@ -169,10 +169,11 @@ def _configure_registers(self, p1, p2, p3):
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self ._si5351 ._write_u8 (_SI5351_REGISTER_177_PLL_RESET , (1 << 7 ) | (1 << 5 ))
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def configure_integer (self , multiplier ):
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- """Configure the PLL with a simple integer mulitplier for the most
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+ """Configure the PLL with a simple integer multiplier for the most
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accurate (but more limited) PLL frequency generation.
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"""
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- assert 14 < multiplier < 91
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+ if multiplier > 91 or multiplier < 14 :
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+ raise Exception ("multiplier must be between 14 and 91" )
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multiplier = int (multiplier )
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# Compute register values and configure them.
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p1 = 128 * multiplier - 512
@@ -192,9 +193,16 @@ def configure_fractional(self, multiplier, numerator, denominator):
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multiplier and numerator/denominator. This is less accurate and
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susceptible to jitter but allows a larger range of PLL frequencies.
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"""
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- assert 14 < multiplier < 91
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- assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
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- assert 0 <= numerator < 0xFFFFF
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+ if multiplier > 91 or multiplier < 14 :
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+ raise Exception ("multiplier must be between 14 and 91" )
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+ if denominator > 0xFFFFF or denominator <= 0 : # Prevent divide by zero.
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+ raise Exception (
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+ "denominator must be greater than 0 and lower than 0xFFFFF"
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+ )
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+ if numerator > 0xFFFFF or numerator < 0 :
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+ raise Exception (
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+ "numerator must be greater than 0 and lower than 0xFFFFF"
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+ )
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multiplier = int (multiplier )
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numerator = int (numerator )
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denominator = int (denominator )
@@ -279,7 +287,8 @@ def r_divider(self):
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@r_divider .setter
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def r_divider (self , divider ):
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- assert 0 <= divider <= 7
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+ if divider > 7 or divider < 0 :
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+ raise Exception ("divider must be between 0 and 7" )
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reg_value = self ._si5351 ._read_u8 (self ._r )
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reg_value &= 0x0F
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divider &= 0x07
@@ -306,10 +315,12 @@ def configure_integer(self, pll, divider):
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divider. This is the most accurate way to set the clock output
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frequency but supports less of a range of values.
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"""
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- assert 3 < divider < 2049
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+ if divider >= 2049 or divider <= 3 :
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+ raise Exception ("divider must be between 3 and 2049" )
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divider = int (divider )
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# Make sure the PLL is configured (has a frequency set).
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- assert pll .frequency is not None
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+ if pll .frequency is None :
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+ raise Exception ("PLL must be configured" )
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# Compute MSx register values.
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p1 = 128 * divider - 512
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p2 = 0
@@ -331,14 +342,22 @@ def configure_fractional(self, pll, divider, numerator, denominator):
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fractional divider with numerator/denominator. Again this is less
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accurate but has a wider range of output frequencies.
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"""
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- assert 3 < divider < 2049
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- assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
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- assert 0 <= numerator < 0xFFFFF
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+ if divider >= 2049 or divider <= 3 :
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+ raise Exception ("divider must be between 3 and 2049" )
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+ if denominator > 0xFFFFF or denominator <= 0 : # Prevent divide by zero.
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+ raise Exception (
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+ "denominator must be greater than 0 and lower than 0xFFFFF"
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+ )
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+ if numerator > 0xFFFFF or numerator < 0 :
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+ raise Exception (
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+ "numerator must be greater than 0 and lower than 0xFFFFF"
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+ )
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divider = int (divider )
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numerator = int (numerator )
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denominator = int (denominator )
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# Make sure the PLL is configured (has a frequency set).
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- assert pll .frequency is not None
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+ if pll .frequency is None :
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+ raise Exception ("PLL must be configured" )
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# Compute MSx register values.
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p1 = int (128 * divider + math .floor (128 * (numerator / denominator )) - 512 )
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p2 = int (
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