@@ -128,9 +128,9 @@ def configure(self, *, baudrate=100000, polarity=0, phase=0, bits=8):
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if phase not in (0 , 1 ):
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raise ValueError ("phase must be either 0 or 1" )
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self ._baudrate = baudrate
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- self ._bits = bits
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self ._polarity = polarity
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self ._phase = phase
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+ self ._bits = bits
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self ._half_period = (1 / self ._baudrate ) / 2 # 50% Duty Cyle delay
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else :
@@ -156,18 +156,19 @@ def write(self, buffer, start=0, end=None):
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for byte in buffer [start :end ]:
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for bit_position in range (self ._bits ):
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bit_value = byte & 0x80 >> bit_position
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- # Flip clock off base
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- self ._sclk .value = 0
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- start_time = self ._wait (start_time )
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- # Write bit to MOSI.
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- if not self ._phase : # Mode 1, 3
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+ # Set clock to base
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+ if not self ._phase : # Mode 0, 2
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self ._mosi .value = bit_value
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- # Return clock to base
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- self ._sclk .value = 1
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+ self ._sclk .value = self ._polarity
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start_time = self ._wait (start_time )
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- if self ._phase : # Mode 0, 2
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+
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+ # Flip clock off base
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+ if self ._phase : # Mode 1, 3
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self ._mosi .value = bit_value
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- # Return pins to resting positions
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+ self ._sclk .value = not self ._polarity
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+ start_time = self ._wait (start_time )
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+
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+ # Return pins to base positions
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self ._mosi .value = 0
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self ._sclk .value = self ._polarity
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@@ -184,11 +185,11 @@ def readinto(self, buffer, start=0, end=None, write_value=0):
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for bit_position in range (self ._bits ):
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bit_mask = 0x80 >> bit_position
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bit_value = write_value & 0x80 >> bit_position
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- # Return clock to 0
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- self ._sclk .value = 0
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+ # Return clock to base
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+ self ._sclk .value = self . _polarity
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start_time = self ._wait (start_time )
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# Handle read on leading edge of clock.
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- if not self ._phase :
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+ if not self ._phase : # Mode 0, 2
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if self ._mosi is not None :
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self ._mosi .value = bit_value
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if self ._miso .value :
@@ -198,10 +199,10 @@ def readinto(self, buffer, start=0, end=None, write_value=0):
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# Set bit to 0 at appropriate location.
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buffer [byte_position ] &= ~ bit_mask
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# Flip clock off base
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- self ._sclk .value = 1
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+ self ._sclk .value = not self . _polarity
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start_time = self ._wait (start_time )
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# Handle read on trailing edge of clock.
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- if self ._phase :
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+ if self ._phase : # Mode 1, 3
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if self ._mosi is not None :
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self ._mosi .value = bit_value
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if self ._miso .value :
@@ -211,7 +212,7 @@ def readinto(self, buffer, start=0, end=None, write_value=0):
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# Set bit to 0 at appropriate location.
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buffer [byte_position ] &= ~ bit_mask
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- # Return pins to resting positions
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+ # Return pins to base positions
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self ._mosi .value = 0
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self ._sclk .value = self ._polarity
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@@ -249,10 +250,10 @@ def write_readinto(
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bit_value = buffer_out [byte_position + out_start ] & 0x80 >> bit_position
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in_byte_position = byte_position + in_start
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# Return clock to 0
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- self ._sclk .value = 0
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+ self ._sclk .value = self . _polarity
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start_time = self ._wait (start_time )
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# Handle read on leading edge of clock.
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- if not self ._phase :
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+ if not self ._phase : # Mode 0, 2
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self ._mosi .value = bit_value
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if self ._miso .value :
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# Set bit to 1 at appropriate location.
@@ -261,10 +262,10 @@ def write_readinto(
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# Set bit to 0 at appropriate location.
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buffer_in [in_byte_position ] &= ~ bit_mask
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# Flip clock off base
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- self ._sclk .value = 1
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+ self ._sclk .value = not self . _polarity
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start_time = self ._wait (start_time )
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# Handle read on trailing edge of clock.
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- if self ._phase :
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+ if self ._phase : # Mode 1, 3
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self ._mosi .value = bit_value
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if self ._miso .value :
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# Set bit to 1 at appropriate location.
@@ -273,6 +274,10 @@ def write_readinto(
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# Set bit to 0 at appropriate location.
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buffer_in [in_byte_position ] &= ~ bit_mask
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+ # Return pins to base positions
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+ self ._mosi .value = 0
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+ self ._sclk .value = self ._polarity
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+
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# pylint: enable=too-many-branches
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@property
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