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31 | 31 | #define MII_DP83822_RCSR 0x17
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32 | 32 | #define MII_DP83822_RESET_CTRL 0x1f
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33 | 33 | #define MII_DP83822_MLEDCR 0x25
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| 34 | +#define MII_DP83822_LDCTRL 0x403 |
34 | 35 | #define MII_DP83822_LEDCFG1 0x460
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35 | 36 | #define MII_DP83822_IOCTRL1 0x462
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36 | 37 | #define MII_DP83822_IOCTRL2 0x463
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123 | 124 | #define DP83822_IOCTRL1_GPIO1_CTRL GENMASK(2, 0)
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124 | 125 | #define DP83822_IOCTRL1_GPIO1_CTRL_LED_1 BIT(0)
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125 | 126 |
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| 127 | +/* LDCTRL bits */ |
| 128 | +#define DP83822_100BASE_TX_LINE_DRIVER_SWING GENMASK(7, 4) |
| 129 | + |
126 | 130 | /* IOCTRL2 bits */
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127 | 131 | #define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)
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128 | 132 | #define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)
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@@ -197,6 +201,7 @@ struct dp83822_private {
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197 | 201 | bool set_gpio2_clk_out;
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198 | 202 | u32 gpio2_clk_out;
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199 | 203 | bool led_pin_enable[DP83822_MAX_LED_PINS];
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| 204 | + int tx_amplitude_100base_tx_index; |
200 | 205 | };
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201 | 206 |
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202 | 207 | static int dp83822_config_wol(struct phy_device *phydev,
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@@ -522,6 +527,12 @@ static int dp83822_config_init(struct phy_device *phydev)
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522 | 527 | FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC,
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523 | 528 | dp83822->gpio2_clk_out));
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524 | 529 |
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| 530 | + if (dp83822->tx_amplitude_100base_tx_index >= 0) |
| 531 | + phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_LDCTRL, |
| 532 | + DP83822_100BASE_TX_LINE_DRIVER_SWING, |
| 533 | + FIELD_PREP(DP83822_100BASE_TX_LINE_DRIVER_SWING, |
| 534 | + dp83822->tx_amplitude_100base_tx_index)); |
| 535 | + |
525 | 536 | err = dp83822_config_init_leds(phydev);
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526 | 537 | if (err)
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527 | 538 | return err;
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@@ -720,6 +731,11 @@ static int dp83822_phy_reset(struct phy_device *phydev)
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720 | 731 | }
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721 | 732 |
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722 | 733 | #ifdef CONFIG_OF_MDIO
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| 734 | +static const u32 tx_amplitude_100base_tx_gain[] = { |
| 735 | + 80, 82, 83, 85, 87, 88, 90, 92, |
| 736 | + 93, 95, 97, 98, 100, 102, 103, 105, |
| 737 | +}; |
| 738 | + |
723 | 739 | static int dp83822_of_init_leds(struct phy_device *phydev)
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724 | 740 | {
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725 | 741 | struct device_node *node = phydev->mdio.dev.of_node;
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@@ -780,6 +796,8 @@ static int dp83822_of_init(struct phy_device *phydev)
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780 | 796 | struct dp83822_private *dp83822 = phydev->priv;
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781 | 797 | struct device *dev = &phydev->mdio.dev;
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782 | 798 | const char *of_val;
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| 799 | + int i, ret; |
| 800 | + u32 val; |
783 | 801 |
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784 | 802 | /* Signal detection for the PHY is only enabled if the FX_EN and the
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785 | 803 | * SD_EN pins are strapped. Signal detection can only enabled if FX_EN
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@@ -815,6 +833,26 @@ static int dp83822_of_init(struct phy_device *phydev)
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815 | 833 | dp83822->set_gpio2_clk_out = true;
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816 | 834 | }
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817 | 835 |
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| 836 | + dp83822->tx_amplitude_100base_tx_index = -1; |
| 837 | + ret = phy_get_tx_amplitude_gain(phydev, dev, |
| 838 | + ETHTOOL_LINK_MODE_100baseT_Full_BIT, |
| 839 | + &val); |
| 840 | + if (!ret) { |
| 841 | + for (i = 0; i < ARRAY_SIZE(tx_amplitude_100base_tx_gain); i++) { |
| 842 | + if (tx_amplitude_100base_tx_gain[i] == val) { |
| 843 | + dp83822->tx_amplitude_100base_tx_index = i; |
| 844 | + break; |
| 845 | + } |
| 846 | + } |
| 847 | + |
| 848 | + if (dp83822->tx_amplitude_100base_tx_index < 0) { |
| 849 | + phydev_err(phydev, |
| 850 | + "Invalid value for tx-amplitude-100base-tx-percent property (%u)\n", |
| 851 | + val); |
| 852 | + return -EINVAL; |
| 853 | + } |
| 854 | + } |
| 855 | + |
818 | 856 | return dp83822_of_init_leds(phydev);
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819 | 857 | }
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820 | 858 |
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