From 97ea31dec0fc6cda40914dee25ffae722fcbf9ef Mon Sep 17 00:00:00 2001 From: jeanlego Date: Wed, 11 Dec 2019 00:44:43 -0400 Subject: [PATCH 001/107] Fix regression flow wrongly included test (#1061) this commit also: - add helpfull errors on missing packages - add facility to only run subset of task - fix the overrides of config files, must specify that we want to override - add method to forcefully disable coloring in case we can't pick up that its a CI --- ODIN_II/exec_wrapper.sh | 72 +- .../.library/output_on_error.conf | 4 +- ODIN_II/verify_odin.sh | 750 ++++++++++-------- 3 files changed, 478 insertions(+), 348 deletions(-) diff --git a/ODIN_II/exec_wrapper.sh b/ODIN_II/exec_wrapper.sh index 711f9f084d6..20c20564e06 100755 --- a/ODIN_II/exec_wrapper.sh +++ b/ODIN_II/exec_wrapper.sh @@ -23,6 +23,8 @@ PERF_EXEC="perf stat record -a -d -d -d -o" GDB_EXEC="gdb --args" EXEC_PREFIX="" +TOOL_LIST="" + TEST_NAME="N/A" LOG="" LOG_FILE="" @@ -98,6 +100,7 @@ Usage: ./exec_wrapper.sh [options] --time_limit * stops Odin after X seconds --limit_ressource * limit ressource usage using ulimit -m (25% of hrdw memory) and nice value of 19 --verbosity [0, 1, 2] * [0] no output, [1] output on error, [2] output the log to stdout + --no_color * force no color on output " } @@ -213,6 +216,12 @@ then _exit_with_code "-1" fi +if [[ -t 1 ]] && [[ -t 2 ]] && [[ ! -p /dev/stdout ]] && [[ ! -p /dev/stderr ]] +then + COLORIZE_OUTPUT="on" + log_it "Using colorized output\n" +fi + while [[ "$#" > 0 ]] do case $1 in @@ -242,6 +251,10 @@ do RESTRICT_RESSOURCE="on" ;; + --no_color) + COLORIZE_OUTPUT="off" + ;; + --verbosity) case "_$2" in _0) VERBOSE="0";; @@ -267,14 +280,17 @@ do else case $2 in valgrind) + TOOL_LIST="valgrind ${TOOL_LIST}" EXEC_PREFIX="${VALGRIND_EXEC} ${EXEC_PREFIX}" ;; gdb) + TOOL_LIST="gdb ${TOOL_LIST}" USE_TIMEOUT="off" USE_LOGS="off" EXEC_PREFIX="${GDB_EXEC} ${EXEC_PREFIX}" ;; perf) + TOOL_LIST="perf ${TOOL_LIST}" EXEC_PREFIX="${PERF_EXEC} ${EXEC_PREFIX}" shift ;; @@ -302,13 +318,6 @@ then restrict_ressource fi - -if [[ -t 1 ]] && [[ -t 2 ]] && [[ ! -p /dev/stdout ]] && [[ ! -p /dev/stderr ]] -then - COLORIZE_OUTPUT="on" - log_it "Using colorized output\n" -fi - if [ "${USE_LOGS}" == "on" ] then if [ "_${LOG_FILE}" == "_" ] @@ -331,12 +340,14 @@ fi if [ "${USE_TIME}" == "on" ] then + TOOL_LIST="time ${TOOL_LIST}" EXEC_PREFIX="${TIME_EXEC} --output=${LOG_FILE} --append ${EXEC_PREFIX}" log_it "running with /bin/time\n" fi if [ "${USE_TIMEOUT}" == "on" ] then + TOOL_LIST="timeout ${TOOL_LIST}" EXEC_PREFIX="timeout ${TIME_LIMIT} ${EXEC_PREFIX}" log_it "running with timeout ${TIME_LIMIT}\n" fi @@ -352,23 +363,52 @@ then log_it "Must define a path to a valid argument file" dump_log else - _ARGS=$(cat ${ARG_FILE}) - if [ "${USE_LOGS}" == "on" ] + failed_requirements="" + # test all necessary tool + for tool_used in ${TOOL_LIST} + do + which ${tool_used} &> /dev/null + if [ "$?" != "0" ]; + then + failed_requirements="${tool_used} ${failed_requirements}" + fi + done + + if [ "_${failed_requirements}" != "_" ]; then - if [ "${VERBOSE}" == "2" ] + if [ "${USE_LOGS}" == "on" ] then - ${EXEC_PREFIX} ${_ARGS} 2>&1 | tee ${LOG_FILE} + if [ "${VERBOSE}" == "2" ] + then + echo "missing \"${failed_requirements}\"" | tee ${LOG_FILE} + else + echo "missing \"${failed_requirements}\"" &>> ${LOG_FILE} + fi else - ${EXEC_PREFIX} ${_ARGS} &>> ${LOG_FILE} + echo "missing \"${failed_requirements}\"" fi + + EXIT_CODE="-1" + pretty_print_status "Missing package: ${failed_requirements}" + else - ${EXEC_PREFIX} ${_ARGS} + _ARGS=$(cat ${ARG_FILE}) + if [ "${USE_LOGS}" == "on" ] + then + if [ "${VERBOSE}" == "2" ] + then + ${EXEC_PREFIX} ${_ARGS} 2>&1 | tee ${LOG_FILE} + else + ${EXEC_PREFIX} ${_ARGS} &>> ${LOG_FILE} + fi + else + ${EXEC_PREFIX} ${_ARGS} + fi + EXIT_CODE=$? + display "${EXIT_CODE}" fi - EXIT_CODE=$? fi -display "${EXIT_CODE}" - EXIT_STATUS=0 if [ "${EXIT_CODE}" != "0" ] then diff --git a/ODIN_II/regression_test/.library/output_on_error.conf b/ODIN_II/regression_test/.library/output_on_error.conf index 7db9a08a2f6..c13223adb16 100644 --- a/ODIN_II/regression_test/.library/output_on_error.conf +++ b/ODIN_II/regression_test/.library/output_on_error.conf @@ -1,2 +1,2 @@ -script_synthesis_params=--verbosity 1 -script_simulation_params=--verbosity 1 \ No newline at end of file +script_synthesis_params=--verbosity 1 --no_color +script_simulation_params=--verbosity 1 --no_color \ No newline at end of file diff --git a/ODIN_II/verify_odin.sh b/ODIN_II/verify_odin.sh index 1f1ad028cbc..ec61de0cf03 100755 --- a/ODIN_II/verify_odin.sh +++ b/ODIN_II/verify_odin.sh @@ -23,7 +23,17 @@ ODIN_EXEC="${THIS_DIR}/odin_II" BENCHMARK_DIR="${REGRESSION_DIR}/benchmark" -TEST_DIR_LIST=$(ls -d ${BENCHMARK_DIR}/*/ | sed "s/\/$//g" | xargs -n1 -I TEST_FILE /bin/bash -c 'printf "$(basename TEST_FILE) "') + +VTR_REG_DIR="${THIS_DIR}/../vtr_flow/tasks/regression_tests" +VTR_REG_LIST=$(ls ${VTR_REG_DIR} | grep "vtr_reg") + +SUITE_DIR="${BENCHMARK_DIR}/suite" +SUITE_LIST=$(ls ${SUITE_DIR}) + +TASK_DIR="${BENCHMARK_DIR}/task" +TASK_LIST=$(ls ${TASK_DIR}) + +PREVIOUS_RUN_DIR="" NEW_RUN_DIR="${REGRESSION_DIR}/run001/" ############################################## @@ -63,12 +73,14 @@ _prt_cur_arg() { ############## # defaults _TEST="" +_TEST_NAME="" +_SUBTEST_LIST="" _NUMBER_OF_PROCESS="1" _SIM_COUNT="1" _RUN_DIR_OVERRIDE="" +_EXTRA_CONFIG="" -_CONFIG_OVERRIDE="" - +_OVERRIDE_CONFIG="off" _GENERATE_BENCH="off" _GENERATE_OUTPUT="off" _GENERATE_CONFIG="off" @@ -78,22 +90,41 @@ function help() { printf "Called program with $INPUT Usage: - $0 [ OPTIONS / FLAGS ] + $0 [ OPTIONS / FLAGS ] [ SUBTEST_LIST ... ] + SUBTEST_LIST + should be a list of the form < task_name/test_file_name/architecture_file_name > + passing this in will limit a task to a subset of test + current: $(_prt_cur_arg ${_SUBTEST_LIST}) - OPTIONS: - -h|--help $(_prt_cur_arg off) print this - -t|--test < test name > $(_prt_cur_arg ${_TEST}) Test name is one of ( ${TEST_DIR_LIST} heavy_suite light_suite full_suite vtr_basic vtr_strong pre_commit pre_merge) - -j|--nb_of_process < N > $(_prt_cur_arg ${_NUMBER_OF_PROCESS}) Number of process requested to be used - -d|--output_dir < /abs/path > $(_prt_cur_arg ${_RUN_DIR_OVERRIDE}) Change the run directory output - -C|--config $(_prt_cur_arg ${_CONFIG_OVERRIDE}) Add a config override file - - FLAGS: + FLAGS -g|--generate_bench $(_prt_cur_arg ${_GENERATE_BENCH}) Generate input and output vector for test -o|--generate_output $(_prt_cur_arg ${_GENERATE_OUTPUT}) Generate output vector for test given its input vector -b|--build_config $(_prt_cur_arg ${_GENERATE_CONFIG}) Generate a config file for a given directory -c|--clean $(_prt_cur_arg off ) Clean temporary directory -f|--force_simulate $(_prt_cur_arg ${_FORCE_SIM}) Force the simulation to be executed regardless of the config + --override $(_prt_cur_arg ${_OVERRIDE_CONFIG}) if a config file is passed in, override arguments rather than append + + OPTIONS + -h|--help $(_prt_cur_arg off) print this + -j|--nb_of_process < N > $(_prt_cur_arg ${_NUMBER_OF_PROCESS}) Number of process requested to be used + -d|--output_dir < /abs/path > $(_prt_cur_arg ${_RUN_DIR_OVERRIDE}) Change the run directory output + -C|--config $(_prt_cur_arg ${_EXTRA_CONFIG}) Add a config file to append to the config for the tests + -t|--test < test name > $(_prt_cur_arg ${_TEST}) Test name is either a absolute or relative path to + a directory containing a task.conf, task_list.conf + (see CONFIG FILE HELP) or one of the following predefined test + + AVAILABLE_TEST: + + regression_test/benchmark/suite/ +$( echo "${SUITE_LIST}" | awk '{print "\t " $0}') + + regression_test/benchmark/task/ +$( echo "${TASK_LIST}" | awk '{print "\t " $0}') + + vtr_reg_ +$( echo "${VTR_REG_LIST}" | awk '{print "\t " substr($0,9)}') + CONFIG FILE HELP: " @@ -131,11 +162,11 @@ function init_temp() { OUTPUT_DIRECTORY=${_RUN_DIR_OVERRIDE} fi - last_run=$(find ${OUTPUT_DIRECTORY}/run* -maxdepth 0 -type d 2>/dev/null | tail -1 ) + PREVIOUS_RUN_DIR=$(find ${OUTPUT_DIRECTORY}/run* -maxdepth 0 -type d 2>/dev/null | tail -1 ) n="1" - if [ "_${last_run}" != "_" ] + if [ "_${PREVIOUS_RUN_DIR}" != "_" ] then - n=$(echo ${last_run##${OUTPUT_DIRECTORY}/run} | awk '{print $0 + 1}') + n=$(echo ${PREVIOUS_RUN_DIR##${OUTPUT_DIRECTORY}/run} | awk '{print $0 + 1}') fi NEW_RUN_DIR=${OUTPUT_DIRECTORY}/run$(printf "%03d" $n) @@ -150,6 +181,11 @@ function create_temp() { rm -Rf ${REGRESSION_DIR}/latest || /bin/true ln -s ${NEW_RUN_DIR} ${REGRESSION_DIR}/latest + + # put in the passed parameter for keepsake + echo ${_TEST} > ${NEW_RUN_DIR}/cmd.task + echo "=========" + echo "$0 ${INPUT}" >> ${NEW_RUN_DIR}/cmd.task fi } @@ -212,94 +248,108 @@ function mv_failed() { fi } + function parse_args() { + PARSE_SUBTEST="off" while [[ "$#" > 0 ]] do - case $1 in + if [ ${PARSE_SUBTEST} == "on" ]; + then + # parse subtest + _SUBTEST_LIST="$1 ${_SUBTEST_LIST}" + shift + else + # parse [ OPTIONS / FLAGS ] + case $1 in - # Help Desk - -h|--help) - echo "Printing Help information" - help - _exit_with_code "0" + # Help Desk + -h|--help) + echo "Printing Help information" + help + _exit_with_code "0" - - ## directory in benchmark - ;;-t|--test) - # this is handled down stream - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi + + ## directory in benchmark + ;;-t|--test) + # this is handled down stream + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _TEST="$2" + shift + + ;;-d|--output_dir) + + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _RUN_DIR_OVERRIDE=$2 - _TEST="$2" - shift + if [ ! -d "${_RUN_DIR_OVERRIDE}" ] + then + echo "Directory ${_RUN_DIR_OVERRIDE} does not exist" + _exit_with_code "-1" + fi - ;;-d|--output_dir) + shift - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi - - _RUN_DIR_OVERRIDE=$2 + ;;-C|--config) - if [ ! -d "${_RUN_DIR_OVERRIDE}" ] - then - echo "Directory ${_RUN_DIR_OVERRIDE} does not exist" - _exit_with_code "-1" - fi + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _EXTRA_CONFIG=$2 + echo "Reading extra config directive from ${_EXTRA_CONFIG}" - shift + shift - ;;-C|--config) + ## number + ;;-j|--nb_of_process) + _NUMBER_OF_PROCESS=$(_flag_is_number $1 $2) + echo "Using [$2] processors for this benchmarking suite" + shift - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi - - _CONFIG_OVERRIDE=$2 - echo "Reading override from ${_CONFIG_OVERRIDE}" + # Boolean flags + ;;-g|--generate_bench) + _GENERATE_BENCH="on" + echo "generating output vector for test given predefined input" - shift + ;;-o|--generate_output) + _GENERATE_OUTPUT="on" + echo "generating input and output vector for test" - ## number - ;;-j|--nb_of_process) - _NUMBER_OF_PROCESS=$(_flag_is_number $1 $2) - echo "Using [$2] processors for this benchmarking suite" - shift + ;;-b|--build_config) + _GENERATE_CONFIG="on" + echo "generating a config file for test directory" - # Boolean flags - ;;-g|--generate_bench) - _GENERATE_BENCH="on" - echo "generating output vector for test given predefined input" + ;;-c|--clean) + echo "Cleaning temporary run in directory" + cleanup_temp - ;;-o|--generate_output) - _GENERATE_OUTPUT="on" - echo "generating input and output vector for test" + ;;-f|--force_simulate) + _FORCE_SIM="on" + echo "Forcing Simulation" - ;;-b|--build_config) - _GENERATE_CONFIG="on" - echo "generating a config file for test directory" + ;;--override) + _OVERRIDE_CONFIG="on" + echo "Forcing override of config" - ;;-c|--clean) - echo "Cleaning temporary run in directory" - cleanup_temp - - ;;-f|--force_simulate) - _FORCE_SIM="on" - echo "Forcing Simulation" + ;;*) + PARSE_SUBTEST="on" + esac - ;;*) - echo "Unknown parameter passed: $1" - help - _exit_with_code "-1" - esac - shift + # keep the subtest in case we caught the end of options and flags + [ ${PARSE_SUBTEST} != "on" ] && shift + fi done } @@ -440,11 +490,21 @@ function populate_arg_from_file() { IFS=${OLD_IFS} fi - _regression_params=$(echo "${_local_regression_params} ") - _script_simulation_params=$(echo "${_local_script_simulation_params} ") - _script_synthesis_params=$(echo "${_local_script_synthesis_params} ") - _synthesis_params=$(echo "${_local_synthesis_params} ") - _simulation_params=$(echo "${_local_simulation_params} ") + if [ "${_OVERRIDE_CONFIG}" == "on" ]; + then + _regression_params=$(echo "${_local_regression_params} ") + _script_simulation_params=$(echo "${_local_script_simulation_params} ") + _script_synthesis_params=$(echo "${_local_script_synthesis_params} ") + _synthesis_params=$(echo "${_local_synthesis_params} ") + _simulation_params=$(echo "${_local_simulation_params} ") + else + _regression_params=$(echo "${_local_regression_params} ${_regression_params} ") + _script_simulation_params=$(echo "${_local_script_simulation_params} ${_script_simulation_params} ") + _script_synthesis_params=$(echo "${_local_script_synthesis_params} ${_script_synthesis_params}") + _synthesis_params=$(echo "${_local_synthesis_params} ${_synthesis_params}") + _simulation_params=$(echo "${_local_simulation_params} ${_simulation_params}") + fi + _circuit_list=$(echo "${_circuit_list} ") _arch_list=$(echo "${_arch_list} ") _circuit_dir=$(echo "${THIS_DIR}/${_circuit_dir}") @@ -560,7 +620,6 @@ function run_bench_in_parallel() { function sim() { - ########################################### # find the benchmark benchmark_dir=$1 @@ -577,283 +636,314 @@ function sim() { benchmark_dir=$(readlink -f "${benchmark_dir}") bench_name=$(basename ${benchmark_dir}) - echo "Task is: ${bench_name}" - ########################################## - # setup the parameters + # check if we only run some subtask + run_benchmark="off" + if [ "_${_SUBTEST_LIST}" == "_" ]; + then + run_benchmark="on" + else + for subtest in ${_SUBTEST_LIST}; + do + if [ "_${subtest%%/*}" == "_${bench_name}" ] + then + run_benchmark="on" + break; + fi + done + fi + + if [ "${run_benchmark}" == "on" ]; + then + echo "Task is: ${bench_name}" - init_args_for_test - populate_arg_from_file "${benchmark_dir}/task.conf" + ########################################## + # setup the parameters - ########################################## - # use the overrides from the user - if [ "_${_CONFIG_OVERRIDE}" != "_" ] - then - _CONFIG_OVERRIDE=$(readlink -f ${_CONFIG_OVERRIDE}) - if [ ! -f ${_CONFIG_OVERRIDE} ] + init_args_for_test + populate_arg_from_file "${benchmark_dir}/task.conf" + + ########################################## + # use the overrides from the user + if [ "_${_EXTRA_CONFIG}" != "_" ] then - echo "Passed in an invalid global configuration file ${_CONFIG_OVERRIDE}" - _exit_with_code "-1" - else - populate_arg_from_file "${_CONFIG_OVERRIDE}" + _EXTRA_CONFIG=$(readlink -f ${_EXTRA_CONFIG}) + if [ ! -f ${_EXTRA_CONFIG} ] + then + echo "Passed in an invalid global configuration file ${_EXTRA_CONFIG}" + _exit_with_code "-1" + else + populate_arg_from_file "${_EXTRA_CONFIG}" + fi fi - fi - #################################### - # parse the function commands passed - _threads=${_NUMBER_OF_PROCESS} - _generate_bench="off" - _generate_output="off" - _concat_circuit_list="off" - _synthesis="on" - _simulation="on" + #################################### + # parse the function commands passed + _threads=${_NUMBER_OF_PROCESS} + _generate_bench="off" + _generate_output="off" + _concat_circuit_list="off" + _synthesis="on" + _simulation="on" + + ########################################## + # populate the wrapper command using the configs + for _regression_param in ${_regression_params} + do + case ${_regression_param} in - ########################################## - # populate the wrapper command using the configs - for _regression_param in ${_regression_params} - do - case ${_regression_param} in + --concat_circuit_list) + _concat_circuit_list="on" + ;; - --concat_circuit_list) - _concat_circuit_list="on" - ;; + --generate_bench) + echo "This test will have the input and output regenerated" + _generate_bench="on" + ;; - --generate_bench) - echo "This test will have the input and output regenerated" - _generate_bench="on" - ;; + --generate_output) + echo "This test will have the output regenerated" + _generate_output="on" + ;; - --generate_output) - echo "This test will have the output regenerated" - _generate_output="on" - ;; + --disable_simulation) + echo "This test will not be simulated" + if [ "_${_FORCE_SIM}" == "on" ] + then + echo "WARNING: This test will be forcefully simulated, unexpected results may occur" + _simulation="on" + else + _simulation="off" + fi + ;; + + --disable_parallel_jobs) + echo "This test will not be multithreaded" + _threads="1" + ;; + + --include_default_arch) + _arch_list="no_arch ${_arch_list}" + ;; - --disable_simulation) - echo "This test will not be simulated" - if [ "_${_FORCE_SIM}" == "on" ] - then - echo "WARNING: This test will be forcefully simulated, unexpected results may occur" - _simulation="on" - else - _simulation="off" - fi - ;; - - --disable_parallel_jobs) - echo "This test will not be multithreaded" - _threads="1" + *) + echo "Unknown internal parameter passed: ${_regression_param}" + config_help + _exit_with_code "-1" + ;; + esac + done + + ########################################## + # setup defaults + global_synthesis_failure="${NEW_RUN_DIR}/synthesis_failures" + global_simulation_failure="${NEW_RUN_DIR}/simulation_failures" + + wrapper_synthesis_file_name="wrapper_synthesis_params" + wrapper_simulation_generate_io_file_name="wrapper_simulation_generate_io_file_name" + wrapper_simulation_generate_output_file_name="wrapper_simulation_generate_output_file_name" + wrapper_simulation_predefined_io_file_name="wrapper_simulation_predefined_io_file_name" + + circuit_list_temp="" + if [ ${_concat_circuit_list} == "on" ] + then + circuit_list_temp="$(echo ${_circuit_list} | sed 's/\n/ /g')" + _circuit_list=${bench_name} + fi + + for circuit in $(echo ${_circuit_list}) + do + circuit_dir=$(dirname ${circuit}) + circuit_file=$(basename ${circuit}) + input_verilog_file="" + input_blif_file="" + + case "${circuit_file}" in + *.v) + input_verilog_file="${circuit}" + _synthesis="on" ;; - - --include_default_arch) - _arch_list="no_arch ${_arch_list}" + *.blif) + input_blif_file="${circuit}" + # disable synthesis for blif files + _synthesis="off" ;; - - *) - echo "Unknown internal parameter passed: ${_regression_param}" - config_help - _exit_with_code "-1" + *) + if [ ${_concat_circuit_list} == "on" ] + then + input_verilog_file="${circuit_list_temp}" + _synthesis="on" + else + echo "Invalid circuit passed in: ${circuit}, skipping" + continue + fi ;; - esac - done - - ########################################## - # setup defaults - global_synthesis_failure="${NEW_RUN_DIR}/synthesis_failures" - global_simulation_failure="${NEW_RUN_DIR}/simulation_failures" + esac + circuit_name="${circuit_file%.*}" - wrapper_synthesis_file_name="wrapper_synthesis_params" - wrapper_simulation_generate_io_file_name="wrapper_simulation_generate_io_file_name" - wrapper_simulation_generate_output_file_name="wrapper_simulation_generate_output_file_name" - wrapper_simulation_predefined_io_file_name="wrapper_simulation_predefined_io_file_name" - circuit_list_temp="" - if [ ${_concat_circuit_list} == "on" ] - then - circuit_list_temp="$(echo ${_circuit_list} | sed 's/\n/ /g')" - _circuit_list=${bench_name} - fi + # lookup for input and output vector files to do comparison + input_vector_file="${circuit_dir}/${circuit_name}_input" + output_vector_file="${circuit_dir}/${circuit_name}_output" - for circuit in $(echo ${_circuit_list}) - do - circuit_dir=$(dirname ${circuit}) - circuit_file=$(basename ${circuit}) - input_verilog_file="" - input_blif_file="" - - case "${circuit_file}" in - *.v) - input_verilog_file="${circuit}" - _synthesis="on" - ;; - *.blif) - input_blif_file="${circuit}" - # disable synthesis for blif files - _synthesis="off" - ;; - *) - if [ ${_concat_circuit_list} == "on" ] + for arches in $(echo ${_arch_list}) + do + arch_cmd="" + if [ -e ${arches} ] then - input_verilog_file="${circuit_list_temp}" - _synthesis="on" - else - echo "Invalid circuit passed in: ${circuit}, skipping" - continue + arch_cmd="-a ${arches}" fi - ;; - esac - circuit_name="${circuit_file%.*}" + arch_name=$(basename ${arches%.*}) - # lookup for input and output vector files to do comparison - input_vector_file="${circuit_dir}/${circuit_name}_input" - output_vector_file="${circuit_dir}/${circuit_name}_output" + TEST_FULL_REF="${bench_name}/${circuit_name}/${arch_name}" - for arches in $(echo ${_arch_list}) - do - arch_cmd="" - if [ -e ${arches} ] - then - arch_cmd="-a ${arches}" - fi + run_this_test="on" - arch_name=$(basename ${arches%.*}) - - TEST_FULL_REF="${bench_name}/${circuit_name}/${arch_name}" - DIR="${NEW_RUN_DIR}/${TEST_FULL_REF}" - mkdir -p $DIR - - ############################### - # Synthesis - if [ "${_synthesis}" == "on" ] - then - - # if synthesis was on, we need to specify a blif output name - input_blif_file="${DIR}/${circuit_name}.blif" - - synthesis_params_file=${DIR}/synthesis_params - - wrapper_command="${WRAPPER_EXEC} - ${_script_synthesis_params} - --log_file ${DIR}/synthesis.log - --test_name ${TEST_FULL_REF} - --failure_log ${global_synthesis_failure}.log - ${synthesis_params_file}" - - synthesis_command="${ODIN_EXEC} - ${_synthesis_params} - ${arch_cmd} - -V ${input_verilog_file} - -o ${input_blif_file} - -sim_dir ${DIR}" - - _echo_args "${synthesis_command}" > ${synthesis_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_synthesis_file_name} - fi - ############################### - # Simulation - if [ "${_simulation}" == "on" ] - then - simulation_params_file=${DIR}/simulation_params - - wrapper_command="${WRAPPER_EXEC} - ${_script_simulation_params} - --log_file ${DIR}/simulation.log - --test_name ${TEST_FULL_REF} - --failure_log ${global_simulation_failure}.log - ${simulation_params_file}" - - simulation_command="${ODIN_EXEC} - ${_simulation_params} - ${arch_cmd} - -b ${input_blif_file} - -sim_dir ${DIR}" - - if [ "${_GENERATE_BENCH}" == "on" ] || [ ! -f ${input_vector_file} ] + if [ "_${_SUBTEST_LIST}" != "_" ]; then - _echo_args "${simulation_command}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_io_file_name} + echo ${_SUBTEST_LIST} | grep "${TEST_FULL_REF}" &> /dev/null + [ "$?" != "0" ] && run_this_test="off" + fi - elif [ "${_GENERATE_OUTPUT}" == "on" ] || [ ! -f ${output_vector_file} ] + if [ "${run_this_test}" == "on" ]; then - _echo_args "${simulation_command} -t ${input_vector_file}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_output_file_name} - else - _echo_args "${simulation_command} -t ${input_vector_file} -T ${output_vector_file}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_predefined_io_file_name} + DIR="${NEW_RUN_DIR}/${TEST_FULL_REF}" + mkdir -p $DIR + ############################### + # Synthesis + if [ "${_synthesis}" == "on" ] + then + + # if synthesis was on, we need to specify a blif output name + input_blif_file="${DIR}/${circuit_name}.blif" + + synthesis_params_file=${DIR}/synthesis_params + + wrapper_command="${WRAPPER_EXEC} + ${_script_synthesis_params} + --log_file ${DIR}/synthesis.log + --test_name ${TEST_FULL_REF} + --failure_log ${global_synthesis_failure}.log + ${synthesis_params_file}" + + synthesis_command="${ODIN_EXEC} + ${_synthesis_params} + ${arch_cmd} + -V ${input_verilog_file} + -o ${input_blif_file} + -sim_dir ${DIR}" + + _echo_args "${synthesis_command}" > ${synthesis_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_synthesis_file_name} + fi + ############################### + # Simulation + if [ "${_simulation}" == "on" ] + then + simulation_params_file=${DIR}/simulation_params + + wrapper_command="${WRAPPER_EXEC} + ${_script_simulation_params} + --log_file ${DIR}/simulation.log + --test_name ${TEST_FULL_REF} + --failure_log ${global_simulation_failure}.log + ${simulation_params_file}" + + simulation_command="${ODIN_EXEC} + ${_simulation_params} + ${arch_cmd} + -b ${input_blif_file} + -sim_dir ${DIR}" + + if [ "${_GENERATE_BENCH}" == "on" ] || [ ! -f ${input_vector_file} ] + then + _echo_args "${simulation_command}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_io_file_name} + + elif [ "${_GENERATE_OUTPUT}" == "on" ] || [ ! -f ${output_vector_file} ] + then + _echo_args "${simulation_command} -t ${input_vector_file}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_output_file_name} + + else + _echo_args "${simulation_command} -t ${input_vector_file} -T ${output_vector_file}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_predefined_io_file_name} + + fi + fi fi + done + done - fi - - done - done - - #synthesize the circuits - if [ "${_synthesis}" == "on" ] - then - run_bench_in_parallel \ - "Synthesis" \ - "${_threads}" \ - "${global_synthesis_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_synthesis_file_name})" - fi + #synthesize the circuits + if [ "${_synthesis}" == "on" ] + then + run_bench_in_parallel \ + "Synthesis" \ + "${_threads}" \ + "${global_synthesis_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_synthesis_file_name})" + fi - if [ "${_simulation}" == "on" ] - then + if [ "${_simulation}" == "on" ] + then - run_bench_in_parallel \ - "Generate_IO_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_io_file_name})" - - run_bench_in_parallel \ - "Generate_Output_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_output_file_name})" - - run_bench_in_parallel \ - "Predefined_IO_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_predefined_io_file_name})" + run_bench_in_parallel \ + "Generate_IO_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_io_file_name})" + + run_bench_in_parallel \ + "Generate_Output_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_output_file_name})" + + run_bench_in_parallel \ + "Predefined_IO_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_predefined_io_file_name})" - fi + fi - INPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name input_vectors)" - if [ "${_simulation}" == "on" ] && [ "_${INPUT_VECTOR_LIST}" != "_" ] - then - mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors + INPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name input_vectors)" + if [ "${_simulation}" == "on" ] && [ "_${INPUT_VECTOR_LIST}" != "_" ] + then + mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors - # move the input vectors - for sim_input_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "input_vectors") - do - BM_DIR=$(dirname ${sim_input_vectors}) - BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_input" + # move the input vectors + for sim_input_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "input_vectors") + do + BM_DIR=$(dirname ${sim_input_vectors}) + BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_input" - cp ${sim_input_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} - mv ${sim_input_vectors} ${BM_DIR}/${BM_NAME} - - done - fi + cp ${sim_input_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} + mv ${sim_input_vectors} ${BM_DIR}/${BM_NAME} + + done + fi - OUTPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name output_vectors)" - if [ "${_simulation}" == "on" ] && [ "_${OUTPUT_VECTOR_LIST}" != "_" ] - then - mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors + OUTPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name output_vectors)" + if [ "${_simulation}" == "on" ] && [ "_${OUTPUT_VECTOR_LIST}" != "_" ] + then + mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors - # move the output vectors - for sim_output_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "output_vectors") - do - BM_DIR=$(dirname ${sim_output_vectors}) - BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_output" + # move the output vectors + for sim_output_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "output_vectors") + do + BM_DIR=$(dirname ${sim_output_vectors}) + BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_output" - cp ${sim_output_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} - mv ${sim_output_vectors} ${BM_DIR}/${BM_NAME} + cp ${sim_output_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} + mv ${sim_output_vectors} ${BM_DIR}/${BM_NAME} - done + done + fi fi } @@ -914,7 +1004,7 @@ function run_suite() { input_path=$(ls -d -1 ${THIS_DIR}/${input_path} 2> /dev/null) ;; esac - + input_list=( ${input_list[@]} ${input_path[@]} ) done @@ -931,7 +1021,6 @@ function run_suite() { ;; *) - # bash expand when possible echo "no such Directory for task: ${current_input}" ;; esac @@ -978,8 +1067,9 @@ then fi _TEST=$(readlink -f ${_TEST}) +_TEST_NAME=$(basename ${_TEST}) -echo "Task: ${_TEST}" +echo "Task: ${_TEST_NAME} (${_TEST})" input_list=( "${_TEST}" ) From a84a0334538bf7a5441ce71e2b1b1e874ec2789f Mon Sep 17 00:00:00 2001 From: kmurray Date: Wed, 11 Dec 2019 11:55:00 -0500 Subject: [PATCH 002/107] flow: Add buffer absorption regression test --- .../strong_absorb_buffers/config/config.txt | 31 +++++++++++++++++++ .../config/golden_results.txt | 3 ++ .../vtr_reg_strong/task_list.txt | 1 + 3 files changed, 35 insertions(+) create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt new file mode 100644 index 00000000000..e06768cd4cf --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt @@ -0,0 +1,31 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/tests + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=riscv_core_lut6.blif #Contains dangling LUT buffers + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-starting_stage vpr -track_memory_usage --pack + +script_params_list_add=--absorb_buffer_luts on +script_params_list_add=--absorb_buffer_luts off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt new file mode 100644 index 00000000000..c0e55d1f94c --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -0,0 +1,3 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 0.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 v8.0.0-rc1-1192-gcb2043b7e success 31912 130 150 1183 1333 1 898 364 12 12 144 clb auto 0.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 v8.0.0-rc1-1192-gcb2043b7e success 31984 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.64 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index f1e9286c4d3..4f29fadb034 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -54,3 +54,4 @@ regression_tests/vtr_reg_strong/strong_timing_report_detail regression_tests/vtr_reg_strong/strong_route_reconverge regression_tests/vtr_reg_strong/strong_clock_buf regression_tests/vtr_reg_strong/strong_equivalent_sites +regression_tests/vtr_reg_strong/strong_absorb_buffers From 052fde6e0b954e5f4450ebd73609d9cfcdf95aa9 Mon Sep 17 00:00:00 2001 From: kmurray Date: Wed, 11 Dec 2019 12:07:20 -0500 Subject: [PATCH 003/107] vpr: Update buffer absorption to be less conservative. Previous changes would avoid absorbing buffers driving two primary outputs. We now absorb buffers in that case. --- vpr/src/base/atom_netlist_utils.cpp | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index 55315e0ef40..ea32a2d071b 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -863,26 +863,16 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { }); std::string new_net_name; - if (!driver_is_pi && !po_in_input_sinks && !po_in_output_sinks) { - //No PIs or POs, we can choose arbitarily in this case - new_net_name = netlist.net_name(output_net); - } else if ((driver_is_pi || po_in_input_sinks) && !po_in_output_sinks) { + if ((driver_is_pi || po_in_input_sinks) && !po_in_output_sinks) { //Must use the input name to perserve primary-input or primary-output name new_net_name = netlist.net_name(input_net); - - } else if ((!driver_is_pi && !po_in_input_sinks) && po_in_output_sinks) { + } else if (!(driver_is_pi || po_in_input_sinks) && po_in_output_sinks) { //Must use the output name to perserve primary-output name new_net_name = netlist.net_name(output_net); - } else { - VTR_ASSERT((driver_is_pi || po_in_input_sinks) && po_in_output_sinks); - //This is a buffered connection from a primary input to primary output, or to - //more than one primary output. - //TODO: consider implications of removing these... - - //Do not remove such buffers - return false; + //Arbitrarily merge the net names + new_net_name = netlist.net_name(input_net) + "__" + netlist.net_name(output_net); } size_t initial_input_net_pins = netlist.net_pins(input_net).size(); From 7c6fe31220d03249a9247dda3f9bd86d3bddd0d9 Mon Sep 17 00:00:00 2001 From: kmurray Date: Wed, 11 Dec 2019 12:24:35 -0500 Subject: [PATCH 004/107] flow: Update strong regression results Less conservative buffer absorption improves delay on strong_multiclock test, as an additional buffer is absorbed. --- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../strong_bidir/config/golden_results.txt | 8 ++-- .../strong_binary/config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 16 ++++---- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 16 ++++---- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 2 +- .../strong_depop/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../strong_fc_abs/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 40 +++++++++---------- .../config/golden_results.txt | 12 +++--- .../config/golden_results.txt | 12 +++--- .../config/golden_results.txt | 6 +-- .../config/golden_results.txt | 2 +- .../strong_mcnc/config/golden_results.txt | 6 +-- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../strong_pack/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../strong_power/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../strong_sdc/config/golden_results.txt | 12 +++--- .../config/golden_results.txt | 12 +++--- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 26 ++++++------ .../strong_timing/config/golden_results.txt | 2 +- .../config/golden_results.txt | 6 +-- .../strong_titan/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 8 ++-- .../config/golden_results.txt | 4 +- 54 files changed, 144 insertions(+), 144 deletions(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index c0e55d1f94c..54fc8433be0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 0.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 v8.0.0-rc1-1192-gcb2043b7e success 31912 130 150 1183 1333 1 898 364 12 12 144 clb auto 0.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 v8.0.0-rc1-1192-gcb2043b7e success 31984 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.64 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 33088 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 32980 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 3c52ef71400..d4ffa0b7bb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.97 0.02 9300 4 0.13 -1 -1 33000 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25448 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.22 0.04 9516 5 0.14 -1 -1 33248 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.06 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 0.05 9344 4 0.16 -1 -1 33048 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25420 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 433 752 1884 183020 26826 1.07788e+06 1.02399e+06 207176. 4228.08 24 2.24005 -174.527 -2.24005 0 0 0.08 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.72 0.05 9596 5 0.12 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 28136 11 30 313 321 2 117 55 7 7 49 clb auto 0.32 380 0.12 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 2cb5bad9888..ea2684cd3c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_n4_v7_bidir.xml styr.blif common 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21744 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1261 0.12 5.33383 -68.3994 -5.33383 16 1903 29 2.43e+06 2.01e+06 -1 -1 0.48 1826 16 939 2863 195365 30983 7.17859 -89.6405 -7.17859 0 0 -1 -1 0.06 -k4_n4_v7_longline_bidir.xml styr.blif common 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21888 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2324 21 2.43e+06 2.01e+06 -1 -1 0.25 2262 45 1271 3738 304440 42218 8.37849 -101.759 -8.37849 0 0 -1 -1 0.07 -k4_n4_v7_l1_bidir.xml styr.blif common 1.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22404 10 10 253 263 1 169 87 11 11 121 clb auto 0.04 1227 0.12 6.05408 -74.8187 -6.05408 10 1522 37 2.43e+06 2.01e+06 -1 -1 1.07 1214 16 1112 3531 274215 52624 7.44659 -87.7658 -7.44659 0 0 -1 -1 0.05 -k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21504 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1236 0.33 5.30313 -63.535 -5.30313 16 2042 28 2.43e+06 2.01e+06 -1 -1 0.59 1979 19 1142 3366 494089 68283 7.86978 -98.8292 -7.86978 0 0 -1 -1 0.07 +k4_n4_v7_bidir.xml styr.blif common 1.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22008 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1261 0.20 5.33383 -68.3994 -5.33383 17 1934 35 2.43e+06 2.01e+06 -1 -1 0.75 1937 20 1286 4168 328994 46247 7.85307 -98.3305 -7.85307 0 0 -1 -1 0.11 +k4_n4_v7_longline_bidir.xml styr.blif common 1.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21856 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2206 22 2.43e+06 2.01e+06 -1 -1 0.59 2235 28 1635 4962 403273 51999 8.46175 -102.579 -8.46175 0 0 -1 -1 0.12 +k4_n4_v7_l1_bidir.xml styr.blif common 1.97 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22524 10 10 253 263 1 169 87 11 11 121 clb auto 0.07 1227 0.26 6.05408 -74.8187 -6.05408 10 1516 43 2.43e+06 2.01e+06 -1 -1 1.24 1193 18 1215 4020 298127 55249 7.03996 -86.5204 -7.03996 0 0 -1 -1 0.09 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21800 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1236 0.59 5.30313 -63.535 -5.30313 14 2242 44 2.43e+06 2.01e+06 -1 -1 0.93 2224 21 1592 5130 856330 113214 30.5003 -302.812 -30.5003 0 0 -1 -1 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 802eb7792dc..23c3bbba0e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 0.97 0.03 9344 4 0.11 -1 -1 33140 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25236 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.09 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.24 0.04 9336 4 0.16 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25204 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.25 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.51 0.04 9340 4 0.17 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25384 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.14 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.21 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.90 0.05 9312 4 0.14 -1 -1 33012 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25696 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 404 0.16 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.55 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 34026948a96..3e8c896e8d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.55 0.03 9248 4 0.09 -1 -1 33040 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25732 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 395 0.51 2.21922 -172.773 -2.21922 20 659 32 1.07788e+06 1.02399e+06 49980.0 1020.00 0.13 490 19 532 1247 59762 19337 2.76555 -183.23 -2.76555 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 2.48 0.05 9352 4 0.14 -1 -1 33052 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25580 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 395 0.95 2.21922 -172.773 -2.21922 20 670 41 1.07788e+06 1.02399e+06 49980.0 1020.00 0.26 548 21 878 2095 96841 30313 2.52691 -184.979 -2.52691 0 0 65453.8 1335.79 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt index ef4741413f3..de859d8d00d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.84 0.04 9256 4 0.10 -1 -1 33156 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25920 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 392 0.06 2.2162 -164.467 -2.2162 488 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.43079 -179.827 -2.43079 0 0 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.19 0.04 9472 4 0.15 -1 -1 33020 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25812 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 506 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.56012 -181.991 -2.56012 0 0 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index f8b490ba19f..368b2219414 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.76 0.00 5876 1 0.01 -1 -1 29900 -1 -1 3 9 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24584 9 8 71 66 1 37 20 5 5 25 clb auto 0.41 85 0.02 2.22275 -22.4732 -2.22275 26 275 17 151211 75605.7 37105.9 1484.24 0.03 181 14 125 161 5553 3001 3.37425 -36.3478 -3.37425 0 0 45067.1 1802.68 0.01 14 16 16 6 0 0 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.29 0.01 6252 1 0.00 -1 -1 30268 -1 -1 8 19 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26792 19 18 299 240 1 150 45 6 6 36 clb auto 1.68 513 0.07 3.94024 -72.8405 -3.94024 66 919 32 403230 201615 140689. 3908.03 0.13 788 16 603 878 36522 13558 4.8522 -103.597 -4.8522 0 0 172795. 4799.85 0.02 62 81 85 13 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.01 5912 1 0.01 -1 -1 29788 -1 -1 3 9 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23852 9 8 71 66 1 37 20 5 5 25 clb auto 0.65 85 0.04 2.22275 -22.4732 -2.22275 26 275 17 151211 75605.7 37105.9 1484.24 0.05 181 14 125 161 5553 3001 3.37425 -36.3478 -3.37425 0 0 45067.1 1802.68 0.01 14 16 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.65 0.01 6104 1 0.01 -1 -1 30212 -1 -1 8 19 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 26504 19 18 299 240 1 150 45 6 6 36 clb auto 2.60 513 0.13 3.94024 -72.8405 -3.94024 66 918 26 403230 201615 140689. 3908.03 0.27 783 17 611 899 37480 13874 4.75135 -103.522 -4.75135 0 0 172795. 4799.85 0.03 62 81 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index e6b840828dd..472c1c7a13d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_global_nets num_routed_nets -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.22 0.00 5380 1 0.00 -1 -1 29660 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18580 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 3 3 56 48 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.23 0.00 5380 1 0.01 -1 -1 29768 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18620 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 1 53894 53894 1588.16 176.462 0.00 5 1 3 3 71 58 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 3.10 0.17 48060 2 0.92 -1 -1 51000 -1 -1 155 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 27504 5 156 191 347 1 163 316 15 15 225 clb auto 0.04 22 0.14 1.10064 -11.3943 -1.10064 8 58 10 9.10809e+06 8.35357e+06 130230. 578.801 0.20 45 11 35 41 1194 592 1.16775 -13.0518 -1.16775 0 0 158426. 704.117 0.01 154 9 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 2.96 0.19 48064 2 0.92 -1 -1 50868 -1 -1 155 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 27624 5 156 191 347 1 163 316 15 15 225 clb auto 0.03 25 0.16 1.079 -11.7073 -1.079 12 80 9 9.10809e+06 8.35357e+06 194400. 864.002 0.12 78 5 36 51 4226 1673 1.7756 -16.1044 -1.7756 -3.13612 -0.488149 255657. 1136.26 0.01 153 10 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.26 0.00 5736 1 0.01 -1 -1 29784 -1 -1 1 2 0 0 v8.0.0-rc1-1092-gb22604c1a success 22984 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 3 3 56 48 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.27 0.01 5744 1 0.00 -1 -1 29744 -1 -1 1 2 0 0 v8.0.0-rc1-1092-gb22604c1a success 22716 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 1 53894 53894 1588.16 176.462 0.00 5 1 3 3 71 58 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 8.01 0.07 15940 2 0.07 -1 -1 33480 -1 -1 32 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 57868 311 156 972 1128 1 953 514 28 28 784 memory auto 0.36 7976 1.53 4.26612 -4292.66 -4.26612 40 13615 28 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 3.77 12850 18 2816 3295 4898763 1500574 4.29603 -4929.32 -4.29603 -20.3472 -0.298787 2.55406e+06 3257.73 0.94 15 938 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 7.96 0.10 15892 2 0.11 -1 -1 33504 -1 -1 32 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 58204 311 156 972 1128 1 953 514 28 28 784 memory auto 0.30 8142 1.46 3.96275 -2917.87 -3.96275 40 13931 23 4.25198e+07 9.94461e+06 2.07480e+06 2646.43 3.81 12943 21 3274 3870 4601511 1352718 4.43746 -3526.24 -4.43746 -894.645 -2.58347 2.60581e+06 3323.74 0.90 14 939 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.28 0.00 5408 1 0.00 -1 -1 29736 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18644 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 4 4 87 77 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.28 0.00 5344 1 0.01 -1 -1 29656 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18612 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 2 53894 53894 1588.16 176.462 0.00 5 2 4 4 114 93 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 4.79 0.27 47992 2 1.47 -1 -1 50904 -1 -1 155 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 27108 5 156 191 347 1 163 316 15 15 225 clb auto 0.06 22 0.27 1.10064 -11.3943 -1.10064 8 58 10 9.10809e+06 8.35357e+06 130230. 578.801 0.28 45 12 37 43 1274 630 1.16775 -13.0518 -1.16775 0 0 158426. 704.117 0.01 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 4.67 0.25 48016 2 1.44 -1 -1 50872 -1 -1 155 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 27236 5 156 191 347 1 163 316 15 15 225 clb auto 0.07 25 0.29 1.079 -11.7073 -1.079 12 81 10 9.10809e+06 8.35357e+06 194400. 864.002 0.21 78 5 36 51 4359 1735 1.7756 -16.1044 -1.7756 -3.13612 -0.488149 255657. 1136.26 0.01 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.34 0.01 5832 1 0.00 -1 -1 29732 -1 -1 1 2 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22900 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 4 4 87 77 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.32 0.01 5936 1 0.00 -1 -1 29852 -1 -1 1 2 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22796 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.01 0.524421 -0.946421 -0.524421 2 5 2 53894 53894 1588.16 176.462 0.00 5 2 4 4 114 93 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 10.02 0.12 15992 2 0.12 -1 -1 33496 -1 -1 32 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 57752 311 156 972 1128 1 953 514 28 28 784 memory auto 0.52 7976 2.61 4.26612 -4292.66 -4.26612 40 13542 15 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 3.95 12829 18 2820 3287 4811709 1472844 4.29603 -4980.64 -4.29603 -21.7586 -0.298787 2.55406e+06 3257.73 0.93 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 10.30 0.11 15988 2 0.11 -1 -1 33640 -1 -1 32 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 57728 311 156 972 1128 1 953 514 28 28 784 memory auto 0.55 8142 2.69 3.96275 -2917.87 -3.96275 40 13846 26 4.25198e+07 9.94461e+06 2.07480e+06 2646.43 4.15 12969 19 3084 3659 4345349 1258957 4.30407 -3216.46 -4.30407 -770.89 -1.60451 2.60581e+06 3323.74 0.84 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index e3d8437a449..e88a5877964 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 v8.0.0-rc1-1092-gb22604c1a success 22856 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.00 nan 0 0 2 0 1 107788 107788 1342.00 83.8749 0.00 0 1 0 0 0 0 nan 0 0 0 0 1342.00 83.8749 0.00 +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22644 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.01 nan 0 0 2 0 1 107788 107788 1342.00 83.8749 0.02 0 1 0 0 0 0 nan 0 0 0 0 1342.00 83.8749 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index a0956006466..9fd514ba486 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -fixed_grid.xml raygentop.v common 16.69 0.24 29528 3 0.99 -1 -1 40352 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 70880 214 305 3028 2934 1 1505 639 25 25 625 -1 25x25 1.99 12651 2.06 4.38026 -2583.98 -4.38026 56 24540 32 3.19446e+07 9.20413e+06 2.27235e+06 3635.76 8.26 22288 19 6347 12799 3830329 928731 4.75753 -3063.31 -4.75753 0 0 2.89946e+06 4639.14 0.79 -column_io.xml raygentop.v common 12.88 0.29 29588 3 0.92 -1 -1 40428 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 69504 214 305 3028 2934 1 1505 639 25 25 625 io auto 1.99 11186 2.08 4.44947 -2598 -4.44947 48 26204 47 2.82259e+07 9.20413e+06 1.82181e+06 2914.90 4.90 20751 16 6209 13258 3619980 797372 4.75972 -3122.48 -4.75972 0 0 2.33544e+06 3736.71 0.73 -multiwidth_blocks.xml raygentop.v common 18.90 0.26 29624 3 0.95 -1 -1 40576 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 64284 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.03 11009 2.11 4.22667 -2561.65 -4.22667 66 24404 44 1.65001e+07 9.20413e+06 1.25644e+06 3480.44 10.83 19871 17 6204 13195 4124469 1036083 4.736 -3000.86 -4.736 0 0 1.57029e+06 4349.83 0.84 -non_column.xml raygentop.v common 14.02 0.26 30084 3 0.95 -1 -1 40408 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 91316 214 305 3028 2934 1 1505 639 33 33 1089 io auto 2.01 14430 2.61 4.43648 -2628.32 -4.43648 52 28027 39 5.44432e+07 9.20413e+06 3.22151e+06 2958.23 5.12 24244 17 6098 13695 3439743 840375 4.9934 -3179.25 -4.9934 0 0 4.23526e+06 3889.13 0.72 -non_column_tall_aspect_ratio.xml raygentop.v common 14.96 0.26 30008 3 0.99 -1 -1 40336 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 87860 214 305 3028 2934 1 1505 639 23 46 1058 io auto 2.04 12763 2.53 4.57417 -2705.58 -4.57417 42 29470 40 5.05849e+07 9.20413e+06 2.64587e+06 2500.82 6.12 24010 22 6480 14274 4186244 1076955 5.43192 -3216.12 -5.43192 0 0 3.33112e+06 3148.51 0.93 -non_column_wide_aspect_ratio.xml raygentop.v common 17.56 0.22 29936 3 1.02 -1 -1 40420 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 94048 214 305 3028 2934 1 1505 639 43 22 946 io auto 2.06 14488 2.56 4.40404 -2785.34 -4.40404 46 28929 33 4.55909e+07 9.20413e+06 2.54300e+06 2688.17 8.61 24597 20 6679 14345 3752569 941575 5.01984 -3325.4 -5.01984 0 0 3.26968e+06 3456.32 0.91 -custom_sbloc.xml raygentop.v common 15.53 0.23 29468 3 0.95 -1 -1 40572 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 67396 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.04 11490 2.27 4.51616 -2579.11 -4.51616 64 23626 24 1.65001e+07 9.20413e+06 1.19565e+06 3312.06 7.16 20822 17 6396 13768 4524387 1101304 4.91789 -3004.32 -4.91789 0 0 1.50465e+06 4168.01 0.90 -multiple_io_types.xml raygentop.v common 49.28 0.22 29644 3 0.97 -1 -1 40528 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 417392 214 305 3028 2934 1 1505 639 67 67 4489 io_left auto 2.60 40772 9.67 6.83522 -4708.83 -6.83522 44 55544 39 2.48753e+08 9.20413e+06 1.09868e+07 2447.50 30.38 51052 14 6794 14917 7553090 1756444 7.06512 -5349.8 -7.06512 0 0 1.42904e+07 3183.43 1.31 +fixed_grid.xml raygentop.v common 25.84 0.31 29664 3 1.52 -1 -1 40360 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 72184 214 305 2964 2870 1 1438 634 25 25 625 -1 25x25 3.17 12875 3.64 4.4701 -2560.95 -4.4701 56 24974 27 3.19446e+07 8.93466e+06 2.27235e+06 3635.76 12.48 22306 18 5829 12928 3763475 891650 4.89048 -2985.86 -4.89048 0 0 2.89946e+06 4639.14 1.30 +column_io.xml raygentop.v common 30.79 0.30 29656 3 1.47 -1 -1 40420 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 75196 214 305 2964 2870 1 1438 634 25 25 625 io auto 3.12 11261 3.33 4.46107 -2506.79 -4.46107 50 26270 36 2.82259e+07 8.93466e+06 1.88190e+06 3011.03 17.84 20904 17 6177 13915 3771135 818422 4.87754 -2920.16 -4.87754 0 0 2.49714e+06 3995.43 1.34 +multiwidth_blocks.xml raygentop.v common 31.76 0.33 29788 3 1.78 -1 -1 40428 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 67884 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.19 10446 3.78 4.42441 -2494.7 -4.42441 68 23181 35 1.65001e+07 8.93466e+06 1.28755e+06 3566.63 18.26 18866 14 5520 12874 4172039 1070780 4.77245 -2886.5 -4.77245 0 0 1.60474e+06 4445.26 1.39 +non_column.xml raygentop.v common 24.18 0.36 30204 3 1.60 -1 -1 40416 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 90400 214 305 2964 2870 1 1438 634 33 33 1089 io auto 3.14 13212 4.09 4.29383 -2619.77 -4.29383 50 28185 27 5.44432e+07 8.93466e+06 3.11799e+06 2863.17 9.53 22797 19 6862 15251 4449583 1089545 5.14569 -3069.09 -5.14569 0 0 4.13529e+06 3797.33 1.50 +non_column_tall_aspect_ratio.xml raygentop.v common 39.22 0.38 30152 3 1.55 -1 -1 40444 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 98128 214 305 2964 2870 1 1438 634 23 46 1058 io auto 3.13 13287 4.13 4.49581 -2567.26 -4.49581 50 25552 23 5.05849e+07 8.93466e+06 3.11839e+06 2947.44 24.98 21898 15 5590 12773 2718112 668692 5.25903 -2987.14 -5.25903 0 0 4.13508e+06 3908.40 1.05 +non_column_wide_aspect_ratio.xml raygentop.v common 41.31 0.38 30232 3 1.56 -1 -1 40360 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 83160 214 305 2964 2870 1 1438 634 43 22 946 io auto 3.16 14109 3.90 4.53087 -2746.94 -4.53087 46 30005 40 4.55909e+07 8.93466e+06 2.54300e+06 2688.17 26.99 24419 24 7023 15864 4574615 1097967 4.99799 -3215.24 -4.99799 0 0 3.26968e+06 3456.32 1.68 +custom_sbloc.xml raygentop.v common 25.36 0.34 29672 3 1.45 -1 -1 40356 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 62944 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.31 10710 3.67 4.29215 -2514.15 -4.29215 62 23655 46 1.65001e+07 8.93466e+06 1.15634e+06 3203.15 12.04 19234 20 6084 13886 3597203 896399 4.84201 -2951.3 -4.84201 0 0 1.43990e+06 3988.64 1.35 +multiple_io_types.xml raygentop.v common 112.14 0.30 29536 3 1.42 -1 -1 40528 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 416268 214 305 2964 2870 1 1438 634 67 67 4489 io_left auto 3.94 37811 16.94 5.77645 -4658.65 -5.77645 50 52755 46 2.48753e+08 8.93466e+06 1.23326e+07 2747.29 82.43 48473 14 6877 15481 6627715 1528770 6.07015 -5121.09 -6.07015 0 0 1.63652e+07 3645.63 1.15 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index ea08b5de124..a02a8e7c371 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 1.52 0.04 8976 3 0.19 -1 -1 36164 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30184 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 648 0.27 1.98044 -205.036 -1.98044 50 1402 13 5.66058e+06 4.05111e+06 423042. 2937.80 0.36 1312 11 576 728 57051 20205 2.49644 -241.033 -2.49644 0 0 561550. 3899.65 0.03 +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 2.10 0.03 9176 3 0.24 -1 -1 36308 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29860 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 648 0.49 1.98044 -205.036 -1.98044 50 1402 13 5.66058e+06 4.05111e+06 423042. 2937.80 0.43 1312 11 576 728 57051 20205 2.49644 -241.033 -2.49644 0 0 561550. 3899.65 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index 86bd5fae5cb..79184563f70 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.18 0.03 8824 4 0.17 -1 -1 33880 -1 -1 75 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 33720 99 130 378 508 1 307 305 15 15 225 memory auto 0.04 867 0.31 1.53958 -153.957 -1.53958 1404 664 1563 256146 64082 1.16234e+06 375248 2.18283e+06 9701.45 11 1.7679 -171.086 -1.7679 -0.0322204 -0.0322204 0.07 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.85 0.04 8880 4 0.28 -1 -1 33932 -1 -1 75 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 33336 99 130 378 508 1 307 305 15 15 225 memory auto 0.06 867 0.50 1.53958 -153.957 -1.53958 1404 664 1563 256146 64082 1.16234e+06 375248 2.18283e+06 9701.45 11 1.7679 -171.086 -1.7679 -0.0322204 -0.0322204 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index b49d3ca6078..7308c682561 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_global_nets num_routed_nets -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.89 0.11 16120 2 0.07 -1 -1 34408 -1 -1 29 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 66492 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.45 7926 1.62 3.71918 -3791.41 -3.71918 38 14664 22 4.25198e+07 9.78293e+06 2.06134e+06 2629.25 3.64 13215 12 2732 3118 2727016 877575 4.6565 -4338.38 -4.6565 -217.731 -0.937841 2.60756e+06 3325.97 0.72 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.87 0.06 16248 2 0.08 -1 -1 34316 -1 -1 29 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 66812 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.50 7855 1.47 4.29577 -3815.97 -4.29577 40 14565 31 4.25198e+07 9.78293e+06 2.18945e+06 2792.66 3.62 13338 15 2997 3368 3172344 938757 4.44197 -4744.17 -4.44197 -296.205 -1.26627 2.74222e+06 3497.72 0.88 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 7.86 0.09 16224 2 0.09 -1 -1 34260 -1 -1 29 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 65944 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.51 7926 1.53 3.71918 -3791.41 -3.71918 38 15411 17 4.25198e+07 9.78293e+06 2.05675e+06 2623.40 3.63 14101 14 2682 3088 2565258 816433 4.6565 -4410.32 -4.6565 -156.683 -0.791471 2.60298e+06 3320.12 0.72 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 12.79 0.11 16188 2 0.11 -1 -1 34240 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 65912 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.76 7926 2.69 3.71918 -3791.41 -3.71918 38 14664 22 4.25198e+07 9.78293e+06 2.06134e+06 2629.25 5.78 13215 12 2732 3118 2727378 877873 4.6565 -4338.38 -4.6565 -217.731 -0.937841 2.60756e+06 3325.97 1.23 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.71 0.10 16176 2 0.10 -1 -1 34268 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 65764 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.79 7855 2.67 4.29577 -3815.97 -4.29577 40 14565 31 4.25198e+07 9.78293e+06 2.18945e+06 2792.66 6.37 13336 16 3013 3384 3288699 970769 4.44197 -4744.42 -4.44197 -296.276 -1.26627 2.74222e+06 3497.72 1.46 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.25 0.11 16296 2 0.10 -1 -1 34304 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 66468 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.76 7926 2.70 3.71918 -3791.41 -3.71918 38 15436 16 4.25198e+07 9.78293e+06 2.05675e+06 2623.40 6.15 14101 14 2682 3088 2566936 820999 4.6565 -4410.32 -4.6565 -156.683 -0.791471 2.60298e+06 3320.12 1.27 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index 677e608df28..3e6f00a5572 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 6.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 47932 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.29 10133 1.54 6.77352 -1333.3 -6.77352 24 12220 20 983127 929624 797780. 1508.09 3.07 10949 16 6016 20588 2159891 493894 6.8984 -1445.89 -6.8984 0 0 1.04508e+06 1975.57 0.51 +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 11.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 47732 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.40 10133 2.53 6.77352 -1333.3 -6.77352 24 12541 23 983127 929624 797780. 1508.09 6.43 11441 17 6774 22853 2446188 571128 6.96084 -1500.96 -6.96084 0 0 1.04508e+06 1975.57 0.64 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 6bf3edd42e8..74a5f0d6399 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.66 0.18 29408 4 1.52 -1 -1 39844 -1 -1 167 193 5 0 v8.0.0-rc1-1092-gb22604c1a success 71136 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.32 10711 2.51 4.0362 -2478.27 -4.0362 80 21050 36 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 6.52 19612 16 5228 14998 1697996 377704 4.77524 -2855.18 -4.77524 -7.14113 -0.293253 2.64606e+06 6615.15 0.60 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 30.68 0.28 29452 4 2.32 -1 -1 39812 -1 -1 167 193 5 0 v8.0.0-rc1-1194-g64d9b2790 success 70264 193 205 2926 2852 1 1371 570 20 20 400 memory auto 2.06 10711 4.38 4.0362 -2478.27 -4.0362 76 23027 46 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 18.33 20051 16 5536 15485 1831924 411676 4.70984 -2868.45 -4.70984 -7.09172 -0.292146 2.51807e+06 6295.18 0.56 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 0e654601b04..d6d715660c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 0.03 9016 3 0.18 -1 -1 36164 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 29808 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 655 0.42 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.35 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.37 0.04 9064 3 0.28 -1 -1 36168 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29732 99 130 363 493 1 251 295 12 12 144 clb auto 0.15 655 0.51 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.48 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index f801f4edbdd..b6c87f17e76 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml test_eblif.eblif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19196 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 20 9 1 53894 53894 4880.82 542.314 0.00 5 1 3 3 38 28 0.544641 -1.07365 -0.544641 0 0 6579.40 731.044 0.00 -k6_frac_N10_40nm.xml conn_order.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19088 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.709011 -1.25365 -0.709011 20 4 2 53894 53894 4880.82 542.314 0.00 8 1 2 2 36 29 1.17134 -1.71599 -1.17134 0 0 6579.40 731.044 0.00 +k6_frac_N10_40nm.xml test_eblif.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19208 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 20 9 1 53894 53894 4880.82 542.314 0.00 5 1 3 3 38 28 0.544641 -1.07365 -0.544641 0 0 6579.40 731.044 0.00 +k6_frac_N10_40nm.xml conn_order.eblif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18628 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.709011 -1.25365 -0.709011 20 4 2 53894 53894 4880.82 542.314 0.00 8 1 2 2 36 29 1.17134 -1.71599 -1.17134 0 0 6579.40 731.044 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index bd3931e8890..f2e465c68c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.17 0.06 9248 4 0.12 -1 -1 33044 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25408 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 404 0.10 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.10 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.96 0.04 9312 4 0.14 -1 -1 32968 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25592 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 404 0.19 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.21 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 999794c9784..0518b8e3905 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.33 0.04 9276 4 0.10 -1 -1 33068 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25828 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 414 0.08 2.2252 -166.078 -2.2252 14 572 36 1.07788e+06 1.02399e+06 81563.3 1664.56 0.23 496 17 566 1248 92246 25162 2.83162 -197.755 -2.83162 0 0 98201.7 2004.12 0.04 +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.69 0.04 9412 4 0.13 -1 -1 33048 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25564 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 414 0.13 2.2252 -166.078 -2.2252 18 543 24 1.07788e+06 1.02399e+06 98201.7 2004.12 0.44 452 22 829 1925 144634 31657 2.69784 -193.844 -2.69784 0 0 111547. 2276.47 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt index 8cf331b7341..8e6838e0dae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_40nm.xml stereovision3.v common 1.04 0.04 8832 4 0.13 -1 -1 33000 -1 -1 19 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21948 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 449 0.11 2.21945 -168.153 -2.21945 20 707 20 1.34735e+06 1.02399e+06 54591.7 1114.12 0.09 543 15 507 1173 62601 20949 2.36754 -182.136 -2.36754 0 0 71469.7 1458.57 0.04 +k6_N10_40nm.xml stereovision3.v common 1.78 0.04 8840 4 0.15 -1 -1 33152 -1 -1 19 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21668 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 449 0.18 2.21945 -168.153 -2.21945 20 700 27 1.34735e+06 1.02399e+06 54591.7 1114.12 0.22 592 27 884 2154 107177 33979 2.48822 -190.515 -2.48822 0 0 71469.7 1458.57 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index fea01e181d6..ef5f67f9390 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.13 0.03 9288 4 0.15 -1 -1 32996 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25796 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 478 0.10 2.23761 -174.252 -2.23761 20 719 19 1.07788e+06 1.02399e+06 49980.0 1020.00 0.20 614 18 539 1332 68243 22358 2.67002 -194.193 -2.67002 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 2.32 0.04 9360 4 0.15 -1 -1 33176 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25668 11 30 262 292 2 104 60 7 7 49 clb auto 0.13 478 0.17 2.23761 -174.252 -2.23761 22 729 34 1.07788e+06 1.02399e+06 54623.3 1114.76 0.57 706 32 955 2278 127150 37450 3.18721 -193.511 -3.18721 0 0 69322.2 1414.74 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 002da357c43..4635f896009 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -shorted_flyover_wires.xml raygentop.v common 13.95 0.29 29620 3 1.01 -1 -1 40424 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 62756 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.22 11388 2.11 4.27581 -2648.79 -4.27581 64 28724 29 1.65001e+07 9.20413e+06 1.11360e+06 3084.77 5.16 23851 15 6088 13507 4078200 1049123 5.27078 -3186.3 -5.27078 0 0 1.39747e+06 3871.11 0.84 -buffered_flyover_wires.xml raygentop.v common 16.04 0.26 29596 3 0.99 -1 -1 40432 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 63300 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.08 10724 2.11 4.42883 -2547.95 -4.42883 70 27239 49 1.65001e+07 9.20413e+06 1.25135e+06 3466.35 7.35 21887 21 5718 12377 4320243 1123061 4.86613 -3081.64 -4.86613 0 0 1.57792e+06 4370.98 0.97 +shorted_flyover_wires.xml raygentop.v common 30.04 0.29 29556 3 1.51 -1 -1 40428 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 68244 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.25 11108 3.58 4.79392 -2540.18 -4.79392 66 27597 36 1.65001e+07 8.93466e+06 1.15238e+06 3192.19 16.05 23046 15 6018 13533 4245665 1060813 5.29045 -2968.52 -5.29045 0 0 1.43513e+06 3975.42 1.54 +buffered_flyover_wires.xml raygentop.v common 25.09 0.30 29760 3 1.50 -1 -1 40384 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 63188 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.16 10687 3.41 4.50659 -2437.12 -4.50659 70 26328 36 1.65001e+07 8.93466e+06 1.25135e+06 3466.35 11.46 20953 17 5222 11702 4411046 1119985 5.08067 -2980.08 -5.08067 0 0 1.57792e+06 4370.98 1.65 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index 65377a5c306..20d8adc93f1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -hard_fpu_arch_timing.xml mm3.v common 1.82 0.01 6520 1 0.02 -1 -1 30472 -1 -1 0 193 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 33644 193 32 545 422 1 289 227 21 21 441 io auto 0.78 3143 0.29 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.37 +hard_fpu_arch_timing.xml mm3.v common 3.04 0.02 6688 1 0.02 -1 -1 30484 -1 -1 0 193 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 33224 193 32 545 422 1 289 227 21 21 441 io auto 1.30 3143 0.53 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.69 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 184eb3554ca..a4fbccd25c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 1.36 0.03 8936 3 0.18 -1 -1 36228 -1 -1 67 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30848 99 130 363 493 1 249 297 13 13 169 clb auto 0.38 558 0.18 36 1328 8 0 0 481804. 2850.91 0.15 +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.47 0.04 8992 3 0.27 -1 -1 36292 -1 -1 67 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 30520 99 130 363 493 1 249 297 13 13 169 clb auto 0.74 558 0.36 36 1328 8 0 0 481804. 2850.91 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 4c2acbdc699..cfab22fbd74 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.02 0.03 9304 4 0.11 -1 -1 33040 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25512 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.09 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.55 0.04 9476 4 0.14 -1 -1 33008 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25868 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.16 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.20 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index 05380269819..4b348ee8b63 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml const_true.blif common 0.23 -1 -1 0 0.01 -1 -1 29592 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19016 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.20 -1 -1 0 0.00 -1 -1 29600 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19236 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.18 -1 -1 0 0.00 -1 -1 29712 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19160 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.23 -1 -1 0 0.00 -1 -1 29692 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19028 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and.blif common 0.22 -1 -1 1 0.00 -1 -1 29724 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18952 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.708653 -0.708653 -0.708653 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.22 -1 -1 1 0.01 -1 -1 31460 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19292 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.27 -1 -1 1 0.03 -1 -1 31980 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19124 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and_latch.blif common 0.20 -1 -1 1 0.00 -1 -1 29772 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19388 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml false_path_mux.blif common 0.26 -1 -1 1 0.02 -1 -1 31604 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19204 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.708653 -0.708653 -0.708653 -1 4 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_2x2.blif common 0.25 -1 -1 1 0.02 -1 -1 31504 -1 -1 1 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19328 4 4 8 12 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.83461 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_3x3.blif common 0.25 -1 -1 1 0.02 -1 -1 32044 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19304 6 6 12 18 0 12 13 3 3 9 -1 auto 0.00 24 0.00 0.734653 -4.35592 -0.734653 -1 18 12 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_3x4.blif common 0.33 -1 -1 2 0.03 -1 -1 32640 -1 -1 3 7 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19676 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 1.09565 -6.57093 -1.09565 -1 43 15 215576 161682 99039.1 6189.95 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_4x4.blif common 0.32 -1 -1 4 0.03 -1 -1 32432 -1 -1 2 8 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19880 8 8 29 37 0 21 18 4 4 16 clb auto 0.01 54 0.01 1.79165 -10.3186 -1.79165 -1 59 17 215576 107788 99039.1 6189.95 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_5x5.blif common 0.33 -1 -1 4 0.04 -1 -1 32236 -1 -1 4 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 20056 10 10 47 57 0 39 24 4 4 16 clb auto 0.02 126 0.02 2.32358 -16.2013 -2.32358 -1 141 18 215576 215576 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_5x6.blif common 0.52 -1 -1 5 0.07 -1 -1 32692 -1 -1 5 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 20308 11 11 61 72 0 51 27 5 5 25 clb auto 0.03 176 0.03 2.93136 -19.368 -2.93136 -1 215 15 485046 269470 186194. 7447.77 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_1bit.blif common 0.29 -1 -1 1 0.03 -1 -1 30932 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19364 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.708653 -1.41731 -0.708653 -1 6 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_2bit.blif common 0.27 -1 -1 1 0.03 -1 -1 32292 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19312 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.12596 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_3bit.blif common 0.31 -1 -1 2 0.03 -1 -1 32112 -1 -1 1 7 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19400 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 1.04365 -3.83961 -1.04365 -1 19 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_4bit.blif common 0.26 -1 -1 2 0.02 -1 -1 32148 -1 -1 1 9 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19348 9 5 15 20 0 14 15 3 3 9 -1 auto 0.01 28 0.00 1.04365 -4.54826 -1.04365 -1 22 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_5bit.blif common 0.29 -1 -1 3 0.02 -1 -1 31900 -1 -1 1 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19392 11 6 19 25 0 17 18 3 3 9 -1 auto 0.01 34 0.00 1.37865 -6.93192 -1.37865 -1 27 4 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_true.blif common 0.41 -1 -1 0 0.01 -1 -1 29724 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19124 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.59 -1 -1 0 0.01 -1 -1 29596 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18640 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.38 -1 -1 0 0.00 -1 -1 29720 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19040 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 -1 -1 0 0.00 -1 -1 29592 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18780 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.23 -1 -1 1 0.00 -1 -1 29692 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19144 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.708653 -0.708653 -0.708653 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 -1 -1 1 0.02 -1 -1 31376 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19124 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.37 -1 -1 1 0.03 -1 -1 31888 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18808 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.24 -1 -1 1 0.00 -1 -1 29708 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18996 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.31 -1 -1 1 0.02 -1 -1 31544 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19180 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.708653 -0.708653 -0.708653 -1 4 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.33 -1 -1 1 0.03 -1 -1 31564 -1 -1 1 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18776 4 4 8 12 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.83461 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.32 -1 -1 1 0.03 -1 -1 31928 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18756 6 6 12 18 0 12 13 3 3 9 -1 auto 0.01 24 0.00 0.734653 -4.35592 -0.734653 -1 18 12 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.36 -1 -1 2 0.04 -1 -1 32456 -1 -1 3 7 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19572 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 1.09565 -6.57093 -1.09565 -1 43 15 215576 161682 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.38 -1 -1 4 0.05 -1 -1 32444 -1 -1 2 8 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19596 8 8 29 37 0 21 18 4 4 16 clb auto 0.02 54 0.02 1.79165 -10.3186 -1.79165 -1 59 17 215576 107788 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.47 -1 -1 4 0.06 -1 -1 32056 -1 -1 4 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19884 10 10 47 57 0 39 24 4 4 16 clb auto 0.03 126 0.03 2.32358 -16.2013 -2.32358 -1 141 18 215576 215576 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.61 -1 -1 5 0.08 -1 -1 32484 -1 -1 5 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 20232 11 11 61 72 0 51 27 5 5 25 clb auto 0.04 176 0.04 2.93136 -19.368 -2.93136 -1 215 15 485046 269470 186194. 7447.77 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.32 -1 -1 1 0.03 -1 -1 30776 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19060 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.708653 -1.41731 -0.708653 -1 6 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.36 -1 -1 1 0.03 -1 -1 32372 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19144 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.12596 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.34 -1 -1 2 0.03 -1 -1 32092 -1 -1 1 7 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18996 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 1.04365 -3.83961 -1.04365 -1 19 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.36 -1 -1 2 0.02 -1 -1 32136 -1 -1 1 9 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19176 9 5 15 20 0 14 15 3 3 9 -1 auto 0.01 28 0.00 1.04365 -4.54826 -1.04365 -1 22 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.33 -1 -1 3 0.03 -1 -1 31852 -1 -1 1 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18836 11 6 19 25 0 17 18 3 3 9 -1 auto 0.01 34 0.00 1.37865 -6.93192 -1.37865 -1 27 4 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index ddd64c08c03..74e4825ed33 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml const_true.blif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18828 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19132 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18816 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19212 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19128 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19096 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_true.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18860 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18628 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18852 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19120 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19072 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18496 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index d304b6b230c..7142409fdae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -x_gaussian_y_uniform.xml stereovision3.v common 1.11 0.04 9284 4 0.12 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25832 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 367 0.08 1.91988 -135.359 -1.91988 12 297 4 1.07788e+06 700622 -1 -1 0.12 294 2 153 228 9385 3448 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_uniform_y_gaussian.xml stereovision3.v common 1.15 0.04 9284 4 0.11 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25808 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 344 0.07 1.91988 -135.359 -1.91988 10 310 15 1.07788e+06 700622 -1 -1 0.16 260 2 148 223 8418 3113 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_gaussian_y_gaussian.xml stereovision3.v common 1.13 0.04 9296 4 0.10 -1 -1 33064 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26008 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 349 0.09 1.91988 -135.359 -1.91988 12 289 6 1.07788e+06 700622 -1 -1 0.15 276 3 174 263 10238 3816 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_delta_y_uniform.xml stereovision3.v common 1.05 0.03 9264 4 0.13 -1 -1 33028 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26112 11 30 262 292 2 110 54 7 7 49 clb auto 0.09 370 0.07 1.91988 -135.359 -1.91988 48 290 2 1.07788e+06 700622 -1 -1 0.11 288 2 152 226 9074 3374 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_delta_y_delta.xml stereovision3.v common 1.09 0.04 9200 4 0.15 -1 -1 33012 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25788 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 365 0.08 1.91988 -135.359 -1.91988 48 290 3 1.07788e+06 700622 -1 -1 0.12 285 2 160 237 10171 3912 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_uniform_y_delta.xml stereovision3.v common 1.07 0.04 9272 4 0.14 -1 -1 33160 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26220 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 365 0.07 1.91988 -135.359 -1.91988 38 281 3 1.07788e+06 700622 -1 -1 0.13 282 2 161 237 9088 3379 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 +x_gaussian_y_uniform.xml stereovision3.v common 1.55 0.07 9364 4 0.15 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25968 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 367 0.12 1.91988 -135.359 -1.91988 12 297 4 1.07788e+06 700622 -1 -1 0.16 294 2 153 228 9385 3448 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_uniform_y_gaussian.xml stereovision3.v common 1.68 0.05 9548 4 0.14 -1 -1 33140 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25988 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 344 0.11 1.91988 -135.359 -1.91988 10 310 15 1.07788e+06 700622 -1 -1 0.27 260 2 148 223 8418 3113 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_gaussian_y_gaussian.xml stereovision3.v common 1.53 0.04 9372 4 0.15 -1 -1 33040 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26148 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 349 0.11 1.91988 -135.359 -1.91988 12 289 6 1.07788e+06 700622 -1 -1 0.25 276 3 174 263 10238 3816 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_delta_y_uniform.xml stereovision3.v common 1.53 0.05 9324 4 0.15 -1 -1 32996 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25704 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 370 0.13 1.91988 -135.359 -1.91988 48 290 2 1.07788e+06 700622 -1 -1 0.19 288 2 152 226 9074 3374 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_delta_y_delta.xml stereovision3.v common 1.52 0.05 9332 4 0.16 -1 -1 32980 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26332 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 365 0.14 1.91988 -135.359 -1.91988 48 290 3 1.07788e+06 700622 -1 -1 0.21 285 2 160 237 10171 3912 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 +x_uniform_y_delta.xml stereovision3.v common 1.42 0.04 9484 4 0.14 -1 -1 33052 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26116 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.12 1.91988 -135.359 -1.91988 38 281 3 1.07788e+06 700622 -1 -1 0.16 282 2 161 237 9088 3379 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 4ea8edf62a9..aa93381d5b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.14 0.03 9272 4 0.10 -1 -1 33200 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25580 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.10 1.93141 -141.327 -1.93141 10 278 24 1.07788e+06 1.02399e+06 -1 -1 0.14 269 19 473 930 51635 19952 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 -nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.03 0.04 9284 4 0.14 -1 -1 33136 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25384 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 397 0.06 1.93141 -141.327 -1.93141 14 277 19 1.07788e+06 1.02399e+06 -1 -1 0.09 268 25 443 969 53893 20310 1.93141 -141.327 -1.93141 0 0 -1 -1 0.03 -nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.12 0.05 9304 4 0.13 -1 -1 33004 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25308 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 426 0.06 1.93141 -141.327 -1.93141 14 302 17 1.07788e+06 1.02399e+06 -1 -1 0.08 301 17 408 911 50388 19833 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.65 0.06 9332 4 0.15 -1 -1 32980 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25460 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.11 1.93141 -141.327 -1.93141 10 280 19 1.07788e+06 1.02399e+06 -1 -1 0.17 270 21 623 1237 68382 26000 1.93141 -141.327 -1.93141 0 0 -1 -1 0.05 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.66 0.04 9332 4 0.15 -1 -1 33028 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25276 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 397 0.12 1.93141 -141.327 -1.93141 14 275 26 1.07788e+06 1.02399e+06 -1 -1 0.18 268 31 572 1220 67739 25259 1.93141 -141.327 -1.93141 0 0 -1 -1 0.07 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.47 0.05 9320 4 0.14 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25376 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 426 0.10 1.93141 -141.327 -1.93141 14 307 16 1.07788e+06 1.02399e+06 -1 -1 0.14 304 17 558 1204 67109 26114 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index 03592ae360c..9ad3391d09b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml stereovision3.v common 1.12 0.02 8736 4 0.13 -1 -1 33008 -1 -1 13 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22172 11 30 262 292 2 110 54 6 6 36 clb auto 0.11 381 0.05 2.26562 -157.07 -2.26562 34 760 33 862304 700622 62337.4 1731.59 0.19 540 11 343 559 21904 8621 2.5114 -178.2 -2.5114 0 0 76364.4 2121.23 0.02 +k6_frac_N10_40nm.xml stereovision3.v common 1.81 0.04 8876 4 0.14 -1 -1 33064 -1 -1 13 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22068 11 30 262 292 2 110 54 6 6 36 clb auto 0.12 381 0.06 2.26562 -157.07 -2.26562 34 764 40 862304 700622 62337.4 1731.59 0.29 540 11 343 559 21904 8621 2.5114 -178.2 -2.5114 0 0 76364.4 2121.23 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 2a0b67754bb..040866a427e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_N4_90nm.xml diffeq.blif common 5.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 47684 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.24 10133 1.50 6.77352 -1333.3 -6.77352 24 12220 20 983127 929624 797780. 1508.09 2.95 10949 16 6016 20588 2159891 493894 6.8984 -1445.89 -6.8984 0 0 1.04508e+06 1975.57 0.51 -k4_N4_90nm.xml ex5p.blif common 13.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 41056 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.23 11365 1.08 6.2011 -272.5 -6.2011 34 15486 43 804782 771343 910617. 2064.89 10.60 13214 20 7563 24669 4289697 1119035 6.2011 -285.89 -6.2011 0 0 1.15594e+06 2621.17 0.77 -k4_N4_90nm.xml s298.blif common 8.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 56600 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.27 12944 1.73 11.3412 -87.4002 -11.3412 26 16841 26 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 5.04 15969 19 7557 34543 4267407 813984 11.3825 -88.9401 -11.3825 0 0 1.43821e+06 2127.53 0.88 +k4_N4_90nm.xml diffeq.blif common 11.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 47468 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.38 10133 2.53 6.77352 -1333.3 -6.77352 24 12541 23 983127 929624 797780. 1508.09 6.49 11441 17 6774 22853 2446188 571128 6.96084 -1500.96 -6.96084 0 0 1.04508e+06 1975.57 0.89 +k4_N4_90nm.xml ex5p.blif common 23.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 44112 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.27 11365 1.81 6.2011 -272.5 -6.2011 36 14690 30 804782 771343 957936. 2172.19 18.82 13031 20 7558 24835 4031744 1002168 6.5642 -288.81 -6.5642 0 0 1.20592e+06 2734.52 1.36 +k4_N4_90nm.xml s298.blif common 17.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 55720 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.41 12944 2.92 11.3412 -87.4002 -11.3412 26 18082 37 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 11.23 16266 19 8684 41436 5277893 987865 11.5285 -89.8977 -11.5285 0 0 1.43821e+06 2127.53 1.70 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index a2b03c74342..9032f461e98 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.20 0.04 9588 5 0.11 -1 -1 33396 -1 -1 15 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 29120 11 30 313 321 2 114 56 7 7 49 clb auto 0.31 384 0.06 4.29791 0 0 587 167 333 10080 3225 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.564 -1.707 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.44 0.04 9500 5 0.14 -1 -1 33300 -1 -1 15 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 29076 11 30 313 321 2 114 56 7 7 49 clb auto 0.35 384 0.11 4.29791 0 0 587 167 333 10080 3225 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.564 -1.707 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index f77968e2d9f..5c2edaa907f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.06954 0.595 0.782256 -1 -1 0.57 0.757256 -1 1.06954 -1 1.06964 -1 2.09744 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.66026 -1 -1 0.268 3.18526 -1 0.918173 -1 3.30764 -1 -1.26893 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.31564 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.31564 -1 1.07141 -1 1.7816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.16427 -1 3.30941 -1 -1.46477 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 87cdc7fbc8b..6440841a9dc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.19 0.03 8956 3 0.20 -1 -1 36196 -1 -1 64 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30468 99 130 363 493 1 251 294 12 12 144 clb auto 0.10 631 0.18 40 1719 15 5.66058e+06 3.99722e+06 360333. 2502.31 0.16 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.97 0.04 9212 3 0.27 -1 -1 36240 -1 -1 64 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29748 99 130 363 493 1 251 294 12 12 144 clb auto 0.17 631 0.39 40 1719 15 5.66058e+06 3.99722e+06 360333. 2502.31 0.31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index db2e8480e78..3f4919acaf4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.78 0.04 9304 4 0.10 -1 -1 33076 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 24028 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common 0.93 0.07 9336 4 0.14 -1 -1 33044 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24268 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 539a74acf5d..707f2c9ba36 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.82 0.05 9344 4 0.13 -1 -1 33012 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25056 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.09 2.22026 -169.026 -2.22026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.06 0.04 9472 4 0.15 -1 -1 33032 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24400 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.14 2.22026 -169.026 -2.22026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index cc2ed9cb61b..df9b581009d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 19.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 765552 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.36 333 0.78 6.34392 -68.6483 -6.34392 18 769 24 0 0 66239.6 946.281 0.29 683 17 322 1139 141511 78590 7.01253 -76.014 -7.01253 0 0 84868.6 1212.41 0.04 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 19.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 765500 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.36 338 0.78 6.37916 -68.7252 -6.37916 18 722 18 0 0 66239.6 946.281 0.54 641 16 284 987 122407 67992 6.83552 -76.2255 -6.83552 0 0 84868.6 1212.41 0.04 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 31.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 765288 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.59 333 1.42 6.34392 -68.6483 -6.34392 16 953 45 0 0 60092.3 858.461 1.73 730 17 380 1479 176321 92346 7.14809 -77.4881 -7.14809 0 0 74567.7 1065.25 0.07 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 31.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 765580 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.52 338 1.43 6.37916 -68.7252 -6.37916 16 890 49 0 0 60092.3 858.461 1.60 722 17 358 1194 144422 78787 6.91544 -77 -6.91544 0 0 74567.7 1065.25 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index 657f785364b..ce1694b5e1e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.74 0.03 8988 3 0.24 -1 -1 36284 -1 52468 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30424 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 654 0.27 2.16091 -202.472 -2.16091 50 1447 13 5.66058e+06 4.05111e+06 406292. 2821.48 0.24 1301 8 594 746 62382 23285 2.63418 -229.877 -2.63418 0 0 539112. 3743.83 0.02 0.008733 0.2181 0.07312 0.7088 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.91 0.02 8588 15 0.29 -1 -1 34384 -1 55128 36 162 0 5 v8.0.0-rc1-1092-gb22604c1a success 44428 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.24 5302 0.78 19.6083 -1810.12 -19.6083 48 13097 37 1.21132e+07 3.92018e+06 756778. 2956.16 4.28 10038 17 3116 6081 1638625 418610 22.4888 -2094.22 -22.4888 0 0 968034. 3781.38 0.37 0.007854 0.3502 0.01663 0.6332 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.91 0.04 9028 3 0.28 -1 -1 36172 -1 52332 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29764 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 654 0.51 2.16091 -202.472 -2.16091 50 1447 13 5.66058e+06 4.05111e+06 406292. 2821.48 0.50 1301 8 594 746 62382 23285 2.63418 -229.877 -2.63418 0 0 539112. 3743.83 0.10 0.008811 0.2233 0.07246 0.7042 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 12.66 0.04 8648 15 0.39 -1 -1 34380 -1 55136 36 162 0 5 v8.0.0-rc1-1194-g64d9b2790 success 44228 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.38 5302 1.33 19.6083 -1810.12 -19.6083 48 13061 34 1.21132e+07 3.92018e+06 756778. 2956.16 6.74 10038 17 3116 6081 1638625 418610 22.4888 -2094.22 -22.4888 0 0 968034. 3781.38 0.56 0.007854 0.3502 0.01663 0.6332 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index b6530c4a927..bf1fcf5440e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.07 0.04 9284 4 0.15 -1 -1 33024 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25936 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.18 0.03 9592 5 0.14 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 27756 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.07 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.40 0.05 9472 4 0.15 -1 -1 33020 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25496 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 433 752 1884 183020 26826 1.07788e+06 1.02399e+06 207176. 4228.08 24 2.24005 -174.527 -2.24005 0 0 0.07 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.75 0.05 9532 5 0.13 -1 -1 33276 -1 -1 14 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.36 380 0.14 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index ed32602935a..ae53077a65f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 16.76 0.18 29384 4 1.49 -1 -1 39764 -1 -1 167 193 5 0 v8.0.0-rc1-1092-gb22604c1a success 70844 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.27 10711 2.14 4.0362 -2478.27 -4.0362 80 21050 37 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 9.38 19612 17 5228 14998 1697996 377704 4.77524 -2855.18 -4.77524 -7.14113 -0.293253 2.64606e+06 6615.15 0.46 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 19.82 0.29 29640 4 1.60 -1 -1 39856 -1 -1 167 193 5 0 v8.0.0-rc1-1194-g64d9b2790 success 71364 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.30 10711 2.36 4.0362 -2478.27 -4.0362 76 23027 51 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 11.51 20051 17 5536 15485 1831924 411676 4.70984 -2868.45 -4.70984 -7.09172 -0.292146 2.51807e+06 6295.18 0.55 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 80e16928c1b..fd9f173e71d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1092-gb22604c1a success 37728 8 63 748 811 0 474 151 13 13 169 clb auto 0.25 4714 0.43 3.70871 -159.069 -3.70871 6562 3107 11690 976222 174155 6.63067e+06 4.31152e+06 558096. 3302.35 24 4.15429 -179.259 -4.15429 0 0 0.24 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1092-gb22604c1a success 37616 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4726 0.61 3.89144 -158.648 -3.89144 6642 3324 12982 1030781 185339 6.63067e+06 4.31152e+06 558096. 3302.35 22 4.59291 -186.559 -4.59291 0 0 0.29 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1194-g64d9b2790 success 37700 8 63 748 811 0 474 151 13 13 169 clb auto 0.44 4714 0.79 3.70871 -159.069 -3.70871 6703 4263 15313 1252438 219655 6.63067e+06 4.31152e+06 558096. 3302.35 24 4.15304 -182.999 -4.15304 0 0 0.48 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1194-g64d9b2790 success 37376 8 63 748 811 0 474 151 13 13 169 clb auto 0.43 4726 0.96 3.89144 -158.648 -3.89144 6985 4100 15083 1207360 214092 6.63067e+06 4.31152e+06 558096. 3302.35 26 4.16831 -189.499 -4.16831 0 0 0.49 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 2e34bd63c2b..bac71dd39b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -slicem.xml carry_chain.blif common 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19472 1 1 69 49 1 47 8 5 5 25 BLK_IG-SLICEM auto 0.15 102 0.01 0.764286 -10.588 -0.764286 25 401 35 133321 88880.4 -1 -1 0.34 409 22 194 196 56704 26791 3.01746 -35.9539 -3.01746 0 0 -1 -1 0.02 +slicem.xml carry_chain.blif common 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19176 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.15 65 0.02 0.55434 -5.54475 -0.55434 25 164 11 59253.6 59253.6 -1 -1 0.13 197 19 159 159 29188 17227 1.32558 -14.0361 -1.32558 0 0 -1 -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index d3cbcf7a149..efe434968ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -arch.xml ndff.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18404 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.198362 -1.99999 -0.198362 4 26 13 59253.6 44440.2 -1 -1 0.01 26 2 12 15 621 269 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 +arch.xml ndff.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18452 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.198362 -1.99999 -0.198362 4 26 13 59253.6 44440.2 -1 -1 0.02 26 2 12 15 621 269 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 25040fd3f74..7fe2eb3ff2f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 0.96 0.03 9444 5 0.12 -1 -1 33316 -1 -1 15 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 27692 11 30 313 321 2 114 56 7 7 49 clb auto 0.22 384 0.06 4.29791 0 0 537 167 331 10396 3294 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.809 -1.707 0.01 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.38 0.04 9548 5 0.13 -1 -1 33284 -1 -1 15 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27844 11 30 313 321 2 114 56 7 7 49 clb auto 0.34 384 0.13 4.29791 0 0 537 167 331 10396 3294 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.809 -1.707 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index b365cb947f3..64869255b58 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23308 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.738757 -2.61951 -0.738757 8 22 7 323364 161682 9037.03 361.481 0.02 17 7 20 20 554 322 0.756339 -2.63886 -0.756339 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23504 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 27 0.01 0.571 0 0 8 36 4 323364 161682 9037.03 361.481 0.02 45 3 12 12 990 624 0.571 0 0 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23260 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.02 0.570641 -1.88754 -0.570641 6 13 10 323364 161682 7009.75 280.390 0.01 19 1 8 8 231 149 0.592131 -2.24748 -0.592131 0 0 9037.03 361.481 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23468 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 1.57064 -4.87629 -1.57064 8 35 26 323364 161682 9037.03 361.481 0.02 26 7 24 24 700 407 1.58926 -5.4843 -1.58926 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23420 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 1.37401 -2.68253 -1.37401 6 26 13 323364 161682 7009.75 280.390 0.01 30 2 13 13 598 378 1.3955 -2.70755 -1.3955 0 0 9037.03 361.481 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23408 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 0.0706414 0 0 6 19 1 323364 161682 7009.75 280.390 0.01 21 1 8 8 286 184 0.0715255 0 0 0 0 9037.03 361.481 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23348 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.738757 -2.61951 -0.738757 8 23 8 107788 107788 4794.78 299.674 0.01 32 4 14 14 735 589 0.739641 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23268 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 19 0.01 0.571 0 0 8 30 6 107788 107788 4794.78 299.674 0.01 23 4 13 13 349 215 0.571 0 0 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23240 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.569757 -1.88754 -0.569757 8 26 4 107788 107788 4794.78 299.674 0.01 18 8 24 24 632 426 0.681776 -2.31791 -0.681776 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23096 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 1.56976 -4.87541 -1.56976 8 25 11 107788 107788 4794.78 299.674 0.01 17 4 11 11 300 189 1.57153 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23392 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 1.37313 -2.68253 -1.37313 6 24 4 107788 107788 3417.33 213.583 0.01 18 2 10 10 290 190 1.39454 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22904 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.0697572 0 0 8 22 3 107788 107788 4794.78 299.674 0.01 32 5 15 15 764 607 0.0724097 0 0 0 0 5401.54 337.596 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index e31b123c31a..10bc179e6ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 0.83 0.01 5868 1 0.00 -1 -1 29844 -1 -1 3 9 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24252 9 8 74 69 1 33 20 5 5 25 clb auto 0.45 71 0.02 2.25879 -23.7509 -2.25879 26 164 14 151211 75605.7 37105.9 1484.24 0.03 141 10 97 117 3917 2091 2.55561 -33.5675 -2.55561 0 0 45067.1 1802.68 0.00 13 16 19 7 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.18 0.00 5932 1 0.01 -1 -1 29864 -1 -1 2 11 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24476 11 10 107 96 1 44 23 4 4 16 clb auto 2.81 96 0.02 2.96669 -32.6902 -2.96669 34 188 14 50403.8 50403.8 21558.4 1347.40 0.05 137 14 148 202 5606 3428 3.73364 -44.2193 -3.73364 0 0 26343.3 1646.46 0.01 14 25 29 8 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 2.43 0.00 6032 1 0.01 -1 -1 30192 -1 -1 2 13 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24616 13 12 148 128 1 59 27 4 4 16 clb auto 1.97 132 0.02 3.01831 -41.2936 -3.01831 36 280 46 50403.8 50403.8 22423.4 1401.47 0.06 189 14 189 223 6865 4126 3.49231 -57.8176 -3.49231 0 0 28178.5 1761.16 0.01 19 36 42 9 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 1.91 0.00 6148 1 0.01 -1 -1 29872 -1 -1 5 15 0 -1 v8.0.0-rc1-1092-gb22604c1a success 25536 15 14 195 164 1 87 34 5 5 25 clb auto 1.24 270 0.05 3.1163 -51.6217 -3.1163 44 573 24 151211 126010 54748.7 2189.95 0.17 404 16 322 527 18672 8548 3.82203 -71.71 -3.82203 0 0 71025.7 2841.03 0.02 33 49 57 11 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 2.22 0.00 6204 1 0.01 -1 -1 30020 -1 -1 7 17 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26060 17 16 250 205 1 114 40 6 6 36 clb auto 1.64 361 0.06 3.26818 -53.849 -3.26818 52 707 33 403230 176413 110337. 3064.92 0.12 578 17 549 859 33650 13481 4.24968 -85.1999 -4.24968 0 0 143382. 3982.83 0.02 52 64 75 13 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 2.82 0.00 6152 1 0.01 -1 -1 30212 -1 -1 7 19 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26408 19 18 307 248 1 141 44 6 6 36 clb auto 1.97 436 0.10 4.13322 -71.9714 -4.13322 60 926 18 403230 176413 127342. 3537.27 0.23 689 20 677 1075 39870 15591 5.49585 -110.351 -5.49585 0 0 157803. 4383.41 0.02 58 81 93 14 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.01 5956 1 0.01 -1 -1 29680 -1 -1 3 9 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23860 9 8 74 69 1 33 20 5 5 25 clb auto 0.62 71 0.04 2.25879 -23.7509 -2.25879 26 164 14 151211 75605.7 37105.9 1484.24 0.05 141 11 100 122 4102 2193 2.55561 -33.5675 -2.55561 0 0 45067.1 1802.68 0.01 13 16 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.68 0.01 6032 1 0.01 -1 -1 29860 -1 -1 2 11 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23724 11 10 107 96 1 44 23 4 4 16 clb auto 4.08 96 0.04 2.96669 -32.6902 -2.96669 34 188 14 50403.8 50403.8 21558.4 1347.40 0.08 156 18 168 232 6556 3975 3.32273 -45.5748 -3.32273 0 0 26343.3 1646.46 0.01 14 25 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.64 0.01 6012 1 0.01 -1 -1 30336 -1 -1 2 13 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 24260 13 12 148 128 1 59 27 4 4 16 clb auto 2.98 132 0.05 3.01831 -41.2936 -3.01831 38 239 23 50403.8 50403.8 23356.0 1459.75 0.14 182 14 192 219 6796 4029 3.25531 -54.787 -3.25531 0 0 29887.0 1867.94 0.02 19 36 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.86 0.01 6184 1 0.01 -1 -1 29916 -1 -1 5 15 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 24724 15 14 195 164 1 87 34 5 5 25 clb auto 2.08 270 0.08 3.1163 -51.6217 -3.1163 44 537 26 151211 126010 54748.7 2189.95 0.18 404 16 322 527 18672 8548 3.82203 -71.71 -3.82203 0 0 71025.7 2841.03 0.02 33 49 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 3.48 0.01 6120 1 0.01 -1 -1 29956 -1 -1 7 17 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 25948 17 16 250 205 1 114 40 6 6 36 clb auto 2.56 361 0.11 3.26818 -53.849 -3.26818 52 742 23 403230 176413 110337. 3064.92 0.22 590 21 594 946 37002 14662 4.43 -86.7352 -4.43 0 0 143382. 3982.83 0.03 52 64 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.26 0.01 6412 1 0.02 -1 -1 30328 -1 -1 7 19 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 26428 19 18 307 248 1 141 44 6 6 36 clb auto 3.17 436 0.14 4.13322 -71.9714 -4.13322 60 1014 29 403230 176413 127342. 3537.27 0.32 692 21 740 1202 45108 17377 5.26938 -108.577 -5.26938 0 0 157803. 4383.41 0.04 58 81 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index b2b931b1575..08fe0f39203 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.19 0.04 9016 3 0.23 -1 -1 36184 -1 -1 14 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 26484 99 74 307 381 1 199 188 8 8 64 io memory auto 0.04 647 0.22 1.9311 -196.847 -1.9311 32 1451 42 2.23746e+06 1.30252e+06 106908. 1670.44 0.18 1153 20 803 1153 162355 59128 2.18486 -225.489 -2.18486 0 0 130676. 2041.82 0.04 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.26 0.05 9016 3 0.29 -1 -1 36168 -1 -1 14 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 26796 99 74 307 381 1 199 188 8 8 64 io memory auto 0.08 647 0.30 1.9311 -196.847 -1.9311 34 1358 46 2.23746e+06 1.30252e+06 111309. 1739.21 0.67 1092 28 827 1194 140107 49979 2.25027 -229.924 -2.25027 0 0 136889. 2138.88 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 7d751a2b093..2e1804264a7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -EArch.xml styr.blif common_--target_ext_pin_util_1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26940 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 375 0.05 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.11 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.78 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 27172 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.09 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.15 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33272 10 10 168 178 1 162 110 14 14 196 clb auto 0.39 1408 0.18 2.63178 -32.0244 -2.63178 22 2983 14 9.20055e+06 4.85046e+06 325918. 1662.85 0.22 2866 17 635 2380 148243 38092 3.68891 -45.9088 -3.68891 0 0 407540. 2079.28 0.04 -EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.79 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 27648 10 10 168 178 1 73 33 7 7 49 clb auto 0.14 357 0.06 2.19476 -24.8471 -2.19476 28 1161 45 1.07788e+06 700622 79600.7 1624.51 0.29 876 17 434 1600 76377 28777 3.12807 -34.6232 -3.12807 0 0 95067.4 1940.15 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33424 10 10 168 178 1 163 121 14 14 196 clb auto 0.58 1381 0.20 2.72722 -32.4843 -2.72722 20 2827 12 9.20055e+06 5.44329e+06 295730. 1508.82 0.09 2752 15 536 2083 128119 32657 3.60179 -43.9525 -3.60179 0 0 387483. 1976.95 0.05 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26880 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.05 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.10 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26748 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.10 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.11 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.02 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 1.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33392 10 10 168 178 1 162 110 14 14 196 clb auto 0.50 1408 0.21 2.63178 -32.0244 -2.63178 22 2983 14 9.20055e+06 4.85046e+06 325918. 1662.85 0.24 2866 17 635 2380 148243 38092 3.68891 -45.9088 -3.68891 0 0 407540. 2079.28 0.05 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26848 10 10 168 178 1 74 31 6 6 36 clb auto 0.12 375 0.06 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.13 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.02 -EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23284 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23536 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23704 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23408 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1 0.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26888 10 10 168 178 1 74 31 6 6 36 clb auto 0.22 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.20 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27080 10 10 168 178 1 74 31 6 6 36 clb auto 0.21 375 0.11 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.21 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33320 10 10 168 178 1 162 110 14 14 196 clb auto 0.67 1408 0.38 2.63178 -32.0244 -2.63178 22 3011 17 9.20055e+06 4.85046e+06 325918. 1662.85 0.39 2821 14 736 2642 165648 42230 3.68891 -45.7774 -3.68891 0 0 407540. 2079.28 0.07 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27564 10 10 168 178 1 73 33 7 7 49 clb auto 0.20 357 0.09 2.19476 -24.8471 -2.19476 26 1076 29 1.07788e+06 700622 75813.7 1547.22 0.56 893 24 615 2230 111320 40005 2.71043 -34.388 -2.71043 0 0 91376.6 1864.83 0.07 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33408 10 10 168 178 1 163 121 14 14 196 clb auto 0.81 1381 0.41 2.72722 -32.4843 -2.72722 20 2801 19 9.20055e+06 5.44329e+06 295730. 1508.82 0.18 2742 15 598 2202 137075 34724 3.60179 -43.907 -3.60179 0 0 387483. 1976.95 0.06 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27236 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.22 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27208 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.22 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33072 10 10 168 178 1 162 110 14 14 196 clb auto 0.69 1408 0.39 2.63178 -32.0244 -2.63178 22 3011 17 9.20055e+06 4.85046e+06 325918. 1662.85 0.42 2821 14 736 2642 165648 42230 3.68891 -45.7774 -3.68891 0 0 407540. 2079.28 0.08 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26956 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.20 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23764 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23680 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23584 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23892 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index ca2c1ef5b3e..9a3389c2249 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.34 0.03 8980 3 0.20 -1 -1 36172 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 29976 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 655 0.27 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.27 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.03 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.25 0.04 9196 3 0.25 -1 -1 36188 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29304 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 655 0.50 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.46 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 6280904abf3..79087b62319 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24860 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24700 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24996 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24868 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24876 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24552 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index 8aa53db08b8..7d46687cffd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.05 42 753 0 0 0 0 v8.0.0-rc1-1092-gb22604c1a success 1011288 13 29 26295 20086 1 12415 795 39 29 1131 LAB auto 9.57 80370 40.19 4.8494 -14201.6 -4.8494 83423 24866 32259 28860263 3251424 0 0 2.17765e+07 19254.2 13 4.97188 -15343.1 -4.97188 0 0 3.30 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 80.16 42 753 0 0 0 0 v8.0.0-rc1-1194-g64d9b2790 success 1011024 13 29 26295 20086 1 12415 795 39 29 1131 LAB auto 15.84 80370 38.02 4.8494 -14201.6 -4.8494 83215 26269 34662 30836512 3446780 0 0 2.17765e+07 19254.2 13 4.97188 -15454.7 -4.97188 0 0 3.51 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 2532b379d5b..835e38df2df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 8.59 0.01 8828 6 0.09 -1 -1 34012 -1 -1 15 66 0 -1 v8.0.0-rc1-1092-gb22604c1a success 53224 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.14 4812 0.76 14.7278 -819.907 -14.7278 62 11943 18 6.4517e+06 1.13409e+06 1.72337e+06 5319.03 5.17 10760 17 3483 7402 3135131 764282 16.6282 -1030.56 -16.6282 0 0 2.10074e+06 6483.76 0.52 135 200 146 33 66 33 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 15.76 0.02 8916 6 0.12 -1 -1 34112 -1 -1 15 66 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 46780 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.61 4812 1.39 14.7278 -819.907 -14.7278 60 12276 35 6.4517e+06 1.13409e+06 1.66893e+06 5151.03 9.76 10886 40 3329 7348 3578053 1134156 16.8599 -1041.74 -16.8599 0 0 2.06264e+06 6366.18 1.40 135 200 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index 9afc4c5ccd7..580d216346d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a success 23148 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.01 1.10382 -14.1235 -1.10382 62 98 144 4949 2328 323364 161682 20103.2 804.128 15 1.18331 -15.7108 -1.18331 0 0 0.00 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a success 22972 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.01 1.10382 -14.1235 -1.10382 62 98 144 4949 2328 323364 161682 20103.2 804.128 15 1.18331 -15.7108 -1.18331 0 0 0.01 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a exited with return code 2 23616 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 52 0.01 1.14517 -14.2319 -1.14517 -1 734 954 51286 35882 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.02 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a exited with return code 2 23468 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 52 0.01 1.14517 -14.2319 -1.14517 138 734 954 51286 35882 323364 161682 9037.03 361.481 -1 1.57884 -20.2194 -1.57884 0 0 0.02 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22676 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.04 1.10382 -14.1235 -1.10382 69 167 230 8395 3681 323364 161682 20103.2 804.128 21 1.18331 -15.9141 -1.18331 0 0 0.02 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23216 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.02 1.10382 -14.1235 -1.10382 69 167 230 8395 3681 323364 161682 20103.2 804.128 21 1.18331 -15.9141 -1.18331 0 0 0.01 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 exited with return code 2 23648 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 52 0.02 1.14517 -14.2319 -1.14517 -1 761 989 53376 36845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.04 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 exited with return code 2 23284 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 52 0.02 1.14517 -14.2319 -1.14517 139 761 989 53376 36845 323364 161682 9037.03 361.481 -1 1.66401 -20.8061 -1.66401 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 5af3c158894..60b71a0b84b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N4_90nm.xml stereovision3.v common 4.92 0.03 8728 6 0.15 -1 -1 33160 -1 -1 66 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 23608 11 30 336 366 2 186 107 11 11 121 clb auto 0.04 1075 0.11 3.34892 -239.501 -3.34892 995 849 2411 331915 45511 180575 147135 597941. 4941.66 13 3.34892 -248.18 -3.34892 -0.21991 -0.0734 0.05 -k6_frac_N10_40nm.xml stereovision3.v common 2.21 0.02 8852 4 0.14 -1 -1 33044 -1 -1 13 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22544 11 30 262 292 2 110 54 6 6 36 clb auto 0.08 366 0.07 2.26563 -155.916 -2.26563 467 182 317 10207 3363 862304 700622 161034. 4473.17 6 2.47845 -169.802 -2.47845 0 0 0.01 +k4_N4_90nm.xml stereovision3.v common 7.18 0.04 8836 6 0.17 -1 -1 33036 -1 -1 66 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 23748 11 30 336 366 2 186 107 11 11 121 clb auto 0.06 1075 0.19 3.34892 -239.501 -3.34892 1023 868 2391 322050 43514 180575 147135 597941. 4941.66 13 3.34892 -247.922 -3.34892 -0.21991 -0.0734 0.09 +k6_frac_N10_40nm.xml stereovision3.v common 3.08 0.03 8864 4 0.16 -1 -1 33036 -1 -1 13 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22576 11 30 262 292 2 110 54 6 6 36 clb auto 0.13 366 0.14 2.26563 -155.916 -2.26563 467 183 320 10273 3381 862304 700622 161034. 4473.17 6 2.47845 -169.802 -2.47845 0 0 0.03 From 96fbe3ad4057be4846dab2abf7bbda9f8dc499a5 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 16:18:07 -0500 Subject: [PATCH 005/107] vpr: Prefer using is_empty_type() instead of direct comparison --- vpr/src/draw/intra_logic_block.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index a3771f7fed5..2ce4fc4b5d7 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -68,7 +68,7 @@ void draw_internal_alloc_blk() { draw_coords->blk_info.resize(device_ctx.logical_block_types.size()); for (const auto& type : device_ctx.logical_block_types) { - if (&type == device_ctx.EMPTY_LOGICAL_BLOCK_TYPE) { + if (is_empty_type(&type)) { continue; } @@ -153,7 +153,7 @@ void draw_internal_draw_subblk(ezgl::renderer* g) { continue; /* Don't draw if tile is empty. This includes corners. */ - if (device_ctx.grid[i][j].type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) + if (is_empty_type(device_ctx.grid[i][j].type)) continue; int num_sub_tiles = device_ctx.grid[i][j].type->capacity; From 5ef92dc8d7d09d7ca99f45a1549dc201f3e49766 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 17:16:58 -0500 Subject: [PATCH 006/107] vpr: Fix drawing with equivalent sites Previously would crash. Now works and draws blocks the color of the physical tile currently implementing them. Note that internal hierarchy drawing still needs work. --- vpr/src/draw/draw.cpp | 36 +++++++++++++++++++++++++----- vpr/src/draw/draw_types.cpp | 23 +++++++++++++++++++ vpr/src/draw/draw_types.h | 2 ++ vpr/src/draw/intra_logic_block.cpp | 27 +++++++++++++--------- 4 files changed, 72 insertions(+), 16 deletions(-) diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index d29ede76133..b13d8e1e121 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -500,6 +500,11 @@ void update_screen(ScreenUpdatePriority priority, const char* msg, enum pic_type } } + //Block placements may have changed since previous invocation, + //so we need to update the block colors in case blocks have changed + //the tiles where they are implemented + draw_reset_blk_colors(); + if (draw_state->show_graphics) { application.update_message(msg); application.refresh_drawing(); @@ -934,6 +939,7 @@ static void drawplace(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); + auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_ctx = g_vpr_ctx.placement(); ClusterBlockId bnum; @@ -961,15 +967,20 @@ static void drawplace(ezgl::renderer* g) { if (bnum == INVALID_BLOCK_ID) continue; //Determine the block color ezgl::color block_color; + t_logical_block_type_ptr logical_block_type = nullptr; if (bnum != EMPTY_BLOCK_ID) { block_color = draw_state->block_color[bnum]; + logical_block_type = cluster_ctx.clb_nlist.block_type(bnum); } else { block_color = get_block_type_color(device_ctx.grid[i][j].type); block_color = lighten_color(block_color, EMPTY_BLOCK_LIGHTEN_FACTOR); + + auto tile_type = device_ctx.grid[i][j].type; + logical_block_type = pick_best_logical_type(tile_type); } g->set_color(block_color); /* Get coords of current sub_tile */ - ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(i, j, k); + ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(i, j, k, logical_block_type); ezgl::point2d center = abs_clb_bbox.center(); g->fill_rectangle(abs_clb_bbox); @@ -980,7 +991,6 @@ static void drawplace(ezgl::renderer* g) { g->draw_rectangle(abs_clb_bbox); /* Draw text if the space has parts of the netlist */ if (bnum != EMPTY_BLOCK_ID && bnum != INVALID_BLOCK_ID) { - auto& cluster_ctx = g_vpr_ctx.clustering(); std::string name = cluster_ctx.clb_nlist.block_name(bnum) + vtr::string_fmt(" (#%zu)", size_t(bnum)); g->draw_text(center, name.c_str(), abs_clb_bbox.width(), abs_clb_bbox.height()); @@ -2730,13 +2740,27 @@ void deselect_all() { } static void draw_reset_blk_color(ClusterBlockId blk_id) { - auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; + t_draw_state* draw_state = get_draw_state_vars(); - auto logical_block = clb_nlist.block_type(blk_id); + auto& place_ctx = g_vpr_ctx.placement(); - t_draw_state* draw_state = get_draw_state_vars(); + t_physical_tile_type_ptr tile_type = nullptr; + if (place_ctx.block_locs.empty()) { + //No placement, use best guess tile type color + auto& cluster_ctx = g_vpr_ctx.clustering(); + + tile_type = pick_best_physical_type(cluster_ctx.clb_nlist.block_type(blk_id)); + } else { + //Color the block to match the tile where it is placed + auto& device_ctx = g_vpr_ctx.device(); + auto& grid = device_ctx.grid; + + t_pl_loc loc = place_ctx.block_locs[blk_id].loc; + + tile_type = grid[loc.x][loc.y].type; + } - draw_state->block_color[blk_id] = get_block_type_color(pick_best_physical_type(logical_block)); + draw_state->block_color[blk_id] = get_block_type_color(tile_type); } /** diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index 5d6e4ca7a83..e19aee8cdf4 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -75,6 +75,25 @@ ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block return result; } +ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { + auto& device_ctx = g_vpr_ctx.device(); + t_draw_pb_type_info& blk_type_info = this->blk_info.at(logical_block_type->index); + + auto& pb_gnode = *logical_block_type->pb_graph_head; + ezgl::rectangle result = blk_type_info.get_pb_bbox(pb_gnode); + + // if getting clb bbox, apply location info. + if (pb_gnode.is_root()) { + float sub_blk_offset = this->tile_width * (sub_block_index / (float)device_ctx.grid[grid_x][grid_y].type->capacity); + + result += ezgl::point2d(this->tile_x[grid_x], this->tile_y[grid_y]); + if (sub_block_index != 0) { + result += ezgl::point2d(sub_blk_offset, 0); + } + } + return result; +} + ezgl::rectangle t_draw_coords::get_absolute_pb_bbox(const ClusterBlockId clb_index, const t_pb_graph_node* pb_gnode) { ezgl::rectangle result = this->get_pb_bbox(clb_index, *pb_gnode); @@ -98,4 +117,8 @@ ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int return get_pb_bbox(grid_x, grid_y, sub_block_index, *pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)->pb_graph_head); } +ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { + return get_pb_bbox(grid_x, grid_y, sub_block_index, logical_block_type); +} + #endif // NO_GRAPHICS diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index f6e507a02ac..4f4a12dbda4 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -229,6 +229,7 @@ struct t_draw_coords { */ ezgl::rectangle get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode); ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode); + ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type); /** * Return a bounding box for the given pb in the given @@ -242,6 +243,7 @@ struct t_draw_coords { */ ezgl::rectangle get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type); ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index); + ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr pb_gnode); private: float tile_width; diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 2ce4fc4b5d7..48e08c02436 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -90,17 +90,24 @@ void draw_internal_init_blk() { t_pb_graph_node* pb_graph_head_node; auto& device_ctx = g_vpr_ctx.device(); - for (const auto& type : device_ctx.physical_tile_types) { + for (const auto& type : device_ctx.logical_block_types) { /* Empty block has no sub_blocks */ if (is_empty_type(&type)) { continue; } - auto logical_block = pick_best_logical_type(&type); - pb_graph_head_node = logical_block->pb_graph_head; + pb_graph_head_node = type.pb_graph_head; int type_descriptor_index = type.index; - int num_sub_tiles = type.capacity; + //We use the maximum over all tiles which can implement this logical block type + int num_sub_tiles = 1; + int width = 1; + int height = 1; + for (const auto& tile : type.equivalent_tiles) { + num_sub_tiles = std::max(num_sub_tiles, tile->capacity); + width = std::max(width, tile->width); + height = std::max(height, tile->height); + } // set the clb dimensions ezgl::rectangle& clb_bbox = draw_coords->blk_info.at(type_descriptor_index).subblk_array.at(0); @@ -110,17 +117,17 @@ void draw_internal_init_blk() { // note, that all clbs of the same type are the same size, // and that consequently we have *one* model for each type. bot_left = {0, 0}; - if (size_t(type.width) > device_ctx.grid.width() || size_t(type.height) > device_ctx.grid.height()) { + if (size_t(width) > device_ctx.grid.width() || size_t(height) > device_ctx.grid.height()) { // in this case, the clb certainly wont't fit, but this prevents // an out-of-bounds access, and provides some sort of (probably right) // value top_right = ezgl::point2d( - (draw_coords->tile_x[1] - draw_coords->tile_x[0]) * (type.width - 1), - (draw_coords->tile_y[1] - draw_coords->tile_y[0]) * (type.height - 1)); + (draw_coords->tile_x[1] - draw_coords->tile_x[0]) * (width - 1), + (draw_coords->tile_y[1] - draw_coords->tile_y[0]) * (height - 1)); } else { top_right = ezgl::point2d( - draw_coords->tile_x[type.width - 1], - draw_coords->tile_y[type.height - 1]); + draw_coords->tile_x[width - 1], + draw_coords->tile_y[height - 1]); } top_right += ezgl::point2d( draw_coords->get_tile_width() / num_sub_tiles, @@ -131,7 +138,7 @@ void draw_internal_init_blk() { clb_bbox.width(), clb_bbox.height()); /* Determine the max number of sub_block levels in the FPGA */ - draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*logical_block->pb_type), + draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*type.pb_type), draw_state->max_sub_blk_lvl); } } From c2e486321af25399f026e5dd8d66e57e0cb87a09 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 18:32:37 -0500 Subject: [PATCH 007/107] vpr: Fix drawing block mouse selection --- vpr/src/draw/draw_types.cpp | 9 ++++++--- vpr/src/draw/draw_types.h | 3 ++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index e19aee8cdf4..f96ac882b32 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -108,13 +108,16 @@ ezgl::rectangle t_draw_coords::get_absolute_pb_bbox(const ClusterBlockId clb_ind return result; } -ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type) { - return get_pb_bbox(clb_index, *type->pb_graph_head); +ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr block_type) { + auto& place_ctx = g_vpr_ctx.placement(); + + t_pl_loc loc = place_ctx.block_locs[clb_index].loc; + return get_pb_bbox(loc.x, loc.y, loc.z, block_type); } ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index) { auto& device_ctx = g_vpr_ctx.device(); - return get_pb_bbox(grid_x, grid_y, sub_block_index, *pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)->pb_graph_head); + return get_pb_bbox(grid_x, grid_y, sub_block_index, pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)); } ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 4f4a12dbda4..921ed240c28 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -243,7 +243,8 @@ struct t_draw_coords { */ ezgl::rectangle get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type); ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index); - ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr pb_gnode); + + ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr block_type); private: float tile_width; From 2f6023eebfcdd673158ee50b9c98b8d9072655c7 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 18:56:21 -0500 Subject: [PATCH 008/107] vpr: Fix drawing of block internals Previously only the first block type's internals were drawn. --- vpr/src/draw/draw_types.cpp | 8 ++++---- vpr/src/draw/draw_types.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index f96ac882b32..30f05c61f31 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -53,13 +53,13 @@ float t_draw_coords::get_tile_height() { ezgl::rectangle t_draw_coords::get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode) { auto& place_ctx = g_vpr_ctx.placement(); - return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, pb_gnode); + auto& cluster_ctx = g_vpr_ctx.clustering(); + return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, cluster_ctx.clb_nlist.block_type(clb_index), pb_gnode); } -ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode) { +ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type, const t_pb_graph_node& pb_gnode) { auto& device_ctx = g_vpr_ctx.device(); - const int clb_type_id = device_ctx.grid[grid_x][grid_y].type->index; - t_draw_pb_type_info& blk_type_info = this->blk_info.at(clb_type_id); + t_draw_pb_type_info& blk_type_info = this->blk_info.at(logical_block_type->index); ezgl::rectangle result = blk_type_info.get_pb_bbox(pb_gnode); diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 921ed240c28..86d6718ed69 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -228,7 +228,7 @@ struct t_draw_coords { * clb, from this data structure */ ezgl::rectangle get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode); - ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode); + ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type, const t_pb_graph_node& pb_gnode); ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type); /** From b6f1c115f0a50ce41f18171bf7a5d789586d647d Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 19:23:26 -0500 Subject: [PATCH 009/107] vpr: Fix color of drawn block internals to match tile color --- vpr/src/draw/draw.cpp | 1 - vpr/src/draw/draw.h | 2 ++ vpr/src/draw/intra_logic_block.cpp | 9 +-------- vpr/src/util/vpr_utils.cpp | 14 ++++++++++++++ vpr/src/util/vpr_utils.h | 8 ++++++++ 5 files changed, 25 insertions(+), 9 deletions(-) diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index b13d8e1e121..941cca27bf4 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -124,7 +124,6 @@ static t_edge_size find_edge(int prev_inode, int inode); static void draw_color_map_legend(const vtr::ColorMap& cmap, ezgl::renderer* g); -ezgl::color get_block_type_color(t_physical_tile_type_ptr type); ezgl::color lighten_color(ezgl::color color, float amount); static void draw_block_pin_util(); diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index eb8dd4c2df7..acc9d214572 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -77,6 +77,8 @@ void toggle_block_pin_util(GtkWidget* /*widget*/, gint /*response_id*/, gpointer void toggle_router_rr_costs(GtkWidget* /*widget*/, gint /*response_id*/, gpointer /*data*/); void toggle_placement_macros(GtkWidget* /*widget*/, gint /*response_id*/, gpointer /*data*/); +ezgl::color get_block_type_color(t_physical_tile_type_ptr type); + #endif /* NO_GRAPHICS */ #endif /* DRAW_H */ diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 48e08c02436..5f9634ab12c 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -356,9 +356,6 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg // If block is used, draw it in colour with solid border. g->set_line_dash(ezgl::line_dash::none); - // type_index indicates what type of block. - const int type_index = type->index; - // determine default background color if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { g->set_color(SELECTED_COLOR); @@ -368,12 +365,8 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg g->set_color(DRIVEN_BY_IT_COLOR); } else if (pb_type->depth != draw_state->show_blk_internal && pb->child_pbs != nullptr) { g->set_color(ezgl::WHITE); // draw anything else that will have a child as white - } else if (type_index < 3) { - g->set_color(blk_LIGHTGREY); - } else if (type_index < 3 + MAX_BLOCK_COLOURS) { - g->set_color((block_colors[MAX_BLOCK_COLOURS + type_index - 3])); } else { - g->set_color((block_colors[2 * MAX_BLOCK_COLOURS - 1])); + g->set_color(draw_state->block_color[clb_index]); } } else { // If block is not used, draw as empty block (ie. white diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 69e712d4999..e19d1720915 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -2114,6 +2114,20 @@ t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physica return physical_tile->equivalent_sites[0]; } +t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk) { + auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& place_ctx = g_vpr_ctx.placement(); + if (place_ctx.block_locs.empty()) { //No placement, pick best match + return pick_best_physical_type(cluster_ctx.clb_nlist.block_type(blk)); + } else { //Have placement, select physical tile implementing blk + auto& device_ctx = g_vpr_ctx.device(); + + t_pl_loc loc = place_ctx.block_locs[blk].loc; + + return device_ctx.grid[loc.x][loc.y].type; + } +} + int get_logical_pin(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int pin) { diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index d05dc88173e..e43cc91dacd 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -154,9 +154,17 @@ void place_sync_external_block_connections(ClusterBlockId iblk); int get_max_num_pins(t_logical_block_type_ptr logical_block); bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block); + +//Returns the physical tile type which 'best' matches logical_block t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block); + +//Returns the logical block type which 'best' matches the physical tile t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physical_tile); +//Returns the current tile implemnting blk (if placement is valid), or +//the best expected physical tile the block should use (if no valid placement). +t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk); + int get_logical_pin(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int pin); From 5b7ec33aae0e7e7fd3eb7ee3dc1516b5c0152d38 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 19:26:57 -0500 Subject: [PATCH 010/107] vpr: Remove MAX_BLOCK_COLORS --- vpr/src/draw/draw_global.h | 2 -- vpr/src/draw/intra_logic_block.cpp | 13 ++----------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/vpr/src/draw/draw_global.h b/vpr/src/draw/draw_global.h index 68e6df6062d..158546f7ec4 100644 --- a/vpr/src/draw/draw_global.h +++ b/vpr/src/draw/draw_global.h @@ -15,8 +15,6 @@ # include "draw_types.h" -# define MAX_BLOCK_COLOURS 5 - constexpr float DEFAULT_ARROW_SIZE = 0.3; // a very small area, in (screen pixels)^2 diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 5f9634ab12c..3c1739ee26e 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -671,17 +671,8 @@ static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_lo /* Call accessor function to retrieve global variables. */ draw_state = get_draw_state_vars(); - if (type->index < 3) { - if (draw_state->block_color[blk_id] == blk_LIGHTGREY) - return false; - } else if (type->index < 3 + MAX_BLOCK_COLOURS) { - if (draw_state->block_color[blk_id] == block_colors[MAX_BLOCK_COLOURS + type->index - 3]) - // if (draw_state->block_color[blk_id] == to_ezgl_color((color_types)(BISQUE + MAX_BLOCK_COLOURS + type->index - 3))) - return false; - } else { - if (draw_state->block_color[blk_id] == block_colors[2 * MAX_BLOCK_COLOURS - 1]) - // if (draw_state->block_color[blk_id] == to_ezgl_color((color_types)(BISQUE + 2 * MAX_BLOCK_COLOURS - 1))) - return false; + if (draw_state->block_color[blk_id] == get_block_type_color(get_physical_tile_type(blk_id))) { + return false; } return true; From 5fc282cc4484362ab44425cd5ae0990a5f11e833 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 19:34:32 -0500 Subject: [PATCH 011/107] vpr: Remove unused parameter --- vpr/src/draw/intra_logic_block.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 3c1739ee26e..4f67bdcd239 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -40,7 +40,7 @@ static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height); static int draw_internal_find_max_lvl(const t_pb_type& pb_type); static void draw_internal_calc_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, int num_pb_types, int type_index, int num_pb, int pb_index, float parent_width, float parent_height, float* blk_width, float* blk_height); -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_logical_block_type_ptr type); +static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id); std::vector collect_pb_atoms(const t_pb* pb); void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms); t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const ezgl::point2d& local_pt, int max_depth); @@ -341,7 +341,7 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg /// first draw box /// if (pb_type->depth == 0) { - if (!is_top_lvl_block_highlighted(clb_index, type)) { + if (!is_top_lvl_block_highlighted(clb_index)) { // if this is a top level pb, and only if it isn't selected (ie. a funny colour), // overwrite it. (but stil draw the text) @@ -665,7 +665,7 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p /* This function checks whether a top-level clb has been highlighted. It does * so by checking whether the color in this block is default color. */ -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_logical_block_type_ptr type) { +static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id) { t_draw_state* draw_state; /* Call accessor function to retrieve global variables. */ From 5d64b8cbee1e34cd1bf7c9caaa7cbd1c2a9d929a Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 19:51:13 -0500 Subject: [PATCH 012/107] vpr: Fix drawing of lowest sub-block level Previously this was incorrectly skipped. Also fixes range on GUI selector. --- vpr/src/draw/buttons.cpp | 2 +- vpr/src/draw/intra_logic_block.cpp | 80 ++++++++++-------------------- 2 files changed, 26 insertions(+), 56 deletions(-) diff --git a/vpr/src/draw/buttons.cpp b/vpr/src/draw/buttons.cpp index 21a2781ee31..aac65fff2e3 100644 --- a/vpr/src/draw/buttons.cpp +++ b/vpr/src/draw/buttons.cpp @@ -59,7 +59,7 @@ void button_for_toggle_blk_internal() { t_draw_state* draw_state = get_draw_state_vars(); //spin box for toggle_blk_internal, set the range and increment step - GtkWidget* toggle_blk_internal_widget = gtk_spin_button_new_with_range(0., (double)draw_state->max_sub_blk_lvl, 1.); + GtkWidget* toggle_blk_internal_widget = gtk_spin_button_new_with_range(0., (double)(draw_state->max_sub_blk_lvl - 1), 1.); GtkWidget* toggle_blk_internal_label = gtk_label_new("Toggle Block Internal:"); gtk_widget_set_name(toggle_blk_internal_widget, "toggle_blk_internal"); diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 4f67bdcd239..42e5f610f3d 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -40,7 +40,6 @@ static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height); static int draw_internal_find_max_lvl(const t_pb_type& pb_type); static void draw_internal_calc_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, int num_pb_types, int type_index, int num_pb, int pb_index, float parent_width, float parent_height, float* blk_width, float* blk_height); -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id); std::vector collect_pb_atoms(const t_pb* pb); void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms); t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const ezgl::point2d& local_pt, int max_depth); @@ -141,6 +140,7 @@ void draw_internal_init_blk() { draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*type.pb_type), draw_state->max_sub_blk_lvl); } + //draw_state->max_sub_blk_lvl -= 1; } # ifndef NO_GRAPHICS @@ -338,47 +338,33 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg if (pb_type->depth > draw_state->show_blk_internal) { return; } - /// first draw box /// - if (pb_type->depth == 0) { - if (!is_top_lvl_block_highlighted(clb_index)) { - // if this is a top level pb, and only if it isn't selected (ie. a funny colour), - // overwrite it. (but stil draw the text) + /// first draw box /// - g->set_color(ezgl::WHITE); - g->fill_rectangle(abs_bbox); - g->set_color(ezgl::BLACK); - g->set_line_dash(ezgl::line_dash::none); - g->draw_rectangle(abs_bbox); + if (pb->name != nullptr) { + // If block is used, draw it in colour with solid border. + g->set_line_dash(ezgl::line_dash::none); + + // determine default background color + if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { + g->set_color(SELECTED_COLOR); + } else if (sel_sub_info.is_sink_of_selected(pb->pb_graph_node, clb_index)) { + g->set_color(DRIVES_IT_COLOR); + } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { + g->set_color(DRIVEN_BY_IT_COLOR); + } else { + g->set_color(draw_state->block_color[clb_index]); } } else { - if (pb->name != nullptr) { - // If block is used, draw it in colour with solid border. - g->set_line_dash(ezgl::line_dash::none); - - // determine default background color - if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { - g->set_color(SELECTED_COLOR); - } else if (sel_sub_info.is_sink_of_selected(pb->pb_graph_node, clb_index)) { - g->set_color(DRIVES_IT_COLOR); - } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { - g->set_color(DRIVEN_BY_IT_COLOR); - } else if (pb_type->depth != draw_state->show_blk_internal && pb->child_pbs != nullptr) { - g->set_color(ezgl::WHITE); // draw anything else that will have a child as white - } else { - g->set_color(draw_state->block_color[clb_index]); - } - } else { - // If block is not used, draw as empty block (ie. white - // background with dashed border). + // If block is not used, draw as empty block (ie. white + // background with dashed border). - g->set_line_dash(ezgl::line_dash::asymmetric_5_3); - g->set_color(ezgl::WHITE); - } - g->fill_rectangle(abs_bbox); - g->set_color(ezgl::BLACK); - g->draw_rectangle(abs_bbox); + g->set_line_dash(ezgl::line_dash::asymmetric_5_3); + g->set_color(ezgl::WHITE); } + g->fill_rectangle(abs_bbox); + g->set_color(ezgl::BLACK); + g->draw_rectangle(abs_bbox); /// then draw text /// @@ -393,7 +379,7 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg int tot_len = type_len + name_len; char* blk_tag = (char*)vtr::malloc((tot_len + 8) * sizeof(char)); - sprintf(blk_tag, "%s(%s)", pb_type->name, pb->name); + sprintf(blk_tag, "%s (%s)", pb_type->name, pb->name); g->draw_text( abs_bbox.center(), @@ -444,10 +430,10 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg t_pb_type* pb_child_type = child_pb->pb_graph_node->pb_type; - // don't go farther if 0 modes - if (pb_child_type == nullptr || pb_child_type->num_modes == 0) { + if (pb_child_type == nullptr) { continue; } + // now recurse draw_internal_pb(clb_index, child_pb, abs_bbox, type, g); } @@ -662,22 +648,6 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p } # endif /* NO_GRAPHICS */ -/* This function checks whether a top-level clb has been highlighted. It does - * so by checking whether the color in this block is default color. - */ -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id) { - t_draw_state* draw_state; - - /* Call accessor function to retrieve global variables. */ - draw_state = get_draw_state_vars(); - - if (draw_state->block_color[blk_id] == get_block_type_color(get_physical_tile_type(blk_id))) { - return false; - } - - return true; -} - int highlight_sub_block(const ezgl::point2d& point_in_clb, ClusterBlockId clb_index, t_pb* pb) { t_draw_state* draw_state = get_draw_state_vars(); From f7a6462069d9d5809f14a6f1b7eae17fa3a9545f Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 19:55:51 -0500 Subject: [PATCH 013/107] vpr: Include pin name in RR node no fanin warning --- vpr/src/route/check_rr_graph.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp index 2c0e7c435a1..66609917624 100644 --- a/vpr/src/route/check_rr_graph.cpp +++ b/vpr/src/route/check_rr_graph.cpp @@ -177,8 +177,9 @@ void check_rr_graph(const t_graph_type graph_type, if (node.type() == IPIN || node.type() == OPIN) { if (has_adjacent_channel(node, device_ctx.grid)) { auto block_type = device_ctx.grid[node.xlow()][node.ylow()].type; - VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s has no fanin.\n", - inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string()); + std::string pin_name = block_type_pin_index_to_name(block_type, node.pin_num()); + VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s pin=%s has no fanin.\n", + inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string(), pin_name.c_str()); } } else { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) has no fanin.\n", From 079b4389557dc72dc2b6e9c6f72a5aa38847f9da Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 20:41:55 -0500 Subject: [PATCH 014/107] vpr: Update grid sizing to be equvalent sites aware This avoids significantly bloating the auto-sized device if a logical block type (e.g. LAB) can be implemented at multiple sites (e.g. LAB or MLAB). --- vpr/src/base/SetupGrid.cpp | 71 +++++++++++++++++++++++------------- vpr/src/base/device_grid.cpp | 2 +- vpr/src/base/device_grid.h | 6 +-- 3 files changed, 50 insertions(+), 29 deletions(-) diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index 982f313cafc..e306dda21a5 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -25,9 +25,9 @@ #include "expr_eval.h" static DeviceGrid auto_size_device_grid(const std::vector& grid_layouts, const std::map& minimum_instance_counts, float maximum_device_utilization); -static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); +static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, std::map instance_counts, float maximum_utilization); -static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, std::vector limiting_resources = std::vector()); +static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, std::vector limiting_resources = std::vector()); static void CheckGrid(const DeviceGrid& grid); @@ -152,7 +152,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo //specifications size_t width = 3; size_t height = 3; - std::vector limiting_resources; + std::vector limiting_resources; do { //Scale opposite dimension to match aspect ratio height = vtr::nint(width / grid_def.aspect_ratio); @@ -203,7 +203,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo }; std::stable_sort(grid_layouts_view.begin(), grid_layouts_view.end(), area_cmp); - std::vector limiting_resources; + std::vector limiting_resources; //Try all the fixed devices in order from smallest to largest for (const auto* grid_def : grid_layouts_view) { @@ -220,37 +220,58 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo return grid; //Unreachable } -static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts) { +static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts) { + //Estimates what logical block types will be unimplementable due to resource limits in the available grid + // + //Performs a fast counting based estimate, allocating the least flexible block types (those with the fewest + //equivalent tiles) first. auto& device_ctx = g_vpr_ctx.device(); - std::vector overused_resources; + std::vector overused_resources; std::unordered_map min_count_map; // Initialize min_count_map - for (const auto& physical_tile : device_ctx.physical_tile_types) { - min_count_map.insert(std::make_pair(&physical_tile, size_t(0))); + for (const auto& tile_type : device_ctx.physical_tile_types) { + min_count_map.insert(std::make_pair(&tile_type, size_t(0))); } - //Are the resources satisified? - for (auto kv : instance_counts) { - t_physical_tile_type_ptr type = nullptr; + //Initialize available tile counts + std::unordered_map avail_tiles; + for (auto& tile_type : device_ctx.physical_tile_types) { + avail_tiles[&tile_type] = grid.num_instances(&tile_type); + } - size_t inst_cnt = 0; - for (auto& physical_tile : kv.first->equivalent_tiles) { - size_t tmp_inst_cnt = grid.num_instances(physical_tile); + //Sort so we allocate logical blocks with the fewest equivalent sites first (least flexible) + std::vector logical_block_types; + for (auto& block_type : device_ctx.logical_block_types) { + logical_block_types.push_back(&block_type); + } - if (inst_cnt <= tmp_inst_cnt) { - type = physical_tile; - inst_cnt = tmp_inst_cnt; - } - } + auto by_ascending_equiv_tiles = [](t_logical_block_type_ptr lhs, t_logical_block_type_ptr rhs) { + return lhs->equivalent_tiles.size() < rhs->equivalent_tiles.size(); + }; + std::stable_sort(logical_block_types.begin(), logical_block_types.end(), by_ascending_equiv_tiles); + + //Allocate logical blocks to available tiles + for (auto block_type : logical_block_types) { + if (instance_counts.count(block_type)) { + int required_blocks = instance_counts[block_type]; + + for (auto tile_type : block_type->equivalent_tiles) { + if (avail_tiles[tile_type] >= required_blocks) { + avail_tiles[tile_type] -= required_blocks; + required_blocks = 0; + } else { + required_blocks -= avail_tiles[tile_type]; + avail_tiles[tile_type] = 0; + } - VTR_ASSERT(type); - size_t min_count = min_count_map.at(type) + kv.second; - min_count_map.at(type) = min_count; + if (required_blocks == 0) break; + } - if (inst_cnt < min_count) { - overused_resources.push_back(type); + if (required_blocks > 0) { + overused_resources.push_back(block_type); + } } } @@ -276,7 +297,7 @@ static bool grid_satisfies_instance_counts(const DeviceGrid& grid, std::map limiting_resources) { +static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range, const std::vector limiting_resources) { if (grid_def.grid_type == GridDefType::FIXED) { if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, diff --git a/vpr/src/base/device_grid.cpp b/vpr/src/base/device_grid.cpp index 3be488d26dd..e4e05a7241c 100644 --- a/vpr/src/base/device_grid.cpp +++ b/vpr/src/base/device_grid.cpp @@ -7,7 +7,7 @@ DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid) count_instances(); } -DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res) +DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res) : DeviceGrid(grid_name, grid) { limiting_resources_ = limiting_res; } diff --git a/vpr/src/base/device_grid.h b/vpr/src/base/device_grid.h index 6f0584c94db..44bdc8b6659 100644 --- a/vpr/src/base/device_grid.h +++ b/vpr/src/base/device_grid.h @@ -8,7 +8,7 @@ class DeviceGrid { public: DeviceGrid() = default; DeviceGrid(std::string grid_name, vtr::Matrix grid); - DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res); + DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res); const std::string& name() const { return name_; } @@ -25,7 +25,7 @@ class DeviceGrid { //Returns the block types which limits the device size (may be empty if //resource limits were not considered when selecting the device). - std::vector limiting_resources() const { return limiting_resources_; } + std::vector limiting_resources() const { return limiting_resources_; } private: void count_instances(); @@ -39,7 +39,7 @@ class DeviceGrid { std::map instance_counts_; - std::vector limiting_resources_; + std::vector limiting_resources_; }; #endif From ee51cbe43132b3da692282412fdb9f5ecb78fc56 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 20:59:45 -0500 Subject: [PATCH 015/107] vpr: Improve initial macro placement to consider equivalent tile locations Initial placement now tries all equivalent tile locations before giving up when placing macros. --- vpr/src/place/initial_placement.cpp | 85 ++++++++++++++--------------- 1 file changed, 41 insertions(+), 44 deletions(-) diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 8a1f0e12e94..6631e3f70e8 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -167,7 +167,6 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca ClusterBlockId blk_id; auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); auto& place_ctx = g_vpr_ctx.placement(); auto& pl_macros = place_ctx.pl_macros; @@ -185,9 +184,7 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca return lhs_num_tiles < rhs_num_tiles; }; - if (device_ctx.has_multiple_equivalent_tiles) { - std::sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); - } + std::stable_sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); /* Macros are harder to place. Do them first */ for (auto pl_macro : sorted_pl_macros) { @@ -196,57 +193,57 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca // Assume that all the blocks in the macro are of the same type blk_id = pl_macro.members[0].blk_index; - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - auto type = pick_placement_type(logical_block, int(pl_macro.members.size()), free_locations); + auto block_type = cluster_ctx.clb_nlist.block_type(blk_id); - if (type == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n" - "VPR cannot auto-size for your circuit, please resize the FPGA manually.\n", - pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); - } - - itype = type->index; - - // Try to place the macro first, if can be placed - place them, otherwise try again - for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) { - // Choose a random position for the head - ipos = vtr::irand(free_locations[itype] - 1); + for (auto tile_type : block_type->equivalent_tiles) { //Try each possible tile type + itype = tile_type->index; - // Try to place the macro - macro_placed = try_place_macro(itype, ipos, pl_macro); + // Try to place the macro first, if can be placed - place them, otherwise try again + for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) { + // Choose a random position for the head + ipos = vtr::irand(free_locations[itype] - 1); - } // Finished all tries - - if (macro_placed == false) { - // if a macro still could not be placed after macros_max_num_tries times, - // go through the chip exhaustively to find a legal placement for the macro - // place the macro on the first location that is legal - // then set macro_placed = true; - // if there are no legal positions, error out - - // Exhaustive placement of carry macros - for (ipos = 0; ipos < free_locations[itype] && macro_placed == false; ipos++) { // Try to place the macro macro_placed = try_place_macro(itype, ipos, pl_macro); - } // Exhausted all the legal placement position for this macro + } // Finished all tries - // If macro could not be placed after exhaustive placement, error out if (macro_placed == false) { - // Error out - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n" - "Please manually size the FPGA because VPR can't do this yet.\n", - pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), device_ctx.physical_tile_types[itype].name, itype); + // if a macro still could not be placed after macros_max_num_tries times, + // go through the chip exhaustively to find a legal placement for the macro + // place the macro on the first location that is legal + // then set macro_placed = true; + // if there are no legal positions, error out + + // Exhaustive placement of carry macros + for (ipos = 0; ipos < free_locations[itype] && macro_placed == false; ipos++) { + // Try to place the macro + macro_placed = try_place_macro(itype, ipos, pl_macro); + + } // Exhausted all the legal placement position for this macro + + // If macro could not be placed after exhaustive placement, error out + } else { + // This macro has been placed successfully + break; } + } - } else { - // This macro has been placed successfully, proceed to place the next macro - continue; + if (macro_placed == false) { + std::vector tried_types; + for (auto tile_type : block_type->equivalent_tiles) { + tried_types.push_back(tile_type->name); + } + std::string tried_types_str = "{" + vtr::join(tried_types, ", ") + "}"; + + // Error out + VPR_FATAL_ERROR(VPR_ERROR_PLACE, + "Initial placement failed.\n" + "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type(s) %s.\n" + "Please manually size the FPGA because VPR can't do this yet.\n", + pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), tried_types_str.c_str()); } + } // Finish placing all the pl_macros successfully } From f063aeca534606c17a594ad435ea41de68de0835 Mon Sep 17 00:00:00 2001 From: kmurray Date: Tue, 10 Dec 2019 21:33:20 -0500 Subject: [PATCH 016/107] vpr: Encapsulate block color drawing state The drawing code now directly looks-up the default block color based on the placement state. This avoids having to synchronize it manually and fixes a crash when graphics is turned off. --- vpr/src/draw/draw.cpp | 45 ++++++++---------------------- vpr/src/draw/draw_types.cpp | 24 ++++++++++++++++ vpr/src/draw/draw_types.h | 11 +++++++- vpr/src/draw/intra_logic_block.cpp | 2 +- 4 files changed, 46 insertions(+), 36 deletions(-) diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 941cca27bf4..505928cf667 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -499,11 +499,6 @@ void update_screen(ScreenUpdatePriority priority, const char* msg, enum pic_type } } - //Block placements may have changed since previous invocation, - //so we need to update the block colors in case blocks have changed - //the tiles where they are implemented - draw_reset_blk_colors(); - if (draw_state->show_graphics) { application.update_message(msg); application.refresh_drawing(); @@ -830,7 +825,8 @@ void alloc_draw_structs(const t_arch* arch) { draw_internal_alloc_blk(); draw_state->net_color.resize(cluster_ctx.clb_nlist.nets().size()); - draw_state->block_color.resize(cluster_ctx.clb_nlist.blocks().size()); + draw_state->block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); + draw_state->use_default_block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); /* Space is allocated for draw_rr_node but not initialized because we do * * not yet know information about the routing resources. */ @@ -968,7 +964,7 @@ static void drawplace(ezgl::renderer* g) { ezgl::color block_color; t_logical_block_type_ptr logical_block_type = nullptr; if (bnum != EMPTY_BLOCK_ID) { - block_color = draw_state->block_color[bnum]; + block_color = draw_state->block_color(bnum); logical_block_type = cluster_ctx.clb_nlist.block_type(bnum); } else { block_color = get_block_type_color(device_ctx.grid[i][j].type); @@ -2675,7 +2671,7 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b iclass = physical_tile->pin_class[physical_pin]; if (physical_tile->class_inf[iclass].type == DRIVER) { /* Fanout */ - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanout. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { @@ -2687,11 +2683,11 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b draw_state->net_color[net_id] = DRIVES_IT_COLOR; for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { fanblk = cluster_ctx.clb_nlist.pin_block(pin_id); - draw_state->block_color[fanblk] = DRIVES_IT_COLOR; + draw_state->set_block_color(fanblk, DRIVES_IT_COLOR); } } } else { /* This net is fanin to the block. */ - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanin. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; fanblk = cluster_ctx.clb_nlist.net_driver_block(net_id); /* DRIVER to net */ @@ -2700,17 +2696,17 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b /* Highlight the fanin */ draw_state->net_color[net_id] = DRIVEN_BY_IT_COLOR; fanblk = cluster_ctx.clb_nlist.net_driver_block(net_id); /* DRIVER to net */ - draw_state->block_color[fanblk] = DRIVEN_BY_IT_COLOR; + draw_state->set_block_color(fanblk, DRIVEN_BY_IT_COLOR); } } } - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the selected block. */ draw_reset_blk_color(blk_id); } else { /* Highlight the selected block. */ - draw_state->block_color[blk_id] = SELECTED_COLOR; + draw_state->set_block_color(blk_id, SELECTED_COLOR); } } @@ -2740,26 +2736,7 @@ void deselect_all() { static void draw_reset_blk_color(ClusterBlockId blk_id) { t_draw_state* draw_state = get_draw_state_vars(); - - auto& place_ctx = g_vpr_ctx.placement(); - - t_physical_tile_type_ptr tile_type = nullptr; - if (place_ctx.block_locs.empty()) { - //No placement, use best guess tile type color - auto& cluster_ctx = g_vpr_ctx.clustering(); - - tile_type = pick_best_physical_type(cluster_ctx.clb_nlist.block_type(blk_id)); - } else { - //Color the block to match the tile where it is placed - auto& device_ctx = g_vpr_ctx.device(); - auto& grid = device_ctx.grid; - - t_pl_loc loc = place_ctx.block_locs[blk_id].loc; - - tile_type = grid[loc.x][loc.y].type; - } - - draw_state->block_color[blk_id] = get_block_type_color(tile_type); + draw_state->reset_block_color(blk_id); } /** @@ -3360,7 +3337,7 @@ static void draw_block_pin_util() { for (auto blk : blks) { ezgl::color color = to_ezgl_color(cmap->color(pin_util[blk])); - draw_state->block_color[blk] = color; + draw_state->set_block_color(blk, color); } draw_state->color_map = std::move(cmap); diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index 30f05c61f31..fdb0755b689 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -4,11 +4,34 @@ # include "draw_types.h" # include "globals.h" # include "vpr_utils.h" +# include "draw.h" # include /******************************************* * begin t_draw_state function definitions * *******************************************/ +ezgl::color t_draw_state::block_color(ClusterBlockId blk) const { + if (use_default_block_color_[blk]) { + t_physical_tile_type_ptr tile_type = get_physical_tile_type(blk); + return get_block_type_color(tile_type); + } else { + return block_color_[blk]; + } +} + +void t_draw_state::set_block_color(ClusterBlockId blk, ezgl::color color) { + block_color_[blk] = color; + use_default_block_color_[blk] = false; +} + +void t_draw_state::reset_block_color(ClusterBlockId blk) { + use_default_block_color_[blk] = true; +} +void t_draw_state::reset_block_colors() { + std::fill(use_default_block_color_.begin(), + use_default_block_color_.end(), + true); +} void t_draw_state::reset_nets_congestion_and_rr() { show_nets = DRAW_NO_NETS; @@ -19,6 +42,7 @@ void t_draw_state::reset_nets_congestion_and_rr() { bool t_draw_state::showing_sub_blocks() { return show_blk_internal > 0; } + /************************************************** * begin t_draw_pb_type_info function definitions * **************************************************/ diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 86d6718ed69..1ef320afabc 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -172,7 +172,6 @@ struct t_draw_state { e_route_type draw_route_type = GLOBAL; char default_message[vtr::bufsize]; vtr::vector net_color; - vtr::vector block_color; t_draw_rr_node* draw_rr_node = nullptr; std::shared_ptr setup_timing_info; const t_arch* arch_info = nullptr; @@ -185,6 +184,16 @@ struct t_draw_state { void reset_nets_congestion_and_rr(); bool showing_sub_blocks(); + + ezgl::color block_color(ClusterBlockId blk) const; + void set_block_color(ClusterBlockId blk, ezgl::color color); + void reset_block_color(ClusterBlockId blk); + void reset_block_colors(); + + private: + friend void alloc_draw_structs(const t_arch* arch); + vtr::vector block_color_; + vtr::vector use_default_block_color_; }; /* For each cluster type, this structure stores drawing diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index 42e5f610f3d..2c2166ecd95 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -353,7 +353,7 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { g->set_color(DRIVEN_BY_IT_COLOR); } else { - g->set_color(draw_state->block_color[clb_index]); + g->set_color(draw_state->block_color(clb_index)); } } else { // If block is not used, draw as empty block (ie. white From 96cd66489e593296ccba3ecf782145a0e17d09e2 Mon Sep 17 00:00:00 2001 From: kmurray Date: Wed, 11 Dec 2019 13:22:05 -0500 Subject: [PATCH 017/107] vpr: Tweak post-placement resource usage format New format includes enough context to parse as a single line --- vpr/src/place/place.cpp | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index 8a2b32fd962..0d82de03fdf 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -800,6 +800,8 @@ void try_place(const t_placer_opts& placer_opts, size_t total_swap_attempts = num_swap_rejected + num_swap_accepted + num_swap_aborted; VTR_ASSERT(total_swap_attempts > 0); + print_resources_utilization(); + size_t num_swap_print_digits = ceil(log10(total_swap_attempts)); float reject_rate = (float)num_swap_rejected / total_swap_attempts; float accept_rate = (float)num_swap_accepted / total_swap_attempts; @@ -812,8 +814,6 @@ void try_place(const t_placer_opts& placer_opts, report_aborted_moves(); - print_resources_utilization(); - free_placement_structs(placer_opts); if (placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE || placer_opts.enable_timing_computations) { @@ -2572,6 +2572,9 @@ static void print_resources_utilization() { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); + int max_block_name = 0; + int max_tile_name = 0; + //Record the resource requirement std::map num_type_instances; std::map> num_placed_instances; @@ -2584,15 +2587,17 @@ static void print_resources_utilization() { num_type_instances[logical_block]++; num_placed_instances[logical_block][physical_tile]++; + + max_block_name = std::max(max_block_name, strlen(logical_block->name)); + max_tile_name = std::max(max_tile_name, strlen(physical_tile->name)); } + VTR_LOG("\n"); + VTR_LOG("Placement resource usage:\n"); for (auto logical_block : num_type_instances) { - VTR_LOG("Logical Block: %s\n", logical_block.first->name); - VTR_LOG("\tInstances -> %d\n", logical_block.second); - - VTR_LOG("\tPhysical Tiles used:\n"); for (auto physical_tile : num_placed_instances[logical_block.first]) { - VTR_LOG("\t\t%s: %d\n", physical_tile.first->name, physical_tile.second); + VTR_LOG(" %-*s implemented as %-*s: %d\n", max_block_name, logical_block.first->name, max_tile_name, physical_tile.first->name, physical_tile.second); } } + VTR_LOG("\n"); } From 7b24eaa359da00afe4ef9cf87b0f6a7c9cc76db0 Mon Sep 17 00:00:00 2001 From: kmurray Date: Wed, 11 Dec 2019 13:41:53 -0500 Subject: [PATCH 018/107] vpr: Fix comment typo --- vpr/src/place/move_utils.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index ef00c65cbbe..b2ea57bf1c5 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -217,8 +217,8 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //At the moment, we only support blk_to being the first element of the 'to' macro. // //For instance, this means that we can swap two carry chains so long as one starts - //below the other (not a big limitation since swapping in the oppostie direction would - //allow these blocks to swap) + //below the other (not a big limitation since swapping in the opposite direction + //allows these blocks to swap) if (place_ctx.pl_macros[imacro_to].members[0].blk_index != blk_to) { int imember_to = 0; auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset); From bc4c175ed29daec6f566a8c88d65f6054bb4fe94 Mon Sep 17 00:00:00 2001 From: kmurray Date: Wed, 11 Dec 2019 13:57:41 -0500 Subject: [PATCH 019/107] vpr: Clarify heap pre/post pruning --- vpr/src/route/route_timing.cpp | 37 ++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index b1ac06a1eca..cc738162be4 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -1594,8 +1594,8 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, int inode = cheapest->index; - float old_total_cost = route_ctx.rr_node_route_inf[inode].path_cost; - float old_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost; + float best_total_cost = route_ctx.rr_node_route_inf[inode].path_cost; + float best_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost; float new_total_cost = cheapest->cost; float new_back_cost = cheapest->backward_path_cost; @@ -1608,7 +1608,9 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, * than one with higher cost. Test whether or not I should disallow * * re-expansion based on a higher total cost. */ - if (old_total_cost > new_total_cost && old_back_cost > new_back_cost) { + if (best_total_cost > new_total_cost && best_back_cost > new_back_cost) { + //Explore from this node, since the current/new partial path has the best cost + //found so far VTR_LOGV_DEBUG(f_router_debug, " Better cost to %d\n", inode); VTR_LOGV_DEBUG(f_router_debug, " New total cost: %g\n", new_total_cost); VTR_LOGV_DEBUG(f_router_debug, " New back cost: %g\n", new_back_cost); @@ -1626,9 +1628,11 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, target_node, router_stats); } else { + //Post-heap prune, do not re-explore from the current/new partial path as it + //has worse cost than the best partial path to this node found so far VTR_LOGV_DEBUG(f_router_debug, " Worse cost to %d\n", inode); - VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", old_total_cost); - VTR_LOGV_DEBUG(f_router_debug, " Old back cost: %g\n", old_back_cost); + VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", best_total_cost); + VTR_LOGV_DEBUG(f_router_debug, " Old back cost: %g\n", best_back_cost); VTR_LOGV_DEBUG(f_router_debug, " New total cost: %g\n", new_total_cost); VTR_LOGV_DEBUG(f_router_debug, " New back cost: %g\n", new_back_cost); } @@ -2081,20 +2085,23 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, auto& route_ctx = g_vpr_ctx.routing(); - float old_next_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost; - float old_next_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost; + float best_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost; + float best_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost; - float new_next_total_cost = next->cost; - float new_next_back_cost = next->backward_path_cost; + float new_total_cost = next->cost; + float new_back_cost = next->backward_path_cost; - if (old_next_total_cost > new_next_total_cost && old_next_back_cost > new_next_back_cost) { - //Add node to the heap only if the current cost is less than its historic cost, since - //there is no point in for the router to expand more expensive paths. + VTR_ASSERT_SAFE(next->index == to_node); + + if (new_total_cost < best_total_cost && new_back_cost < best_back_cost) { + //Add node to the heap only if the cost via the current partial path is less than the + //best known cost, since there is no reason for the router to expand more expensive paths. + // + //Pre-heap prune to keep the heap small, by not putting paths which are known to be + //sub-optimal (at this point in time) into the heap. add_to_heap(next); ++router_stats.heap_pushes; - } - - else { + } else { free_heap_data(next); } } From 2780988d58da6be454364e4a06cff8da8caf09e8 Mon Sep 17 00:00:00 2001 From: kmurray Date: Thu, 12 Dec 2019 09:37:19 -0500 Subject: [PATCH 020/107] flow: Add missing benchmark --- .../benchmarks/tests/riscv_core_lut6.blif | 19187 ++++++++++++++++ 1 file changed, 19187 insertions(+) create mode 100644 vtr_flow/benchmarks/tests/riscv_core_lut6.blif diff --git a/vtr_flow/benchmarks/tests/riscv_core_lut6.blif b/vtr_flow/benchmarks/tests/riscv_core_lut6.blif new file mode 100644 index 00000000000..a313bebc127 --- /dev/null +++ b/vtr_flow/benchmarks/tests/riscv_core_lut6.blif @@ -0,0 +1,19187 @@ +# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os) + +.model riscv_core +.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31] +.outputs bus_address[0] bus_address[1] bus_address[2] bus_address[3] bus_address[4] bus_address[5] bus_address[6] bus_address[7] bus_address[8] bus_address[9] bus_address[10] bus_address[11] bus_address[12] bus_address[13] bus_address[14] bus_address[15] bus_address[16] bus_address[17] bus_address[18] bus_address[19] bus_address[20] bus_address[21] bus_address[22] bus_address[23] bus_address[24] bus_address[25] bus_address[26] bus_address[27] bus_address[28] bus_address[29] bus_address[30] bus_address[31] bus_write_data[0] bus_write_data[1] bus_write_data[2] bus_write_data[3] bus_write_data[4] bus_write_data[5] bus_write_data[6] bus_write_data[7] bus_write_data[8] bus_write_data[9] bus_write_data[10] bus_write_data[11] bus_write_data[12] bus_write_data[13] bus_write_data[14] bus_write_data[15] bus_write_data[16] bus_write_data[17] bus_write_data[18] bus_write_data[19] bus_write_data[20] bus_write_data[21] bus_write_data[22] bus_write_data[23] bus_write_data[24] bus_write_data[25] bus_write_data[26] bus_write_data[27] bus_write_data[28] bus_write_data[29] bus_write_data[30] bus_write_data[31] bus_byte_enable[0] bus_byte_enable[1] bus_byte_enable[2] bus_byte_enable[3] bus_read_enable bus_write_enable pc[0] pc[1] pc[2] pc[3] pc[4] pc[5] pc[6] pc[7] pc[8] pc[9] pc[10] pc[11] pc[12] pc[13] pc[14] pc[15] pc[16] pc[17] pc[18] pc[19] pc[20] pc[21] pc[22] pc[23] pc[24] pc[25] pc[26] pc[27] pc[28] pc[29] pc[30] pc[31] regfile_write_enable rd_address[0] rd_address[1] rd_address[2] rd_address[3] rd_address[4] rs1_address[0] rs1_address[1] rs1_address[2] rs1_address[3] rs1_address[4] rs2_address[0] rs2_address[1] rs2_address[2] rs2_address[3] rs2_address[4] rd_data[0] rd_data[1] rd_data[2] rd_data[3] rd_data[4] rd_data[5] rd_data[6] rd_data[7] rd_data[8] rd_data[9] rd_data[10] rd_data[11] rd_data[12] rd_data[13] rd_data[14] rd_data[15] rd_data[16] rd_data[17] rd_data[18] rd_data[19] rd_data[20] rd_data[21] rd_data[22] rd_data[23] rd_data[24] rd_data[25] rd_data[26] rd_data[27] rd_data[28] rd_data[29] rd_data[30] rd_data[31] +.names $false +.names $true +1 +.names $undef +.names $abc$8517$new_n299_ $abc$8517$new_n303_ inst[2] regfile_write_enable +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n302_ $abc$8517$new_n301_ $abc$8517$new_n300_ $abc$8517$new_n299_ +000 1 +.names inst[1] inst[0] inst[2] inst[4] inst[3] inst[6] $abc$8517$new_n300_ +111100 1 +.names inst[1] inst[0] inst[4] inst[2] inst[3] inst[6] $abc$8517$new_n301_ +111000 1 +.names inst[1] inst[0] inst[2] inst[6] inst[5] inst[4] $abc$8517$new_n302_ +111110 1 +.names inst[1] inst[0] inst[3] inst[6] inst[5] inst[4] $abc$8517$new_n303_ +110000 1 +.names $abc$8517$new_n1349_ $abc$8517$new_n1352_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1344_ bus_address[0] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n307_ $abc$8517$new_n374_ $abc$8517$new_n407_ $abc$8517$new_n404_ $abc$8517$new_n409_ $abc$8517$new_n340_ $abc$8517$new_n306_ +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n308_ $abc$8517$new_n322_ $abc$8517$new_n336_ $abc$8517$new_n307_ +110 1 +.names $abc$8517$new_n319_ $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n308_ +000 1 +.names $abc$8517$new_n315_ $abc$8517$new_n310_ $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ rs2_data[19] $abc$8517$new_n309_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n311_ inst[4] inst[6] $abc$8517$new_n302_ inst[5] inst[2] $abc$8517$new_n310_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100001 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +.names inst[1] inst[0] inst[3] $abc$8517$new_n311_ +110 1 +.names $abc$8517$new_n313_ inst[3] inst[6] inst[5] inst[4] inst[2] $abc$8517$new_n312_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100011 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names inst[1] inst[0] $abc$8517$new_n313_ +11 1 +.names inst[19] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n314_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[19] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n315_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n318_ $abc$8517$new_n310_ $abc$8517$new_n317_ inst[31] $abc$8517$new_n312_ rs2_data[18] $abc$8517$new_n316_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[18] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n317_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[18] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n318_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n321_ $abc$8517$new_n310_ $abc$8517$new_n320_ inst[31] $abc$8517$new_n312_ rs2_data[17] $abc$8517$new_n319_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[17] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n320_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[17] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[17] $abc$8517$new_n321_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n333_ $abc$8517$new_n330_ $abc$8517$new_n327_ $abc$8517$new_n323_ $abc$8517$new_n322_ +0000 1 +.names $abc$8517$new_n326_ $abc$8517$new_n310_ $abc$8517$new_n325_ inst[31] $abc$8517$new_n324_ rs2_data[23] $abc$8517$new_n323_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n311_ inst[5] inst[2] inst[6] inst[4] $abc$8517$new_n302_ $abc$8517$new_n324_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100110 1 +101010 1 +101100 1 +101110 1 +110010 1 +110110 1 +111010 1 +111100 1 +111110 1 +.names inst[23] $abc$8517$new_n300_ $abc$8517$new_n325_ +11 1 +.names rs1_data[23] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n326_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n329_ $abc$8517$new_n310_ $abc$8517$new_n328_ inst[31] $abc$8517$new_n324_ rs2_data[22] $abc$8517$new_n327_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[22] $abc$8517$new_n300_ $abc$8517$new_n328_ +11 1 +.names rs1_data[22] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n329_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n332_ $abc$8517$new_n310_ $abc$8517$new_n331_ inst[31] $abc$8517$new_n324_ rs2_data[21] $abc$8517$new_n330_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[21] $abc$8517$new_n300_ $abc$8517$new_n331_ +11 1 +.names rs1_data[21] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[21] $abc$8517$new_n332_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n335_ $abc$8517$new_n310_ $abc$8517$new_n334_ inst[31] $abc$8517$new_n324_ rs2_data[20] $abc$8517$new_n333_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[20] $abc$8517$new_n300_ $abc$8517$new_n334_ +11 1 +.names rs1_data[20] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n335_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n339_ $abc$8517$new_n337_ $abc$8517$new_n336_ +01 1 +10 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[16] inst[31] inst[16] $abc$8517$new_n337_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n300_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n338_ +000 1 +001 1 +010 1 +.names rs1_data[16] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[16] $abc$8517$new_n339_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n369_ $abc$8517$new_n341_ $abc$8517$new_n367_ $abc$8517$new_n365_ $abc$8517$new_n351_ $abc$8517$new_n340_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8517$new_n345_ $abc$8517$new_n350_ $abc$8517$new_n344_ $abc$8517$new_n342_ $abc$8517$new_n341_ +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8517$new_n310_ rs2_data[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n342_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n344_ $abc$8517$new_n310_ rs2_data[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n343_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names rs1_data[5] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[5] $abc$8517$new_n344_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[4] $abc$8517$new_n346_ inst[11] inst[24] $abc$8517$new_n347_ $abc$8517$new_n345_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +.names inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n346_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n303_ $abc$8517$new_n302_ $abc$8517$new_n348_ $abc$8517$new_n349_ $abc$8517$new_n347_ +0000 1 +0001 1 +0010 1 +.names inst[1] inst[0] inst[2] inst[3] $abc$8517$new_n348_ +1100 1 +.names inst[6] inst[5] $abc$8517$new_n349_ +00 1 +.names rs1_data[4] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[4] $abc$8517$new_n350_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n359_ $abc$8517$new_n363_ $abc$8517$new_n356_ $abc$8517$new_n352_ $abc$8517$new_n351_ +000000 1 +000100 1 +000101 1 +000110 1 +110000 1 +110100 1 +110101 1 +110110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n353_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n352_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names rs1_data[0] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n353_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names inst[7] $abc$8517$new_n311_ inst[5] inst[6] inst[4] $abc$8517$new_n354_ +11100 1 +.names inst[20] $abc$8517$new_n303_ $abc$8517$new_n349_ $abc$8517$new_n348_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n355_ +100010 1 +100110 1 +101010 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n310_ rs2_data[1] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n356_ +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names inst[8] inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n357_ +111000 1 +111001 1 +111010 1 +.names inst[21] $abc$8517$new_n303_ $abc$8517$new_n302_ $abc$8517$new_n349_ $abc$8517$new_n348_ $abc$8517$new_n358_ +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n361_ $abc$8517$new_n310_ $abc$8517$new_n360_ inst[23] $abc$8517$new_n347_ rs2_data[3] $abc$8517$new_n359_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[10] inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n360_ +111000 1 +111001 1 +111010 1 +.names rs1_data[3] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n361_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[2] $abc$8517$new_n346_ inst[9] inst[22] $abc$8517$new_n347_ $abc$8517$new_n362_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +.names rs1_data[1] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n363_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[2] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n364_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n366_ $abc$8517$new_n365_ +100 1 +.names $abc$8517$new_n310_ $abc$8517$new_n361_ $abc$8517$new_n360_ rs2_data[3] $abc$8517$new_n347_ inst[23] $abc$8517$new_n366_ +000000 1 +000010 1 +000011 1 +000100 1 +000110 1 +000111 1 +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +.names $abc$8517$new_n343_ $abc$8517$new_n345_ $abc$8517$new_n350_ $abc$8517$new_n361_ $abc$8517$new_n368_ $abc$8517$new_n367_ +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n360_ rs2_data[3] $abc$8517$new_n347_ inst[23] $abc$8517$new_n368_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n370_ $abc$8517$new_n372_ $abc$8517$new_n373_ $abc$8517$new_n369_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n371_ $abc$8517$new_n310_ rs2_data[7] inst[27] $abc$8517$new_n324_ $abc$8517$new_n370_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names rs1_data[7] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n371_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n372_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names rs1_data[6] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n373_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n375_ $abc$8517$new_n381_ $abc$8517$new_n829_ $abc$8517$new_n402_ $abc$8517$new_n395_ $abc$8517$new_n387_ $abc$8517$new_n374_ +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n380_ $abc$8517$new_n376_ $abc$8517$new_n377_ $abc$8517$new_n375_ +000 1 +110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[14] inst[31] inst[14] $abc$8517$new_n376_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n379_ $abc$8517$new_n310_ $abc$8517$new_n378_ inst[31] $abc$8517$new_n312_ rs2_data[15] $abc$8517$new_n377_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[15] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n378_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[15] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n379_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[14] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[14] $abc$8517$new_n380_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n386_ $abc$8517$new_n385_ $abc$8517$new_n382_ $abc$8517$new_n381_ +000 1 +110 1 +.names $abc$8517$new_n384_ $abc$8517$new_n310_ $abc$8517$new_n383_ inst[31] $abc$8517$new_n312_ rs2_data[13] $abc$8517$new_n382_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[13] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n383_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[13] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n384_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[12] inst[31] inst[12] $abc$8517$new_n385_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names rs1_data[12] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n386_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n394_ $abc$8517$new_n388_ $abc$8517$new_n392_ $abc$8517$new_n387_ +000 1 +110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n389_ rs2_data[11] $abc$8517$new_n390_ inst[31] $abc$8517$new_n388_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n313_ inst[3] inst[2] inst[5] inst[6] inst[4] $abc$8517$new_n389_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100101 1 +100110 1 +100111 1 +101001 1 +101010 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names inst[20] inst[3] $abc$8517$new_n302_ $abc$8517$new_n390_ +111 1 +.names inst[7] inst[6] inst[5] $abc$8517$new_n348_ inst[4] $abc$8517$new_n391_ +11110 1 +.names $abc$8517$new_n393_ $abc$8517$new_n310_ inst[30] $abc$8517$new_n324_ rs2_data[10] $abc$8517$new_n392_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names rs1_data[10] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[10] $abc$8517$new_n393_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[11] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[11] $abc$8517$new_n394_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n399_ $abc$8517$new_n398_ $abc$8517$new_n397_ $abc$8517$new_n396_ $abc$8517$new_n395_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ rs2_data[9] inst[29] $abc$8517$new_n324_ $abc$8517$new_n396_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n310_ rs2_data[8] inst[28] $abc$8517$new_n324_ $abc$8517$new_n397_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names rs1_data[9] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[9] $abc$8517$new_n398_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[8] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n399_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n383_ rs2_data[13] $abc$8517$new_n312_ inst[31] $abc$8517$new_n401_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n394_ $abc$8517$new_n403_ $abc$8517$new_n388_ $abc$8517$new_n402_ +010 1 +100 1 +110 1 +111 1 +.names $abc$8517$new_n393_ $abc$8517$new_n310_ rs2_data[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n403_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n405_ $abc$8517$new_n387_ $abc$8517$new_n381_ $abc$8517$new_n375_ $abc$8517$new_n404_ +1111 1 +.names $abc$8517$new_n399_ $abc$8517$new_n397_ $abc$8517$new_n406_ $abc$8517$new_n405_ +000 1 +110 1 +.names $abc$8517$new_n398_ $abc$8517$new_n310_ inst[29] $abc$8517$new_n324_ rs2_data[9] $abc$8517$new_n406_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n380_ $abc$8517$new_n379_ $abc$8517$new_n376_ $abc$8517$new_n408_ $abc$8517$new_n407_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n378_ rs2_data[15] $abc$8517$new_n312_ inst[31] $abc$8517$new_n408_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n371_ $abc$8517$new_n410_ inst[27] $abc$8517$new_n324_ rs2_data[7] $abc$8517$new_n409_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +011111 1 +100000 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n373_ rs2_data[6] $abc$8517$new_n324_ inst[26] $abc$8517$new_n410_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n326_ $abc$8517$new_n428_ $abc$8517$new_n1347_ $abc$8517$new_n426_ $abc$8517$new_n411_ +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1101 1 +1111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n414_ rs2_data[22] $abc$8517$new_n413_ +010 1 +011 1 +100 1 +110 1 +.names $abc$8517$new_n328_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n414_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n418_ $abc$8517$new_n335_ $abc$8517$new_n332_ $abc$8517$new_n416_ $abc$8517$new_n415_ +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n331_ rs2_data[21] $abc$8517$new_n324_ inst[31] $abc$8517$new_n416_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n334_ rs2_data[20] $abc$8517$new_n324_ inst[31] $abc$8517$new_n418_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n339_ $abc$8517$new_n321_ $abc$8517$new_n337_ $abc$8517$new_n420_ $abc$8517$new_n419_ +000100 1 +000110 1 +001000 1 +001100 1 +001101 1 +001110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n320_ rs2_data[17] $abc$8517$new_n312_ inst[31] $abc$8517$new_n420_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n314_ rs2_data[19] $abc$8517$new_n312_ inst[31] $abc$8517$new_n422_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n317_ rs2_data[18] $abc$8517$new_n312_ inst[31] $abc$8517$new_n423_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n427_ rs2_data[23] $abc$8517$new_n426_ +010 1 +011 1 +100 1 +110 1 +.names $abc$8517$new_n325_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n427_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n329_ $abc$8517$new_n414_ rs2_data[22] $abc$8517$new_n428_ +0010 1 +0011 1 +1000 1 +1010 1 +.names $abc$8517$new_n310_ $abc$8517$new_n324_ rs2_data[30] inst[31] inst[30] $abc$8517$new_n431_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names rs1_data[30] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[30] $abc$8517$new_n432_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n434_ $abc$8517$new_n310_ inst[31] rs2_data[31] $abc$8517$new_n433_ +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names rs1_data[31] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n434_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n441_ $abc$8517$new_n440_ $abc$8517$new_n438_ $abc$8517$new_n437_ $abc$8517$new_n436_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n324_ rs2_data[29] inst[31] inst[29] $abc$8517$new_n437_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n439_ rs2_data[28] $abc$8517$new_n324_ inst[31] $abc$8517$new_n438_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[28] $abc$8517$new_n300_ $abc$8517$new_n439_ +11 1 +.names rs1_data[29] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n440_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[28] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[28] $abc$8517$new_n441_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n443_ $abc$8517$new_n442_ +000 1 +110 1 +.names $abc$8517$new_n441_ $abc$8517$new_n310_ $abc$8517$new_n439_ inst[31] $abc$8517$new_n324_ rs2_data[28] $abc$8517$new_n443_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n450_ $abc$8517$new_n449_ $abc$8517$new_n447_ $abc$8517$new_n445_ $abc$8517$new_n444_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n446_ rs2_data[27] $abc$8517$new_n324_ inst[31] $abc$8517$new_n445_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[27] $abc$8517$new_n300_ $abc$8517$new_n446_ +11 1 +.names $abc$8517$new_n310_ $abc$8517$new_n448_ rs2_data[26] $abc$8517$new_n324_ inst[31] $abc$8517$new_n447_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[26] $abc$8517$new_n300_ $abc$8517$new_n448_ +11 1 +.names rs1_data[27] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n449_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[26] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[26] $abc$8517$new_n450_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n453_ $abc$8517$new_n452_ $abc$8517$new_n451_ +00 1 +.names $abc$8517$new_n449_ $abc$8517$new_n310_ $abc$8517$new_n446_ inst[31] $abc$8517$new_n324_ rs2_data[27] $abc$8517$new_n452_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n450_ $abc$8517$new_n310_ $abc$8517$new_n448_ inst[31] $abc$8517$new_n324_ rs2_data[26] $abc$8517$new_n453_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n460_ $abc$8517$new_n459_ $abc$8517$new_n457_ $abc$8517$new_n455_ $abc$8517$new_n454_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n456_ rs2_data[25] $abc$8517$new_n324_ inst[31] $abc$8517$new_n455_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[25] $abc$8517$new_n300_ $abc$8517$new_n456_ +11 1 +.names $abc$8517$new_n310_ $abc$8517$new_n458_ rs2_data[24] $abc$8517$new_n324_ inst[31] $abc$8517$new_n457_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[24] $abc$8517$new_n300_ $abc$8517$new_n458_ +11 1 +.names rs1_data[25] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n459_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[24] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[24] $abc$8517$new_n460_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n462_ $abc$8517$new_n442_ $abc$8517$new_n461_ +11 1 +.names $abc$8517$new_n464_ $abc$8517$new_n463_ $abc$8517$new_n453_ $abc$8517$new_n452_ $abc$8517$new_n462_ +0000 1 +.names $abc$8517$new_n459_ $abc$8517$new_n310_ $abc$8517$new_n456_ inst[31] $abc$8517$new_n324_ rs2_data[25] $abc$8517$new_n463_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n460_ $abc$8517$new_n310_ $abc$8517$new_n458_ inst[31] $abc$8517$new_n324_ rs2_data[24] $abc$8517$new_n464_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n478_ $abc$8517$new_n489_ $abc$8517$new_n467_ $abc$8517$new_n466_ +100 1 +.names $abc$8517$new_n476_ $abc$8517$new_n470_ $abc$8517$new_n468_ $abc$8517$new_n404_ $abc$8517$new_n467_ +1111 1 +.names $abc$8517$new_n469_ $abc$8517$new_n442_ $abc$8517$new_n322_ $abc$8517$new_n308_ $abc$8517$new_n462_ $abc$8517$new_n336_ $abc$8517$new_n468_ +111110 1 +.names $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n433_ $abc$8517$new_n469_ +000 1 +110 1 +.names $abc$8517$new_n474_ $abc$8517$new_n472_ $abc$8517$new_n359_ $abc$8517$new_n352_ $abc$8517$new_n471_ $abc$8517$new_n470_ +11000 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n471_ +01 1 +10 1 +.names $abc$8517$new_n363_ $abc$8517$new_n356_ $abc$8517$new_n473_ $abc$8517$new_n472_ +000 1 +110 1 +.names $abc$8517$new_n353_ $abc$8517$new_n310_ rs2_data[0] $abc$8517$new_n354_ $abc$8517$new_n355_ $abc$8517$new_n473_ +10001 1 +10010 1 +10011 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n373_ $abc$8517$new_n372_ $abc$8517$new_n475_ $abc$8517$new_n474_ +000 1 +110 1 +.names $abc$8517$new_n371_ $abc$8517$new_n310_ inst[27] $abc$8517$new_n324_ rs2_data[7] $abc$8517$new_n475_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n350_ $abc$8517$new_n345_ $abc$8517$new_n477_ $abc$8517$new_n476_ +000 1 +110 1 +.names $abc$8517$new_n344_ $abc$8517$new_n310_ inst[25] $abc$8517$new_n324_ rs2_data[5] $abc$8517$new_n477_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n486_ $abc$8517$new_n479_ $abc$8517$new_n478_ +00 1 +.names $abc$8517$new_n481_ $abc$8517$new_n484_ $abc$8517$new_n482_ $abc$8517$new_n485_ $abc$8517$new_n310_ $abc$8517$new_n479_ +00001 1 +00011 1 +00110 1 +00111 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +11110 1 +11111 1 +.names $abc$8517$new_n311_ inst[2] inst[4] inst[5] inst[6] $abc$8517$new_n302_ $abc$8517$new_n481_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100010 1 +101000 1 +101010 1 +101110 1 +110000 1 +110010 1 +110100 1 +110110 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n301_ $abc$8517$new_n483_ $abc$8517$new_n482_ +10 1 +.names inst[30] inst[12] inst[13] $abc$8517$new_n483_ +100 1 +101 1 +111 1 +.names inst[5] $abc$8517$new_n348_ inst[14] inst[4] inst[13] $abc$8517$new_n484_ +11100 1 +.names inst[12] inst[14] inst[13] inst[30] $abc$8517$new_n485_ +0110 1 +0111 1 +1001 1 +1010 1 +1011 1 +1100 1 +.names $abc$8517$new_n487_ $abc$8517$new_n481_ $abc$8517$new_n488_ $abc$8517$new_n301_ $abc$8517$new_n483_ $abc$8517$new_n486_ +00000 1 +00001 1 +00010 1 +00100 1 +00101 1 +01000 1 +01001 1 +01010 1 +01011 1 +.names inst[6] inst[5] $abc$8517$new_n348_ inst[4] inst[13] inst[14] $abc$8517$new_n487_ +111000 1 +111001 1 +111010 1 +.names inst[13] inst[12] inst[14] $abc$8517$new_n488_ +010 1 +100 1 +101 1 +111 1 +.names $abc$8517$new_n487_ inst[14] inst[12] inst[13] $abc$8517$new_n482_ $abc$8517$new_n481_ $abc$8517$new_n489_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n469_ $abc$8517$new_n442_ $abc$8517$new_n436_ $abc$8517$new_n444_ $abc$8517$new_n454_ $abc$8517$new_n451_ $abc$8517$new_n492_ +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n434_ $abc$8517$new_n310_ $abc$8517$new_n494_ rs2_data[31] $abc$8517$new_n493_ +1000 1 +1001 1 +1101 1 +1111 1 +.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n338_ $abc$8517$new_n494_ +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n496_ $abc$8517$new_n470_ $abc$8517$new_n468_ $abc$8517$new_n404_ $abc$8517$new_n476_ $abc$8517$new_n495_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 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$abc$8517$new_n535_ $abc$8517$new_n967_ +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1100 1 +.names $abc$8517$new_n441_ $abc$8517$new_n576_ $abc$8517$new_n438_ $abc$8517$new_n547_ $abc$8517$new_n579_ $abc$8517$new_n968_ +00000 1 +00010 1 +00100 1 +00101 1 +10000 1 +10001 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n692_ $abc$8517$new_n719_ $abc$8517$new_n630_ $abc$8517$new_n629_ $abc$8517$new_n718_ $abc$8517$new_n969_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00110 1 +01000 1 +01001 1 +.names $abc$8517$new_n546_ $abc$8517$new_n973_ $abc$8517$new_n441_ $abc$8517$new_n438_ $abc$8517$new_n962_ $abc$8517$new_n971_ bus_address[29] +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101010 1 +101100 1 +101110 1 +110000 1 +110010 1 +110100 1 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1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n983_ $abc$8517$new_n546_ $abc$8517$new_n981_ bus_address[30] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n982_ $abc$8517$new_n441_ $abc$8517$new_n438_ $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n962_ $abc$8517$new_n981_ +000110 1 +000111 1 +001011 1 +001101 1 +001110 1 +001111 1 +010011 1 +010101 1 +010110 1 +010111 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101100 1 +110000 1 +110001 1 +110010 1 +110100 1 +111000 1 +111001 1 +.names $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n982_ +00 1 +11 1 +.names $abc$8517$new_n548_ $abc$8517$new_n984_ $abc$8517$new_n982_ $abc$8517$new_n987_ $abc$8517$new_n543_ $abc$8517$new_n985_ $abc$8517$new_n983_ +000100 1 +000101 1 +000110 1 +001100 1 +001101 1 +001110 1 +010100 1 +010101 1 +010110 1 +011100 1 +011101 1 +011110 1 +101100 1 +101101 1 +101110 1 +110100 1 +110101 1 +110110 1 +.names $abc$8517$new_n437_ $abc$8517$new_n440_ $abc$8517$new_n974_ $abc$8517$new_n442_ $abc$8517$new_n963_ $abc$8517$new_n984_ +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n898_ $abc$8517$new_n943_ $abc$8517$new_n986_ $abc$8517$new_n985_ +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n356_ $abc$8517$new_n539_ $abc$8517$new_n538_ $abc$8517$new_n535_ $abc$8517$new_n537_ $abc$8517$new_n986_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n988_ $abc$8517$new_n789_ $abc$8517$new_n819_ $abc$8517$new_n345_ $abc$8517$new_n795_ $abc$8517$new_n987_ +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8517$new_n811_ $abc$8517$new_n432_ $abc$8517$new_n576_ $abc$8517$new_n431_ $abc$8517$new_n547_ $abc$8517$new_n579_ $abc$8517$new_n988_ +000000 1 +000010 1 +000100 1 +000101 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n546_ $abc$8517$new_n433_ $abc$8517$new_n990_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n991_ bus_address[31] +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n982_ $abc$8517$new_n441_ $abc$8517$new_n438_ $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n962_ $abc$8517$new_n990_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +001000 1 +001001 1 +001010 1 +001100 1 +010000 1 +010001 1 +010010 1 +010100 1 +011000 1 +011001 1 +.names $abc$8517$new_n992_ $abc$8517$new_n433_ $abc$8517$new_n431_ $abc$8517$new_n432_ $abc$8517$new_n984_ $abc$8517$new_n548_ $abc$8517$new_n991_ +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +110000 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n996_ $abc$8517$new_n997_ $abc$8517$new_n995_ $abc$8517$new_n993_ $abc$8517$new_n803_ $abc$8517$new_n819_ $abc$8517$new_n992_ +100000 1 +100010 1 +100011 1 +.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n994_ $abc$8517$new_n910_ $abc$8517$new_n957_ $abc$8517$new_n362_ $abc$8517$new_n993_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110011 1 +110100 1 +110101 1 +110111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n519_ $abc$8517$new_n977_ $abc$8517$new_n434_ $abc$8517$new_n432_ $abc$8517$new_n994_ +100100 1 +100101 1 +100110 1 +100111 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n434_ $abc$8517$new_n576_ rs2_data[31] $abc$8517$new_n494_ $abc$8517$new_n547_ $abc$8517$new_n995_ +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010001 1 +010101 1 +011000 1 +011001 1 +011100 1 +011101 1 +100001 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110101 1 +110111 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n434_ $abc$8517$new_n579_ $abc$8517$new_n310_ $abc$8517$new_n568_ $abc$8517$new_n494_ rs2_data[31] $abc$8517$new_n996_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010010 1 +010011 1 +011000 1 +011010 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n690_ $abc$8517$new_n608_ $abc$8517$new_n549_ $abc$8517$new_n997_ +1111 1 +.names singlecycle_datapath.program_counter.value[0] reset $abc$8517$new_n1013_ $abc$8517$new_n1011_ $abc$8517$new_n999_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] +00000 1 +00001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n302_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1009_ $abc$8517$new_n999_ +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names $abc$8517$new_n1001_ $abc$8517$new_n983_ bus_address[29] bus_address[28] $abc$8517$new_n981_ $abc$8517$new_n546_ $abc$8517$new_n1000_ +110000 1 +110001 1 +110010 1 +.names $abc$8517$new_n1396_ $abc$8517$new_n1002_ $abc$8517$new_n950_ bus_address[26] bus_address[25] $abc$8517$new_n1001_ +11000 1 +.names $abc$8517$new_n1003_ $abc$8517$new_n1007_ bus_address[21] bus_address[24] bus_address[23] bus_address[22] $abc$8517$new_n1002_ +110000 1 +.names $abc$8517$new_n1004_ bus_address[11] bus_address[14] bus_address[16] bus_address[20] $abc$8517$new_n1003_ +10000 1 +.names $abc$8517$new_n1005_ $abc$8517$new_n1006_ bus_address[9] bus_address[10] $abc$8517$new_n1004_ +1100 1 +.names $abc$8517$new_n1352_ $abc$8517$new_n1349_ bus_address[1] $abc$8517$new_n1344_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1005_ +100000 1 +100001 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +.names bus_address[2] bus_address[8] bus_address[7] bus_address[5] bus_address[4] bus_address[3] $abc$8517$new_n1006_ +000000 1 +.names $abc$8517$new_n1008_ bus_address[12] bus_address[19] $abc$8517$new_n1007_ +100 1 +.names bus_address[6] bus_address[13] bus_address[15] bus_address[18] bus_address[17] $abc$8517$new_n1008_ +00000 1 +.names inst[6] inst[5] $abc$8517$new_n348_ inst[4] $abc$8517$new_n1009_ +1110 1 +.names inst[12] inst[13] inst[14] $abc$8517$new_n1010_ +100 1 +101 1 +111 1 +.names $abc$8517$new_n1012_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1009_ $abc$8517$new_n1011_ +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names inst[3] $abc$8517$new_n302_ $abc$8517$new_n1012_ +11 1 +.names $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n1013_ +00 1 +.names reset $abc$8517$new_n1015_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n999_ $abc$8517$new_n1017_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[1] $abc$8517$new_n1015_ +11 1 +.names $abc$8517$new_n302_ inst[3] $abc$8517$new_n1016_ +10 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.program_counter.value[0] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n1013_ $abc$8517$new_n1017_ +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names reset $abc$8517$new_n1019_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n999_ $abc$8517$new_n1020_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] +000010 1 +000100 1 +000101 1 +000110 1 +000111 1 +001010 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[2] $abc$8517$new_n1019_ +11 1 +.names singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1020_ +001 1 +010 1 +100 1 +111 1 +.names inst[9] $abc$8517$new_n346_ inst[22] $abc$8517$new_n347_ $abc$8517$new_n1021_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8517$new_n358_ $abc$8517$new_n357_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n354_ $abc$8517$new_n355_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n1022_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010100 1 +010110 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +.names reset $abc$8517$new_n1024_ $abc$8517$new_n1028_ $abc$8517$new_n999_ $abc$8517$new_n1025_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[3] $abc$8517$new_n1024_ +11 1 +.names singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1025_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1022_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1021_ $abc$8517$new_n1026_ +001 1 +100 1 +101 1 +111 1 +.names $abc$8517$new_n360_ $abc$8517$new_n347_ inst[23] $abc$8517$new_n1027_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1028_ +01 1 +10 1 +.names reset $abc$8517$new_n1030_ $abc$8517$new_n1033_ $abc$8517$new_n999_ $abc$8517$new_n1031_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[4] $abc$8517$new_n1030_ +11 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1031_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[11] $abc$8517$new_n346_ inst[24] $abc$8517$new_n347_ $abc$8517$new_n1032_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1033_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1035_ $abc$8517$new_n1042_ $abc$8517$new_n999_ $abc$8517$new_n1036_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[5] $abc$8517$new_n1035_ +11 1 +.names $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1036_ +00 1 +11 1 +.names $abc$8517$new_n1039_ $abc$8517$new_n1038_ $abc$8517$new_n1037_ +00 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ $abc$8517$new_n1038_ +10 1 +.names $abc$8517$new_n1040_ singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1027_ $abc$8517$new_n1039_ +100000 1 +101000 1 +101010 1 +101100 1 +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n347_ inst[24] inst[11] $abc$8517$new_n1040_ +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +.names singlecycle_datapath.program_counter.value[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n1041_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1042_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1044_ $abc$8517$new_n1048_ $abc$8517$new_n999_ $abc$8517$new_n1045_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[6] $abc$8517$new_n1044_ +11 1 +.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1045_ +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names inst[25] singlecycle_datapath.program_counter.value[5] $abc$8517$new_n324_ $abc$8517$new_n1046_ +110 1 +.names singlecycle_datapath.program_counter.value[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n1047_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1048_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1050_ $abc$8517$new_n1054_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[7] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1051_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1050_ +100001 1 +100011 1 +100101 1 +100111 1 +101001 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110110 1 +110111 1 +111001 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1051_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n1041_ $abc$8517$new_n1038_ $abc$8517$new_n1039_ $abc$8517$new_n1052_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1054_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1056_ $abc$8517$new_n1060_ $abc$8517$new_n999_ $abc$8517$new_n1057_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[8] $abc$8517$new_n1056_ +11 1 +.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1057_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1058_ +000 1 +001 1 +011 1 +101 1 +.names inst[28] $abc$8517$new_n324_ $abc$8517$new_n1059_ +10 1 +.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1060_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1061_ +111111 1 +.names reset $abc$8517$new_n1063_ $abc$8517$new_n1067_ $abc$8517$new_n999_ $abc$8517$new_n1064_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[9] $abc$8517$new_n1063_ +11 1 +.names $abc$8517$new_n1066_ $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1064_ +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names inst[29] singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ $abc$8517$new_n1065_ +110 1 +.names singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ inst[29] $abc$8517$new_n1066_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1067_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1069_ $abc$8517$new_n1073_ $abc$8517$new_n999_ $abc$8517$new_n1070_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[10] $abc$8517$new_n1069_ +11 1 +.names $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1070_ +000 1 +101 1 +110 1 +111 1 +.names $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1052_ $abc$8517$new_n1071_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +001000 1 +001001 1 +001011 1 +001101 1 +010000 1 +010001 1 +010011 1 +010101 1 +011000 1 +011001 1 +.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1072_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1073_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1075_ $abc$8517$new_n1079_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[11] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1076_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1075_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1078_ $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1076_ +000100 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100101 1 +100110 1 +100111 1 +110100 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n390_ $abc$8517$new_n391_ $abc$8517$new_n389_ inst[31] $abc$8517$new_n1077_ +0000 1 +0010 1 +0011 1 +.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1078_ +110 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1079_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1081_ $abc$8517$new_n1086_ $abc$8517$new_n999_ $abc$8517$new_n1082_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[12] $abc$8517$new_n1081_ +11 1 +.names singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1084_ $abc$8517$new_n1083_ $abc$8517$new_n1082_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1072_ $abc$8517$new_n1071_ $abc$8517$new_n1066_ $abc$8517$new_n1078_ $abc$8517$new_n1083_ +000001 1 +000011 1 +000101 1 +000111 1 +001000 1 +001001 1 +001011 1 +001101 1 +001111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[12] $abc$8517$new_n1084_ +000 1 +010 1 +011 1 +.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n1085_ +10 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1086_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1091_ $abc$8517$new_n1092_ $abc$8517$new_n999_ $abc$8517$new_n1088_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1088_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1084_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1083_ $abc$8517$new_n1089_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n383_ $abc$8517$new_n1085_ $abc$8517$new_n1090_ +00 1 +.names $abc$8517$new_n1016_ bus_address[13] $abc$8517$new_n1091_ +11 1 +.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1092_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1093_ +111111 1 +.names reset $abc$8517$new_n1095_ $abc$8517$new_n1098_ $abc$8517$new_n999_ $abc$8517$new_n1096_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[14] $abc$8517$new_n1095_ +11 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1096_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[14] $abc$8517$new_n1097_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1098_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1106_ $abc$8517$new_n1107_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1100_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1100_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ $abc$8517$new_n1101_ +00 1 +.names $abc$8517$new_n1103_ singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1084_ $abc$8517$new_n1090_ $abc$8517$new_n1083_ $abc$8517$new_n1102_ +100001 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +110000 1 +110001 1 +110101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1103_ +00 1 +11 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1104_ +10 1 +.names $abc$8517$new_n378_ $abc$8517$new_n1085_ $abc$8517$new_n1105_ +00 1 +.names $abc$8517$new_n1016_ bus_address[15] $abc$8517$new_n1106_ +11 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1107_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1109_ $abc$8517$new_n1112_ $abc$8517$new_n999_ $abc$8517$new_n1110_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[16] $abc$8517$new_n1109_ +11 1 +.names singlecycle_datapath.program_counter.value[16] $abc$8517$new_n1111_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1110_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[16] $abc$8517$new_n1111_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1112_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1114_ $abc$8517$new_n1118_ $abc$8517$new_n999_ bus_address[17] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1115_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1114_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1115_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1111_ $abc$8517$new_n1116_ +000000 1 +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010010 1 +010011 1 +010101 1 +010111 1 +011011 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101011 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111011 1 +.names $abc$8517$new_n320_ $abc$8517$new_n1085_ $abc$8517$new_n1117_ +00 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1118_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1123_ $abc$8517$new_n1124_ $abc$8517$new_n999_ $abc$8517$new_n1120_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1120_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1121_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n317_ $abc$8517$new_n1085_ $abc$8517$new_n1122_ +00 1 +.names $abc$8517$new_n1016_ bus_address[18] $abc$8517$new_n1123_ +11 1 +.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1124_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1125_ +111111 1 +.names reset $abc$8517$new_n1129_ $abc$8517$new_n1130_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1127_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1127_ +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$8517$new_n314_ $abc$8517$new_n1085_ $abc$8517$new_n1128_ +00 1 +.names $abc$8517$new_n1016_ bus_address[19] $abc$8517$new_n1129_ +11 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1130_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1132_ $abc$8517$new_n1138_ $abc$8517$new_n999_ $abc$8517$new_n1133_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[20] $abc$8517$new_n1132_ +11 1 +.names singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1133_ +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n1135_ $abc$8517$new_n1117_ singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1116_ $abc$8517$new_n1134_ +000001 1 +000010 1 +000011 1 +000111 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +010111 1 +011001 1 +011010 1 +011011 1 +011111 1 +.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ $abc$8517$new_n1135_ +10 1 +.names $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1136_ +10 1 +.names $abc$8517$new_n334_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1137_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1138_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1140_ $abc$8517$new_n1143_ $abc$8517$new_n999_ $abc$8517$new_n1141_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[21] $abc$8517$new_n1140_ +11 1 +.names singlecycle_datapath.program_counter.value[21] $abc$8517$new_n1142_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1141_ +000000 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011101 1 +011110 1 +011111 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101101 1 +101110 1 +101111 1 +110000 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +.names $abc$8517$new_n331_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1142_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1143_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1145_ $abc$8517$new_n1146_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +.names reset bus_address[22] $abc$8517$new_n1016_ $abc$8517$new_n1145_ +000 1 +001 1 +010 1 +.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n414_ $abc$8517$new_n1147_ $abc$8517$new_n1146_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1137_ $abc$8517$new_n1142_ $abc$8517$new_n1147_ +000000 1 +010000 1 +010010 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101010 1 +101100 1 +101110 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +111000 1 +111001 1 +111010 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1148_ +11111 1 +.names reset $abc$8517$new_n1152_ $abc$8517$new_n1153_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1150_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1150_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n414_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1147_ $abc$8517$new_n1151_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n1016_ bus_address[23] $abc$8517$new_n1152_ +11 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1153_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1154_ +11 1 +.names reset $abc$8517$new_n1158_ $abc$8517$new_n1159_ $abc$8517$new_n999_ $abc$8517$new_n1156_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1156_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n458_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1157_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[24] $abc$8517$new_n1158_ +11 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1159_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1160_ +11 1 +.names reset $abc$8517$new_n1168_ $abc$8517$new_n1169_ $abc$8517$new_n999_ $abc$8517$new_n1162_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1162_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ $abc$8517$new_n1163_ +00 1 +.names $abc$8517$new_n1165_ singlecycle_datapath.program_counter.value[22] singlecycle_datapath.program_counter.value[23] $abc$8517$new_n414_ $abc$8517$new_n427_ $abc$8517$new_n1147_ $abc$8517$new_n1164_ +100001 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +110000 1 +110001 1 +110101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1165_ +00 1 +11 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1166_ +10 1 +.names $abc$8517$new_n456_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1167_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[25] $abc$8517$new_n1168_ +11 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1169_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1173_ $abc$8517$new_n1174_ $abc$8517$new_n999_ $abc$8517$new_n1171_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[26] $abc$8517$new_n1172_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1171_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n448_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1172_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[26] $abc$8517$new_n1173_ +11 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1174_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1176_ $abc$8517$new_n1180_ $abc$8517$new_n999_ $abc$8517$new_n1177_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[27] $abc$8517$new_n1176_ +11 1 +.names singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1177_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1172_ $abc$8517$new_n1178_ +000000 1 +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010010 1 +010011 1 +010101 1 +010111 1 +011011 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101011 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111011 1 +.names $abc$8517$new_n446_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1179_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1180_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1182_ $abc$8517$new_n1185_ $abc$8517$new_n999_ bus_address[28] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1183_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1182_ +100001 1 +100011 1 +100101 1 +100111 1 +101001 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110110 1 +110111 1 +111001 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1183_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n439_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1184_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1185_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1190_ $abc$8517$new_n1191_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1187_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1187_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1179_ singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ $abc$8517$new_n1178_ $abc$8517$new_n1188_ +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[29] $abc$8517$new_n1189_ +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n1016_ bus_address[29] $abc$8517$new_n1190_ +11 1 +.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1191_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1192_ +111111 1 +.names reset $abc$8517$new_n1194_ $abc$8517$new_n1197_ $abc$8517$new_n999_ $abc$8517$new_n1195_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[30] $abc$8517$new_n1194_ +11 1 +.names singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1195_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[30] $abc$8517$new_n1196_ +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1197_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ $abc$8517$new_n1199_ $abc$8517$new_n1202_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001010 1 +001011 1 +001101 1 +001110 1 +001111 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1200_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1199_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names $abc$8517$new_n1201_ $abc$8517$new_n1189_ singlecycle_datapath.program_counter.value[29] singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ $abc$8517$new_n1188_ $abc$8517$new_n1200_ +000001 1 +000010 1 +000011 1 +000111 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +010111 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101100 1 +101101 1 +101110 1 +101111 1 +110100 1 +110101 1 +111000 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[31] $abc$8517$new_n494_ $abc$8517$new_n1201_ +00 1 +11 1 +.names $abc$8517$new_n1016_ bus_address[31] $abc$8517$new_n1202_ +11 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1203_ +111 1 +.names $abc$8517$new_n1005_ inst[13] inst[12] bus_byte_enable[0] +100 1 +101 1 +110 1 +.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +.names inst[13] inst[12] bus_address[0] bus_address[1] bus_byte_enable[2] +0001 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[3] +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1209_ bus_address[0] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n302_ rd_data[0] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[24] bus_read_data[8] bus_read_data[16] bus_read_data[0] $abc$8517$new_n1209_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n301_ $abc$8517$new_n300_ inst[5] $abc$8517$new_n1210_ +000 1 +001 1 +011 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1212_ bus_address[1] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n302_ rd_data[1] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[25] bus_read_data[9] bus_read_data[17] bus_read_data[1] $abc$8517$new_n1212_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1214_ bus_address[2] $abc$8517$new_n1210_ $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[2] rd_data[2] +000010 1 +000110 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +010010 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110010 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +.names bus_address[1] bus_address[0] bus_read_data[26] bus_read_data[10] bus_read_data[18] bus_read_data[2] $abc$8517$new_n1214_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1216_ bus_address[3] $abc$8517$new_n1210_ $abc$8517$new_n1028_ $abc$8517$new_n302_ rd_data[3] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[27] bus_read_data[11] bus_read_data[19] bus_read_data[3] $abc$8517$new_n1216_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1218_ bus_address[4] $abc$8517$new_n1210_ $abc$8517$new_n1033_ $abc$8517$new_n302_ rd_data[4] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[28] bus_read_data[12] bus_read_data[20] bus_read_data[4] $abc$8517$new_n1218_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1220_ bus_address[5] $abc$8517$new_n1210_ $abc$8517$new_n1042_ $abc$8517$new_n302_ rd_data[5] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[29] bus_read_data[13] bus_read_data[21] bus_read_data[5] $abc$8517$new_n1220_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1222_ bus_address[6] $abc$8517$new_n1210_ $abc$8517$new_n1048_ $abc$8517$new_n302_ rd_data[6] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[30] bus_read_data[14] bus_read_data[22] bus_read_data[6] $abc$8517$new_n1222_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1224_ bus_address[7] $abc$8517$new_n1210_ $abc$8517$new_n1054_ $abc$8517$new_n302_ rd_data[7] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[31] bus_read_data[15] bus_read_data[23] bus_read_data[7] $abc$8517$new_n1224_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n1226_ $abc$8517$new_n1210_ bus_address[8] $abc$8517$new_n1060_ $abc$8517$new_n302_ rd_data[8] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1228_ $abc$8517$new_n1227_ $abc$8517$new_n1226_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names inst[13] inst[12] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1227_ +0000 1 +1100 1 +.names bus_address[1] bus_address[0] bus_read_data[16] bus_read_data[24] bus_read_data[8] $abc$8517$new_n1228_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1230_ $abc$8517$new_n1210_ bus_address[9] $abc$8517$new_n1067_ $abc$8517$new_n302_ rd_data[9] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1231_ $abc$8517$new_n1227_ $abc$8517$new_n1230_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[17] bus_read_data[25] bus_read_data[9] $abc$8517$new_n1231_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1233_ $abc$8517$new_n1210_ bus_address[10] $abc$8517$new_n1073_ $abc$8517$new_n302_ rd_data[10] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1234_ $abc$8517$new_n1227_ $abc$8517$new_n1233_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[18] bus_read_data[26] bus_read_data[10] $abc$8517$new_n1234_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1236_ $abc$8517$new_n1210_ bus_address[11] $abc$8517$new_n1079_ $abc$8517$new_n302_ rd_data[11] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1237_ $abc$8517$new_n1227_ $abc$8517$new_n1236_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[19] bus_read_data[27] bus_read_data[11] $abc$8517$new_n1237_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1239_ $abc$8517$new_n302_ $abc$8517$new_n1086_ rd_data[12] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n1241_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1240_ $abc$8517$new_n1239_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[20] bus_read_data[28] bus_read_data[12] $abc$8517$new_n1240_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1210_ bus_address[12] $abc$8517$new_n300_ $abc$8517$new_n1084_ $abc$8517$new_n1241_ +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8517$new_n1243_ bus_address[13] $abc$8517$new_n1210_ rd_data[13] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1245_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1244_ $abc$8517$new_n1243_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[21] bus_read_data[29] bus_read_data[13] $abc$8517$new_n1244_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1092_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1090_ $abc$8517$new_n1245_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1247_ bus_address[14] $abc$8517$new_n1210_ rd_data[14] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1249_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1248_ $abc$8517$new_n1247_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[22] bus_read_data[30] bus_read_data[14] $abc$8517$new_n1248_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1098_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1097_ $abc$8517$new_n1249_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1251_ bus_address[15] $abc$8517$new_n1210_ rd_data[15] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1253_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1252_ $abc$8517$new_n1251_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[23] bus_read_data[31] bus_read_data[15] $abc$8517$new_n1252_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1107_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1105_ $abc$8517$new_n1253_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1255_ bus_address[16] $abc$8517$new_n1210_ rd_data[16] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1256_ $abc$8517$new_n302_ $abc$8517$new_n1112_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1111_ $abc$8517$new_n1255_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[24] bus_read_data[16] $abc$8517$new_n1256_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names inst[12] inst[13] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1252_ $abc$8517$new_n1257_ +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names inst[13] inst[12] bus_address[1] $abc$8517$new_n1258_ +100 1 +.names $abc$8517$new_n1260_ $abc$8517$new_n302_ $abc$8517$new_n1118_ rd_data[17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n1261_ bus_address[17] $abc$8517$new_n1210_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1117_ $abc$8517$new_n1260_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[25] bus_read_data[17] $abc$8517$new_n1261_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1263_ bus_address[18] $abc$8517$new_n1210_ rd_data[18] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1264_ $abc$8517$new_n302_ $abc$8517$new_n1124_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1122_ $abc$8517$new_n1263_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[26] bus_read_data[18] $abc$8517$new_n1264_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1266_ bus_address[19] $abc$8517$new_n1210_ rd_data[19] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1267_ $abc$8517$new_n302_ $abc$8517$new_n1130_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1128_ $abc$8517$new_n1266_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[27] bus_read_data[19] $abc$8517$new_n1267_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1269_ bus_address[20] $abc$8517$new_n1210_ rd_data[20] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1270_ $abc$8517$new_n302_ $abc$8517$new_n1138_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1137_ $abc$8517$new_n1269_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[28] bus_read_data[20] $abc$8517$new_n1270_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1272_ bus_address[21] $abc$8517$new_n1210_ rd_data[21] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1273_ $abc$8517$new_n302_ $abc$8517$new_n1143_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1142_ $abc$8517$new_n1272_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[29] bus_read_data[21] $abc$8517$new_n1273_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1276_ $abc$8517$new_n1275_ bus_address[22] $abc$8517$new_n1210_ rd_data[22] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[30] bus_read_data[22] $abc$8517$new_n1275_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n414_ $abc$8517$new_n1276_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names $abc$8517$new_n1278_ bus_address[23] $abc$8517$new_n1210_ rd_data[23] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1279_ $abc$8517$new_n302_ $abc$8517$new_n1153_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n427_ $abc$8517$new_n1278_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[31] bus_read_data[23] $abc$8517$new_n1279_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1281_ bus_address[24] $abc$8517$new_n1210_ rd_data[24] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1283_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[24] $abc$8517$new_n1281_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1282_ +10 1 +.names $abc$8517$new_n1159_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1157_ $abc$8517$new_n1283_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1285_ bus_address[25] $abc$8517$new_n1210_ rd_data[25] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1286_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[25] $abc$8517$new_n1285_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1169_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1167_ $abc$8517$new_n1286_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1288_ bus_address[26] $abc$8517$new_n1210_ rd_data[26] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1289_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[26] $abc$8517$new_n1288_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1174_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1172_ $abc$8517$new_n1289_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1291_ bus_address[27] $abc$8517$new_n1210_ rd_data[27] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1292_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[27] $abc$8517$new_n1291_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1180_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1179_ $abc$8517$new_n1292_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1294_ bus_address[28] $abc$8517$new_n1210_ rd_data[28] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1295_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[28] $abc$8517$new_n1294_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1185_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1184_ $abc$8517$new_n1295_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1297_ bus_address[29] $abc$8517$new_n1210_ rd_data[29] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1298_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[29] $abc$8517$new_n1297_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1191_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1189_ $abc$8517$new_n1298_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1300_ bus_address[30] $abc$8517$new_n1210_ rd_data[30] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1301_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[30] $abc$8517$new_n1300_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1197_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1196_ $abc$8517$new_n1301_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1304_ $abc$8517$new_n1303_ bus_address[31] $abc$8517$new_n1210_ rd_data[31] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1257_ bus_read_data[31] $abc$8517$new_n1282_ $abc$8517$new_n1303_ +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n494_ $abc$8517$new_n1304_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1009_ $abc$8517$new_n348_ $abc$8517$new_n1307_ $abc$8517$new_n1306_ inst[3] bus_write_enable +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +.names inst[2] $abc$8517$new_n313_ $abc$8517$new_n1306_ +11 1 +.names inst[6] inst[5] inst[4] $abc$8517$new_n1307_ +000 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1306_ $abc$8517$new_n346_ $abc$8517$new_n1310_ bus_read_enable +1010 1 +1011 1 +1100 1 +1110 1 +.names inst[3] $abc$8517$new_n1307_ $abc$8517$new_n1310_ +11 1 +.names rs2_data[0] $abc$8517$new_n1005_ bus_write_data[0] +11 1 +.names rs2_data[1] $abc$8517$new_n1005_ bus_write_data[1] +11 1 +.names rs2_data[2] $abc$8517$new_n1005_ bus_write_data[2] +11 1 +.names rs2_data[3] $abc$8517$new_n1005_ bus_write_data[3] +11 1 +.names rs2_data[4] $abc$8517$new_n1005_ bus_write_data[4] +11 1 +.names rs2_data[5] $abc$8517$new_n1005_ bus_write_data[5] +11 1 +.names rs2_data[6] $abc$8517$new_n1005_ bus_write_data[6] +11 1 +.names rs2_data[7] $abc$8517$new_n1005_ bus_write_data[7] +11 1 +.names bus_address[0] bus_address[1] rs2_data[0] rs2_data[8] bus_write_data[8] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[1] rs2_data[9] bus_write_data[9] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[2] rs2_data[10] bus_write_data[10] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[3] rs2_data[11] bus_write_data[11] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[4] rs2_data[12] bus_write_data[12] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[5] rs2_data[13] bus_write_data[13] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[6] rs2_data[14] bus_write_data[14] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[7] rs2_data[15] bus_write_data[15] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[1] bus_address[0] rs2_data[8] rs2_data[0] rs2_data[16] bus_write_data[16] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[9] rs2_data[1] rs2_data[17] bus_write_data[17] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[10] rs2_data[2] rs2_data[18] bus_write_data[18] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[11] rs2_data[3] rs2_data[19] bus_write_data[19] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[12] rs2_data[4] rs2_data[20] bus_write_data[20] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[13] rs2_data[5] rs2_data[21] bus_write_data[21] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[14] rs2_data[6] rs2_data[22] bus_write_data[22] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[15] rs2_data[7] rs2_data[23] bus_write_data[23] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[0] rs2_data[16] rs2_data[8] rs2_data[24] bus_write_data[24] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[1] rs2_data[17] rs2_data[9] rs2_data[25] bus_write_data[25] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[2] rs2_data[18] rs2_data[10] rs2_data[26] bus_write_data[26] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[3] rs2_data[19] rs2_data[11] rs2_data[27] bus_write_data[27] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[4] rs2_data[20] rs2_data[12] rs2_data[28] bus_write_data[28] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[5] rs2_data[21] rs2_data[13] rs2_data[29] bus_write_data[29] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[6] rs2_data[22] rs2_data[14] rs2_data[30] bus_write_data[30] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[7] rs2_data[23] rs2_data[15] rs2_data[31] bus_write_data[31] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n462_ $abc$8517$new_n444_ $abc$8517$new_n306_ $abc$8517$new_n411_ $abc$8517$new_n454_ $abc$8517$new_n451_ $abc$8517$new_n1343_ +000011 1 +000111 1 +001011 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n433_ $abc$8517$new_n436_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n442_ $abc$8517$new_n1343_ $abc$8517$new_n1344_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +010100 1 +010101 1 +010110 1 +010111 1 +.names $abc$8517$new_n310_ rs2_data[19] $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ $abc$8517$new_n1345_ +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n318_ $abc$8517$new_n315_ $abc$8517$new_n423_ $abc$8517$new_n1345_ $abc$8517$new_n335_ $abc$8517$new_n418_ $abc$8517$new_n1346_ +000000 1 +000001 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +100000 1 +100001 1 +100011 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101111 1 +111000 1 +111001 1 +111011 1 +.names $abc$8517$new_n1346_ $abc$8517$new_n413_ $abc$8517$new_n419_ $abc$8517$new_n330_ $abc$8517$new_n329_ $abc$8517$new_n415_ $abc$8517$new_n1347_ +000000 1 +000100 1 +001000 1 +001100 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100100 1 +101000 1 +101100 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110110 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n433_ $abc$8517$new_n461_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n411_ $abc$8517$new_n306_ $abc$8517$new_n1348_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +001111 1 +010010 1 +010100 1 +010101 1 +010110 1 +010111 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n495_ $abc$8517$new_n1348_ $abc$8517$new_n493_ $abc$8517$new_n492_ $abc$8517$new_n1349_ +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n479_ $abc$8517$new_n497_ $abc$8517$new_n519_ $abc$8517$new_n353_ $abc$8517$new_n467_ $abc$8517$new_n489_ $abc$8517$new_n1350_ +000000 1 +000001 1 +000010 1 +000011 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +110010 1 +110110 1 +111010 1 +111110 1 +.names $abc$8517$new_n551_ $abc$8517$new_n520_ $abc$8517$new_n368_ $abc$8517$new_n543_ $abc$8517$new_n542_ $abc$8517$new_n362_ $abc$8517$new_n1351_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +110000 1 +110001 1 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+00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1357_ $abc$8517$new_n612_ $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n1358_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n659_ $abc$8517$new_n547_ $abc$8517$new_n344_ $abc$8517$new_n342_ $abc$8517$new_n576_ $abc$8517$new_n579_ $abc$8517$new_n1359_ +000000 1 +000100 1 +000101 1 +001000 1 +001001 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010010 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1359_ $abc$8517$new_n653_ $abc$8517$new_n647_ $abc$8517$new_n646_ $abc$8517$new_n549_ $abc$8517$new_n657_ bus_address[5] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n682_ $abc$8517$new_n681_ $abc$8517$new_n680_ $abc$8517$new_n1361_ +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100100 1 +100101 1 +100110 1 +100111 1 +101100 1 +101101 1 +101110 1 +101111 1 +110100 1 +110110 1 +111110 1 +111111 1 +.names $abc$8517$new_n1361_ $abc$8517$new_n665_ $abc$8517$new_n368_ $abc$8517$new_n549_ $abc$8517$new_n1365_ $abc$8517$new_n1367_ $abc$8517$new_n1362_ +100000 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +.names $abc$8517$new_n663_ $abc$8517$new_n548_ $abc$8517$new_n664_ $abc$8517$new_n546_ $abc$8517$new_n662_ $abc$8517$new_n1362_ bus_address[6] +000000 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001010 1 +001100 1 +001101 1 +001110 1 +010000 1 +010010 1 +010100 1 +010101 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100010 1 +100100 1 +100110 1 +100111 1 +101000 1 +101010 1 +101100 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n517_ $abc$8517$new_n516_ $abc$8517$new_n507_ $abc$8517$new_n506_ $abc$8517$new_n1364_ +010000 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +.names $abc$8517$new_n1364_ $abc$8517$new_n356_ $abc$8517$new_n505_ $abc$8517$new_n504_ $abc$8517$new_n510_ $abc$8517$new_n509_ $abc$8517$new_n1365_ +000000 1 +000100 1 +001000 1 +001100 1 +100000 1 +100001 1 +100010 1 +100011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n512_ $abc$8517$new_n511_ $abc$8517$new_n525_ $abc$8517$new_n524_ $abc$8517$new_n1366_ +010000 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +.names $abc$8517$new_n1366_ $abc$8517$new_n356_ $abc$8517$new_n523_ $abc$8517$new_n522_ $abc$8517$new_n528_ $abc$8517$new_n527_ $abc$8517$new_n1367_ +000000 1 +000100 1 +001000 1 +001100 1 +100000 1 +100001 1 +100010 1 +100011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n497_ $abc$8517$new_n486_ $abc$8517$new_n399_ $abc$8517$new_n479_ $abc$8517$new_n397_ $abc$8517$new_n489_ $abc$8517$new_n1368_ +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +001111 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n712_ $abc$8517$new_n1368_ $abc$8517$new_n497_ $abc$8517$new_n701_ $abc$8517$new_n548_ $abc$8517$new_n711_ $abc$8517$new_n1369_ +001000 1 +001001 1 +001010 1 +001100 1 +001101 1 +001110 1 +010000 1 +010001 1 +010010 1 +010100 1 +010101 1 +010110 1 +011100 1 +011101 1 +011110 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101111 1 +110000 1 +110001 1 +110011 1 +110100 1 +110101 1 +110111 1 +111000 1 +111001 1 +111011 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n571_ $abc$8517$new_n556_ $abc$8517$new_n572_ $abc$8517$new_n557_ $abc$8517$new_n1371_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n724_ $abc$8517$new_n720_ $abc$8517$new_n717_ $abc$8517$new_n549_ $abc$8517$new_n1371_ $abc$8517$new_n345_ $abc$8517$new_n1372_ +100001 1 +100011 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +.names $abc$8517$new_n1372_ $abc$8517$new_n715_ $abc$8517$new_n406_ $abc$8517$new_n714_ $abc$8517$new_n709_ $abc$8517$new_n546_ bus_address[9] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100011 1 +100101 1 +100111 1 +101001 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n620_ $abc$8517$new_n605_ $abc$8517$new_n621_ $abc$8517$new_n606_ $abc$8517$new_n1374_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n754_ $abc$8517$new_n752_ $abc$8517$new_n755_ $abc$8517$new_n756_ $abc$8517$new_n745_ $abc$8517$new_n548_ $abc$8517$new_n1375_ +100000 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101100 1 +101110 1 +.names $abc$8517$new_n1375_ $abc$8517$new_n746_ $abc$8517$new_n1374_ $abc$8517$new_n549_ $abc$8517$new_n1376_ +1000 1 +1001 1 +1010 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n521_ $abc$8517$new_n531_ $abc$8517$new_n1377_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 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+111101 1 +.names $abc$8517$new_n1383_ $abc$8517$new_n820_ $abc$8517$new_n345_ $abc$8517$new_n840_ $abc$8517$new_n554_ $abc$8517$new_n581_ $abc$8517$new_n1384_ +000100 1 +000101 1 +000110 1 +000111 1 +001110 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011110 1 +011111 1 +100100 1 +100101 1 +100110 1 +100111 1 +101110 1 +101111 1 +110100 1 +110110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n820_ $abc$8517$new_n588_ $abc$8517$new_n345_ $abc$8517$new_n734_ $abc$8517$new_n850_ $abc$8517$new_n1385_ +000100 1 +000101 1 +000110 1 +000111 1 +010110 1 +010111 1 +100100 1 +100101 1 +100110 1 +100111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +.names $abc$8517$new_n853_ $abc$8517$new_n345_ $abc$8517$new_n845_ $abc$8517$new_n1385_ $abc$8517$new_n600_ $abc$8517$new_n583_ $abc$8517$new_n1386_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +110100 1 +110110 1 +.names $abc$8517$new_n546_ $abc$8517$new_n843_ $abc$8517$new_n316_ $abc$8517$new_n1386_ bus_address[18] +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n543_ $abc$8517$new_n874_ $abc$8517$new_n819_ $abc$8517$new_n634_ $abc$8517$new_n877_ $abc$8517$new_n1388_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010001 1 +010011 1 +010101 1 +010111 1 +011001 1 +011011 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1388_ $abc$8517$new_n878_ $abc$8517$new_n879_ $abc$8517$new_n869_ $abc$8517$new_n333_ $abc$8517$new_n548_ $abc$8517$new_n1389_ +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +110111 1 +.names $abc$8517$new_n413_ $abc$8517$new_n329_ $abc$8517$new_n497_ $abc$8517$new_n552_ $abc$8517$new_n547_ $abc$8517$new_n478_ $abc$8517$new_n1390_ +000000 1 +000010 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +011000 1 +011001 1 +011100 1 +011101 1 +100000 1 +100001 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n1390_ $abc$8517$new_n901_ $abc$8517$new_n897_ $abc$8517$new_n896_ $abc$8517$new_n894_ $abc$8517$new_n811_ bus_address[22] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n345_ $abc$8517$new_n717_ $abc$8517$new_n933_ $abc$8517$new_n543_ $abc$8517$new_n568_ $abc$8517$new_n434_ $abc$8517$new_n1392_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +110000 1 +110001 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n936_ $abc$8517$new_n1392_ $abc$8517$new_n932_ $abc$8517$new_n929_ $abc$8517$new_n546_ $abc$8517$new_n927_ bus_address[25] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n820_ $abc$8517$new_n368_ $abc$8517$new_n863_ $abc$8517$new_n362_ $abc$8517$new_n612_ $abc$8517$new_n1394_ +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n345_ $abc$8517$new_n748_ $abc$8517$new_n692_ $abc$8517$new_n1394_ $abc$8517$new_n719_ $abc$8517$new_n747_ $abc$8517$new_n1395_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100011 1 +100100 1 +100101 1 +100111 1 +.names $abc$8517$new_n959_ $abc$8517$new_n1395_ $abc$8517$new_n956_ $abc$8517$new_n811_ $abc$8517$new_n548_ $abc$8517$new_n952_ $abc$8517$new_n1396_ +110000 1 +110001 1 +110010 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n623_ $abc$8517$new_n620_ $abc$8517$new_n624_ $abc$8517$new_n621_ $abc$8517$new_n1397_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n1355_ $abc$8517$new_n603_ $abc$8517$new_n1397_ $abc$8517$new_n549_ bus_address[3] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n503_ $abc$8517$new_n521_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n1399_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n1369_ $abc$8517$new_n707_ $abc$8517$new_n703_ $abc$8517$new_n1399_ $abc$8517$new_n549_ bus_address[8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] singlecycle_datapath.program_counter.value[0] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] singlecycle_datapath.program_counter.value[1] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] singlecycle_datapath.program_counter.value[2] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] singlecycle_datapath.program_counter.value[3] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] singlecycle_datapath.program_counter.value[4] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] singlecycle_datapath.program_counter.value[5] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] singlecycle_datapath.program_counter.value[6] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] singlecycle_datapath.program_counter.value[7] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] singlecycle_datapath.program_counter.value[8] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] singlecycle_datapath.program_counter.value[9] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] singlecycle_datapath.program_counter.value[10] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] singlecycle_datapath.program_counter.value[11] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] singlecycle_datapath.program_counter.value[12] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] singlecycle_datapath.program_counter.value[13] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] singlecycle_datapath.program_counter.value[14] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] singlecycle_datapath.program_counter.value[15] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] singlecycle_datapath.program_counter.value[16] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] singlecycle_datapath.program_counter.value[17] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] singlecycle_datapath.program_counter.value[18] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] singlecycle_datapath.program_counter.value[19] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] singlecycle_datapath.program_counter.value[20] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] singlecycle_datapath.program_counter.value[21] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] singlecycle_datapath.program_counter.value[22] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] singlecycle_datapath.program_counter.value[23] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] singlecycle_datapath.program_counter.value[24] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] singlecycle_datapath.program_counter.value[25] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] singlecycle_datapath.program_counter.value[26] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] singlecycle_datapath.program_counter.value[27] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] singlecycle_datapath.program_counter.value[28] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] singlecycle_datapath.program_counter.value[29] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] singlecycle_datapath.program_counter.value[30] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] singlecycle_datapath.program_counter.value[31] re clock 2 +.names bus_address[0] address[0] +1 1 +.names bus_address[1] address[1] +1 1 +.names bus_address[2] address[2] +1 1 +.names bus_address[3] address[3] +1 1 +.names bus_address[4] address[4] +1 1 +.names bus_address[5] address[5] +1 1 +.names bus_address[6] address[6] +1 1 +.names bus_address[7] address[7] +1 1 +.names bus_address[8] address[8] +1 1 +.names bus_address[9] address[9] +1 1 +.names bus_address[10] address[10] +1 1 +.names bus_address[11] address[11] +1 1 +.names bus_address[12] address[12] +1 1 +.names bus_address[13] address[13] +1 1 +.names bus_address[14] address[14] +1 1 +.names bus_address[15] address[15] +1 1 +.names bus_address[16] address[16] +1 1 +.names bus_address[17] address[17] +1 1 +.names bus_address[18] address[18] +1 1 +.names bus_address[19] address[19] +1 1 +.names bus_address[20] address[20] +1 1 +.names bus_address[21] address[21] +1 1 +.names bus_address[22] address[22] +1 1 +.names bus_address[23] address[23] +1 1 +.names bus_address[24] address[24] +1 1 +.names bus_address[25] address[25] +1 1 +.names bus_address[26] address[26] +1 1 +.names bus_address[27] address[27] +1 1 +.names bus_address[28] address[28] +1 1 +.names bus_address[29] address[29] +1 1 +.names bus_address[30] address[30] +1 1 +.names bus_address[31] address[31] +1 1 +.names $false alu_function[4] +1 1 +.names bus_address[0] data_memory_interface.address[0] +1 1 +.names bus_address[1] data_memory_interface.address[1] +1 1 +.names bus_address[2] data_memory_interface.address[2] +1 1 +.names bus_address[3] data_memory_interface.address[3] +1 1 +.names bus_address[4] data_memory_interface.address[4] +1 1 +.names bus_address[5] data_memory_interface.address[5] +1 1 +.names bus_address[6] data_memory_interface.address[6] +1 1 +.names bus_address[7] data_memory_interface.address[7] +1 1 +.names bus_address[8] data_memory_interface.address[8] +1 1 +.names bus_address[9] data_memory_interface.address[9] +1 1 +.names bus_address[10] data_memory_interface.address[10] +1 1 +.names bus_address[11] data_memory_interface.address[11] +1 1 +.names bus_address[12] data_memory_interface.address[12] +1 1 +.names bus_address[13] data_memory_interface.address[13] +1 1 +.names bus_address[14] data_memory_interface.address[14] +1 1 +.names bus_address[15] data_memory_interface.address[15] +1 1 +.names bus_address[16] data_memory_interface.address[16] +1 1 +.names bus_address[17] data_memory_interface.address[17] +1 1 +.names bus_address[18] data_memory_interface.address[18] +1 1 +.names bus_address[19] data_memory_interface.address[19] +1 1 +.names bus_address[20] data_memory_interface.address[20] +1 1 +.names bus_address[21] data_memory_interface.address[21] +1 1 +.names bus_address[22] data_memory_interface.address[22] +1 1 +.names bus_address[23] data_memory_interface.address[23] +1 1 +.names bus_address[24] data_memory_interface.address[24] +1 1 +.names bus_address[25] data_memory_interface.address[25] +1 1 +.names bus_address[26] data_memory_interface.address[26] +1 1 +.names bus_address[27] data_memory_interface.address[27] +1 1 +.names bus_address[28] data_memory_interface.address[28] +1 1 +.names bus_address[29] data_memory_interface.address[29] +1 1 +.names bus_address[30] data_memory_interface.address[30] +1 1 +.names bus_address[31] data_memory_interface.address[31] +1 1 +.names bus_address[0] data_memory_interface.bus_address[0] +1 1 +.names bus_address[1] data_memory_interface.bus_address[1] +1 1 +.names bus_address[2] data_memory_interface.bus_address[2] +1 1 +.names bus_address[3] data_memory_interface.bus_address[3] +1 1 +.names bus_address[4] data_memory_interface.bus_address[4] +1 1 +.names bus_address[5] data_memory_interface.bus_address[5] +1 1 +.names bus_address[6] data_memory_interface.bus_address[6] +1 1 +.names bus_address[7] data_memory_interface.bus_address[7] +1 1 +.names bus_address[8] data_memory_interface.bus_address[8] +1 1 +.names bus_address[9] data_memory_interface.bus_address[9] +1 1 +.names bus_address[10] data_memory_interface.bus_address[10] +1 1 +.names bus_address[11] data_memory_interface.bus_address[11] +1 1 +.names bus_address[12] data_memory_interface.bus_address[12] +1 1 +.names bus_address[13] data_memory_interface.bus_address[13] +1 1 +.names bus_address[14] data_memory_interface.bus_address[14] +1 1 +.names bus_address[15] data_memory_interface.bus_address[15] +1 1 +.names bus_address[16] data_memory_interface.bus_address[16] +1 1 +.names bus_address[17] data_memory_interface.bus_address[17] +1 1 +.names bus_address[18] data_memory_interface.bus_address[18] +1 1 +.names bus_address[19] data_memory_interface.bus_address[19] +1 1 +.names bus_address[20] data_memory_interface.bus_address[20] +1 1 +.names bus_address[21] data_memory_interface.bus_address[21] +1 1 +.names bus_address[22] data_memory_interface.bus_address[22] +1 1 +.names bus_address[23] data_memory_interface.bus_address[23] +1 1 +.names bus_address[24] data_memory_interface.bus_address[24] +1 1 +.names bus_address[25] data_memory_interface.bus_address[25] +1 1 +.names bus_address[26] data_memory_interface.bus_address[26] +1 1 +.names bus_address[27] data_memory_interface.bus_address[27] +1 1 +.names bus_address[28] data_memory_interface.bus_address[28] +1 1 +.names bus_address[29] data_memory_interface.bus_address[29] +1 1 +.names bus_address[30] data_memory_interface.bus_address[30] +1 1 +.names bus_address[31] data_memory_interface.bus_address[31] +1 1 +.names bus_byte_enable[0] data_memory_interface.bus_byte_enable[0] +1 1 +.names bus_byte_enable[1] data_memory_interface.bus_byte_enable[1] +1 1 +.names bus_byte_enable[2] data_memory_interface.bus_byte_enable[2] +1 1 +.names bus_byte_enable[3] data_memory_interface.bus_byte_enable[3] +1 1 +.names bus_read_data[0] data_memory_interface.bus_read_data[0] +1 1 +.names bus_read_data[1] data_memory_interface.bus_read_data[1] +1 1 +.names bus_read_data[2] data_memory_interface.bus_read_data[2] +1 1 +.names bus_read_data[3] data_memory_interface.bus_read_data[3] +1 1 +.names bus_read_data[4] data_memory_interface.bus_read_data[4] +1 1 +.names bus_read_data[5] data_memory_interface.bus_read_data[5] +1 1 +.names bus_read_data[6] data_memory_interface.bus_read_data[6] +1 1 +.names bus_read_data[7] data_memory_interface.bus_read_data[7] +1 1 +.names bus_read_data[8] data_memory_interface.bus_read_data[8] +1 1 +.names bus_read_data[9] data_memory_interface.bus_read_data[9] +1 1 +.names bus_read_data[10] data_memory_interface.bus_read_data[10] +1 1 +.names bus_read_data[11] data_memory_interface.bus_read_data[11] +1 1 +.names bus_read_data[12] data_memory_interface.bus_read_data[12] +1 1 +.names bus_read_data[13] data_memory_interface.bus_read_data[13] +1 1 +.names bus_read_data[14] data_memory_interface.bus_read_data[14] +1 1 +.names bus_read_data[15] data_memory_interface.bus_read_data[15] +1 1 +.names bus_read_data[16] data_memory_interface.bus_read_data[16] +1 1 +.names bus_read_data[17] data_memory_interface.bus_read_data[17] +1 1 +.names bus_read_data[18] data_memory_interface.bus_read_data[18] +1 1 +.names bus_read_data[19] data_memory_interface.bus_read_data[19] +1 1 +.names bus_read_data[20] data_memory_interface.bus_read_data[20] +1 1 +.names bus_read_data[21] data_memory_interface.bus_read_data[21] +1 1 +.names bus_read_data[22] data_memory_interface.bus_read_data[22] +1 1 +.names bus_read_data[23] data_memory_interface.bus_read_data[23] +1 1 +.names bus_read_data[24] data_memory_interface.bus_read_data[24] +1 1 +.names bus_read_data[25] data_memory_interface.bus_read_data[25] +1 1 +.names bus_read_data[26] data_memory_interface.bus_read_data[26] +1 1 +.names bus_read_data[27] data_memory_interface.bus_read_data[27] +1 1 +.names bus_read_data[28] data_memory_interface.bus_read_data[28] +1 1 +.names bus_read_data[29] data_memory_interface.bus_read_data[29] +1 1 +.names bus_read_data[30] data_memory_interface.bus_read_data[30] +1 1 +.names bus_read_data[31] data_memory_interface.bus_read_data[31] +1 1 +.names bus_read_enable data_memory_interface.bus_read_enable +1 1 +.names bus_write_data[0] data_memory_interface.bus_write_data[0] +1 1 +.names bus_write_data[1] data_memory_interface.bus_write_data[1] +1 1 +.names bus_write_data[2] data_memory_interface.bus_write_data[2] +1 1 +.names bus_write_data[3] data_memory_interface.bus_write_data[3] +1 1 +.names bus_write_data[4] data_memory_interface.bus_write_data[4] +1 1 +.names bus_write_data[5] data_memory_interface.bus_write_data[5] +1 1 +.names bus_write_data[6] data_memory_interface.bus_write_data[6] +1 1 +.names bus_write_data[7] data_memory_interface.bus_write_data[7] +1 1 +.names bus_write_data[8] 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bus_write_data[22] data_memory_interface.bus_write_data[22] +1 1 +.names bus_write_data[23] data_memory_interface.bus_write_data[23] +1 1 +.names bus_write_data[24] data_memory_interface.bus_write_data[24] +1 1 +.names bus_write_data[25] data_memory_interface.bus_write_data[25] +1 1 +.names bus_write_data[26] data_memory_interface.bus_write_data[26] +1 1 +.names bus_write_data[27] data_memory_interface.bus_write_data[27] +1 1 +.names bus_write_data[28] data_memory_interface.bus_write_data[28] +1 1 +.names bus_write_data[29] data_memory_interface.bus_write_data[29] +1 1 +.names bus_write_data[30] data_memory_interface.bus_write_data[30] +1 1 +.names bus_write_data[31] data_memory_interface.bus_write_data[31] +1 1 +.names bus_write_enable data_memory_interface.bus_write_enable +1 1 +.names clock data_memory_interface.clock +1 1 +.names inst[12] data_memory_interface.data_format[0] +1 1 +.names inst[13] data_memory_interface.data_format[1] +1 1 +.names inst[14] data_memory_interface.data_format[2] +1 1 +.names bus_read_enable data_memory_interface.read_enable +1 1 +.names rs2_data[0] data_memory_interface.write_data[0] +1 1 +.names rs2_data[1] data_memory_interface.write_data[1] +1 1 +.names rs2_data[2] data_memory_interface.write_data[2] +1 1 +.names rs2_data[3] data_memory_interface.write_data[3] +1 1 +.names rs2_data[4] data_memory_interface.write_data[4] +1 1 +.names rs2_data[5] data_memory_interface.write_data[5] +1 1 +.names rs2_data[6] data_memory_interface.write_data[6] +1 1 +.names rs2_data[7] data_memory_interface.write_data[7] +1 1 +.names rs2_data[8] data_memory_interface.write_data[8] +1 1 +.names rs2_data[9] data_memory_interface.write_data[9] +1 1 +.names rs2_data[10] data_memory_interface.write_data[10] +1 1 +.names rs2_data[11] data_memory_interface.write_data[11] +1 1 +.names rs2_data[12] data_memory_interface.write_data[12] +1 1 +.names rs2_data[13] data_memory_interface.write_data[13] +1 1 +.names rs2_data[14] data_memory_interface.write_data[14] +1 1 +.names rs2_data[15] data_memory_interface.write_data[15] +1 1 +.names rs2_data[16] data_memory_interface.write_data[16] +1 1 +.names rs2_data[17] data_memory_interface.write_data[17] +1 1 +.names rs2_data[18] data_memory_interface.write_data[18] +1 1 +.names rs2_data[19] data_memory_interface.write_data[19] +1 1 +.names rs2_data[20] data_memory_interface.write_data[20] +1 1 +.names rs2_data[21] data_memory_interface.write_data[21] +1 1 +.names rs2_data[22] data_memory_interface.write_data[22] +1 1 +.names rs2_data[23] data_memory_interface.write_data[23] +1 1 +.names rs2_data[24] data_memory_interface.write_data[24] +1 1 +.names rs2_data[25] data_memory_interface.write_data[25] +1 1 +.names rs2_data[26] data_memory_interface.write_data[26] +1 1 +.names rs2_data[27] data_memory_interface.write_data[27] +1 1 +.names rs2_data[28] data_memory_interface.write_data[28] +1 1 +.names rs2_data[29] data_memory_interface.write_data[29] +1 1 +.names rs2_data[30] data_memory_interface.write_data[30] +1 1 +.names rs2_data[31] data_memory_interface.write_data[31] +1 1 +.names bus_write_enable data_memory_interface.write_enable +1 1 +.names inst[12] inst_funct3[0] +1 1 +.names inst[13] inst_funct3[1] +1 1 +.names inst[14] inst_funct3[2] +1 1 +.names inst[25] inst_funct7[0] +1 1 +.names inst[26] inst_funct7[1] +1 1 +.names inst[27] inst_funct7[2] +1 1 +.names inst[28] inst_funct7[3] +1 1 +.names inst[29] inst_funct7[4] +1 1 +.names inst[30] inst_funct7[5] +1 1 +.names inst[31] inst_funct7[6] +1 1 +.names inst[0] inst_opcode[0] +1 1 +.names inst[1] inst_opcode[1] +1 1 +.names inst[2] inst_opcode[2] +1 1 +.names inst[3] inst_opcode[3] +1 1 +.names inst[4] inst_opcode[4] +1 1 +.names inst[5] inst_opcode[5] +1 1 +.names inst[6] inst_opcode[6] +1 1 +.names singlecycle_datapath.program_counter.value[0] pc[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] pc[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] pc[2] +1 1 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singlecycle_datapath.program_counter.value[18] pc[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] pc[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] pc[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] pc[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] pc[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] pc[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] pc[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] pc[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] pc[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] pc[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] pc[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] pc[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] pc[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] pc[31] +1 1 +.names $true pc_write_enable +1 1 +.names inst[7] rd_address[0] +1 1 +.names $false rd_address[1] +1 1 +.names $false rd_address[2] +1 1 +.names $false rd_address[3] +1 1 +.names $false rd_address[4] +1 1 +.names bus_read_enable read_enable +1 1 +.names inst[15] rs1_address[0] +1 1 +.names $false rs1_address[1] +1 1 +.names $false rs1_address[2] +1 1 +.names $false rs1_address[3] +1 1 +.names $false rs1_address[4] +1 1 +.names inst[20] rs2_address[0] +1 1 +.names $false rs2_address[1] +1 1 +.names $false rs2_address[2] +1 1 +.names $false rs2_address[3] +1 1 +.names $false rs2_address[4] +1 1 +.names alu_function[0] singlecycle_ctlpath.alu_control.alu_function[0] +1 1 +.names alu_function[1] singlecycle_ctlpath.alu_control.alu_function[1] +1 1 +.names alu_function[2] singlecycle_ctlpath.alu_control.alu_function[2] +1 1 +.names alu_function[3] singlecycle_ctlpath.alu_control.alu_function[3] +1 1 +.names $false singlecycle_ctlpath.alu_control.alu_function[4] +1 1 +.names singlecycle_ctlpath.alu_control.branch_funct[2] singlecycle_ctlpath.alu_control.branch_funct[1] +1 1 +.names inst[12] singlecycle_ctlpath.alu_control.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.alu_control.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.alu_control.inst_funct3[2] +1 1 +.names inst[25] singlecycle_ctlpath.alu_control.inst_funct7[0] +1 1 +.names inst[26] singlecycle_ctlpath.alu_control.inst_funct7[1] +1 1 +.names inst[27] singlecycle_ctlpath.alu_control.inst_funct7[2] +1 1 +.names inst[28] singlecycle_ctlpath.alu_control.inst_funct7[3] +1 1 +.names inst[29] singlecycle_ctlpath.alu_control.inst_funct7[4] +1 1 +.names inst[30] singlecycle_ctlpath.alu_control.inst_funct7[5] +1 1 +.names inst[31] singlecycle_ctlpath.alu_control.inst_funct7[6] +1 1 +.names $false singlecycle_ctlpath.alu_control.op_funct[4] +1 1 +.names $false singlecycle_ctlpath.alu_control.op_imm_funct[4] +1 1 +.names alu_function[0] singlecycle_ctlpath.alu_function[0] +1 1 +.names alu_function[1] singlecycle_ctlpath.alu_function[1] +1 1 +.names alu_function[2] singlecycle_ctlpath.alu_function[2] +1 1 +.names alu_function[3] singlecycle_ctlpath.alu_function[3] +1 1 +.names $false singlecycle_ctlpath.alu_function[4] +1 1 +.names inst[12] singlecycle_ctlpath.control_transfer.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.control_transfer.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.control_transfer.inst_funct3[2] +1 1 +.names bus_read_enable singlecycle_ctlpath.data_mem_read_enable +1 1 +.names bus_write_enable singlecycle_ctlpath.data_mem_write_enable +1 1 +.names inst[12] singlecycle_ctlpath.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.inst_funct3[2] +1 1 +.names inst[25] singlecycle_ctlpath.inst_funct7[0] +1 1 +.names inst[26] singlecycle_ctlpath.inst_funct7[1] +1 1 +.names inst[27] singlecycle_ctlpath.inst_funct7[2] +1 1 +.names inst[28] singlecycle_ctlpath.inst_funct7[3] +1 1 +.names inst[29] singlecycle_ctlpath.inst_funct7[4] +1 1 +.names inst[30] singlecycle_ctlpath.inst_funct7[5] +1 1 +.names inst[31] singlecycle_ctlpath.inst_funct7[6] +1 1 +.names inst[0] singlecycle_ctlpath.inst_opcode[0] +1 1 +.names inst[1] singlecycle_ctlpath.inst_opcode[1] +1 1 +.names inst[2] singlecycle_ctlpath.inst_opcode[2] +1 1 +.names inst[3] singlecycle_ctlpath.inst_opcode[3] +1 1 +.names inst[4] singlecycle_ctlpath.inst_opcode[4] +1 1 +.names inst[5] singlecycle_ctlpath.inst_opcode[5] +1 1 +.names inst[6] singlecycle_ctlpath.inst_opcode[6] +1 1 +.names $true singlecycle_ctlpath.pc_write_enable +1 1 +.names $false singlecycle_ctlpath.reg_writeback_select[2] +1 1 +.names regfile_write_enable singlecycle_ctlpath.regfile_write_enable +1 1 +.names bus_read_enable singlecycle_ctlpath.singlecycle_control.data_mem_read_enable +1 1 +.names bus_write_enable singlecycle_ctlpath.singlecycle_control.data_mem_write_enable +1 1 +.names inst[0] singlecycle_ctlpath.singlecycle_control.inst_opcode[0] +1 1 +.names inst[1] singlecycle_ctlpath.singlecycle_control.inst_opcode[1] +1 1 +.names inst[2] singlecycle_ctlpath.singlecycle_control.inst_opcode[2] +1 1 +.names inst[3] singlecycle_ctlpath.singlecycle_control.inst_opcode[3] +1 1 +.names inst[4] singlecycle_ctlpath.singlecycle_control.inst_opcode[4] +1 1 +.names inst[5] singlecycle_ctlpath.singlecycle_control.inst_opcode[5] +1 1 +.names inst[6] singlecycle_ctlpath.singlecycle_control.inst_opcode[6] +1 1 +.names $true singlecycle_ctlpath.singlecycle_control.pc_write_enable +1 1 +.names $false singlecycle_ctlpath.singlecycle_control.reg_writeback_select[2] +1 1 +.names regfile_write_enable singlecycle_ctlpath.singlecycle_control.regfile_write_enable +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[0] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[1] +1 1 +.names $true singlecycle_datapath.adder_pc_plus_4.operand_a[2] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[3] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[4] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[5] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[6] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[7] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[8] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[9] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[10] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[11] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[12] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[13] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[14] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[15] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[16] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[17] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[18] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[19] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[20] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[21] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[22] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[23] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[24] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[25] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[26] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[27] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[28] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[29] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[30] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.operand_b[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.operand_b[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_4.operand_b[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_4.operand_b[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_4.operand_b[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_4.operand_b[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_4.operand_b[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_4.operand_b[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_4.operand_b[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_4.operand_b[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.adder_pc_plus_4.operand_b[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.adder_pc_plus_4.operand_b[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.adder_pc_plus_4.operand_b[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.adder_pc_plus_4.operand_b[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_4.operand_b[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.adder_pc_plus_4.operand_b[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.adder_pc_plus_4.operand_b[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.adder_pc_plus_4.operand_b[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.adder_pc_plus_4.operand_b[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.adder_pc_plus_4.operand_b[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.adder_pc_plus_4.operand_b[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.adder_pc_plus_4.operand_b[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.adder_pc_plus_4.operand_b[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.adder_pc_plus_4.operand_b[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_4.operand_b[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_4.operand_b[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.adder_pc_plus_4.operand_b[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.adder_pc_plus_4.operand_b[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.adder_pc_plus_4.operand_b[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.adder_pc_plus_4.operand_b[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.adder_pc_plus_4.operand_b[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_4.operand_b[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.result[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.result[1] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_immediate.operand_a[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_immediate.operand_a[1] +1 1 +.names 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1 +.names bus_address[12] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[44] +1 1 +.names bus_address[13] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[45] +1 1 +.names bus_address[14] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[46] +1 1 +.names bus_address[15] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[47] +1 1 +.names bus_address[16] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[48] +1 1 +.names bus_address[17] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[49] +1 1 +.names bus_address[18] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[50] +1 1 +.names bus_address[19] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[51] +1 1 +.names bus_address[20] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[52] +1 1 +.names bus_address[21] singlecycle_datapath.mux_next_pc_select.multiplexer.in_bus[53] +1 1 +.names bus_address[22] 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singlecycle_datapath.program_counter.value[9] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.mux_operand_a.multiplexer.in_bus[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] 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rs1_data[16] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][16] +1 1 +.names rs1_data[17] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][17] +1 1 +.names rs1_data[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][18] +1 1 +.names rs1_data[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][19] +1 1 +.names rs1_data[20] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][20] +1 1 +.names rs1_data[21] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][21] +1 1 +.names rs1_data[22] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][22] +1 1 +.names rs1_data[23] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][23] +1 1 +.names rs1_data[24] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][24] +1 1 +.names rs1_data[25] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][25] +1 1 +.names rs1_data[26] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][26] 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singlecycle_datapath.program_counter.value[4] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][19] +1 1 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singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][31] +1 1 +.names rs2_data[0] singlecycle_datapath.mux_operand_b.in0[0] +1 1 +.names rs2_data[1] singlecycle_datapath.mux_operand_b.in0[1] +1 1 +.names rs2_data[2] singlecycle_datapath.mux_operand_b.in0[2] +1 1 +.names rs2_data[3] singlecycle_datapath.mux_operand_b.in0[3] +1 1 +.names rs2_data[4] singlecycle_datapath.mux_operand_b.in0[4] +1 1 +.names rs2_data[5] singlecycle_datapath.mux_operand_b.in0[5] +1 1 +.names rs2_data[6] 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rs1_data[22] singlecycle_datapath.rs1_data[22] +1 1 +.names rs1_data[23] singlecycle_datapath.rs1_data[23] +1 1 +.names rs1_data[24] singlecycle_datapath.rs1_data[24] +1 1 +.names rs1_data[25] singlecycle_datapath.rs1_data[25] +1 1 +.names rs1_data[26] singlecycle_datapath.rs1_data[26] +1 1 +.names rs1_data[27] singlecycle_datapath.rs1_data[27] +1 1 +.names rs1_data[28] singlecycle_datapath.rs1_data[28] +1 1 +.names rs1_data[29] singlecycle_datapath.rs1_data[29] +1 1 +.names rs1_data[30] singlecycle_datapath.rs1_data[30] +1 1 +.names rs1_data[31] singlecycle_datapath.rs1_data[31] +1 1 +.names inst[20] singlecycle_datapath.rs2_address[0] +1 1 +.names $false singlecycle_datapath.rs2_address[1] +1 1 +.names $false singlecycle_datapath.rs2_address[2] +1 1 +.names $false singlecycle_datapath.rs2_address[3] +1 1 +.names $false singlecycle_datapath.rs2_address[4] +1 1 +.names rs2_data[0] singlecycle_datapath.rs2_data[0] +1 1 +.names rs2_data[1] singlecycle_datapath.rs2_data[1] +1 1 +.names rs2_data[2] singlecycle_datapath.rs2_data[2] +1 1 +.names rs2_data[3] singlecycle_datapath.rs2_data[3] +1 1 +.names rs2_data[4] singlecycle_datapath.rs2_data[4] +1 1 +.names rs2_data[5] singlecycle_datapath.rs2_data[5] +1 1 +.names rs2_data[6] singlecycle_datapath.rs2_data[6] +1 1 +.names rs2_data[7] singlecycle_datapath.rs2_data[7] +1 1 +.names rs2_data[8] singlecycle_datapath.rs2_data[8] +1 1 +.names rs2_data[9] singlecycle_datapath.rs2_data[9] +1 1 +.names rs2_data[10] singlecycle_datapath.rs2_data[10] +1 1 +.names rs2_data[11] singlecycle_datapath.rs2_data[11] +1 1 +.names rs2_data[12] singlecycle_datapath.rs2_data[12] +1 1 +.names rs2_data[13] singlecycle_datapath.rs2_data[13] +1 1 +.names rs2_data[14] singlecycle_datapath.rs2_data[14] +1 1 +.names rs2_data[15] singlecycle_datapath.rs2_data[15] +1 1 +.names rs2_data[16] singlecycle_datapath.rs2_data[16] +1 1 +.names rs2_data[17] singlecycle_datapath.rs2_data[17] +1 1 +.names rs2_data[18] singlecycle_datapath.rs2_data[18] +1 1 +.names rs2_data[19] singlecycle_datapath.rs2_data[19] +1 1 +.names rs2_data[20] singlecycle_datapath.rs2_data[20] +1 1 +.names rs2_data[21] singlecycle_datapath.rs2_data[21] +1 1 +.names rs2_data[22] singlecycle_datapath.rs2_data[22] +1 1 +.names rs2_data[23] singlecycle_datapath.rs2_data[23] +1 1 +.names rs2_data[24] singlecycle_datapath.rs2_data[24] +1 1 +.names rs2_data[25] singlecycle_datapath.rs2_data[25] +1 1 +.names rs2_data[26] singlecycle_datapath.rs2_data[26] +1 1 +.names rs2_data[27] singlecycle_datapath.rs2_data[27] +1 1 +.names rs2_data[28] singlecycle_datapath.rs2_data[28] +1 1 +.names rs2_data[29] singlecycle_datapath.rs2_data[29] +1 1 +.names rs2_data[30] singlecycle_datapath.rs2_data[30] +1 1 +.names rs2_data[31] singlecycle_datapath.rs2_data[31] +1 1 +.names rs2_data[0] write_data[0] +1 1 +.names rs2_data[1] write_data[1] +1 1 +.names rs2_data[2] write_data[2] +1 1 +.names rs2_data[3] write_data[3] +1 1 +.names rs2_data[4] write_data[4] +1 1 +.names rs2_data[5] write_data[5] +1 1 +.names rs2_data[6] write_data[6] +1 1 +.names rs2_data[7] write_data[7] +1 1 +.names rs2_data[8] write_data[8] +1 1 +.names rs2_data[9] write_data[9] +1 1 +.names rs2_data[10] write_data[10] +1 1 +.names rs2_data[11] write_data[11] +1 1 +.names rs2_data[12] write_data[12] +1 1 +.names rs2_data[13] write_data[13] +1 1 +.names rs2_data[14] write_data[14] +1 1 +.names rs2_data[15] write_data[15] +1 1 +.names rs2_data[16] write_data[16] +1 1 +.names rs2_data[17] write_data[17] +1 1 +.names rs2_data[18] write_data[18] +1 1 +.names rs2_data[19] write_data[19] +1 1 +.names rs2_data[20] write_data[20] +1 1 +.names rs2_data[21] write_data[21] +1 1 +.names rs2_data[22] write_data[22] +1 1 +.names rs2_data[23] write_data[23] +1 1 +.names rs2_data[24] write_data[24] +1 1 +.names rs2_data[25] write_data[25] +1 1 +.names rs2_data[26] write_data[26] +1 1 +.names rs2_data[27] write_data[27] +1 1 +.names rs2_data[28] write_data[28] +1 1 +.names rs2_data[29] write_data[29] +1 1 +.names rs2_data[30] write_data[30] +1 1 +.names rs2_data[31] write_data[31] +1 1 +.names bus_write_enable write_enable +1 1 +.end From c26370e913b875a8b59850bd4d801ceadd8cb021 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 13 Dec 2019 15:19:54 -0800 Subject: [PATCH 021/107] New integration point for master+wip. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> From 42da49db79aec07ba1961d76d8b942d0658069d6 Mon Sep 17 00:00:00 2001 From: Michael Gielda Date: Sun, 16 Jun 2019 15:33:38 +0200 Subject: [PATCH 022/107] Add VTR change issue template Signed-off-by: Alessandro Comodi --- .github/ISSUE_TEMPLATE/bug_report.md | 3 +++ .github/ISSUE_TEMPLATE/feature_request.md | 3 +++ .github/ISSUE_TEMPLATE/vtr-change.md | 25 +++++++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/vtr-change.md diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index dc1b48f28cc..1e5584ab1b6 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -1,6 +1,9 @@ --- name: Bug report about: Create a report to help us improve +title: '' +labels: '' +assignees: '' --- diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md index 96a3a6f322e..7523b9efbf8 100644 --- a/.github/ISSUE_TEMPLATE/feature_request.md +++ b/.github/ISSUE_TEMPLATE/feature_request.md @@ -1,6 +1,9 @@ --- name: Feature request about: Suggest an idea for this project +title: '' +labels: '' +assignees: '' --- diff --git a/.github/ISSUE_TEMPLATE/vtr-change.md b/.github/ISSUE_TEMPLATE/vtr-change.md new file mode 100644 index 00000000000..74d5ec9e8f6 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/vtr-change.md @@ -0,0 +1,25 @@ +--- +name: VTR change +about: Describe purpose and lifecycle of a local change we made to VTR +title: '' +labels: '' +assignees: '' + +--- + +### Why did we need this? (what does this change enable us to do) + + +### What did it change? + + +### Should it be merged upstream - if not, when can we delete it? + +### What is needed to get this merged / deleted? + +* [ ] is the implementation work to make suitable for merging / deletion completed? +* [ ] Is there an associated test? +* [ ] is this currently part of the Conda package? +* [ ] is this properly cleaned up in our local repositories? + +### Tracker / branch / PR & other useful links From f0fd61977ba18e41a4ff6bea07e77a815267e665 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 12 Dec 2019 00:51:04 -0800 Subject: [PATCH 023/107] Implement initial explicit ports. This implements part one of #1063 Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- libs/libarchfpga/src/physical_types.h | 15 +- libs/libarchfpga/src/read_xml_arch_file.cpp | 214 +++++++++++++++----- vpr/src/base/ShowSetup.cpp | 2 +- vpr/src/base/check_netlist.cpp | 2 +- vpr/src/base/read_netlist.cpp | 4 +- vpr/src/draw/draw.cpp | 2 +- vpr/src/pack/output_clustering.cpp | 2 +- vpr/src/place/place_macro.cpp | 4 +- vpr/src/util/vpr_utils.cpp | 61 +++--- vpr/src/util/vpr_utils.h | 7 +- 10 files changed, 221 insertions(+), 92 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 36901e6f0ed..e28832bf918 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -523,6 +523,12 @@ enum class e_sb_type { }; +enum class e_capacity_type { + DUPLICATE, // Capacity duplicates ports. + EXPLICIT // Capacity increases the number of logical tiles, but does not + // modify the physical ports. +}; + constexpr int NO_SWITCH = -1; constexpr int DEFAULT_SWITCH = -2; @@ -577,6 +583,7 @@ struct t_physical_tile_type { int num_clock_pins = 0; int capacity = 0; + e_capacity_type capacity_type = e_capacity_type::DUPLICATE; int width = 0; int height = 0; @@ -625,18 +632,20 @@ struct t_physical_tile_type { * vtr::bimap container. */ struct t_logical_pin { + int z_index = -1; int pin = -1; - t_logical_pin(int value) { + t_logical_pin(int z_index_value, int value) { + z_index = z_index_value; pin = value; } bool operator==(const t_logical_pin o) const { - return pin == o.pin; + return z_index == o.z_index && pin == o.pin; } bool operator<(const t_logical_pin o) const { - return pin < o.pin; + return std::make_pair(z_index, pin) < std::make_pair(o.z_index, o.pin); } }; diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 32381facab6..edadfd5e62e 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -86,10 +86,10 @@ static void LoadPinLoc(pugi::xml_node Locations, t_physical_tile_type* type, const pugiutil::loc_data& loc_data); template -static std::pair ProcessPinString(pugi::xml_node Locations, - T type, - const char* pin_loc_string, - const pugiutil::loc_data& loc_data); +static std::pair> ProcessPinString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data); /* Process XML hierarchy */ static void ProcessTiles(pugi::xml_node Node, @@ -427,7 +427,12 @@ static void SetupPinLocationsAndPinClasses(pugi::xml_node Locations, pugi::xml_node Cur; - capacity = PhysicalTileType->capacity; + if (PhysicalTileType->capacity_type == e_capacity_type::DUPLICATE) { + capacity = PhysicalTileType->capacity; + } else { + VTR_ASSERT(PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT); + capacity = 1; + } if (!Locations) { PhysicalTileType->pin_location_distribution = E_SPREAD_PIN_DISTR; } else { @@ -816,10 +821,19 @@ static void LoadPinLoc(pugi::xml_node Locations, for (int height = 0; height < type->height; ++height) { for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) { for (int pin = 0; pin < type->num_pin_loc_assignments[width][height][side]; ++pin) { - auto pin_range = ProcessPinString(Locations, - type, - type->pin_loc_assignments[width][height][side][pin], - loc_data); + int instance_idx; + std::pair pin_range; + std::tie(instance_idx, pin_range) = ProcessPinString(Locations, + type, + type->pin_loc_assignments[width][height][side][pin], + loc_data); + if (instance_idx != 0) { + archfpga_throw( + loc_data.filename_c_str(), + loc_data.line(Locations), + "Instance index is not allocated on custom pin: %s\n", + type->pin_loc_assignments[width][height][side][pin]); + } for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { VTR_ASSERT(pin_num < type->num_pins / type->capacity); @@ -848,10 +862,11 @@ static void LoadPinLoc(pugi::xml_node Locations, } template -static std::pair ProcessPinString(pugi::xml_node Locations, - T type, - const char* pin_loc_string, - const pugiutil::loc_data& loc_data) { +static std::pair> ProcessPinString(pugi::xml_node Locations, + T type, + const char* pin_loc_string, + const pugiutil::loc_data& loc_data) { + int instance_idx = 0; int num_tokens; auto tokens = GetTokensFromString(pin_loc_string, &num_tokens); @@ -866,6 +881,31 @@ static std::pair ProcessPinString(pugi::xml_node Locations, token_index++; token = tokens[token_index]; + if (token.type == TOKEN_OPEN_SQUARE_BRACKET) { + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_INT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Instance index is not a valid number: %s\n", + pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + + if (token.type != TOKEN_CLOSE_SQUARE_BRACKET) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), + "Missing close brace on instance index: %s\n", + pin_loc_string); + } + + token_index++; + token = tokens[token_index]; + + instance_idx = vtr::atoi(token.data); + } + if (token.type != TOKEN_DOT) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Locations), "No dot is present to separate type name and port name: %s\n", pin_loc_string); @@ -893,7 +933,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, // All the pins of the port are taken or the port has a single pin if (token_index == num_tokens) { freeTokens(tokens, num_tokens); - return std::make_pair(abs_first_pin_idx, abs_first_pin_idx + port->num_pins); + return std::make_pair(instance_idx, std::make_pair(abs_first_pin_idx, abs_first_pin_idx + port->num_pins)); } token = tokens[token_index]; @@ -931,7 +971,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, } freeTokens(tokens, num_tokens); - return std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + first_pin + 1); + return std::make_pair(instance_idx, std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + first_pin + 1)); } token_index++; @@ -964,7 +1004,7 @@ static std::pair ProcessPinString(pugi::xml_node Locations, } freeTokens(tokens, num_tokens); - return std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + last_pin + 1); + return std::make_pair(instance_idx, std::make_pair(abs_first_pin_idx + first_pin, abs_first_pin_idx + last_pin + 1)); } static void ProcessPinToPinAnnotations(pugi::xml_node Parent, @@ -2065,9 +2105,16 @@ static void Process_Fc(pugi::xml_node Node, /* Go through all the port/segment combinations and create the (potentially * overriden) pin/seg Fc specifications */ - int pins_per_capacity_instance = PhysicalTileType->num_pins / PhysicalTileType->capacity; + int capacity; + if (PhysicalTileType->capacity_type == e_capacity_type::DUPLICATE) { + capacity = PhysicalTileType->capacity; + } else { + VTR_ASSERT(PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT); + capacity = 1; + } + int pins_per_capacity_instance = PhysicalTileType->num_pins / capacity; for (size_t iseg = 0; iseg < segments.size(); ++iseg) { - for (int icapacity = 0; icapacity < PhysicalTileType->capacity; ++icapacity) { + for (int icapacity = 0; icapacity < capacity; ++icapacity) { //If capacity > 0, we need t offset the block index by the number of pins per instance //this ensures that all pins have an Fc specification int iblk_pin = icapacity * pins_per_capacity_instance; @@ -2998,12 +3045,21 @@ static void ProcessTiles(pugi::xml_node Node, /* Process tile port definitions */ ProcessTilePorts(CurTileType, &PhysicalTileType, loc_data); - PhysicalTileType.num_pins = PhysicalTileType.capacity - * (PhysicalTileType.num_input_pins - + PhysicalTileType.num_output_pins - + PhysicalTileType.num_clock_pins); - PhysicalTileType.num_receivers = PhysicalTileType.capacity * PhysicalTileType.num_input_pins; - PhysicalTileType.num_drivers = PhysicalTileType.capacity * PhysicalTileType.num_output_pins; + if (PhysicalTileType.capacity_type == e_capacity_type::DUPLICATE) { + PhysicalTileType.num_pins = PhysicalTileType.capacity + * (PhysicalTileType.num_input_pins + + PhysicalTileType.num_output_pins + + PhysicalTileType.num_clock_pins); + PhysicalTileType.num_receivers = PhysicalTileType.capacity * PhysicalTileType.num_input_pins; + PhysicalTileType.num_drivers = PhysicalTileType.capacity * PhysicalTileType.num_output_pins; + } else { + VTR_ASSERT(PhysicalTileType.capacity_type == e_capacity_type::EXPLICIT); + PhysicalTileType.num_pins = (PhysicalTileType.num_input_pins + + PhysicalTileType.num_output_pins + + PhysicalTileType.num_clock_pins); + PhysicalTileType.num_receivers = PhysicalTileType.num_input_pins; + PhysicalTileType.num_drivers = PhysicalTileType.num_output_pins; + } /* Assign Fc, Pin locations ans Switch Block locations to the Physical Tile Type */ @@ -3050,7 +3106,7 @@ static void ProcessTiles(pugi::xml_node Node, static void ProcessTileProps(pugi::xml_node Node, t_physical_tile_type* PhysicalTileType, const pugiutil::loc_data& loc_data) { - expect_only_attributes(Node, {"name", "capacity", "width", "height", "area"}, loc_data); + expect_only_attributes(Node, {"name", "capacity", "capacity_type", "width", "height", "area"}, loc_data); /* Load type name */ auto Prop = get_attribute(Node, "name", loc_data).value(); @@ -3066,6 +3122,20 @@ static void ProcessTileProps(pugi::xml_node Node, archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), "Area for type %s must be non-negative\n", PhysicalTileType->name); } + + const char* capacity_type = get_attribute(Node, "capacity_type", loc_data, ReqOpt::OPTIONAL).as_string(nullptr); + if (capacity_type) { + if (strcmp(capacity_type, "duplicate") == 0) { + PhysicalTileType->capacity_type = e_capacity_type::DUPLICATE; + } else if (strcmp(capacity_type, "explicit") == 0) { + PhysicalTileType->capacity_type = e_capacity_type::EXPLICIT; + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node), + "Unknown 'capacity_type' %s\n", capacity_type); + } + } else { + PhysicalTileType->capacity_type = e_capacity_type::DUPLICATE; + } } static void ProcessTilePorts(pugi::xml_node Parent, @@ -3261,11 +3331,16 @@ static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, PhysicalTileType->name); } + if (PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Custom site pins are required if capacity_type == explicit\n"); + } + vtr::bimap directs_map; for (int npin = 0; npin < num_pins; npin++) { t_physical_pin physical_pin(npin); - t_logical_pin logical_pin(npin); + t_logical_pin logical_pin(/*z_index=*/0, npin); directs_map.insert(logical_pin, physical_pin); } @@ -3302,8 +3377,35 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, // `to` attribute is relative to the logical block pins to = std::string(get_attribute(CurDirect, "to", loc_data).value()); - auto from_pins = ProcessPinString(CurDirect, PhysicalTileType, from.c_str(), loc_data); - auto to_pins = ProcessPinString(CurDirect, LogicalBlockType, to.c_str(), loc_data); + int to_idx; + int from_idx; + std::pair from_pins; + std::pair to_pins; + std::tie(from_idx, from_pins) = ProcessPinString(CurDirect, PhysicalTileType, from.c_str(), loc_data); + std::tie(to_idx, to_pins) = ProcessPinString(CurDirect, LogicalBlockType, to.c_str(), loc_data); + + if (from_idx != 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "No physical tile instance index is allowed: %s.\n", from.c_str()); + } + + if (PhysicalTileType->capacity_type == e_capacity_type::DUPLICATE) { + if (to_idx != 0) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Logical tile instances are not allowed with capacity_type == DUPLICATE: %s\n", + to.c_str()); + } + } else if (PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT) { + if (to_idx < 0 || to_idx >= PhysicalTileType->capacity) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Logical tile instance %d is out of bounds of capacity: %s\n", + to_idx, to.c_str()); + } + } else { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), + "Unknown capacity_type %d.\n", + PhysicalTileType->capacity_type); + } // Checking that the number of pins is exactly the same if (from_pins.second - from_pins.first != to_pins.second - to_pins.first) { @@ -3316,7 +3418,7 @@ static void ProcessEquivalentSiteCustomConnection(pugi::xml_node Parent, int num_pins = from_pins.second - from_pins.first; for (int i = 0; i < num_pins; i++) { t_physical_pin physical_pin(from_pins.first + i); - t_logical_pin logical_pin(to_pins.first + i); + t_logical_pin logical_pin(to_idx, to_pins.first + i); auto result = directs_map.insert(logical_pin, physical_pin); if (!result.second) { @@ -4861,33 +4963,43 @@ static void link_physical_logical_types(std::vector& Physi for (int pin = 0; pin < logical_block.pb_type->num_pins; pin++) { for (auto& tile : logical_block.equivalent_tiles) { - auto direct_map = tile->tile_block_pin_directs_map.at(logical_block.index); - auto result = direct_map.find(t_logical_pin(pin)); - if (result == direct_map.end()) { - archfpga_throw(__FILE__, __LINE__, - "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", - pin, tile->name, logical_block.name); + int capacity; + if (tile->capacity_type == e_capacity_type::DUPLICATE) { + capacity = 1; + } else { + VTR_ASSERT(tile->capacity_type == e_capacity_type::EXPLICIT); + capacity = tile->capacity; } - int phy_index = result->second.pin; + for (int z_index = 0; z_index < capacity; ++z_index) { + const auto& direct_map = tile->tile_block_pin_directs_map.at(logical_block.index); + auto result = direct_map.find(t_logical_pin(z_index, pin)); + if (result == direct_map.end()) { + archfpga_throw(__FILE__, __LINE__, + "Logical pin %d not present in pin mapping between Tile %s and Block %s.\n", + pin, tile->name, logical_block.name); + } - bool is_ignored = tile->is_ignored_pin[phy_index]; - bool is_global = tile->is_pin_global[phy_index]; + int phy_index = result->second.pin; - auto ignored_result = ignored_pins_check_map.insert(std::pair(pin, is_ignored)); - if (!ignored_result.second && ignored_result.first->second != is_ignored) { - archfpga_throw(__FILE__, __LINE__, - "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " - "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); - } + bool is_ignored = tile->is_ignored_pin[phy_index]; + bool is_global = tile->is_pin_global[phy_index]; - auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); - if (!global_result.second && global_result.first->second != is_global) { - archfpga_throw(__FILE__, __LINE__, - "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " - "different from the corresponding pins of the other equivalent sites\n.", - tile->name, phy_index, pin); + auto ignored_result = ignored_pins_check_map.insert(std::pair(pin, is_ignored)); + if (!ignored_result.second && ignored_result.first->second != is_ignored) { + archfpga_throw(__FILE__, __LINE__, + "Physical Tile %s has a different value for the ignored pin (physical pin: %d, logical pin: %d) " + "different from the corresponding pins of the other equivalent sites\n.", + tile->name, phy_index, pin); + } + + auto global_result = global_pins_check_map.insert(std::pair(pin, is_global)); + if (!global_result.second && global_result.first->second != is_global) { + archfpga_throw(__FILE__, __LINE__, + "Physical Tile %s has a different value for the global pin (physical pin: %d, logical pin: %d) " + "different from the corresponding pins of the other equivalent sites\n.", + tile->name, phy_index, pin); + } } } } diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 05501cc9c71..66a21ac3f18 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -79,7 +79,7 @@ void printClusteredNetlistStats() { num_blocks_type[logical_block->index]++; if (is_io_type(physical_tile)) { for (j = 0; j < logical_block->pb_type->num_pins; j++) { - int physical_pin = get_physical_pin(physical_tile, logical_block, j); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, j); auto pin_class = physical_tile->pin_class[physical_pin]; auto class_inf = physical_tile->class_inf[pin_class]; diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index ee77a8b8fff..aeafa487e82 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -95,7 +95,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi auto physical_type = pick_best_physical_type(logical_type); int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id); - int pin_index = get_physical_pin(physical_type, logical_type, log_index); + int pin_index = get_physical_pin(physical_type, /*z_index=*/0, logical_type, log_index); if (physical_type->is_ignored_pin[pin_index] != net_is_ignored && !is_io_type(physical_type)) { diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index a44ad17e6b3..c2b570740f4 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -951,7 +951,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { block_type = clb_nlist.block_type(blk_id); auto tile_type = pick_best_physical_type(block_type); for (j = 0; j < block_type->pb_type->num_pins; j++) { - int physical_pin = get_physical_pin(tile_type, block_type, j); + int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, j); //Iterate through each pin of the block, and see if there is a net allocated/used for it clb_net_id = clb_nlist.block_net(blk_id, j); @@ -1001,7 +1001,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { block_type = clb_nlist.block_type(clb_nlist.pin_block(pin_id)); auto tile_type = pick_best_physical_type(block_type); int logical_pin = clb_nlist.pin_logical_index(pin_id); - int physical_pin = get_physical_pin(tile_type, block_type, logical_pin); + int physical_pin = get_physical_pin(tile_type, /*z_index=*/0, block_type, logical_pin); if (tile_type->is_ignored_pin[physical_pin] != is_ignored_net) { VTR_LOG_WARN( diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 505928cf667..8743140e6ec 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -2666,7 +2666,7 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b continue; auto physical_tile = physical_tile_type(blk_id); - int physical_pin = get_physical_pin(physical_tile, type, k); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, type, k); iclass = physical_tile->pin_class[physical_pin]; diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index bb8a98ae5d0..257793b86ff 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -66,7 +66,7 @@ static void print_stats() { auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); auto physical_tile = pick_best_physical_type(logical_block); for (ipin = 0; ipin < logical_block->pb_type->num_pins; ipin++) { - int physical_pin = get_physical_pin(physical_tile, logical_block, ipin); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, ipin); auto pin_class = physical_tile->pin_class[physical_pin]; auto pin_class_inf = physical_tile->class_inf[pin_class]; diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index 5411e3223f8..18b89732735 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -82,7 +82,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p num_blk_pins = cluster_ctx.clb_nlist.block_type(blk_id)->pb_type->num_pins; for (to_iblk_pin = 0; to_iblk_pin < num_blk_pins; to_iblk_pin++) { - int to_physical_pin = get_physical_pin(physical_tile, logical_block, to_iblk_pin); + int to_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, to_iblk_pin); to_net_id = cluster_ctx.clb_nlist.block_net(blk_id, to_iblk_pin); to_idirect = f_idirect_from_blk_pin[physical_tile->index][to_physical_pin]; @@ -102,7 +102,7 @@ static void find_all_the_macro(int* num_of_macro, std::vector& p || (is_constant_clb_net(to_net_id) && !net_is_driven_by_direct(to_net_id)))) { for (from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { - int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); + int from_physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, from_iblk_pin); from_net_id = cluster_ctx.clb_nlist.block_net(blk_id, from_iblk_pin); from_idirect = f_idirect_from_blk_pin[physical_tile->index][from_physical_pin]; diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index e19d1720915..4e5ac918fd0 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -319,7 +319,7 @@ std::vector find_clb_pin_connected_atom_pins(ClusterBlockId clb, int auto logical_block = clb_nlist.block_type(clb); auto physical_tile = pick_best_physical_type(logical_block); - int physical_pin = get_physical_pin(physical_tile, logical_block, logical_pin); + int physical_pin = get_physical_pin(physical_tile, /*z_index=*/0, logical_block, logical_pin); if (is_opin(physical_pin, physical_tile)) { //output @@ -2059,14 +2059,11 @@ void place_sync_external_block_connections(ClusterBlockId iblk) { auto logical_block = clb_nlist.block_type(iblk); VTR_ASSERT(physical_tile->num_pins % physical_tile->capacity == 0); - int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity; - /* Logical location and physical location is offset by z * max_num_block_pins */ - for (auto pin : clb_nlist.block_pins(iblk)) { int logical_pin_index = clb_nlist.pin_logical_index(pin); - int physical_pin_index = get_physical_pin(physical_tile, logical_block, logical_pin_index); - - int new_physical_pin_index = physical_pin_index + place_ctx.block_locs[iblk].loc.z * max_num_block_pins; + int new_physical_pin_index = get_physical_pin( + physical_tile, place_ctx.block_locs[iblk].loc.z, + logical_block, logical_pin_index); auto result = place_ctx.physical_pins.find(pin); if (result != place_ctx.physical_pins.end()) { @@ -2128,32 +2125,34 @@ t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk) { } } -int get_logical_pin(t_physical_tile_type_ptr physical_tile, - t_logical_block_type_ptr logical_block, - int pin) { - t_physical_pin physical_pin(pin); - - auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); - auto result = direct_map.find(physical_pin); +int get_physical_pin(const ClusterBlockId blk, + t_logical_block_type_ptr logical_block, + int pin) { + auto& place_ctx = g_vpr_ctx.placement(); + auto& device_ctx = g_vpr_ctx.device(); - if (result == direct_map.inverse_end()) { - VTR_LOG_WARN( - "Couldn't find the corresponding logical pin of the physical pin %d." - "Physical Tile: %s, Logical Block: %s.\n", - pin, physical_tile->name, logical_block->name); - return OPEN; - } + auto block_loc = place_ctx.block_locs[blk]; + auto loc = block_loc.loc; - return result->second.pin; + return get_physical_pin( + device_ctx.grid[loc.x][loc.y].type, + loc.z, + logical_block, + pin); } int get_physical_pin(t_physical_tile_type_ptr physical_tile, + int z_index, t_logical_block_type_ptr logical_block, int pin) { - t_logical_pin logical_pin(pin); - - auto direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); - auto result = direct_map.find(logical_pin); + const auto& direct_map = physical_tile->tile_block_pin_directs_map.at(logical_block->index); + auto result = direct_map.begin(); + if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) { + result = direct_map.find(t_logical_pin(/*z_index=*/0, pin)); + } else { + VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT); + result = direct_map.find(t_logical_pin(z_index, pin)); + } if (result == direct_map.end()) { VTR_LOG_WARN( @@ -2163,7 +2162,15 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, return OPEN; } - return result->second.pin; + int physical_pin_index = result->second.pin; + if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) { + int max_num_block_pins = physical_tile->num_pins / physical_tile->capacity; + /* Logical location and physical location is offset by z * max_num_block_pins */ + return physical_pin_index + z_index * max_num_block_pins; + } else { + VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT); + return physical_pin_index; + } } int net_pin_to_tile_pin_index(const ClusterNetId net_id, int net_pin_index) { diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index e43cc91dacd..1d8e24fbf7c 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -165,10 +165,11 @@ t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physica //the best expected physical tile the block should use (if no valid placement). t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk); -int get_logical_pin(t_physical_tile_type_ptr physical_tile, - t_logical_block_type_ptr logical_block, - int pin); int get_physical_pin(t_physical_tile_type_ptr physical_tile, + int z_index, + t_logical_block_type_ptr logical_block, + int pin); +int get_physical_pin(const ClusterBlockId blk, t_logical_block_type_ptr logical_block, int pin); From 3096297d390f47473fe68e461937a0de748b9baa Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 12 Dec 2019 13:51:55 -0800 Subject: [PATCH 024/107] Fix bugs in reading explicit pin definitions. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- libs/libarchfpga/src/read_xml_arch_file.cpp | 35 +++++++++++++++------ 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index edadfd5e62e..40b0195673d 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -816,6 +816,14 @@ static void LoadPinLoc(pugi::xml_node Locations, VTR_ASSERT(ipin == output_pins.size()); } else { + int capacity; + if (type->capacity_type == e_capacity_type::DUPLICATE) { + capacity = type->capacity; + } else { + VTR_ASSERT(type->capacity_type == e_capacity_type::EXPLICIT); + capacity = 1; + } + VTR_ASSERT(type->pin_location_distribution == E_CUSTOM_PIN_DISTR); for (int width = 0; width < type->width; ++width) { for (int height = 0; height < type->height; ++height) { @@ -836,12 +844,12 @@ static void LoadPinLoc(pugi::xml_node Locations, } for (int pin_num = pin_range.first; pin_num < pin_range.second; ++pin_num) { - VTR_ASSERT(pin_num < type->num_pins / type->capacity); - for (int capacity = 0; capacity < type->capacity; ++capacity) { - type->pinloc[width][height][side][pin_num + capacity * type->num_pins / type->capacity] = true; - type->pin_width_offset[pin_num + capacity * type->num_pins / type->capacity] += width; - type->pin_height_offset[pin_num + capacity * type->num_pins / type->capacity] += height; - physical_pin_counts[pin_num + capacity * type->num_pins / type->capacity] += 1; + VTR_ASSERT(pin_num < type->num_pins / capacity); + for (int icapacity = 0; icapacity < capacity; ++icapacity) { + type->pinloc[width][height][side][pin_num + icapacity * type->num_pins / capacity] = true; + type->pin_width_offset[pin_num + icapacity * type->num_pins / capacity] += width; + type->pin_height_offset[pin_num + icapacity * type->num_pins / capacity] += height; + physical_pin_counts[pin_num + icapacity * type->num_pins / capacity] += 1; } } } @@ -891,6 +899,8 @@ static std::pair> ProcessPinString(pugi::xml_node Locat pin_loc_string); } + instance_idx = vtr::atoi(token.data); + token_index++; token = tokens[token_index]; @@ -903,7 +913,6 @@ static std::pair> ProcessPinString(pugi::xml_node Locat token_index++; token = tokens[token_index]; - instance_idx = vtr::atoi(token.data); } if (token.type != TOKEN_DOT) { @@ -3331,7 +3340,7 @@ static void ProcessEquivalentSiteDirectConnection(pugi::xml_node Parent, "Pin definition differ between site %s and tile %s. User-defined pin mapping is required.\n", LogicalBlockType->pb_type->name, PhysicalTileType->name); } - if (PhysicalTileType->capacity_type == e_capacity_type::EXPLICIT) { + if (PhysicalTileType->capacity_type != e_capacity_type::DUPLICATE) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(Parent), "Custom site pins are required if capacity_type == explicit\n"); } @@ -5017,7 +5026,15 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t auto& pin_direct_mapping = physical_tile->tile_block_pin_directs_map.at(logical_block->index); - if (pb_type->num_pins != (int)pin_direct_mapping.size()) { + int capacity; + if (physical_tile->capacity_type == e_capacity_type::DUPLICATE) { + capacity = 1; + } else { + VTR_ASSERT(physical_tile->capacity_type == e_capacity_type::EXPLICIT); + capacity = physical_tile->capacity; + } + + if (pb_type->num_pins * capacity != (int)pin_direct_mapping.size()) { archfpga_throw(__FILE__, __LINE__, "Logical block (%s) and Physical tile (%s) have a different number of ports.\n", logical_block->name, physical_tile->name); From 74bdc5fe981deeaf344ebf20173befea82336c9c Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 13 Dec 2019 11:07:26 -0800 Subject: [PATCH 025/107] Finish initial implementation of explicit port definitions. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- libs/libarchfpga/src/physical_types.cpp | 7 ++- libs/libarchfpga/src/read_xml_arch_file.cpp | 1 - vpr/src/base/read_route.cpp | 60 +++++++++++++++++++-- vpr/src/base/vpr_context.h | 1 + vpr/src/route/route_common.cpp | 36 ++++++++++--- vpr/src/util/vpr_utils.cpp | 34 +++++++----- 6 files changed, 113 insertions(+), 26 deletions(-) diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index f604e291657..28deac94516 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -110,7 +110,12 @@ std::vector t_physical_tile_type::get_clock_pins_indices() const { int clock_pins_start_idx = 0; int clock_pins_stop_idx = 0; - for (int capacity_num = 0; capacity_num < this->capacity; capacity_num++) { + int num_capacity = 1; + if (capacity_type == e_capacity_type::DUPLICATE) { + num_capacity = this->capacity; + } + + for (int capacity_num = 0; capacity_num < num_capacity; capacity_num++) { // Ranges are picked on the basis that pins are ordered: inputs, outputs, then clock pins // This is because ProcessPb_type assigns pb_type port indices in that order and // SetupPinLocationsAndPinClasses assigns t_logical_block_type_ptr pin indices in the order of port indices diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 40b0195673d..bba80f64fda 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -912,7 +912,6 @@ static std::pair> ProcessPinString(pugi::xml_node Locat token_index++; token = tokens[token_index]; - } if (token.type != TOKEN_DOT) { diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index 9ec4069fe2c..6d4dd1142ed 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -23,6 +23,7 @@ #include "rr_graph.h" #include "vtr_assert.h" #include "vtr_util.h" +#include "vtr_time.h" #include "tatum/echo_writer.hpp" #include "vtr_log.h" #include "check_route.h" @@ -40,6 +41,7 @@ #include "echo_files.h" #include "route_common.h" #include "read_route.h" +#include "rr_graph2.h" /*************Functions local to this module*************/ static void process_route(std::ifstream& fp, const char* filename, int& lineno); @@ -192,7 +194,7 @@ static void process_nets(std::ifstream& fp, ClusterNetId inet, std::string name, static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* filename, int& lineno) { /* Not a global net. Goes through every node and add it into trace.head*/ - auto& cluster_ctx = g_vpr_ctx.mutable_clustering(); + auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.mutable_device(); auto& route_ctx = g_vpr_ctx.mutable_routing(); auto& place_ctx = g_vpr_ctx.placement(); @@ -206,6 +208,45 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file std::string input; std::vector tokens; + // Build lookup from SOURCE/SINK node to ClusterBlockId. + std::unordered_map node_to_block; + + { + vtr::ScopedStartFinishTimer timer("Building ClusterBlockId lookup"); + + for (auto net_id : cluster_ctx.clb_nlist.nets()) { + int pin_count = 0; + for (auto pin_id : cluster_ctx.clb_nlist.net_pins(net_id)) { + auto block_id = cluster_ctx.clb_nlist.pin_block(pin_id); + + const auto* logical_tile = cluster_ctx.clb_nlist.block_type(block_id); + const auto* physical_tile = physical_tile_type(block_id); + VTR_ASSERT(block_id); + int i = place_ctx.block_locs[block_id].loc.x; + int j = place_ctx.block_locs[block_id].loc.y; + + int logical_pin_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id); + int physical_pin_index = get_physical_pin( + physical_tile, place_ctx.block_locs[block_id].loc.z, + logical_tile, logical_pin_index); + int physical_pin_class = physical_tile->pin_class[physical_pin_index]; + int class_inode = get_rr_node_index(device_ctx.rr_node_indices, + i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */ + physical_pin_class); + + auto result = node_to_block.insert(std::make_pair(class_inode, block_id)); + if (!result.second && result.first->second != block_id) { + vpr_throw(VPR_ERROR_ROUTE, filename, lineno, + "Clustered netlist has inconsistent rr node mapping, class rr node %d has two block ids %zu and %zu?", + class_inode, (size_t)block_id, result.first->second); + } + pin_count++; + } + } + + VTR_LOG("ClusterBlockId lookup has %zu entries\n", node_to_block.size()); + } + /*Walk through every line that begins with Node:*/ while (std::getline(fp, input)) { ++lineno; @@ -285,9 +326,22 @@ static void process_nodes(std::ifstream& fp, ClusterNetId inet, const char* file if (tokens[6 + offset] != "Switch:") { /*This is an opin or ipin, process its pin nums*/ if (!is_io_type(device_ctx.grid[x][y].type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) { + // Convert this IPIN/OPIN back to class. + auto rr_type = device_ctx.rr_nodes[inode].type(); + VTR_ASSERT(rr_type == IPIN || rr_type == OPIN); int pin_num = device_ctx.rr_nodes[inode].ptc_num(); - int height_offset = device_ctx.grid[x][y].height_offset; - ClusterBlockId iblock = place_ctx.grid_blocks[x][y - height_offset].blocks[0]; + int iclass = device_ctx.grid[x][y].type->pin_class[pin_num]; + int class_inode = get_rr_node_index(device_ctx.rr_node_indices, + x, y, (rr_type == OPIN ? SOURCE : SINK), iclass); + + auto itr = node_to_block.find(class_inode); + if (itr == node_to_block.end()) { + vpr_throw(VPR_ERROR_ROUTE, filename, lineno, + "Class RR node %d does not have an associated ClusterBlockId?", class_inode); + } + + ClusterBlockId iblock = itr->second; + VTR_ASSERT(iblock); t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num); t_pb_type* pb_type = pb_pin->parent_node->pb_type; diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index b6a1f9859da..6419fe8fee3 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -282,6 +282,7 @@ struct RoutingContext : public Context { vtr::vector> trace_nodes; vtr::vector> net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ + std::unordered_map rr_net_map; vtr::vector> rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */ diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 6204dad984b..78c541071e7 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -96,7 +96,8 @@ static t_trace_branch traceback_branch(int node, std::unordered_set& main_b static std::pair add_trace_non_configurable(t_trace* head, t_trace* tail, int node, std::unordered_set& visited); static std::pair add_trace_non_configurable_recurr(int node, std::unordered_set& visited, int depth = 0); -static vtr::vector> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices); +static vtr::vector> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices, + std::unordered_map* rr_net_map); static vtr::vector> load_rr_clb_sources(const t_rr_node_indices& L_rr_node_indices); static t_clb_opins_used alloc_and_load_clb_opins_used_locally(); @@ -496,7 +497,7 @@ void init_route_structs(int bb_factor) { init_heap(device_ctx.grid); //Various look-ups - route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices); + route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices, &route_ctx.rr_net_map); route_ctx.route_bb = load_route_bb(bb_factor); route_ctx.rr_blk_source = load_rr_clb_sources(device_ctx.rr_node_indices); route_ctx.clb_opins_used_locally = alloc_and_load_clb_opins_used_locally(); @@ -1031,7 +1032,11 @@ void reset_rr_node_route_structs() { /* Allocates and loads the route_ctx.net_rr_terminals data structure. For each net it stores the rr_node * * index of the SOURCE of the net and all the SINKs of the net [clb_nlist.nets()][clb_nlist.net_pins()]. * * Entry [inet][pnum] stores the rr index corresponding to the SOURCE (opin) or SINK (ipin) of the pin. */ -static vtr::vector> load_net_rr_terminals(const t_rr_node_indices& L_rr_node_indices) { +static vtr::vector> load_net_rr_terminals( + const t_rr_node_indices& L_rr_node_indices, + std::unordered_map* rr_net_map) { + VTR_ASSERT(rr_net_map != nullptr); + rr_net_map->clear(); vtr::vector> net_rr_terminals; auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -1061,6 +1066,16 @@ static vtr::vector> load_net_rr_terminals(const t int inode = get_rr_node_index(L_rr_node_indices, i, j, (pin_count == 0 ? SOURCE : SINK), /* First pin is driver */ iclass); net_rr_terminals[net_id][pin_count] = inode; + + auto result = rr_net_map->insert(std::make_pair(inode, block_id)); + // If the map already contains an entry for inode, make sure it + // is consistent with the existing entry. + if (!result.second && block_id != result.first->second) { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, + "Clustered netlist has inconsistent rr node mapping, class rr node %d has two block ids %zu and %zu?", + inode, (size_t)block_id, (size_t)result.first->second); + } + pin_count++; } } @@ -1513,11 +1528,18 @@ void print_route(FILE* fp, const vtr::vector& traceba fprintf(fp, "%d ", device_ctx.rr_nodes[inode].ptc_num()); if (!is_io_type(device_ctx.grid[ilow][jlow].type) && (rr_type == IPIN || rr_type == OPIN)) { + // Go from IPIN/OPIN to SOURCE/SINK + auto* type = device_ctx.grid[ilow][jlow].type; int pin_num = device_ctx.rr_nodes[inode].ptc_num(); - int xoffset = device_ctx.grid[ilow][jlow].width_offset; - int yoffset = device_ctx.grid[ilow][jlow].height_offset; - ClusterBlockId iblock = place_ctx.grid_blocks[ilow - xoffset][jlow - yoffset].blocks[0]; - VTR_ASSERT(iblock); + int iclass = type->pin_class[pin_num]; + int class_inode = get_rr_node_index(device_ctx.rr_node_indices, + ilow, jlow, (rr_type == OPIN ? SOURCE : SINK), iclass); + + // Use the rr_net_map to go from class inode back to ClusterBlockId. + auto itr = route_ctx.rr_net_map.find(class_inode); + VTR_ASSERT(itr != route_ctx.rr_net_map.end()); + ClusterBlockId iblock = itr->second; + t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(iblock, pin_num); t_pb_type* pb_type = pb_pin->parent_node->pb_type; fprintf(fp, " %s.%s[%d] ", pb_type->name, pb_pin->port->name, pb_pin->pin_number); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 4e5ac918fd0..fed1feae89a 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -192,15 +192,21 @@ std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_ std::string pin_name = type->name; - if (type->capacity > 1) { - int pins_per_inst = type->num_pins / type->capacity; - int inst_num = pin_index / pins_per_inst; - pin_index %= pins_per_inst; + if (type->capacity_type == e_capacity_type::DUPLICATE) { + if (type->capacity > 1) { + int pins_per_inst = type->num_pins / type->capacity; + int inst_num = pin_index / pins_per_inst; + pin_index %= pins_per_inst; - pin_name += "[" + std::to_string(inst_num) + "]"; - } + pin_name += "[" + std::to_string(inst_num) + "]"; + } - pin_name += "."; + pin_name += "."; + } else { + VTR_ASSERT(type->capacity_type == e_capacity_type::EXPLICIT); + VTR_ASSERT(pin_index < type->num_pins); + pin_name += "."; + } int curr_index = 0; for (auto const& port : type->ports) { @@ -2058,18 +2064,18 @@ void place_sync_external_block_connections(ClusterBlockId iblk) { auto physical_tile = physical_tile_type(iblk); auto logical_block = clb_nlist.block_type(iblk); - VTR_ASSERT(physical_tile->num_pins % physical_tile->capacity == 0); for (auto pin : clb_nlist.block_pins(iblk)) { int logical_pin_index = clb_nlist.pin_logical_index(pin); - int new_physical_pin_index = get_physical_pin( + + int new_physical_pin = get_physical_pin( physical_tile, place_ctx.block_locs[iblk].loc.z, logical_block, logical_pin_index); - - auto result = place_ctx.physical_pins.find(pin); - if (result != place_ctx.physical_pins.end()) { - place_ctx.physical_pins[pin] = new_physical_pin_index; + auto iter = place_ctx.physical_pins.find(pin); + if (iter != place_ctx.physical_pins.end()) { + *iter = new_physical_pin; } else { - place_ctx.physical_pins.insert(pin, new_physical_pin_index); + place_ctx.physical_pins.insert( + pin, new_physical_pin); } } } From 2107b7f6d48dc88f7888183f117a05f80f38262e Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 8 Oct 2018 19:35:29 -0700 Subject: [PATCH 026/107] Avoid criticality issue. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> Signed-off-by: Alessandro Comodi --- vpr/src/timing/timing_util.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/timing/timing_util.cpp b/vpr/src/timing/timing_util.cpp index 0117ea5fc49..79afcfd67ed 100644 --- a/vpr/src/timing/timing_util.cpp +++ b/vpr/src/timing/timing_util.cpp @@ -571,6 +571,10 @@ float calc_relaxed_criticality(const std::map& domains_max_re max_req += shift; } + if (!std::isfinite(slack)) { + continue; + } + float crit = std::numeric_limits::quiet_NaN(); if (max_req > 0.) { //Standard case From 652e8cf2de80c830aa852f55531796d255244887 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 13 Dec 2019 14:11:40 -0800 Subject: [PATCH 027/107] Run make format. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/route_timing.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index cc738162be4..4136c7d7b65 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -1628,7 +1628,7 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, target_node, router_stats); } else { - //Post-heap prune, do not re-explore from the current/new partial path as it + //Post-heap prune, do not re-explore from the current/new partial path as it //has worse cost than the best partial path to this node found so far VTR_LOGV_DEBUG(f_router_debug, " Worse cost to %d\n", inode); VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", best_total_cost); From ecc22f2685a88e7914f53b6a5423a1b86eeb95a8 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 8 Oct 2018 19:35:29 -0700 Subject: [PATCH 028/107] Avoid criticality issue. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> Signed-off-by: Alessandro Comodi --- vpr/src/timing/timing_util.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/vpr/src/timing/timing_util.cpp b/vpr/src/timing/timing_util.cpp index 0117ea5fc49..79afcfd67ed 100644 --- a/vpr/src/timing/timing_util.cpp +++ b/vpr/src/timing/timing_util.cpp @@ -571,6 +571,10 @@ float calc_relaxed_criticality(const std::map& domains_max_re max_req += shift; } + if (!std::isfinite(slack)) { + continue; + } + float crit = std::numeric_limits::quiet_NaN(); if (max_req > 0.) { //Standard case From e6fae2e59708b362a57b032ae38b9b53187b1e05 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Tue, 7 May 2019 17:29:52 +0200 Subject: [PATCH 029/107] vpr options: added option to disable check_route Signed-off-by: Alessandro Comodi --- vpr/src/base/SetupVPR.cpp | 2 +- vpr/src/base/read_options.cpp | 5 +++++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 4 +++- vpr/src/base/vpr_types.h | 1 + 5 files changed, 11 insertions(+), 2 deletions(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 4fd21004eb5..a05f45cf21a 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -371,11 +371,11 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->max_convergence_count = Options.router_max_convergence_count; RouterOpts->reconvergence_cpd_threshold = Options.router_reconvergence_cpd_threshold; RouterOpts->first_iteration_timing_report_file = Options.router_first_iteration_timing_report_file; - RouterOpts->strict_checks = Options.strict_checks; RouterOpts->write_router_lookahead = Options.write_router_lookahead; RouterOpts->read_router_lookahead = Options.read_router_lookahead; + RouterOpts->disable_check_route = Options.disable_check_route; } static void SetupAnnealSched(const t_options& Options, diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 5f654445efd..962ff4cf913 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1620,6 +1620,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.disable_check_route, "--disable_check_route") + .help("Disables check_route once routing step has finished or when routing file is loaded") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.router_debug_net, "--router_debug_net") .help( "Controls when router debugging is enabled.\n" diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 97d320abbe3..12f3f1e959a 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -133,6 +133,7 @@ struct t_options { argparse::ArgValue verify_binary_search; argparse::ArgValue RouterAlgorithm; argparse::ArgValue min_incremental_reroute_fanout; + argparse::ArgValue disable_check_route; /* Timing-driven router options only */ argparse::ArgValue astar_fac; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index f2900d0d299..1fd99c1aa4a 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -688,7 +688,9 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { std::string graphics_msg; if (route_status.success()) { //Sanity check the routing - check_route(router_opts.route_type); + if (!router_opts.disable_check_route) { + check_route(router_opts.route_type); + } get_serial_num(); //Update status diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index e6c010f7398..230e2569450 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -949,6 +949,7 @@ struct t_router_opts { std::string write_router_lookahead; std::string read_router_lookahead; + bool disable_check_route; }; struct t_analysis_opts { From 8fa2b4939f89f19ca642b7a28f65b6d65da60a43 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 2 Dec 2019 11:38:52 -0800 Subject: [PATCH 030/107] Enable faster rr graph reading - Add option to disable checking the rr graph. This check is relatively expensive (~12 seconds), and generates MB's of warnings that we ignore. - Disable loading edge metadata when running normal VPR flows. - Avoid copying rr node side string. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- utils/fasm/src/main.cpp | 1 + vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/place_and_route.cpp | 4 ++- vpr/src/base/read_options.cpp | 5 +++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 4 ++- vpr/src/base/vpr_types.h | 2 ++ vpr/src/route/route_common.cpp | 8 +++-- vpr/src/route/router_delay_profiling.cpp | 4 ++- vpr/src/route/rr_graph.cpp | 8 +++-- vpr/src/route/rr_graph.h | 4 ++- vpr/src/route/rr_graph_reader.cpp | 42 ++++++++++++++---------- vpr/src/route/rr_graph_reader.h | 4 ++- 13 files changed, 61 insertions(+), 27 deletions(-) diff --git a/utils/fasm/src/main.cpp b/utils/fasm/src/main.cpp index dae4edf9994..58cc2227cc5 100644 --- a/utils/fasm/src/main.cpp +++ b/utils/fasm/src/main.cpp @@ -72,6 +72,7 @@ int main(int argc, const char **argv) { vpr_setup.PackerOpts.doPacking = STAGE_LOAD; vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD; vpr_setup.RouterOpts.doRouting = STAGE_LOAD; + vpr_setup.RouterOpts.read_edge_metadata = true; vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP; bool flow_succeeded = false; diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 4fd21004eb5..358b807c21b 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -322,6 +322,7 @@ static void SetupRoutingArch(const t_arch& Arch, } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { + RouterOpts->do_check_rr_graph = !Options.disable_check_rr_graph; RouterOpts->astar_fac = Options.astar_fac; RouterOpts->bb_factor = Options.bb_factor; RouterOpts->criticality_exp = Options.criticality_exp; diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 0f47ebebb37..abd197f320d 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -357,7 +357,9 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref, router_opts.trim_obs_channels, router_opts.clock_modeling, arch->Directs, arch->num_directs, - &warnings); + &warnings, + router_opts.read_edge_metadata, + router_opts.do_check_rr_graph); init_draw_coords(final); restore_routing(best_routing, route_ctx.clb_opins_used_locally, saved_clb_opins_used_locally); diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 5f654445efd..e7af61e75f5 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1642,6 +1642,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("-2") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.disable_check_rr_graph, "--disable_check_rr_graph") + .help("Disables checking rr graph when reading from disk.") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + auto& analysis_grp = parser.add_argument_group("analysis options"); analysis_grp.add_argument(args.full_stats, "--full_stats") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 97d320abbe3..adf7c3fd205 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -119,6 +119,7 @@ struct t_options { argparse::ArgValue allowed_tiles_for_delay_model; /* Router Options */ + argparse::ArgValue disable_check_rr_graph; argparse::ArgValue max_router_iterations; argparse::ArgValue first_iter_pres_fac; argparse::ArgValue initial_pres_fac; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index f2900d0d299..0bdb05ca77f 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -849,7 +849,9 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi router_opts.trim_obs_channels, router_opts.clock_modeling, arch.Directs, arch.num_directs, - &warnings); + &warnings, + router_opts.read_edge_metadata, + router_opts.do_check_rr_graph); //Initialize drawing, now that we have an RR graph init_draw_coords(chan_width_fac); } diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index e6c010f7398..c280cdb97f9 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -905,6 +905,8 @@ enum class e_incr_reroute_delay_ripup { constexpr int NO_FIXED_CHANNEL_WIDTH = -1; struct t_router_opts { + bool read_edge_metadata = false; + bool do_check_rr_graph = true; float first_iter_pres_fac; float initial_pres_fac; float pres_fac_mult; diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 6204dad984b..56a17de513c 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -238,7 +238,9 @@ void try_graph(int width_fac, const t_router_opts& router_opts, t_det_routing_ar router_opts.trim_obs_channels, router_opts.clock_modeling, directs, num_directs, - &warning_count); + &warning_count, + router_opts.read_edge_metadata, + router_opts.do_check_rr_graph); } bool try_route(int width_fac, @@ -288,7 +290,9 @@ bool try_route(int width_fac, router_opts.trim_obs_channels, router_opts.clock_modeling, directs, num_directs, - &warning_count); + &warning_count, + router_opts.read_edge_metadata, + router_opts.do_check_rr_graph); //Initialize drawing, now that we have an RR graph init_draw_coords(width_fac); diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index ab0343e4380..59352d966ef 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -197,7 +197,9 @@ void alloc_routing_structs(t_chan_width chan_width, router_opts.trim_obs_channels, router_opts.clock_modeling, directs, num_directs, - &warnings); + &warnings, + router_opts.read_edge_metadata, + router_opts.do_check_rr_graph); alloc_and_load_rr_node_route_structs(); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index df1bb8b0967..31f7c70a56e 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -318,7 +318,9 @@ void create_rr_graph(const t_graph_type graph_type, const enum e_clock_modeling clock_modeling, const t_direct_inf* directs, const int num_directs, - int* Warnings) { + int* Warnings, + bool read_edge_metadata, + bool do_check_rr_graph) { const auto& device_ctx = g_vpr_ctx.device(); if (!det_routing_arch->read_rr_graph_filename.empty()) { @@ -330,7 +332,9 @@ void create_rr_graph(const t_graph_type graph_type, segment_inf, base_cost_type, &det_routing_arch->wire_to_rr_ipin_switch, - det_routing_arch->read_rr_graph_filename.c_str()); + det_routing_arch->read_rr_graph_filename.c_str(), + read_edge_metadata, + do_check_rr_graph); } } else { if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_nodes.empty()) { diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index f55a64f7f9f..afa02a1c9d6 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -38,7 +38,9 @@ void create_rr_graph(const t_graph_type graph_type, const enum e_clock_modeling clock_modeling, const t_direct_inf* directs, const int num_directs, - int* Warnings); + int* Warnings, + bool read_edge_metadata, + bool do_check_rr_graph); void free_rr_graph(); diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index e9380b12d7e..5baa2c4031c 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -53,7 +53,7 @@ void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid); void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); -void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches); +void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata); void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_rr_node_indices(const DeviceGrid& grid); void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data); @@ -69,7 +69,9 @@ void load_rr_file(const t_graph_type graph_type, const std::vector& segment_inf, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, - const char* read_rr_graph_name) { + const char* read_rr_graph_name, + bool read_edge_metadata, + bool do_check_rr_graph) { vtr::ScopedStartFinishTimer timer("Loading routing resource graph"); const char* Prop; @@ -154,7 +156,7 @@ void load_rr_file(const t_graph_type graph_type, process_switches(next_component, loc_data); next_component = get_single_child(rr_graph, "rr_edges", loc_data); - process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches); + process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches, read_edge_metadata); //Partition the rr graph edges for efficient access to configurable/non-configurable //edge subsets. Must be done after RR switches have been allocated @@ -176,7 +178,9 @@ void load_rr_file(const t_graph_type graph_type, device_ctx.chan_width = nodes_per_chan; device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); - check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); + if (do_check_rr_graph) { + check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); + } } catch (pugiutil::XmlError& e) { vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what()); @@ -336,15 +340,15 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { if (node.type() == IPIN || node.type() == OPIN) { e_side side; - std::string side_str = get_attribute(locSubnode, "side", loc_data).as_string(); - if (side_str == "LEFT") { + const char* side_str = get_attribute(locSubnode, "side", loc_data).as_string(); + if (strcmp(side_str, "LEFT") == 0) { side = LEFT; - } else if (side_str == "RIGHT") { + } else if (strcmp(side_str, "RIGHT") == 0) { side = RIGHT; - } else if (side_str == "TOP") { + } else if (strcmp(side_str, "TOP") == 0) { side = TOP; } else { - VTR_ASSERT(side_str == "BOTTOM"); + VTR_ASSERT(strcmp(side_str, "BOTTOM") == 0); side = BOTTOM; } node.set_side(side); @@ -388,7 +392,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { /*Loads the edges information from file into vpr. Nodes and switches must be loaded * before calling this function*/ -void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches) { +void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata) { auto& device_ctx = g_vpr_ctx.mutable_device(); pugi::xml_node edges; @@ -462,16 +466,18 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in device_ctx.rr_nodes[source_node].set_edge_switch(num_edges_for_node[source_node], switch_id); // Read the metadata for the edge - auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL); - if (metadata) { - auto edges_meta = get_first_child(metadata, "meta", loc_data); - while (edges_meta) { - auto key = get_attribute(edges_meta, "name", loc_data).as_string(); + if (read_edge_metadata) { + auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL); + if (metadata) { + auto edges_meta = get_first_child(metadata, "meta", loc_data); + while (edges_meta) { + auto key = get_attribute(edges_meta, "name", loc_data).as_string(); - vpr::add_rr_edge_metadata(source_node, sink_node, switch_id, - key, edges_meta.child_value()); + vpr::add_rr_edge_metadata(source_node, sink_node, switch_id, + key, edges_meta.child_value()); - edges_meta = edges_meta.next_sibling(edges_meta.name()); + edges_meta = edges_meta.next_sibling(edges_meta.name()); + } } } num_edges_for_node[source_node]++; diff --git a/vpr/src/route/rr_graph_reader.h b/vpr/src/route/rr_graph_reader.h index 83a5f1100b2..0b7a67392b8 100644 --- a/vpr/src/route/rr_graph_reader.h +++ b/vpr/src/route/rr_graph_reader.h @@ -9,6 +9,8 @@ void load_rr_file(const t_graph_type graph_type, const std::vector& segment_inf, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, - const char* read_rr_graph_name); + const char* read_rr_graph_name, + bool read_edge_metadata, + bool do_check_rr_graph); #endif /* RR_GRAPH_READER_H */ From e8fd53abfe4b9078b8208a3cb8b8520e8e578ec6 Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Thu, 12 Dec 2019 16:12:05 -0800 Subject: [PATCH 031/107] add --quick_check_route, disables slow non-configurable edge check Signed-off-by: Dustin DeWeese --- vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/read_options.cpp | 5 +++++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 2 +- vpr/src/base/vpr_types.h | 1 + vpr/src/route/check_route.cpp | 29 ++++++++++++++++++++++++----- vpr/src/route/check_route.h | 2 +- 7 files changed, 34 insertions(+), 7 deletions(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index a05f45cf21a..d189c8d4da5 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -376,6 +376,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->write_router_lookahead = Options.write_router_lookahead; RouterOpts->read_router_lookahead = Options.read_router_lookahead; RouterOpts->disable_check_route = Options.disable_check_route; + RouterOpts->quick_check_route = Options.quick_check_route; } static void SetupAnnealSched(const t_options& Options, diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 962ff4cf913..721c7ebc279 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1625,6 +1625,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("off") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.quick_check_route, "--quick_check_route") + .help("Runs check_route, disabling slow checks, once routing step has finished or when routing file is loaded") + .default_value("off") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.router_debug_net, "--router_debug_net") .help( "Controls when router debugging is enabled.\n" diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 12f3f1e959a..46825e55d86 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -134,6 +134,7 @@ struct t_options { argparse::ArgValue RouterAlgorithm; argparse::ArgValue min_incremental_reroute_fanout; argparse::ArgValue disable_check_route; + argparse::ArgValue quick_check_route; /* Timing-driven router options only */ argparse::ArgValue astar_fac; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 1fd99c1aa4a..3f67f3e9ad7 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -689,7 +689,7 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { if (route_status.success()) { //Sanity check the routing if (!router_opts.disable_check_route) { - check_route(router_opts.route_type); + check_route(router_opts.route_type, router_opts.quick_check_route); } get_serial_num(); diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 230e2569450..2563a8b5a8e 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -950,6 +950,7 @@ struct t_router_opts { std::string write_router_lookahead; std::string read_router_lookahead; bool disable_check_route; + bool quick_check_route; }; struct t_analysis_opts { diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index e9fa206736d..fa69b991e0a 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -27,12 +27,13 @@ static void reset_flags(ClusterNetId inet, bool* connected_to_route); static void check_locally_used_clb_opins(const t_clb_opins_used& clb_opins_used_locally, enum e_route_type route_type); +static void check_all_non_configurable_edges(); static bool check_non_configurable_edges(ClusterNetId net, const t_non_configurable_rr_sets& non_configurable_rr_sets); static void check_net_for_stubs(ClusterNetId net); /************************ Subroutine definitions ****************************/ -void check_route(enum e_route_type route_type) { +void check_route(enum e_route_type route_type, bool quick) { /* This routine checks that a routing: (1) Describes a properly * * connected path for each net, (2) this path connects all the * * pins spanned by that net, and (3) that no routing resources are * @@ -68,8 +69,6 @@ void check_route(enum e_route_type route_type) { check_locally_used_clb_opins(route_ctx.clb_opins_used_locally, route_type); - auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); - connected_to_route = (bool*)vtr::calloc(device_ctx.rr_nodes.size(), sizeof(bool)); max_pins = 0; @@ -156,8 +155,6 @@ void check_route(enum e_route_type route_type) { } } - check_non_configurable_edges(net_id, non_configurable_rr_sets); - check_net_for_stubs(net_id); reset_flags(net_id, connected_to_route); @@ -166,6 +163,11 @@ void check_route(enum e_route_type route_type) { free(pin_done); free(connected_to_route); + + if (!quick) { + check_all_non_configurable_edges(); + } + VTR_LOG("Completed routing consistency check successfully.\n"); VTR_LOG("\n"); } @@ -625,6 +627,23 @@ static void check_node_and_range(int inode, enum e_route_type route_type) { check_rr_node(inode, route_type, device_ctx); } +//Checks that all non-configurable edges are in a legal configuration +//This check is slow, so it has been moved out of check_route() +static void check_all_non_configurable_edges() { + VTR_LOG("\n"); + VTR_LOG("Checking to ensure non-configurable edges are legal...\n"); + + auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); + + auto& cluster_ctx = g_vpr_ctx.clustering(); + for (auto net_id : cluster_ctx.clb_nlist.nets()) { + check_non_configurable_edges(net_id, non_configurable_rr_sets); + } + + VTR_LOG("Completed non-configurable edge check successfully.\n"); + VTR_LOG("\n"); +} + //Checks that the specified routing is legal with respect to non-configurable edges // //For routing to be legal if *any* non-configurable edge is used, so must *all* diff --git a/vpr/src/route/check_route.h b/vpr/src/route/check_route.h index 4ad6075ec4e..5e73383d00c 100644 --- a/vpr/src/route/check_route.h +++ b/vpr/src/route/check_route.h @@ -3,7 +3,7 @@ #include "physical_types.h" #include "route_common.h" -void check_route(enum e_route_type route_type); +void check_route(enum e_route_type route_type, bool quick); void recompute_occupancy_from_scratch(); From e4c17cd824471b55c6223c2907edded2e2244cb2 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 23 Oct 2019 10:00:26 -0700 Subject: [PATCH 032/107] Inline and make const ref some args in the inner loop of the router. - Avoid copying cost_parameters structure. - Request inline of inner loop functions as they are invoked at few (1-3) callsites, but get called many many times. - Don't get congestion if it won't be used. Useful for accelerating pure expansion. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/route_timing.cpp | 160 ++++++++++++++++----------------- 1 file changed, 80 insertions(+), 80 deletions(-) diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index cc738162be4..d12e548411c 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -179,13 +179,13 @@ static std::vector timing_driven_find_all_shortest_paths_from_heap(const RouterStats& router_stats); void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* node); -static void timing_driven_expand_cheapest(t_heap* cheapest, - int target_node, - const t_conn_cost_params cost_params, - t_bb bounding_box, - const RouterLookahead& router_lookahead, - std::vector& modified_rr_node_inf, - RouterStats& router_stats); +static inline void timing_driven_expand_cheapest(t_heap* cheapest, + int target_node, + const t_conn_cost_params cost_params, + t_bb bounding_box, + const RouterLookahead& router_lookahead, + std::vector& modified_rr_node_inf, + RouterStats& router_stats); static t_rt_node* setup_routing_resources(int itry, ClusterNetId net_id, unsigned num_sinks, float pres_fac, int min_incremental_reroute_fanout, CBRR& incremental_rerouting_res, t_rt_node** rt_node_of_sink); @@ -205,54 +205,54 @@ static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root, static t_bb adjust_highfanout_bounding_box(t_bb highfanout_bb); -static void add_route_tree_node_to_heap(t_rt_node* rt_node, - int target_node, - const t_conn_cost_params cost_params, - const RouterLookahead& router_lookahead, - RouterStats& router_stats); - -static void timing_driven_expand_neighbours(t_heap* current, - const t_conn_cost_params cost_params, - t_bb bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - RouterStats& router_stats); - -static void timing_driven_expand_neighbour(t_heap* current, - const int from_node, - const t_edge_size from_edge, - const int to_node, - const t_conn_cost_params cost_params, - const t_bb bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - const t_bb target_bb, - RouterStats& router_stats); - -static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, - const RouterLookahead& router_lookahead, - const t_heap* current, - const int from_node, - const int to_node, - const int iconn, - const int target_node, - RouterStats& router_stats); - -static void timing_driven_expand_node(const t_conn_cost_params cost_params, - const RouterLookahead& router_lookahead, - t_heap* current, - const int from_node, - const int to_node, - const int iconn, - const int target_node); +static inline void add_route_tree_node_to_heap(t_rt_node* rt_node, + int target_node, + const t_conn_cost_params cost_params, + const RouterLookahead& router_lookahead, + RouterStats& router_stats); -static void evaluate_timing_driven_node_costs(t_heap* from, - const t_conn_cost_params cost_params, - const RouterLookahead& router_lookahead, - const int from_node, - const int to_node, - const int iconn, - const int target_node); +static inline void timing_driven_expand_neighbours(t_heap* current, + const t_conn_cost_params cost_params, + const t_bb& bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + RouterStats& router_stats); + +static inline void timing_driven_expand_neighbour(t_heap* current, + const int from_node, + const t_edge_size from_edge, + const int to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + const t_bb& target_bb, + RouterStats& router_stats); + +static inline void timing_driven_add_to_heap(const t_conn_cost_params& cost_params, + const RouterLookahead& router_lookahead, + const t_heap* current, + const int from_node, + const int to_node, + const int iconn, + const int target_node, + RouterStats& router_stats); + +static inline void timing_driven_expand_node(const t_conn_cost_params& cost_params, + const RouterLookahead& router_lookahead, + t_heap* current, + const int from_node, + const int to_node, + const int iconn, + const int target_node); + +static inline void evaluate_timing_driven_node_costs(t_heap* from, + const t_conn_cost_params& cost_params, + const RouterLookahead& router_lookahead, + const int from_node, + const int to_node, + const int iconn, + const int target_node); static bool timing_driven_check_net_delays(vtr::vector& net_delay); @@ -1961,12 +1961,12 @@ static void add_route_tree_node_to_heap(t_rt_node* rt_node, ++router_stats.heap_pushes; } -static void timing_driven_expand_neighbours(t_heap* current, - const t_conn_cost_params cost_params, - t_bb bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - RouterStats& router_stats) { +static inline void timing_driven_expand_neighbours(t_heap* current, + const t_conn_cost_params cost_params, + const t_bb& bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + RouterStats& router_stats) { /* Puts all the rr_nodes adjacent to current on the heap. */ @@ -1998,16 +1998,16 @@ static void timing_driven_expand_neighbours(t_heap* current, //Conditionally adds to_node to the router heap (via path from from_node via from_edge). //RR nodes outside the expanded bounding box specified in bounding_box are not added //to the heap. -static void timing_driven_expand_neighbour(t_heap* current, - const int from_node, - const t_edge_size from_edge, - const int to_node, - const t_conn_cost_params cost_params, - const t_bb bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - const t_bb target_bb, - RouterStats& router_stats) { +static inline void timing_driven_expand_neighbour(t_heap* current, + const int from_node, + const t_edge_size from_edge, + const int to_node, + const t_conn_cost_params& cost_params, + const t_bb& bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + const t_bb& target_bb, + RouterStats& router_stats) { auto& device_ctx = g_vpr_ctx.device(); int to_xlow = device_ctx.rr_nodes[to_node].xlow(); @@ -2063,14 +2063,14 @@ static void timing_driven_expand_neighbour(t_heap* current, } //Add to_node to the heap, and also add any nodes which are connected by non-configurable edges -static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, - const RouterLookahead& router_lookahead, - const t_heap* current, - const int from_node, - const int to_node, - const int iconn, - const int target_node, - RouterStats& router_stats) { +static inline void timing_driven_add_to_heap(const t_conn_cost_params& cost_params, + const RouterLookahead& router_lookahead, + const t_heap* current, + const int from_node, + const int to_node, + const int iconn, + const int target_node, + RouterStats& router_stats) { t_heap* next = alloc_heap_data(); next->index = to_node; @@ -2107,7 +2107,7 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, } //Updates current (path step and costs) to account for the step taken to reach to_node -static void timing_driven_expand_node(const t_conn_cost_params cost_params, +static void timing_driven_expand_node(const t_conn_cost_params& cost_params, const RouterLookahead& router_lookahead, t_heap* current, const int from_node, @@ -2129,7 +2129,7 @@ static void timing_driven_expand_node(const t_conn_cost_params cost_params, //Calculates the cost of reaching to_node static void evaluate_timing_driven_node_costs(t_heap* to, - const t_conn_cost_params cost_params, + const t_conn_cost_params& cost_params, const RouterLookahead& router_lookahead, const int from_node, const int to_node, From 7028e832f0cd10c5a13e7fb80aaf0d5c50422797 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 4 Dec 2019 05:39:22 -0800 Subject: [PATCH 033/107] Add back some missing enables for reading of edge metadata. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- utils/fasm/test/test_fasm.cpp | 2 ++ vpr/test/test_vpr.cpp | 2 ++ 2 files changed, 4 insertions(+) diff --git a/utils/fasm/test/test_fasm.cpp b/utils/fasm/test/test_fasm.cpp index 543d3a92636..706f1eb0e04 100644 --- a/utils/fasm/test/test_fasm.cpp +++ b/utils/fasm/test/test_fasm.cpp @@ -182,6 +182,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") { }; vpr_init(sizeof(argv)/sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_setup.RouterOpts.read_edge_metadata = true; bool flow_succeeded = vpr_flow(vpr_setup, arch); REQUIRE(flow_succeeded == true); @@ -219,6 +220,7 @@ TEST_CASE("fasm_integration_test", "[fasm]") { vpr_setup.PackerOpts.doPacking = STAGE_LOAD; vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD; vpr_setup.RouterOpts.doRouting = STAGE_LOAD; + vpr_setup.RouterOpts.read_edge_metadata = true; vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP; bool flow_succeeded = vpr_flow(vpr_setup, arch); diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index 3aa4029deed..f3ff24b61b1 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -123,6 +123,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { }; vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_setup.RouterOpts.read_edge_metadata = true; vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); @@ -164,6 +165,7 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); + vpr_setup.RouterOpts.read_edge_metadata = true; vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); From e347a86f02560b899e9d13c61cc7d326eccd7194 Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Thu, 12 Dec 2019 17:15:11 -0800 Subject: [PATCH 034/107] use vtr::ScopedStartFinishTimer Signed-off-by: Dustin DeWeese --- vpr/src/route/check_route.cpp | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index fa69b991e0a..855c5d8670d 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -3,6 +3,7 @@ #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_memory.h" +#include "vtr_time.h" #include "vpr_types.h" #include "vpr_error.h" @@ -630,18 +631,13 @@ static void check_node_and_range(int inode, enum e_route_type route_type) { //Checks that all non-configurable edges are in a legal configuration //This check is slow, so it has been moved out of check_route() static void check_all_non_configurable_edges() { - VTR_LOG("\n"); - VTR_LOG("Checking to ensure non-configurable edges are legal...\n"); - + vtr::ScopedStartFinishTimer timer("Checking to ensure non-configurable edges are legal"); auto non_configurable_rr_sets = identify_non_configurable_rr_sets(); - auto& cluster_ctx = g_vpr_ctx.clustering(); + for (auto net_id : cluster_ctx.clb_nlist.nets()) { check_non_configurable_edges(net_id, non_configurable_rr_sets); } - - VTR_LOG("Completed non-configurable edge check successfully.\n"); - VTR_LOG("\n"); } //Checks that the specified routing is legal with respect to non-configurable edges From b5d9fa59986e5a282d37d8e90487f585d2aeffda Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 8 Jul 2019 13:49:21 -0700 Subject: [PATCH 035/107] Sync connection_box with upstream. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- libs/EXTERNAL/CMakeLists.txt | 2 +- libs/libvtrcapnproto/CMakeLists.txt | 1 + libs/libvtrcapnproto/connection_map.capnp | 19 + vpr/src/base/echo_files.cpp | 2 + vpr/src/base/echo_files.h | 1 + vpr/src/base/read_options.cpp | 15 +- vpr/src/base/vpr_context.h | 3 + vpr/src/base/vpr_types.h | 5 +- vpr/src/route/connection_box.cpp | 127 ++++ vpr/src/route/connection_box.h | 76 +++ .../route/connection_box_lookahead_map.cpp | 578 ++++++++++++++++++ vpr/src/route/connection_box_lookahead_map.h | 17 + vpr/src/route/router_lookahead.cpp | 3 + vpr/src/route/router_lookahead_map_utils.cpp | 192 ++++++ vpr/src/route/router_lookahead_map_utils.h | 144 +++++ vpr/src/route/rr_graph.cpp | 1 + vpr/src/route/rr_graph_reader.cpp | 54 ++ vpr/src/route/rr_node.h | 2 +- 18 files changed, 1235 insertions(+), 7 deletions(-) create mode 100644 libs/libvtrcapnproto/connection_map.capnp create mode 100644 vpr/src/route/connection_box.cpp create mode 100644 vpr/src/route/connection_box.h create mode 100644 vpr/src/route/connection_box_lookahead_map.cpp create mode 100644 vpr/src/route/connection_box_lookahead_map.h create mode 100644 vpr/src/route/router_lookahead_map_utils.cpp create mode 100644 vpr/src/route/router_lookahead_map_utils.h diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index 38a14d76e25..ebf52b0e3c7 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -8,7 +8,7 @@ add_subdirectory(libsdcparse) add_subdirectory(libblifparse) add_subdirectory(libtatum) -#VPR_USE_EZGL is initialized in the root CMakeLists. +#VPR_USE_EZGL is initialized in the root CMakeLists. #compile libezgl only if the user asks for or has its dependencies installed. if(VPR_USE_EZGL STREQUAL "on") add_subdirectory(libezgl) diff --git a/libs/libvtrcapnproto/CMakeLists.txt b/libs/libvtrcapnproto/CMakeLists.txt index ccf3b6bd80b..33ce15ef397 100644 --- a/libs/libvtrcapnproto/CMakeLists.txt +++ b/libs/libvtrcapnproto/CMakeLists.txt @@ -19,6 +19,7 @@ endif() # Each schema used should appear here. capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS place_delay_model.capnp + connection_map.capnp matrix.capnp ) diff --git a/libs/libvtrcapnproto/connection_map.capnp b/libs/libvtrcapnproto/connection_map.capnp new file mode 100644 index 00000000000..ac03ddfc9c0 --- /dev/null +++ b/libs/libvtrcapnproto/connection_map.capnp @@ -0,0 +1,19 @@ +@0x876ec83c2fea5a18; + +using Matrix = import "matrix.capnp"; + +struct VprCostEntry { + delay @0 :Float32; + congestion @1 :Float32; +} + +struct VprVector2D { + x @0 :Int64; + y @1 :Int64; +} + +struct VprCostMap { + costMap @0 :List(Matrix.Matrix(VprCostEntry)); + offset @1 :List(VprVector2D); + segmentMap @2 :List(Int64); +} diff --git a/vpr/src/base/echo_files.cpp b/vpr/src/base/echo_files.cpp index 6f8de45933b..cd4e2566f9b 100644 --- a/vpr/src/base/echo_files.cpp +++ b/vpr/src/base/echo_files.cpp @@ -114,6 +114,8 @@ void alloc_and_load_echo_file_info() { setEchoFileName(E_ECHO_CHAN_DETAILS, "chan_details.txt"); setEchoFileName(E_ECHO_SBLOCK_PATTERN, "sblock_pattern.txt"); setEchoFileName(E_ECHO_ENDPOINT_TIMING, "endpoint_timing.echo.json"); + + setEchoFileName(E_ECHO_LOOKAHEAD_MAP, "lookahead_map.echo"); } void free_echo_file_info() { diff --git a/vpr/src/base/echo_files.h b/vpr/src/base/echo_files.h index 70df3a3d962..d273c575d50 100644 --- a/vpr/src/base/echo_files.h +++ b/vpr/src/base/echo_files.h @@ -46,6 +46,7 @@ enum e_echo_files { E_ECHO_CHAN_DETAILS, E_ECHO_SBLOCK_PATTERN, E_ECHO_ENDPOINT_TIMING, + E_ECHO_LOOKAHEAD_MAP, //Timing Graphs E_ECHO_PRE_PACKING_TIMING_GRAPH, diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 5f654445efd..b9bbedf30c3 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -652,6 +652,8 @@ struct ParseRouterLookahead { conv_value.set_value(e_router_lookahead::CLASSIC); else if (str == "map") conv_value.set_value(e_router_lookahead::MAP); + else if (str == "connection_box_map") + conv_value.set_value(e_router_lookahead::CONNECTION_BOX_MAP); else { std::stringstream msg; msg << "Invalid conversion from '" @@ -665,17 +667,22 @@ struct ParseRouterLookahead { ConvertedValue to_str(e_router_lookahead val) { ConvertedValue conv_value; - if (val == e_router_lookahead::CLASSIC) + if (val == e_router_lookahead::CLASSIC) { conv_value.set_value("classic"); - else { - VTR_ASSERT(val == e_router_lookahead::MAP); + } else if (val == e_router_lookahead::MAP) { conv_value.set_value("map"); + } else if (val == e_router_lookahead::CONNECTION_BOX_MAP) { + conv_value.set_value("connection_box_map"); + } else { + std::stringstream msg; + msg << "Unrecognized e_router_lookahead"; + conv_value.set_error(msg.str()); } return conv_value; } std::vector default_choices() { - return {"classic", "map"}; + return {"classic", "map", "connection_box_map"}; } }; diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index b6a1f9859da..122fa95229a 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -21,6 +21,7 @@ #include "router_lookahead.h" #include "place_macro.h" #include "compressed_grid.h" +#include "connection_box.h" //A Context is collection of state relating to a particular part of VPR // @@ -212,6 +213,8 @@ struct DeviceContext : public Context { // Name of rrgraph file read (if any). // Used to determine when reading rrgraph if file is already loaded. std::string read_rr_graph_filename; + + ConnectionBoxes connection_boxes; }; //State relating to power analysis diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index e6c010f7398..b23080cc4f4 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -104,7 +104,10 @@ constexpr const char* EMPTY_BLOCK_NAME = "EMPTY"; enum class e_router_lookahead { CLASSIC, //VPR's classic lookahead (assumes uniform wire types) MAP, //Lookahead considering different wire types (see Oleg Petelin's MASc Thesis) - NO_OP //A no-operation lookahead which always returns zero + NO_OP, //A no-operation lookahead which always returns zero + CONNECTION_BOX_MAP, + // Lookahead considering different wire types and IPIN + // connection box. }; enum class e_route_bb_update { diff --git a/vpr/src/route/connection_box.cpp b/vpr/src/route/connection_box.cpp new file mode 100644 index 00000000000..85d554b4307 --- /dev/null +++ b/vpr/src/route/connection_box.cpp @@ -0,0 +1,127 @@ +#include "connection_box.h" +#include "vtr_assert.h" +#include "globals.h" + +ConnectionBoxes::ConnectionBoxes() + : size_(std::make_pair(0, 0)) { +} + +size_t ConnectionBoxes::num_connection_box_types() const { + return boxes_.size(); +} + +std::pair ConnectionBoxes::connection_box_grid_size() const { + return size_; +} + +const ConnectionBox* ConnectionBoxes::get_connection_box(ConnectionBoxId box) const { + if (bool(box)) { + return nullptr; + } + + size_t index = size_t(box); + if (index >= boxes_.size()) { + return nullptr; + } + + return &boxes_.at(index); +} + +bool ConnectionBoxes::find_connection_box(int inode, + ConnectionBoxId* box_id, + std::pair* box_location) const { + VTR_ASSERT(box_id != nullptr); + VTR_ASSERT(box_location != nullptr); + + const auto& conn_box_loc = ipin_map_[inode]; + if (conn_box_loc.box_id == ConnectionBoxId::INVALID()) { + return false; + } + + *box_id = conn_box_loc.box_id; + *box_location = conn_box_loc.box_location; + return true; +} + +// Clear IPIN map and set connection box grid size and box ids. +void ConnectionBoxes::reset_boxes(std::pair size, + const std::vector boxes) { + clear(); + + size_ = size; + boxes_ = boxes; +} + +void ConnectionBoxes::resize_nodes(size_t rr_node_size) { + ipin_map_.resize(rr_node_size); + canonical_loc_map_.resize(rr_node_size, + std::make_pair(-1, -1)); +} + +void ConnectionBoxes::clear() { + ipin_map_.clear(); + size_ = std::make_pair(0, 0); + boxes_.clear(); + canonical_loc_map_.clear(); + sink_to_ipin_.clear(); +} + +void ConnectionBoxes::add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location) { + // Ensure that box location is in bounds + VTR_ASSERT(box_location.first < size_.first); + VTR_ASSERT(box_location.second < size_.second); + + // Bounds check box_id + VTR_ASSERT(bool(box_id)); + VTR_ASSERT(size_t(box_id) < boxes_.size()); + + // Make sure sink map will not be invalidated upon insertion. + VTR_ASSERT(sink_to_ipin_.size() == 0); + + ipin_map_[inode] = ConnBoxLoc(box_location, box_id); +} + +void ConnectionBoxes::add_canonical_loc(int inode, std::pair loc) { + VTR_ASSERT(loc.first < size_.first); + VTR_ASSERT(loc.second < size_.second); + canonical_loc_map_[inode] = loc; +} + +const std::pair* ConnectionBoxes::find_canonical_loc(int inode) const { + const auto& canon_loc = canonical_loc_map_[inode]; + if (canon_loc.first == size_t(-1)) { + return nullptr; + } + + return &canon_loc; +} + +void ConnectionBoxes::create_sink_back_ref() { + const auto& device_ctx = g_vpr_ctx.device(); + + sink_to_ipin_.resize(device_ctx.rr_nodes.size(), {{0, 0, 0, 0}, 0}); + + for (size_t i = 0; i < device_ctx.rr_nodes.size(); ++i) { + const auto& ipin_node = device_ctx.rr_nodes[i]; + if (ipin_node.type() != IPIN) { + continue; + } + + if (ipin_map_[i].box_id == ConnectionBoxId::INVALID()) { + continue; + } + + for (auto edge : ipin_node.edges()) { + int sink_inode = ipin_node.edge_sink_node(edge); + VTR_ASSERT(device_ctx.rr_nodes[sink_inode].type() == SINK); + VTR_ASSERT(sink_to_ipin_[sink_inode].ipin_count < 4); + auto& sink_to_ipin = sink_to_ipin_[sink_inode]; + sink_to_ipin.ipin_nodes[sink_to_ipin.ipin_count++] = i; + } + } +} + +const SinkToIpin& ConnectionBoxes::find_sink_connection_boxes( + int inode) const { + return sink_to_ipin_[inode]; +} diff --git a/vpr/src/route/connection_box.h b/vpr/src/route/connection_box.h new file mode 100644 index 00000000000..06217ac2a41 --- /dev/null +++ b/vpr/src/route/connection_box.h @@ -0,0 +1,76 @@ +#ifndef CONNECTION_BOX_H +#define CONNECTION_BOX_H +// Some routing graphs have connectivity driven by types of connection boxes. +// This class relates IPIN rr nodes with connection box type and locations, used +// for connection box driven map lookahead. + +#include +#include "vtr_strong_id.h" +#include "vtr_flat_map.h" +#include "vtr_range.h" +#include + +struct connection_box_tag {}; +typedef vtr::StrongId ConnectionBoxId; + +struct ConnectionBox { + std::string name; +}; + +struct ConnBoxLoc { + ConnBoxLoc() + : box_location(std::make_pair(-1, -1)) {} + ConnBoxLoc( + const std::pair& a_box_location, + ConnectionBoxId a_box_id) + : box_location(a_box_location) + , box_id(a_box_id) {} + + std::pair box_location; + ConnectionBoxId box_id; +}; + +struct SinkToIpin { + int ipin_nodes[4]; + int ipin_count; +}; + +class ConnectionBoxes { + public: + ConnectionBoxes(); + + size_t num_connection_box_types() const; + std::pair connection_box_grid_size() const; + const ConnectionBox* get_connection_box(ConnectionBoxId box) const; + + bool find_connection_box(int inode, + ConnectionBoxId* box_id, + std::pair* box_location) const; + const std::pair* find_canonical_loc(int inode) const; + + // Clear IPIN map and set connection box grid size and box ids. + void clear(); + void reset_boxes(std::pair size, + const std::vector boxes); + void resize_nodes(size_t rr_node_size); + + void add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location); + void add_canonical_loc(int inode, std::pair loc); + + // Create map from SINK's back to IPIN's + // + // This must be called after all connection boxes have been added. + void create_sink_back_ref(); + const SinkToIpin& find_sink_connection_boxes( + int inode) const; + + private: + std::pair size_; + std::vector boxes_; + std::vector ipin_map_; + std::vector sink_to_ipin_; + std::vector> + canonical_loc_map_; +}; + +#endif diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp new file mode 100644 index 00000000000..dad1b8d2b93 --- /dev/null +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -0,0 +1,578 @@ +#include "connection_box_lookahead_map.h" + +#include +#include + +#include "connection_box.h" +#include "rr_node.h" +#include "router_lookahead_map_utils.h" +#include "globals.h" +#include "vtr_math.h" +#include "vtr_time.h" +#include "echo_files.h" + +#include "route_timing.h" + +#include "capnp/serialize.h" +#include "connection_map.capnp.h" +#include "ndmatrix_serdes.h" +#include "mmap_file.h" +#include "serdes_utils.h" + +/* we're profiling routing cost over many tracks for each wire type, so we'll + * have many cost entries at each |dx|,|dy| offset. There are many ways to + * "boil down" the many costs at each offset to a single entry for a given + * (wire type, chan_type) combination we can take the smallest cost, the + * average, median, etc. This define selects the method we use. + * + * See e_representative_entry_method */ +#define REPRESENTATIVE_ENTRY_METHOD SMALLEST + +#define REF_X 25 +#define REF_Y 23 + +static int signum(int x) { + if (x > 0) return 1; + if (x < 0) + return -1; + else + return 0; +} + +typedef std::vector, Cost_Entry>> t_routing_cost_map; +static void run_dijkstra(int start_node_ind, + t_routing_cost_map* cost_map); + +class CostMap { + public: + void set_segment_count(size_t seg_count) { + cost_map_.clear(); + offset_.clear(); + cost_map_.resize(seg_count); + offset_.resize(seg_count); + + const auto& device_ctx = g_vpr_ctx.device(); + segment_map_.resize(device_ctx.rr_nodes.size()); + for (size_t i = 0; i < segment_map_.size(); ++i) { + auto& from_node = device_ctx.rr_nodes[i]; + + int from_cost_index = from_node.cost_index(); + int from_seg_index = device_ctx.rr_indexed_data[from_cost_index].seg_index; + + segment_map_[i] = from_seg_index; + } + } + + int node_to_segment(int from_node_ind) { + return segment_map_[from_node_ind]; + } + + Cost_Entry find_cost(int from_seg_index, int delta_x, int delta_y) const { + VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); + int dx = delta_x - offset_[from_seg_index].first; + int dy = delta_y - offset_[from_seg_index].second; + const auto& cost_map = cost_map_[from_seg_index]; + + if (dx < 0) { + dx = 0; + } + if (dy < 0) { + dy = 0; + } + + if (dx >= (ssize_t)cost_map.dim_size(0)) { + dx = cost_map.dim_size(0) - 1; + } + if (dy >= (ssize_t)cost_map.dim_size(1)) { + dy = cost_map.dim_size(1) - 1; + } + + return cost_map_[from_seg_index][dx][dy]; + } + + void set_cost_map(int from_seg_index, + const t_routing_cost_map& cost_map, + e_representative_entry_method method) { + VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); + + // Find coordinate offset for this segment. + int min_dx = 0; + int min_dy = 0; + int max_dx = 0; + int max_dy = 0; + for (const auto& entry : cost_map) { + min_dx = std::min(entry.first.first, min_dx); + min_dy = std::min(entry.first.second, min_dy); + + max_dx = std::max(entry.first.first, max_dx); + max_dy = std::max(entry.first.second, max_dy); + } + + offset_[from_seg_index].first = min_dx; + offset_[from_seg_index].second = min_dy; + size_t dim_x = max_dx - min_dx + 1; + size_t dim_y = max_dy - min_dy + 1; + + vtr::NdMatrix expansion_cost_map( + {dim_x, dim_y}); + + for (const auto& entry : cost_map) { + int x = entry.first.first - min_dx; + int y = entry.first.second - min_dy; + expansion_cost_map[x][y].add_cost_entry( + method, entry.second.delay, + entry.second.congestion); + } + + cost_map_[from_seg_index] = vtr::NdMatrix( + {dim_x, dim_y}); + + /* set the lookahead cost map entries with a representative cost + * entry from routing_cost_map */ + for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { + for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { + cost_map_[from_seg_index][ix][iy] = expansion_cost_map[ix][iy].get_representative_cost_entry(method); + } + } + + /* find missing cost entries and fill them in by copying a nearby cost entry */ + for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { + for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { + Cost_Entry cost_entry = cost_map_[from_seg_index][ix][iy]; + + if (!cost_entry.valid()) { + Cost_Entry copied_entry = get_nearby_cost_entry( + from_seg_index, + offset_[from_seg_index].first + ix, + offset_[from_seg_index].second + iy); + cost_map_[from_seg_index][ix][iy] = copied_entry; + } + } + } + } + + Cost_Entry get_nearby_cost_entry(int segment_index, int x, int y) { + /* compute the slope from x,y to 0,0 and then move towards 0,0 by one + * unit to get the coordinates of the cost entry to be copied */ + + float slope; + int copy_x, copy_y; + if (x == 0 || y == 0) { + slope = std::numeric_limits::infinity(); + copy_x = x - signum(x); + copy_y = y - signum(y); + } else { + slope = (float)y / (float)x; + if (slope >= 1.0) { + copy_y = y - signum(y); + copy_x = vtr::nint((float)y / slope); + } else { + copy_x = x - signum(x); + copy_y = vtr::nint((float)x * slope); + } + } + + Cost_Entry copy_entry = find_cost(segment_index, copy_x, copy_y); + + /* if the entry to be copied is also empty, recurse */ + if (copy_entry.valid()) { + return copy_entry; + } else if (copy_x == 0 && copy_y == 0) { + return Cost_Entry(); + } + + return get_nearby_cost_entry(segment_index, copy_x, copy_y); + } + + void print_cost_map(const std::vector& segment_inf, + const char* fname) { + FILE* fp = vtr::fopen(fname, "w"); + for (size_t iseg = 0; iseg < cost_map_.size(); iseg++) { + fprintf(fp, "Seg %s(%zu) (%d, %d)\n", segment_inf.at(iseg).name.c_str(), + iseg, + offset_[iseg].first, + offset_[iseg].second); + for (size_t iy = 0; iy < cost_map_[iseg].dim_size(1); iy++) { + for (size_t ix = 0; ix < cost_map_[iseg].dim_size(0); ix++) { + fprintf(fp, "%.4g,\t", + cost_map_[iseg][ix][iy].delay); + } + fprintf(fp, "\n"); + } + fprintf(fp, "\n\n"); + } + + fclose(fp); + } + + void read(const std::string& file); + void write(const std::string& file) const; + + private: + std::vector> cost_map_; + std::vector> offset_; + std::vector segment_map_; +}; + +static CostMap g_cost_map; + +class StartNode { + public: + StartNode(int start_x, int start_y, t_rr_type rr_type, int seg_index) + : start_x_(start_x) + , start_y_(start_y) + , rr_type_(rr_type) + , seg_index_(seg_index) + , index_(0) {} + int get_next_node() { + const auto& device_ctx = g_vpr_ctx.device(); + const std::vector& channel_node_list = device_ctx.rr_node_indices[rr_type_][start_x_][start_y_][0]; + + for (; index_ < channel_node_list.size(); index_++) { + int node_ind = channel_node_list[index_]; + + if (node_ind == OPEN || device_ctx.rr_nodes[node_ind].capacity() == 0) { + continue; + } + + const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(node_ind); + if (loc == nullptr) { + continue; + } + + int node_cost_ind = device_ctx.rr_nodes[node_ind].cost_index(); + int node_seg_ind = device_ctx.rr_indexed_data[node_cost_ind].seg_index; + if (node_seg_ind == seg_index_) { + index_ += 1; + return node_ind; + } + } + + return UNDEFINED; + } + + private: + int start_x_; + int start_y_; + t_rr_type rr_type_; + int seg_index_; + size_t index_; +}; + +// Minimum size of search for channels to profile. kMinProfile results +// in searching x = [0, kMinProfile], and y = [0, kMinProfile[. +// +// Making this value larger will increase the sample size, but also the runtime +// to produce the lookahead. +static constexpr int kMinProfile = 1; + +// Maximum size of search for channels to profile. Once search is outside of +// kMinProfile distance, lookahead will stop searching once: +// - At least one channel has been profiled +// - kMaxProfile is exceeded. +static constexpr int kMaxProfile = 7; + +static void compute_connection_box_lookahead( + const std::vector& segment_inf) { + size_t num_segments = segment_inf.size(); + vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); + + /* free previous delay map and allocate new one */ + g_cost_map.set_segment_count(segment_inf.size()); + + /* run Dijkstra's algorithm for each segment type & channel type combination */ + for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { + VTR_LOG("Creating cost map for %s(%d)\n", + segment_inf[iseg].name.c_str(), iseg); + /* allocate the cost map for this iseg/chan_type */ + t_routing_cost_map cost_map; + + int count = 0; + + int dx = 0; + int dy = 0; + //int start_x = vtr::nint(device_ctx.grid.width()/2); + //int start_y = vtr::nint(device_ctx.grid.height()/2); + int start_x = REF_X; + int start_y = REF_Y; + while ((count == 0 && dx < kMaxProfile) || dy <= kMinProfile) { + for (e_rr_type chan_type : {CHANX, CHANY}) { + StartNode start_node(start_x + dx, start_y + dy, chan_type, iseg); + + for (int start_node_ind = start_node.get_next_node(); + start_node_ind != UNDEFINED; + start_node_ind = start_node.get_next_node()) { + count += 1; + + /* run Dijkstra's algorithm */ + run_dijkstra(start_node_ind, &cost_map); + } + } + + if (dy < dx) { + dy += 1; + } else { + dx += 1; + } + } + + if (count == 0) { + VTR_LOG_WARN("Segment %s(%d) found no start_node_ind\n", + segment_inf[iseg].name.c_str(), iseg); + } + + /* boil down the cost list in routing_cost_map at each coordinate to a + * representative cost entry and store it in the lookahead cost map */ + g_cost_map.set_cost_map(iseg, cost_map, + REPRESENTATIVE_ENTRY_METHOD); + } + + if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_LOOKAHEAD_MAP)) { + g_cost_map.print_cost_map(segment_inf, getEchoFileName(E_ECHO_LOOKAHEAD_MAP)); + } +} + +static float get_connection_box_lookahead_map_cost(int from_node_ind, + int to_node_ind, + float criticality_fac) { + if (from_node_ind == to_node_ind) { + return 0.f; + } + + auto& device_ctx = g_vpr_ctx.device(); + + std::pair from_location; + std::pair to_location; + auto to_node_type = device_ctx.rr_nodes[to_node_ind].type(); + + if (to_node_type == SINK) { + const auto& sink_to_ipin = device_ctx.connection_boxes.find_sink_connection_boxes(to_node_ind); + if (sink_to_ipin.ipin_count > 1) { + float cost = std::numeric_limits::infinity(); + // Find cheapest cost from from_node_ind to IPINs for this SINK. + for (int i = 0; i < sink_to_ipin.ipin_count; ++i) { + cost = std::min(cost, + get_connection_box_lookahead_map_cost( + from_node_ind, + sink_to_ipin.ipin_nodes[i], criticality_fac)); + } + + return cost; + } else if (sink_to_ipin.ipin_count == 1) { + to_node_ind = sink_to_ipin.ipin_nodes[0]; + if (from_node_ind == to_node_ind) { + return 0.f; + } + } else { + return std::numeric_limits::infinity(); + } + } + + if (device_ctx.rr_nodes[to_node_ind].type() == IPIN) { + ConnectionBoxId box_id; + std::pair box_location; + bool found = device_ctx.connection_boxes.find_connection_box( + to_node_ind, &box_id, &box_location); + if (!found) { + VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", to_node_ind); + } + + to_location = box_location; + } else { + const std::pair* to_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(to_node_ind); + if (!to_canonical_loc) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical loc for %d", to_node_ind); + } + + to_location = *to_canonical_loc; + } + + const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(from_node_ind); + if (from_canonical_loc == nullptr) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical loc for %d (to %d)", + from_node_ind, to_node_ind); + } + + ssize_t dx = ssize_t(from_canonical_loc->first) - ssize_t(to_location.first); + ssize_t dy = ssize_t(from_canonical_loc->second) - ssize_t(to_location.second); + + int from_seg_index = g_cost_map.node_to_segment(from_node_ind); + Cost_Entry cost_entry = g_cost_map.find_cost(from_seg_index, dx, dy); + float expected_delay = cost_entry.delay; + float expected_congestion = cost_entry.congestion; + + float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; + return expected_cost; +} + +/* runs Dijkstra's algorithm from specified node until all nodes have been + * visited. Each time a pin is visited, the delay/congestion information + * to that pin is stored to an entry in the routing_cost_map */ +static void run_dijkstra(int start_node_ind, + t_routing_cost_map* routing_cost_map) { + auto& device_ctx = g_vpr_ctx.device(); + + /* a list of boolean flags (one for each rr node) to figure out if a + * certain node has already been expanded */ + std::vector node_expanded(device_ctx.rr_nodes.size(), false); + /* for each node keep a list of the cost with which that node has been + * visited (used to determine whether to push a candidate node onto the + * expansion queue */ + std::vector node_visited_costs(device_ctx.rr_nodes.size(), -1.0); + /* a priority queue for expansion */ + std::priority_queue pq; + + /* first entry has no upstream delay or congestion */ + util::PQ_Entry first_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); + + pq.push(first_entry); + + const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(start_node_ind); + if (from_canonical_loc == nullptr) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", + start_node_ind); + } + + /* now do routing */ + while (!pq.empty()) { + util::PQ_Entry current = pq.top(); + pq.pop(); + + int node_ind = current.rr_node_ind; + + /* check that we haven't already expanded from this node */ + if (node_expanded[node_ind]) { + continue; + } + + /* if this node is an ipin record its congestion/delay in the routing_cost_map */ + if (device_ctx.rr_nodes[node_ind].type() == IPIN) { + ConnectionBoxId box_id; + std::pair box_location; + bool found = device_ctx.connection_boxes.find_connection_box( + node_ind, &box_id, &box_location); + if (!found) { + VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); + } + + int delta_x = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); + int delta_y = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); + + routing_cost_map->push_back(std::make_pair( + std::make_pair(delta_x, delta_y), + Cost_Entry( + current.delay, + current.congestion_upstream))); + } + + expand_dijkstra_neighbours(current, node_visited_costs, node_expanded, pq); + node_expanded[node_ind] = true; + } +} + +void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf) { + compute_connection_box_lookahead(segment_inf); +} + +float ConnectionBoxMapLookahead::get_expected_cost( + int current_node, + int target_node, + const t_conn_cost_params& params, + float /*R_upstream*/) const { + auto& device_ctx = g_vpr_ctx.device(); + + t_rr_type rr_type = device_ctx.rr_nodes[current_node].type(); + + if (rr_type == CHANX || rr_type == CHANY) { + return get_connection_box_lookahead_map_cost( + current_node, target_node, params.criticality); + } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ + return (device_ctx.rr_indexed_data[SINK_COST_INDEX].base_cost); + } else { /* Change this if you want to investigate route-throughs */ + return (0.); + } +} + +void ConnectionBoxMapLookahead::read(const std::string& file) { + g_cost_map.read(file); +} +void ConnectionBoxMapLookahead::write(const std::string& file) const { + g_cost_map.write(file); +} + +static void ToCostEntry(Cost_Entry* out, const VprCostEntry::Reader& in) { + out->delay = in.getDelay(); + out->congestion = in.getCongestion(); +} + +static void FromCostEntry(VprCostEntry::Builder* out, const Cost_Entry& in) { + out->setDelay(in.delay); + out->setCongestion(in.congestion); +} + +void CostMap::read(const std::string& file) { + MmapFile f(file); + ::capnp::FlatArrayMessageReader reader(f.getData()); + + auto cost_map = reader.getRoot(); + + { + const auto& segment_map = cost_map.getSegmentMap(); + segment_map_.resize(segment_map.size()); + auto dst_iter = segment_map_.begin(); + for (const auto& src : segment_map) { + *dst_iter++ = src; + } + } + + { + const auto& offset = cost_map.getOffset(); + offset_.resize(offset.size()); + auto dst_iter = offset_.begin(); + for (const auto& src : offset) { + *dst_iter++ = std::make_pair(src.getX(), src.getY()); + } + } + + { + const auto& cost_maps = cost_map.getCostMap(); + cost_map_.resize(cost_maps.size()); + auto dst_iter = cost_map_.begin(); + for (const auto& src : cost_maps) { + ToNdMatrix<2, VprCostEntry, Cost_Entry>(&(*dst_iter++), src, ToCostEntry); + } + } +} + +void CostMap::write(const std::string& file) const { + ::capnp::MallocMessageBuilder builder; + + auto cost_map = builder.initRoot(); + + { + auto segment_map = cost_map.initSegmentMap(segment_map_.size()); + for (size_t i = 0; i < segment_map_.size(); ++i) { + segment_map.set(i, segment_map_[i]); + } + } + + { + auto offset = cost_map.initOffset(offset_.size()); + for (size_t i = 0; i < offset_.size(); ++i) { + auto elem = offset[i]; + elem.setX(offset_[i].first); + elem.setY(offset_[i].second); + } + } + + { + auto cost_maps = cost_map.initCostMap(cost_map_.size()); + for (size_t i = 0; i < cost_map_.size(); ++i) { + Matrix::Builder elem = cost_maps[i]; + FromNdMatrix<2, VprCostEntry, Cost_Entry>( + &elem, cost_map_[i], FromCostEntry); + } + } + + writeMessageToFile(file, &builder); +} diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h new file mode 100644 index 00000000000..03e1a140f0b --- /dev/null +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -0,0 +1,17 @@ +#ifndef CONNECTION_BOX_LOOKAHEAD_H_ +#define CONNECTION_BOX_LOOKAHEAD_H_ + +#include +#include "physical_types.h" +#include "router_lookahead.h" + +class ConnectionBoxMapLookahead : public RouterLookahead { + public: + float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; + void compute(const std::vector& segment_inf) override; + + void read(const std::string& file) override; + void write(const std::string& file) const override; +}; + +#endif diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp index 130b862e94c..80f29911aa9 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead.cpp @@ -1,6 +1,7 @@ #include "router_lookahead.h" #include "router_lookahead_map.h" +#include "connection_box_lookahead_map.h" #include "vpr_error.h" #include "globals.h" #include "route_timing.h" @@ -13,6 +14,8 @@ static std::unique_ptr make_router_lookahead_object(e_router_lo return std::make_unique(); } else if (router_lookahead_type == e_router_lookahead::MAP) { return std::make_unique(); + } else if (router_lookahead_type == e_router_lookahead::CONNECTION_BOX_MAP) { + return std::make_unique(); } else if (router_lookahead_type == e_router_lookahead::NO_OP) { return std::make_unique(); } diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp new file mode 100644 index 00000000000..d50aa372a5f --- /dev/null +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -0,0 +1,192 @@ +#include "router_lookahead_map_utils.h" + +#include "globals.h" +#include "vpr_context.h" +#include "vtr_math.h" + +/* Number of CLBs I think the average conn. goes. */ +static const int CLB_DIST = 3; + +util::PQ_Entry::PQ_Entry( + int set_rr_node_ind, + int switch_ind, + float parent_delay, + float parent_R_upstream, + float parent_congestion_upstream, + bool starting_node) { + this->rr_node_ind = set_rr_node_ind; + + auto& device_ctx = g_vpr_ctx.device(); + this->delay = parent_delay; + this->congestion_upstream = parent_congestion_upstream; + this->R_upstream = parent_R_upstream; + if (!starting_node) { + int cost_index = device_ctx.rr_nodes[set_rr_node_ind].cost_index(); + + float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; + float Rsw = device_ctx.rr_switch_inf[switch_ind].R; + float Cnode = device_ctx.rr_nodes[set_rr_node_ind].C(); + float Rnode = device_ctx.rr_nodes[set_rr_node_ind].R(); + + float T_linear = 0.f; + float T_quadratic = 0.f; + if (device_ctx.rr_switch_inf[switch_ind].buffered()) { + T_linear = Tsw + Rsw * Cnode + 0.5 * Rnode * Cnode; + T_quadratic = 0.; + } else { /* Pass transistor */ + T_linear = Tsw + 0.5 * Rsw * Cnode; + T_quadratic = (Rsw + Rnode) * 0.5 * Cnode; + } + + float base_cost; + if (device_ctx.rr_indexed_data[cost_index].inv_length < 0) { + base_cost = device_ctx.rr_indexed_data[cost_index].base_cost; + } else { + float frac_num_seg = CLB_DIST * device_ctx.rr_indexed_data[cost_index].inv_length; + + base_cost = frac_num_seg * T_linear + + frac_num_seg * frac_num_seg * T_quadratic; + } + + VTR_ASSERT(T_linear >= 0.); + VTR_ASSERT(base_cost >= 0.); + this->delay += T_linear; + + this->congestion_upstream += base_cost; + } + + /* set the cost of this node */ + this->cost = this->delay; +} + +/* returns cost entry with the smallest delay */ +Cost_Entry Expansion_Cost_Entry::get_smallest_entry() const { + Cost_Entry smallest_entry; + + for (auto entry : this->cost_vector) { + if (!smallest_entry.valid() || entry.delay < smallest_entry.delay) { + smallest_entry = entry; + } + } + + return smallest_entry; +} + +/* returns a cost entry that represents the average of all the recorded entries */ +Cost_Entry Expansion_Cost_Entry::get_average_entry() const { + float avg_delay = 0; + float avg_congestion = 0; + + for (auto cost_entry : this->cost_vector) { + avg_delay += cost_entry.delay; + avg_congestion += cost_entry.congestion; + } + + avg_delay /= (float)this->cost_vector.size(); + avg_congestion /= (float)this->cost_vector.size(); + + return Cost_Entry(avg_delay, avg_congestion); +} + +/* returns a cost entry that represents the geomean of all the recorded entries */ +Cost_Entry Expansion_Cost_Entry::get_geomean_entry() const { + float geomean_delay = 0; + float geomean_cong = 0; + for (auto cost_entry : this->cost_vector) { + geomean_delay += log(cost_entry.delay); + geomean_cong += log(cost_entry.congestion); + } + + geomean_delay = exp(geomean_delay / (float)this->cost_vector.size()); + geomean_cong = exp(geomean_cong / (float)this->cost_vector.size()); + + return Cost_Entry(geomean_delay, geomean_cong); +} + +/* returns a cost entry that represents the medial of all recorded entries */ +Cost_Entry Expansion_Cost_Entry::get_median_entry() const { + /* find median by binning the delays of all entries and then chosing the bin + * with the largest number of entries */ + + int num_bins = 10; + + /* find entries with smallest and largest delays */ + Cost_Entry min_del_entry; + Cost_Entry max_del_entry; + for (auto entry : this->cost_vector) { + if (!min_del_entry.valid() || entry.delay < min_del_entry.delay) { + min_del_entry = entry; + } + if (!max_del_entry.valid() || entry.delay > max_del_entry.delay) { + max_del_entry = entry; + } + } + + /* get the bin size */ + float delay_diff = max_del_entry.delay - min_del_entry.delay; + float bin_size = delay_diff / (float)num_bins; + + /* sort the cost entries into bins */ + std::vector > entry_bins(num_bins, std::vector()); + for (auto entry : this->cost_vector) { + float bin_num = floor((entry.delay - min_del_entry.delay) / bin_size); + + VTR_ASSERT(vtr::nint(bin_num) >= 0 && vtr::nint(bin_num) <= num_bins); + if (vtr::nint(bin_num) == num_bins) { + /* largest entry will otherwise have an out-of-bounds bin number */ + bin_num -= 1; + } + entry_bins[vtr::nint(bin_num)].push_back(entry); + } + + /* find the bin with the largest number of elements */ + int largest_bin = 0; + int largest_size = 0; + for (int ibin = 0; ibin < num_bins; ibin++) { + if (entry_bins[ibin].size() > (unsigned)largest_size) { + largest_bin = ibin; + largest_size = (unsigned)entry_bins[ibin].size(); + } + } + + /* get the representative delay of the largest bin */ + Cost_Entry representative_entry = entry_bins[largest_bin][0]; + + return representative_entry; +} + +/* iterates over the children of the specified node and selectively pushes them onto the priority queue */ +void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, + std::vector& node_visited_costs, + std::vector& node_expanded, + std::priority_queue& pq) { + auto& device_ctx = g_vpr_ctx.device(); + + int parent_ind = parent_entry.rr_node_ind; + + auto& parent_node = device_ctx.rr_nodes[parent_ind]; + + for (int iedge = 0; iedge < parent_node.num_edges(); iedge++) { + int child_node_ind = parent_node.edge_sink_node(iedge); + int switch_ind = parent_node.edge_switch(iedge); + + /* skip this child if it has already been expanded from */ + if (node_expanded[child_node_ind]) { + continue; + } + + util::PQ_Entry child_entry(child_node_ind, switch_ind, parent_entry.delay, + parent_entry.R_upstream, parent_entry.congestion_upstream, false); + + VTR_ASSERT(child_entry.cost >= 0); + + /* skip this child if it has been visited with smaller cost */ + if (node_visited_costs[child_node_ind] >= 0 && node_visited_costs[child_node_ind] < child_entry.cost) { + continue; + } + + /* finally, record the cost with which the child was visited and put the child entry on the queue */ + node_visited_costs[child_node_ind] = child_entry.cost; + pq.push(child_entry); + } +} diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h new file mode 100644 index 00000000000..af37006669a --- /dev/null +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -0,0 +1,144 @@ +#ifndef ROUTER_LOOKAHEAD_MAP_UTILS_H_ +#define ROUTER_LOOKAHEAD_MAP_UTILS_H_ +/* + * The router lookahead provides an estimate of the cost from an intermediate node to the target node + * during directed (A*-like) routing. + * + * The VPR 7.0 lookahead (route/route_timing.c ==> get_timing_driven_expected_cost) lower-bounds the remaining delay and + * congestion by assuming that a minimum number of wires, of the same type as the current node being expanded, can be used + * to complete the route. While this method is efficient, it can run into trouble with architectures that use + * multiple interconnected wire types. + * + * The lookahead in this file pre-computes delay/congestion costs up and to the right of a starting tile. This generates + * delay/congestion tables for {CHANX, CHANY} channel types, over all wire types defined in the architecture file. + * See Section 3.2.4 in Oleg Petelin's MASc thesis (2016) for more discussion. + * + */ + +#include +#include +#include +#include +#include "vpr_types.h" + +/* when a list of delay/congestion entries at a coordinate in Cost_Entry is boiled down to a single + * representative entry, this enum is passed-in to specify how that representative entry should be + * calculated */ +enum e_representative_entry_method { + FIRST = 0, //the first cost that was recorded + SMALLEST, //the smallest-delay cost recorded + AVERAGE, + GEOMEAN, + MEDIAN +}; + +/* f_cost_map is an array of these cost entries that specifies delay/congestion estimates + * to travel relative x/y distances */ +class Cost_Entry { + public: + float delay; + float congestion; + + Cost_Entry() { + delay = std::numeric_limits::infinity(); + congestion = std::numeric_limits::infinity(); + } + Cost_Entry(float set_delay, float set_congestion) { + delay = set_delay; + congestion = set_congestion; + } + + bool valid() const { + return std::isfinite(delay) && std::isfinite(congestion); + } +}; + +/* a class that stores delay/congestion information for a given relative coordinate during the Dijkstra expansion. + * since it stores multiple cost entries, it is later boiled down to a single representative cost entry to be stored + * in the final lookahead cost map */ +class Expansion_Cost_Entry { + private: + std::vector cost_vector; + + Cost_Entry get_smallest_entry() const; + Cost_Entry get_average_entry() const; + Cost_Entry get_geomean_entry() const; + Cost_Entry get_median_entry() const; + + public: + void add_cost_entry(e_representative_entry_method method, + float add_delay, + float add_congestion) { + Cost_Entry cost_entry(add_delay, add_congestion); + if (method == SMALLEST) { + /* taking the smallest-delay entry anyway, so no need to push back multple entries */ + if (this->cost_vector.empty()) { + this->cost_vector.push_back(cost_entry); + } else { + if (add_delay < this->cost_vector[0].delay) { + this->cost_vector[0] = cost_entry; + } + } + } else { + this->cost_vector.push_back(cost_entry); + } + } + void clear_cost_entries() { + this->cost_vector.clear(); + } + + Cost_Entry get_representative_cost_entry(e_representative_entry_method method) const { + Cost_Entry entry; + + if (!cost_vector.empty()) { + switch (method) { + case FIRST: + entry = cost_vector[0]; + break; + case SMALLEST: + entry = this->get_smallest_entry(); + break; + case AVERAGE: + entry = this->get_average_entry(); + break; + case GEOMEAN: + entry = this->get_geomean_entry(); + break; + case MEDIAN: + entry = this->get_median_entry(); + break; + default: + break; + } + } + return entry; + } +}; + +namespace util { +/* a class that represents an entry in the Dijkstra expansion priority queue */ +class PQ_Entry { + public: + int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents + float cost; //the cost of the path to get to this node + + /* store backward delay, R and congestion info */ + float delay; + float R_upstream; + float congestion_upstream; + + PQ_Entry(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, float parent_R_upstream, float parent_congestion_upstream, bool starting_node); + + bool operator<(const PQ_Entry& obj) const { + /* inserted into max priority queue so want queue entries with a lower cost to be greater */ + return (this->cost > obj.cost); + } +}; +} // namespace util + +void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, + std::vector& node_visited_costs, + std::vector& node_expanded, + std::priority_queue& pq); + +#endif diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index df1bb8b0967..d714d6d2006 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -32,6 +32,7 @@ #include "rr_graph_writer.h" #include "rr_graph_reader.h" #include "router_lookahead_map.h" +#include "connection_box_lookahead_map.h" #include "rr_graph_clock.h" #include "rr_types.h" diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index e9380b12d7e..aafd94afec4 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -53,6 +53,7 @@ void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid); void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); +void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches); void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_rr_node_indices(const DeviceGrid& grid); @@ -130,6 +131,13 @@ void load_rr_file(const t_graph_type graph_type, t_chan_width nodes_per_chan; process_channels(nodes_per_chan, grid, next_component, loc_data); + next_component = get_first_child(rr_graph, "connection_boxes", loc_data, OPTIONAL); + if (next_component != nullptr) { + process_connection_boxes(next_component, loc_data); + } else { + device_ctx.connection_boxes.clear(); + } + /* Decode the graph_type */ bool is_global_graph = (GRAPH_GLOBAL == graph_type ? true : false); @@ -143,6 +151,7 @@ void load_rr_file(const t_graph_type graph_type, int num_rr_nodes = count_children(next_component, "node", loc_data); device_ctx.rr_nodes.resize(num_rr_nodes); + device_ctx.connection_boxes.resize_nodes(num_rr_nodes); process_nodes(next_component, loc_data); /* Loads edges, switches, and node look up tables*/ @@ -177,6 +186,7 @@ void load_rr_file(const t_graph_type graph_type, device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); + device_ctx.connection_boxes.create_sink_back_ref(); } catch (pugiutil::XmlError& e) { vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what()); @@ -304,6 +314,18 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { node.set_type(OPIN); } else if (strcmp(node_type, "IPIN") == 0) { node.set_type(IPIN); + + pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "connection_box", loc_data, OPTIONAL); + if (connection_boxSubnode) { + int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); + int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); + int id = get_attribute(connection_boxSubnode, "id", loc_data).as_int(); + + device_ctx.connection_boxes.add_connection_box(inode, + ConnectionBoxId(id), + std::make_pair(x, y)); + } + } else { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Valid inputs for class types are \"CHANX\", \"CHANY\",\"SOURCE\", \"SINK\",\"OPIN\", and \"IPIN\"."); @@ -323,6 +345,15 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { } } + pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "canonical_loc", loc_data, OPTIONAL); + if (connection_boxSubnode) { + int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); + int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); + + device_ctx.connection_boxes.add_canonical_loc(inode, + std::make_pair(x, y)); + } + node.set_capacity(get_attribute(rr_node, "capacity", loc_data).as_float()); //-------------- @@ -884,3 +915,26 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, rr_node = rr_node.next_sibling(rr_node.name()); } } + +void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { + auto& device_ctx = g_vpr_ctx.mutable_device(); + + int x_dim = get_attribute(parent, "x_dim", loc_data).as_int(0); + int y_dim = get_attribute(parent, "y_dim", loc_data).as_int(0); + int num_boxes = get_attribute(parent, "num_boxes", loc_data).as_int(0); + VTR_ASSERT(num_boxes >= 0); + + pugi::xml_node connection_box = get_first_child(parent, "connection_box", loc_data); + std::vector boxes(num_boxes); + while (connection_box) { + int id = get_attribute(connection_box, "id", loc_data).as_int(-1); + const char* name = get_attribute(connection_box, "name", loc_data).as_string(nullptr); + VTR_ASSERT(id >= 0 && id < num_boxes); + VTR_ASSERT(boxes.at(id).name == ""); + boxes.at(id).name = std::string(name); + + connection_box = connection_box.next_sibling(connection_box.name()); + } + + device_ctx.connection_boxes.reset_boxes(std::make_pair(x_dim, y_dim), boxes); +} diff --git a/vpr/src/route/rr_node.h b/vpr/src/route/rr_node.h index cc9df7a42f8..9ff480b0848 100644 --- a/vpr/src/route/rr_node.h +++ b/vpr/src/route/rr_node.h @@ -173,7 +173,7 @@ class t_rr_node { t_edge_size edges_capacity_ = 0; uint8_t num_non_configurable_edges_ = 0; - int8_t cost_index_ = -1; + uint16_t cost_index_ = -1; int16_t rc_index_ = -1; int16_t xlow_ = -1; From cb7b946e4d47edce1559cfa257dd8f1e342706a1 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 15 Aug 2019 18:09:05 -0700 Subject: [PATCH 036/107] Complete connection box lookahead to be aware of connection box. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- libs/libvtrcapnproto/connection_map.capnp | 4 +- .../route/connection_box_lookahead_map.cpp | 309 ++++++++++-------- 2 files changed, 177 insertions(+), 136 deletions(-) diff --git a/libs/libvtrcapnproto/connection_map.capnp b/libs/libvtrcapnproto/connection_map.capnp index ac03ddfc9c0..1ca672108c8 100644 --- a/libs/libvtrcapnproto/connection_map.capnp +++ b/libs/libvtrcapnproto/connection_map.capnp @@ -13,7 +13,7 @@ struct VprVector2D { } struct VprCostMap { - costMap @0 :List(Matrix.Matrix(VprCostEntry)); - offset @1 :List(VprVector2D); + costMap @0 :Matrix.Matrix((Matrix.Matrix(VprCostEntry))); + offset @1 :Matrix.Matrix(VprVector2D); segmentMap @2 :List(Int64); } diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index dad1b8d2b93..99ca45789ba 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -13,11 +13,13 @@ #include "route_timing.h" -#include "capnp/serialize.h" -#include "connection_map.capnp.h" -#include "ndmatrix_serdes.h" -#include "mmap_file.h" -#include "serdes_utils.h" +#ifdef VTR_ENABLE_CAPNPROTO +# include "capnp/serialize.h" +# include "connection_map.capnp.h" +# include "ndmatrix_serdes.h" +# include "mmap_file.h" +# include "serdes_utils.h" +#endif /* we're profiling routing cost over many tracks for each wire type, so we'll * have many cost entries at each |dx|,|dy| offset. There are many ways to @@ -39,17 +41,17 @@ static int signum(int x) { return 0; } -typedef std::vector, Cost_Entry>> t_routing_cost_map; +typedef std::vector, std::pair, Cost_Entry, ConnectionBoxId>> t_routing_cost_map; static void run_dijkstra(int start_node_ind, - t_routing_cost_map* cost_map); + t_routing_cost_map* routing_cost_map); class CostMap { public: - void set_segment_count(size_t seg_count) { + void set_counts(size_t seg_count, size_t box_count) { cost_map_.clear(); offset_.clear(); - cost_map_.resize(seg_count); - offset_.resize(seg_count); + cost_map_.resize({seg_count, box_count}); + offset_.resize({seg_count, box_count}); const auto& device_ctx = g_vpr_ctx.device(); segment_map_.resize(device_ctx.rr_nodes.size()); @@ -67,11 +69,11 @@ class CostMap { return segment_map_[from_node_ind]; } - Cost_Entry find_cost(int from_seg_index, int delta_x, int delta_y) const { + Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); - int dx = delta_x - offset_[from_seg_index].first; - int dy = delta_y - offset_[from_seg_index].second; - const auto& cost_map = cost_map_[from_seg_index]; + int dx = delta_x - offset_[from_seg_index][size_t(box_id)].first; + int dy = delta_y - offset_[from_seg_index][size_t(box_id)].second; + const auto& cost_map = cost_map_[from_seg_index][size_t(box_id)]; if (dx < 0) { dx = 0; @@ -87,12 +89,21 @@ class CostMap { dy = cost_map.dim_size(1) - 1; } - return cost_map_[from_seg_index][dx][dy]; + return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; } void set_cost_map(int from_seg_index, const t_routing_cost_map& cost_map, e_representative_entry_method method) { + const auto& device_ctx = g_vpr_ctx.device(); + for (size_t box_id = 0; + box_id < device_ctx.connection_boxes.num_connection_box_types(); + ++box_id) { + set_cost_map(from_seg_index, ConnectionBoxId(box_id), cost_map, method); + } + } + + void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const t_routing_cost_map& cost_map, e_representative_entry_method method) { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); // Find coordinate offset for this segment. @@ -101,15 +112,18 @@ class CostMap { int max_dx = 0; int max_dy = 0; for (const auto& entry : cost_map) { - min_dx = std::min(entry.first.first, min_dx); - min_dy = std::min(entry.first.second, min_dy); + if (std::get<3>(entry) != box_id) { + continue; + } + min_dx = std::min(std::get<1>(entry).first, min_dx); + min_dy = std::min(std::get<1>(entry).second, min_dy); - max_dx = std::max(entry.first.first, max_dx); - max_dy = std::max(entry.first.second, max_dy); + max_dx = std::max(std::get<1>(entry).first, max_dx); + max_dy = std::max(std::get<1>(entry).second, max_dy); } - offset_[from_seg_index].first = min_dx; - offset_[from_seg_index].second = min_dy; + offset_[from_seg_index][size_t(box_id)].first = min_dx; + offset_[from_seg_index][size_t(box_id)].second = min_dy; size_t dim_x = max_dx - min_dx + 1; size_t dim_y = max_dy - min_dy + 1; @@ -117,41 +131,45 @@ class CostMap { {dim_x, dim_y}); for (const auto& entry : cost_map) { - int x = entry.first.first - min_dx; - int y = entry.first.second - min_dy; + if (std::get<3>(entry) != box_id) { + continue; + } + int x = std::get<1>(entry).first - min_dx; + int y = std::get<1>(entry).second - min_dy; expansion_cost_map[x][y].add_cost_entry( - method, entry.second.delay, - entry.second.congestion); + method, std::get<2>(entry).delay, + std::get<2>(entry).congestion); } - cost_map_[from_seg_index] = vtr::NdMatrix( + cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( {dim_x, dim_y}); /* set the lookahead cost map entries with a representative cost * entry from routing_cost_map */ for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { - cost_map_[from_seg_index][ix][iy] = expansion_cost_map[ix][iy].get_representative_cost_entry(method); + cost_map_[from_seg_index][size_t(box_id)][ix][iy] = expansion_cost_map[ix][iy].get_representative_cost_entry(method); } } /* find missing cost entries and fill them in by copying a nearby cost entry */ for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { - Cost_Entry cost_entry = cost_map_[from_seg_index][ix][iy]; + Cost_Entry cost_entry = cost_map_[from_seg_index][size_t(box_id)][ix][iy]; if (!cost_entry.valid()) { Cost_Entry copied_entry = get_nearby_cost_entry( from_seg_index, - offset_[from_seg_index].first + ix, - offset_[from_seg_index].second + iy); - cost_map_[from_seg_index][ix][iy] = copied_entry; + box_id, + offset_[from_seg_index][size_t(box_id)].first + ix, + offset_[from_seg_index][size_t(box_id)].second + iy); + cost_map_[from_seg_index][size_t(box_id)][ix][iy] = copied_entry; } } } } - Cost_Entry get_nearby_cost_entry(int segment_index, int x, int y) { + Cost_Entry get_nearby_cost_entry(int segment_index, ConnectionBoxId box_id, int x, int y) { /* compute the slope from x,y to 0,0 and then move towards 0,0 by one * unit to get the coordinates of the cost entry to be copied */ @@ -172,7 +190,7 @@ class CostMap { } } - Cost_Entry copy_entry = find_cost(segment_index, copy_x, copy_y); + Cost_Entry copy_entry = find_cost(segment_index, box_id, copy_x, copy_y); /* if the entry to be copied is also empty, recurse */ if (copy_entry.valid()) { @@ -181,41 +199,31 @@ class CostMap { return Cost_Entry(); } - return get_nearby_cost_entry(segment_index, copy_x, copy_y); - } - - void print_cost_map(const std::vector& segment_inf, - const char* fname) { - FILE* fp = vtr::fopen(fname, "w"); - for (size_t iseg = 0; iseg < cost_map_.size(); iseg++) { - fprintf(fp, "Seg %s(%zu) (%d, %d)\n", segment_inf.at(iseg).name.c_str(), - iseg, - offset_[iseg].first, - offset_[iseg].second); - for (size_t iy = 0; iy < cost_map_[iseg].dim_size(1); iy++) { - for (size_t ix = 0; ix < cost_map_[iseg].dim_size(0); ix++) { - fprintf(fp, "%.4g,\t", - cost_map_[iseg][ix][iy].delay); - } - fprintf(fp, "\n"); - } - fprintf(fp, "\n\n"); - } - - fclose(fp); + return get_nearby_cost_entry(segment_index, box_id, copy_x, copy_y); } void read(const std::string& file); void write(const std::string& file) const; private: - std::vector> cost_map_; - std::vector> offset_; + vtr::NdMatrix, 2> cost_map_; + vtr::NdMatrix, 2> offset_; std::vector segment_map_; }; static CostMap g_cost_map; +const std::vector& get_rr_node_indcies(t_rr_type rr_type, int start_x, int start_y) { + const auto& device_ctx = g_vpr_ctx.device(); + if (rr_type == CHANX) { + return device_ctx.rr_node_indices[rr_type][start_y][start_x][0]; + } else if (rr_type == CHANY) { + return device_ctx.rr_node_indices[rr_type][start_x][start_y][0]; + } else { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown channel type %d", rr_type); + } +} + class StartNode { public: StartNode(int start_x, int start_y, t_rr_type rr_type, int seg_index) @@ -226,7 +234,8 @@ class StartNode { , index_(0) {} int get_next_node() { const auto& device_ctx = g_vpr_ctx.device(); - const std::vector& channel_node_list = device_ctx.rr_node_indices[rr_type_][start_x_][start_y_][0]; + const std::vector& channel_node_list = get_rr_node_indcies( + rr_type_, start_x_, start_y_); for (; index_ < channel_node_list.size(); index_++) { int node_ind = channel_node_list[index_]; @@ -272,13 +281,45 @@ static constexpr int kMinProfile = 1; // - kMaxProfile is exceeded. static constexpr int kMaxProfile = 7; +static int search_at(int iseg, int start_x, int start_y, t_routing_cost_map* cost_map) { + int count = 0; + int dx = 0; + int dy = 0; + + while ((count == 0 && dx < kMaxProfile) || dy <= kMinProfile) { + for (e_rr_type chan_type : {CHANX, CHANY}) { + StartNode start_node(start_x + dx, start_y + dy, chan_type, iseg); + VTR_LOG("Searching for %d at (%d, %d)\n", iseg, start_x + dx, start_y + dy); + + for (int start_node_ind = start_node.get_next_node(); + start_node_ind != UNDEFINED; + start_node_ind = start_node.get_next_node()) { + count += 1; + + /* run Dijkstra's algorithm */ + run_dijkstra(start_node_ind, cost_map); + } + } + + if (dy < dx) { + dy += 1; + } else { + dx += 1; + } + } + + return count; +} + static void compute_connection_box_lookahead( const std::vector& segment_inf) { size_t num_segments = segment_inf.size(); vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); /* free previous delay map and allocate new one */ - g_cost_map.set_segment_count(segment_inf.size()); + auto& device_ctx = g_vpr_ctx.device(); + g_cost_map.set_counts(segment_inf.size(), + device_ctx.connection_boxes.num_connection_box_types()); /* run Dijkstra's algorithm for each segment type & channel type combination */ for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { @@ -288,48 +329,33 @@ static void compute_connection_box_lookahead( t_routing_cost_map cost_map; int count = 0; - - int dx = 0; - int dy = 0; - //int start_x = vtr::nint(device_ctx.grid.width()/2); - //int start_y = vtr::nint(device_ctx.grid.height()/2); - int start_x = REF_X; - int start_y = REF_Y; - while ((count == 0 && dx < kMaxProfile) || dy <= kMinProfile) { - for (e_rr_type chan_type : {CHANX, CHANY}) { - StartNode start_node(start_x + dx, start_y + dy, chan_type, iseg); - - for (int start_node_ind = start_node.get_next_node(); - start_node_ind != UNDEFINED; - start_node_ind = start_node.get_next_node()) { - count += 1; - - /* run Dijkstra's algorithm */ - run_dijkstra(start_node_ind, &cost_map); - } - } - - if (dy < dx) { - dy += 1; - } else { - dx += 1; - } - } + count += search_at(iseg, REF_X, REF_Y, &cost_map); + count += search_at(iseg, REF_Y, REF_X, &cost_map); + count += search_at(iseg, 1, 1, &cost_map); + count += search_at(iseg, 76, 1, &cost_map); + count += search_at(iseg, 25, 25, &cost_map); + count += search_at(iseg, 25, 27, &cost_map); + count += search_at(iseg, 75, 26, &cost_map); if (count == 0) { VTR_LOG_WARN("Segment %s(%d) found no start_node_ind\n", segment_inf[iseg].name.c_str(), iseg); } +#if 0 + for(const auto & e : cost_map) { + VTR_LOG("%d -> %d (%d, %d): %g, %g\n", + std::get<0>(e).first, std::get<0>(e).second, + std::get<1>(e).first, std::get<1>(e).second, + std::get<2>(e).delay, std::get<2>(e).congestion); + } +#endif + /* boil down the cost list in routing_cost_map at each coordinate to a * representative cost entry and store it in the lookahead cost map */ g_cost_map.set_cost_map(iseg, cost_map, REPRESENTATIVE_ENTRY_METHOD); } - - if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_LOOKAHEAD_MAP)) { - g_cost_map.print_cost_map(segment_inf, getEchoFileName(E_ECHO_LOOKAHEAD_MAP)); - } } static float get_connection_box_lookahead_map_cost(int from_node_ind, @@ -368,23 +394,15 @@ static float get_connection_box_lookahead_map_cost(int from_node_ind, } } - if (device_ctx.rr_nodes[to_node_ind].type() == IPIN) { - ConnectionBoxId box_id; - std::pair box_location; - bool found = device_ctx.connection_boxes.find_connection_box( - to_node_ind, &box_id, &box_location); - if (!found) { - VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", to_node_ind); - } - - to_location = box_location; - } else { - const std::pair* to_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(to_node_ind); - if (!to_canonical_loc) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical loc for %d", to_node_ind); - } - - to_location = *to_canonical_loc; + if (device_ctx.rr_nodes[to_node_ind].type() != IPIN) { + VPR_THROW(VPR_ERROR_ROUTE, "Not an IPIN/SINK, is %d", to_node_ind); + } + ConnectionBoxId box_id; + std::pair box_location; + bool found = device_ctx.connection_boxes.find_connection_box( + to_node_ind, &box_id, &box_location); + if (!found) { + VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", to_node_ind); } const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(from_node_ind); @@ -393,11 +411,11 @@ static float get_connection_box_lookahead_map_cost(int from_node_ind, from_node_ind, to_node_ind); } - ssize_t dx = ssize_t(from_canonical_loc->first) - ssize_t(to_location.first); - ssize_t dy = ssize_t(from_canonical_loc->second) - ssize_t(to_location.second); + ssize_t dx = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); + ssize_t dy = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); int from_seg_index = g_cost_map.node_to_segment(from_node_ind); - Cost_Entry cost_entry = g_cost_map.find_cost(from_seg_index, dx, dy); + Cost_Entry cost_entry = g_cost_map.find_cost(from_seg_index, box_id, dx, dy); float expected_delay = cost_entry.delay; float expected_congestion = cost_entry.congestion; @@ -458,11 +476,13 @@ static void run_dijkstra(int start_node_ind, int delta_x = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); int delta_y = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); - routing_cost_map->push_back(std::make_pair( + routing_cost_map->push_back(std::make_tuple( + std::make_pair(start_node_ind, node_ind), std::make_pair(delta_x, delta_y), Cost_Entry( current.delay, - current.congestion_upstream))); + current.congestion_upstream), + box_id)); } expand_dijkstra_neighbours(current, node_visited_costs, node_expanded, pq); @@ -493,6 +513,17 @@ float ConnectionBoxMapLookahead::get_expected_cost( } } +#ifndef VTR_ENABLE_CAPNPROTO + +void ConnectionBoxMapLookahead::read(const std::string& file) { + VPR_THROW(VPR_ERROR_ROUTE, "ConnectionBoxMapLookahead::read not implemented"); +} +void ConnectionBoxMapLookahead::write(const std::string& file) const { + VPR_THROW(VPR_ERROR_ROUTE, "ConnectionBoxMapLookahead::write not implemented"); +} + +#else + void ConnectionBoxMapLookahead::read(const std::string& file) { g_cost_map.read(file); } @@ -510,6 +541,27 @@ static void FromCostEntry(VprCostEntry::Builder* out, const Cost_Entry& in) { out->setCongestion(in.congestion); } +static void ToVprVector2D(std::pair* out, const VprVector2D::Reader& in) { + *out = std::make_pair(in.getX(), in.getY()); +} + +static void FromVprVector2D(VprVector2D::Builder* out, const std::pair& in) { + out->setX(in.first); + out->setY(in.second); +} + +static void ToMatrixCostEntry(vtr::NdMatrix* out, + const Matrix::Reader& in) { + ToNdMatrix<2, VprCostEntry, Cost_Entry>(out, in, ToCostEntry); +} + +static void FromMatrixCostEntry( + Matrix::Builder* out, + const vtr::NdMatrix& in) { + FromNdMatrix<2, VprCostEntry, Cost_Entry>( + out, in, FromCostEntry); +} + void CostMap::read(const std::string& file) { MmapFile f(file); ::capnp::FlatArrayMessageReader reader(f.getData()); @@ -527,20 +579,14 @@ void CostMap::read(const std::string& file) { { const auto& offset = cost_map.getOffset(); - offset_.resize(offset.size()); - auto dst_iter = offset_.begin(); - for (const auto& src : offset) { - *dst_iter++ = std::make_pair(src.getX(), src.getY()); - } + ToNdMatrix<2, VprVector2D, std::pair>( + &offset_, offset, ToVprVector2D); } { const auto& cost_maps = cost_map.getCostMap(); - cost_map_.resize(cost_maps.size()); - auto dst_iter = cost_map_.begin(); - for (const auto& src : cost_maps) { - ToNdMatrix<2, VprCostEntry, Cost_Entry>(&(*dst_iter++), src, ToCostEntry); - } + ToNdMatrix<2, Matrix, vtr::NdMatrix>( + &cost_map_, cost_maps, ToMatrixCostEntry); } } @@ -557,22 +603,17 @@ void CostMap::write(const std::string& file) const { } { - auto offset = cost_map.initOffset(offset_.size()); - for (size_t i = 0; i < offset_.size(); ++i) { - auto elem = offset[i]; - elem.setX(offset_[i].first); - elem.setY(offset_[i].second); - } + auto offset = cost_map.initOffset(); + FromNdMatrix<2, VprVector2D, std::pair>( + &offset, offset_, FromVprVector2D); } { - auto cost_maps = cost_map.initCostMap(cost_map_.size()); - for (size_t i = 0; i < cost_map_.size(); ++i) { - Matrix::Builder elem = cost_maps[i]; - FromNdMatrix<2, VprCostEntry, Cost_Entry>( - &elem, cost_map_[i], FromCostEntry); - } + auto cost_maps = cost_map.initCostMap(); + FromNdMatrix<2, Matrix, vtr::NdMatrix>( + &cost_maps, cost_map_, FromMatrixCostEntry); } writeMessageToFile(file, &builder); } +#endif From 2a3c53690fa5643930690a08b958871ef7da5cfc Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 27 Sep 2019 11:08:58 -0700 Subject: [PATCH 037/107] Mark file location function as static. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/connection_box_lookahead_map.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 99ca45789ba..d7cd1b02c2b 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -213,7 +213,7 @@ class CostMap { static CostMap g_cost_map; -const std::vector& get_rr_node_indcies(t_rr_type rr_type, int start_x, int start_y) { +static const std::vector& get_rr_node_indcies(t_rr_type rr_type, int start_x, int start_y) { const auto& device_ctx = g_vpr_ctx.device(); if (rr_type == CHANX) { return device_ctx.rr_node_indices[rr_type][start_y][start_x][0]; From 9bbd145054cd4744b561938d2aee5e2786db72ba Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 2 Oct 2019 10:57:12 -0700 Subject: [PATCH 038/107] Add pugixml namespace to OPTIONAL's now that using is gone. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/rr_graph_reader.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index aafd94afec4..c2544dc4720 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -131,7 +131,7 @@ void load_rr_file(const t_graph_type graph_type, t_chan_width nodes_per_chan; process_channels(nodes_per_chan, grid, next_component, loc_data); - next_component = get_first_child(rr_graph, "connection_boxes", loc_data, OPTIONAL); + next_component = get_first_child(rr_graph, "connection_boxes", loc_data, pugiutil::OPTIONAL); if (next_component != nullptr) { process_connection_boxes(next_component, loc_data); } else { @@ -315,7 +315,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { } else if (strcmp(node_type, "IPIN") == 0) { node.set_type(IPIN); - pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "connection_box", loc_data, OPTIONAL); + pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "connection_box", loc_data, pugiutil::OPTIONAL); if (connection_boxSubnode) { int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); @@ -345,7 +345,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { } } - pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "canonical_loc", loc_data, OPTIONAL); + pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "canonical_loc", loc_data, pugiutil::OPTIONAL); if (connection_boxSubnode) { int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); From ad22d78e592e943ad030174434b6a22e77ef55ed Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 11 Oct 2019 16:28:47 -0700 Subject: [PATCH 039/107] Add option for search locations. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- utils/route_diag/src/main.cpp | 6 ++-- vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/read_options.cpp | 5 +++ vpr/src/base/read_options.h | 1 + vpr/src/base/vpr_api.cpp | 3 +- vpr/src/base/vpr_context.h | 2 +- vpr/src/base/vpr_types.h | 1 + vpr/src/place/timing_place_lookup.cpp | 3 +- .../route/connection_box_lookahead_map.cpp | 35 +++++++++++++------ vpr/src/route/connection_box_lookahead_map.h | 2 +- vpr/src/route/route_timing.cpp | 9 +++-- vpr/src/route/router_lookahead.cpp | 16 +++++---- vpr/src/route/router_lookahead.h | 17 +++++---- 13 files changed, 70 insertions(+), 31 deletions(-) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index ee1c467d17c..30c4fa09773 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -97,7 +97,8 @@ static void do_one_route(int source_node, int sink_node, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf + segment_inf, + router_opts.lookahead_search_locations ); t_heap* cheapest = timing_driven_route_connection_from_route_tree(rt_root, sink_node, cost_params, bounding_box, *router_lookahead, modified_rr_node_inf, router_stats); @@ -139,7 +140,8 @@ static void profile_source(int source_rr_node, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf + segment_inf, + router_opts.lookahead_search_locations ); RouterDelayProfiler profiler(router_lookahead.get()); diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 4fd21004eb5..0c82c04d89a 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -358,6 +358,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->doRouting = STAGE_DO; } RouterOpts->routing_failure_predictor = Options.routing_failure_predictor; + RouterOpts->lookahead_search_locations = Options.lookahead_search_locations; RouterOpts->routing_budgets_algorithm = Options.routing_budgets_algorithm; RouterOpts->save_routing_per_iteration = Options.save_routing_per_iteration; RouterOpts->congested_routing_iteration_threshold_frac = Options.congested_routing_iteration_threshold_frac; diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index b9bbedf30c3..3ccbe318681 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1520,6 +1520,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.lookahead_search_locations, "--lookahead_search_locations") + .help("Semi-colon seperated x,y coordinates to use for lookahead search coordinates.") + .default_value("") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.max_criticality, "--max_criticality") .help( "Sets the maximum fraction of routing cost derived from delay (vs routability) for any net." diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 97d320abbe3..c8caa7116c4 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -152,6 +152,7 @@ struct t_options { argparse::ArgValue router_max_convergence_count; argparse::ArgValue router_reconvergence_cpd_threshold; argparse::ArgValue router_first_iteration_timing_report_file; + argparse::ArgValue lookahead_search_locations; /* Analysis options */ argparse::ArgValue full_stats; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index f2900d0d299..63952666e5c 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -738,7 +738,8 @@ RouteStatus vpr_route_fixed_W(t_vpr_setup& vpr_setup, vpr_setup.RouterOpts.lookahead_type, vpr_setup.RouterOpts.write_router_lookahead, vpr_setup.RouterOpts.read_router_lookahead, - vpr_setup.Segments); + vpr_setup.Segments, + vpr_setup.RouterOpts.lookahead_search_locations); } vtr::ScopedStartFinishTimer timer("Routing"); diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 122fa95229a..55e3548c0c7 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -304,7 +304,7 @@ struct RoutingContext : public Context { // Cache of router lookahead object. // // Cache key: (lookahead type, read lookahead (if any), segment definitions). - vtr::Cache>, + vtr::Cache, std::string>, RouterLookahead> cached_router_lookahead_; }; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index b23080cc4f4..fa048c56f48 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -949,6 +949,7 @@ struct t_router_opts { float reconvergence_cpd_threshold; std::string first_iteration_timing_report_file; bool strict_checks; + std::string lookahead_search_locations; std::string write_router_lookahead; std::string read_router_lookahead; diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 4aa439aab16..18402399ea2 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -147,7 +147,8 @@ std::unique_ptr compute_place_delay_model(const t_placer_opts& router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf); + segment_inf, + router_opts.lookahead_search_locations); RouterDelayProfiler route_profiler(router_lookahead); int longest_length = get_longest_segment_length(segment_inf); diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index d7cd1b02c2b..733d0c171be 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -312,7 +312,8 @@ static int search_at(int iseg, int start_x, int start_y, t_routing_cost_map* cos } static void compute_connection_box_lookahead( - const std::vector& segment_inf) { + const std::vector& segment_inf, + const std::string& search_locations_str) { size_t num_segments = segment_inf.size(); vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); @@ -321,6 +322,24 @@ static void compute_connection_box_lookahead( g_cost_map.set_counts(segment_inf.size(), device_ctx.connection_boxes.num_connection_box_types()); + std::vector> search_locations; + for (const auto& loc_str : vtr::split(search_locations_str, ";")) { + auto loc_parts = vtr::split(loc_str, ","); + if (loc_parts.size() != 2) { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Expected two parts from loc_str %s, got %d", + loc_str.c_str(), loc_parts.size()); + } + + std::pair loc; + loc.first = vtr::atoi(loc_parts[0]); + loc.second = vtr::atoi(loc_parts[1]); + search_locations.push_back(loc); + } + + if (search_locations.size() == 0) { + VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "No search locations provided."); + } + /* run Dijkstra's algorithm for each segment type & channel type combination */ for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { VTR_LOG("Creating cost map for %s(%d)\n", @@ -329,13 +348,9 @@ static void compute_connection_box_lookahead( t_routing_cost_map cost_map; int count = 0; - count += search_at(iseg, REF_X, REF_Y, &cost_map); - count += search_at(iseg, REF_Y, REF_X, &cost_map); - count += search_at(iseg, 1, 1, &cost_map); - count += search_at(iseg, 76, 1, &cost_map); - count += search_at(iseg, 25, 25, &cost_map); - count += search_at(iseg, 25, 27, &cost_map); - count += search_at(iseg, 75, 26, &cost_map); + for (const auto loc : search_locations) { + count += search_at(iseg, loc.first, loc.second, &cost_map); + } if (count == 0) { VTR_LOG_WARN("Segment %s(%d) found no start_node_ind\n", @@ -490,8 +505,8 @@ static void run_dijkstra(int start_node_ind, } } -void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf) { - compute_connection_box_lookahead(segment_inf); +void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) { + compute_connection_box_lookahead(segment_inf, lookahead_search_locations); } float ConnectionBoxMapLookahead::get_expected_cost( diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 03e1a140f0b..ff3cee59eee 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -8,7 +8,7 @@ class ConnectionBoxMapLookahead : public RouterLookahead { public: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& segment_inf) override; + void compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) override; void read(const std::string& file) override; void write(const std::string& file) const override; diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index cc738162be4..a9d0465eb68 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -374,7 +374,8 @@ bool try_timing_driven_route(const t_router_opts& router_opts, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf); + segment_inf, + router_opts.lookahead_search_locations); /* * Routing parameters @@ -1513,7 +1514,8 @@ std::vector timing_driven_find_all_shortest_paths_from_route_tree(t_rt_n int target_node = OPEN; auto router_lookahead = make_router_lookahead(e_router_lookahead::NO_OP, /*write_lookahead=*/"", /*read_lookahead=*/"", - /*segment_inf=*/{}); + /*segment_inf=*/{}, + /*lookahead_search_locations=*/""); add_route_tree_to_heap(rt_root, target_node, cost_params, *router_lookahead, router_stats); heap_::build_heap(); // via sifting down everything @@ -1535,7 +1537,8 @@ static std::vector timing_driven_find_all_shortest_paths_from_heap(const RouterStats& router_stats) { auto router_lookahead = make_router_lookahead(e_router_lookahead::NO_OP, /*write_lookahead=*/"", /*read_lookahead=*/"", - /*segment_inf=*/{}); + /*segment_inf=*/{}, + /*lookahead_search_locations=*/""); auto& device_ctx = g_vpr_ctx.device(); std::vector cheapest_paths(device_ctx.rr_nodes.size()); diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp index 80f29911aa9..7ea29db4e65 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead.cpp @@ -28,11 +28,12 @@ std::unique_ptr make_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf) { + const std::vector& segment_inf, + const std::string& lookahead_search_locations) { std::unique_ptr router_lookahead = make_router_lookahead_object(router_lookahead_type); if (read_lookahead.empty()) { - router_lookahead->compute(segment_inf); + router_lookahead->compute(segment_inf, lookahead_search_locations); } else { router_lookahead->read(read_lookahead); } @@ -104,7 +105,8 @@ float MapLookahead::get_expected_cost(int current_node, int target_node, const t } } -void MapLookahead::compute(const std::vector& segment_inf) { +void MapLookahead::compute(const std::vector& segment_inf, + const std::string& lookahead_search_locations) { compute_router_lookahead(segment_inf.size()); } @@ -206,10 +208,11 @@ const RouterLookahead* get_cached_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf) { + const std::vector& segment_inf, + const std::string& lookahead_search_locations) { auto& router_ctx = g_vpr_ctx.routing(); - auto cache_key = std::make_tuple(router_lookahead_type, read_lookahead, segment_inf); + auto cache_key = std::make_tuple(router_lookahead_type, read_lookahead, segment_inf, lookahead_search_locations); // Check if cache is valid. const RouterLookahead* router_lookahead = router_ctx.cached_router_lookahead_.get(cache_key); @@ -225,6 +228,7 @@ const RouterLookahead* get_cached_router_lookahead( router_lookahead_type, write_lookahead, read_lookahead, - segment_inf)); + segment_inf, + lookahead_search_locations)); } } diff --git a/vpr/src/route/router_lookahead.h b/vpr/src/route/router_lookahead.h index 283df54befe..1d797a04484 100644 --- a/vpr/src/route/router_lookahead.h +++ b/vpr/src/route/router_lookahead.h @@ -15,7 +15,7 @@ class RouterLookahead { virtual float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const = 0; // Compute router lookahead (if needed). - virtual void compute(const std::vector& segment_inf) = 0; + virtual void compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) = 0; // Read router lookahead data (if any) from specified file. // May be unimplemented, in which case method should throw an exception. @@ -36,7 +36,8 @@ std::unique_ptr make_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf); + const std::vector& segment_inf, + const std::string& lookahead_search_locations); // Clear router lookahead cache (e.g. when changing or free rrgraph). void invalidate_router_lookahead_cache(); @@ -49,12 +50,14 @@ const RouterLookahead* get_cached_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf); + const std::vector& segment_inf, + const std::string& lookahead_search_locations); class ClassicLookahead : public RouterLookahead { public: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& /*segment_inf*/) override { + void compute(const std::vector& /*segment_inf*/, + const std::string& /*lookahead_search_locations*/) override { } void read(const std::string& /*file*/) override { @@ -71,7 +74,8 @@ class ClassicLookahead : public RouterLookahead { class MapLookahead : public RouterLookahead { protected: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& segment_inf) override; + void compute(const std::vector& segment_inf, + const std::string& /*lookahead_search_locations*/) override; void read(const std::string& /*file*/) override { VPR_THROW(VPR_ERROR_ROUTE, "MapLookahead::read unimplemented"); } @@ -83,7 +87,8 @@ class MapLookahead : public RouterLookahead { class NoOpLookahead : public RouterLookahead { protected: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& /*segment_inf*/) override { + void compute(const std::vector& /*segment_inf*/, + const std::string& /*lookahead_search_locations*/) override { } void read(const std::string& /*file*/) override { VPR_THROW(VPR_ERROR_ROUTE, "Read not supported for NoOpLookahead"); From e9a9a257a70951b0689f9191d43ba55cecad4c5f Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 11 Oct 2019 16:43:37 -0700 Subject: [PATCH 040/107] Add bounds checking when search grid. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/connection_box_lookahead_map.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 733d0c171be..47eea81e7de 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -282,11 +282,20 @@ static constexpr int kMinProfile = 1; static constexpr int kMaxProfile = 7; static int search_at(int iseg, int start_x, int start_y, t_routing_cost_map* cost_map) { + const auto& device_ctx = g_vpr_ctx.device(); + int count = 0; int dx = 0; int dy = 0; while ((count == 0 && dx < kMaxProfile) || dy <= kMinProfile) { + if (start_x + dx >= device_ctx.grid.width()) { + break; + } + if (start_y + dy >= device_ctx.grid.height()) { + break; + } + for (e_rr_type chan_type : {CHANX, CHANY}) { StartNode start_node(start_x + dx, start_y + dy, chan_type, iseg); VTR_LOG("Searching for %d at (%d, %d)\n", iseg, start_x + dx, start_y + dy); From 0b8fd9b8996aeb5b25c007a90fa09d1db66d7d3c Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 16 Oct 2019 12:25:52 -0700 Subject: [PATCH 041/107] Increase capnproto traversal limit to allow large input files. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/place/place_delay_model.cpp | 6 +++++- vpr/src/route/connection_box_lookahead_map.cpp | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/vpr/src/place/place_delay_model.cpp b/vpr/src/place/place_delay_model.cpp index a7bfc674895..75342d54fed 100644 --- a/vpr/src/place/place_delay_model.cpp +++ b/vpr/src/place/place_delay_model.cpp @@ -239,7 +239,11 @@ void DeltaDelayModel::write(const std::string& file) const { void OverrideDelayModel::read(const std::string& file) { MmapFile f(file); - ::capnp::FlatArrayMessageReader reader(f.getData()); + + /* Increase reader limit to 1G words. */ + ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); + opts.traversalLimitInWords = 1024 * 1024 * 1024; + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); vtr::Matrix delays; auto model = reader.getRoot(); diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 47eea81e7de..14e554fe98a 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -588,7 +588,11 @@ static void FromMatrixCostEntry( void CostMap::read(const std::string& file) { MmapFile f(file); - ::capnp::FlatArrayMessageReader reader(f.getData()); + + /* Increase reader limit to 1G words. */ + ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); + opts.traversalLimitInWords = 1024 * 1024 * 1024; + ::capnp::FlatArrayMessageReader reader(f.getData(), opts); auto cost_map = reader.getRoot(); From d42192f0dddb37f8a3b5a0b9ca616e7bc7a6d9d2 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 09:43:51 -0700 Subject: [PATCH 042/107] add bounding box calculations to vtr::Rect Signed-off-by: Dusty DeWeese --- libs/libvtrutil/src/vtr_geometry.h | 9 +- libs/libvtrutil/src/vtr_geometry.tpp | 32 +++++ libs/libvtrutil/test/test_geometry.cpp | 188 ++++++++++++++----------- 3 files changed, 144 insertions(+), 85 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 65c53ecea65..c9775400b5c 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -75,9 +75,10 @@ class Point { template class Rect { public: //Constructors + Rect(); Rect(T left_val, T bottom_val, T right_val, T top_val); Rect(Point bottom_left_val, Point top_right_val); - Rect(); + Rect(Point bottom_left_val, T size); public: //Accessors //Co-ordinates @@ -101,9 +102,15 @@ class Rect { //Returns true if the point is coincident with the rectangle (including the top-right edges) bool coincident(Point point) const; + //Returns true if no points are contained in the rectangle + bool empty() const; + friend bool operator== <>(const Rect& lhs, const Rect& rhs); friend bool operator!= <>(const Rect& lhs, const Rect& rhs); + template friend Rect operator|(const Rect& lhs, const Rect& rhs); + template friend Rect& operator|=(Rect& lhs, const Rect& rhs); + public: //Mutators //Co-ordinates void set_xmin(T xmin_val); diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index a1a852850c1..00a6decc225 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -61,6 +61,12 @@ void Point::swap() { /* * Rect */ +template +Rect::Rect() + : Rect(Point(0, 0), Point(0, 0)) { + //pass +} + template Rect::Rect(T left_val, T bottom_val, T right_val, T top_val) : Rect(Point(left_val, bottom_val), Point(right_val, top_val)) { @@ -74,6 +80,14 @@ Rect::Rect(Point bottom_left_val, Point top_right_val) //pass } +template +Rect::Rect(Point bottom_left_val, T size) + : bottom_left_(bottom_left_val) + , top_right_(bottom_left_val.x() + size, + bottom_left_val.y() + size) { + //pass +} + template T Rect::xmin() const { return bottom_left_.x(); @@ -135,6 +149,11 @@ bool Rect::coincident(Point point) const { && point.y() >= ymin() && point.y() <= ymax(); } +template +bool Rect::empty() const { + return xmax() <= xmin() || ymax() <= ymin(); +} + template bool operator==(const Rect& lhs, const Rect& rhs) { return lhs.bottom_left() == rhs.bottom_left() @@ -166,6 +185,19 @@ void Rect::set_ymax(T ymax_val) { top_right_.set_y(ymax_val); } +template +Rect operator|(const Rect& lhs, const Rect& rhs) { + return Rect(std::min(lhs.xmin(), rhs.xmin()), + std::min(lhs.ymin(), rhs.ymin()), + std::max(lhs.xmax(), rhs.xmax()), + std::max(lhs.ymax(), rhs.ymax())); +} + +template +Rect& operator|=(Rect& lhs, const Rect& rhs) { + return lhs = lhs | rhs; +} + /* * Line */ diff --git a/libs/libvtrutil/test/test_geometry.cpp b/libs/libvtrutil/test/test_geometry.cpp index 60010d503c6..d005a4e269f 100644 --- a/libs/libvtrutil/test/test_geometry.cpp +++ b/libs/libvtrutil/test/test_geometry.cpp @@ -20,108 +20,128 @@ TEST_CASE("Point", "[vtr_geometry/Point]") { } TEST_CASE("Rect", "[vtr_geometry/Rect]") { - vtr::Point pi_1(5, 3); - vtr::Point pi_2(10, 11); + // int tests + { + vtr::Point pi_1(5, 3); + vtr::Point pi_2(10, 11); + vtr::Point pi_3(7, 9); + + vtr::Rect r1(pi_1.x(), pi_1.y(), pi_2.x(), pi_2.y()); + vtr::Rect r2(pi_1, pi_2); + vtr::Rect r3(pi_1, pi_3); + vtr::Rect r4(pi_3, pi_2); + + SECTION("equality") { + REQUIRE(r1 == r2); + } - vtr::Rect r1(pi_1.x(), pi_1.y(), pi_2.x(), pi_2.y()); - vtr::Rect r2(pi_1, pi_2); + SECTION("location") { + REQUIRE(r1.xmin() == pi_1.x()); + REQUIRE(r1.xmax() == pi_2.x()); + REQUIRE(r1.ymin() == pi_1.y()); + REQUIRE(r1.ymax() == pi_2.y()); + } - SECTION("equality") { - REQUIRE(r1 == r2); - } + SECTION("point_accessors") { + REQUIRE(r1.bottom_left() == pi_1); + REQUIRE(r1.top_right() == pi_2); + REQUIRE(r2.bottom_left() == pi_1); + REQUIRE(r2.top_right() == pi_2); + } - SECTION("location") { - REQUIRE(r1.xmin() == pi_1.x()); - REQUIRE(r1.xmax() == pi_2.x()); - REQUIRE(r1.ymin() == pi_1.y()); - REQUIRE(r1.ymax() == pi_2.y()); - } + SECTION("dimensions") { + REQUIRE(r1.width() == 5); + REQUIRE(r1.height() == 8); + REQUIRE(r2.width() == 5); + REQUIRE(r2.height() == 8); + } - SECTION("point_accessors") { - REQUIRE(r1.bottom_left() == pi_1); - REQUIRE(r1.top_right() == pi_2); - REQUIRE(r2.bottom_left() == pi_1); - REQUIRE(r2.top_right() == pi_2); - } + SECTION("contains_int") { + REQUIRE(r2.contains(pi_1)); + REQUIRE(r2.contains({6, 4})); + REQUIRE_FALSE(r2.contains({100, 4})); + REQUIRE_FALSE(r2.contains(pi_2)); + } - SECTION("dimensions") { - REQUIRE(r1.width() == 5); - REQUIRE(r1.height() == 8); - REQUIRE(r2.width() == 5); - REQUIRE(r2.height() == 8); - } + SECTION("strictly_contains_int") { + REQUIRE_FALSE(r2.strictly_contains(pi_1)); + REQUIRE(r2.strictly_contains({6, 4})); + REQUIRE_FALSE(r2.strictly_contains({100, 4})); + REQUIRE_FALSE(r2.strictly_contains(pi_2)); + } - SECTION("contains_int") { - REQUIRE(r2.contains(pi_1)); - REQUIRE(r2.contains({6, 4})); - REQUIRE_FALSE(r2.contains({100, 4})); - REQUIRE_FALSE(r2.contains(pi_2)); - } + SECTION("coincident_int") { + REQUIRE(r2.coincident(pi_1)); + REQUIRE(r2.coincident({6, 4})); + REQUIRE_FALSE(r2.coincident({100, 4})); + REQUIRE(r2.coincident(pi_2)); + } - SECTION("strictly_contains_int") { - REQUIRE_FALSE(r2.strictly_contains(pi_1)); - REQUIRE(r2.strictly_contains({6, 4})); - REQUIRE_FALSE(r2.strictly_contains({100, 4})); - REQUIRE_FALSE(r2.strictly_contains(pi_2)); + SECTION("bounds_int") { + REQUIRE(r1 == (r3 | r4)); + } } - SECTION("coincident_int") { - REQUIRE(r2.coincident(pi_1)); - REQUIRE(r2.coincident({6, 4})); - REQUIRE_FALSE(r2.coincident({100, 4})); - REQUIRE(r2.coincident(pi_2)); - } + // float tests + { + vtr::Point pf_1(5.3, 3.9); + vtr::Point pf_2(10.5, 11.1); + vtr::Point pf_3(7.2, 9.4); - vtr::Point pf_1(5.3, 3.9); - vtr::Point pf_2(10.5, 11.1); + vtr::Rect r3(pf_1.x(), pf_1.y(), pf_2.x(), pf_2.y()); + vtr::Rect r4(pf_1, pf_2); + vtr::Rect r5(pf_1, pf_3); + vtr::Rect r6(pf_3, pf_2); - vtr::Rect r3(pf_1.x(), pf_1.y(), pf_2.x(), pf_2.y()); - vtr::Rect r4(pf_1, pf_2); + SECTION("equality_float") { + REQUIRE(r3 == r4); + } - SECTION("equality_float") { - REQUIRE(r3 == r4); - } + SECTION("location_float") { + REQUIRE(r3.xmin() == pf_1.x()); + REQUIRE(r3.xmax() == pf_2.x()); + REQUIRE(r3.ymin() == pf_1.y()); + REQUIRE(r3.ymax() == pf_2.y()); + } - SECTION("location_float") { - REQUIRE(r3.xmin() == pf_1.x()); - REQUIRE(r3.xmax() == pf_2.x()); - REQUIRE(r3.ymin() == pf_1.y()); - REQUIRE(r3.ymax() == pf_2.y()); - } + SECTION("point_accessors_float") { + REQUIRE(r3.bottom_left() == pf_1); + REQUIRE(r3.top_right() == pf_2); + REQUIRE(r4.bottom_left() == pf_1); + REQUIRE(r4.top_right() == pf_2); + } - SECTION("point_accessors_float") { - REQUIRE(r3.bottom_left() == pf_1); - REQUIRE(r3.top_right() == pf_2); - REQUIRE(r4.bottom_left() == pf_1); - REQUIRE(r4.top_right() == pf_2); - } + SECTION("dimensions") { + REQUIRE(r3.width() == Approx(5.2)); + REQUIRE(r3.height() == Approx(7.2)); + REQUIRE(r4.width() == Approx(5.2)); + REQUIRE(r4.height() == Approx(7.2)); + } - SECTION("dimensions") { - REQUIRE(r3.width() == Approx(5.2)); - REQUIRE(r3.height() == Approx(7.2)); - REQUIRE(r4.width() == Approx(5.2)); - REQUIRE(r4.height() == Approx(7.2)); - } + SECTION("contains_float") { + REQUIRE(r4.contains(pf_1)); + REQUIRE(r4.contains({6, 4})); + REQUIRE_FALSE(r4.contains({100, 4})); + REQUIRE_FALSE(r4.contains(pf_2)); + } - SECTION("contains_float") { - REQUIRE(r4.contains(pf_1)); - REQUIRE(r4.contains({6, 4})); - REQUIRE_FALSE(r4.contains({100, 4})); - REQUIRE_FALSE(r4.contains(pf_2)); - } + SECTION("strictly_contains_float") { + REQUIRE_FALSE(r4.strictly_contains(pf_1)); + REQUIRE(r4.strictly_contains({6, 4})); + REQUIRE_FALSE(r4.strictly_contains({100, 4})); + REQUIRE_FALSE(r4.strictly_contains(pf_2)); + } - SECTION("strictly_contains_float") { - REQUIRE_FALSE(r4.strictly_contains(pf_1)); - REQUIRE(r4.strictly_contains({6, 4})); - REQUIRE_FALSE(r4.strictly_contains({100, 4})); - REQUIRE_FALSE(r4.strictly_contains(pf_2)); - } + SECTION("coincident_float") { + REQUIRE(r4.coincident(pf_1)); + REQUIRE(r4.coincident({6, 4})); + REQUIRE_FALSE(r4.coincident({100, 4})); + REQUIRE(r4.coincident(pf_2)); + } - SECTION("coincident_float") { - REQUIRE(r4.coincident(pf_1)); - REQUIRE(r4.coincident({6, 4})); - REQUIRE_FALSE(r4.coincident({100, 4})); - REQUIRE(r4.coincident(pf_2)); + SECTION("bounds_float") { + REQUIRE(r3 == (r5 | r6)); + } } } From d949c66fcd6e15239936beb54da9e5435bda203d Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 31 Oct 2019 12:28:59 -0700 Subject: [PATCH 043/107] add comments, rename operators, and change Point -> Rect constructor Signed-off-by: Dusty DeWeese --- libs/libvtrutil/src/vtr_geometry.h | 20 ++++++++++++++--- libs/libvtrutil/src/vtr_geometry.tpp | 30 ++++++++++++++------------ libs/libvtrutil/test/test_geometry.cpp | 6 ++++-- 3 files changed, 37 insertions(+), 19 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index c9775400b5c..3627545be70 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -5,6 +5,7 @@ #include #include #include +#include namespace vtr { @@ -78,7 +79,13 @@ class Rect { Rect(); Rect(T left_val, T bottom_val, T right_val, T top_val); Rect(Point bottom_left_val, Point top_right_val); - Rect(Point bottom_left_val, T size); + + //Constructs a rectangle that only contains the given point + // Rect(p1).contains(p2) => p1 == p2 + //It is only enabled for integral types, because making this work for floating point types would be difficult and brittle. + //The following line only enables the constructor if std::is_integral::value == true + template::value>::type...> + Rect(Point point); public: //Accessors //Co-ordinates @@ -103,13 +110,17 @@ class Rect { bool coincident(Point point) const; //Returns true if no points are contained in the rectangle + // rect.empty() => not exists p. rect.contains(p) + // This also implies either the width or height is 0. bool empty() const; friend bool operator== <>(const Rect& lhs, const Rect& rhs); friend bool operator!= <>(const Rect& lhs, const Rect& rhs); - template friend Rect operator|(const Rect& lhs, const Rect& rhs); - template friend Rect& operator|=(Rect& lhs, const Rect& rhs); + //Return the smallest rectangle containing both given rectangles + //Note that this isn't a union and the resulting rectangle may include points not in either given rectangle + template + friend Rect bounding_box(const Rect& lhs, const Rect& rhs); public: //Mutators //Co-ordinates @@ -118,6 +129,9 @@ class Rect { void set_xmax(T xmax_val); void set_ymax(T ymax_val); + //Equivalent to `*this = bounding_box(*this, other)` + Rect& expand_bounding_box(const Rect& other); + private: Point bottom_left_; Point top_right_; diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 00a6decc225..4698ec7a913 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -81,10 +81,11 @@ Rect::Rect(Point bottom_left_val, Point top_right_val) } template -Rect::Rect(Point bottom_left_val, T size) - : bottom_left_(bottom_left_val) - , top_right_(bottom_left_val.x() + size, - bottom_left_val.y() + size) { +template::value>::type...> +Rect::Rect(Point point) + : bottom_left_(point) + , top_right_(point.x() + 1, + point.y() + 1) { //pass } @@ -165,6 +166,14 @@ bool operator!=(const Rect& lhs, const Rect& rhs) { return !(lhs == rhs); } +template +Rect bounding_box(const Rect& lhs, const Rect& rhs) { + return Rect(std::min(lhs.xmin(), rhs.xmin()), + std::min(lhs.ymin(), rhs.ymin()), + std::max(lhs.xmax(), rhs.xmax()), + std::max(lhs.ymax(), rhs.ymax())); +} + template void Rect::set_xmin(T xmin_val) { bottom_left_.set_x(xmin_val); @@ -186,16 +195,9 @@ void Rect::set_ymax(T ymax_val) { } template -Rect operator|(const Rect& lhs, const Rect& rhs) { - return Rect(std::min(lhs.xmin(), rhs.xmin()), - std::min(lhs.ymin(), rhs.ymin()), - std::max(lhs.xmax(), rhs.xmax()), - std::max(lhs.ymax(), rhs.ymax())); -} - -template -Rect& operator|=(Rect& lhs, const Rect& rhs) { - return lhs = lhs | rhs; +Rect& Rect::expand_bounding_box(const Rect& other) { + *this = bounding_box(*this, other); + return *this; } /* diff --git a/libs/libvtrutil/test/test_geometry.cpp b/libs/libvtrutil/test/test_geometry.cpp index d005a4e269f..a41d88ec99d 100644 --- a/libs/libvtrutil/test/test_geometry.cpp +++ b/libs/libvtrutil/test/test_geometry.cpp @@ -61,6 +61,7 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { REQUIRE(r2.contains({6, 4})); REQUIRE_FALSE(r2.contains({100, 4})); REQUIRE_FALSE(r2.contains(pi_2)); + REQUIRE(vtr::Rect(pi_1).contains(pi_1)); } SECTION("strictly_contains_int") { @@ -78,7 +79,7 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { } SECTION("bounds_int") { - REQUIRE(r1 == (r3 | r4)); + REQUIRE(r1 == bounding_box(r3, r4)); } } @@ -92,6 +93,7 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { vtr::Rect r4(pf_1, pf_2); vtr::Rect r5(pf_1, pf_3); vtr::Rect r6(pf_3, pf_2); + // vtr::Rect r7(pf_1); // <-- will fail to compile SECTION("equality_float") { REQUIRE(r3 == r4); @@ -140,7 +142,7 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { } SECTION("bounds_float") { - REQUIRE(r3 == (r5 | r6)); + REQUIRE(r3 == bounding_box(r5, r6)); } } } From 820d1b84bdfa026dc71a1eb957b70fcb390bbd5b Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 31 Oct 2019 12:51:09 -0700 Subject: [PATCH 044/107] add empty() tests Signed-off-by: Dusty DeWeese --- libs/libvtrutil/test/test_geometry.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libs/libvtrutil/test/test_geometry.cpp b/libs/libvtrutil/test/test_geometry.cpp index a41d88ec99d..b89d7be9c3a 100644 --- a/libs/libvtrutil/test/test_geometry.cpp +++ b/libs/libvtrutil/test/test_geometry.cpp @@ -81,6 +81,10 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { SECTION("bounds_int") { REQUIRE(r1 == bounding_box(r3, r4)); } + + SECTION("empty_int") { + REQUIRE(vtr::Rect().empty()); + } } // float tests @@ -144,6 +148,10 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { SECTION("bounds_float") { REQUIRE(r3 == bounding_box(r5, r6)); } + + SECTION("empty_float") { + REQUIRE(vtr::Rect().empty()); + } } } From 538f7e8a934611485d6d527426423915c78be518 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 09:47:07 -0700 Subject: [PATCH 045/107] new sampling method Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 278 +++++++++--------- vpr/src/route/connection_box_lookahead_map.h | 2 + 2 files changed, 144 insertions(+), 136 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 14e554fe98a..211c8818011 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -9,6 +9,7 @@ #include "globals.h" #include "vtr_math.h" #include "vtr_time.h" +#include "vtr_geometry.h" #include "echo_files.h" #include "route_timing.h" @@ -30,18 +31,10 @@ * See e_representative_entry_method */ #define REPRESENTATIVE_ENTRY_METHOD SMALLEST -#define REF_X 25 -#define REF_Y 23 +static constexpr int SAMPLE_GRID_SIZE = 4; -static int signum(int x) { - if (x > 0) return 1; - if (x < 0) - return -1; - else - return 0; -} +typedef std::array, SAMPLE_GRID_SIZE>, SAMPLE_GRID_SIZE> SampleGrid; -typedef std::vector, std::pair, Cost_Entry, ConnectionBoxId>> t_routing_cost_map; static void run_dijkstra(int start_node_ind, t_routing_cost_map* routing_cost_map); @@ -213,100 +206,15 @@ class CostMap { static CostMap g_cost_map; -static const std::vector& get_rr_node_indcies(t_rr_type rr_type, int start_x, int start_y) { - const auto& device_ctx = g_vpr_ctx.device(); - if (rr_type == CHANX) { - return device_ctx.rr_node_indices[rr_type][start_y][start_x][0]; - } else if (rr_type == CHANY) { - return device_ctx.rr_node_indices[rr_type][start_x][start_y][0]; - } else { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Unknown channel type %d", rr_type); } -} - -class StartNode { - public: - StartNode(int start_x, int start_y, t_rr_type rr_type, int seg_index) - : start_x_(start_x) - , start_y_(start_y) - , rr_type_(rr_type) - , seg_index_(seg_index) - , index_(0) {} - int get_next_node() { - const auto& device_ctx = g_vpr_ctx.device(); - const std::vector& channel_node_list = get_rr_node_indcies( - rr_type_, start_x_, start_y_); - - for (; index_ < channel_node_list.size(); index_++) { - int node_ind = channel_node_list[index_]; - if (node_ind == OPEN || device_ctx.rr_nodes[node_ind].capacity() == 0) { - continue; - } - - const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(node_ind); - if (loc == nullptr) { - continue; } - - int node_cost_ind = device_ctx.rr_nodes[node_ind].cost_index(); - int node_seg_ind = device_ctx.rr_indexed_data[node_cost_ind].seg_index; - if (node_seg_ind == seg_index_) { - index_ += 1; - return node_ind; } } - - return UNDEFINED; } - private: - int start_x_; - int start_y_; - t_rr_type rr_type_; - int seg_index_; - size_t index_; -}; - -// Minimum size of search for channels to profile. kMinProfile results -// in searching x = [0, kMinProfile], and y = [0, kMinProfile[. -// -// Making this value larger will increase the sample size, but also the runtime -// to produce the lookahead. -static constexpr int kMinProfile = 1; - -// Maximum size of search for channels to profile. Once search is outside of -// kMinProfile distance, lookahead will stop searching once: -// - At least one channel has been profiled -// - kMaxProfile is exceeded. -static constexpr int kMaxProfile = 7; - -static int search_at(int iseg, int start_x, int start_y, t_routing_cost_map* cost_map) { const auto& device_ctx = g_vpr_ctx.device(); - - int count = 0; - int dx = 0; - int dy = 0; - - while ((count == 0 && dx < kMaxProfile) || dy <= kMinProfile) { - if (start_x + dx >= device_ctx.grid.width()) { - break; - } - if (start_y + dy >= device_ctx.grid.height()) { - break; } - - for (e_rr_type chan_type : {CHANX, CHANY}) { - StartNode start_node(start_x + dx, start_y + dy, chan_type, iseg); - VTR_LOG("Searching for %d at (%d, %d)\n", iseg, start_x + dx, start_y + dy); - - for (int start_node_ind = start_node.get_next_node(); - start_node_ind != UNDEFINED; - start_node_ind = start_node.get_next_node()) { - count += 1; - - /* run Dijkstra's algorithm */ - run_dijkstra(start_node_ind, cost_map); } } @@ -320,50 +228,11 @@ static int search_at(int iseg, int start_x, int start_y, t_routing_cost_map* cos return count; } -static void compute_connection_box_lookahead( - const std::vector& segment_inf, - const std::string& search_locations_str) { - size_t num_segments = segment_inf.size(); - vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); - - /* free previous delay map and allocate new one */ - auto& device_ctx = g_vpr_ctx.device(); - g_cost_map.set_counts(segment_inf.size(), - device_ctx.connection_boxes.num_connection_box_types()); - - std::vector> search_locations; - for (const auto& loc_str : vtr::split(search_locations_str, ";")) { - auto loc_parts = vtr::split(loc_str, ","); - if (loc_parts.size() != 2) { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Expected two parts from loc_str %s, got %d", - loc_str.c_str(), loc_parts.size()); } - - std::pair loc; - loc.first = vtr::atoi(loc_parts[0]); - loc.second = vtr::atoi(loc_parts[1]); - search_locations.push_back(loc); } - if (search_locations.size() == 0) { - VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "No search locations provided."); - } - /* run Dijkstra's algorithm for each segment type & channel type combination */ - for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { - VTR_LOG("Creating cost map for %s(%d)\n", - segment_inf[iseg].name.c_str(), iseg); - /* allocate the cost map for this iseg/chan_type */ - t_routing_cost_map cost_map; - - int count = 0; - for (const auto loc : search_locations) { - count += search_at(iseg, loc.first, loc.second, &cost_map); } - - if (count == 0) { - VTR_LOG_WARN("Segment %s(%d) found no start_node_ind\n", - segment_inf[iseg].name.c_str(), iseg); } #if 0 @@ -514,8 +383,65 @@ static void run_dijkstra(int start_node_ind, } } -void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) { - compute_connection_box_lookahead(segment_inf, lookahead_search_locations); +void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf, + const std::string& lookahead_search_locations) { + vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); + + size_t num_segments = segment_inf.size(); + std::vector inodes_for_segment(num_segments); + find_inodes_for_segment_types(&inodes_for_segment); + + /* free previous delay map and allocate new one */ + auto& device_ctx = g_vpr_ctx.device(); + cost_map_.set_counts(segment_inf.size(), + device_ctx.connection_boxes.num_connection_box_types()); + + /* run Dijkstra's algorithm for each segment type & channel type combination */ + for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { + VTR_LOG("Creating cost map for %s(%d)\n", + segment_inf[iseg].name.c_str(), iseg); + /* allocate the cost map for this iseg/chan_type */ + std::vector costs; + bool found = false; + for (const auto& row : inodes_for_segment[iseg]) { + for (auto cell : row) { + for (auto node_ind : cell) { + found = true; + run_dijkstra(node_ind, costs); + } + } + } + if (!found) { + VTR_LOG_WARN("Segment %s(%d) found no start_node_ind\n", + segment_inf[iseg].name.c_str(), iseg); + } else { + /* boil down the cost list in routing_cost_map at each coordinate to a + * representative cost entry and store it in the lookahead cost map */ + cost_map_.set_cost_map(iseg, costs, + REPRESENTATIVE_ENTRY_METHOD); + } + } + + for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { +#if 0 + for (auto &e : cost_map_per_segment[iseg]) { + VTR_LOG("%d -> %d (%d, %d): %g, %g\n", + std::get<0>(e).first, std::get<0>(e).second, + std::get<1>(e).first, std::get<1>(e).second, + std::get<2>(e).delay, std::get<2>(e).congestion); + } +#endif + //VTR_LOG("cost map for %s(%d)\n", + // segment_inf[iseg].name.c_str(), iseg); + //cost_map_.print(iseg); + } + + for(std::pair p : cost_map_.list_empty()) { + int iseg, box_id; + std::tie(iseg, box_id) = p; + VTR_LOG("cost map for %s(%d), connection box %d EMPTY\n", + segment_inf[iseg].name.c_str(), iseg, box_id); + } } float ConnectionBoxMapLookahead::get_expected_cost( @@ -537,6 +463,86 @@ float ConnectionBoxMapLookahead::get_expected_cost( } } +static int manhattan_distance(const t_rr_node& node, int x, int y) { + int node_center_x = (node.xhigh() + node.xlow()) / 2; + int node_center_y = (node.yhigh() + node.ylow()) / 2; + return abs(node_center_x - x) + abs(node_center_y - y); +} + +static vtr::Rect bounding_box_for_node(const t_rr_node& node) { + return vtr::Rect(node.xlow(), node.ylow(), + node.xhigh() + 1, node.yhigh() + 1); +} + +static void find_inodes_for_segment_types(std::vector *inodes_for_segment) { + auto& device_ctx = g_vpr_ctx.device(); + auto& rr_nodes = device_ctx.rr_nodes; + const int num_segments = inodes_for_segment->size(); + + // compute bounding boxes for each segment type + std::vector> bounding_box_for_segment(num_segments, vtr::Rect()); + for (size_t i = 0; i < rr_nodes.size(); i++) { + auto& node = rr_nodes[i]; + if (node.type() != CHANX && node.type() != CHANY) continue; + int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; + + VTR_ASSERT(seg_index != OPEN); + VTR_ASSERT(seg_index < num_segments); + + bounding_box_for_segment[seg_index] |= bounding_box_for_node(node); + } + + // select an inode near the center of the bounding box for each segment type + inodes_for_segment->clear(); + inodes_for_segment->resize(num_segments); + for (auto& grid : *inodes_for_segment) { + for (auto& row : grid) { + for (auto& cell : row) { + cell = std::vector(); + } + } + } + + for (size_t i = 0; i < rr_nodes.size(); i++) { + auto& node = rr_nodes[i]; + if (node.type() != CHANX && node.type() != CHANY) continue; + if (node.capacity() == 0 || device_ctx.connection_boxes.find_canonical_loc(i) == nullptr) continue; + + int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; + + VTR_ASSERT(seg_index != OPEN); + VTR_ASSERT(seg_index < num_segments); + + auto& grid = (*inodes_for_segment)[seg_index]; + for (int sy = 0; sy < SAMPLE_GRID_SIZE; sy++) { + for (int sx = 0; sx < SAMPLE_GRID_SIZE; sx++) { + auto& stored_inodes = grid[sy][sx]; + if (stored_inodes.empty()) { + stored_inodes.push_back(i); + goto next_rr_node; + } + + auto& first_stored_node = rr_nodes[stored_inodes.front()]; + if (first_stored_node.xhigh() >= node.xhigh() && first_stored_node.xlow() <= node.xlow() && first_stored_node.yhigh() >= node.yhigh() && first_stored_node.ylow() <= node.ylow()) { + stored_inodes.push_back(i); + goto next_rr_node; + } + + vtr::Point target = sample(bounding_box_for_segment[seg_index], sx + 1, sy + 1, SAMPLE_GRID_SIZE + 1); + int distance_new = manhattan_distance(node, target.x(), target.y()); + int distance_stored = manhattan_distance(first_stored_node, target.x(), target.y()); + if (distance_new < distance_stored) { + stored_inodes.clear(); + stored_inodes.push_back(i); + goto next_rr_node; + } + } + } + next_rr_node: + continue; + } +} + #ifndef VTR_ENABLE_CAPNPROTO void ConnectionBoxMapLookahead::read(const std::string& file) { diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index ff3cee59eee..e49b5d56327 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -12,6 +12,8 @@ class ConnectionBoxMapLookahead : public RouterLookahead { void read(const std::string& file) override; void write(const std::string& file) const override; + + CostMap cost_map_; }; #endif From 2ff861d18f5405048713db8ac1219d80333efac7 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 09:59:45 -0700 Subject: [PATCH 046/107] spiral hole filling Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 410 ++++++++++-------- vpr/src/route/connection_box_lookahead_map.h | 32 ++ 2 files changed, 264 insertions(+), 178 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 211c8818011..0c642066117 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -36,224 +36,271 @@ static constexpr int SAMPLE_GRID_SIZE = 4; typedef std::array, SAMPLE_GRID_SIZE>, SAMPLE_GRID_SIZE> SampleGrid; static void run_dijkstra(int start_node_ind, - t_routing_cost_map* routing_cost_map); - -class CostMap { - public: - void set_counts(size_t seg_count, size_t box_count) { - cost_map_.clear(); - offset_.clear(); - cost_map_.resize({seg_count, box_count}); - offset_.resize({seg_count, box_count}); - - const auto& device_ctx = g_vpr_ctx.device(); - segment_map_.resize(device_ctx.rr_nodes.size()); - for (size_t i = 0; i < segment_map_.size(); ++i) { - auto& from_node = device_ctx.rr_nodes[i]; + std::vector& routing_costs); - int from_cost_index = from_node.cost_index(); - int from_seg_index = device_ctx.rr_indexed_data[from_cost_index].seg_index; +void CostMap::set_counts(size_t seg_count, size_t box_count) { + cost_map_.clear(); + offset_.clear(); + cost_map_.resize({seg_count, box_count}); + offset_.resize({seg_count, box_count}); - segment_map_[i] = from_seg_index; - } - } + const auto& device_ctx = g_vpr_ctx.device(); + segment_map_.resize(device_ctx.rr_nodes.size()); + for (size_t i = 0; i < segment_map_.size(); ++i) { + auto& from_node = device_ctx.rr_nodes[i]; + + int from_cost_index = from_node.cost_index(); + int from_seg_index = device_ctx.rr_indexed_data[from_cost_index].seg_index; - int node_to_segment(int from_node_ind) { - return segment_map_[from_node_ind]; + segment_map_[i] = from_seg_index; } +} - Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { - VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); - int dx = delta_x - offset_[from_seg_index][size_t(box_id)].first; - int dy = delta_y - offset_[from_seg_index][size_t(box_id)].second; - const auto& cost_map = cost_map_[from_seg_index][size_t(box_id)]; +int CostMap::node_to_segment(int from_node_ind) const { + return segment_map_[from_node_ind]; +} - if (dx < 0) { - dx = 0; - } - if (dy < 0) { - dy = 0; - } +Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { + VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); + const auto& cost_map = cost_map_[from_seg_index][size_t(box_id)]; + if (cost_map.dim_size(0) == 0 || cost_map.dim_size(1) == 0) { + return Cost_Entry(); + } - if (dx >= (ssize_t)cost_map.dim_size(0)) { - dx = cost_map.dim_size(0) - 1; - } - if (dy >= (ssize_t)cost_map.dim_size(1)) { - dy = cost_map.dim_size(1) - 1; - } + int dx = delta_x - offset_[from_seg_index][size_t(box_id)].first; + int dy = delta_y - offset_[from_seg_index][size_t(box_id)].second; - return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; + if (dx < 0) { + dx = 0; + } + if (dy < 0) { + dy = 0; } - void set_cost_map(int from_seg_index, - const t_routing_cost_map& cost_map, - e_representative_entry_method method) { - const auto& device_ctx = g_vpr_ctx.device(); - for (size_t box_id = 0; - box_id < device_ctx.connection_boxes.num_connection_box_types(); - ++box_id) { - set_cost_map(from_seg_index, ConnectionBoxId(box_id), cost_map, method); - } + if (dx >= (ssize_t)cost_map.dim_size(0)) { + dx = cost_map.dim_size(0) - 1; + } + if (dy >= (ssize_t)cost_map.dim_size(1)) { + dy = cost_map.dim_size(1) - 1; } - void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const t_routing_cost_map& cost_map, e_representative_entry_method method) { - VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); + return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; +} - // Find coordinate offset for this segment. - int min_dx = 0; - int min_dy = 0; - int max_dx = 0; - int max_dy = 0; - for (const auto& entry : cost_map) { - if (std::get<3>(entry) != box_id) { - continue; - } - min_dx = std::min(std::get<1>(entry).first, min_dx); - min_dy = std::min(std::get<1>(entry).second, min_dy); +void CostMap::set_cost_map(int from_seg_index, + const std::vector& costs, + e_representative_entry_method method) { + // sort the entries + const auto& device_ctx = g_vpr_ctx.device(); + std::vector> costs_per_box(device_ctx.connection_boxes.num_connection_box_types()); + for (const auto& entry : costs) { + costs_per_box[size_t(std::get<3>(entry))].push_back(entry); + } - max_dx = std::max(std::get<1>(entry).first, max_dx); - max_dy = std::max(std::get<1>(entry).second, max_dy); - } + for (size_t box_id = 0; + box_id < device_ctx.connection_boxes.num_connection_box_types(); + ++box_id) { + set_cost_map(from_seg_index, ConnectionBoxId(box_id), costs_per_box[box_id], method); + } +} - offset_[from_seg_index][size_t(box_id)].first = min_dx; - offset_[from_seg_index][size_t(box_id)].second = min_dy; - size_t dim_x = max_dx - min_dx + 1; - size_t dim_y = max_dy - min_dy + 1; +void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const std::vector& costs, e_representative_entry_method method) { + VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); - vtr::NdMatrix expansion_cost_map( - {dim_x, dim_y}); + if (costs.empty()) { + offset_[from_seg_index][size_t(box_id)] = std::make_pair(0, 0); + cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( + {size_t(0), size_t(0)}); + return; + } - for (const auto& entry : cost_map) { - if (std::get<3>(entry) != box_id) { - continue; - } - int x = std::get<1>(entry).first - min_dx; - int y = std::get<1>(entry).second - min_dy; - expansion_cost_map[x][y].add_cost_entry( - method, std::get<2>(entry).delay, - std::get<2>(entry).congestion); - } + // calculate the bounding box + vtr::Rect bounds; + for (const auto& entry : costs) { + bounds |= vtr::Rect(std::get<1>(entry), 1); + } - cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( - {dim_x, dim_y}); + offset_[from_seg_index][size_t(box_id)] = std::make_pair(bounds.xmin(), bounds.ymin()); - /* set the lookahead cost map entries with a representative cost - * entry from routing_cost_map */ - for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { - for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { - cost_map_[from_seg_index][size_t(box_id)][ix][iy] = expansion_cost_map[ix][iy].get_representative_cost_entry(method); - } - } + vtr::NdMatrix expansion_cost_map( + {size_t(bounds.width()), size_t(bounds.height())}); - /* find missing cost entries and fill them in by copying a nearby cost entry */ - for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { - for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { - Cost_Entry cost_entry = cost_map_[from_seg_index][size_t(box_id)][ix][iy]; - - if (!cost_entry.valid()) { - Cost_Entry copied_entry = get_nearby_cost_entry( - from_seg_index, - box_id, - offset_[from_seg_index][size_t(box_id)].first + ix, - offset_[from_seg_index][size_t(box_id)].second + iy); - cost_map_[from_seg_index][size_t(box_id)][ix][iy] = copied_entry; - } - } - } + for (const auto& entry : costs) { + int x = std::get<1>(entry).x() - bounds.xmin(); + int y = std::get<1>(entry).y() - bounds.ymin(); + expansion_cost_map[x][y].add_cost_entry( + method, std::get<2>(entry).delay, + std::get<2>(entry).congestion); } - Cost_Entry get_nearby_cost_entry(int segment_index, ConnectionBoxId box_id, int x, int y) { - /* compute the slope from x,y to 0,0 and then move towards 0,0 by one - * unit to get the coordinates of the cost entry to be copied */ + cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( + {size_t(bounds.width()), size_t(bounds.height())}); + auto& matrix = cost_map_[from_seg_index][size_t(box_id)]; - float slope; - int copy_x, copy_y; - if (x == 0 || y == 0) { - slope = std::numeric_limits::infinity(); - copy_x = x - signum(x); - copy_y = y - signum(y); - } else { - slope = (float)y / (float)x; - if (slope >= 1.0) { - copy_y = y - signum(y); - copy_x = vtr::nint((float)y / slope); - } else { - copy_x = x - signum(x); - copy_y = vtr::nint((float)x * slope); - } + /* set the lookahead cost map entries with a representative cost + * entry from routing_cost_map */ + for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { + for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { + matrix[ix][iy] = expansion_cost_map[ix][iy].get_representative_cost_entry(method); } + } - Cost_Entry copy_entry = find_cost(segment_index, box_id, copy_x, copy_y); - - /* if the entry to be copied is also empty, recurse */ - if (copy_entry.valid()) { - return copy_entry; - } else if (copy_x == 0 && copy_y == 0) { - return Cost_Entry(); + std::list > missing; + bool couldnt_fill = false; + auto shifted_bounds = vtr::Rect(0, 0, bounds.width(), bounds.height()); + /* find missing cost entries and fill them in by copying a nearby cost entry */ + for (unsigned ix = 0; ix < matrix.dim_size(0) && !couldnt_fill; ix++) { + for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { + Cost_Entry& cost_entry = matrix[ix][iy]; + if (!cost_entry.valid()) { + // maximum search radius + Cost_Entry filler = get_nearby_cost_entry(matrix, ix, iy, shifted_bounds); + if (filler.valid()) { + missing.push_back(std::make_tuple(ix, iy, filler)); + } else { + couldnt_fill = true; + } + } } - - return get_nearby_cost_entry(segment_index, box_id, copy_x, copy_y); } - void read(const std::string& file); - void write(const std::string& file) const; - - private: - vtr::NdMatrix, 2> cost_map_; - vtr::NdMatrix, 2> offset_; - std::vector segment_map_; -}; - -static CostMap g_cost_map; - + // write back the missing entries + for (auto& xy_entry : missing) { + matrix[std::get<0>(xy_entry)][std::get<1>(xy_entry)] = std::get<2>(xy_entry); } + if (couldnt_fill) { + VTR_LOG_WARN("Couldn't fill holes in the cost matrix for %d -> %ld\n", + from_seg_index, size_t(box_id)); + for (unsigned y = 0; y < matrix.dim_size(1); y++) { + for (unsigned x = 0; x < matrix.dim_size(0); x++) { + VTR_ASSERT(!matrix[x][y].valid()); } + } +#if 0 + for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { + for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { + if(matrix[ix][iy].valid()) { + printf("O"); + } else { + printf("."); + } } + printf("\n"); } +#endif } +} +void CostMap::print(int iseg) const { const auto& device_ctx = g_vpr_ctx.device(); + for (size_t box_id = 0; + box_id < device_ctx.connection_boxes.num_connection_box_types(); + box_id++) { + auto& matrix = cost_map_[iseg][box_id]; + if (matrix.dim_size(0) == 0 || matrix.dim_size(1) == 0) { + printf("cost EMPTY for box_id = %lu\n", box_id); + continue; } + printf("cost for box_id = %lu\n", box_id); + double sum = 0.0; + for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { + for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { + const auto& entry = matrix[ix][iy]; + if (entry.valid()) { + sum += entry.delay; + } } } - - if (dy < dx) { - dy += 1; - } else { - dx += 1; + double avg = sum / ((double)matrix.dim_size(0) * (double)matrix.dim_size(1)); + for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { + for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { + const auto& entry = matrix[ix][iy]; + if (entry.valid() && entry.delay > avg) { + printf("o"); + } else { + printf("."); + } + } + printf("\n"); } } - - return count; } +std::list > CostMap::list_empty() const { + std::list > results; + for (int iseg = 0; iseg < (int)cost_map_.dim_size(0); iseg++) { + for (int box_id = 0; box_id < (int)cost_map_.dim_size(1); box_id++) { + auto& matrix = cost_map_[iseg][box_id]; + if (matrix.dim_size(0) == 0 || matrix.dim_size(1) == 0) results.push_back(std::make_pair(iseg, box_id)); } } + return results; +} +static void assign_min_entry(Cost_Entry& dst, const Cost_Entry& src) { + if (src.delay < dst.delay) dst.delay = src.delay; + if (src.congestion < dst.congestion) dst.congestion = src.congestion; +} +Cost_Entry CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, + int cx, + int cy, + const vtr::Rect& bounds) { + // spiral around (cx, cy) looking for a nearby entry + int n = 1, x, y; + bool in_bounds; + Cost_Entry entry; + + do { + in_bounds = false; + y = cy - n; // top + // left -> right + for (x = cx - n; x < cx + n; x++) { + if (bounds.contains(vtr::Point(x, y))) { + assign_min_entry(entry, matrix[x][y]); + in_bounds = true; + } } + x = cx + n; // right + // top -> bottom + for (; y < cy + n; y++) { + if (bounds.contains(vtr::Point(x, y))) { + assign_min_entry(entry, matrix[x][y]); + in_bounds = true; + } } - -#if 0 - for(const auto & e : cost_map) { - VTR_LOG("%d -> %d (%d, %d): %g, %g\n", - std::get<0>(e).first, std::get<0>(e).second, - std::get<1>(e).first, std::get<1>(e).second, - std::get<2>(e).delay, std::get<2>(e).congestion); + y = cy + n; // bottom + // right -> left + for (; x > cx - n; x--) { + if (bounds.contains(vtr::Point(x, y))) { + assign_min_entry(entry, matrix[x][y]); + in_bounds = true; + } } -#endif + x = cx - n; // left + // bottom -> top + for (; y > cy - n; y--) { + if (bounds.contains(vtr::Point(x, y))) { + assign_min_entry(entry, matrix[x][y]); + in_bounds = true; + } + } + if (entry.valid()) return entry; + n++; + } while (in_bounds); + return Cost_Entry(); +} - /* boil down the cost list in routing_cost_map at each coordinate to a - * representative cost entry and store it in the lookahead cost map */ - g_cost_map.set_cost_map(iseg, cost_map, - REPRESENTATIVE_ENTRY_METHOD); - } +template +vtr::Point sample(const vtr::Rect& r, T x, T y, T d) { + return vtr::Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, + (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); } -static float get_connection_box_lookahead_map_cost(int from_node_ind, - int to_node_ind, - float criticality_fac) { +float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, + int to_node_ind, + float criticality_fac) const { if (from_node_ind == to_node_ind) { return 0.f; } @@ -271,7 +318,7 @@ static float get_connection_box_lookahead_map_cost(int from_node_ind, // Find cheapest cost from from_node_ind to IPINs for this SINK. for (int i = 0; i < sink_to_ipin.ipin_count; ++i) { cost = std::min(cost, - get_connection_box_lookahead_map_cost( + get_map_cost( from_node_ind, sink_to_ipin.ipin_nodes[i], criticality_fac)); } @@ -307,12 +354,19 @@ static float get_connection_box_lookahead_map_cost(int from_node_ind, ssize_t dx = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); ssize_t dy = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); - int from_seg_index = g_cost_map.node_to_segment(from_node_ind); - Cost_Entry cost_entry = g_cost_map.find_cost(from_seg_index, box_id, dx, dy); + int from_seg_index = cost_map_.node_to_segment(from_node_ind); + Cost_Entry cost_entry = cost_map_.find_cost(from_seg_index, box_id, dx, dy); + + if (!cost_entry.valid()) { + // there is no route + return std::numeric_limits::infinity(); + } + float expected_delay = cost_entry.delay; float expected_congestion = cost_entry.congestion; float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; + VTR_ASSERT(std::isfinite(expected_cost) && expected_cost >= 0.f); return expected_cost; } @@ -320,7 +374,7 @@ static float get_connection_box_lookahead_map_cost(int from_node_ind, * visited. Each time a pin is visited, the delay/congestion information * to that pin is stored to an entry in the routing_cost_map */ static void run_dijkstra(int start_node_ind, - t_routing_cost_map* routing_cost_map) { + std::vector& routing_costs) { auto& device_ctx = g_vpr_ctx.device(); /* a list of boolean flags (one for each rr node) to figure out if a @@ -369,9 +423,9 @@ static void run_dijkstra(int start_node_ind, int delta_x = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); int delta_y = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); - routing_cost_map->push_back(std::make_tuple( + routing_costs.push_back(std::make_tuple( std::make_pair(start_node_ind, node_ind), - std::make_pair(delta_x, delta_y), + vtr::Point(delta_x, delta_y), Cost_Entry( current.delay, current.congestion_upstream), @@ -454,7 +508,7 @@ float ConnectionBoxMapLookahead::get_expected_cost( t_rr_type rr_type = device_ctx.rr_nodes[current_node].type(); if (rr_type == CHANX || rr_type == CHANY) { - return get_connection_box_lookahead_map_cost( + return get_map_cost( current_node, target_node, params.criticality); } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ return (device_ctx.rr_indexed_data[SINK_COST_INDEX].base_cost); @@ -555,10 +609,10 @@ void ConnectionBoxMapLookahead::write(const std::string& file) const { #else void ConnectionBoxMapLookahead::read(const std::string& file) { - g_cost_map.read(file); + cost_map_.read(file); } void ConnectionBoxMapLookahead::write(const std::string& file) const { - g_cost_map.write(file); + cost_map_.write(file); } static void ToCostEntry(Cost_Entry* out, const VprCostEntry::Reader& in) { @@ -613,13 +667,13 @@ void CostMap::read(const std::string& file) { { const auto& offset = cost_map.getOffset(); - ToNdMatrix<2, VprVector2D, std::pair>( + ToNdMatrix<2, VprVector2D, std::pair >( &offset_, offset, ToVprVector2D); } { const auto& cost_maps = cost_map.getCostMap(); - ToNdMatrix<2, Matrix, vtr::NdMatrix>( + ToNdMatrix<2, Matrix, vtr::NdMatrix >( &cost_map_, cost_maps, ToMatrixCostEntry); } } @@ -638,13 +692,13 @@ void CostMap::write(const std::string& file) const { { auto offset = cost_map.initOffset(); - FromNdMatrix<2, VprVector2D, std::pair>( + FromNdMatrix<2, VprVector2D, std::pair >( &offset, offset_, FromVprVector2D); } { auto cost_maps = cost_map.initCostMap(); - FromNdMatrix<2, Matrix, vtr::NdMatrix>( + FromNdMatrix<2, Matrix, vtr::NdMatrix >( &cost_maps, cost_map_, FromMatrixCostEntry); } diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index e49b5d56327..bdd42623f7e 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -2,12 +2,44 @@ #define CONNECTION_BOX_LOOKAHEAD_H_ #include +#include #include "physical_types.h" #include "router_lookahead.h" +#include "router_lookahead_map_utils.h" +#include "connection_box.h" +#include "vtr_geometry.h" + +class CostMap { + public: + typedef std::tuple, + vtr::Point, + Cost_Entry, + ConnectionBoxId> + routing_cost; + + void set_counts(size_t seg_count, size_t box_count); + int node_to_segment(int from_node_ind) const; + Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; + void set_cost_map(int from_seg_index, + const std::vector& costs, + e_representative_entry_method method); + void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const std::vector& costs, e_representative_entry_method method); + Cost_Entry get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); + void read(const std::string& file); + void write(const std::string& file) const; + void print(int iseg) const; + std::list> list_empty() const; + + private: + vtr::NdMatrix, 2> cost_map_; + vtr::NdMatrix, 2> offset_; + std::vector segment_map_; +}; class ConnectionBoxMapLookahead : public RouterLookahead { public: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; + float get_map_cost(int from_node_ind, int to_node_ind, float criticality_fac) const; void compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) override; void read(const std::string& file) override; From d5d22632d83e0253d46cec59b09fa0fc0ddbc53d Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 10:08:45 -0700 Subject: [PATCH 047/107] use a lightweight version of PQ_Entry (PQ_Entry_Lite) Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 69 +++++++++++++++---- vpr/src/route/router_lookahead_map_utils.cpp | 47 ++++++++++--- vpr/src/route/router_lookahead_map_utils.h | 29 +++++++- 3 files changed, 118 insertions(+), 27 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 0c642066117..7afdfc0e353 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -385,10 +385,10 @@ static void run_dijkstra(int start_node_ind, * expansion queue */ std::vector node_visited_costs(device_ctx.rr_nodes.size(), -1.0); /* a priority queue for expansion */ - std::priority_queue pq; + std::priority_queue, std::greater> pq; /* first entry has no upstream delay or congestion */ - util::PQ_Entry first_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); + util::PQ_Entry_Lite first_entry(start_node_ind, UNDEFINED, 0, true); pq.push(first_entry); @@ -400,7 +400,7 @@ static void run_dijkstra(int start_node_ind, /* now do routing */ while (!pq.empty()) { - util::PQ_Entry current = pq.top(); + auto current = pq.top(); pq.pop(); int node_ind = current.rr_node_ind; @@ -420,20 +420,59 @@ static void run_dijkstra(int start_node_ind, VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); } - int delta_x = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); - int delta_y = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); + // reconstruct the path + std::vector path; + for (int i = node_ind; i != start_node_ind; path.push_back(i = paths[i].parent)); + util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); + + // recalculate the path with congestion + util::PQ_Entry current_full = parent_entry; + int parent = start_node_ind; + for (auto it = path.rbegin(); it != path.rend(); it++) { + auto& parent_node = device_ctx.rr_nodes[parent]; + current_full = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), current_full.delay, + current_full.R_upstream, current_full.congestion_upstream, false); + parent = *it; + } - routing_costs.push_back(std::make_tuple( - std::make_pair(start_node_ind, node_ind), - vtr::Point(delta_x, delta_y), - Cost_Entry( - current.delay, - current.congestion_upstream), - box_id)); + // add each node along the path subtracting the incremental costs from the current costs + parent = start_node_ind; + for (auto it = path.rbegin(); it != path.rend(); it++) { + auto& parent_node = device_ctx.rr_nodes[parent]; + int seg_index = device_ctx.rr_indexed_data[parent_node.cost_index()].seg_index; + if (!node_recorded[parent]) { + + const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); + if (from_canonical_loc == nullptr) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", + parent); + } + + vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), + ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); + RoutingCostKey key = { + delta, + box_id + }; + RoutingCost cost = { + parent, + node_ind, + Cost_Entry( + current_full.delay - parent_entry.delay, + current_full.congestion_upstream - parent_entry.congestion_upstream) + }; + routing_costs.push_back(std::make_tuple(seg_index, key, cost)); + } + node_recorded[parent] = true; + parent_entry = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), parent_entry.delay, + parent_entry.R_upstream, parent_entry.congestion_upstream, false); + parent = *it; + } + node_expanded[node_ind] = true; + } else { + expand_dijkstra_neighbours(current, paths, node_expanded, pq); + node_expanded[node_ind] = true; } - - expand_dijkstra_neighbours(current, node_visited_costs, node_expanded, pq); - node_expanded[node_ind] = true; } } diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index d50aa372a5f..262edaac433 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -59,6 +59,33 @@ util::PQ_Entry::PQ_Entry( this->cost = this->delay; } +util::PQ_Entry_Lite::PQ_Entry_Lite( + int set_rr_node_ind, + int switch_ind, + float parent_delay, + bool starting_node) { + this->rr_node_ind = set_rr_node_ind; + + auto& device_ctx = g_vpr_ctx.device(); + this->delay_cost = parent_delay; + if (!starting_node) { + float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; + float Rsw = device_ctx.rr_switch_inf[switch_ind].R; + float Cnode = device_ctx.rr_nodes[set_rr_node_ind].C(); + float Rnode = device_ctx.rr_nodes[set_rr_node_ind].R(); + + float T_linear = 0.f; + if (device_ctx.rr_switch_inf[switch_ind].buffered()) { + T_linear = Tsw + Rsw * Cnode + 0.5 * Rnode * Cnode; + } else { /* Pass transistor */ + T_linear = Tsw + 0.5 * Rsw * Cnode; + } + + VTR_ASSERT(T_linear >= 0.); + this->delay_cost += T_linear; + } +} + /* returns cost entry with the smallest delay */ Cost_Entry Expansion_Cost_Entry::get_smallest_entry() const { Cost_Entry smallest_entry; @@ -156,10 +183,12 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { } /* iterates over the children of the specified node and selectively pushes them onto the priority queue */ -void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, - std::vector& node_visited_costs, +void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, + std::unordered_map& paths, std::vector& node_expanded, - std::priority_queue& pq) { + std::priority_queue, + std::greater>& pq) { auto& device_ctx = g_vpr_ctx.device(); int parent_ind = parent_entry.rr_node_ind; @@ -175,18 +204,18 @@ void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, continue; } - util::PQ_Entry child_entry(child_node_ind, switch_ind, parent_entry.delay, - parent_entry.R_upstream, parent_entry.congestion_upstream, false); + util::PQ_Entry_Lite child_entry(child_node_ind, switch_ind, parent_entry.delay_cost, false); - VTR_ASSERT(child_entry.cost >= 0); + VTR_ASSERT(child_entry.delay_cost >= 0); - /* skip this child if it has been visited with smaller cost */ - if (node_visited_costs[child_node_ind] >= 0 && node_visited_costs[child_node_ind] < child_entry.cost) { + /* skip this child if it has been visited with smaller or the same cost */ + auto stored_cost = paths.find(child_node_ind); + if (stored_cost != paths.end() && stored_cost->second.cost <= child_entry.delay_cost) { continue; } /* finally, record the cost with which the child was visited and put the child entry on the queue */ - node_visited_costs[child_node_ind] = child_entry.cost; + paths[child_node_ind] = { child_entry.delay_cost, parent_ind, iedge }; pq.push(child_entry); } } diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index af37006669a..44ca3f07d79 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -19,6 +19,7 @@ #include #include #include +#include #include "vpr_types.h" /* when a list of delay/congestion entries at a coordinate in Cost_Entry is boiled down to a single @@ -134,11 +135,33 @@ class PQ_Entry { return (this->cost > obj.cost); } }; + +// A version of PQ_Entry that only calculates and stores the delay (cost.) +class PQ_Entry_Lite { + public: + int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents + float delay_cost; //the cost of the path to get to this node + + PQ_Entry_Lite(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, bool starting_node); + + bool operator>(const PQ_Entry_Lite& obj) const { + return (this->delay_cost > obj.delay_cost); + } +}; + +struct Search_Path { + float cost; + int parent; + int edge; +}; + } // namespace util -void expand_dijkstra_neighbours(util::PQ_Entry parent_entry, - std::vector& node_visited_costs, +void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, + std::unordered_map& paths, std::vector& node_expanded, - std::priority_queue& pq); + std::priority_queue, + std::greater>& pq); #endif From b2114b011cb0ec54e3340a5952d66609730e6c67 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 10:08:24 -0700 Subject: [PATCH 048/107] use maps in run_dijkstra() Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 210 ++++++++++-------- vpr/src/route/connection_box_lookahead_map.h | 41 +++- 2 files changed, 146 insertions(+), 105 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 7afdfc0e353..d2eab064b67 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -36,7 +36,8 @@ static constexpr int SAMPLE_GRID_SIZE = 4; typedef std::array, SAMPLE_GRID_SIZE>, SAMPLE_GRID_SIZE> SampleGrid; static void run_dijkstra(int start_node_ind, - std::vector& routing_costs); + std::vector* routing_costs); +static void find_inodes_for_segment_types(std::vector* inodes_for_segment); void CostMap::set_counts(size_t seg_count, size_t box_count) { cost_map_.clear(); @@ -88,60 +89,46 @@ Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int de } void CostMap::set_cost_map(int from_seg_index, - const std::vector& costs, + const RoutingCosts& costs, e_representative_entry_method method) { // sort the entries const auto& device_ctx = g_vpr_ctx.device(); - std::vector> costs_per_box(device_ctx.connection_boxes.num_connection_box_types()); - for (const auto& entry : costs) { - costs_per_box[size_t(std::get<3>(entry))].push_back(entry); - } - for (size_t box_id = 0; box_id < device_ctx.connection_boxes.num_connection_box_types(); ++box_id) { - set_cost_map(from_seg_index, ConnectionBoxId(box_id), costs_per_box[box_id], method); + set_cost_map(from_seg_index, ConnectionBoxId(box_id), costs, method); } } -void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const std::vector& costs, e_representative_entry_method method) { +void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs, e_representative_entry_method method) { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); - if (costs.empty()) { + // calculate the bounding box + vtr::Rect bounds; + for (const auto& entry : costs) { + if (entry.first.box_id == box_id) { + bounds |= vtr::Rect(entry.first.delta, 1); + } + } + + if (bounds.empty()) { offset_[from_seg_index][size_t(box_id)] = std::make_pair(0, 0); cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( {size_t(0), size_t(0)}); return; } - // calculate the bounding box - vtr::Rect bounds; - for (const auto& entry : costs) { - bounds |= vtr::Rect(std::get<1>(entry), 1); - } - offset_[from_seg_index][size_t(box_id)] = std::make_pair(bounds.xmin(), bounds.ymin()); - vtr::NdMatrix expansion_cost_map( - {size_t(bounds.width()), size_t(bounds.height())}); - - for (const auto& entry : costs) { - int x = std::get<1>(entry).x() - bounds.xmin(); - int y = std::get<1>(entry).y() - bounds.ymin(); - expansion_cost_map[x][y].add_cost_entry( - method, std::get<2>(entry).delay, - std::get<2>(entry).congestion); - } - cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( {size_t(bounds.width()), size_t(bounds.height())}); auto& matrix = cost_map_[from_seg_index][size_t(box_id)]; - /* set the lookahead cost map entries with a representative cost - * entry from routing_cost_map */ - for (unsigned ix = 0; ix < expansion_cost_map.dim_size(0); ix++) { - for (unsigned iy = 0; iy < expansion_cost_map.dim_size(1); iy++) { - matrix[ix][iy] = expansion_cost_map[ix][iy].get_representative_cost_entry(method); + for (const auto& entry : costs) { + if (entry.first.box_id == box_id) { + int x = entry.first.delta.x() - bounds.xmin(); + int y = entry.first.delta.y() - bounds.ymin(); + matrix[x][y] = entry.second.cost_entry; } } @@ -216,7 +203,9 @@ void CostMap::print(int iseg) const { for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { const auto& entry = matrix[ix][iy]; - if (entry.valid() && entry.delay > avg) { + if (!entry.valid()) { + printf("*"); + } else if (entry.delay > avg) { printf("o"); } else { printf("."); @@ -313,25 +302,18 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, if (to_node_type == SINK) { const auto& sink_to_ipin = device_ctx.connection_boxes.find_sink_connection_boxes(to_node_ind); - if (sink_to_ipin.ipin_count > 1) { - float cost = std::numeric_limits::infinity(); - // Find cheapest cost from from_node_ind to IPINs for this SINK. - for (int i = 0; i < sink_to_ipin.ipin_count; ++i) { - cost = std::min(cost, - get_map_cost( - from_node_ind, - sink_to_ipin.ipin_nodes[i], criticality_fac)); - } - - return cost; - } else if (sink_to_ipin.ipin_count == 1) { - to_node_ind = sink_to_ipin.ipin_nodes[0]; - if (from_node_ind == to_node_ind) { - return 0.f; - } - } else { - return std::numeric_limits::infinity(); + float cost = std::numeric_limits::infinity(); + + // Find cheapest cost from from_node_ind to IPINs for this SINK. + for (int i = 0; i < sink_to_ipin.ipin_count; ++i) { + cost = std::min(cost, + get_map_cost( + from_node_ind, + sink_to_ipin.ipin_nodes[i], criticality_fac)); + if (cost <= 0.f) break; } + + return cost; } if (device_ctx.rr_nodes[to_node_ind].type() != IPIN) { @@ -359,6 +341,10 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, if (!cost_entry.valid()) { // there is no route + // VTR_LOG_WARN("Not connected %d (%s, %d) -> %d (%s, %d, (%d, %d))\n", + // from_node_ind, device_ctx.rr_nodes[from_node_ind].type_string(), from_seg_index, + // to_node_ind, device_ctx.rr_nodes[to_node_ind].type_string(), + // (int)size_t(box_id), (int)box_location.first, (int)box_location.second); return std::numeric_limits::infinity(); } @@ -374,7 +360,7 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, * visited. Each time a pin is visited, the delay/congestion information * to that pin is stored to an entry in the routing_cost_map */ static void run_dijkstra(int start_node_ind, - std::vector& routing_costs) { + std::vector* routing_costs) { auto& device_ctx = g_vpr_ctx.device(); /* a list of boolean flags (one for each rr node) to figure out if a @@ -383,7 +369,7 @@ static void run_dijkstra(int start_node_ind, /* for each node keep a list of the cost with which that node has been * visited (used to determine whether to push a candidate node onto the * expansion queue */ - std::vector node_visited_costs(device_ctx.rr_nodes.size(), -1.0); + std::unordered_map paths; /* a priority queue for expansion */ std::priority_queue, std::greater> pq; @@ -392,12 +378,6 @@ static void run_dijkstra(int start_node_ind, pq.push(first_entry); - const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(start_node_ind); - if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", - start_node_ind); - } - /* now do routing */ while (!pq.empty()) { auto current = pq.top(); @@ -440,35 +420,36 @@ static void run_dijkstra(int start_node_ind, for (auto it = path.rbegin(); it != path.rend(); it++) { auto& parent_node = device_ctx.rr_nodes[parent]; int seg_index = device_ctx.rr_indexed_data[parent_node.cost_index()].seg_index; - if (!node_recorded[parent]) { - - const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); - if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", - parent); - } + const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); + if (from_canonical_loc == nullptr) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", + parent); + } - vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), - ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); - RoutingCostKey key = { - delta, - box_id - }; - RoutingCost cost = { - parent, - node_ind, - Cost_Entry( - current_full.delay - parent_entry.delay, - current_full.congestion_upstream - parent_entry.congestion_upstream) - }; - routing_costs.push_back(std::make_tuple(seg_index, key, cost)); + vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), + ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); + RoutingCostKey key = { + delta, + box_id + }; + RoutingCost val = { + parent, + node_ind, + Cost_Entry( + current_full.delay - parent_entry.delay, + current_full.congestion_upstream - parent_entry.congestion_upstream)}; + + const auto& x = (*routing_costs)[seg_index].find(key); + + // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST + if (x == (*routing_costs)[seg_index].end() || x->second.cost_entry.delay > val.cost_entry.delay) { + (*routing_costs)[seg_index][key] = val; } - node_recorded[parent] = true; + parent_entry = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), parent_entry.delay, parent_entry.R_upstream, parent_entry.congestion_upstream, false); parent = *it; } - node_expanded[node_ind] = true; } else { expand_dijkstra_neighbours(current, paths, node_expanded, pq); node_expanded[node_ind] = true; @@ -489,32 +470,39 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen cost_map_.set_counts(segment_inf.size(), device_ctx.connection_boxes.num_connection_box_types()); + VTR_ASSERT(REPRESENTATIVE_ENTRY_METHOD == SMALLEST); + std::vector all_costs(num_segments); + /* run Dijkstra's algorithm for each segment type & channel type combination */ for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { VTR_LOG("Creating cost map for %s(%d)\n", segment_inf[iseg].name.c_str(), iseg); /* allocate the cost map for this iseg/chan_type */ - std::vector costs; - bool found = false; + std::vector costs(num_segments); for (const auto& row : inodes_for_segment[iseg]) { for (auto cell : row) { for (auto node_ind : cell) { - found = true; - run_dijkstra(node_ind, costs); + run_dijkstra(node_ind, &costs); } } } - if (!found) { - VTR_LOG_WARN("Segment %s(%d) found no start_node_ind\n", - segment_inf[iseg].name.c_str(), iseg); - } else { - /* boil down the cost list in routing_cost_map at each coordinate to a - * representative cost entry and store it in the lookahead cost map */ - cost_map_.set_cost_map(iseg, costs, - REPRESENTATIVE_ENTRY_METHOD); + + for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { + for (const auto& cost : costs[iseg]) { + const auto& key = cost.first; + const auto& val = cost.second; + const auto &x = all_costs[iseg].find(key); + + // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST + if(x == all_costs[iseg].end() || + x->second.cost_entry.delay > val.cost_entry.delay) { + all_costs[iseg][key] = val; + } + } } } + VTR_LOG("Combining results\n"); for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { #if 0 for (auto &e : cost_map_per_segment[iseg]) { @@ -524,9 +512,37 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen std::get<2>(e).delay, std::get<2>(e).congestion); } #endif - //VTR_LOG("cost map for %s(%d)\n", - // segment_inf[iseg].name.c_str(), iseg); - //cost_map_.print(iseg); + const auto &costs = all_costs[iseg]; + if(costs.empty()) { + // check that there were no start nodes + bool empty = true; + for (const auto& row : inodes_for_segment[iseg]) { + for (auto cell : row) { + if (!cell.empty()) { + empty = false; + break; + } + } + if (!empty) break; + } + if (empty) { + VTR_LOG_WARN("Segment %s(%d) found no routes\n", + segment_inf[iseg].name.c_str(), iseg); + } else { + VTR_LOG_WARN("Segment %s(%d) found no routes, even though there are some matching nodes\n", + segment_inf[iseg].name.c_str(), iseg); + } + } else { + /* boil down the cost list in routing_cost_map at each coordinate to a + * representative cost entry and store it in the lookahead cost map */ + cost_map_.set_cost_map(iseg, costs, + REPRESENTATIVE_ENTRY_METHOD); + } + /* + VTR_LOG("cost map for %s(%d)\n", + segment_inf[iseg].name.c_str(), iseg); + cost_map_.print(iseg); + */ } for(std::pair p : cost_map_.list_empty()) { diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index bdd42623f7e..c218c9c5735 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -9,21 +9,46 @@ #include "connection_box.h" #include "vtr_geometry.h" +struct RoutingCostKey { + vtr::Point delta; + ConnectionBoxId box_id; + bool operator==(const RoutingCostKey& other) const { + return delta == other.delta && box_id == other.box_id; + } +}; +struct RoutingCost { + int from_node, to_node; + Cost_Entry cost_entry; +}; + +// specialization of std::hash for RoutingCostKey +namespace std +{ + template<> struct hash + { + typedef RoutingCostKey argument_type; + typedef std::size_t result_type; + result_type operator()(argument_type const& s) const noexcept + { + result_type const h1 ( std::hash{}(s.delta.x()) ); + result_type const h2 ( std::hash{}(s.delta.y()) ); + result_type const h3 ( std::hash{}(size_t(s.box_id)) ); + return h1 ^ ((h2 ^ (h3 << 1)) << 1); + } + }; +} + +typedef std::unordered_map RoutingCosts; + class CostMap { public: - typedef std::tuple, - vtr::Point, - Cost_Entry, - ConnectionBoxId> - routing_cost; - void set_counts(size_t seg_count, size_t box_count); int node_to_segment(int from_node_ind) const; Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; void set_cost_map(int from_seg_index, - const std::vector& costs, + const RoutingCosts& costs, e_representative_entry_method method); - void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const std::vector& costs, e_representative_entry_method method); + void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs, e_representative_entry_method method); Cost_Entry get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); void read(const std::string& file); void write(const std::string& file) const; From e7576698bd73d7cbfb43c2e29b70768defbc84f9 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 10:20:50 -0700 Subject: [PATCH 049/107] make format Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 59 +++++++++---------- vpr/src/route/connection_box_lookahead_map.h | 28 ++++----- vpr/src/route/router_lookahead_map_utils.cpp | 4 +- vpr/src/route/router_lookahead_map_utils.h | 4 +- 4 files changed, 46 insertions(+), 49 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index d2eab064b67..dc685cfdb17 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -132,7 +132,7 @@ void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const Rou } } - std::list > missing; + std::list> missing; bool couldnt_fill = false; auto shifted_bounds = vtr::Rect(0, 0, bounds.width(), bounds.height()); /* find missing cost entries and fill them in by copying a nearby cost entry */ @@ -216,8 +216,8 @@ void CostMap::print(int iseg) const { } } -std::list > CostMap::list_empty() const { - std::list > results; +std::list> CostMap::list_empty() const { + std::list> results; for (int iseg = 0; iseg < (int)cost_map_.dim_size(0); iseg++) { for (int box_id = 0; box_id < (int)cost_map_.dim_size(1); box_id++) { auto& matrix = cost_map_[iseg][box_id]; @@ -283,8 +283,8 @@ Cost_Entry CostMap::get_nearby_cost_entry(const vtr::NdMatrix& ma template vtr::Point sample(const vtr::Rect& r, T x, T y, T d) { - return vtr::Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, - (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); + return vtr::Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, + (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); } float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, @@ -402,17 +402,18 @@ static void run_dijkstra(int start_node_ind, // reconstruct the path std::vector path; - for (int i = node_ind; i != start_node_ind; path.push_back(i = paths[i].parent)); + for (int i = node_ind; i != start_node_ind; path.push_back(i = paths[i].parent)) + ; util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); // recalculate the path with congestion util::PQ_Entry current_full = parent_entry; int parent = start_node_ind; for (auto it = path.rbegin(); it != path.rend(); it++) { - auto& parent_node = device_ctx.rr_nodes[parent]; - current_full = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), current_full.delay, - current_full.R_upstream, current_full.congestion_upstream, false); - parent = *it; + auto& parent_node = device_ctx.rr_nodes[parent]; + current_full = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), current_full.delay, + current_full.R_upstream, current_full.congestion_upstream, false); + parent = *it; } // add each node along the path subtracting the incremental costs from the current costs @@ -422,16 +423,15 @@ static void run_dijkstra(int start_node_ind, int seg_index = device_ctx.rr_indexed_data[parent_node.cost_index()].seg_index; const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", - parent); + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", + parent); } vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); RoutingCostKey key = { - delta, - box_id - }; + delta, + box_id}; RoutingCost val = { parent, node_ind, @@ -491,11 +491,10 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen for (const auto& cost : costs[iseg]) { const auto& key = cost.first; const auto& val = cost.second; - const auto &x = all_costs[iseg].find(key); + const auto& x = all_costs[iseg].find(key); // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - if(x == all_costs[iseg].end() || - x->second.cost_entry.delay > val.cost_entry.delay) { + if (x == all_costs[iseg].end() || x->second.cost_entry.delay > val.cost_entry.delay) { all_costs[iseg][key] = val; } } @@ -512,8 +511,8 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen std::get<2>(e).delay, std::get<2>(e).congestion); } #endif - const auto &costs = all_costs[iseg]; - if(costs.empty()) { + const auto& costs = all_costs[iseg]; + if (costs.empty()) { // check that there were no start nodes bool empty = true; for (const auto& row : inodes_for_segment[iseg]) { @@ -539,13 +538,13 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen REPRESENTATIVE_ENTRY_METHOD); } /* - VTR_LOG("cost map for %s(%d)\n", - segment_inf[iseg].name.c_str(), iseg); - cost_map_.print(iseg); - */ + * VTR_LOG("cost map for %s(%d)\n", + * segment_inf[iseg].name.c_str(), iseg); + * cost_map_.print(iseg); + */ } - for(std::pair p : cost_map_.list_empty()) { + for (std::pair p : cost_map_.list_empty()) { int iseg, box_id; std::tie(iseg, box_id) = p; VTR_LOG("cost map for %s(%d), connection box %d EMPTY\n", @@ -583,7 +582,7 @@ static vtr::Rect bounding_box_for_node(const t_rr_node& node) { node.xhigh() + 1, node.yhigh() + 1); } -static void find_inodes_for_segment_types(std::vector *inodes_for_segment) { +static void find_inodes_for_segment_types(std::vector* inodes_for_segment) { auto& device_ctx = g_vpr_ctx.device(); auto& rr_nodes = device_ctx.rr_nodes; const int num_segments = inodes_for_segment->size(); @@ -722,13 +721,13 @@ void CostMap::read(const std::string& file) { { const auto& offset = cost_map.getOffset(); - ToNdMatrix<2, VprVector2D, std::pair >( + ToNdMatrix<2, VprVector2D, std::pair>( &offset_, offset, ToVprVector2D); } { const auto& cost_maps = cost_map.getCostMap(); - ToNdMatrix<2, Matrix, vtr::NdMatrix >( + ToNdMatrix<2, Matrix, vtr::NdMatrix>( &cost_map_, cost_maps, ToMatrixCostEntry); } } @@ -747,13 +746,13 @@ void CostMap::write(const std::string& file) const { { auto offset = cost_map.initOffset(); - FromNdMatrix<2, VprVector2D, std::pair >( + FromNdMatrix<2, VprVector2D, std::pair>( &offset, offset_, FromVprVector2D); } { auto cost_maps = cost_map.initCostMap(); - FromNdMatrix<2, Matrix, vtr::NdMatrix >( + FromNdMatrix<2, Matrix, vtr::NdMatrix>( &cost_maps, cost_map_, FromMatrixCostEntry); } diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index c218c9c5735..475b615cc7e 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -22,21 +22,19 @@ struct RoutingCost { }; // specialization of std::hash for RoutingCostKey -namespace std -{ - template<> struct hash - { - typedef RoutingCostKey argument_type; - typedef std::size_t result_type; - result_type operator()(argument_type const& s) const noexcept - { - result_type const h1 ( std::hash{}(s.delta.x()) ); - result_type const h2 ( std::hash{}(s.delta.y()) ); - result_type const h3 ( std::hash{}(size_t(s.box_id)) ); - return h1 ^ ((h2 ^ (h3 << 1)) << 1); - } - }; -} +namespace std { +template<> +struct hash { + typedef RoutingCostKey argument_type; + typedef std::size_t result_type; + result_type operator()(argument_type const& s) const noexcept { + result_type const h1(std::hash{}(s.delta.x())); + result_type const h2(std::hash{}(s.delta.y())); + result_type const h3(std::hash{}(size_t(s.box_id))); + return h1 ^ ((h2 ^ (h3 << 1)) << 1); + } +}; +} // namespace std typedef std::unordered_map RoutingCosts; diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 262edaac433..d52faa595de 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -154,7 +154,7 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { float bin_size = delay_diff / (float)num_bins; /* sort the cost entries into bins */ - std::vector > entry_bins(num_bins, std::vector()); + std::vector> entry_bins(num_bins, std::vector()); for (auto entry : this->cost_vector) { float bin_num = floor((entry.delay - min_del_entry.delay) / bin_size); @@ -215,7 +215,7 @@ void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, } /* finally, record the cost with which the child was visited and put the child entry on the queue */ - paths[child_node_ind] = { child_entry.delay_cost, parent_ind, iedge }; + paths[child_node_ind] = {child_entry.delay_cost, parent_ind, iedge}; pq.push(child_entry); } } diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index 44ca3f07d79..bd32915dcd5 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -139,8 +139,8 @@ class PQ_Entry { // A version of PQ_Entry that only calculates and stores the delay (cost.) class PQ_Entry_Lite { public: - int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents - float delay_cost; //the cost of the path to get to this node + int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents + float delay_cost; //the cost of the path to get to this node PQ_Entry_Lite(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, bool starting_node); From 3cc0a402f918e3d00fa60f0c427dd9e139d2d92c Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 13:25:41 -0700 Subject: [PATCH 050/107] add documentation Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 83 ++++++++++++------- vpr/src/route/connection_box_lookahead_map.h | 15 +++- 2 files changed, 68 insertions(+), 30 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index dc685cfdb17..dd0eacc5ec8 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -28,9 +28,12 @@ * (wire type, chan_type) combination we can take the smallest cost, the * average, median, etc. This define selects the method we use. * + * NOTE: Currently, only SMALLEST is supported. + * * See e_representative_entry_method */ #define REPRESENTATIVE_ENTRY_METHOD SMALLEST +/* Sample based an NxN grid of starting segments, where N = SAMPLE_GRID_SIZE */ static constexpr int SAMPLE_GRID_SIZE = 4; typedef std::array, SAMPLE_GRID_SIZE>, SAMPLE_GRID_SIZE> SampleGrid; @@ -39,6 +42,7 @@ static void run_dijkstra(int start_node_ind, std::vector* routing_costs); static void find_inodes_for_segment_types(std::vector* inodes_for_segment); +// resize internal data structures void CostMap::set_counts(size_t seg_count, size_t box_count) { cost_map_.clear(); offset_.clear(); @@ -57,10 +61,12 @@ void CostMap::set_counts(size_t seg_count, size_t box_count) { } } +// cached node -> segment map int CostMap::node_to_segment(int from_node_ind) const { return segment_map_[from_node_ind]; } +// get a cost entry for a segment type, connection box type, and offset Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); const auto& cost_map = cost_map_[from_seg_index][size_t(box_id)]; @@ -88,6 +94,7 @@ Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int de return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; } +// set all cost maps for the segment type void CostMap::set_cost_map(int from_seg_index, const RoutingCosts& costs, e_representative_entry_method method) { @@ -100,6 +107,7 @@ void CostMap::set_cost_map(int from_seg_index, } } +// set the cost map for a segment type and connection box type, filling holes void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs, e_representative_entry_method method) { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); @@ -112,6 +120,7 @@ void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const Rou } if (bounds.empty()) { + // Didn't find any sample routes, so routing isn't possible between these segment/connection box types. offset_[from_seg_index][size_t(box_id)] = std::make_pair(0, 0); cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( {size_t(0), size_t(0)}); @@ -132,10 +141,10 @@ void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const Rou } } + // find missing cost entries and fill them in by copying a nearby cost entry std::list> missing; bool couldnt_fill = false; auto shifted_bounds = vtr::Rect(0, 0, bounds.width(), bounds.height()); - /* find missing cost entries and fill them in by copying a nearby cost entry */ for (unsigned ix = 0; ix < matrix.dim_size(0) && !couldnt_fill; ix++) { for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { Cost_Entry& cost_entry = matrix[ix][iy]; @@ -164,21 +173,13 @@ void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const Rou VTR_ASSERT(!matrix[x][y].valid()); } } -#if 0 - for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { - if(matrix[ix][iy].valid()) { - printf("O"); - } else { - printf("."); - } - } - printf("\n"); - } -#endif } } +// prints an ASCII diagram of each cost map for a segment type (debug) +// o => above average +// . => at or below average +// * => invalid (missing) void CostMap::print(int iseg) const { const auto& device_ctx = g_vpr_ctx.device(); for (size_t box_id = 0; @@ -216,6 +217,7 @@ void CostMap::print(int iseg) const { } } +// list segment type and connection box type pairs that have empty cost maps (debug) std::list> CostMap::list_empty() const { std::list> results; for (int iseg = 0; iseg < (int)cost_map_.dim_size(0); iseg++) { @@ -232,6 +234,7 @@ static void assign_min_entry(Cost_Entry& dst, const Cost_Entry& src) { if (src.congestion < dst.congestion) dst.congestion = src.congestion; } +// find the minimum cost entry from the nearest manhattan distance neighbor Cost_Entry CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, @@ -281,12 +284,17 @@ Cost_Entry CostMap::get_nearby_cost_entry(const vtr::NdMatrix& ma return Cost_Entry(); } +// sample on a uniformly spaced grid within a rectangle +// sample(vtr::Rect(N), 0, 0, M) is vtr::Point(0, 0) +// sample(vtr::Rect(N), M, M, M) is vtr::Point(N, N) +// To avoid the edges, use `sample(r, x+1, y+1, N+1) for x, y, in 0..N-1 template vtr::Point sample(const vtr::Rect& r, T x, T y, T d) { return vtr::Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); } +// derive a cost from the map between two nodes float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, int to_node_ind, float criticality_fac) const { @@ -341,10 +349,13 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, if (!cost_entry.valid()) { // there is no route - // VTR_LOG_WARN("Not connected %d (%s, %d) -> %d (%s, %d, (%d, %d))\n", - // from_node_ind, device_ctx.rr_nodes[from_node_ind].type_string(), from_seg_index, - // to_node_ind, device_ctx.rr_nodes[to_node_ind].type_string(), - // (int)size_t(box_id), (int)box_location.first, (int)box_location.second); +#if 0 + // useful for debugging but can be really noisy + VTR_LOG_WARN("Not connected %d (%s, %d) -> %d (%s, %d, (%d, %d))\n", + from_node_ind, device_ctx.rr_nodes[from_node_ind].type_string(), from_seg_index, + to_node_ind, device_ctx.rr_nodes[to_node_ind].type_string(), + (int)size_t(box_id), (int)box_location.first, (int)box_location.second); +#endif return std::numeric_limits::infinity(); } @@ -366,9 +377,10 @@ static void run_dijkstra(int start_node_ind, /* a list of boolean flags (one for each rr node) to figure out if a * certain node has already been expanded */ std::vector node_expanded(device_ctx.rr_nodes.size(), false); - /* for each node keep a list of the cost with which that node has been + /* For each node keep a list of the cost with which that node has been * visited (used to determine whether to push a candidate node onto the - * expansion queue */ + * expansion queue. + * Also store the parent node so we can reconstruct a specific path. */ std::unordered_map paths; /* a priority queue for expansion */ std::priority_queue, std::greater> pq; @@ -457,6 +469,7 @@ static void run_dijkstra(int start_node_ind, } } +// compute the cost maps for lookahead void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) { vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); @@ -477,7 +490,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { VTR_LOG("Creating cost map for %s(%d)\n", segment_inf[iseg].name.c_str(), iseg); - /* allocate the cost map for this iseg/chan_type */ + std::vector costs(num_segments); for (const auto& row : inodes_for_segment[iseg]) { for (auto cell : row) { @@ -487,6 +500,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } } + // combine the cost map from this run with the final cost maps for each segment for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { for (const auto& cost : costs[iseg]) { const auto& key = cost.first; @@ -504,11 +518,13 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen VTR_LOG("Combining results\n"); for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { #if 0 - for (auto &e : cost_map_per_segment[iseg]) { + for (auto &cost : all_costs[iseg]) { + const auto& key = cost.first; + const auto& val = cost.second; VTR_LOG("%d -> %d (%d, %d): %g, %g\n", - std::get<0>(e).first, std::get<0>(e).second, - std::get<1>(e).first, std::get<1>(e).second, - std::get<2>(e).delay, std::get<2>(e).congestion); + val.from_node, val.to_node, + key.delta.x(), key.delta.y(), + val.cost_entry.delay, val.cost_entry.congestion); } #endif const auto& costs = all_costs[iseg]; @@ -537,21 +553,25 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen cost_map_.set_cost_map(iseg, costs, REPRESENTATIVE_ENTRY_METHOD); } - /* - * VTR_LOG("cost map for %s(%d)\n", - * segment_inf[iseg].name.c_str(), iseg); - * cost_map_.print(iseg); - */ + +#if 0 + VTR_LOG("cost map for %s(%d)\n", + segment_inf[iseg].name.c_str(), iseg); + cost_map_.print(iseg); +#endif } +#if 0 for (std::pair p : cost_map_.list_empty()) { int iseg, box_id; std::tie(iseg, box_id) = p; VTR_LOG("cost map for %s(%d), connection box %d EMPTY\n", segment_inf[iseg].name.c_str(), iseg, box_id); } +#endif } +// get an expected minimum cost for routing from the current node to the target node float ConnectionBoxMapLookahead::get_expected_cost( int current_node, int target_node, @@ -571,6 +591,7 @@ float ConnectionBoxMapLookahead::get_expected_cost( } } +// also known as the L1 norm static int manhattan_distance(const t_rr_node& node, int x, int y) { int node_center_x = (node.xhigh() + node.xlow()) / 2; int node_center_y = (node.yhigh() + node.ylow()) / 2; @@ -582,6 +603,8 @@ static vtr::Rect bounding_box_for_node(const t_rr_node& node) { node.xhigh() + 1, node.yhigh() + 1); } +// for each segment type, find the nearest nodes to an equally spaced grid of points +// within the bounding box for that segment type static void find_inodes_for_segment_types(std::vector* inodes_for_segment) { auto& device_ctx = g_vpr_ctx.device(); auto& rr_nodes = device_ctx.rr_nodes; @@ -646,6 +669,8 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se } } } + + // to break out from the inner loop next_rr_node: continue; } diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 475b615cc7e..6a8e2076c80 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -9,19 +9,29 @@ #include "connection_box.h" #include "vtr_geometry.h" +// Keys in the RoutingCosts map struct RoutingCostKey { + // offset of the destination connection box from the starting segment vtr::Point delta; + + // type of the destination connection box ConnectionBoxId box_id; + bool operator==(const RoutingCostKey& other) const { return delta == other.delta && box_id == other.box_id; } }; + +// Data in the RoutingCosts map struct RoutingCost { + // source and destination node indices int from_node, to_node; + + // cost entry for the route Cost_Entry cost_entry; }; -// specialization of std::hash for RoutingCostKey +// Specialization of std::hash for RoutingCostKey namespace std { template<> struct hash { @@ -36,8 +46,10 @@ struct hash { }; } // namespace std +// Map used to store intermediate routing costs typedef std::unordered_map RoutingCosts; +// Dense cost maps per source segment and destination connection box types class CostMap { public: void set_counts(size_t seg_count, size_t box_count); @@ -59,6 +71,7 @@ class CostMap { std::vector segment_map_; }; +// Implementation of RouterLookahead based on source segment and destination connection box types class ConnectionBoxMapLookahead : public RouterLookahead { public: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; From ab62139964c3e305f564b1fbc5f61a7534118a97 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 15:04:39 -0700 Subject: [PATCH 051/107] un-shadow a variable Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index dd0eacc5ec8..5f17fab1745 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -501,15 +501,15 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } // combine the cost map from this run with the final cost maps for each segment - for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { - for (const auto& cost : costs[iseg]) { + for (int i = 0; i < (ssize_t)num_segments; i++) { + for (const auto& cost : costs[i]) { const auto& key = cost.first; const auto& val = cost.second; - const auto& x = all_costs[iseg].find(key); + const auto& x = all_costs[i].find(key); // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - if (x == all_costs[iseg].end() || x->second.cost_entry.delay > val.cost_entry.delay) { - all_costs[iseg][key] = val; + if (x == all_costs[i].end() || x->second.cost_entry.delay > val.cost_entry.delay) { + all_costs[i][key] = val; } } } From 26387c2ab74b6fdbd3bd12f23b45fc1c28e0aeae Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 17:00:44 -0700 Subject: [PATCH 052/107] remove method from set_cost_map Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 10 ++++------ vpr/src/route/connection_box_lookahead_map.h | 5 ++--- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 5f17fab1745..d5afed24421 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -96,19 +96,18 @@ Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int de // set all cost maps for the segment type void CostMap::set_cost_map(int from_seg_index, - const RoutingCosts& costs, - e_representative_entry_method method) { + const RoutingCosts& costs) { // sort the entries const auto& device_ctx = g_vpr_ctx.device(); for (size_t box_id = 0; box_id < device_ctx.connection_boxes.num_connection_box_types(); ++box_id) { - set_cost_map(from_seg_index, ConnectionBoxId(box_id), costs, method); + set_cost_map(from_seg_index, ConnectionBoxId(box_id), costs); } } // set the cost map for a segment type and connection box type, filling holes -void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs, e_representative_entry_method method) { +void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs) { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); // calculate the bounding box @@ -550,8 +549,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } else { /* boil down the cost list in routing_cost_map at each coordinate to a * representative cost entry and store it in the lookahead cost map */ - cost_map_.set_cost_map(iseg, costs, - REPRESENTATIVE_ENTRY_METHOD); + cost_map_.set_cost_map(iseg, costs); } #if 0 diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 6a8e2076c80..9e5ebb9b3df 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -56,9 +56,8 @@ class CostMap { int node_to_segment(int from_node_ind) const; Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; void set_cost_map(int from_seg_index, - const RoutingCosts& costs, - e_representative_entry_method method); - void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs, e_representative_entry_method method); + const RoutingCosts& costs); + void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs); Cost_Entry get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); void read(const std::string& file); void write(const std::string& file) const; From 5baa6024e0c3f02c8289c1c434362906e6d04bcb Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 24 Oct 2019 12:51:01 -0700 Subject: [PATCH 053/107] replace std::list with std::vector Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 6 +++--- vpr/src/route/connection_box_lookahead_map.h | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index d5afed24421..10cbbfcdf29 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -141,7 +141,7 @@ void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const Rou } // find missing cost entries and fill them in by copying a nearby cost entry - std::list> missing; + std::vector> missing; bool couldnt_fill = false; auto shifted_bounds = vtr::Rect(0, 0, bounds.width(), bounds.height()); for (unsigned ix = 0; ix < matrix.dim_size(0) && !couldnt_fill; ix++) { @@ -217,8 +217,8 @@ void CostMap::print(int iseg) const { } // list segment type and connection box type pairs that have empty cost maps (debug) -std::list> CostMap::list_empty() const { - std::list> results; +std::vector> CostMap::list_empty() const { + std::vector> results; for (int iseg = 0; iseg < (int)cost_map_.dim_size(0); iseg++) { for (int box_id = 0; box_id < (int)cost_map_.dim_size(1); box_id++) { auto& matrix = cost_map_[iseg][box_id]; diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 9e5ebb9b3df..3ad52016c12 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -2,7 +2,6 @@ #define CONNECTION_BOX_LOOKAHEAD_H_ #include -#include #include "physical_types.h" #include "router_lookahead.h" #include "router_lookahead_map_utils.h" @@ -62,7 +61,7 @@ class CostMap { void read(const std::string& file); void write(const std::string& file) const; void print(int iseg) const; - std::list> list_empty() const; + std::vector> list_empty() const; private: vtr::NdMatrix, 2> cost_map_; From c3f7369ec12f40c97d91c44005a3d4ffe2331d04 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 15:03:13 -0700 Subject: [PATCH 054/107] Revert "Add option for search locations." This reverts commit 05b8479d2f4cbd3c191d41a1d25bc0c08103839c. Signed-off-by: Dusty DeWeese --- utils/route_diag/src/main.cpp | 6 ++---- vpr/src/base/SetupVPR.cpp | 1 - vpr/src/base/read_options.cpp | 5 ----- vpr/src/base/read_options.h | 1 - vpr/src/base/vpr_api.cpp | 3 +-- vpr/src/base/vpr_context.h | 2 +- vpr/src/base/vpr_types.h | 1 - vpr/src/place/timing_place_lookup.cpp | 3 +-- vpr/src/route/connection_box_lookahead_map.cpp | 3 +-- vpr/src/route/connection_box_lookahead_map.h | 2 +- vpr/src/route/route_timing.cpp | 9 +++------ vpr/src/route/router_lookahead.cpp | 16 ++++++---------- vpr/src/route/router_lookahead.h | 17 ++++++----------- 13 files changed, 22 insertions(+), 47 deletions(-) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index 30c4fa09773..ee1c467d17c 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -97,8 +97,7 @@ static void do_one_route(int source_node, int sink_node, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf, - router_opts.lookahead_search_locations + segment_inf ); t_heap* cheapest = timing_driven_route_connection_from_route_tree(rt_root, sink_node, cost_params, bounding_box, *router_lookahead, modified_rr_node_inf, router_stats); @@ -140,8 +139,7 @@ static void profile_source(int source_rr_node, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf, - router_opts.lookahead_search_locations + segment_inf ); RouterDelayProfiler profiler(router_lookahead.get()); diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 0c82c04d89a..4fd21004eb5 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -358,7 +358,6 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->doRouting = STAGE_DO; } RouterOpts->routing_failure_predictor = Options.routing_failure_predictor; - RouterOpts->lookahead_search_locations = Options.lookahead_search_locations; RouterOpts->routing_budgets_algorithm = Options.routing_budgets_algorithm; RouterOpts->save_routing_per_iteration = Options.save_routing_per_iteration; RouterOpts->congested_routing_iteration_threshold_frac = Options.congested_routing_iteration_threshold_frac; diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 3ccbe318681..b9bbedf30c3 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1520,11 +1520,6 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.lookahead_search_locations, "--lookahead_search_locations") - .help("Semi-colon seperated x,y coordinates to use for lookahead search coordinates.") - .default_value("") - .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.max_criticality, "--max_criticality") .help( "Sets the maximum fraction of routing cost derived from delay (vs routability) for any net." diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index c8caa7116c4..97d320abbe3 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -152,7 +152,6 @@ struct t_options { argparse::ArgValue router_max_convergence_count; argparse::ArgValue router_reconvergence_cpd_threshold; argparse::ArgValue router_first_iteration_timing_report_file; - argparse::ArgValue lookahead_search_locations; /* Analysis options */ argparse::ArgValue full_stats; diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 63952666e5c..f2900d0d299 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -738,8 +738,7 @@ RouteStatus vpr_route_fixed_W(t_vpr_setup& vpr_setup, vpr_setup.RouterOpts.lookahead_type, vpr_setup.RouterOpts.write_router_lookahead, vpr_setup.RouterOpts.read_router_lookahead, - vpr_setup.Segments, - vpr_setup.RouterOpts.lookahead_search_locations); + vpr_setup.Segments); } vtr::ScopedStartFinishTimer timer("Routing"); diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 55e3548c0c7..122fa95229a 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -304,7 +304,7 @@ struct RoutingContext : public Context { // Cache of router lookahead object. // // Cache key: (lookahead type, read lookahead (if any), segment definitions). - vtr::Cache, std::string>, + vtr::Cache>, RouterLookahead> cached_router_lookahead_; }; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index fa048c56f48..b23080cc4f4 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -949,7 +949,6 @@ struct t_router_opts { float reconvergence_cpd_threshold; std::string first_iteration_timing_report_file; bool strict_checks; - std::string lookahead_search_locations; std::string write_router_lookahead; std::string read_router_lookahead; diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 18402399ea2..4aa439aab16 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -147,8 +147,7 @@ std::unique_ptr compute_place_delay_model(const t_placer_opts& router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf, - router_opts.lookahead_search_locations); + segment_inf); RouterDelayProfiler route_profiler(router_lookahead); int longest_length = get_longest_segment_length(segment_inf); diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 10cbbfcdf29..0fab2b48c86 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -469,8 +469,7 @@ static void run_dijkstra(int start_node_ind, } // compute the cost maps for lookahead -void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf, - const std::string& lookahead_search_locations) { +void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf) { vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); size_t num_segments = segment_inf.size(); diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 3ad52016c12..f25366e3708 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -74,7 +74,7 @@ class ConnectionBoxMapLookahead : public RouterLookahead { public: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; float get_map_cost(int from_node_ind, int to_node_ind, float criticality_fac) const; - void compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) override; + void compute(const std::vector& segment_inf) override; void read(const std::string& file) override; void write(const std::string& file) const override; diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index a9d0465eb68..cc738162be4 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -374,8 +374,7 @@ bool try_timing_driven_route(const t_router_opts& router_opts, router_opts.lookahead_type, router_opts.write_router_lookahead, router_opts.read_router_lookahead, - segment_inf, - router_opts.lookahead_search_locations); + segment_inf); /* * Routing parameters @@ -1514,8 +1513,7 @@ std::vector timing_driven_find_all_shortest_paths_from_route_tree(t_rt_n int target_node = OPEN; auto router_lookahead = make_router_lookahead(e_router_lookahead::NO_OP, /*write_lookahead=*/"", /*read_lookahead=*/"", - /*segment_inf=*/{}, - /*lookahead_search_locations=*/""); + /*segment_inf=*/{}); add_route_tree_to_heap(rt_root, target_node, cost_params, *router_lookahead, router_stats); heap_::build_heap(); // via sifting down everything @@ -1537,8 +1535,7 @@ static std::vector timing_driven_find_all_shortest_paths_from_heap(const RouterStats& router_stats) { auto router_lookahead = make_router_lookahead(e_router_lookahead::NO_OP, /*write_lookahead=*/"", /*read_lookahead=*/"", - /*segment_inf=*/{}, - /*lookahead_search_locations=*/""); + /*segment_inf=*/{}); auto& device_ctx = g_vpr_ctx.device(); std::vector cheapest_paths(device_ctx.rr_nodes.size()); diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp index 7ea29db4e65..80f29911aa9 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead.cpp @@ -28,12 +28,11 @@ std::unique_ptr make_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf, - const std::string& lookahead_search_locations) { + const std::vector& segment_inf) { std::unique_ptr router_lookahead = make_router_lookahead_object(router_lookahead_type); if (read_lookahead.empty()) { - router_lookahead->compute(segment_inf, lookahead_search_locations); + router_lookahead->compute(segment_inf); } else { router_lookahead->read(read_lookahead); } @@ -105,8 +104,7 @@ float MapLookahead::get_expected_cost(int current_node, int target_node, const t } } -void MapLookahead::compute(const std::vector& segment_inf, - const std::string& lookahead_search_locations) { +void MapLookahead::compute(const std::vector& segment_inf) { compute_router_lookahead(segment_inf.size()); } @@ -208,11 +206,10 @@ const RouterLookahead* get_cached_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf, - const std::string& lookahead_search_locations) { + const std::vector& segment_inf) { auto& router_ctx = g_vpr_ctx.routing(); - auto cache_key = std::make_tuple(router_lookahead_type, read_lookahead, segment_inf, lookahead_search_locations); + auto cache_key = std::make_tuple(router_lookahead_type, read_lookahead, segment_inf); // Check if cache is valid. const RouterLookahead* router_lookahead = router_ctx.cached_router_lookahead_.get(cache_key); @@ -228,7 +225,6 @@ const RouterLookahead* get_cached_router_lookahead( router_lookahead_type, write_lookahead, read_lookahead, - segment_inf, - lookahead_search_locations)); + segment_inf)); } } diff --git a/vpr/src/route/router_lookahead.h b/vpr/src/route/router_lookahead.h index 1d797a04484..283df54befe 100644 --- a/vpr/src/route/router_lookahead.h +++ b/vpr/src/route/router_lookahead.h @@ -15,7 +15,7 @@ class RouterLookahead { virtual float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const = 0; // Compute router lookahead (if needed). - virtual void compute(const std::vector& segment_inf, const std::string& lookahead_search_locations) = 0; + virtual void compute(const std::vector& segment_inf) = 0; // Read router lookahead data (if any) from specified file. // May be unimplemented, in which case method should throw an exception. @@ -36,8 +36,7 @@ std::unique_ptr make_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf, - const std::string& lookahead_search_locations); + const std::vector& segment_inf); // Clear router lookahead cache (e.g. when changing or free rrgraph). void invalidate_router_lookahead_cache(); @@ -50,14 +49,12 @@ const RouterLookahead* get_cached_router_lookahead( e_router_lookahead router_lookahead_type, std::string write_lookahead, std::string read_lookahead, - const std::vector& segment_inf, - const std::string& lookahead_search_locations); + const std::vector& segment_inf); class ClassicLookahead : public RouterLookahead { public: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& /*segment_inf*/, - const std::string& /*lookahead_search_locations*/) override { + void compute(const std::vector& /*segment_inf*/) override { } void read(const std::string& /*file*/) override { @@ -74,8 +71,7 @@ class ClassicLookahead : public RouterLookahead { class MapLookahead : public RouterLookahead { protected: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& segment_inf, - const std::string& /*lookahead_search_locations*/) override; + void compute(const std::vector& segment_inf) override; void read(const std::string& /*file*/) override { VPR_THROW(VPR_ERROR_ROUTE, "MapLookahead::read unimplemented"); } @@ -87,8 +83,7 @@ class MapLookahead : public RouterLookahead { class NoOpLookahead : public RouterLookahead { protected: float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - void compute(const std::vector& /*segment_inf*/, - const std::string& /*lookahead_search_locations*/) override { + void compute(const std::vector& /*segment_inf*/) override { } void read(const std::string& /*file*/) override { VPR_THROW(VPR_ERROR_ROUTE, "Read not supported for NoOpLookahead"); From 1de49a0fb22499e479e8f656d396d08d20735522 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 15:07:59 -0700 Subject: [PATCH 055/107] TEMPORARY ignore --lookahead_search_locations Signed-off-by: Dusty DeWeese --- vpr/src/base/read_options.cpp | 5 +++++ vpr/src/base/read_options.h | 1 + 2 files changed, 6 insertions(+) diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index b9bbedf30c3..a9e4d2c810d 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -1520,6 +1520,11 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.lookahead_search_locations, "--lookahead_search_locations") + .help("DEPRECATED Semi-colon seperated x,y coordinates to use for lookahead search coordinates.") + .default_value("") + .show_in(argparse::ShowIn::HELP_ONLY); + route_timing_grp.add_argument(args.max_criticality, "--max_criticality") .help( "Sets the maximum fraction of routing cost derived from delay (vs routability) for any net." diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 97d320abbe3..c8caa7116c4 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -152,6 +152,7 @@ struct t_options { argparse::ArgValue router_max_convergence_count; argparse::ArgValue router_reconvergence_cpd_threshold; argparse::ArgValue router_first_iteration_timing_report_file; + argparse::ArgValue lookahead_search_locations; /* Analysis options */ argparse::ArgValue full_stats; From 147a5af0288c103d87874ba57f9d6138d45f84ad Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 23 Oct 2019 09:25:19 -0700 Subject: [PATCH 056/107] parallelize connection box lookahead Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 0fab2b48c86..ccfe89ec5c0 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -22,6 +22,11 @@ # include "serdes_utils.h" #endif +#if defined(VPR_USE_TBB) +# include +# include +#endif + /* we're profiling routing cost over many tracks for each wire type, so we'll * have many cost entries at each |dx|,|dy| offset. There are many ways to * "boil down" the many costs at each offset to a single entry for a given @@ -485,7 +490,12 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen std::vector all_costs(num_segments); /* run Dijkstra's algorithm for each segment type & channel type combination */ +#if defined(VPR_USE_TBB) + tbb::mutex all_costs_mutex; + tbb::parallel_for(size_t(0), size_t(num_segments), [&](int iseg) { +#else for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { +#endif VTR_LOG("Creating cost map for %s(%d)\n", segment_inf[iseg].name.c_str(), iseg); @@ -498,6 +508,10 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } } +#if defined(VPR_USE_TBB) + all_costs_mutex.lock(); +#endif + // combine the cost map from this run with the final cost maps for each segment for (int i = 0; i < (ssize_t)num_segments; i++) { for (const auto& cost : costs[i]) { @@ -511,7 +525,15 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } } } + +#if defined(VPR_USE_TBB) + all_costs_mutex.unlock(); +#endif +#if !defined(VPR_USE_TBB) } +#else + }); +#endif VTR_LOG("Combining results\n"); for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { From 7ee50b39ebc8c03e239446025669a7f87057147f Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 24 Oct 2019 18:46:28 -0700 Subject: [PATCH 057/107] performance improvements Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 528 +++++++++++------- vpr/src/route/connection_box_lookahead_map.h | 64 ++- 2 files changed, 377 insertions(+), 215 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index ccfe89ec5c0..ce095361e63 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -23,7 +23,7 @@ #endif #if defined(VPR_USE_TBB) -# include +# include # include #endif @@ -37,22 +37,88 @@ * * See e_representative_entry_method */ #define REPRESENTATIVE_ENTRY_METHOD SMALLEST +// #define FILL_LIMIT 30 /* Sample based an NxN grid of starting segments, where N = SAMPLE_GRID_SIZE */ -static constexpr int SAMPLE_GRID_SIZE = 4; - -typedef std::array, SAMPLE_GRID_SIZE>, SAMPLE_GRID_SIZE> SampleGrid; - -static void run_dijkstra(int start_node_ind, - std::vector* routing_costs); +static constexpr int SAMPLE_GRID_SIZE = 3; +static constexpr float COST_LIMIT = std::numeric_limits::infinity(); +static constexpr int DIJKSTRA_CACHE_SIZE = 64; +static constexpr int DIJKSTRA_CACHE_WINDOW = 3; +static constexpr bool BREAK_ON_MISS = false; +static constexpr float PENALTY_FACTOR = 1.f; + +struct SamplePoint { + uint64_t order; + vtr::Point location; + std::vector samples; + SamplePoint() : location(0, 0) {} +}; + +struct SampleGrid { + SamplePoint point[SAMPLE_GRID_SIZE][SAMPLE_GRID_SIZE]; +}; + +template +class SimpleCache { +public: + SimpleCache() : pos(0), hits(0), misses(0) {} + bool get(K key, V* value) { + for (int i = 0; i < N; i++) { + auto &k = keys[i]; + if (k == key) { + auto &v = values[i]; +#if 0 + // preserve the found key by pushing it back + int last = (pos + N - 1) % N; + std::swap(k, keys[last]); + std::swap(v, values[last]); +#endif + *value = v; + hits++; + return true; + } + } + misses++; + return false; + } + void insert(K key, V val) { + keys[pos] = key; + values[pos] = val; + pos = (pos + 1) % N; + } + float hit_ratio() { + return hits ? static_cast(hits) / static_cast(hits + misses) : 0.f; + } + float miss_ratio() { + return misses ? static_cast(misses) / static_cast(hits + misses) : 0.f; + } +private: + std::array keys; // keep keys together for faster scanning + std::array values; + size_t pos; + uint64_t hits; + uint64_t misses; +}; + +static float run_dijkstra(int start_node_ind, + RoutingCosts* routing_costs, + SimpleCache* cache, + float max_cost); static void find_inodes_for_segment_types(std::vector* inodes_for_segment); +// also known as the L1 norm +static int manhattan_distance(const vtr::Point& a, const vtr::Point& b) { + return abs(b.x() - a.x()) + abs(b.y() - a.y()); +} + // resize internal data structures void CostMap::set_counts(size_t seg_count, size_t box_count) { cost_map_.clear(); offset_.clear(); cost_map_.resize({seg_count, box_count}); offset_.resize({seg_count, box_count}); + seg_count_ = seg_count; + box_count_ = box_count; const auto& device_ctx = g_vpr_ctx.device(); segment_map_.resize(device_ctx.rr_nodes.size()); @@ -99,82 +165,119 @@ Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int de return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; } -// set all cost maps for the segment type -void CostMap::set_cost_map(int from_seg_index, - const RoutingCosts& costs) { - // sort the entries - const auto& device_ctx = g_vpr_ctx.device(); - for (size_t box_id = 0; - box_id < device_ctx.connection_boxes.num_connection_box_types(); - ++box_id) { - set_cost_map(from_seg_index, ConnectionBoxId(box_id), costs); - } +static Cost_Entry penalize(const Cost_Entry &entry, int distance, float penalty) { + return Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, + entry.congestion); } // set the cost map for a segment type and connection box type, filling holes -void CostMap::set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs) { - VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); +void CostMap::set_cost_map(const RoutingCosts& costs) { - // calculate the bounding box - vtr::Rect bounds; + // calculate the bounding boxes + vtr::Matrix> bounds({seg_count_, box_count_}); for (const auto& entry : costs) { - if (entry.first.box_id == box_id) { - bounds |= vtr::Rect(entry.first.delta, 1); + bounds[entry.first.seg_index][size_t(entry.first.box_id)] |= vtr::Rect(entry.first.delta, 1); + } + + // store bounds + for (size_t seg = 0; seg < seg_count_; seg++) { + for (size_t box = 0; box < box_count_; box++) { + const auto& seg_box_bounds = bounds[seg][box]; + if (seg_box_bounds.empty()) { + // Didn't find any sample routes, so routing isn't possible between these segment/connection box types. + offset_[seg][box] = std::make_pair(0, 0); + cost_map_[seg][box] = vtr::NdMatrix( + {size_t(0), size_t(0)}); + continue; + } else { + offset_[seg][box] = std::make_pair(seg_box_bounds.xmin(), seg_box_bounds.ymin()); + cost_map_[seg][box] = vtr::NdMatrix( + {size_t(seg_box_bounds.width()), size_t(seg_box_bounds.height())}); + } } } - if (bounds.empty()) { - // Didn't find any sample routes, so routing isn't possible between these segment/connection box types. - offset_[from_seg_index][size_t(box_id)] = std::make_pair(0, 0); - cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( - {size_t(0), size_t(0)}); - return; - } - - offset_[from_seg_index][size_t(box_id)] = std::make_pair(bounds.xmin(), bounds.ymin()); - - cost_map_[from_seg_index][size_t(box_id)] = vtr::NdMatrix( - {size_t(bounds.width()), size_t(bounds.height())}); - auto& matrix = cost_map_[from_seg_index][size_t(box_id)]; - + // store entries into the matrices for (const auto& entry : costs) { - if (entry.first.box_id == box_id) { - int x = entry.first.delta.x() - bounds.xmin(); - int y = entry.first.delta.y() - bounds.ymin(); - matrix[x][y] = entry.second.cost_entry; - } - } + int seg = entry.first.seg_index; + int box = size_t(entry.first.box_id); + const auto& seg_box_bounds = bounds[seg][box]; + int x = entry.first.delta.x() - seg_box_bounds.xmin(); + int y = entry.first.delta.y() - seg_box_bounds.ymin(); + cost_map_[seg][box][x][y] = entry.second.cost_entry; + } + + // fill the holes + for (size_t seg = 0; seg < seg_count_; seg++) { + for (size_t box = 0; box < box_count_; box++) { + const auto& seg_box_bounds = bounds[seg][box]; + if (seg_box_bounds.empty()) { + continue; + } + auto& matrix = cost_map_[seg][box]; - // find missing cost entries and fill them in by copying a nearby cost entry - std::vector> missing; - bool couldnt_fill = false; - auto shifted_bounds = vtr::Rect(0, 0, bounds.width(), bounds.height()); - for (unsigned ix = 0; ix < matrix.dim_size(0) && !couldnt_fill; ix++) { - for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - Cost_Entry& cost_entry = matrix[ix][iy]; - if (!cost_entry.valid()) { - // maximum search radius - Cost_Entry filler = get_nearby_cost_entry(matrix, ix, iy, shifted_bounds); - if (filler.valid()) { - missing.push_back(std::make_tuple(ix, iy, filler)); - } else { - couldnt_fill = true; + // calculate delay penalty + float min_delay = 0.f, max_delay = 0.f; + vtr::Point min_location(0, 0), max_location(0, 0); + for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { + for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { + Cost_Entry& cost_entry = matrix[ix][iy]; + if (cost_entry.valid()) { + if (cost_entry.delay < min_delay) { + min_delay = cost_entry.delay; + min_location = vtr::Point(ix, iy); + } + if (cost_entry.delay > max_delay) { + max_delay = cost_entry.delay; + max_location = vtr::Point(ix, iy); + } + } + } + } + float delay_penalty = (max_delay - min_delay) / static_cast(std::max(1, manhattan_distance(max_location, min_location))); + + // find missing cost entries and fill them in by copying a nearby cost entry + std::vector> missing; + bool couldnt_fill = false; + auto shifted_bounds = vtr::Rect(0, 0, seg_box_bounds.width(), seg_box_bounds.height()); + int max_fill = 0; + for (unsigned ix = 0; ix < matrix.dim_size(0) && !couldnt_fill; ix++) { + for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { + Cost_Entry& cost_entry = matrix[ix][iy]; + if (!cost_entry.valid()) { + // maximum search radius + Cost_Entry filler; + int distance; + std::tie(filler, distance) = get_nearby_cost_entry(matrix, ix, iy, shifted_bounds); + if (filler.valid()) { + missing.push_back(std::make_tuple(ix, iy, penalize(filler, distance, delay_penalty))); + max_fill = std::max(max_fill, distance); + } else { + couldnt_fill = true; + } + } } } - } - } - // write back the missing entries - for (auto& xy_entry : missing) { - matrix[std::get<0>(xy_entry)][std::get<1>(xy_entry)] = std::get<2>(xy_entry); - } + if (!couldnt_fill) { + VTR_LOG("At %d -> %d: max_fill = %d, delay_penalty = %e\n", seg, box, max_fill, delay_penalty); + } + + // write back the missing entries + for (auto& xy_entry : missing) { + matrix[std::get<0>(xy_entry)][std::get<1>(xy_entry)] = std::get<2>(xy_entry); + } - if (couldnt_fill) { - VTR_LOG_WARN("Couldn't fill holes in the cost matrix for %d -> %ld\n", - from_seg_index, size_t(box_id)); - for (unsigned y = 0; y < matrix.dim_size(1); y++) { - for (unsigned x = 0; x < matrix.dim_size(0); x++) { - VTR_ASSERT(!matrix[x][y].valid()); + if (couldnt_fill) { + VTR_LOG_WARN("Couldn't fill holes in the cost matrix for %d -> %ld, %d x %d bounding box\n", + seg, box, seg_box_bounds.width(), seg_box_bounds.height()); +#if !defined(FILL_LIMIT) + for (unsigned y = 0; y < matrix.dim_size(1); y++) { + for (unsigned x = 0; x < matrix.dim_size(0); x++) { + VTR_ASSERT(!matrix[x][y].valid()); + } + } +#endif } } } @@ -210,10 +313,14 @@ void CostMap::print(int iseg) const { const auto& entry = matrix[ix][iy]; if (!entry.valid()) { printf("*"); + } else if (entry.delay * 4 > avg * 5) { + printf("O"); } else if (entry.delay > avg) { printf("o"); - } else { + } else if (entry.delay * 4 > avg * 3) { printf("."); + } else { + printf(" "); } } printf("\n"); @@ -239,53 +346,40 @@ static void assign_min_entry(Cost_Entry& dst, const Cost_Entry& src) { } // find the minimum cost entry from the nearest manhattan distance neighbor -Cost_Entry CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, - int cx, - int cy, - const vtr::Rect& bounds) { +std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, + int cx, + int cy, + const vtr::Rect& bounds) { // spiral around (cx, cy) looking for a nearby entry - int n = 1, x, y; + int n = 1; bool in_bounds; Cost_Entry entry; do { in_bounds = false; - y = cy - n; // top - // left -> right - for (x = cx - n; x < cx + n; x++) { - if (bounds.contains(vtr::Point(x, y))) { - assign_min_entry(entry, matrix[x][y]); - in_bounds = true; - } - } - x = cx + n; // right - // top -> bottom - for (; y < cy + n; y++) { - if (bounds.contains(vtr::Point(x, y))) { - assign_min_entry(entry, matrix[x][y]); - in_bounds = true; - } - } - y = cy + n; // bottom - // right -> left - for (; x > cx - n; x--) { - if (bounds.contains(vtr::Point(x, y))) { - assign_min_entry(entry, matrix[x][y]); + for (int ox = -n; ox <= n; ox++) { + int x = cx + ox; + int oy = n - abs(ox); + int yp = cy + oy; + int yn = cy - oy; + if (bounds.contains(vtr::Point(x, yp))) { + assign_min_entry(entry, matrix[x][yp]); in_bounds = true; } - } - x = cx - n; // left - // bottom -> top - for (; y > cy - n; y--) { - if (bounds.contains(vtr::Point(x, y))) { - assign_min_entry(entry, matrix[x][y]); + if (bounds.contains(vtr::Point(x, yn))) { + assign_min_entry(entry, matrix[x][yn]); in_bounds = true; } } - if (entry.valid()) return entry; + if (entry.valid()) return std::make_pair(entry, n); n++; +#if defined(FILL_LIMIT) + if (n > FILL_LIMIT) { + break; + } +#endif } while (in_bounds); - return Cost_Entry(); + return std::make_pair(Cost_Entry(), n); } // sample on a uniformly spaced grid within a rectangle @@ -374,8 +468,10 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, /* runs Dijkstra's algorithm from specified node until all nodes have been * visited. Each time a pin is visited, the delay/congestion information * to that pin is stored to an entry in the routing_cost_map */ -static void run_dijkstra(int start_node_ind, - std::vector* routing_costs) { +static float run_dijkstra(int start_node_ind, + RoutingCosts* routing_costs, + SimpleCache *cache, + float cost_limit) { auto& device_ctx = g_vpr_ctx.device(); /* a list of boolean flags (one for each rr node) to figure out if a @@ -392,6 +488,8 @@ static void run_dijkstra(int start_node_ind, /* first entry has no upstream delay or congestion */ util::PQ_Entry_Lite first_entry(start_node_ind, UNDEFINED, 0, true); + float max_cost = 0.f; + pq.push(first_entry); /* now do routing */ @@ -446,8 +544,10 @@ static void run_dijkstra(int start_node_ind, vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); RoutingCostKey key = { - delta, - box_id}; + seg_index, + box_id, + delta}; + CompressedRoutingCostKey compressed_key(key); RoutingCost val = { parent, node_ind, @@ -455,11 +555,45 @@ static void run_dijkstra(int start_node_ind, current_full.delay - parent_entry.delay, current_full.congestion_upstream - parent_entry.congestion_upstream)}; - const auto& x = (*routing_costs)[seg_index].find(key); // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - if (x == (*routing_costs)[seg_index].end() || x->second.cost_entry.delay > val.cost_entry.delay) { - (*routing_costs)[seg_index][key] = val; + float cost = 0.f; + bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && + abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; + if(in_window && + cache->get(compressed_key, &cost) && + cost <= val.cost_entry.delay) { + // the sample was not cheaper than the cached sample + if (BREAK_ON_MISS) { + // don't store the rest of the path + break; + } + } else { + const auto& x = routing_costs->find(key); + if (x != routing_costs->end()) { + if(x->second.cost_entry.delay > val.cost_entry.delay) { + // this sample is cheaper + (*routing_costs)[key] = val; + if (in_window) { + cache->insert(compressed_key, val.cost_entry.delay); + } + } else { + // this sample is not cheaper + if (BREAK_ON_MISS) { + // don't store the rest of the path + break; + } + if (in_window) { + cache->insert(compressed_key, x->second.cost_entry.delay); + } + } + } else { + // this sample is new + (*routing_costs)[key] = val; + if (in_window) { + cache->insert(compressed_key, val.cost_entry.delay); + } + } } parent_entry = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), parent_entry.delay, @@ -470,7 +604,13 @@ static void run_dijkstra(int start_node_ind, expand_dijkstra_neighbours(current, paths, node_expanded, pq); node_expanded[node_ind] = true; } + + max_cost = std::max(max_cost, current.delay_cost); + if (max_cost > cost_limit) { + break; + } } + return max_cost; } // compute the cost maps for lookahead @@ -478,8 +618,30 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); size_t num_segments = segment_inf.size(); - std::vector inodes_for_segment(num_segments); - find_inodes_for_segment_types(&inodes_for_segment); + std::vector sample_points; + { + std::vector inodes_for_segment(num_segments); + find_inodes_for_segment_types(&inodes_for_segment); + + // collapse into a vector + for (auto& grid : inodes_for_segment) { + for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { + for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { + auto& point = grid.point[y][x]; + if (!point.samples.empty()) { + point.order = point.samples[0]; + sample_points.push_back(point); + } + } + } + } + } + + // sort by VPR coordinate + std::sort(sample_points.begin(), sample_points.end(), + [](const SamplePoint &a, const SamplePoint &b) { + return a.order < b.order; + }); /* free previous delay map and allocate new one */ auto& device_ctx = g_vpr_ctx.device(); @@ -487,98 +649,74 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen device_ctx.connection_boxes.num_connection_box_types()); VTR_ASSERT(REPRESENTATIVE_ENTRY_METHOD == SMALLEST); - std::vector all_costs(num_segments); + RoutingCosts all_costs; /* run Dijkstra's algorithm for each segment type & channel type combination */ #if defined(VPR_USE_TBB) tbb::mutex all_costs_mutex; - tbb::parallel_for(size_t(0), size_t(num_segments), [&](int iseg) { + tbb::parallel_for_each(sample_points, [&](const SamplePoint& point) { #else - for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { + for (const auto &point : sample_points) { #endif - VTR_LOG("Creating cost map for %s(%d)\n", - segment_inf[iseg].name.c_str(), iseg); - - std::vector costs(num_segments); - for (const auto& row : inodes_for_segment[iseg]) { - for (auto cell : row) { - for (auto node_ind : cell) { - run_dijkstra(node_ind, &costs); - } - } + + float max_cost = 0.f; + RoutingCosts costs; + SimpleCache cache; + for (auto node_ind : point.samples) { + max_cost = std::max(max_cost, run_dijkstra(node_ind, &costs, &cache, COST_LIMIT)); } #if defined(VPR_USE_TBB) all_costs_mutex.lock(); #endif + VTR_LOG("Expanded sample point (%d, %d) %e miss %g\n", + point.location.x(), point.location.y(), max_cost, cache.miss_ratio()); + + // combine the cost map from this run with the final cost maps for each segment - for (int i = 0; i < (ssize_t)num_segments; i++) { - for (const auto& cost : costs[i]) { - const auto& key = cost.first; - const auto& val = cost.second; - const auto& x = all_costs[i].find(key); + for (const auto& cost : costs) { + const auto& key = cost.first; + const auto& val = cost.second; + const auto& x = all_costs.find(key); - // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - if (x == all_costs[i].end() || x->second.cost_entry.delay > val.cost_entry.delay) { - all_costs[i][key] = val; - } + // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST + if (x == all_costs.end() || x->second.cost_entry.delay > val.cost_entry.delay) { + all_costs[key] = val; } } #if defined(VPR_USE_TBB) all_costs_mutex.unlock(); -#endif -#if !defined(VPR_USE_TBB) - } -#else }); +#else + } #endif VTR_LOG("Combining results\n"); - for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { + /* boil down the cost list in routing_cost_map at each coordinate to a + * representative cost entry and store it in the lookahead cost map */ + cost_map_.set_cost_map(all_costs); + +// diagnostics #if 0 - for (auto &cost : all_costs[iseg]) { - const auto& key = cost.first; - const auto& val = cost.second; - VTR_LOG("%d -> %d (%d, %d): %g, %g\n", - val.from_node, val.to_node, - key.delta.x(), key.delta.y(), - val.cost_entry.delay, val.cost_entry.congestion); - } + for (auto &cost : all_costs) { + const auto& key = cost.first; + const auto& val = cost.second; + VTR_LOG("%d -> %d (%d, %d): %g, %g\n", + val.from_node, val.to_node, + key.delta.x(), key.delta.y(), + val.cost_entry.delay, val.cost_entry.congestion); + } #endif - const auto& costs = all_costs[iseg]; - if (costs.empty()) { - // check that there were no start nodes - bool empty = true; - for (const auto& row : inodes_for_segment[iseg]) { - for (auto cell : row) { - if (!cell.empty()) { - empty = false; - break; - } - } - if (!empty) break; - } - if (empty) { - VTR_LOG_WARN("Segment %s(%d) found no routes\n", - segment_inf[iseg].name.c_str(), iseg); - } else { - VTR_LOG_WARN("Segment %s(%d) found no routes, even though there are some matching nodes\n", - segment_inf[iseg].name.c_str(), iseg); - } - } else { - /* boil down the cost list in routing_cost_map at each coordinate to a - * representative cost entry and store it in the lookahead cost map */ - cost_map_.set_cost_map(iseg, costs); - } -#if 0 +#if 1 + for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { VTR_LOG("cost map for %s(%d)\n", segment_inf[iseg].name.c_str(), iseg); cost_map_.print(iseg); -#endif } +#endif #if 0 for (std::pair p : cost_map_.list_empty()) { @@ -610,18 +748,17 @@ float ConnectionBoxMapLookahead::get_expected_cost( } } -// also known as the L1 norm -static int manhattan_distance(const t_rr_node& node, int x, int y) { - int node_center_x = (node.xhigh() + node.xlow()) / 2; - int node_center_y = (node.yhigh() + node.ylow()) / 2; - return abs(node_center_x - x) + abs(node_center_y - y); -} - static vtr::Rect bounding_box_for_node(const t_rr_node& node) { return vtr::Rect(node.xlow(), node.ylow(), node.xhigh() + 1, node.yhigh() + 1); } +static vtr::Point point_for_node(const t_rr_node& node) { + int x = (node.xhigh() + node.xlow()) / 2; + int y = (node.yhigh() + node.ylow()) / 2; + return vtr::Point(x, y); +} + // for each segment type, find the nearest nodes to an equally spaced grid of points // within the bounding box for that segment type static void find_inodes_for_segment_types(std::vector* inodes_for_segment) { @@ -646,15 +783,16 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se inodes_for_segment->clear(); inodes_for_segment->resize(num_segments); for (auto& grid : *inodes_for_segment) { - for (auto& row : grid) { - for (auto& cell : row) { - cell = std::vector(); + for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { + for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { + grid.point[y][x].samples = std::vector(); } } } for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; + vtr::Rect node_bounds = bounding_box_for_node(node); if (node.type() != CHANX && node.type() != CHANY) continue; if (node.capacity() == 0 || device_ctx.connection_boxes.find_canonical_loc(i) == nullptr) continue; @@ -666,24 +804,24 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se auto& grid = (*inodes_for_segment)[seg_index]; for (int sy = 0; sy < SAMPLE_GRID_SIZE; sy++) { for (int sx = 0; sx < SAMPLE_GRID_SIZE; sx++) { - auto& stored_inodes = grid[sy][sx]; - if (stored_inodes.empty()) { - stored_inodes.push_back(i); + auto& point = grid.point[sy][sx]; + if (point.samples.empty()) { + point.samples.push_back(i); + point.location = vtr::Point(node.xlow(), node.ylow()); goto next_rr_node; } - auto& first_stored_node = rr_nodes[stored_inodes.front()]; - if (first_stored_node.xhigh() >= node.xhigh() && first_stored_node.xlow() <= node.xlow() && first_stored_node.yhigh() >= node.yhigh() && first_stored_node.ylow() <= node.ylow()) { - stored_inodes.push_back(i); + if (node_bounds.contains(point.location)) { + point.samples.push_back(i); goto next_rr_node; } vtr::Point target = sample(bounding_box_for_segment[seg_index], sx + 1, sy + 1, SAMPLE_GRID_SIZE + 1); - int distance_new = manhattan_distance(node, target.x(), target.y()); - int distance_stored = manhattan_distance(first_stored_node, target.x(), target.y()); + int distance_new = manhattan_distance(point_for_node(node), target); + int distance_stored = manhattan_distance(point.location, target); if (distance_new < distance_stored) { - stored_inodes.clear(); - stored_inodes.push_back(i); + point.samples.clear(); + point.samples.push_back(i); goto next_rr_node; } } diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index f25366e3708..6d0ae12e013 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -10,14 +10,41 @@ // Keys in the RoutingCosts map struct RoutingCostKey { - // offset of the destination connection box from the starting segment - vtr::Point delta; + // segment type index + int seg_index; // type of the destination connection box ConnectionBoxId box_id; + // offset of the destination connection box from the starting segment + vtr::Point delta; + + RoutingCostKey() : seg_index(-1), delta(0, 0) {} + RoutingCostKey(int seg_index_arg, ConnectionBoxId box_id_arg, vtr::Point delta_arg) : + seg_index(seg_index_arg), box_id(box_id_arg), delta(delta_arg) {} + bool operator==(const RoutingCostKey& other) const { - return delta == other.delta && box_id == other.box_id; + return seg_index == other.seg_index && box_id == other.box_id && delta == other.delta; + } +}; + +// compressed version of RoutingCostKey +// TODO add bounds checks +struct CompressedRoutingCostKey { + uint32_t data; + + CompressedRoutingCostKey() { + data = -1; + } + CompressedRoutingCostKey(const RoutingCostKey& key) { + data = key.seg_index & 0xff; data <<= 8; + data |= size_t(key.box_id) & 0xff; data <<= 8; + data |= key.delta.x() & 0xff; data <<= 8; + data |= key.delta.y() & 0xff; + } + + bool operator==(CompressedRoutingCostKey other) const { + return data == other.data; } }; @@ -30,23 +57,20 @@ struct RoutingCost { Cost_Entry cost_entry; }; -// Specialization of std::hash for RoutingCostKey -namespace std { -template<> -struct hash { - typedef RoutingCostKey argument_type; - typedef std::size_t result_type; - result_type operator()(argument_type const& s) const noexcept { - result_type const h1(std::hash{}(s.delta.x())); - result_type const h2(std::hash{}(s.delta.y())); - result_type const h3(std::hash{}(size_t(s.box_id))); - return h1 ^ ((h2 ^ (h3 << 1)) << 1); +// hash implementation for RoutingCostKey +struct HashRoutingCostKey { + std::size_t operator()(RoutingCostKey const& key) const noexcept { + uint64_t data; + data = key.seg_index & 0xffff; data <<= 16; + data |= size_t(key.box_id) & 0xffff; data <<= 16; + data |= key.delta.x() & 0xffff; data <<= 16; + data |= key.delta.y() & 0xffff; + return std::hash{}(data); } }; -} // namespace std // Map used to store intermediate routing costs -typedef std::unordered_map RoutingCosts; +typedef std::unordered_map RoutingCosts; // Dense cost maps per source segment and destination connection box types class CostMap { @@ -54,10 +78,8 @@ class CostMap { void set_counts(size_t seg_count, size_t box_count); int node_to_segment(int from_node_ind) const; Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; - void set_cost_map(int from_seg_index, - const RoutingCosts& costs); - void set_cost_map(int from_seg_index, ConnectionBoxId box_id, const RoutingCosts& costs); - Cost_Entry get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); + void set_cost_map(const RoutingCosts& costs); + std::pair get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); void read(const std::string& file); void write(const std::string& file) const; void print(int iseg) const; @@ -67,6 +89,8 @@ class CostMap { vtr::NdMatrix, 2> cost_map_; vtr::NdMatrix, 2> offset_; std::vector segment_map_; + size_t seg_count_; + size_t box_count_; }; // Implementation of RouterLookahead based on source segment and destination connection box types From 4b31ffd76a71fc2ba4f288a73504c520281f05a7 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 30 Oct 2019 15:41:54 -0700 Subject: [PATCH 058/107] make format Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 48 +++++++++---------- vpr/src/route/connection_box_lookahead_map.h | 30 ++++++++---- 2 files changed, 43 insertions(+), 35 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index ce095361e63..3233080b1cc 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -51,7 +51,8 @@ struct SamplePoint { uint64_t order; vtr::Point location; std::vector samples; - SamplePoint() : location(0, 0) {} + SamplePoint() + : location(0, 0) {} }; struct SampleGrid { @@ -60,13 +61,16 @@ struct SampleGrid { template class SimpleCache { -public: - SimpleCache() : pos(0), hits(0), misses(0) {} + public: + SimpleCache() + : pos(0) + , hits(0) + , misses(0) {} bool get(K key, V* value) { for (int i = 0; i < N; i++) { - auto &k = keys[i]; + auto& k = keys[i]; if (k == key) { - auto &v = values[i]; + auto& v = values[i]; #if 0 // preserve the found key by pushing it back int last = (pos + N - 1) % N; @@ -92,7 +96,8 @@ class SimpleCache { float miss_ratio() { return misses ? static_cast(misses) / static_cast(hits + misses) : 0.f; } -private: + + private: std::array keys; // keep keys together for faster scanning std::array values; size_t pos; @@ -101,9 +106,9 @@ class SimpleCache { }; static float run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs, - SimpleCache* cache, - float max_cost); + RoutingCosts* routing_costs, + SimpleCache* cache, + float max_cost); static void find_inodes_for_segment_types(std::vector* inodes_for_segment); // also known as the L1 norm @@ -165,14 +170,13 @@ Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int de return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; } -static Cost_Entry penalize(const Cost_Entry &entry, int distance, float penalty) { +static Cost_Entry penalize(const Cost_Entry& entry, int distance, float penalty) { return Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, entry.congestion); } // set the cost map for a segment type and connection box type, filling holes void CostMap::set_cost_map(const RoutingCosts& costs) { - // calculate the bounding boxes vtr::Matrix> bounds({seg_count_, box_count_}); for (const auto& entry : costs) { @@ -375,7 +379,7 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix FILL_LIMIT) { - break; + break; } #endif } while (in_bounds); @@ -470,7 +474,7 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, * to that pin is stored to an entry in the routing_cost_map */ static float run_dijkstra(int start_node_ind, RoutingCosts* routing_costs, - SimpleCache *cache, + SimpleCache* cache, float cost_limit) { auto& device_ctx = g_vpr_ctx.device(); @@ -555,14 +559,10 @@ static float run_dijkstra(int start_node_ind, current_full.delay - parent_entry.delay, current_full.congestion_upstream - parent_entry.congestion_upstream)}; - // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST float cost = 0.f; - bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && - abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; - if(in_window && - cache->get(compressed_key, &cost) && - cost <= val.cost_entry.delay) { + bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; + if (in_window && cache->get(compressed_key, &cost) && cost <= val.cost_entry.delay) { // the sample was not cheaper than the cached sample if (BREAK_ON_MISS) { // don't store the rest of the path @@ -571,7 +571,7 @@ static float run_dijkstra(int start_node_ind, } else { const auto& x = routing_costs->find(key); if (x != routing_costs->end()) { - if(x->second.cost_entry.delay > val.cost_entry.delay) { + if (x->second.cost_entry.delay > val.cost_entry.delay) { // this sample is cheaper (*routing_costs)[key] = val; if (in_window) { @@ -639,7 +639,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen // sort by VPR coordinate std::sort(sample_points.begin(), sample_points.end(), - [](const SamplePoint &a, const SamplePoint &b) { + [](const SamplePoint& a, const SamplePoint& b) { return a.order < b.order; }); @@ -656,9 +656,8 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen tbb::mutex all_costs_mutex; tbb::parallel_for_each(sample_points, [&](const SamplePoint& point) { #else - for (const auto &point : sample_points) { + for (const auto& point : sample_points) { #endif - float max_cost = 0.f; RoutingCosts costs; SimpleCache cache; @@ -673,7 +672,6 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen VTR_LOG("Expanded sample point (%d, %d) %e miss %g\n", point.location.x(), point.location.y(), max_cost, cache.miss_ratio()); - // combine the cost map from this run with the final cost maps for each segment for (const auto& cost : costs) { const auto& key = cost.first; @@ -713,7 +711,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen #if 1 for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { VTR_LOG("cost map for %s(%d)\n", - segment_inf[iseg].name.c_str(), iseg); + segment_inf[iseg].name.c_str(), iseg); cost_map_.print(iseg); } #endif diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 6d0ae12e013..cb7b0f652cb 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -19,12 +19,16 @@ struct RoutingCostKey { // offset of the destination connection box from the starting segment vtr::Point delta; - RoutingCostKey() : seg_index(-1), delta(0, 0) {} - RoutingCostKey(int seg_index_arg, ConnectionBoxId box_id_arg, vtr::Point delta_arg) : - seg_index(seg_index_arg), box_id(box_id_arg), delta(delta_arg) {} + RoutingCostKey() + : seg_index(-1) + , delta(0, 0) {} + RoutingCostKey(int seg_index_arg, ConnectionBoxId box_id_arg, vtr::Point delta_arg) + : seg_index(seg_index_arg) + , box_id(box_id_arg) + , delta(delta_arg) {} bool operator==(const RoutingCostKey& other) const { - return seg_index == other.seg_index && box_id == other.box_id && delta == other.delta; + return seg_index == other.seg_index && box_id == other.box_id && delta == other.delta; } }; @@ -37,9 +41,12 @@ struct CompressedRoutingCostKey { data = -1; } CompressedRoutingCostKey(const RoutingCostKey& key) { - data = key.seg_index & 0xff; data <<= 8; - data |= size_t(key.box_id) & 0xff; data <<= 8; - data |= key.delta.x() & 0xff; data <<= 8; + data = key.seg_index & 0xff; + data <<= 8; + data |= size_t(key.box_id) & 0xff; + data <<= 8; + data |= key.delta.x() & 0xff; + data <<= 8; data |= key.delta.y() & 0xff; } @@ -61,9 +68,12 @@ struct RoutingCost { struct HashRoutingCostKey { std::size_t operator()(RoutingCostKey const& key) const noexcept { uint64_t data; - data = key.seg_index & 0xffff; data <<= 16; - data |= size_t(key.box_id) & 0xffff; data <<= 16; - data |= key.delta.x() & 0xffff; data <<= 16; + data = key.seg_index & 0xffff; + data <<= 16; + data |= size_t(key.box_id) & 0xffff; + data <<= 16; + data |= key.delta.x() & 0xffff; + data <<= 16; data |= key.delta.y() & 0xffff; return std::hash{}(data); } From 0f553eae3df42a920d2495ce3d0e28e7d7948556 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 30 Oct 2019 16:25:13 -0700 Subject: [PATCH 059/107] suggested changes Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 3233080b1cc..70c238e66ab 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -344,9 +344,11 @@ std::vector> CostMap::list_empty() const { return results; } -static void assign_min_entry(Cost_Entry& dst, const Cost_Entry& src) { - if (src.delay < dst.delay) dst.delay = src.delay; - if (src.congestion < dst.congestion) dst.congestion = src.congestion; +static void assign_min_entry(Cost_Entry* dst, const Cost_Entry& src) { + if (src.delay < dst->delay) { + dst->delay = src.delay; + dst->congestion = src.congestion; + } } // find the minimum cost entry from the nearest manhattan distance neighbor @@ -367,11 +369,11 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix(x, yp))) { - assign_min_entry(entry, matrix[x][yp]); + assign_min_entry(&entry, matrix[x][yp]); in_bounds = true; } if (bounds.contains(vtr::Point(x, yn))) { - assign_min_entry(entry, matrix[x][yn]); + assign_min_entry(&entry, matrix[x][yn]); in_bounds = true; } } @@ -465,7 +467,10 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, float expected_congestion = cost_entry.congestion; float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; - VTR_ASSERT(std::isfinite(expected_cost) && expected_cost >= 0.f); + if (!std::isfinite(expected_cost) || expected_cost < 0.f) { + VTR_LOG_ERROR("invalid cost for segment %d to connection box %d at (%d, %d)\n", from_seg_index, (int)size_t(box_id), (int)dx, (int)dy); + VTR_ASSERT(0); + } return expected_cost; } From c0a6a40587aa5e9ac7fbb801cd3f8ea93acb1afb Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 30 Oct 2019 18:18:10 -0700 Subject: [PATCH 060/107] changes suggested in PR Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 261 +++++++++++------- vpr/src/route/route_timing.h | 2 + 2 files changed, 158 insertions(+), 105 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 70c238e66ab..7f247e3b1ce 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -39,26 +39,41 @@ #define REPRESENTATIVE_ENTRY_METHOD SMALLEST // #define FILL_LIMIT 30 -/* Sample based an NxN grid of starting segments, where N = SAMPLE_GRID_SIZE */ +#define CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_MAPS + +// Sample based an NxN grid of starting segments, where N = SAMPLE_GRID_SIZE static constexpr int SAMPLE_GRID_SIZE = 3; + +// Stop Dijkstra expansion after reaching COST_LIMIT static constexpr float COST_LIMIT = std::numeric_limits::infinity(); + +// Number of entries in the routing cost cache static constexpr int DIJKSTRA_CACHE_SIZE = 64; + +// Only entries with a delta inside the window (+- DIJKSTRA_CACHE_WINDOW x/y) are cached static constexpr int DIJKSTRA_CACHE_WINDOW = 3; + +// Don't continue storing a path after hitting a lower-or-same cost entry. static constexpr bool BREAK_ON_MISS = false; + +// Distance penalties filling are calculated based on available samples, but can be adjusted with this factor. static constexpr float PENALTY_FACTOR = 1.f; +// a sample point for a segment type, contains all segments at the VPR location struct SamplePoint { - uint64_t order; + uint64_t order; // used to order sample points vtr::Point location; std::vector samples; SamplePoint() : location(0, 0) {} }; +// a grid of sample points struct SampleGrid { SamplePoint point[SAMPLE_GRID_SIZE][SAMPLE_GRID_SIZE]; }; +// implements a simple cache of key(K)/value(V) pairs of N entries template class SimpleCache { public: @@ -66,12 +81,14 @@ class SimpleCache { : pos(0) , hits(0) , misses(0) {} + + // O(N) lookup bool get(K key, V* value) { for (int i = 0; i < N; i++) { auto& k = keys[i]; if (k == key) { auto& v = values[i]; -#if 0 +#if defined(CONNECTION_BOX_LOOKAHEAD_PUSH_BACK_HITS) // preserve the found key by pushing it back int last = (pos + N - 1) % N; std::swap(k, keys[last]); @@ -85,14 +102,20 @@ class SimpleCache { misses++; return false; } + + // O(1) insertion (overwriting an older entry) void insert(K key, V val) { keys[pos] = key; values[pos] = val; pos = (pos + 1) % N; } + + // ratio of successful lookups float hit_ratio() { return hits ? static_cast(hits) / static_cast(hits + misses) : 0.f; } + + // ratio of unsuccessful lookups float miss_ratio() { return misses ? static_cast(misses) / static_cast(hits + misses) : 0.f; } @@ -245,7 +268,7 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { bool couldnt_fill = false; auto shifted_bounds = vtr::Rect(0, 0, seg_box_bounds.width(), seg_box_bounds.height()); int max_fill = 0; - for (unsigned ix = 0; ix < matrix.dim_size(0) && !couldnt_fill; ix++) { + for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { Cost_Entry& cost_entry = matrix[ix][iy]; if (!cost_entry.valid()) { @@ -261,6 +284,11 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { } } } +#if !defined(FILL_LIMIT) + if (couldnt_fill) { + break; + } +#endif } if (!couldnt_fill) { @@ -453,13 +481,11 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, if (!cost_entry.valid()) { // there is no route -#if 0 - // useful for debugging but can be really noisy - VTR_LOG_WARN("Not connected %d (%s, %d) -> %d (%s, %d, (%d, %d))\n", - from_node_ind, device_ctx.rr_nodes[from_node_ind].type_string(), from_seg_index, - to_node_ind, device_ctx.rr_nodes[to_node_ind].type_string(), - (int)size_t(box_id), (int)box_location.first, (int)box_location.second); -#endif + VTR_LOGV_DEBUG(f_router_debug, + "Not connected %d (%s, %d) -> %d (%s, %d, (%d, %d))\n", + from_node_ind, device_ctx.rr_nodes[from_node_ind].type_string(), from_seg_index, + to_node_ind, device_ctx.rr_nodes[to_node_ind].type_string(), + (int)size_t(box_id), (int)box_location.first, (int)box_location.second); return std::numeric_limits::infinity(); } @@ -474,6 +500,110 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, return expected_cost; } +// add a best cost routing path from start_node_ind to node_ind to routing costs +static void add_paths(int start_node_ind, + int node_ind, + std::unordered_map* paths, + RoutingCosts* routing_costs, + SimpleCache* cache) { + auto& device_ctx = g_vpr_ctx.device(); + ConnectionBoxId box_id; + std::pair box_location; + bool found = device_ctx.connection_boxes.find_connection_box( + node_ind, &box_id, &box_location); + if (!found) { + VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); + } + + // reconstruct the path + std::vector path; + for (int i = node_ind; i != start_node_ind; path.push_back(i = (*paths)[i].parent)) + ; + util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); + + // recalculate the path with congestion + util::PQ_Entry current_full = parent_entry; + int parent = start_node_ind; + for (auto it = path.rbegin(); it != path.rend(); it++) { + auto& parent_node = device_ctx.rr_nodes[parent]; + current_full = util::PQ_Entry(*it, parent_node.edge_switch((*paths)[*it].edge), current_full.delay, + current_full.R_upstream, current_full.congestion_upstream, false); + parent = *it; + } + + // add each node along the path subtracting the incremental costs from the current costs + parent = start_node_ind; + for (auto it = path.rbegin(); it != path.rend(); it++) { + auto& parent_node = device_ctx.rr_nodes[parent]; + int seg_index = device_ctx.rr_indexed_data[parent_node.cost_index()].seg_index; + const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); + if (from_canonical_loc == nullptr) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", + parent); + } + + vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), + ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); + RoutingCostKey key = { + seg_index, + box_id, + delta}; + CompressedRoutingCostKey compressed_key(key); + RoutingCost val = { + parent, + node_ind, + Cost_Entry( + current_full.delay - parent_entry.delay, + current_full.congestion_upstream - parent_entry.congestion_upstream)}; + + // NOTE: implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST + + // use a cache for a small window around a delta of (0, 0) + float cost = 0.f; + bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; + if (in_window && cache->get(compressed_key, &cost) && cost <= val.cost_entry.delay) { + // the sample was not cheaper than the cached sample + const auto& x = routing_costs->find(key); + VTR_ASSERT(x != routing_costs->end()); + if (BREAK_ON_MISS) { + // don't store the rest of the path + break; + } + } else { + const auto& x = routing_costs->find(key); + if (x != routing_costs->end()) { + if (x->second.cost_entry.delay > val.cost_entry.delay) { + // this sample is cheaper + (*routing_costs)[key] = val; + if (in_window) { + cache->insert(compressed_key, val.cost_entry.delay); + } + } else { + // this sample is not cheaper + if (BREAK_ON_MISS) { + // don't store the rest of the path + break; + } + if (in_window) { + cache->insert(compressed_key, x->second.cost_entry.delay); + } + } + } else { + // this sample is new + (*routing_costs)[key] = val; + if (in_window) { + cache->insert(compressed_key, val.cost_entry.delay); + } + } + } + + // update parent data + parent_entry = util::PQ_Entry(*it, parent_node.edge_switch((*paths)[*it].edge), parent_entry.delay, + parent_entry.R_upstream, parent_entry.congestion_upstream, false); + parent = *it; + } +} + /* runs Dijkstra's algorithm from specified node until all nodes have been * visited. Each time a pin is visited, the delay/congestion information * to that pin is stored to an entry in the routing_cost_map */ @@ -515,96 +645,7 @@ static float run_dijkstra(int start_node_ind, /* if this node is an ipin record its congestion/delay in the routing_cost_map */ if (device_ctx.rr_nodes[node_ind].type() == IPIN) { - ConnectionBoxId box_id; - std::pair box_location; - bool found = device_ctx.connection_boxes.find_connection_box( - node_ind, &box_id, &box_location); - if (!found) { - VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); - } - - // reconstruct the path - std::vector path; - for (int i = node_ind; i != start_node_ind; path.push_back(i = paths[i].parent)) - ; - util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); - - // recalculate the path with congestion - util::PQ_Entry current_full = parent_entry; - int parent = start_node_ind; - for (auto it = path.rbegin(); it != path.rend(); it++) { - auto& parent_node = device_ctx.rr_nodes[parent]; - current_full = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), current_full.delay, - current_full.R_upstream, current_full.congestion_upstream, false); - parent = *it; - } - - // add each node along the path subtracting the incremental costs from the current costs - parent = start_node_ind; - for (auto it = path.rbegin(); it != path.rend(); it++) { - auto& parent_node = device_ctx.rr_nodes[parent]; - int seg_index = device_ctx.rr_indexed_data[parent_node.cost_index()].seg_index; - const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); - if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", - parent); - } - - vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), - ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); - RoutingCostKey key = { - seg_index, - box_id, - delta}; - CompressedRoutingCostKey compressed_key(key); - RoutingCost val = { - parent, - node_ind, - Cost_Entry( - current_full.delay - parent_entry.delay, - current_full.congestion_upstream - parent_entry.congestion_upstream)}; - - // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - float cost = 0.f; - bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; - if (in_window && cache->get(compressed_key, &cost) && cost <= val.cost_entry.delay) { - // the sample was not cheaper than the cached sample - if (BREAK_ON_MISS) { - // don't store the rest of the path - break; - } - } else { - const auto& x = routing_costs->find(key); - if (x != routing_costs->end()) { - if (x->second.cost_entry.delay > val.cost_entry.delay) { - // this sample is cheaper - (*routing_costs)[key] = val; - if (in_window) { - cache->insert(compressed_key, val.cost_entry.delay); - } - } else { - // this sample is not cheaper - if (BREAK_ON_MISS) { - // don't store the rest of the path - break; - } - if (in_window) { - cache->insert(compressed_key, x->second.cost_entry.delay); - } - } - } else { - // this sample is new - (*routing_costs)[key] = val; - if (in_window) { - cache->insert(compressed_key, val.cost_entry.delay); - } - } - } - - parent_entry = util::PQ_Entry(*it, parent_node.edge_switch(paths[*it].edge), parent_entry.delay, - parent_entry.R_upstream, parent_entry.congestion_upstream, false); - parent = *it; - } + add_paths(start_node_ind, node_ind, &paths, routing_costs, cache); } else { expand_dijkstra_neighbours(current, paths, node_expanded, pq); node_expanded[node_ind] = true; @@ -664,8 +705,15 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen for (const auto& point : sample_points) { #endif float max_cost = 0.f; + + // holds the cost entries for a run RoutingCosts costs; + + // a cache to avoid hammering the RoutingCosts map, since lookups will be dominated by a few keys + // must be consistent with `costs` i.e. any entry in the cache should also be in `costs` + // NOTE: this is used as a write-through cache, maybe try write-back SimpleCache cache; + for (auto node_ind : point.samples) { max_cost = std::max(max_cost, run_dijkstra(node_ind, &costs, &cache, COST_LIMIT)); } @@ -702,8 +750,8 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen cost_map_.set_cost_map(all_costs); // diagnostics -#if 0 - for (auto &cost : all_costs) { +#if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_ENTRIES) + for (auto& cost : all_costs) { const auto& key = cost.first; const auto& val = cost.second; VTR_LOG("%d -> %d (%d, %d): %g, %g\n", @@ -713,7 +761,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } #endif -#if 1 +#if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_MAPS) for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { VTR_LOG("cost map for %s(%d)\n", segment_inf[iseg].name.c_str(), iseg); @@ -721,7 +769,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } #endif -#if 0 +#if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_EMPTY_MAPS) for (std::pair p : cost_map_.list_empty()) { int iseg, box_id; std::tie(iseg, box_id) = p; @@ -751,11 +799,14 @@ float ConnectionBoxMapLookahead::get_expected_cost( } } +// the smallest bounding box containing a node static vtr::Rect bounding_box_for_node(const t_rr_node& node) { return vtr::Rect(node.xlow(), node.ylow(), node.xhigh() + 1, node.yhigh() + 1); } +// the center point for a node +// it is unknown where the the node starts, so use the average static vtr::Point point_for_node(const t_rr_node& node) { int x = (node.xhigh() + node.xlow()) / 2; int y = (node.yhigh() + node.ylow()) / 2; diff --git a/vpr/src/route/route_timing.h b/vpr/src/route/route_timing.h index c356b096c3b..7f3a646624d 100644 --- a/vpr/src/route/route_timing.h +++ b/vpr/src/route/route_timing.h @@ -11,6 +11,8 @@ #include "router_stats.h" #include "router_lookahead.h" +extern bool f_router_debug; + int get_max_pins_per_net(); bool try_timing_driven_route(const t_router_opts& router_opts, From f919545cd1aac1b07b6648fd59d9c37d3132fb55 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 31 Oct 2019 18:19:10 -0700 Subject: [PATCH 061/107] add penalty to Cost_Map::find_cost for points outside of the map Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 54 +++++++++++-------- vpr/src/route/connection_box_lookahead_map.h | 5 +- 2 files changed, 34 insertions(+), 25 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 7f247e3b1ce..27882c65fed 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -139,12 +139,29 @@ static int manhattan_distance(const vtr::Point& a, const vtr::Point& b return abs(b.x() - a.x()) + abs(b.y() - a.y()); } +template +constexpr const T& clamp( const T& v, const T& lo, const T& hi ) { + return std::min(std::max(v, lo), hi); +} + +template +static vtr::Point closest_point_in_rect(const vtr::Rect& r, const vtr::Point& p) { + if(r.empty()) { + return vtr::Point(0, 0); + } else { + return vtr::Point(clamp(p.x(), r.xmin(), r.xmax() - 1), + clamp(p.y(), r.ymin(), r.ymax() - 1)); + } +} + // resize internal data structures void CostMap::set_counts(size_t seg_count, size_t box_count) { cost_map_.clear(); offset_.clear(); + penalty_.clear(); cost_map_.resize({seg_count, box_count}); offset_.resize({seg_count, box_count}); + penalty_.resize({seg_count, box_count}); seg_count_ = seg_count; box_count_ = box_count; @@ -165,6 +182,11 @@ int CostMap::node_to_segment(int from_node_ind) const { return segment_map_[from_node_ind]; } +static Cost_Entry penalize(const Cost_Entry& entry, int distance, float penalty) { + return Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, + entry.congestion); +} + // get a cost entry for a segment type, connection box type, and offset Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); @@ -173,29 +195,14 @@ Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int de return Cost_Entry(); } - int dx = delta_x - offset_[from_seg_index][size_t(box_id)].first; - int dy = delta_y - offset_[from_seg_index][size_t(box_id)].second; - - if (dx < 0) { - dx = 0; - } - if (dy < 0) { - dy = 0; - } - - if (dx >= (ssize_t)cost_map.dim_size(0)) { - dx = cost_map.dim_size(0) - 1; - } - if (dy >= (ssize_t)cost_map.dim_size(1)) { - dy = cost_map.dim_size(1) - 1; - } - - return cost_map_[from_seg_index][size_t(box_id)][dx][dy]; -} - -static Cost_Entry penalize(const Cost_Entry& entry, int distance, float penalty) { - return Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, - entry.congestion); + vtr::Point coord(delta_x - offset_[from_seg_index][size_t(box_id)].first, + delta_y - offset_[from_seg_index][size_t(box_id)].second); + vtr::Rect bounds(0, 0, cost_map.dim_size(0), cost_map.dim_size(1)); + auto closest = closest_point_in_rect(bounds, coord); + auto cost = cost_map_[from_seg_index][size_t(box_id)][closest.x()][closest.y()]; + float penalty = penalty_[from_seg_index][size_t(box_id)]; + auto distance = manhattan_distance(closest, coord); + return penalize(cost, distance, penalty); } // set the cost map for a segment type and connection box type, filling holes @@ -262,6 +269,7 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { } } float delay_penalty = (max_delay - min_delay) / static_cast(std::max(1, manhattan_distance(max_location, min_location))); + penalty_[seg][box] = delay_penalty; // find missing cost entries and fill them in by copying a nearby cost entry std::vector> missing; diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index cb7b0f652cb..108f75e5969 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -96,8 +96,9 @@ class CostMap { std::vector> list_empty() const; private: - vtr::NdMatrix, 2> cost_map_; - vtr::NdMatrix, 2> offset_; + vtr::Matrix> cost_map_; + vtr::Matrix> offset_; + vtr::Matrix penalty_; std::vector segment_map_; size_t seg_count_; size_t box_count_; From b031fe01dcdefdb139f0f96f09bbf8b3a7f2d2df Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Fri, 1 Nov 2019 18:07:41 -0700 Subject: [PATCH 062/107] store penalties Signed-off-by: Dusty DeWeese --- libs/libvtrcapnproto/connection_map.capnp | 5 ++++ .../route/connection_box_lookahead_map.cpp | 25 ++++++++++++++++++- 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/libs/libvtrcapnproto/connection_map.capnp b/libs/libvtrcapnproto/connection_map.capnp index 1ca672108c8..bc445a30e70 100644 --- a/libs/libvtrcapnproto/connection_map.capnp +++ b/libs/libvtrcapnproto/connection_map.capnp @@ -12,8 +12,13 @@ struct VprVector2D { y @1 :Int64; } +struct VprFloatEntry { + value @0 :Float32; +} + struct VprCostMap { costMap @0 :Matrix.Matrix((Matrix.Matrix(VprCostEntry))); offset @1 :Matrix.Matrix(VprVector2D); segmentMap @2 :List(Int64); + penalty @3 :Matrix.Matrix(VprFloatEntry); } diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 27882c65fed..f2d5ecaf350 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -244,6 +244,7 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { // fill the holes for (size_t seg = 0; seg < seg_count_; seg++) { for (size_t box = 0; box < box_count_; box++) { + penalty_[seg][box] = std::numeric_limits::infinity(); const auto& seg_box_bounds = bounds[seg][box]; if (seg_box_bounds.empty()) { continue; @@ -251,7 +252,7 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { auto& matrix = cost_map_[seg][box]; // calculate delay penalty - float min_delay = 0.f, max_delay = 0.f; + float min_delay = std::numeric_limits::infinity(), max_delay = 0.f; vtr::Point min_location(0, 0), max_location(0, 0); for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { @@ -944,6 +945,16 @@ static void FromMatrixCostEntry( out, in, FromCostEntry); } +static void ToFloat(float* out, const VprFloatEntry::Reader& in) { + // Getting a scalar field is always "get()". + *out = in.getValue(); +} + +static void FromFloat(VprFloatEntry::Builder* out, const float& in) { + // Setting a scalar field is always "set(value)". + out->setValue(in); +} + void CostMap::read(const std::string& file) { MmapFile f(file); @@ -974,6 +985,12 @@ void CostMap::read(const std::string& file) { ToNdMatrix<2, Matrix, vtr::NdMatrix>( &cost_map_, cost_maps, ToMatrixCostEntry); } + + { + const auto& penalty = cost_map.getPenalty(); + ToNdMatrix<2, VprFloatEntry, float>( + &penalty_, penalty, ToFloat); + } } void CostMap::write(const std::string& file) const { @@ -1000,6 +1017,12 @@ void CostMap::write(const std::string& file) const { &cost_maps, cost_map_, FromMatrixCostEntry); } + { + auto penalty = cost_map.initPenalty(); + FromNdMatrix<2, VprFloatEntry, float>( + &penalty, penalty_, FromFloat); + } + writeMessageToFile(file, &builder); } #endif From b640e62c8e9100acb88b5eb800707dd421c5e1ac Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Fri, 1 Nov 2019 18:07:54 -0700 Subject: [PATCH 063/107] move Cost_Entry into the util namespace Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 50 +++++++++---------- vpr/src/route/connection_box_lookahead_map.h | 8 +-- vpr/src/route/router_lookahead_map_utils.cpp | 8 ++- vpr/src/route/router_lookahead_map_utils.h | 2 +- 4 files changed, 36 insertions(+), 32 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index f2d5ecaf350..ac18db7dc36 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -182,17 +182,17 @@ int CostMap::node_to_segment(int from_node_ind) const { return segment_map_[from_node_ind]; } -static Cost_Entry penalize(const Cost_Entry& entry, int distance, float penalty) { - return Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, +static util::Cost_Entry penalize(const util::Cost_Entry& entry, int distance, float penalty) { + return util::Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, entry.congestion); } // get a cost entry for a segment type, connection box type, and offset -Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { +util::Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); const auto& cost_map = cost_map_[from_seg_index][size_t(box_id)]; if (cost_map.dim_size(0) == 0 || cost_map.dim_size(1) == 0) { - return Cost_Entry(); + return util::Cost_Entry(); } vtr::Point coord(delta_x - offset_[from_seg_index][size_t(box_id)].first, @@ -220,13 +220,13 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { if (seg_box_bounds.empty()) { // Didn't find any sample routes, so routing isn't possible between these segment/connection box types. offset_[seg][box] = std::make_pair(0, 0); - cost_map_[seg][box] = vtr::NdMatrix( + cost_map_[seg][box] = vtr::NdMatrix( {size_t(0), size_t(0)}); continue; } else { offset_[seg][box] = std::make_pair(seg_box_bounds.xmin(), seg_box_bounds.ymin()); - cost_map_[seg][box] = vtr::NdMatrix( - {size_t(seg_box_bounds.width()), size_t(seg_box_bounds.height())}); + cost_map_[seg][box] = vtr::NdMatrix( + {size_t(seg_box_bounds.width()), size_t(seg_box_bounds.height())}, util::Cost_Entry()); } } } @@ -256,7 +256,7 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { vtr::Point min_location(0, 0), max_location(0, 0); for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - Cost_Entry& cost_entry = matrix[ix][iy]; + util::Cost_Entry& cost_entry = matrix[ix][iy]; if (cost_entry.valid()) { if (cost_entry.delay < min_delay) { min_delay = cost_entry.delay; @@ -273,16 +273,16 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { penalty_[seg][box] = delay_penalty; // find missing cost entries and fill them in by copying a nearby cost entry - std::vector> missing; + std::vector> missing; bool couldnt_fill = false; auto shifted_bounds = vtr::Rect(0, 0, seg_box_bounds.width(), seg_box_bounds.height()); int max_fill = 0; for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - Cost_Entry& cost_entry = matrix[ix][iy]; + util::Cost_Entry& cost_entry = matrix[ix][iy]; if (!cost_entry.valid()) { // maximum search radius - Cost_Entry filler; + util::Cost_Entry filler; int distance; std::tie(filler, distance) = get_nearby_cost_entry(matrix, ix, iy, shifted_bounds); if (filler.valid()) { @@ -381,7 +381,7 @@ std::vector> CostMap::list_empty() const { return results; } -static void assign_min_entry(Cost_Entry* dst, const Cost_Entry& src) { +static void assign_min_entry(util::Cost_Entry* dst, const util::Cost_Entry& src) { if (src.delay < dst->delay) { dst->delay = src.delay; dst->congestion = src.congestion; @@ -389,14 +389,14 @@ static void assign_min_entry(Cost_Entry* dst, const Cost_Entry& src) { } // find the minimum cost entry from the nearest manhattan distance neighbor -std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, +std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds) { // spiral around (cx, cy) looking for a nearby entry int n = 1; bool in_bounds; - Cost_Entry entry; + util::Cost_Entry entry; do { in_bounds = false; @@ -422,7 +422,7 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrixsecond) - ssize_t(box_location.second); int from_seg_index = cost_map_.node_to_segment(from_node_ind); - Cost_Entry cost_entry = cost_map_.find_cost(from_seg_index, box_id, dx, dy); + util::Cost_Entry cost_entry = cost_map_.find_cost(from_seg_index, box_id, dx, dy); if (!cost_entry.valid()) { // there is no route @@ -561,7 +561,7 @@ static void add_paths(int start_node_ind, RoutingCost val = { parent, node_ind, - Cost_Entry( + util::Cost_Entry( current_full.delay - parent_entry.delay, current_full.congestion_upstream - parent_entry.congestion_upstream)}; @@ -914,12 +914,12 @@ void ConnectionBoxMapLookahead::write(const std::string& file) const { cost_map_.write(file); } -static void ToCostEntry(Cost_Entry* out, const VprCostEntry::Reader& in) { +static void ToCostEntry(util::Cost_Entry* out, const VprCostEntry::Reader& in) { out->delay = in.getDelay(); out->congestion = in.getCongestion(); } -static void FromCostEntry(VprCostEntry::Builder* out, const Cost_Entry& in) { +static void FromCostEntry(VprCostEntry::Builder* out, const util::Cost_Entry& in) { out->setDelay(in.delay); out->setCongestion(in.congestion); } @@ -933,15 +933,15 @@ static void FromVprVector2D(VprVector2D::Builder* out, const std::pair out->setY(in.second); } -static void ToMatrixCostEntry(vtr::NdMatrix* out, +static void ToMatrixCostEntry(vtr::NdMatrix* out, const Matrix::Reader& in) { - ToNdMatrix<2, VprCostEntry, Cost_Entry>(out, in, ToCostEntry); + ToNdMatrix<2, VprCostEntry, util::Cost_Entry>(out, in, ToCostEntry); } static void FromMatrixCostEntry( Matrix::Builder* out, - const vtr::NdMatrix& in) { - FromNdMatrix<2, VprCostEntry, Cost_Entry>( + const vtr::NdMatrix& in) { + FromNdMatrix<2, VprCostEntry, util::Cost_Entry>( out, in, FromCostEntry); } @@ -982,7 +982,7 @@ void CostMap::read(const std::string& file) { { const auto& cost_maps = cost_map.getCostMap(); - ToNdMatrix<2, Matrix, vtr::NdMatrix>( + ToNdMatrix<2, Matrix, vtr::NdMatrix>( &cost_map_, cost_maps, ToMatrixCostEntry); } @@ -1013,7 +1013,7 @@ void CostMap::write(const std::string& file) const { { auto cost_maps = cost_map.initCostMap(); - FromNdMatrix<2, Matrix, vtr::NdMatrix>( + FromNdMatrix<2, Matrix, vtr::NdMatrix>( &cost_maps, cost_map_, FromMatrixCostEntry); } diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 108f75e5969..9b5bdb0afea 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -61,7 +61,7 @@ struct RoutingCost { int from_node, to_node; // cost entry for the route - Cost_Entry cost_entry; + util::Cost_Entry cost_entry; }; // hash implementation for RoutingCostKey @@ -87,16 +87,16 @@ class CostMap { public: void set_counts(size_t seg_count, size_t box_count); int node_to_segment(int from_node_ind) const; - Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; + util::Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; void set_cost_map(const RoutingCosts& costs); - std::pair get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); + std::pair get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); void read(const std::string& file); void write(const std::string& file) const; void print(int iseg) const; std::vector> list_empty() const; private: - vtr::Matrix> cost_map_; + vtr::Matrix> cost_map_; vtr::Matrix> offset_; vtr::Matrix penalty_; std::vector segment_map_; diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index d52faa595de..e4ea0902d28 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -4,10 +4,12 @@ #include "vpr_context.h" #include "vtr_math.h" +namespace util { + /* Number of CLBs I think the average conn. goes. */ static const int CLB_DIST = 3; -util::PQ_Entry::PQ_Entry( +PQ_Entry::PQ_Entry( int set_rr_node_ind, int switch_ind, float parent_delay, @@ -59,7 +61,7 @@ util::PQ_Entry::PQ_Entry( this->cost = this->delay; } -util::PQ_Entry_Lite::PQ_Entry_Lite( +PQ_Entry_Lite::PQ_Entry_Lite( int set_rr_node_ind, int switch_ind, float parent_delay, @@ -182,6 +184,8 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { return representative_entry; } +} // namespace util + /* iterates over the children of the specified node and selectively pushes them onto the priority queue */ void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, std::unordered_map& paths, diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index bd32915dcd5..a9fa6fbfc67 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -33,6 +33,7 @@ enum e_representative_entry_method { MEDIAN }; +namespace util { /* f_cost_map is an array of these cost entries that specifies delay/congestion estimates * to travel relative x/y distances */ class Cost_Entry { @@ -116,7 +117,6 @@ class Expansion_Cost_Entry { } }; -namespace util { /* a class that represents an entry in the Dijkstra expansion priority queue */ class PQ_Entry { public: From 38fe25d47935ad9d25815bd8f358f7d03d12ddb1 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Mon, 4 Nov 2019 12:02:23 -0800 Subject: [PATCH 064/107] move sample() into vtr_geometry and add test Signed-off-by: Dusty DeWeese --- libs/libvtrutil/src/vtr_geometry.h | 19 ++++++++++++++----- libs/libvtrutil/src/vtr_geometry.tpp | 7 +++++++ libs/libvtrutil/test/test_geometry.cpp | 8 ++++++++ .../route/connection_box_lookahead_map.cpp | 10 ---------- 4 files changed, 29 insertions(+), 15 deletions(-) diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 3627545be70..0545581b3dd 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -1,6 +1,7 @@ #ifndef VTR_GEOMETRY_H #define VTR_GEOMETRY_H #include "vtr_range.h" +#include "vtr_assert.h" #include #include @@ -117,11 +118,6 @@ class Rect { friend bool operator== <>(const Rect& lhs, const Rect& rhs); friend bool operator!= <>(const Rect& lhs, const Rect& rhs); - //Return the smallest rectangle containing both given rectangles - //Note that this isn't a union and the resulting rectangle may include points not in either given rectangle - template - friend Rect bounding_box(const Rect& lhs, const Rect& rhs); - public: //Mutators //Co-ordinates void set_xmin(T xmin_val); @@ -137,6 +133,19 @@ class Rect { Point top_right_; }; +//Return the smallest rectangle containing both given rectangles +//Note that this isn't a union and the resulting rectangle may include points not in either given rectangle +template +Rect bounding_box(const Rect& lhs, const Rect& rhs); + +//Sample on a uniformly spaced grid within a rectangle +// sample(vtr::Rect(l, h), 0, 0, M) == l +// sample(vtr::Rect(l, h), M, M, M) == h +//To avoid the edges, use `sample(r, x+1, y+1, N+1) for x, y, in 0..N-1 +//Only defined for integral types +template::value>::type...> +Point sample(const vtr::Rect& r, T x, T y, T d); + //A 2D line template class Line { diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 4698ec7a913..971fb22a29a 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -174,6 +174,13 @@ Rect bounding_box(const Rect& lhs, const Rect& rhs) { std::max(lhs.ymax(), rhs.ymax())); } +template::value>::type...> +Point sample(const vtr::Rect& r, T x, T y, T d) { + VTR_ASSERT(d > 0); + return Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, + (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); +} + template void Rect::set_xmin(T xmin_val) { bottom_left_.set_x(xmin_val); diff --git a/libs/libvtrutil/test/test_geometry.cpp b/libs/libvtrutil/test/test_geometry.cpp index b89d7be9c3a..8d3d91f4444 100644 --- a/libs/libvtrutil/test/test_geometry.cpp +++ b/libs/libvtrutil/test/test_geometry.cpp @@ -85,6 +85,14 @@ TEST_CASE("Rect", "[vtr_geometry/Rect]") { SECTION("empty_int") { REQUIRE(vtr::Rect().empty()); } + + SECTION("sample_int") { + auto r = vtr::Rect(pi_1, pi_2); + REQUIRE(sample(r, 0, 0, 17) == pi_1); + REQUIRE(sample(r, 17, 17, 17) == pi_2); + auto inside = sample(r, 3, 11, 17); + REQUIRE(r.contains(inside)); + } } // float tests diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index ac18db7dc36..4512879e84b 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -425,16 +425,6 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMat return std::make_pair(util::Cost_Entry(), n); } -// sample on a uniformly spaced grid within a rectangle -// sample(vtr::Rect(N), 0, 0, M) is vtr::Point(0, 0) -// sample(vtr::Rect(N), M, M, M) is vtr::Point(N, N) -// To avoid the edges, use `sample(r, x+1, y+1, N+1) for x, y, in 0..N-1 -template -vtr::Point sample(const vtr::Rect& r, T x, T y, T d) { - return vtr::Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, - (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); -} - // derive a cost from the map between two nodes float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, int to_node_ind, From 85ec8ad052ba5fffdd05a02a9eaa9871fb4766ae Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Mon, 4 Nov 2019 12:03:57 -0800 Subject: [PATCH 065/107] make format Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 4512879e84b..eaef8d21cc7 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -140,13 +140,13 @@ static int manhattan_distance(const vtr::Point& a, const vtr::Point& b } template -constexpr const T& clamp( const T& v, const T& lo, const T& hi ) { +constexpr const T& clamp(const T& v, const T& lo, const T& hi) { return std::min(std::max(v, lo), hi); } template static vtr::Point closest_point_in_rect(const vtr::Rect& r, const vtr::Point& p) { - if(r.empty()) { + if (r.empty()) { return vtr::Point(0, 0); } else { return vtr::Point(clamp(p.x(), r.xmin(), r.xmax() - 1), @@ -184,7 +184,7 @@ int CostMap::node_to_segment(int from_node_ind) const { static util::Cost_Entry penalize(const util::Cost_Entry& entry, int distance, float penalty) { return util::Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, - entry.congestion); + entry.congestion); } // get a cost entry for a segment type, connection box type, and offset @@ -390,9 +390,9 @@ static void assign_min_entry(util::Cost_Entry* dst, const util::Cost_Entry& src) // find the minimum cost entry from the nearest manhattan distance neighbor std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, - int cx, - int cy, - const vtr::Rect& bounds) { + int cx, + int cy, + const vtr::Rect& bounds) { // spiral around (cx, cy) looking for a nearby entry int n = 1; bool in_bounds; From 6a4cffb50366ea4de798864dd25e36a3c9031c6e Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Mon, 4 Nov 2019 12:33:36 -0800 Subject: [PATCH 066/107] printf -> VTR_LOG Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index eaef8d21cc7..1ad337c117d 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -335,10 +335,10 @@ void CostMap::print(int iseg) const { box_id++) { auto& matrix = cost_map_[iseg][box_id]; if (matrix.dim_size(0) == 0 || matrix.dim_size(1) == 0) { - printf("cost EMPTY for box_id = %lu\n", box_id); + VTR_LOG("cost EMPTY for box_id = %lu\n", box_id); continue; } - printf("cost for box_id = %lu\n", box_id); + VTR_LOG("cost for box_id = %lu\n", box_id); double sum = 0.0; for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { @@ -353,18 +353,18 @@ void CostMap::print(int iseg) const { for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { const auto& entry = matrix[ix][iy]; if (!entry.valid()) { - printf("*"); + VTR_LOG("*"); } else if (entry.delay * 4 > avg * 5) { - printf("O"); + VTR_LOG("O"); } else if (entry.delay > avg) { - printf("o"); + VTR_LOG("o"); } else if (entry.delay * 4 > avg * 3) { - printf("."); + VTR_LOG("."); } else { - printf(" "); + VTR_LOG(" "); } } - printf("\n"); + VTR_LOG("\n"); } } } From 25e3566166b3448fef8e01d43880baa52a8aff28 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 6 Nov 2019 12:01:55 -0800 Subject: [PATCH 067/107] change sampling method Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 122 ++++++++++++------ 1 file changed, 83 insertions(+), 39 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 1ad337c117d..eb28edce486 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -799,17 +799,49 @@ float ConnectionBoxMapLookahead::get_expected_cost( } // the smallest bounding box containing a node -static vtr::Rect bounding_box_for_node(const t_rr_node& node) { - return vtr::Rect(node.xlow(), node.ylow(), - node.xhigh() + 1, node.yhigh() + 1); +static vtr::Rect bounding_box_for_node(const ConnectionBoxes &connection_boxes, int node_ind) { + const std::pair* loc = connection_boxes.find_canonical_loc(node_ind); + if (loc == nullptr) { + return vtr::Rect(); + } else { + return vtr::Rect(vtr::Point(loc->first, loc->second)); + } } -// the center point for a node -// it is unknown where the the node starts, so use the average -static vtr::Point point_for_node(const t_rr_node& node) { - int x = (node.xhigh() + node.xlow()) / 2; - int y = (node.yhigh() + node.ylow()) / 2; - return vtr::Point(x, y); +static vtr::Point choose_point(const vtr::Matrix& counts, const vtr::Rect& bounding_box, int sx, int sy, int n) { + vtr::Rect window(sample(bounding_box, sx, sy, n), + sample(bounding_box, sx+1, sy+1, n)); + vtr::Point center = sample(window, 1, 1, 2); + vtr::Point sample_point = center; + int sample_distance = 0; + int sample_count = counts[sample_point.x()][sample_point.y()]; + for (int y = window.ymin(); y < window.ymax(); y++) { + for (int x = window.xmin(); x < window.xmax(); x++) { + vtr::Point here(x, y); + int count = counts[x][y]; + if (count < sample_count) continue; + int distance = manhattan_distance(center, here); + if (count > sample_count || + (count == sample_count && distance < sample_distance)) { + sample_point = here; + sample_count = count; + sample_distance = distance; + } + } + } + return sample_point; +} + +// linear lookup, so consider something more sophisticated for large SAMPLE_GRID_SIZEs +static std::pair grid_lookup(const SampleGrid& grid, vtr::Point point) { + for (int sy = 0; sy < SAMPLE_GRID_SIZE; sy++) { + for (int sx = 0; sx < SAMPLE_GRID_SIZE; sx++) { + if (grid.point[sy][sx].location == point) { + return std::make_pair(sx, sy); + } + } + } + return std::make_pair(-1, -1); } // for each segment type, find the nearest nodes to an equally spaced grid of points @@ -818,6 +850,7 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se auto& device_ctx = g_vpr_ctx.device(); auto& rr_nodes = device_ctx.rr_nodes; const int num_segments = inodes_for_segment->size(); + std::vector> segment_counts(num_segments); // compute bounding boxes for each segment type std::vector> bounding_box_for_segment(num_segments, vtr::Rect()); @@ -829,10 +862,16 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se VTR_ASSERT(seg_index != OPEN); VTR_ASSERT(seg_index < num_segments); - bounding_box_for_segment[seg_index] |= bounding_box_for_node(node); + bounding_box_for_segment[seg_index].expand_bounding_box(bounding_box_for_node(device_ctx.connection_boxes, i)); } - // select an inode near the center of the bounding box for each segment type + // initialize counts + for (int seg = 0; seg < num_segments; seg++) { + const auto& box = bounding_box_for_segment[seg]; + segment_counts[seg] = vtr::Matrix({size_t(box.width()), size_t(box.height())}, 0); + } + + // initialize the samples vector for each sample point inodes_for_segment->clear(); inodes_for_segment->resize(num_segments); for (auto& grid : *inodes_for_segment) { @@ -843,46 +882,51 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se } } + // count sample points for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; - vtr::Rect node_bounds = bounding_box_for_node(node); if (node.type() != CHANX && node.type() != CHANY) continue; - if (node.capacity() == 0 || device_ctx.connection_boxes.find_canonical_loc(i) == nullptr) continue; + if (node.capacity() == 0) continue; + const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(i); + if (loc == nullptr) continue; int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; + segment_counts[seg_index][loc->first][loc->second] += 1; VTR_ASSERT(seg_index != OPEN); VTR_ASSERT(seg_index < num_segments); + } - auto& grid = (*inodes_for_segment)[seg_index]; - for (int sy = 0; sy < SAMPLE_GRID_SIZE; sy++) { - for (int sx = 0; sx < SAMPLE_GRID_SIZE; sx++) { - auto& point = grid.point[sy][sx]; - if (point.samples.empty()) { - point.samples.push_back(i); - point.location = vtr::Point(node.xlow(), node.ylow()); - goto next_rr_node; - } - - if (node_bounds.contains(point.location)) { - point.samples.push_back(i); - goto next_rr_node; - } - - vtr::Point target = sample(bounding_box_for_segment[seg_index], sx + 1, sy + 1, SAMPLE_GRID_SIZE + 1); - int distance_new = manhattan_distance(point_for_node(node), target); - int distance_stored = manhattan_distance(point.location, target); - if (distance_new < distance_stored) { - point.samples.clear(); - point.samples.push_back(i); - goto next_rr_node; - } + // select sample points + for (int i = 0; i < num_segments; i++) { + const auto& counts = segment_counts[i]; + const auto& bounding_box = bounding_box_for_segment[i]; + auto& grid = (*inodes_for_segment)[i]; + for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { + for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { + grid.point[y][x].location = choose_point(counts, bounding_box, x, y, SAMPLE_GRID_SIZE); } } + } - // to break out from the inner loop - next_rr_node: - continue; + // select an inode near the center of the bounding box for each segment type + for (size_t i = 0; i < rr_nodes.size(); i++) { + auto& node = rr_nodes[i]; + if (node.type() != CHANX && node.type() != CHANY) continue; + if (node.capacity() == 0) continue; + const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(i); + if (loc == nullptr) continue; + + int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; + + VTR_ASSERT(seg_index != OPEN); + VTR_ASSERT(seg_index < num_segments); + + auto& grid = (*inodes_for_segment)[seg_index]; + auto grid_loc = grid_lookup(grid, vtr::Point(loc->first, loc->second)); + if (grid_loc.first >= 0) { + grid.point[grid_loc.first][grid_loc.second].samples.push_back(i); + } } } From 9577224362f29583f866ba316a5e3c0aefa38564 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 6 Nov 2019 13:40:27 -0800 Subject: [PATCH 068/107] remove unnecessary lookups Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index eb28edce486..cbfc635421d 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -562,18 +562,18 @@ static void add_paths(int start_node_ind, bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; if (in_window && cache->get(compressed_key, &cost) && cost <= val.cost_entry.delay) { // the sample was not cheaper than the cached sample - const auto& x = routing_costs->find(key); - VTR_ASSERT(x != routing_costs->end()); if (BREAK_ON_MISS) { // don't store the rest of the path break; } } else { - const auto& x = routing_costs->find(key); - if (x != routing_costs->end()) { - if (x->second.cost_entry.delay > val.cost_entry.delay) { + + auto result = routing_costs->insert(std::make_pair(key, val)); + if (!result.second) { + auto &existing = result.first->second; + if (existing.cost_entry.delay > val.cost_entry.delay) { // this sample is cheaper - (*routing_costs)[key] = val; + existing = val; if (in_window) { cache->insert(compressed_key, val.cost_entry.delay); } @@ -584,7 +584,7 @@ static void add_paths(int start_node_ind, break; } if (in_window) { - cache->insert(compressed_key, x->second.cost_entry.delay); + cache->insert(compressed_key, existing.cost_entry.delay); } } } else { @@ -728,11 +728,12 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen for (const auto& cost : costs) { const auto& key = cost.first; const auto& val = cost.second; - const auto& x = all_costs.find(key); + const auto& result = all_costs.insert(std::make_pair(key, val)); + auto& existing = result.first->second; // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - if (x == all_costs.end() || x->second.cost_entry.delay > val.cost_entry.delay) { - all_costs[key] = val; + if (!result.second || existing.cost_entry.delay > val.cost_entry.delay) { + existing = val; } } From 9c1f4b1c981ca4e2267679ecf7590b659e44e6a7 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Wed, 6 Nov 2019 17:39:47 -0800 Subject: [PATCH 069/107] remove SimpleCache, use vtr::hash_combine, add timing stats Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 167 +++++------------- vpr/src/route/connection_box_lookahead_map.h | 37 +--- 2 files changed, 54 insertions(+), 150 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index cbfc635421d..ca31e4dd424 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -47,14 +47,8 @@ static constexpr int SAMPLE_GRID_SIZE = 3; // Stop Dijkstra expansion after reaching COST_LIMIT static constexpr float COST_LIMIT = std::numeric_limits::infinity(); -// Number of entries in the routing cost cache -static constexpr int DIJKSTRA_CACHE_SIZE = 64; - -// Only entries with a delta inside the window (+- DIJKSTRA_CACHE_WINDOW x/y) are cached -static constexpr int DIJKSTRA_CACHE_WINDOW = 3; - // Don't continue storing a path after hitting a lower-or-same cost entry. -static constexpr bool BREAK_ON_MISS = false; +static constexpr bool BREAK_ON_MISS = true; // Distance penalties filling are calculated based on available samples, but can be adjusted with this factor. static constexpr float PENALTY_FACTOR = 1.f; @@ -73,65 +67,9 @@ struct SampleGrid { SamplePoint point[SAMPLE_GRID_SIZE][SAMPLE_GRID_SIZE]; }; -// implements a simple cache of key(K)/value(V) pairs of N entries -template -class SimpleCache { - public: - SimpleCache() - : pos(0) - , hits(0) - , misses(0) {} - - // O(N) lookup - bool get(K key, V* value) { - for (int i = 0; i < N; i++) { - auto& k = keys[i]; - if (k == key) { - auto& v = values[i]; -#if defined(CONNECTION_BOX_LOOKAHEAD_PUSH_BACK_HITS) - // preserve the found key by pushing it back - int last = (pos + N - 1) % N; - std::swap(k, keys[last]); - std::swap(v, values[last]); -#endif - *value = v; - hits++; - return true; - } - } - misses++; - return false; - } - - // O(1) insertion (overwriting an older entry) - void insert(K key, V val) { - keys[pos] = key; - values[pos] = val; - pos = (pos + 1) % N; - } - - // ratio of successful lookups - float hit_ratio() { - return hits ? static_cast(hits) / static_cast(hits + misses) : 0.f; - } - - // ratio of unsuccessful lookups - float miss_ratio() { - return misses ? static_cast(misses) / static_cast(hits + misses) : 0.f; - } - - private: - std::array keys; // keep keys together for faster scanning - std::array values; - size_t pos; - uint64_t hits; - uint64_t misses; -}; - -static float run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs, - SimpleCache* cache, - float max_cost); +static std::pair run_dijkstra(int start_node_ind, + RoutingCosts* routing_costs, + float max_cost); static void find_inodes_for_segment_types(std::vector* inodes_for_segment); // also known as the L1 norm @@ -503,8 +441,7 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, static void add_paths(int start_node_ind, int node_ind, std::unordered_map* paths, - RoutingCosts* routing_costs, - SimpleCache* cache) { + RoutingCosts* routing_costs) { auto& device_ctx = g_vpr_ctx.device(); ConnectionBoxId box_id; std::pair box_location; @@ -547,7 +484,6 @@ static void add_paths(int start_node_ind, seg_index, box_id, delta}; - CompressedRoutingCostKey compressed_key(key); RoutingCost val = { parent, node_ind, @@ -557,43 +493,22 @@ static void add_paths(int start_node_ind, // NOTE: implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - // use a cache for a small window around a delta of (0, 0) - float cost = 0.f; - bool in_window = abs(delta.x()) <= DIJKSTRA_CACHE_WINDOW && abs(delta.y()) <= DIJKSTRA_CACHE_WINDOW; - if (in_window && cache->get(compressed_key, &cost) && cost <= val.cost_entry.delay) { - // the sample was not cheaper than the cached sample - if (BREAK_ON_MISS) { - // don't store the rest of the path - break; - } - } else { - - auto result = routing_costs->insert(std::make_pair(key, val)); - if (!result.second) { - auto &existing = result.first->second; - if (existing.cost_entry.delay > val.cost_entry.delay) { - // this sample is cheaper - existing = val; - if (in_window) { - cache->insert(compressed_key, val.cost_entry.delay); - } - } else { - // this sample is not cheaper - if (BREAK_ON_MISS) { - // don't store the rest of the path - break; - } - if (in_window) { - cache->insert(compressed_key, existing.cost_entry.delay); - } - } + auto result = routing_costs->insert(std::make_pair(key, val)); + if (!result.second) { + auto &existing = result.first->second; + if (existing.cost_entry.delay > val.cost_entry.delay) { + // this sample is cheaper + existing = val; } else { - // this sample is new - (*routing_costs)[key] = val; - if (in_window) { - cache->insert(compressed_key, val.cost_entry.delay); + // this sample is not cheaper + if (BREAK_ON_MISS) { + // don't store the rest of the path + break; } } + } else { + // this sample is new + (*routing_costs)[key] = val; } // update parent data @@ -606,11 +521,11 @@ static void add_paths(int start_node_ind, /* runs Dijkstra's algorithm from specified node until all nodes have been * visited. Each time a pin is visited, the delay/congestion information * to that pin is stored to an entry in the routing_cost_map */ -static float run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs, - SimpleCache* cache, - float cost_limit) { +static std::pair run_dijkstra(int start_node_ind, + RoutingCosts* routing_costs, + float cost_limit) { auto& device_ctx = g_vpr_ctx.device(); + int path_count = 0; /* a list of boolean flags (one for each rr node) to figure out if a * certain node has already been expanded */ @@ -644,7 +559,8 @@ static float run_dijkstra(int start_node_ind, /* if this node is an ipin record its congestion/delay in the routing_cost_map */ if (device_ctx.rr_nodes[node_ind].type() == IPIN) { - add_paths(start_node_ind, node_ind, &paths, routing_costs, cache); + path_count++; + add_paths(start_node_ind, node_ind, &paths, routing_costs); } else { expand_dijkstra_neighbours(current, paths, node_expanded, pq); node_expanded[node_ind] = true; @@ -655,7 +571,17 @@ static float run_dijkstra(int start_node_ind, break; } } - return max_cost; + return std::make_pair(max_cost, path_count); +} + +static uint64_t interleave(uint32_t x) { + uint64_t i = x; + i = (i ^ (i << 16)) & 0x0000ffff0000ffff; + i = (i ^ (i << 8 )) & 0x00ff00ff00ff00ff; + i = (i ^ (i << 4 )) & 0x0f0f0f0f0f0f0f0f; + i = (i ^ (i << 2 )) & 0x3333333333333333; + i = (i ^ (i << 1 )) & 0x5555555555555555; + return i; } // compute the cost maps for lookahead @@ -674,7 +600,9 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { auto& point = grid.point[y][x]; if (!point.samples.empty()) { - point.order = point.samples[0]; + point.order = + interleave(point.location.x()) | + (interleave(point.location.y()) << 1); sample_points.push_back(point); } } @@ -708,21 +636,23 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen // holds the cost entries for a run RoutingCosts costs; - // a cache to avoid hammering the RoutingCosts map, since lookups will be dominated by a few keys - // must be consistent with `costs` i.e. any entry in the cache should also be in `costs` - // NOTE: this is used as a write-through cache, maybe try write-back - SimpleCache cache; - + vtr::Timer run_timer; + int path_count = 0; for (auto node_ind : point.samples) { - max_cost = std::max(max_cost, run_dijkstra(node_ind, &costs, &cache, COST_LIMIT)); + auto result = run_dijkstra(node_ind, &costs, COST_LIMIT); + max_cost = std::max(max_cost, result.first); + path_count += result.second; } #if defined(VPR_USE_TBB) all_costs_mutex.lock(); #endif - VTR_LOG("Expanded sample point (%d, %d) %e miss %g\n", - point.location.x(), point.location.y(), max_cost, cache.miss_ratio()); + VTR_LOG("Expanded %d paths starting at (%d, %d) max_cost %e (%g paths/sec)\n", + path_count, + point.location.x(), point.location.y(), + max_cost, + path_count / run_timer.elapsed_sec()); // combine the cost map from this run with the final cost maps for each segment for (const auto& cost : costs) { @@ -902,6 +832,7 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se for (int i = 0; i < num_segments; i++) { const auto& counts = segment_counts[i]; const auto& bounding_box = bounding_box_for_segment[i]; + if (bounding_box.empty()) continue; auto& grid = (*inodes_for_segment)[i]; for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 9b5bdb0afea..b04c8131800 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -32,29 +32,6 @@ struct RoutingCostKey { } }; -// compressed version of RoutingCostKey -// TODO add bounds checks -struct CompressedRoutingCostKey { - uint32_t data; - - CompressedRoutingCostKey() { - data = -1; - } - CompressedRoutingCostKey(const RoutingCostKey& key) { - data = key.seg_index & 0xff; - data <<= 8; - data |= size_t(key.box_id) & 0xff; - data <<= 8; - data |= key.delta.x() & 0xff; - data <<= 8; - data |= key.delta.y() & 0xff; - } - - bool operator==(CompressedRoutingCostKey other) const { - return data == other.data; - } -}; - // Data in the RoutingCosts map struct RoutingCost { // source and destination node indices @@ -67,15 +44,11 @@ struct RoutingCost { // hash implementation for RoutingCostKey struct HashRoutingCostKey { std::size_t operator()(RoutingCostKey const& key) const noexcept { - uint64_t data; - data = key.seg_index & 0xffff; - data <<= 16; - data |= size_t(key.box_id) & 0xffff; - data <<= 16; - data |= key.delta.x() & 0xffff; - data <<= 16; - data |= key.delta.y() & 0xffff; - return std::hash{}(data); + std::size_t hash = std::hash{}(key.seg_index); + vtr::hash_combine(hash, key.box_id); + vtr::hash_combine(hash, key.delta.x()); + vtr::hash_combine(hash, key.delta.y()); + return hash; } }; From 27e646f802d53d52f9ed10744b6d9331d0a40af5 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Fri, 8 Nov 2019 10:54:26 -0800 Subject: [PATCH 070/107] make format Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 23 ++++++++----------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index ca31e4dd424..8c18938fcf9 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -495,7 +495,7 @@ static void add_paths(int start_node_ind, auto result = routing_costs->insert(std::make_pair(key, val)); if (!result.second) { - auto &existing = result.first->second; + auto& existing = result.first->second; if (existing.cost_entry.delay > val.cost_entry.delay) { // this sample is cheaper existing = val; @@ -574,13 +574,13 @@ static std::pair run_dijkstra(int start_node_ind, return std::make_pair(max_cost, path_count); } -static uint64_t interleave(uint32_t x) { +static uint64_t interleave(uint32_t x) { uint64_t i = x; i = (i ^ (i << 16)) & 0x0000ffff0000ffff; - i = (i ^ (i << 8 )) & 0x00ff00ff00ff00ff; - i = (i ^ (i << 4 )) & 0x0f0f0f0f0f0f0f0f; - i = (i ^ (i << 2 )) & 0x3333333333333333; - i = (i ^ (i << 1 )) & 0x5555555555555555; + i = (i ^ (i << 8)) & 0x00ff00ff00ff00ff; + i = (i ^ (i << 4)) & 0x0f0f0f0f0f0f0f0f; + i = (i ^ (i << 2)) & 0x3333333333333333; + i = (i ^ (i << 1)) & 0x5555555555555555; return i; } @@ -600,9 +600,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { auto& point = grid.point[y][x]; if (!point.samples.empty()) { - point.order = - interleave(point.location.x()) | - (interleave(point.location.y()) << 1); + point.order = interleave(point.location.x()) | (interleave(point.location.y()) << 1); sample_points.push_back(point); } } @@ -730,7 +728,7 @@ float ConnectionBoxMapLookahead::get_expected_cost( } // the smallest bounding box containing a node -static vtr::Rect bounding_box_for_node(const ConnectionBoxes &connection_boxes, int node_ind) { +static vtr::Rect bounding_box_for_node(const ConnectionBoxes& connection_boxes, int node_ind) { const std::pair* loc = connection_boxes.find_canonical_loc(node_ind); if (loc == nullptr) { return vtr::Rect(); @@ -741,7 +739,7 @@ static vtr::Rect bounding_box_for_node(const ConnectionBoxes &connection_bo static vtr::Point choose_point(const vtr::Matrix& counts, const vtr::Rect& bounding_box, int sx, int sy, int n) { vtr::Rect window(sample(bounding_box, sx, sy, n), - sample(bounding_box, sx+1, sy+1, n)); + sample(bounding_box, sx + 1, sy + 1, n)); vtr::Point center = sample(window, 1, 1, 2); vtr::Point sample_point = center; int sample_distance = 0; @@ -752,8 +750,7 @@ static vtr::Point choose_point(const vtr::Matrix& counts, const vtr::R int count = counts[x][y]; if (count < sample_count) continue; int distance = manhattan_distance(center, here); - if (count > sample_count || - (count == sample_count && distance < sample_distance)) { + if (count > sample_count || (count == sample_count && distance < sample_distance)) { sample_point = here; sample_count = count; sample_distance = distance; From a4ca850e82ff07bc9729602bf0873e271e1b077a Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Fri, 8 Nov 2019 12:12:06 -0800 Subject: [PATCH 071/107] integrate lighost's patches Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box.cpp | 9 +++-- vpr/src/route/connection_box.h | 8 +++- .../route/connection_box_lookahead_map.cpp | 40 ++++++++++++++----- vpr/src/route/router_lookahead_map_utils.cpp | 17 +++----- vpr/src/route/router_lookahead_map_utils.h | 2 +- vpr/src/route/rr_graph_reader.cpp | 4 +- 6 files changed, 52 insertions(+), 28 deletions(-) diff --git a/vpr/src/route/connection_box.cpp b/vpr/src/route/connection_box.cpp index 85d554b4307..ab52817e48b 100644 --- a/vpr/src/route/connection_box.cpp +++ b/vpr/src/route/connection_box.cpp @@ -29,9 +29,11 @@ const ConnectionBox* ConnectionBoxes::get_connection_box(ConnectionBoxId box) co bool ConnectionBoxes::find_connection_box(int inode, ConnectionBoxId* box_id, - std::pair* box_location) const { + std::pair* box_location, + float* site_pin_delay) const { VTR_ASSERT(box_id != nullptr); VTR_ASSERT(box_location != nullptr); + VTR_ASSERT(site_pin_delay != nullptr); const auto& conn_box_loc = ipin_map_[inode]; if (conn_box_loc.box_id == ConnectionBoxId::INVALID()) { @@ -40,6 +42,7 @@ bool ConnectionBoxes::find_connection_box(int inode, *box_id = conn_box_loc.box_id; *box_location = conn_box_loc.box_location; + *site_pin_delay = conn_box_loc.site_pin_delay; return true; } @@ -66,7 +69,7 @@ void ConnectionBoxes::clear() { sink_to_ipin_.clear(); } -void ConnectionBoxes::add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location) { +void ConnectionBoxes::add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location, float site_pin_delay) { // Ensure that box location is in bounds VTR_ASSERT(box_location.first < size_.first); VTR_ASSERT(box_location.second < size_.second); @@ -78,7 +81,7 @@ void ConnectionBoxes::add_connection_box(int inode, ConnectionBoxId box_id, std: // Make sure sink map will not be invalidated upon insertion. VTR_ASSERT(sink_to_ipin_.size() == 0); - ipin_map_[inode] = ConnBoxLoc(box_location, box_id); + ipin_map_[inode] = ConnBoxLoc(box_location, site_pin_delay, box_id); } void ConnectionBoxes::add_canonical_loc(int inode, std::pair loc) { diff --git a/vpr/src/route/connection_box.h b/vpr/src/route/connection_box.h index 06217ac2a41..1757c6c726b 100644 --- a/vpr/src/route/connection_box.h +++ b/vpr/src/route/connection_box.h @@ -22,11 +22,14 @@ struct ConnBoxLoc { : box_location(std::make_pair(-1, -1)) {} ConnBoxLoc( const std::pair& a_box_location, + float a_site_pin_delay, ConnectionBoxId a_box_id) : box_location(a_box_location) + , site_pin_delay(a_site_pin_delay) , box_id(a_box_id) {} std::pair box_location; + float site_pin_delay; ConnectionBoxId box_id; }; @@ -45,7 +48,8 @@ class ConnectionBoxes { bool find_connection_box(int inode, ConnectionBoxId* box_id, - std::pair* box_location) const; + std::pair* box_location, + float* site_pin_delay) const; const std::pair* find_canonical_loc(int inode) const; // Clear IPIN map and set connection box grid size and box ids. @@ -54,7 +58,7 @@ class ConnectionBoxes { const std::vector boxes); void resize_nodes(size_t rr_node_size); - void add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location); + void add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location, float site_pin_delay); void add_canonical_loc(int inode, std::pair loc); // Create map from SINK's back to IPIN's diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 8c18938fcf9..208fd2eb51f 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -276,7 +276,7 @@ void CostMap::print(int iseg) const { VTR_LOG("cost EMPTY for box_id = %lu\n", box_id); continue; } - VTR_LOG("cost for box_id = %lu\n", box_id); + VTR_LOG("cost for box_id = %lu (%zu, %zu)\n", box_id, matrix.dim_size(0), matrix.dim_size(1)); double sum = 0.0; for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { @@ -398,8 +398,9 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, } ConnectionBoxId box_id; std::pair box_location; + float site_pin_delay; bool found = device_ctx.connection_boxes.find_connection_box( - to_node_ind, &box_id, &box_location); + to_node_ind, &box_id, &box_location, &site_pin_delay); if (!found) { VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", to_node_ind); } @@ -429,7 +430,16 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, float expected_delay = cost_entry.delay; float expected_congestion = cost_entry.congestion; + expected_delay += site_pin_delay; + expected_congestion += site_pin_delay; + float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; + + VTR_LOGV_DEBUG(f_router_debug, "Lookahead congestion: %g\n", expected_congestion); + VTR_LOGV_DEBUG(f_router_debug, "Criticality: %g\n", criticality_fac); + VTR_LOGV_DEBUG(f_router_debug, "Lookahead cost: %g\n", expected_cost); + VTR_LOGV_DEBUG(f_router_debug, "Site pin delay: %g\n", site_pin_delay); + if (!std::isfinite(expected_cost) || expected_cost < 0.f) { VTR_LOG_ERROR("invalid cost for segment %d to connection box %d at (%d, %d)\n", from_seg_index, (int)size_t(box_id), (int)dx, (int)dy); VTR_ASSERT(0); @@ -445,8 +455,9 @@ static void add_paths(int start_node_ind, auto& device_ctx = g_vpr_ctx.device(); ConnectionBoxId box_id; std::pair box_location; + float site_pin_delay; bool found = device_ctx.connection_boxes.find_connection_box( - node_ind, &box_id, &box_location); + node_ind, &box_id, &box_location, &site_pin_delay); if (!found) { VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); } @@ -455,15 +466,21 @@ static void add_paths(int start_node_ind, std::vector path; for (int i = node_ind; i != start_node_ind; path.push_back(i = (*paths)[i].parent)) ; - util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true); + util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true, /*Tsw_adjust=*/0.f); // recalculate the path with congestion util::PQ_Entry current_full = parent_entry; int parent = start_node_ind; for (auto it = path.rbegin(); it != path.rend(); it++) { auto& parent_node = device_ctx.rr_nodes[parent]; + float Tsw_adjust = 0.f; + + // Remove site pin delay when taking edge from last channel to IPIN. + if (*it == node_ind) { + Tsw_adjust = -site_pin_delay; + } current_full = util::PQ_Entry(*it, parent_node.edge_switch((*paths)[*it].edge), current_full.delay, - current_full.R_upstream, current_full.congestion_upstream, false); + current_full.R_upstream, current_full.congestion_upstream, false, Tsw_adjust); parent = *it; } @@ -484,12 +501,17 @@ static void add_paths(int start_node_ind, seg_index, box_id, delta}; + + float new_delay = current_full.delay - parent_entry.delay; + float new_congestion = current_full.congestion_upstream - parent_entry.congestion_upstream; + + VTR_ASSERT(new_delay >= 0.f); + VTR_ASSERT(new_congestion >= 0.f); + RoutingCost val = { parent, node_ind, - util::Cost_Entry( - current_full.delay - parent_entry.delay, - current_full.congestion_upstream - parent_entry.congestion_upstream)}; + util::Cost_Entry(new_delay, new_congestion)}; // NOTE: implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST @@ -513,7 +535,7 @@ static void add_paths(int start_node_ind, // update parent data parent_entry = util::PQ_Entry(*it, parent_node.edge_switch((*paths)[*it].edge), parent_entry.delay, - parent_entry.R_upstream, parent_entry.congestion_upstream, false); + parent_entry.R_upstream, parent_entry.congestion_upstream, false, /*Tsw_adjust=*/0.f); parent = *it; } } diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index e4ea0902d28..e879fbaec60 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -15,7 +15,8 @@ PQ_Entry::PQ_Entry( float parent_delay, float parent_R_upstream, float parent_congestion_upstream, - bool starting_node) { + bool starting_node, + float Tsw_adjust) { this->rr_node_ind = set_rr_node_ind; auto& device_ctx = g_vpr_ctx.device(); @@ -26,6 +27,8 @@ PQ_Entry::PQ_Entry( int cost_index = device_ctx.rr_nodes[set_rr_node_ind].cost_index(); float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; + Tsw += Tsw_adjust; + VTR_ASSERT(Tsw >= 0.f); float Rsw = device_ctx.rr_switch_inf[switch_ind].R; float Cnode = device_ctx.rr_nodes[set_rr_node_ind].C(); float Rnode = device_ctx.rr_nodes[set_rr_node_ind].R(); @@ -34,21 +37,11 @@ PQ_Entry::PQ_Entry( float T_quadratic = 0.f; if (device_ctx.rr_switch_inf[switch_ind].buffered()) { T_linear = Tsw + Rsw * Cnode + 0.5 * Rnode * Cnode; - T_quadratic = 0.; } else { /* Pass transistor */ T_linear = Tsw + 0.5 * Rsw * Cnode; - T_quadratic = (Rsw + Rnode) * 0.5 * Cnode; } - float base_cost; - if (device_ctx.rr_indexed_data[cost_index].inv_length < 0) { - base_cost = device_ctx.rr_indexed_data[cost_index].base_cost; - } else { - float frac_num_seg = CLB_DIST * device_ctx.rr_indexed_data[cost_index].inv_length; - - base_cost = frac_num_seg * T_linear - + frac_num_seg * frac_num_seg * T_quadratic; - } + float base_cost = device_ctx.rr_indexed_data[cost_index].base_cost; VTR_ASSERT(T_linear >= 0.); VTR_ASSERT(base_cost >= 0.); diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index a9fa6fbfc67..e16491c1809 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -128,7 +128,7 @@ class PQ_Entry { float R_upstream; float congestion_upstream; - PQ_Entry(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, float parent_R_upstream, float parent_congestion_upstream, bool starting_node); + PQ_Entry(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, float parent_R_upstream, float parent_congestion_upstream, bool starting_node, float Tsw_adjust); bool operator<(const PQ_Entry& obj) const { /* inserted into max priority queue so want queue entries with a lower cost to be greater */ diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index c2544dc4720..bdbd8fb9d45 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -320,10 +320,12 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); int id = get_attribute(connection_boxSubnode, "id", loc_data).as_int(); + float site_pin_delay = get_attribute(connection_boxSubnode, "site_pin_delay", loc_data).as_float(); device_ctx.connection_boxes.add_connection_box(inode, ConnectionBoxId(id), - std::make_pair(x, y)); + std::make_pair(x, y), + site_pin_delay); } } else { From 010579b2d589952e3488e81986be59b700622447 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Mon, 11 Nov 2019 11:22:23 -0800 Subject: [PATCH 072/107] independently minimize delay and base cost (congestion) --- vpr/src/route/connection_box_lookahead_map.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 208fd2eb51f..918a8fce439 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -322,6 +322,8 @@ std::vector> CostMap::list_empty() const { static void assign_min_entry(util::Cost_Entry* dst, const util::Cost_Entry& src) { if (src.delay < dst->delay) { dst->delay = src.delay; + } + if (src.congestion < dst->congestion) { dst->congestion = src.congestion; } } From 9959bde7b2d92b120c3fdc1d9e84f4daef61006a Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 14 Nov 2019 15:13:48 -0800 Subject: [PATCH 073/107] Expand delay and base cost independently Expand base_cost too. The delay and base cost matricies are independent, so should be expanded and filled independently. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> Signed-off-by: Dusty DeWeese --- .../route/connection_box_lookahead_map.cpp | 233 +++++++++--------- vpr/src/route/connection_box_lookahead_map.h | 4 +- vpr/src/route/router_lookahead_map_utils.cpp | 92 ++++--- vpr/src/route/router_lookahead_map_utils.h | 55 ++++- 4 files changed, 227 insertions(+), 157 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 918a8fce439..4440ea6f1a5 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -37,16 +37,12 @@ * * See e_representative_entry_method */ #define REPRESENTATIVE_ENTRY_METHOD SMALLEST -// #define FILL_LIMIT 30 #define CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_MAPS // Sample based an NxN grid of starting segments, where N = SAMPLE_GRID_SIZE static constexpr int SAMPLE_GRID_SIZE = 3; -// Stop Dijkstra expansion after reaching COST_LIMIT -static constexpr float COST_LIMIT = std::numeric_limits::infinity(); - // Don't continue storing a path after hitting a lower-or-same cost entry. static constexpr bool BREAK_ON_MISS = true; @@ -67,9 +63,10 @@ struct SampleGrid { SamplePoint point[SAMPLE_GRID_SIZE][SAMPLE_GRID_SIZE]; }; +template static std::pair run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs, - float max_cost); + RoutingCosts* routing_costs); + static void find_inodes_for_segment_types(std::vector* inodes_for_segment); // also known as the L1 norm @@ -144,11 +141,14 @@ util::Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, } // set the cost map for a segment type and connection box type, filling holes -void CostMap::set_cost_map(const RoutingCosts& costs) { +void CostMap::set_cost_map(const RoutingCosts& delay_costs, const RoutingCosts& base_costs) { // calculate the bounding boxes vtr::Matrix> bounds({seg_count_, box_count_}); - for (const auto& entry : costs) { - bounds[entry.first.seg_index][size_t(entry.first.box_id)] |= vtr::Rect(entry.first.delta, 1); + for (const auto& entry : delay_costs) { + bounds[entry.first.seg_index][size_t(entry.first.box_id)].expand_bounding_box(vtr::Rect(entry.first.delta)); + } + for (const auto& entry : base_costs) { + bounds[entry.first.seg_index][size_t(entry.first.box_id)].expand_bounding_box(vtr::Rect(entry.first.delta)); } // store bounds @@ -170,13 +170,21 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { } // store entries into the matrices - for (const auto& entry : costs) { + for (const auto& entry : delay_costs) { int seg = entry.first.seg_index; int box = size_t(entry.first.box_id); const auto& seg_box_bounds = bounds[seg][box]; int x = entry.first.delta.x() - seg_box_bounds.xmin(); int y = entry.first.delta.y() - seg_box_bounds.ymin(); - cost_map_[seg][box][x][y] = entry.second.cost_entry; + cost_map_[seg][box][x][y].delay = entry.second; + } + for (const auto& entry : base_costs) { + int seg = entry.first.seg_index; + int box = size_t(entry.first.box_id); + const auto& seg_box_bounds = bounds[seg][box]; + int x = entry.first.delta.x() - seg_box_bounds.xmin(); + int y = entry.first.delta.y() - seg_box_bounds.ymin(); + cost_map_[seg][box][x][y].congestion = entry.second; } // fill the holes @@ -231,11 +239,10 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { } } } -#if !defined(FILL_LIMIT) if (couldnt_fill) { + // give up trying to fill an empty matrix break; } -#endif } if (!couldnt_fill) { @@ -250,13 +257,11 @@ void CostMap::set_cost_map(const RoutingCosts& costs) { if (couldnt_fill) { VTR_LOG_WARN("Couldn't fill holes in the cost matrix for %d -> %ld, %d x %d bounding box\n", seg, box, seg_box_bounds.width(), seg_box_bounds.height()); -#if !defined(FILL_LIMIT) for (unsigned y = 0; y < matrix.dim_size(1); y++) { for (unsigned x = 0; x < matrix.dim_size(0); x++) { VTR_ASSERT(!matrix[x][y].valid()); } } -#endif } } } @@ -334,35 +339,39 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMat int cy, const vtr::Rect& bounds) { // spiral around (cx, cy) looking for a nearby entry - int n = 1; - bool in_bounds; - util::Cost_Entry entry; + bool in_bounds = bounds.contains(vtr::Point(cx, cy)); + if(!in_bounds) { + return std::make_pair(util::Cost_Entry(), 0); + } + int n = 0; + util::Cost_Entry fill(matrix[cx][cy]); - do { + while(in_bounds && !fill.valid()) { + n++; in_bounds = false; + util::Cost_Entry min_entry; for (int ox = -n; ox <= n; ox++) { int x = cx + ox; int oy = n - abs(ox); int yp = cy + oy; int yn = cy - oy; if (bounds.contains(vtr::Point(x, yp))) { - assign_min_entry(&entry, matrix[x][yp]); + assign_min_entry(&min_entry, matrix[x][yp]); in_bounds = true; } if (bounds.contains(vtr::Point(x, yn))) { - assign_min_entry(&entry, matrix[x][yn]); + assign_min_entry(&min_entry, matrix[x][yn]); in_bounds = true; } + if (!std::isfinite(fill.delay)) { + fill.delay = min_entry.delay; + } + if (!std::isfinite(fill.congestion)) { + fill.congestion = min_entry.congestion; + } } - if (entry.valid()) return std::make_pair(entry, n); - n++; -#if defined(FILL_LIMIT) - if (n > FILL_LIMIT) { - break; - } -#endif - } while (in_bounds); - return std::make_pair(util::Cost_Entry(), n); + } + return std::make_pair(fill, n); } // derive a cost from the map between two nodes @@ -375,8 +384,6 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, auto& device_ctx = g_vpr_ctx.device(); - std::pair from_location; - std::pair to_location; auto to_node_type = device_ctx.rr_nodes[to_node_ind].type(); if (to_node_type == SINK) { @@ -446,18 +453,21 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, VTR_LOG_ERROR("invalid cost for segment %d to connection box %d at (%d, %d)\n", from_seg_index, (int)size_t(box_id), (int)dx, (int)dy); VTR_ASSERT(0); } + return expected_cost; } // add a best cost routing path from start_node_ind to node_ind to routing costs +template static void add_paths(int start_node_ind, - int node_ind, + Entry current, std::unordered_map* paths, RoutingCosts* routing_costs) { auto& device_ctx = g_vpr_ctx.device(); ConnectionBoxId box_id; std::pair box_location; float site_pin_delay; + int node_ind = current.rr_node_ind; bool found = device_ctx.connection_boxes.find_connection_box( node_ind, &box_id, &box_location, &site_pin_delay); if (!found) { @@ -466,32 +476,20 @@ static void add_paths(int start_node_ind, // reconstruct the path std::vector path; - for (int i = node_ind; i != start_node_ind; path.push_back(i = (*paths)[i].parent)) - ; - util::PQ_Entry parent_entry(start_node_ind, UNDEFINED, 0, 0, 0, true, /*Tsw_adjust=*/0.f); - - // recalculate the path with congestion - util::PQ_Entry current_full = parent_entry; - int parent = start_node_ind; - for (auto it = path.rbegin(); it != path.rend(); it++) { - auto& parent_node = device_ctx.rr_nodes[parent]; - float Tsw_adjust = 0.f; - - // Remove site pin delay when taking edge from last channel to IPIN. - if (*it == node_ind) { - Tsw_adjust = -site_pin_delay; - } - current_full = util::PQ_Entry(*it, parent_node.edge_switch((*paths)[*it].edge), current_full.delay, - current_full.R_upstream, current_full.congestion_upstream, false, Tsw_adjust); - parent = *it; + for (int i = (*paths)[node_ind].parent; i != start_node_ind; i = (*paths)[i].parent) { + path.push_back(i); } + path.push_back(start_node_ind); + + current.adjust_Tsw(-site_pin_delay); // add each node along the path subtracting the incremental costs from the current costs - parent = start_node_ind; + Entry start_to_here(start_node_ind, UNDEFINED, nullptr); + int parent = start_node_ind; for (auto it = path.rbegin(); it != path.rend(); it++) { - auto& parent_node = device_ctx.rr_nodes[parent]; - int seg_index = device_ctx.rr_indexed_data[parent_node.cost_index()].seg_index; - const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(parent); + auto& here = device_ctx.rr_nodes[*it]; + int seg_index = device_ctx.rr_indexed_data[here.cost_index()].seg_index; + const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(*it); if (from_canonical_loc == nullptr) { VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", parent); @@ -504,50 +502,37 @@ static void add_paths(int start_node_ind, box_id, delta}; - float new_delay = current_full.delay - parent_entry.delay; - float new_congestion = current_full.congestion_upstream - parent_entry.congestion_upstream; + if(*it != start_node_ind) { + auto& parent_node = device_ctx.rr_nodes[parent]; + start_to_here = Entry(*it, parent_node.edge_switch((*paths)[*it].edge), &start_to_here); + parent = *it; + } - VTR_ASSERT(new_delay >= 0.f); - VTR_ASSERT(new_congestion >= 0.f); + float cost = current.cost() - start_to_here.cost(); + if(cost < 0.f && cost > -1e-15 /* 1 femtosecond */) { + cost = 0.f; + } - RoutingCost val = { - parent, - node_ind, - util::Cost_Entry(new_delay, new_congestion)}; + VTR_ASSERT(cost >= 0.f); // NOTE: implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - - auto result = routing_costs->insert(std::make_pair(key, val)); + auto result = routing_costs->insert(std::make_pair(key, cost)); if (!result.second) { - auto& existing = result.first->second; - if (existing.cost_entry.delay > val.cost_entry.delay) { - // this sample is cheaper - existing = val; - } else { - // this sample is not cheaper - if (BREAK_ON_MISS) { - // don't store the rest of the path - break; - } + if (cost < result.first->second) { + result.first->second = cost; + } else if (BREAK_ON_MISS) { + break; } - } else { - // this sample is new - (*routing_costs)[key] = val; } - - // update parent data - parent_entry = util::PQ_Entry(*it, parent_node.edge_switch((*paths)[*it].edge), parent_entry.delay, - parent_entry.R_upstream, parent_entry.congestion_upstream, false, /*Tsw_adjust=*/0.f); - parent = *it; } } /* runs Dijkstra's algorithm from specified node until all nodes have been * visited. Each time a pin is visited, the delay/congestion information * to that pin is stored to an entry in the routing_cost_map */ +template static std::pair run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs, - float cost_limit) { + RoutingCosts* routing_costs) { auto& device_ctx = g_vpr_ctx.device(); int path_count = 0; @@ -560,12 +545,11 @@ static std::pair run_dijkstra(int start_node_ind, * Also store the parent node so we can reconstruct a specific path. */ std::unordered_map paths; /* a priority queue for expansion */ - std::priority_queue, std::greater> pq; + std::priority_queue, std::greater> pq; /* first entry has no upstream delay or congestion */ - util::PQ_Entry_Lite first_entry(start_node_ind, UNDEFINED, 0, true); - - float max_cost = 0.f; + Entry first_entry(start_node_ind, UNDEFINED, nullptr); + float max_cost = first_entry.cost(); pq.push(first_entry); @@ -576,6 +560,9 @@ static std::pair run_dijkstra(int start_node_ind, int node_ind = current.rr_node_ind; + // the last cost should be the highest + max_cost = current.cost(); + /* check that we haven't already expanded from this node */ if (node_expanded[node_ind]) { continue; @@ -584,16 +571,12 @@ static std::pair run_dijkstra(int start_node_ind, /* if this node is an ipin record its congestion/delay in the routing_cost_map */ if (device_ctx.rr_nodes[node_ind].type() == IPIN) { path_count++; - add_paths(start_node_ind, node_ind, &paths, routing_costs); + add_paths(start_node_ind, current, &paths, routing_costs); } else { - expand_dijkstra_neighbours(current, paths, node_expanded, pq); + util::expand_dijkstra_neighbours(device_ctx.rr_nodes, + current, paths, node_expanded, pq); node_expanded[node_ind] = true; } - - max_cost = std::max(max_cost, current.delay_cost); - if (max_cost > cost_limit) { - break; - } } return std::make_pair(max_cost, path_count); } @@ -644,7 +627,8 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen device_ctx.connection_boxes.num_connection_box_types()); VTR_ASSERT(REPRESENTATIVE_ENTRY_METHOD == SMALLEST); - RoutingCosts all_costs; + RoutingCosts all_delay_costs; + RoutingCosts all_base_costs; /* run Dijkstra's algorithm for each segment type & channel type combination */ #if defined(VPR_USE_TBB) @@ -653,39 +637,58 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen #else for (const auto& point : sample_points) { #endif - float max_cost = 0.f; - // holds the cost entries for a run - RoutingCosts costs; + RoutingCosts delay_costs; + RoutingCosts base_costs; + // statistics vtr::Timer run_timer; int path_count = 0; + float max_delay_cost = 0.f; + float max_base_cost = 0.f; + for (auto node_ind : point.samples) { - auto result = run_dijkstra(node_ind, &costs, COST_LIMIT); - max_cost = std::max(max_cost, result.first); - path_count += result.second; + { + auto result = run_dijkstra(node_ind, &delay_costs); + max_delay_cost = std::max(max_delay_cost, result.first); + path_count += result.second; + } + { + auto result = run_dijkstra(node_ind, &base_costs); + max_base_cost = std::max(max_base_cost, result.first); + path_count += result.second; + } } #if defined(VPR_USE_TBB) all_costs_mutex.lock(); #endif - - VTR_LOG("Expanded %d paths starting at (%d, %d) max_cost %e (%g paths/sec)\n", +/* + for (auto node_ind : point.samples) { + VTR_LOG("Expanded node %s\n", describe_rr_node(node_ind).c_str()); + } +*/ + VTR_LOG("Expanded %d paths starting at (%d, %d) max_cost %e %e (%g paths/sec)\n", path_count, point.location.x(), point.location.y(), - max_cost, + max_delay_cost, max_base_cost, path_count / run_timer.elapsed_sec()); // combine the cost map from this run with the final cost maps for each segment - for (const auto& cost : costs) { - const auto& key = cost.first; + for (const auto& cost : delay_costs) { const auto& val = cost.second; - const auto& result = all_costs.insert(std::make_pair(key, val)); - auto& existing = result.first->second; - - // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - if (!result.second || existing.cost_entry.delay > val.cost_entry.delay) { - existing = val; + auto result = all_delay_costs.insert(std::make_pair(cost.first, val)); + if (!result.second) { + // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST + result.first->second = std::min(result.first->second, val); + } + } + for (const auto& cost : base_costs) { + const auto& val = cost.second; + auto result = all_base_costs.insert(std::make_pair(cost.first, val)); + if (!result.second) { + // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST + result.first->second = std::min(result.first->second, val); } } @@ -699,7 +702,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen VTR_LOG("Combining results\n"); /* boil down the cost list in routing_cost_map at each coordinate to a * representative cost entry and store it in the lookahead cost map */ - cost_map_.set_cost_map(all_costs); + cost_map_.set_cost_map(all_delay_costs, all_base_costs); // diagnostics #if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_ENTRIES) diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index b04c8131800..810dec59135 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -53,7 +53,7 @@ struct HashRoutingCostKey { }; // Map used to store intermediate routing costs -typedef std::unordered_map RoutingCosts; +typedef std::unordered_map RoutingCosts; // Dense cost maps per source segment and destination connection box types class CostMap { @@ -61,7 +61,7 @@ class CostMap { void set_counts(size_t seg_count, size_t box_count); int node_to_segment(int from_node_ind) const; util::Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; - void set_cost_map(const RoutingCosts& costs); + void set_cost_map(const RoutingCosts& delay_costs, const RoutingCosts& base_costs); std::pair get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); void read(const std::string& file); void write(const std::string& file) const; diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index e879fbaec60..20ac7108a3a 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -34,7 +34,6 @@ PQ_Entry::PQ_Entry( float Rnode = device_ctx.rr_nodes[set_rr_node_ind].R(); float T_linear = 0.f; - float T_quadratic = 0.f; if (device_ctx.rr_switch_inf[switch_ind].buffered()) { T_linear = Tsw + Rsw * Cnode + 0.5 * Rnode * Cnode; } else { /* Pass transistor */ @@ -54,16 +53,15 @@ PQ_Entry::PQ_Entry( this->cost = this->delay; } -PQ_Entry_Lite::PQ_Entry_Lite( +util::PQ_Entry_Delay::PQ_Entry_Delay( int set_rr_node_ind, int switch_ind, - float parent_delay, - bool starting_node) { + const util::PQ_Entry_Delay* parent) { + this->rr_node_ind = set_rr_node_ind; - auto& device_ctx = g_vpr_ctx.device(); - this->delay_cost = parent_delay; - if (!starting_node) { + if (parent != nullptr) { + auto& device_ctx = g_vpr_ctx.device(); float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; float Rsw = device_ctx.rr_switch_inf[switch_ind].R; float Cnode = device_ctx.rr_nodes[set_rr_node_ind].C(); @@ -77,7 +75,25 @@ PQ_Entry_Lite::PQ_Entry_Lite( } VTR_ASSERT(T_linear >= 0.); - this->delay_cost += T_linear; + this->delay_cost = parent->delay_cost + T_linear; + } else { + this->delay_cost = 0.f; + } +} + +util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( + int set_rr_node_ind, + int switch_ind, + const util::PQ_Entry_Base_Cost* parent) { + + this->rr_node_ind = set_rr_node_ind; + + if (parent != nullptr) { + auto& device_ctx = g_vpr_ctx.device(); + int cost_index = device_ctx.rr_nodes[set_rr_node_ind].cost_index(); + this->base_cost = parent->base_cost + device_ctx.rr_indexed_data[cost_index].base_cost; + } else { + this->base_cost = 0.f; } } @@ -177,20 +193,17 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { return representative_entry; } -} // namespace util - -/* iterates over the children of the specified node and selectively pushes them onto the priority queue */ -void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, +template +void expand_dijkstra_neighbours(const std::vector& rr_nodes, + const Entry& parent_entry, std::unordered_map& paths, std::vector& node_expanded, - std::priority_queue, - std::greater>& pq) { - auto& device_ctx = g_vpr_ctx.device(); - + std::priority_queue, + std::greater>& pq) { int parent_ind = parent_entry.rr_node_ind; - auto& parent_node = device_ctx.rr_nodes[parent_ind]; + auto& parent_node = rr_nodes[parent_ind]; for (int iedge = 0; iedge < parent_node.num_edges(); iedge++) { int child_node_ind = parent_node.edge_sink_node(iedge); @@ -201,18 +214,39 @@ void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, continue; } - util::PQ_Entry_Lite child_entry(child_node_ind, switch_ind, parent_entry.delay_cost, false); - - VTR_ASSERT(child_entry.delay_cost >= 0); + Entry child_entry(child_node_ind, switch_ind, &parent_entry); + VTR_ASSERT(child_entry.cost() >= 0); + pq.push(child_entry); - /* skip this child if it has been visited with smaller or the same cost */ - auto stored_cost = paths.find(child_node_ind); - if (stored_cost != paths.end() && stored_cost->second.cost <= child_entry.delay_cost) { - continue; + /* Create (if it doesn't exist) or update (if the new cost is lower) + * to specified node */ + Search_Path path_entry = {child_entry.cost(), parent_ind, iedge}; + auto result = paths.insert(std::make_pair( + child_node_ind, + path_entry)); + if (!result.second) { + if (child_entry.cost() < result.first->second.cost) { + result.first->second = path_entry; + } } - - /* finally, record the cost with which the child was visited and put the child entry on the queue */ - paths[child_node_ind] = {child_entry.delay_cost, parent_ind, iedge}; - pq.push(child_entry); } } + +template +void expand_dijkstra_neighbours(const std::vector& rr_nodes, + const PQ_Entry_Delay& parent_entry, + std::unordered_map& paths, + std::vector& node_expanded, + std::priority_queue, + std::greater>& pq); +template +void expand_dijkstra_neighbours(const std::vector& rr_nodes, + const PQ_Entry_Base_Cost& parent_entry, + std::unordered_map& paths, + std::vector& node_expanded, + std::priority_queue, + std::greater>& pq); + +} // namespace util diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index e16491c1809..02b2f71c449 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -21,6 +21,7 @@ #include #include #include "vpr_types.h" +#include "rr_node.h" /* when a list of delay/congestion entries at a coordinate in Cost_Entry is boiled down to a single * representative entry, this enum is passed-in to specify how that representative entry should be @@ -136,32 +137,64 @@ class PQ_Entry { } }; -// A version of PQ_Entry that only calculates and stores the delay (cost.) -class PQ_Entry_Lite { +// A version of PQ_Entry that only calculates and stores the delay. +class PQ_Entry_Delay { public: int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents float delay_cost; //the cost of the path to get to this node - PQ_Entry_Lite(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, bool starting_node); + PQ_Entry_Delay(int set_rr_node_ind, int /*switch_ind*/, const PQ_Entry_Delay* parent); - bool operator>(const PQ_Entry_Lite& obj) const { + float cost() const { + return delay_cost; + } + + void adjust_Tsw(float amount) { + delay_cost += amount; + } + + bool operator>(const PQ_Entry_Delay& obj) const { return (this->delay_cost > obj.delay_cost); } }; +// A version of PQ_Entry that only calculates and stores the base cost. +class PQ_Entry_Base_Cost { + public: + int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents + float base_cost; + + PQ_Entry_Base_Cost(int set_rr_node_ind, int /*switch_ind*/, const PQ_Entry_Base_Cost* parent); + + float cost() const { + return base_cost; + } + + void adjust_Tsw(float amount) { + // do nothing + } + + bool operator>(const PQ_Entry_Base_Cost& obj) const { + return (this->base_cost > obj.base_cost); + } +}; + struct Search_Path { float cost; int parent; int edge; }; -} // namespace util - -void expand_dijkstra_neighbours(util::PQ_Entry_Lite parent_entry, - std::unordered_map& paths, +/* iterates over the children of the specified node and selectively pushes them onto the priority queue */ +template +void expand_dijkstra_neighbours(const std::vector& rr_nodes, + const Entry& parent_entry, + std::unordered_map& paths, std::vector& node_expanded, - std::priority_queue, - std::greater>& pq); + std::priority_queue, + std::greater>& pq); + +} // namespace util #endif From a5742dc00117b0138a0cb7f5ed9933d7bcbf2683 Mon Sep 17 00:00:00 2001 From: Dusty DeWeese Date: Thu, 14 Nov 2019 15:16:26 -0800 Subject: [PATCH 074/107] site_pin_delay shouldn't affect congestion Signed-off-by: Dusty DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 4440ea6f1a5..1b09f8e7b9d 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -440,7 +440,6 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, float expected_congestion = cost_entry.congestion; expected_delay += site_pin_delay; - expected_congestion += site_pin_delay; float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; From f71b5365f6ed4751f266a5ad5d65078e0ffb62bb Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Mon, 18 Nov 2019 18:29:55 -0800 Subject: [PATCH 075/107] use histogram to choose sample sizes, set minimum penalty Signed-off-by: Dustin DeWeese --- .../route/connection_box_lookahead_map.cpp | 139 +++++++++++++----- vpr/src/route/router_lookahead_map_utils.cpp | 1 - vpr/src/route/router_lookahead_map_utils.h | 2 +- 3 files changed, 101 insertions(+), 41 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 1b09f8e7b9d..bcc331fc46f 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -44,16 +44,18 @@ static constexpr int SAMPLE_GRID_SIZE = 3; // Don't continue storing a path after hitting a lower-or-same cost entry. -static constexpr bool BREAK_ON_MISS = true; +static constexpr bool BREAK_ON_MISS = false; // Distance penalties filling are calculated based on available samples, but can be adjusted with this factor. static constexpr float PENALTY_FACTOR = 1.f; +static constexpr float PENALTY_MIN = 1e-12f; // a sample point for a segment type, contains all segments at the VPR location struct SamplePoint { uint64_t order; // used to order sample points vtr::Point location; std::vector samples; + int segment_type; SamplePoint() : location(0, 0) {} }; @@ -118,6 +120,7 @@ int CostMap::node_to_segment(int from_node_ind) const { } static util::Cost_Entry penalize(const util::Cost_Entry& entry, int distance, float penalty) { + penalty = std::max(penalty, PENALTY_MIN); return util::Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, entry.congestion); } @@ -363,12 +366,12 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMat assign_min_entry(&min_entry, matrix[x][yn]); in_bounds = true; } - if (!std::isfinite(fill.delay)) { - fill.delay = min_entry.delay; - } - if (!std::isfinite(fill.congestion)) { - fill.congestion = min_entry.congestion; - } + } + if (!std::isfinite(fill.delay)) { + fill.delay = min_entry.delay; + } + if (!std::isfinite(fill.congestion)) { + fill.congestion = min_entry.congestion; } } return std::make_pair(fill, n); @@ -458,7 +461,7 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, // add a best cost routing path from start_node_ind to node_ind to routing costs template -static void add_paths(int start_node_ind, +static bool add_paths(int start_node_ind, Entry current, std::unordered_map* paths, RoutingCosts* routing_costs) { @@ -469,6 +472,7 @@ static void add_paths(int start_node_ind, int node_ind = current.rr_node_ind; bool found = device_ctx.connection_boxes.find_connection_box( node_ind, &box_id, &box_location, &site_pin_delay); + bool new_sample_found = false; if (!found) { VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); } @@ -490,8 +494,7 @@ static void add_paths(int start_node_ind, int seg_index = device_ctx.rr_indexed_data[here.cost_index()].seg_index; const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(*it); if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", - parent); + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", *it); } vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), @@ -508,7 +511,7 @@ static void add_paths(int start_node_ind, } float cost = current.cost() - start_to_here.cost(); - if(cost < 0.f && cost > -1e-15 /* 1 femtosecond */) { + if(cost < 0.f && cost > -10e-15 /* 10 femtosecond */) { cost = 0.f; } @@ -518,12 +521,16 @@ static void add_paths(int start_node_ind, auto result = routing_costs->insert(std::make_pair(key, cost)); if (!result.second) { if (cost < result.first->second) { - result.first->second = cost; + result.first->second = cost; + new_sample_found = true; } else if (BREAK_ON_MISS) { break; } + } else { + new_sample_found = true; } } + return new_sample_found; } /* runs Dijkstra's algorithm from specified node until all nodes have been @@ -534,6 +541,11 @@ static std::pair run_dijkstra(int start_node_ind, RoutingCosts* routing_costs) { auto& device_ctx = g_vpr_ctx.device(); int path_count = 0; + const std::pair* start_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(start_node_ind); + if (start_canonical_loc == nullptr) { + VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", + start_node_ind); + } /* a list of boolean flags (one for each rr node) to figure out if a * certain node has already been expanded */ @@ -645,7 +657,6 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen int path_count = 0; float max_delay_cost = 0.f; float max_base_cost = 0.f; - for (auto node_ind : point.samples) { { auto result = run_dijkstra(node_ind, &delay_costs); @@ -662,14 +673,10 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen #if defined(VPR_USE_TBB) all_costs_mutex.lock(); #endif -/* - for (auto node_ind : point.samples) { - VTR_LOG("Expanded node %s\n", describe_rr_node(node_ind).c_str()); - } -*/ - VTR_LOG("Expanded %d paths starting at (%d, %d) max_cost %e %e (%g paths/sec)\n", - path_count, + VTR_LOG("Expanded %d paths of segment type %s(%d) starting at (%d, %d) from %d segments, max_cost %e %e (%g paths/sec)\n", + path_count, segment_inf[point.segment_type].name.c_str(), point.segment_type, point.location.x(), point.location.y(), + (int)point.samples.size(), max_delay_cost, max_base_cost, path_count / run_timer.elapsed_sec()); @@ -763,25 +770,29 @@ static vtr::Rect bounding_box_for_node(const ConnectionBoxes& connection_bo } } -static vtr::Point choose_point(const vtr::Matrix& counts, const vtr::Rect& bounding_box, int sx, int sy, int n) { - vtr::Rect window(sample(bounding_box, sx, sy, n), +static vtr::Rect sample_window(const vtr::Rect& bounding_box, int sx, int sy, int n) { + return vtr::Rect(sample(bounding_box, sx, sy, n), sample(bounding_box, sx + 1, sy + 1, n)); +} + +static vtr::Point choose_point(const vtr::Matrix& counts, const vtr::Rect& window, int with_count) { vtr::Point center = sample(window, 1, 1, 2); vtr::Point sample_point = center; - int sample_distance = 0; - int sample_count = counts[sample_point.x()][sample_point.y()]; - for (int y = window.ymin(); y < window.ymax(); y++) { - for (int x = window.xmin(); x < window.xmax(); x++) { - vtr::Point here(x, y); - int count = counts[x][y]; - if (count < sample_count) continue; - int distance = manhattan_distance(center, here); - if (count > sample_count || (count == sample_count && distance < sample_distance)) { - sample_point = here; - sample_count = count; - sample_distance = distance; + if (with_count > 0) { + int sample_distance = std::numeric_limits::max(); + for (int y = window.ymin(); y < window.ymax(); y++) { + for (int x = window.xmin(); x < window.xmax(); x++) { + vtr::Point here(x, y); + if (counts[x][y] == with_count) { + int distance = manhattan_distance(center, here); + if (distance < sample_distance) { + sample_point = here; + sample_distance = distance; + } + } } } + VTR_ASSERT(counts[sample_point.x()][sample_point.y()] > 0); } return sample_point; } @@ -798,6 +809,51 @@ static std::pair grid_lookup(const SampleGrid& grid, vtr::Point p return std::make_pair(-1, -1); } +// histogram is a map from segment count to number of locations having that count +static int max_count_within_quantiles(const std::map& histogram, float lower, float upper) { + if (histogram.empty()) { + return 0; + } + int sum = 0; + for (const auto& entry : histogram) { + sum += entry.second; + } + int lower_limit = std::ceil(sum * lower); + int upper_limit = std::ceil(sum * upper); + std::pair max(0, 0); + for (const auto& entry : histogram) { + upper_limit -= entry.second; + if (lower_limit > 0) { + lower_limit -= entry.second; + if(lower_limit <= 0) { + max = entry; + } + } else { + if (entry.second >= max.second) { + max = entry; + } + if (upper_limit <= 0) { + break; + } + } + } + return max.first; +} + +// select a good number of segments to find +static int select_size(const vtr::Rect& box, const vtr::Matrix& counts) { + std::map histogram; + for (int y = box.ymin(); y < box.ymax(); y++) { + for (int x = box.xmin(); x < box.xmax(); x++) { + int count = counts[x][y]; + if (count > 0) { + histogram[count]++; + } + } + } + return max_count_within_quantiles(histogram, 0.75, 0.9); +} + // for each segment type, find the nearest nodes to an equally spaced grid of points // within the bounding box for that segment type static void find_inodes_for_segment_types(std::vector* inodes_for_segment) { @@ -811,6 +867,7 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; if (node.type() != CHANX && node.type() != CHANY) continue; + if (node.capacity() == 0 || node.num_edges() == 0) continue; int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; VTR_ASSERT(seg_index != OPEN); @@ -828,10 +885,12 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se // initialize the samples vector for each sample point inodes_for_segment->clear(); inodes_for_segment->resize(num_segments); - for (auto& grid : *inodes_for_segment) { + for (int i = 0; i < num_segments; i++) { + auto& grid = (*inodes_for_segment)[i]; for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { grid.point[y][x].samples = std::vector(); + grid.point[y][x].segment_type = i; } } } @@ -840,7 +899,7 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; if (node.type() != CHANX && node.type() != CHANY) continue; - if (node.capacity() == 0) continue; + if (node.capacity() == 0 || node.num_edges() == 0) continue; const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(i); if (loc == nullptr) continue; @@ -859,16 +918,18 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se auto& grid = (*inodes_for_segment)[i]; for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { - grid.point[y][x].location = choose_point(counts, bounding_box, x, y, SAMPLE_GRID_SIZE); + vtr::Rect window = sample_window(bounding_box, x, y, SAMPLE_GRID_SIZE); + int selected_size = select_size(window, segment_counts[i]); + grid.point[y][x].location = choose_point(counts, window, selected_size); } } } - // select an inode near the center of the bounding box for each segment type + // collect the node indices for each segment type at the selected sample points for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; if (node.type() != CHANX && node.type() != CHANY) continue; - if (node.capacity() == 0) continue; + if (node.capacity() == 0 || node.num_edges() == 0) continue; const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(i); if (loc == nullptr) continue; diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 20ac7108a3a..5441462b233 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -90,7 +90,6 @@ util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( if (parent != nullptr) { auto& device_ctx = g_vpr_ctx.device(); - int cost_index = device_ctx.rr_nodes[set_rr_node_ind].cost_index(); this->base_cost = parent->base_cost + device_ctx.rr_indexed_data[cost_index].base_cost; } else { this->base_cost = 0.f; diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index 02b2f71c449..e930de56af6 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -170,7 +170,7 @@ class PQ_Entry_Base_Cost { return base_cost; } - void adjust_Tsw(float amount) { + void adjust_Tsw(float /* amount */) { // do nothing } From f2deff6b72abd8edc0a6ff92c3714aa266e17764 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 21 Nov 2019 09:28:01 -0800 Subject: [PATCH 076/107] Use get_rr_cong_cost to compute base_cost's. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/connection_box_lookahead_map.cpp | 3 +++ vpr/src/route/router_lookahead_map_utils.cpp | 11 +++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index bcc331fc46f..62cbffd602a 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -606,6 +606,9 @@ static uint64_t interleave(uint32_t x) { void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf) { vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); + // Initialize rr_node_route_inf if not already + alloc_and_load_rr_node_route_structs(); + size_t num_segments = segment_inf.size(); std::vector sample_points; { diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 5441462b233..6b62d7c4ff0 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -3,6 +3,7 @@ #include "globals.h" #include "vpr_context.h" #include "vtr_math.h" +#include "route_common.h" namespace util { @@ -24,8 +25,6 @@ PQ_Entry::PQ_Entry( this->congestion_upstream = parent_congestion_upstream; this->R_upstream = parent_R_upstream; if (!starting_node) { - int cost_index = device_ctx.rr_nodes[set_rr_node_ind].cost_index(); - float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; Tsw += Tsw_adjust; VTR_ASSERT(Tsw >= 0.f); @@ -40,7 +39,10 @@ PQ_Entry::PQ_Entry( T_linear = Tsw + 0.5 * Rsw * Cnode; } - float base_cost = device_ctx.rr_indexed_data[cost_index].base_cost; + float base_cost = 0.f; + if (device_ctx.rr_switch_inf[switch_ind].configurable()) { + base_cost = get_rr_cong_cost(set_rr_node_ind); + } VTR_ASSERT(T_linear >= 0.); VTR_ASSERT(base_cost >= 0.); @@ -90,7 +92,8 @@ util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( if (parent != nullptr) { auto& device_ctx = g_vpr_ctx.device(); - this->base_cost = parent->base_cost + device_ctx.rr_indexed_data[cost_index].base_cost; + this->base_cost = parent->base_cost + + (device_ctx.rr_switch_inf[switch_ind].configurable() ? get_rr_cong_cost(set_rr_node_ind) : 0); } else { this->base_cost = 0.f; } From b94323fcf36d5477092038f728db683d51ca1690 Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Mon, 25 Nov 2019 18:01:52 -0800 Subject: [PATCH 077/107] run expansions in a region until a number of paths are found Signed-off-by: Dustin DeWeese --- .../route/connection_box_lookahead_map.cpp | 265 +++++++++--------- 1 file changed, 129 insertions(+), 136 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 62cbffd602a..c6e2ec9c1db 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -11,6 +11,7 @@ #include "vtr_time.h" #include "vtr_geometry.h" #include "echo_files.h" +#include "rr_graph.h" #include "route_timing.h" @@ -50,26 +51,26 @@ static constexpr bool BREAK_ON_MISS = false; static constexpr float PENALTY_FACTOR = 1.f; static constexpr float PENALTY_MIN = 1e-12f; +static constexpr int MIN_PATH_COUNT = 1000; + // a sample point for a segment type, contains all segments at the VPR location struct SamplePoint { - uint64_t order; // used to order sample points vtr::Point location; - std::vector samples; - int segment_type; - SamplePoint() - : location(0, 0) {} + std::vector nodes; }; -// a grid of sample points -struct SampleGrid { - SamplePoint point[SAMPLE_GRID_SIZE][SAMPLE_GRID_SIZE]; +struct SampleRegion { + int segment_type; + vtr::Point grid_location; + std::vector points; + uint64_t order; // for sorting }; template static std::pair run_dijkstra(int start_node_ind, RoutingCosts* routing_costs); -static void find_inodes_for_segment_types(std::vector* inodes_for_segment); +static std::vector find_sample_regions(int num_segments); // also known as the L1 norm static int manhattan_distance(const vtr::Point& a, const vtr::Point& b) { @@ -592,16 +593,6 @@ static std::pair run_dijkstra(int start_node_ind, return std::make_pair(max_cost, path_count); } -static uint64_t interleave(uint32_t x) { - uint64_t i = x; - i = (i ^ (i << 16)) & 0x0000ffff0000ffff; - i = (i ^ (i << 8)) & 0x00ff00ff00ff00ff; - i = (i ^ (i << 4)) & 0x0f0f0f0f0f0f0f0f; - i = (i ^ (i << 2)) & 0x3333333333333333; - i = (i ^ (i << 1)) & 0x5555555555555555; - return i; -} - // compute the cost maps for lookahead void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf) { vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); @@ -610,30 +601,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen alloc_and_load_rr_node_route_structs(); size_t num_segments = segment_inf.size(); - std::vector sample_points; - { - std::vector inodes_for_segment(num_segments); - find_inodes_for_segment_types(&inodes_for_segment); - - // collapse into a vector - for (auto& grid : inodes_for_segment) { - for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { - for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { - auto& point = grid.point[y][x]; - if (!point.samples.empty()) { - point.order = interleave(point.location.x()) | (interleave(point.location.y()) << 1); - sample_points.push_back(point); - } - } - } - } - } - - // sort by VPR coordinate - std::sort(sample_points.begin(), sample_points.end(), - [](const SamplePoint& a, const SamplePoint& b) { - return a.order < b.order; - }); + std::vector sample_regions = find_sample_regions(num_segments); /* free previous delay map and allocate new one */ auto& device_ctx = g_vpr_ctx.device(); @@ -647,41 +615,65 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen /* run Dijkstra's algorithm for each segment type & channel type combination */ #if defined(VPR_USE_TBB) tbb::mutex all_costs_mutex; - tbb::parallel_for_each(sample_points, [&](const SamplePoint& point) { + tbb::parallel_for_each(sample_regions, [&](const SampleRegion& region) { #else - for (const auto& point : sample_points) { + for (const auto& region : sample_regions) { #endif // holds the cost entries for a run RoutingCosts delay_costs; RoutingCosts base_costs; + int total_path_count = 0; + + for (auto& point : region.points) { + // statistics + vtr::Timer run_timer; + float max_delay_cost = 0.f; + float max_base_cost = 0.f; + int path_count = 0; + for (auto node_ind : point.nodes) { + { + auto result = run_dijkstra(node_ind, &delay_costs); + max_delay_cost = std::max(max_delay_cost, result.first); + path_count += result.second; + } + { + auto result = run_dijkstra(node_ind, &base_costs); + max_base_cost = std::max(max_base_cost, result.first); + path_count += result.second; + } + } + + if (path_count > 0) { + VTR_LOG("Expanded %d paths of segment type %s(%d) starting at (%d, %d) from %d segments, max_cost %e %e (%g paths/sec)\n", + path_count, segment_inf[region.segment_type].name.c_str(), region.segment_type, + point.location.x(), point.location.y(), + (int)point.nodes.size(), + max_delay_cost, max_base_cost, + path_count / run_timer.elapsed_sec()); + } - // statistics - vtr::Timer run_timer; - int path_count = 0; - float max_delay_cost = 0.f; - float max_base_cost = 0.f; - for (auto node_ind : point.samples) { - { - auto result = run_dijkstra(node_ind, &delay_costs); - max_delay_cost = std::max(max_delay_cost, result.first); - path_count += result.second; + /* + if (path_count == 0) { + for (auto node_ind : point.nodes) { + VTR_LOG("Expanded node %s\n", describe_rr_node(node_ind).c_str()); + } } - { - auto result = run_dijkstra(node_ind, &base_costs); - max_base_cost = std::max(max_base_cost, result.first); - path_count += result.second; + */ + + total_path_count += path_count; + if (total_path_count > MIN_PATH_COUNT) { + break; } } #if defined(VPR_USE_TBB) all_costs_mutex.lock(); #endif - VTR_LOG("Expanded %d paths of segment type %s(%d) starting at (%d, %d) from %d segments, max_cost %e %e (%g paths/sec)\n", - path_count, segment_inf[point.segment_type].name.c_str(), point.segment_type, - point.location.x(), point.location.y(), - (int)point.samples.size(), - max_delay_cost, max_base_cost, - path_count / run_timer.elapsed_sec()); + + if (total_path_count == 0) { + VTR_LOG("No paths found for sample region %s(%d, %d)\n", + segment_inf[region.segment_type].name.c_str(), region.grid_location.x(), region.grid_location.y()); + } // combine the cost map from this run with the final cost maps for each segment for (const auto& cost : delay_costs) { @@ -778,42 +770,32 @@ static vtr::Rect sample_window(const vtr::Rect& bounding_box, int sx, sample(bounding_box, sx + 1, sy + 1, n)); } -static vtr::Point choose_point(const vtr::Matrix& counts, const vtr::Rect& window, int with_count) { - vtr::Point center = sample(window, 1, 1, 2); - vtr::Point sample_point = center; - if (with_count > 0) { - int sample_distance = std::numeric_limits::max(); - for (int y = window.ymin(); y < window.ymax(); y++) { - for (int x = window.xmin(); x < window.xmax(); x++) { - vtr::Point here(x, y); - if (counts[x][y] == with_count) { - int distance = manhattan_distance(center, here); - if (distance < sample_distance) { - sample_point = here; - sample_distance = distance; - } - } +static std::vector choose_points(const vtr::Matrix& counts, + const vtr::Rect& window, + int min_count, int max_count) { + std::vector points; + for (int y = window.ymin(); y < window.ymax(); y++) { + for (int x = window.xmin(); x < window.xmax(); x++) { + if (counts[x][y] >= min_count && counts[x][y] <= max_count) { + points.push_back(SamplePoint{ /* .location = */ vtr::Point(x, y), + /* .nodes = */ {} }); } } - VTR_ASSERT(counts[sample_point.x()][sample_point.y()] > 0); } - return sample_point; -} -// linear lookup, so consider something more sophisticated for large SAMPLE_GRID_SIZEs -static std::pair grid_lookup(const SampleGrid& grid, vtr::Point point) { - for (int sy = 0; sy < SAMPLE_GRID_SIZE; sy++) { - for (int sx = 0; sx < SAMPLE_GRID_SIZE; sx++) { - if (grid.point[sy][sx].location == point) { - return std::make_pair(sx, sy); - } - } - } - return std::make_pair(-1, -1); + vtr::Point center = sample(window, 1, 1, 2); + + // sort by distance from center + std::sort(points.begin(), points.end(), + [&](const SamplePoint& a, const SamplePoint& b) { + return manhattan_distance(a.location, center) < manhattan_distance(b.location, center); + }); + + return points; } // histogram is a map from segment count to number of locations having that count -static int max_count_within_quantiles(const std::map& histogram, float lower, float upper) { +static int quantile(const std::map& histogram, float ratio) { if (histogram.empty()) { return 0; } @@ -821,48 +803,46 @@ static int max_count_within_quantiles(const std::map& histogram, float for (const auto& entry : histogram) { sum += entry.second; } - int lower_limit = std::ceil(sum * lower); - int upper_limit = std::ceil(sum * upper); - std::pair max(0, 0); + int limit = std::ceil(sum * ratio); for (const auto& entry : histogram) { - upper_limit -= entry.second; - if (lower_limit > 0) { - lower_limit -= entry.second; - if(lower_limit <= 0) { - max = entry; - } - } else { - if (entry.second >= max.second) { - max = entry; - } - if (upper_limit <= 0) { - break; - } + limit -= entry.second; + if (limit <= 0) { + return entry.first; } } - return max.first; + return 0; } // select a good number of segments to find -static int select_size(const vtr::Rect& box, const vtr::Matrix& counts) { +static std::map count_histogram(const vtr::Rect& box, const vtr::Matrix& counts) { std::map histogram; for (int y = box.ymin(); y < box.ymax(); y++) { for (int x = box.xmin(); x < box.xmax(); x++) { int count = counts[x][y]; if (count > 0) { - histogram[count]++; + ++histogram[count]; } } } - return max_count_within_quantiles(histogram, 0.75, 0.9); + return histogram; +} + +static uint64_t interleave(uint32_t x) { + uint64_t i = x; + i = (i ^ (i << 16)) & 0x0000ffff0000ffff; + i = (i ^ (i << 8)) & 0x00ff00ff00ff00ff; + i = (i ^ (i << 4)) & 0x0f0f0f0f0f0f0f0f; + i = (i ^ (i << 2)) & 0x3333333333333333; + i = (i ^ (i << 1)) & 0x5555555555555555; + return i; } // for each segment type, find the nearest nodes to an equally spaced grid of points // within the bounding box for that segment type -static void find_inodes_for_segment_types(std::vector* inodes_for_segment) { +static std::vector find_sample_regions(int num_segments) { + std::vector sample_regions; auto& device_ctx = g_vpr_ctx.device(); auto& rr_nodes = device_ctx.rr_nodes; - const int num_segments = inodes_for_segment->size(); std::vector> segment_counts(num_segments); // compute bounding boxes for each segment type @@ -885,19 +865,6 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se segment_counts[seg] = vtr::Matrix({size_t(box.width()), size_t(box.height())}, 0); } - // initialize the samples vector for each sample point - inodes_for_segment->clear(); - inodes_for_segment->resize(num_segments); - for (int i = 0; i < num_segments; i++) { - auto& grid = (*inodes_for_segment)[i]; - for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { - for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { - grid.point[y][x].samples = std::vector(); - grid.point[y][x].segment_type = i; - } - } - } - // count sample points for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; @@ -918,16 +885,41 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se const auto& counts = segment_counts[i]; const auto& bounding_box = bounding_box_for_segment[i]; if (bounding_box.empty()) continue; - auto& grid = (*inodes_for_segment)[i]; for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { vtr::Rect window = sample_window(bounding_box, x, y, SAMPLE_GRID_SIZE); - int selected_size = select_size(window, segment_counts[i]); - grid.point[y][x].location = choose_point(counts, window, selected_size); + auto histogram = count_histogram(window, segment_counts[i]); + SampleRegion region = { + /* .segment_type = */ i, + /* .grid_location = */ vtr::Point(x, y), + /* .points = */ choose_points(counts, window, + quantile(histogram, 0.5), quantile(histogram, 0.7)), + /* .order = */ 0 + }; + if(!region.points.empty()) { + vtr::Point location = region.points[0].location; + region.order = interleave(location.x()) | (interleave(location.y()) << 1); + sample_regions.push_back(region); + } } } } + // sort regions + std::sort(sample_regions.begin(), sample_regions.end(), + [](const SampleRegion& a, const SampleRegion& b) { + return a.order < b.order; + }); + + + // build an index of sample points on segment type and location + std::map, SamplePoint*> sample_point_index; + for (auto ®ion : sample_regions) { + for (auto &point : region.points) { + sample_point_index[{region.segment_type, point.location.x(), point.location.y()}] = &point; + } + } + // collect the node indices for each segment type at the selected sample points for (size_t i = 0; i < rr_nodes.size(); i++) { auto& node = rr_nodes[i]; @@ -941,12 +933,13 @@ static void find_inodes_for_segment_types(std::vector* inodes_for_se VTR_ASSERT(seg_index != OPEN); VTR_ASSERT(seg_index < num_segments); - auto& grid = (*inodes_for_segment)[seg_index]; - auto grid_loc = grid_lookup(grid, vtr::Point(loc->first, loc->second)); - if (grid_loc.first >= 0) { - grid.point[grid_loc.first][grid_loc.second].samples.push_back(i); + auto point = sample_point_index.find({seg_index, loc->first, loc->second}); + if (point != sample_point_index.end()) { + point->second->nodes.push_back(i); } } + + return sample_regions; } #ifndef VTR_ENABLE_CAPNPROTO From 03e7b34ae90153826996cb65c1650382c9c55bb3 Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Tue, 26 Nov 2019 13:52:10 -0800 Subject: [PATCH 078/107] make format Signed-off-by: Dustin DeWeese --- .../route/connection_box_lookahead_map.cpp | 40 +++++++++---------- vpr/src/route/router_lookahead_map_utils.cpp | 35 +++++++--------- 2 files changed, 34 insertions(+), 41 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index c6e2ec9c1db..31a1793b11a 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -344,13 +344,13 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMat const vtr::Rect& bounds) { // spiral around (cx, cy) looking for a nearby entry bool in_bounds = bounds.contains(vtr::Point(cx, cy)); - if(!in_bounds) { + if (!in_bounds) { return std::make_pair(util::Cost_Entry(), 0); } int n = 0; util::Cost_Entry fill(matrix[cx][cy]); - while(in_bounds && !fill.valid()) { + while (in_bounds && !fill.valid()) { n++; in_bounds = false; util::Cost_Entry min_entry; @@ -505,14 +505,14 @@ static bool add_paths(int start_node_ind, box_id, delta}; - if(*it != start_node_ind) { + if (*it != start_node_ind) { auto& parent_node = device_ctx.rr_nodes[parent]; start_to_here = Entry(*it, parent_node.edge_switch((*paths)[*it].edge), &start_to_here); parent = *it; } float cost = current.cost() - start_to_here.cost(); - if(cost < 0.f && cost > -10e-15 /* 10 femtosecond */) { + if (cost < 0.f && cost > -10e-15 /* 10 femtosecond */) { cost = 0.f; } @@ -653,12 +653,12 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen } /* - if (path_count == 0) { - for (auto node_ind : point.nodes) { - VTR_LOG("Expanded node %s\n", describe_rr_node(node_ind).c_str()); - } - } - */ + * if (path_count == 0) { + * for (auto node_ind : point.nodes) { + * VTR_LOG("Expanded node %s\n", describe_rr_node(node_ind).c_str()); + * } + * } + */ total_path_count += path_count; if (total_path_count > MIN_PATH_COUNT) { @@ -772,13 +772,14 @@ static vtr::Rect sample_window(const vtr::Rect& bounding_box, int sx, static std::vector choose_points(const vtr::Matrix& counts, const vtr::Rect& window, - int min_count, int max_count) { + int min_count, + int max_count) { std::vector points; for (int y = window.ymin(); y < window.ymax(); y++) { for (int x = window.xmin(); x < window.xmax(); x++) { if (counts[x][y] >= min_count && counts[x][y] <= max_count) { - points.push_back(SamplePoint{ /* .location = */ vtr::Point(x, y), - /* .nodes = */ {} }); + points.push_back(SamplePoint{/* .location = */ vtr::Point(x, y), + /* .nodes = */ {}}); } } } @@ -892,11 +893,9 @@ static std::vector find_sample_regions(int num_segments) { SampleRegion region = { /* .segment_type = */ i, /* .grid_location = */ vtr::Point(x, y), - /* .points = */ choose_points(counts, window, - quantile(histogram, 0.5), quantile(histogram, 0.7)), - /* .order = */ 0 - }; - if(!region.points.empty()) { + /* .points = */ choose_points(counts, window, quantile(histogram, 0.5), quantile(histogram, 0.7)), + /* .order = */ 0}; + if (!region.points.empty()) { vtr::Point location = region.points[0].location; region.order = interleave(location.x()) | (interleave(location.y()) << 1); sample_regions.push_back(region); @@ -911,11 +910,10 @@ static std::vector find_sample_regions(int num_segments) { return a.order < b.order; }); - // build an index of sample points on segment type and location std::map, SamplePoint*> sample_point_index; - for (auto ®ion : sample_regions) { - for (auto &point : region.points) { + for (auto& region : sample_regions) { + for (auto& point : region.points) { sample_point_index[{region.segment_type, point.location.x(), point.location.y()}] = &point; } } diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 6b62d7c4ff0..1e26287068b 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -59,7 +59,6 @@ util::PQ_Entry_Delay::PQ_Entry_Delay( int set_rr_node_ind, int switch_ind, const util::PQ_Entry_Delay* parent) { - this->rr_node_ind = set_rr_node_ind; if (parent != nullptr) { @@ -87,13 +86,11 @@ util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( int set_rr_node_ind, int switch_ind, const util::PQ_Entry_Base_Cost* parent) { - this->rr_node_ind = set_rr_node_ind; if (parent != nullptr) { auto& device_ctx = g_vpr_ctx.device(); - this->base_cost = parent->base_cost + - (device_ctx.rr_switch_inf[switch_ind].configurable() ? get_rr_cong_cost(set_rr_node_ind) : 0); + this->base_cost = parent->base_cost + (device_ctx.rr_switch_inf[switch_ind].configurable() ? get_rr_cong_cost(set_rr_node_ind) : 0); } else { this->base_cost = 0.f; } @@ -234,21 +231,19 @@ void expand_dijkstra_neighbours(const std::vector& rr_nodes, } } -template -void expand_dijkstra_neighbours(const std::vector& rr_nodes, - const PQ_Entry_Delay& parent_entry, - std::unordered_map& paths, - std::vector& node_expanded, - std::priority_queue, - std::greater>& pq); -template -void expand_dijkstra_neighbours(const std::vector& rr_nodes, - const PQ_Entry_Base_Cost& parent_entry, - std::unordered_map& paths, - std::vector& node_expanded, - std::priority_queue, - std::greater>& pq); +template void expand_dijkstra_neighbours(const std::vector& rr_nodes, + const PQ_Entry_Delay& parent_entry, + std::unordered_map& paths, + std::vector& node_expanded, + std::priority_queue, + std::greater>& pq); +template void expand_dijkstra_neighbours(const std::vector& rr_nodes, + const PQ_Entry_Base_Cost& parent_entry, + std::unordered_map& paths, + std::vector& node_expanded, + std::priority_queue, + std::greater>& pq); } // namespace util From a0e292c6ae9c8cc98246cfa43ebf0fd9575cd4b8 Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Tue, 3 Dec 2019 10:46:39 -0800 Subject: [PATCH 079/107] use std::make_tuple() Signed-off-by: Dustin DeWeese --- vpr/src/route/connection_box_lookahead_map.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index 31a1793b11a..a8591320d92 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -914,7 +914,7 @@ static std::vector find_sample_regions(int num_segments) { std::map, SamplePoint*> sample_point_index; for (auto& region : sample_regions) { for (auto& point : region.points) { - sample_point_index[{region.segment_type, point.location.x(), point.location.y()}] = &point; + sample_point_index[std::make_tuple(region.segment_type, point.location.x(), point.location.y())] = &point; } } @@ -931,7 +931,7 @@ static std::vector find_sample_regions(int num_segments) { VTR_ASSERT(seg_index != OPEN); VTR_ASSERT(seg_index < num_segments); - auto point = sample_point_index.find({seg_index, loc->first, loc->second}); + auto point = sample_point_index.find(std::make_tuple(seg_index, loc->first, loc->second)); if (point != sample_point_index.end()) { point->second->nodes.push_back(i); } From 38bc36e909d7c0ed210f0211105e12398ca958e1 Mon Sep 17 00:00:00 2001 From: Dustin DeWeese Date: Tue, 3 Dec 2019 15:28:10 -0800 Subject: [PATCH 080/107] suggested changes Signed-off-by: Dustin DeWeese --- libs/libvtrcapnproto/connection_map.capnp | 1 + libs/libvtrutil/src/vtr_geometry.tpp | 2 + .../route/connection_box_lookahead_map.cpp | 72 ++++++++++++++++--- vpr/src/route/connection_box_lookahead_map.h | 9 --- vpr/src/route/router_lookahead_map_utils.cpp | 9 +-- vpr/src/route/router_lookahead_map_utils.h | 3 + 6 files changed, 73 insertions(+), 23 deletions(-) diff --git a/libs/libvtrcapnproto/connection_map.capnp b/libs/libvtrcapnproto/connection_map.capnp index bc445a30e70..30b9864153b 100644 --- a/libs/libvtrcapnproto/connection_map.capnp +++ b/libs/libvtrcapnproto/connection_map.capnp @@ -5,6 +5,7 @@ using Matrix = import "matrix.capnp"; struct VprCostEntry { delay @0 :Float32; congestion @1 :Float32; + fill @2 :Bool; } struct VprVector2D { diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 971fb22a29a..5fd065b3107 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -80,6 +80,7 @@ Rect::Rect(Point bottom_left_val, Point top_right_val) //pass } +//Only defined for integral types template template::value>::type...> Rect::Rect(Point point) @@ -174,6 +175,7 @@ Rect bounding_box(const Rect& lhs, const Rect& rhs) { std::max(lhs.ymax(), rhs.ymax())); } +//Only defined for integral types template::value>::type...> Point sample(const vtr::Rect& r, T x, T y, T d) { VTR_ASSERT(d > 0); diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index a8591320d92..adda9c941ee 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -53,17 +53,34 @@ static constexpr float PENALTY_MIN = 1e-12f; static constexpr int MIN_PATH_COUNT = 1000; +// quantiles (like percentiles but 0-1) of segment count to use as a selection criteria +// choose locations with higher, but not extreme, counts of each segment type +static constexpr double kSamplingCountLowerQuantile = 0.5; +static constexpr double kSamplingCountUpperQuantile = 0.7; + // a sample point for a segment type, contains all segments at the VPR location struct SamplePoint { + // canonical location vtr::Point location; + + // nodes to expand std::vector nodes; }; struct SampleRegion { + // all nodes in `points' have this segment type int segment_type; + + // location on the sample grid vtr::Point grid_location; + + // locations to try + // The computation will keep expanding each of the points + // until a number of paths (segment -> connection box) are found. std::vector points; - uint64_t order; // for sorting + + // used to sort the regions to improve caching + uint64_t order; }; template @@ -168,7 +185,7 @@ void CostMap::set_cost_map(const RoutingCosts& delay_costs, const RoutingCosts& } else { offset_[seg][box] = std::make_pair(seg_box_bounds.xmin(), seg_box_bounds.ymin()); cost_map_[seg][box] = vtr::NdMatrix( - {size_t(seg_box_bounds.width()), size_t(seg_box_bounds.height())}, util::Cost_Entry()); + {size_t(seg_box_bounds.width()), size_t(seg_box_bounds.height())}); } } } @@ -349,6 +366,7 @@ std::pair CostMap::get_nearby_cost_entry(const vtr::NdMat } int n = 0; util::Cost_Entry fill(matrix[cx][cy]); + fill.fill = true; while (in_bounds && !fill.valid()) { n++; @@ -447,6 +465,15 @@ float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; + VTR_LOGV_DEBUG(f_router_debug, "Requested lookahead from node %d to %d\n", from_node_ind, to_node_ind); + const std::string& segment_name = device_ctx.segment_inf[from_seg_index].name; + const std::string& box_name = device_ctx.connection_boxes.get_connection_box(box_id)->name; + VTR_LOGV_DEBUG(f_router_debug, "Lookahead returned %s (%d) to %s (%zu) with distance (%zd, %zd)\n", + segment_name.c_str(), from_seg_index, + box_name.c_str(), + size_t(box_id), + dx, dy); + VTR_LOGV_DEBUG(f_router_debug, "Lookahead delay: %g\n", expected_delay); VTR_LOGV_DEBUG(f_router_debug, "Lookahead congestion: %g\n", expected_congestion); VTR_LOGV_DEBUG(f_router_debug, "Criticality: %g\n", criticality_fac); VTR_LOGV_DEBUG(f_router_debug, "Lookahead cost: %g\n", expected_cost); @@ -534,9 +561,12 @@ static bool add_paths(int start_node_ind, return new_sample_found; } -/* runs Dijkstra's algorithm from specified node until all nodes have been +/* Runs Dijkstra's algorithm from specified node until all nodes have been * visited. Each time a pin is visited, the delay/congestion information - * to that pin is stored to an entry in the routing_cost_map */ + * to that pin is stored to an entry in the routing_cost_map. + * + * Returns the maximum (last) minimum cost path stored, and + * the number of paths from start_node_ind stored. */ template static std::pair run_dijkstra(int start_node_ind, RoutingCosts* routing_costs) { @@ -572,9 +602,6 @@ static std::pair run_dijkstra(int start_node_ind, int node_ind = current.rr_node_ind; - // the last cost should be the highest - max_cost = current.cost(); - /* check that we haven't already expanded from this node */ if (node_expanded[node_ind]) { continue; @@ -582,6 +609,9 @@ static std::pair run_dijkstra(int start_node_ind, /* if this node is an ipin record its congestion/delay in the routing_cost_map */ if (device_ctx.rr_nodes[node_ind].type() == IPIN) { + // the last cost should be the highest + max_cost = current.cost(); + path_count++; add_paths(start_node_ind, current, &paths, routing_costs); } else { @@ -671,8 +701,8 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen #endif if (total_path_count == 0) { - VTR_LOG("No paths found for sample region %s(%d, %d)\n", - segment_inf[region.segment_type].name.c_str(), region.grid_location.x(), region.grid_location.y()); + VTR_LOG_WARN("No paths found for sample region %s(%d, %d)\n", + segment_inf[region.segment_type].name.c_str(), region.grid_location.x(), region.grid_location.y()); } // combine the cost map from this run with the final cost maps for each segment @@ -774,6 +804,7 @@ static std::vector choose_points(const vtr::Matrix& counts, const vtr::Rect& window, int min_count, int max_count) { + VTR_ASSERT(min_count <= max_count); std::vector points; for (int y = window.ymin(); y < window.ymax(); y++) { for (int x = window.xmin(); x < window.xmax(); x++) { @@ -828,6 +859,13 @@ static std::map count_histogram(const vtr::Rect& box, const vtr:: return histogram; } +// Used to calculate each region's `order.' +// A space-filling curve will order the regions so that +// nearby points stay close in order. A Hilbert curve might +// be better, but a Morton (Z)-order curve is easy to compute, +// because it's just interleaving binary bits, so this +// function interleaves with 0's so that the X and Y +// dimensions can then be OR'ed together. static uint64_t interleave(uint32_t x) { uint64_t i = x; i = (i ^ (i << 16)) & 0x0000ffff0000ffff; @@ -841,6 +879,7 @@ static uint64_t interleave(uint32_t x) { // for each segment type, find the nearest nodes to an equally spaced grid of points // within the bounding box for that segment type static std::vector find_sample_regions(int num_segments) { + vtr::ScopedStartFinishTimer timer("finding sample regions"); std::vector sample_regions; auto& device_ctx = g_vpr_ctx.device(); auto& rr_nodes = device_ctx.rr_nodes; @@ -893,11 +932,22 @@ static std::vector find_sample_regions(int num_segments) { SampleRegion region = { /* .segment_type = */ i, /* .grid_location = */ vtr::Point(x, y), - /* .points = */ choose_points(counts, window, quantile(histogram, 0.5), quantile(histogram, 0.7)), + /* .points = */ choose_points(counts, window, quantile(histogram, kSamplingCountLowerQuantile), quantile(histogram, kSamplingCountUpperQuantile)), /* .order = */ 0}; if (!region.points.empty()) { + /* In order to improve caching, the list of sample points are + * sorted to keep points that are nearby on the Euclidean plane also + * nearby in the vector of sample points. + * + * This means subsequent expansions on the same thread are likely + * to cover a similar set of nodes, so they are more likely to be + * cached. This improves performance by about 7%, which isn't a lot, + * but not a bad improvement for a few lines of code. */ vtr::Point location = region.points[0].location; + + // interleave bits of X and Y for a Z-curve ordering. region.order = interleave(location.x()) | (interleave(location.y()) << 1); + sample_regions.push_back(region); } } @@ -961,11 +1011,13 @@ void ConnectionBoxMapLookahead::write(const std::string& file) const { static void ToCostEntry(util::Cost_Entry* out, const VprCostEntry::Reader& in) { out->delay = in.getDelay(); out->congestion = in.getCongestion(); + out->fill = in.getFill(); } static void FromCostEntry(VprCostEntry::Builder* out, const util::Cost_Entry& in) { out->setDelay(in.delay); out->setCongestion(in.congestion); + out->setFill(in.fill); } static void ToVprVector2D(std::pair* out, const VprVector2D::Reader& in) { diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h index 810dec59135..70423409f7a 100644 --- a/vpr/src/route/connection_box_lookahead_map.h +++ b/vpr/src/route/connection_box_lookahead_map.h @@ -32,15 +32,6 @@ struct RoutingCostKey { } }; -// Data in the RoutingCosts map -struct RoutingCost { - // source and destination node indices - int from_node, to_node; - - // cost entry for the route - util::Cost_Entry cost_entry; -}; - // hash implementation for RoutingCostKey struct HashRoutingCostKey { std::size_t operator()(RoutingCostKey const& key) const noexcept { diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index 1e26287068b..dd8f7af7dd3 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -7,9 +7,6 @@ namespace util { -/* Number of CLBs I think the average conn. goes. */ -static const int CLB_DIST = 3; - PQ_Entry::PQ_Entry( int set_rr_node_ind, int switch_ind, @@ -90,7 +87,11 @@ util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( if (parent != nullptr) { auto& device_ctx = g_vpr_ctx.device(); - this->base_cost = parent->base_cost + (device_ctx.rr_switch_inf[switch_ind].configurable() ? get_rr_cong_cost(set_rr_node_ind) : 0); + if (device_ctx.rr_switch_inf[switch_ind].configurable()) { + this->base_cost = parent->base_cost + get_rr_cong_cost(set_rr_node_ind); + } else { + this->base_cost = parent->base_cost; + } } else { this->base_cost = 0.f; } diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index e930de56af6..fc0c35fc0f2 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -41,14 +41,17 @@ class Cost_Entry { public: float delay; float congestion; + bool fill; Cost_Entry() { delay = std::numeric_limits::infinity(); congestion = std::numeric_limits::infinity(); + fill = false; } Cost_Entry(float set_delay, float set_congestion) { delay = set_delay; congestion = set_congestion; + fill = false; } bool valid() const { From e3cdb16c55a2d616ace9e2abc85921a0c418fa7c Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 31 Oct 2019 12:22:58 -0700 Subject: [PATCH 081/107] Add debugging prints and add fill output to lookahead. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/base/SetupVPR.cpp | 1 + vpr/src/base/vpr_context.h | 1 + vpr/src/route/connection_box.cpp | 2 +- .../route/connection_box_lookahead_map.cpp | 6 +-- vpr/src/route/route_profiling.cpp | 40 +++++++++++++++++++ vpr/src/route/route_profiling.h | 4 ++ vpr/src/route/route_timing.cpp | 9 +++++ vpr/src/route/router_lookahead_map_utils.cpp | 22 +++++----- vpr/src/route/router_lookahead_map_utils.h | 17 ++++---- 9 files changed, 80 insertions(+), 22 deletions(-) diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 4fd21004eb5..9033b536b3d 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -160,6 +160,7 @@ void SetupVPR(const t_options* Options, } Segments = Arch->Segments; + device_ctx.segment_inf = Arch->Segments; SetupSwitches(*Arch, RoutingArch, Arch->Switches, Arch->num_switches); SetupRoutingArch(*Arch, RoutingArch); diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 122fa95229a..06b3731cf2b 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -162,6 +162,7 @@ struct DeviceContext : public Context { t_rr_node_indices rr_node_indices; //[0..NUM_RR_TYPES-1][0..grid.width()-1][0..grid.width()-1][0..size-1] std::vector rr_switch_inf; /* autogenerated in build_rr_graph based on switch fan-in. [0..(num_rr_switches-1)] */ + std::vector segment_inf; int num_arch_switches; t_arch_switch_inf* arch_switch_inf; /* [0..(num_arch_switches-1)] */ diff --git a/vpr/src/route/connection_box.cpp b/vpr/src/route/connection_box.cpp index ab52817e48b..efd8ab2bc95 100644 --- a/vpr/src/route/connection_box.cpp +++ b/vpr/src/route/connection_box.cpp @@ -15,7 +15,7 @@ std::pair ConnectionBoxes::connection_box_grid_size() const { } const ConnectionBox* ConnectionBoxes::get_connection_box(ConnectionBoxId box) const { - if (bool(box)) { + if (!bool(box)) { return nullptr; } diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp index adda9c941ee..f0328876019 100644 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ b/vpr/src/route/connection_box_lookahead_map.cpp @@ -37,7 +37,7 @@ * NOTE: Currently, only SMALLEST is supported. * * See e_representative_entry_method */ -#define REPRESENTATIVE_ENTRY_METHOD SMALLEST +#define REPRESENTATIVE_ENTRY_METHOD util::SMALLEST #define CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_MAPS @@ -140,7 +140,7 @@ int CostMap::node_to_segment(int from_node_ind) const { static util::Cost_Entry penalize(const util::Cost_Entry& entry, int distance, float penalty) { penalty = std::max(penalty, PENALTY_MIN); return util::Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, - entry.congestion); + entry.congestion, entry.fill); } // get a cost entry for a segment type, connection box type, and offset @@ -638,7 +638,7 @@ void ConnectionBoxMapLookahead::compute(const std::vector& segmen cost_map_.set_counts(segment_inf.size(), device_ctx.connection_boxes.num_connection_box_types()); - VTR_ASSERT(REPRESENTATIVE_ENTRY_METHOD == SMALLEST); + VTR_ASSERT(REPRESENTATIVE_ENTRY_METHOD == util::SMALLEST); RoutingCosts all_delay_costs; RoutingCosts all_base_costs; diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index c5e5737caca..b393711eba9 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -2,6 +2,7 @@ #include "globals.h" #include "vpr_types.h" #include "route_profiling.h" +#include "rr_graph.h" namespace profiling { @@ -29,6 +30,10 @@ void time_on_fanout_analysis() {} void profiling_initialization(unsigned /*max_net_fanout*/) {} +void conn_start() {} +void conn_finish(int /*src_rr*/, int /*sink_rr*/, float /*criticality*/) {} +void net_finish() {} + #else constexpr unsigned int fanout_per_bin = 1; @@ -181,6 +186,12 @@ void congestion_analysis() { # endif } +static clock_t conn_start_time; +static float worst_conn_time = 0.f; +static int worst_src_rr; +static int worst_sink_rr; +static float worst_crit; + void profiling_initialization(unsigned max_fanout) { // add 1 so that indexing on the max fanout would still be valid time_on_fanout.resize((max_fanout / fanout_per_bin) + 1, 0); @@ -195,8 +206,37 @@ void profiling_initialization(unsigned max_fanout) { part_tree_preserved = 0; connections_forced_to_reroute = 0; connections_rerouted_due_to_forcing = 0; + worst_conn_time = 0.f; return; } + +void conn_start() { + conn_start_time = clock(); +} +void conn_finish(int src_rr, int sink_rr, float criticality) { + float route_time = static_cast(clock() - conn_start_time) / CLOCKS_PER_SEC; + if (route_time > worst_conn_time) { + worst_src_rr = src_rr; + worst_sink_rr = sink_rr; + worst_conn_time = route_time; + worst_crit = criticality; + } + + VTR_LOG("%s to %s (crit: %f) took %f\n", + describe_rr_node(src_rr).c_str(), + describe_rr_node(sink_rr).c_str(), + criticality, + route_time); +} +void net_finish() { + if (worst_conn_time > 0.f) { + VTR_LOG("Worst conn was %s to %s (crit: %f) took %f\n", + describe_rr_node(worst_src_rr).c_str(), + describe_rr_node(worst_sink_rr).c_str(), + worst_crit, + worst_conn_time); + } +} #endif } // end namespace profiling diff --git a/vpr/src/route/route_profiling.h b/vpr/src/route/route_profiling.h index 52a73655214..3cc1ec377a2 100644 --- a/vpr/src/route/route_profiling.h +++ b/vpr/src/route/route_profiling.h @@ -30,6 +30,10 @@ void congestion_analysis(); void time_on_criticality_analysis(); void time_on_fanout_analysis(); +void conn_start(); +void conn_finish(int src_rr, int sink_rr, float criticality); +void net_finish(); + void profiling_initialization(unsigned max_net_fanout); } // end namespace profiling diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index cc738162be4..22dbf73dd91 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -1043,6 +1043,8 @@ bool timing_driven_route_net(ClusterNetId net_id, conn_delay_budget.short_path_criticality = budgeting_inf.get_crit_short_path(net_id, target_pin); } + profiling::conn_start(); + // build a branch in the route tree to the target if (!timing_driven_route_sink(net_id, itarget, @@ -1056,10 +1058,15 @@ bool timing_driven_route_net(ClusterNetId net_id, router_stats)) return false; + profiling::conn_finish(route_ctx.net_rr_terminals[net_id][0], + sink_rr, + pin_criticality[target_pin]); + ++router_stats.connections_routed; } // finished all sinks ++router_stats.nets_routed; + profiling::net_finish(); /* For later timing analysis. */ @@ -2099,6 +2106,8 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, // //Pre-heap prune to keep the heap small, by not putting paths which are known to be //sub-optimal (at this point in time) into the heap. + VTR_LOGV_DEBUG(f_router_debug, " Adding node %8d to heap from init route tree with cost %g (%s)\n", + next->index, new_next_total_cost, describe_rr_node(next->index).c_str()); add_to_heap(next); ++router_stats.heap_pushes; } else { diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp index dd8f7af7dd3..081d6276057 100644 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ b/vpr/src/route/router_lookahead_map_utils.cpp @@ -98,8 +98,8 @@ util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( } /* returns cost entry with the smallest delay */ -Cost_Entry Expansion_Cost_Entry::get_smallest_entry() const { - Cost_Entry smallest_entry; +util::Cost_Entry util::Expansion_Cost_Entry::get_smallest_entry() const { + util::Cost_Entry smallest_entry; for (auto entry : this->cost_vector) { if (!smallest_entry.valid() || entry.delay < smallest_entry.delay) { @@ -111,7 +111,7 @@ Cost_Entry Expansion_Cost_Entry::get_smallest_entry() const { } /* returns a cost entry that represents the average of all the recorded entries */ -Cost_Entry Expansion_Cost_Entry::get_average_entry() const { +util::Cost_Entry util::Expansion_Cost_Entry::get_average_entry() const { float avg_delay = 0; float avg_congestion = 0; @@ -123,11 +123,11 @@ Cost_Entry Expansion_Cost_Entry::get_average_entry() const { avg_delay /= (float)this->cost_vector.size(); avg_congestion /= (float)this->cost_vector.size(); - return Cost_Entry(avg_delay, avg_congestion); + return util::Cost_Entry(avg_delay, avg_congestion); } /* returns a cost entry that represents the geomean of all the recorded entries */ -Cost_Entry Expansion_Cost_Entry::get_geomean_entry() const { +util::Cost_Entry util::Expansion_Cost_Entry::get_geomean_entry() const { float geomean_delay = 0; float geomean_cong = 0; for (auto cost_entry : this->cost_vector) { @@ -138,19 +138,19 @@ Cost_Entry Expansion_Cost_Entry::get_geomean_entry() const { geomean_delay = exp(geomean_delay / (float)this->cost_vector.size()); geomean_cong = exp(geomean_cong / (float)this->cost_vector.size()); - return Cost_Entry(geomean_delay, geomean_cong); + return util::Cost_Entry(geomean_delay, geomean_cong); } /* returns a cost entry that represents the medial of all recorded entries */ -Cost_Entry Expansion_Cost_Entry::get_median_entry() const { +util::Cost_Entry util::Expansion_Cost_Entry::get_median_entry() const { /* find median by binning the delays of all entries and then chosing the bin * with the largest number of entries */ int num_bins = 10; /* find entries with smallest and largest delays */ - Cost_Entry min_del_entry; - Cost_Entry max_del_entry; + util::Cost_Entry min_del_entry; + util::Cost_Entry max_del_entry; for (auto entry : this->cost_vector) { if (!min_del_entry.valid() || entry.delay < min_del_entry.delay) { min_del_entry = entry; @@ -165,7 +165,7 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { float bin_size = delay_diff / (float)num_bins; /* sort the cost entries into bins */ - std::vector> entry_bins(num_bins, std::vector()); + std::vector> entry_bins(num_bins, std::vector()); for (auto entry : this->cost_vector) { float bin_num = floor((entry.delay - min_del_entry.delay) / bin_size); @@ -188,7 +188,7 @@ Cost_Entry Expansion_Cost_Entry::get_median_entry() const { } /* get the representative delay of the largest bin */ - Cost_Entry representative_entry = entry_bins[largest_bin][0]; + util::Cost_Entry representative_entry = entry_bins[largest_bin][0]; return representative_entry; } diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h index fc0c35fc0f2..36e6ea510f7 100644 --- a/vpr/src/route/router_lookahead_map_utils.h +++ b/vpr/src/route/router_lookahead_map_utils.h @@ -23,6 +23,8 @@ #include "vpr_types.h" #include "rr_node.h" +namespace util { + /* when a list of delay/congestion entries at a coordinate in Cost_Entry is boiled down to a single * representative entry, this enum is passed-in to specify how that representative entry should be * calculated */ @@ -34,7 +36,6 @@ enum e_representative_entry_method { MEDIAN }; -namespace util { /* f_cost_map is an array of these cost entries that specifies delay/congestion estimates * to travel relative x/y distances */ class Cost_Entry { @@ -48,12 +49,14 @@ class Cost_Entry { congestion = std::numeric_limits::infinity(); fill = false; } - Cost_Entry(float set_delay, float set_congestion) { - delay = set_delay; - congestion = set_congestion; - fill = false; - } - + Cost_Entry(float set_delay, float set_congestion) + : delay(set_delay) + , congestion(set_congestion) + , fill(false) {} + Cost_Entry(float set_delay, float set_congestion, bool set_fill) + : delay(set_delay) + , congestion(set_congestion) + , fill(set_fill) {} bool valid() const { return std::isfinite(delay) && std::isfinite(congestion); } From 95b6160c3bd9a1ebcdeb9e963ef3803ac654a1b4 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 4 Nov 2019 08:23:43 -0800 Subject: [PATCH 082/107] Have route_diag use criticality from --max_criticality argument. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- utils/route_diag/src/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index ee1c467d17c..e972e7131e1 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -83,7 +83,7 @@ static void do_one_route(int source_node, int sink_node, bounding_box.ymax = device_ctx.grid.height() + 1; t_conn_cost_params cost_params; - cost_params.criticality = 1.; + cost_params.criticality = router_opts.max_criticality; cost_params.astar_fac = router_opts.astar_fac; cost_params.bend_cost = router_opts.bend_cost; From ad3cdbadeb69327ace7d4984cdd1fb9aa05956bd Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 3 Dec 2019 14:43:29 -0800 Subject: [PATCH 083/107] Move around stuff to avoid conflicts. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/rr_graph_reader.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index bdbd8fb9d45..bb273a085b7 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -47,13 +47,13 @@ #include "rr_graph_reader.h" /*********************** Subroutines local to this module *******************/ +void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const std::vector& segment_inf); void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid); void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); -void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches); void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_rr_node_indices(const DeviceGrid& grid); @@ -182,11 +182,12 @@ void load_rr_file(const t_graph_type graph_type, process_seg_id(next_component, loc_data); + device_ctx.connection_boxes.create_sink_back_ref(); + device_ctx.chan_width = nodes_per_chan; device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); - device_ctx.connection_boxes.create_sink_back_ref(); } catch (pugiutil::XmlError& e) { vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what()); From 062b9efc6adae9c8b512b9d6fce52b65f20e24a1 Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Thu, 28 Nov 2019 13:34:18 +0100 Subject: [PATCH 084/107] placement: add possibility to constraint other blocks than IO pads Signed-off-by: Alessandro Comodi --- vpr/src/base/read_place.cpp | 40 ++++++++------- vpr/src/place/initial_placement.cpp | 75 ++++++++++++++--------------- 2 files changed, 58 insertions(+), 57 deletions(-) diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp index 929192ec34c..dc83c90b48e 100644 --- a/vpr/src/base/read_place.cpp +++ b/vpr/src/base/read_place.cpp @@ -146,6 +146,7 @@ void read_user_pad_loc(const char* pad_loc_file) { int xtmp, ytmp; FILE* fp; char buf[vtr::bufsize], bname[vtr::bufsize], *ptr; + std::unordered_set constrained_blocks; auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); @@ -160,17 +161,14 @@ void read_user_pad_loc(const char* pad_loc_file) { hash_table = alloc_hash_table(); for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - if (is_io_type(pick_best_physical_type(logical_block))) { - insert_in_hash_table(hash_table, cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id)); - place_ctx.block_locs[blk_id].loc.x = OPEN; /* Mark as not seen yet. */ - } + insert_in_hash_table(hash_table, cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id)); + place_ctx.block_locs[blk_id].loc.x = OPEN; /* Mark as not seen yet. */ } for (size_t i = 0; i < device_ctx.grid.width(); i++) { for (size_t j = 0; j < device_ctx.grid.height(); j++) { auto type = device_ctx.grid[i][j].type; - if (is_io_type(type)) { + if (!is_empty_type(type)) { for (int k = 0; k < type->capacity; k++) { if (place_ctx.grid_blocks[i][j].blocks[k] != INVALID_BLOCK_ID) { place_ctx.grid_blocks[i][j].blocks[k] = EMPTY_BLOCK_ID; /* Flag for err. check */ @@ -236,12 +234,12 @@ void read_user_pad_loc(const char* pad_loc_file) { int j = ytmp; if (place_ctx.block_locs[bnum].loc.x != OPEN) { - vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), + VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), "Block %s is listed twice in pad file.\n", bname); } if (i < 0 || i > int(device_ctx.grid.width() - 1) || j < 0 || j > int(device_ctx.grid.height() - 1)) { - vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0, + VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, "Block #%zu (%s) location, (%d,%d) is out of range.\n", size_t(bnum), bname, i, j); } @@ -250,27 +248,33 @@ void read_user_pad_loc(const char* pad_loc_file) { place_ctx.block_locs[bnum].loc.z = k; place_ctx.block_locs[bnum].is_fixed = true; - auto type = device_ctx.grid[i][j].type; - if (!is_io_type(type)) { - vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0, - "Attempt to place IO block %s at illegal location (%d, %d).\n", bname, i, j); + auto physical_tile = device_ctx.grid[i][j].type; + auto logical_block = cluster_ctx.clb_nlist.block_type(bnum); + if (!is_tile_compatible(physical_tile, logical_block)) { + VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, + "Attempt to place block %s at illegal location (%d, %d).\n", bname, i, j); } - if (k >= type->capacity || k < 0) { - vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), + if (k >= physical_tile->capacity || k < 0) { + VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), "Block %s subblock number (%d) is out of range.\n", bname, k); } place_ctx.grid_blocks[i][j].blocks[k] = bnum; place_ctx.grid_blocks[i][j].usage++; + constrained_blocks.insert(bnum); + ptr = vtr::fgets(buf, vtr::bufsize, fp); } for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - auto type = pick_best_physical_type(logical_block); - if (is_io_type(type) && place_ctx.block_locs[blk_id].loc.x == OPEN) { - vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0, + auto result = constrained_blocks.find(blk_id); + if (result == constrained_blocks.end()) { + continue; + } + + if (place_ctx.block_locs[blk_id].loc.x == OPEN) { + VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, "IO block %s location was not specified in the pad file.\n", cluster_ctx.clb_nlist.block_name(blk_id).c_str()); } } diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 6631e3f70e8..7060f629e5f 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -282,49 +282,46 @@ static void initial_placement_blocks(int* free_locations, enum e_pad_loc_type pa auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - /* Don't do IOs if the user specifies IOs; we'll read those locations later. */ - if (!(is_io_type(pick_best_physical_type(logical_block)) && pad_loc_type == USER)) { - /* Randomly select a free location of the appropriate type for blk_id. - * We have a linearized list of all the free locations that can - * accommodate a block of that type in free_locations[itype]. - * Choose one randomly and put blk_id there. Then we don't want to pick - * that location again, so remove it from the free_locations array. - */ - - auto type = pick_placement_type(logical_block, 1, free_locations); - - if (type == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place block %s (#%zu); no free locations of type %s (#%d).\n", - cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); - } + /* Randomly select a free location of the appropriate type for blk_id. + * We have a linearized list of all the free locations that can + * accommodate a block of that type in free_locations[itype]. + * Choose one randomly and put blk_id there. Then we don't want to pick + * that location again, so remove it from the free_locations array. + */ + + auto type = pick_placement_type(logical_block, 1, free_locations); - itype = type->index; + if (type == nullptr) { + VPR_FATAL_ERROR(VPR_ERROR_PLACE, + "Initial placement failed.\n" + "Could not place block %s (#%zu); no free locations of type %s (#%d).\n", + cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); + } - t_pl_loc to; - initial_placement_location(free_locations, ipos, itype, to); + itype = type->index; - // Make sure that the position is EMPTY_BLOCK before placing the block down - VTR_ASSERT(place_ctx.grid_blocks[to.x][to.y].blocks[to.z] == EMPTY_BLOCK_ID); + t_pl_loc to; + initial_placement_location(free_locations, ipos, itype, to); - place_ctx.grid_blocks[to.x][to.y].blocks[to.z] = blk_id; - place_ctx.grid_blocks[to.x][to.y].usage++; + // Make sure that the position is EMPTY_BLOCK before placing the block down + VTR_ASSERT(place_ctx.grid_blocks[to.x][to.y].blocks[to.z] == EMPTY_BLOCK_ID); - place_ctx.block_locs[blk_id].loc = to; + place_ctx.grid_blocks[to.x][to.y].blocks[to.z] = blk_id; + place_ctx.grid_blocks[to.x][to.y].usage++; - //Mark IOs as fixed if specifying a (fixed) random placement - if (is_io_type(pick_best_physical_type(logical_block)) && pad_loc_type == RANDOM) { - place_ctx.block_locs[blk_id].is_fixed = true; - } + place_ctx.block_locs[blk_id].loc = to; - /* Ensure randomizer doesn't pick this location again, since it's occupied. Could shift all the - * legal positions in legal_pos to remove the entry (choice) we just used, but faster to - * just move the last entry in legal_pos to the spot we just used and decrement the - * count of free_locations. */ - legal_pos[itype][ipos] = legal_pos[itype][free_locations[itype] - 1]; /* overwrite used block position */ - free_locations[itype]--; + //Mark IOs as fixed if specifying a (fixed) random placement + if (is_io_type(pick_best_physical_type(logical_block)) && pad_loc_type == RANDOM) { + place_ctx.block_locs[blk_id].is_fixed = true; } + + /* Ensure randomizer doesn't pick this location again, since it's occupied. Could shift all the + * legal positions in legal_pos to remove the entry (choice) we just used, but faster to + * just move the last entry in legal_pos to the spot we just used and decrement the + * count of free_locations. */ + legal_pos[itype][ipos] = legal_pos[itype][free_locations[itype] - 1]; /* overwrite used block position */ + free_locations[itype]--; } } @@ -394,6 +391,10 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, place_ctx.block_locs[blk_id].loc = t_pl_loc(); } + if (pad_loc_type == USER) { + read_user_pad_loc(pad_loc_file); + } + initial_placement_pl_macros(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, free_locations); // All the macros are placed, update the legal_pos[][] array @@ -417,10 +418,6 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, initial_placement_blocks(free_locations, pad_loc_type); - if (pad_loc_type == USER) { - read_user_pad_loc(pad_loc_file); - } - /* Restore legal_pos */ load_legal_placement_locations(); From a2cb4770c53d1fa921c6b69ce9d95f11254915b4 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 13 Dec 2019 15:19:17 -0800 Subject: [PATCH 085/107] Update variable name. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/route_timing.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index 22dbf73dd91..29e50551608 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -2107,7 +2107,7 @@ static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, //Pre-heap prune to keep the heap small, by not putting paths which are known to be //sub-optimal (at this point in time) into the heap. VTR_LOGV_DEBUG(f_router_debug, " Adding node %8d to heap from init route tree with cost %g (%s)\n", - next->index, new_next_total_cost, describe_rr_node(next->index).c_str()); + next->index, new_total_cost, describe_rr_node(next->index).c_str()); add_to_heap(next); ++router_stats.heap_pushes; } else { From aef717ce32764726b0f281727f0e86f14dd2fcab Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 21 Nov 2019 09:41:48 -0800 Subject: [PATCH 086/107] Add base cost option that is bounded. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/base/ShowSetup.cpp | 3 +++ vpr/src/base/read_options.cpp | 14 +++++++++++--- vpr/src/base/vpr_types.h | 1 + vpr/src/route/rr_graph_indexed_data.cpp | 17 +++++++++++++++++ 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 05501cc9c71..ac2f324eb92 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -202,6 +202,9 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { case DELAY_NORMALIZED_LENGTH: VTR_LOG("DELAY_NORMALIZED_LENGTH\n"); break; + case DELAY_NORMALIZED_LENGTH_BOUNDED: + VTR_LOG("DELAY_NORMALIZED_LENGTH_BOUNDED\n"); + break; case DELAY_NORMALIZED_FREQUENCY: VTR_LOG("DELAY_NORMALIZED_FREQUENCY\n"); break; diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 5f654445efd..bf602e7035e 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -245,6 +245,8 @@ struct ParseBaseCost { conv_value.set_value(DEMAND_ONLY_NORMALIZED_LENGTH); else if (str == "demand_only") conv_value.set_value(DEMAND_ONLY); + else if (str == "delay_normalized_length_bounded") + conv_value.set_value(DELAY_NORMALIZED_LENGTH_BOUNDED); else { std::stringstream msg; msg << "Invalid conversion from '" << str << "' to e_router_algorithm (expected one of: " << argparse::join(default_choices(), ", ") << ")"; @@ -265,6 +267,8 @@ struct ParseBaseCost { conv_value.set_value("delay_normalized_length_frequency"); else if (val == DEMAND_ONLY_NORMALIZED_LENGTH) conv_value.set_value("demand_only_normalized_length"); + else if (val == DELAY_NORMALIZED_LENGTH_BOUNDED) + conv_value.set_value("delay_normalized_length_bounded"); else { VTR_ASSERT(val == DEMAND_ONLY); conv_value.set_value("demand_only"); @@ -273,7 +277,7 @@ struct ParseBaseCost { } std::vector default_choices() { - return {"demand_only", "demand_only_normalized_length", "delay_normalized", "delay_normalized_length", "delay_normalized_frequency", "delay_normalized_length_frequency"}; + return {"demand_only", "demand_only_normalized_length", "delay_normalized", "delay_normalized_length", "delay_normalized_length_bounded", "delay_normalized_frequency", "delay_normalized_length_frequency"}; } }; @@ -1451,9 +1455,13 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg " to magnitude of typical routing resource delay\n" " * delay_normalized_length: like delay_normalized but\n" " scaled by routing resource length\n" - " * delay_normalized_freqeuncy: like delay_normalized\n" + " * delay_normalized_length_bounded: like delay_normalized but\n" + " scaled by routing resource length. Scaling is normalized\n" + " between 1 to 4, with min lengths getting scaled at 1,\n" + " and max lengths getting scaled at 4.\n" + " * delay_normalized_frequency: like delay_normalized\n" " but scaled inversely by segment type frequency\n" - " * delay_normalized_length_freqeuncy: like delay_normalized\n" + " * delay_normalized_length_frequency: like delay_normalized\n" " but scaled by routing resource length, and inversely\n" " by segment type frequency\n" "(Default: demand_only for breadth-first router,\n" diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index e6c010f7398..be9ea1ef4cd 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -876,6 +876,7 @@ enum e_base_cost_type { DELAY_NORMALIZED_LENGTH, DELAY_NORMALIZED_FREQUENCY, DELAY_NORMALIZED_LENGTH_FREQUENCY, + DELAY_NORMALIZED_LENGTH_BOUNDED, DEMAND_ONLY, DEMAND_ONLY_NORMALIZED_LENGTH }; diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp index 0d8fc853268..2c449d5b95a 100644 --- a/vpr/src/route/rr_graph_indexed_data.cpp +++ b/vpr/src/route/rr_graph_indexed_data.cpp @@ -168,6 +168,14 @@ static void load_rr_indexed_data_base_costs(int nodes_per_chan, size_t total_segments = std::accumulate(rr_segment_counts.begin(), rr_segment_counts.end(), 0u); /* Load base costs for CHANX and CHANY segments */ + float max_length = 0; + float min_length = 1; + if (base_cost_type == DELAY_NORMALIZED_LENGTH_BOUNDED) { + for (index = CHANX_COST_INDEX_START; index < device_ctx.rr_indexed_data.size(); index++) { + float length = (1 / device_ctx.rr_indexed_data[index].inv_length); + max_length = std::max(max_length, length); + } + } //Future Work: Since we can now have wire types which don't connect to IPINs, // perhaps consider lowering cost of wires which connect to IPINs @@ -180,6 +188,15 @@ static void load_rr_indexed_data_base_costs(int nodes_per_chan, } else if (base_cost_type == DELAY_NORMALIZED_LENGTH || base_cost_type == DEMAND_ONLY_NORMALIZED_LENGTH) { device_ctx.rr_indexed_data[index].base_cost = delay_normalization_fac / device_ctx.rr_indexed_data[index].inv_length; + } else if (base_cost_type == DELAY_NORMALIZED_LENGTH_BOUNDED) { + float length = (1 / device_ctx.rr_indexed_data[index].inv_length); + if (max_length != min_length) { + float length_scale = 1.f + 3.f * (length - min_length) / (max_length - min_length); + device_ctx.rr_indexed_data[index].base_cost = delay_normalization_fac * length_scale; + } else { + device_ctx.rr_indexed_data[index].base_cost = delay_normalization_fac; + } + } else if (base_cost_type == DELAY_NORMALIZED_FREQUENCY) { int seg_index = device_ctx.rr_indexed_data[index].seg_index; From 7c943b7f5d89a062596f5c1e4b48c3af60e9acfc Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:43:49 -0800 Subject: [PATCH 087/107] Revert "vpr: Fix formatting" This reverts commit 10967502edb0124a0d8f058fb42d1acde8a76d8b. --- vpr/src/base/atom_netlist_utils.cpp | 3 ++- vpr/src/base/vpr_tatum_error.cpp | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index ea32a2d071b..48b25f05040 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -684,6 +684,7 @@ std::vector find_combinationally_connected_clock_ports(const AtomNet return upstream_ports; } + void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //First we look through the netlist to find LUTs with identity logic functions //we then remove those luts, replacing the net's they drove with the inputs to the @@ -1400,7 +1401,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis AtomBlockId driver_blk = netlist.port_block(driver_port); std::vector upstream_ports; - + if (netlist.block_model(driver_blk)->name == std::string(".names")) { //For .names we allow tracing back through data connections //which allows us to traceback through white-box .names buffers diff --git a/vpr/src/base/vpr_tatum_error.cpp b/vpr/src/base/vpr_tatum_error.cpp index ea106def804..37dfaa448b9 100644 --- a/vpr/src/base/vpr_tatum_error.cpp +++ b/vpr/src/base/vpr_tatum_error.cpp @@ -45,6 +45,7 @@ std::string format_tatum_error(const tatum::Error& error) { } if (error.edge) { + if (timing_ctx.graph) { tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); From ac4e0e1bbc4d1a0d0f655e2bf615db0fcbf53454 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:44:10 -0800 Subject: [PATCH 088/107] Revert "Squashed 'libs/EXTERNAL/libtatum/' changes from ee66714ea..751112a2c" This reverts commit f7bc1618298493a595907bd3145a3f374ee0c66b. --- libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp b/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp index ab46e91ab8e..f897851f52f 100644 --- a/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp +++ b/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp @@ -731,9 +731,8 @@ bool TimingGraph::validate_structure() const { } else if (src_type == NodeType::CPIN) { if( sink_type != NodeType::SOURCE - && sink_type != NodeType::SINK - && sink_type != NodeType::OPIN) { - throw tatum::Error("CPIN nodes should only drive SOURCE, OPIN or SINK nodes", src_node, out_edge); + && sink_type != NodeType::SINK) { + throw tatum::Error("CPIN nodes should only drive SOURCE or SINK nodes", src_node, out_edge); } if(sink_type == NodeType::SOURCE && out_edge_type != EdgeType::PRIMITIVE_CLOCK_LAUNCH) { From 3ca4a4965df2bd34cf002c7fe663031df8a6d1e9 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:44:16 -0800 Subject: [PATCH 089/107] Revert "vpr: Allow creation of clock to output pin edges in the timing graph" This reverts commit 440e6b1baa04e889f11edd4259471a88291e1fa8. --- vpr/src/timing/PreClusterDelayCalculator.h | 3 +-- vpr/src/timing/atom_delay_calc.inl | 6 ++--- vpr/src/timing/timing_graph_builder.cpp | 30 +--------------------- 3 files changed, 4 insertions(+), 35 deletions(-) diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index 54e97e66a1a..24a1b3a5884 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -101,9 +101,8 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { VTR_ASSERT_MSG((src_node_type == tatum::NodeType::IPIN && sink_node_type == tatum::NodeType::OPIN) || (src_node_type == tatum::NodeType::SOURCE && sink_node_type == tatum::NodeType::SINK) || (src_node_type == tatum::NodeType::SOURCE && sink_node_type == tatum::NodeType::OPIN) - || (src_node_type == tatum::NodeType::CPIN && sink_node_type == tatum::NodeType::OPIN) || (src_node_type == tatum::NodeType::IPIN && sink_node_type == tatum::NodeType::SINK), - "Primitive combinational delay must be between {SOURCE, IPIN} and {SINK, OPIN}, or CPIN/OPIN"); + "Primitive combinational delay must be between {SOURCE, IPIN} and {SINK, OPIN}"); //Primitive internal combinational delay AtomPinId input_pin = netlist_lookup_.tnode_atom_pin(src_node); diff --git a/vpr/src/timing/atom_delay_calc.inl b/vpr/src/timing/atom_delay_calc.inl index ec32aa9a361..407602c99f9 100644 --- a/vpr/src/timing/atom_delay_calc.inl +++ b/vpr/src/timing/atom_delay_calc.inl @@ -10,10 +10,8 @@ inline AtomDelayCalc::AtomDelayCalc(const AtomNetlist& netlist, const AtomLookup inline float AtomDelayCalc::atom_combinational_delay(const AtomPinId src_pin, const AtomPinId sink_pin, const DelayType delay_type) const { VTR_ASSERT_MSG(netlist_.pin_block(src_pin) == netlist_.pin_block(sink_pin), "Combinational primitive delay must be between pins on the same block"); - auto src_pin_type = netlist_.port_type(netlist_.pin_port(src_pin)); - auto sink_pin_type = netlist_.port_type(netlist_.pin_port(sink_pin)); - VTR_ASSERT_MSG((src_pin_type == PortType::INPUT && sink_pin_type == PortType::OUTPUT) - || (src_pin_type == PortType::CLOCK && sink_pin_type == PortType::OUTPUT), + VTR_ASSERT_MSG( netlist_.port_type(netlist_.pin_port(src_pin)) == PortType::INPUT + && netlist_.port_type(netlist_.pin_port(sink_pin)) == PortType::OUTPUT, "Combinational connections must go from primitive input to output"); //Determine the combinational delay from the pb_graph_pin. diff --git a/vpr/src/timing/timing_graph_builder.cpp b/vpr/src/timing/timing_graph_builder.cpp index 4d4ac33be99..86ff555711a 100644 --- a/vpr/src/timing/timing_graph_builder.cpp +++ b/vpr/src/timing/timing_graph_builder.cpp @@ -267,7 +267,7 @@ void TimingGraphBuilder::add_block_to_timing_graph(const AtomBlockId blk) { } } - //Connect the combinational edges from input pins + //Connect the combinational edges for (AtomPinId src_pin : netlist_.block_input_pins(blk)) { //Combinational edges go between IPINs and OPINs for combinational blocks //and between the internal SOURCEs and SINKS for sequential blocks @@ -327,34 +327,6 @@ void TimingGraphBuilder::add_block_to_timing_graph(const AtomBlockId blk) { } } } - - //Connect the combinational edges from clock pins - // - //These are typically used to represent clock buffers - for (AtomPinId src_clock_pin : netlist_.block_clock_pins(blk)) { - NodeId src_tnode = netlist_lookup_.atom_pin_tnode(src_clock_pin, BlockTnode::EXTERNAL); - - if (!src_tnode) continue; - - //Look-up the combinationally connected sink ports name on the port model - AtomPortId src_port = netlist_.pin_port(src_clock_pin); - const t_model_ports* model_port = netlist_.port_model(src_port); - - for (const std::string& sink_port_name : model_port->combinational_sink_ports) { - AtomPortId sink_port = netlist_.find_port(blk, sink_port_name); - if (!sink_port) continue; //Port may not be connected - - //We now need to create edges between the source pin, and all the pins in the - //output port - for (AtomPinId sink_pin : netlist_.port_pins(sink_port)) { - //Get the tnode of the sink - NodeId sink_tnode = netlist_lookup_.atom_pin_tnode(sink_pin, BlockTnode::EXTERNAL); - - tg_->add_edge(tatum::EdgeType::PRIMITIVE_COMBINATIONAL, src_tnode, sink_tnode); - VTR_LOG("Adding edge from '%s' (%zu) -> '%s' (%zu)\n", netlist_.pin_name(src_clock_pin).c_str(), size_t(src_tnode), netlist_.pin_name(sink_pin).c_str(), size_t(sink_tnode)); - } - } - } } void TimingGraphBuilder::add_net_to_timing_graph(const AtomNetId net) { From 859fab6c43f8c69d222d480020faf3f9cf2b21a0 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:44:18 -0800 Subject: [PATCH 090/107] Revert "vpr: Fix segfault when reporting errors with no timing graph" This reverts commit bed3849427d1fcaec7c466a8326a30232278323b. --- vpr/src/base/vpr_tatum_error.cpp | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/vpr/src/base/vpr_tatum_error.cpp b/vpr/src/base/vpr_tatum_error.cpp index 37dfaa448b9..61504daa8a5 100644 --- a/vpr/src/base/vpr_tatum_error.cpp +++ b/vpr/src/base/vpr_tatum_error.cpp @@ -45,27 +45,24 @@ std::string format_tatum_error(const tatum::Error& error) { } if (error.edge) { + tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); + tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); - if (timing_ctx.graph) { - tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); - tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); + AtomPinId src_pin = atom_ctx.lookup.tnode_atom_pin(src_node); + AtomPinId sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_node); - AtomPinId src_pin = atom_ctx.lookup.tnode_atom_pin(src_node); - AtomPinId sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_node); + if (src_pin && sink_pin) { + msg += "Between netlist pins "; - if (src_pin && sink_pin) { - msg += "Between netlist pins "; + msg += "'" + atom_ctx.nlist.pin_name(src_pin) + "' -> '" + atom_ctx.nlist.pin_name(sink_pin) + "'"; - msg += "'" + atom_ctx.nlist.pin_name(src_pin) + "' -> '" + atom_ctx.nlist.pin_name(sink_pin) + "'"; - - AtomNetId src_net = atom_ctx.nlist.pin_net(src_pin); - AtomNetId sink_net = atom_ctx.nlist.pin_net(sink_pin); - if (src_net && src_net == sink_net) { - msg += " via net '" + atom_ctx.nlist.net_name(src_net) + "'"; - } - - msg += ", "; + AtomNetId src_net = atom_ctx.nlist.pin_net(src_pin); + AtomNetId sink_net = atom_ctx.nlist.pin_net(sink_pin); + if (src_net && src_net == sink_net) { + msg += " via net '" + atom_ctx.nlist.net_name(src_net) + "'"; } + + msg += ", "; } msg += "Timing Graph Edge: " + std::to_string(size_t(error.edge)); From 72f87b50427257ca4f0019153fbe1be5ecdb725f Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:45:49 -0800 Subject: [PATCH 091/107] Revert "vpr: Improve control over clock tracing" This reverts commit 4d1052d5566dcc0659e0a2bd13f2fec48cf6076c. --- vpr/src/base/atom_netlist_utils.cpp | 42 +++-------------------------- 1 file changed, 4 insertions(+), 38 deletions(-) diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index 48b25f05040..ca4f0ee441f 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -29,9 +29,7 @@ int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomB //Returns the set of input ports which are combinationally connected to output_port std::vector find_combinationally_connected_input_ports(const AtomNetlist& netlist, AtomPortId output_port); -//Returns the set of clock ports which are combinationally connected to output_port -std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port); - +std::vector identify_buffer_luts(const AtomNetlist& netlist); bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk); bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); @@ -662,29 +660,6 @@ std::vector find_combinationally_connected_input_ports(const AtomNet return upstream_ports; } -std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port) { - std::vector upstream_ports; - - VTR_ASSERT(netlist.port_type(output_port) == PortType::OUTPUT); - - std::string out_port_name = netlist.port_name(output_port); - - AtomBlockId blk = netlist.port_block(output_port); - - //Look through each block input port to find those which are combinationally connected to the output port - for (AtomPortId clock_port : netlist.block_clock_ports(blk)) { - const t_model_ports* clock_model_port = netlist.port_model(clock_port); - for (const std::string& sink_port_name : clock_model_port->combinational_sink_ports) { - if (sink_port_name == out_port_name) { - upstream_ports.push_back(clock_port); - } - } - } - - return upstream_ports; -} - - void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //First we look through the netlist to find LUTs with identity logic functions //we then remove those luts, replacing the net's they drove with the inputs to the @@ -1398,18 +1373,8 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis for (auto clk_net : prev_clock_nets) { AtomPinId driver_pin = netlist.net_driver(clk_net); AtomPortId driver_port = netlist.pin_port(driver_pin); - AtomBlockId driver_blk = netlist.port_block(driver_port); - - std::vector upstream_ports; - - if (netlist.block_model(driver_blk)->name == std::string(".names")) { - //For .names we allow tracing back through data connections - //which allows us to traceback through white-box .names buffers - upstream_ports = find_combinationally_connected_input_ports(netlist, driver_port); - } else { - //For black boxes, we only trace back through inputs marked as clocks - upstream_ports = find_combinationally_connected_clock_ports(netlist, driver_port); - } + + std::vector upstream_ports = find_combinationally_connected_input_ports(netlist, driver_port); if (upstream_ports.empty()) { //This net is a root net of a clock, keep it @@ -1426,6 +1391,7 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis VTR_ASSERT(upstream_net); + AtomBlockId driver_blk = netlist.port_block(driver_port); VTR_LOG_WARN("Assuming clocks may propagate through %s (%s) from pin %s to %s (assuming a non-inverting buffer).\n", netlist.block_name(driver_blk).c_str(), netlist.block_model(driver_blk)->name, netlist.pin_name(upstream_pin).c_str(), netlist.pin_name(driver_pin).c_str()); From 0a4b0f266a70c089f3976edc8cf112f3a35a0a62 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:46:01 -0800 Subject: [PATCH 092/107] Revert "archfpga: Improve error reporting for tile/block pin mismatches" This reverts commit 502be5a4c669e5b6083d1d3d75ea0b57d2e3ae5c. --- libs/libarchfpga/src/read_xml_arch_file.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 32381facab6..cb4022a27b6 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -4907,8 +4907,7 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t if (pb_type->num_pins != (int)pin_direct_mapping.size()) { archfpga_throw(__FILE__, __LINE__, - "Logical block (%s) and Physical tile (%s) have a different number of ports.\n", - logical_block->name, physical_tile->name); + "Logical and Physical types have a different number of ports.\n"); } for (auto pin_map : pin_direct_mapping) { @@ -4922,8 +4921,7 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t || tile_port->num_pins != block_port->num_pins || tile_port->equivalent != block_port->equivalent) { archfpga_throw(__FILE__, __LINE__, - "Logical block (%s) and Physical tile (%s) do not have equivalent port specifications.\n", - logical_block->name, physical_tile->name); + "Logical and Physical types do not have equivalent port specifications.\n"); } } } From 629b039f738898278310a424bbf1816b0fd416ad Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 6 Nov 2019 14:46:06 -0800 Subject: [PATCH 093/107] Revert "vpr: Add support for tracing clock nets through general logic" This reverts commit 5007035d3389c84b7506d050e7b2b01bd9017a26. --- vpr/src/base/atom_netlist_utils.cpp | 45 +++++++---------------------- 1 file changed, 10 insertions(+), 35 deletions(-) diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index ca4f0ee441f..bd1af72f348 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -1355,7 +1355,7 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) return clock_nets; } -//Finds all logical clock drivers in the netlist (by back-tracing through logic) +//Finds all logical clock drivers in the netlist std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist) { auto clock_nets = find_netlist_physical_clock_nets(netlist); @@ -1364,53 +1364,28 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis //However, some of them may be the same logical clock (e.g. if there are //buffers between them). Here we trace-back through any clock buffers //to find the true source - size_t assumed_buffer_count = 0; std::set prev_clock_nets; while (prev_clock_nets != clock_nets) { //Still tracing back prev_clock_nets = clock_nets; clock_nets.clear(); for (auto clk_net : prev_clock_nets) { - AtomPinId driver_pin = netlist.net_driver(clk_net); - AtomPortId driver_port = netlist.pin_port(driver_pin); + auto driver_block = netlist.net_driver_block(clk_net); - std::vector upstream_ports = find_combinationally_connected_input_ports(netlist, driver_port); + if (is_buffer(netlist, driver_block)) { + //Driver is a buffer lut, use it's input net + auto input_pins = netlist.block_input_pins(driver_block); + VTR_ASSERT(input_pins.size() == 1); + auto input_pin = *input_pins.begin(); - if (upstream_ports.empty()) { - //This net is a root net of a clock, keep it - clock_nets.insert(clk_net); + auto input_net = netlist.pin_net(input_pin); + clock_nets.insert(input_net); } else { - //Trace the clock back through any combinational logic - // - // We are assuming that the combinational connections are independent and non-inverting. - // If this is not the case, it is up to the end-user to specify the clocks explicitly - // at the intermediate pins in the netlist. - for (AtomPortId upstream_port : upstream_ports) { - for (AtomPinId upstream_pin : netlist.port_pins(upstream_port)) { - AtomNetId upstream_net = netlist.pin_net(upstream_pin); - - VTR_ASSERT(upstream_net); - - AtomBlockId driver_blk = netlist.port_block(driver_port); - VTR_LOG_WARN("Assuming clocks may propagate through %s (%s) from pin %s to %s (assuming a non-inverting buffer).\n", - netlist.block_name(driver_blk).c_str(), netlist.block_model(driver_blk)->name, - netlist.pin_name(upstream_pin).c_str(), netlist.pin_name(driver_pin).c_str()); - - clock_nets.insert(upstream_net); - ++assumed_buffer_count; - } - } + clock_nets.insert(clk_net); } } } - if (assumed_buffer_count > 0) { - VTR_LOG_WARN( - "Assumed %zu netlist logic connections may be clock buffers. " - "To override this behaviour explicitly create clocks at the appropriate netlist pins.\n", - assumed_buffer_count); - } - //Extract the net drivers std::set clock_drivers; for (auto net : clock_nets) { From 115b84a237e03ef77281d4e5715e1c9e95c1086e Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 6 Sep 2019 13:44:04 -0700 Subject: [PATCH 094/107] Refactor router heap to use heap approximation. The heap approximation doesn't precisely follow the heap property, but offers an approximation that is sufficent for the router's purpose. This new data structure is faster to clear, faster during route time, and results in better router behavior because it provides some randomness on elements with costs within ~1%. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/bucket.cpp | 152 ++++++++++++++++ vpr/src/route/bucket.h | 322 +++++++++++++++++++++++++++++++++ vpr/src/route/route_common.cpp | 278 ++-------------------------- vpr/src/route/route_common.h | 70 +------ 4 files changed, 487 insertions(+), 335 deletions(-) create mode 100644 vpr/src/route/bucket.cpp create mode 100644 vpr/src/route/bucket.h diff --git a/vpr/src/route/bucket.cpp b/vpr/src/route/bucket.cpp new file mode 100644 index 00000000000..e531ba8699a --- /dev/null +++ b/vpr/src/route/bucket.cpp @@ -0,0 +1,152 @@ +#include "bucket.h" + +std::vector BucketItems::heap_items_; +size_t BucketItems::alloced_items_ = 0; +int BucketItems::num_heap_allocated_ = 0; +t_heap* BucketItems::heap_free_head_ = nullptr; +vtr::t_chunk BucketItems::heap_ch_; + +void Bucket::init(const DeviceGrid& grid) { + vtr::free(heap_); + heap_ = nullptr; + + heap_size_ = (grid.width() - 1) * (grid.height() - 1); + heap_ = (t_heap**)vtr::malloc(heap_size_ * sizeof(t_heap*)); + memset(heap_, 0, heap_size_ * sizeof(t_heap*)); + + heap_head_ = std::numeric_limits::max(); + heap_tail_ = 0; +} + +void Bucket::free() { + vtr::free(heap_); + heap_ = nullptr; +} + +void Bucket::expand(size_t required_number_of_buckets) { + auto old_size = heap_size_; + heap_size_ = required_number_of_buckets * 2; + + heap_ = (t_heap**)vtr::realloc((void*)(heap_), + heap_size_ * sizeof(t_heap*)); + std::fill(heap_ + old_size, heap_ + heap_size_, nullptr); +} + +void Bucket::verify() { + for (size_t bucket = heap_head_; bucket <= heap_tail_; ++bucket) { + for (t_heap* data = heap_[bucket]; data != nullptr; + data = data->next_bucket) { + VTR_ASSERT(data->cost > 0 && ((size_t)cost_to_int(data->cost)) == bucket); + } + } +} + +size_t Bucket::seed_ = 1231; +t_heap** Bucket::heap_ = nullptr; +size_t Bucket::heap_size_ = 0; +size_t Bucket::heap_head_ = std::numeric_limits::max(); +size_t Bucket::heap_tail_ = 0; + +void Bucket::clear() { + if (heap_head_ != std::numeric_limits::max()) { + std::fill(heap_ + heap_head_, heap_ + heap_tail_ + 1, nullptr); + } + heap_head_ = std::numeric_limits::max(); + heap_tail_ = 0; +} + +void Bucket::push(t_heap* hptr) { + float cost = hptr->cost; + if (!std::isfinite(cost)) { + return; + } + + //heap_::verify_extract_top(); + + // Which bucket should this go into? + auto int_cost = cost_to_int(cost); + + if (int_cost < 0) { + VTR_LOG_WARN("Cost is negative? cost = %g\n", cost); + int_cost = 0; + } + + size_t uint_cost = int_cost; + + // Is that bucket allocated? + if (uint_cost >= heap_size_) { + // Not enough buckets! + expand(uint_cost); + } + + // Insert into bucket + auto* prev = heap_[uint_cost]; + hptr->next_bucket = prev; + heap_[uint_cost] = hptr; + + if (uint_cost < heap_head_) { + heap_head_ = uint_cost; + } + if (uint_cost > heap_tail_) { + heap_tail_ = uint_cost; + } + + //heap_::verify_extract_top(); +} + +t_heap* Bucket::pop() { + auto heap_head = heap_head_; + auto heap_tail = heap_tail_; + t_heap** heap = heap_; + + // Check empty + if (heap_head == std::numeric_limits::max()) { + return nullptr; + } + + // Find first non-empty bucket + + // Randomly remove element + size_t count = fast_rand() % 4; + + t_heap* prev = nullptr; + t_heap* next = heap[heap_head]; + for (size_t i = 0; i < count && next->next_bucket != nullptr; ++i) { + prev = next; + next = prev->next_bucket; + } + + if (prev == nullptr) { + heap[heap_head] = next->next_bucket; + } else { + prev->next_bucket = next->next_bucket; + } + + // Update first non-empty bucket if bucket is now empty + if (heap[heap_head] == nullptr) { + heap_head += 1; + while (heap_head <= heap_tail && heap[heap_head] == nullptr) { + heap_head += 1; + } + + if (heap_head > heap_tail) { + heap_head = std::numeric_limits::max(); + } + + heap_head_ = heap_head; + } + + return next; +} + +void Bucket::print() { + for (size_t i = heap_head_; i < heap_tail_; ++i) { + if (heap_[heap_head_] != nullptr) { + VTR_LOG("B:%d ", i); + for (auto* item = heap_[i]; item != nullptr; item = item->next_bucket) { + VTR_LOG(" %e", item->cost); + } + } + } + VTR_LOG("\n"); +} diff --git a/vpr/src/route/bucket.h b/vpr/src/route/bucket.h new file mode 100644 index 00000000000..aad509a1ccc --- /dev/null +++ b/vpr/src/route/bucket.h @@ -0,0 +1,322 @@ +#ifndef _BUCKET_ITEMS_H_ +#define _BUCKET_ITEMS_H_ + +#include + +#include "netlist_fwd.h" +#include "physical_types.h" +#include "vtr_memory.h" +#include "globals.h" + +/* Used by the heap as its fundamental data structure. + * Each heap element represents a partial route. + * + * cost: The cost used to sort heap. + * For the timing-driven router this is the backward_path_cost + + * expected cost to the target. + * For the breadth-first router it is the node cost to reach this + * point. + * + * backward_path_cost: Used only by the timing-driven router. The "known" + * cost of the path up to and including this node. + * In this case, the .cost member contains not only + * the known backward cost but also an expected cost + * to the target. + * + * R_upstream: Used only by the timing-driven router. Stores the upstream + * resistance to ground from this node, including the + * resistance of the node itself (device_ctx.rr_nodes[index].R). + * + * index: The RR node index associated with the costs/R_upstream values + * + * u.prev.node: The previous node used to reach the current 'index' node + * u.prev.next: The edge from u.prev.node used to reach the current 'index' node + * + * u.next: pointer to the next s_heap structure in the free + * linked list. Not used when on the heap. + * + */ +struct t_heap { + float cost = 0.; + float backward_path_cost = 0.; + float R_upstream = 0.; + + int index = OPEN; + + struct t_prev { + int node; + int edge; + }; + + union { + t_heap* next; + t_prev prev; + } u; + + // Next pointer for Bucket linked list. + t_heap* next_bucket; +}; + +// Allocator for t_heap items. +// +// Supports fast clearing of the items, under the assumption that when clear +// is invoked, all outstanding references can be dropped. This should be true +// between net routing, and avoids the need to rebuild the free list between +// nets. +class BucketItems { + public: + // Returns all allocated items to be available for allocation. + // + // This operation is only safe if all outstanding references are discarded. + // This is true when the router is starting on a new net, as all outstanding + // items should be in the bucket, which is cleared at the start of routing. + static void clear() { + heap_free_head_ = nullptr; + num_heap_allocated_ = 0; + alloced_items_ = 0; + } + + // Iterators over all items ever allocated. This is not the list of alive + // items, but can be used for fast invalidation if needed. + static std::vector::iterator begin() { + return heap_items_.begin(); + } + static std::vector::iterator end() { + return heap_items_.end(); + } + + // Deallocate all items. Outstanding references to items will become + // invalid. + static void free() { + // Free each individual heap item. + for (auto* item : heap_items_) { + vtr::chunk_delete(item, &heap_ch_); + } + heap_items_.clear(); + + /*free the memory chunks that were used by heap and linked f pointer */ + free_chunk_memory(&heap_ch_); + } + + // Allocate an item. This may cause a dynamic allocation if no previously + // allocated items are available. + static t_heap* alloc_item() { + t_heap* temp_ptr; + if (alloced_items_ < heap_items_.size()) { + temp_ptr = heap_items_[alloced_items_++]; + } else { + if (heap_free_head_ == nullptr) { /* No elements on the free list */ + heap_free_head_ = vtr::chunk_new(&heap_ch_); + heap_items_.push_back(heap_free_head_); + alloced_items_ += 1; + } + + temp_ptr = heap_free_head_; + heap_free_head_ = heap_free_head_->u.next; + } + + num_heap_allocated_++; + + return temp_ptr; + } + + // Return a free'd item to be reallocated. + static void free_item(t_heap* hptr) { + hptr->u.next = heap_free_head_; + heap_free_head_ = hptr; + num_heap_allocated_--; + } + + // Number of outstanding allocations. + static int num_heap_allocated() { + return num_heap_allocated_; + } + + private: + /* Vector of all items ever allocated. Used for full item iteration and + * for reuse after a `clear` invocation. */ + static std::vector heap_items_; + + /* Tracks how many items from heap_items_ are in use. */ + static size_t alloced_items_; + + /* Number of outstanding allocated items. */ + static int num_heap_allocated_; + + /* For managing my own list of currently free heap data structures. */ + static t_heap* heap_free_head_; + + /* For keeping track of the sudo malloc memory for the heap*/ + static vtr::t_chunk heap_ch_; +}; + +inline void free_heap_data(t_heap* hptr) { + BucketItems::free_item(hptr); +} + +inline t_heap* +alloc_heap_data() { + //Extract the head + t_heap* temp_ptr = BucketItems::alloc_item(); + + //Reset + temp_ptr->u.next = nullptr; + temp_ptr->next_bucket = nullptr; + temp_ptr->cost = 0.; + temp_ptr->backward_path_cost = 0.; + temp_ptr->R_upstream = 0.; + temp_ptr->index = OPEN; + temp_ptr->u.prev.node = NO_PREVIOUS; + temp_ptr->u.prev.edge = NO_PREVIOUS; + return (temp_ptr); +} + +// Prority queue approximation using cost buckets and randomization. +// +// The Bucket contains linked lists for costs at kConvFactor intervals. Given +// that cost is approximately delay, each bucket contains ~1 picosecond (1e12) +// worth items. +// +// Items are pushed into the linked list that matches their cost [0, 1) +// picosecond. When popping the Bucket, a random item in the cheapest bucket +// with items is returned. This randomization exists to prevent the router +// from following identical paths when operating with identical costs. +// Consider two parallel paths to a node. +class Bucket { + public: + Bucket() {} + + // Allocate initial buckets for items. + static void init(const DeviceGrid& grid); + + // Deallocate memory for buckets. This does NOT call + // BucketItems::free_item on contained items. + static void free(); + + // Empties all buckets of items. + // + // This does NOT call BucketItems::free_item on contained items. The + // assumption is that when Bucket::clear is called, BucketItems::clear + // is also called. + static void clear(); + + // Push an item onto a bucket. + static void push(t_heap* hptr); + + // Pop an item from the cheapest non-empty bucket. + // + // Returns nullptr if empty. + static t_heap* pop(); + + // True if all buckets are empty. + static bool empty() { + return heap_head_ == std::numeric_limits::max(); + } + + // Sanity check state of buckets (e.g. all items within each bucket have + // a cost that matches their bucket index. + static void verify(); + + // Print items contained in buckets. + static void print(); + + private: + // Factor used to convert cost from float to int. Should be scaled to + // enable sufficent precision in bucketting. + static constexpr float kConvFactor = 1e12; + + // Convert cost from float to integer bucket id. + static int cost_to_int(float cost) { + return (int)(cost * kConvFactor); + } + + // Simple fast random function used for randomizing item selection on pop. + static size_t fast_rand() { + seed_ = (0x234ab32a1 * seed_) ^ (0x12acbade); + return seed_; + } + + // Expand the number of buckets. + // + // Only call if insufficient bucets exist. + static void expand(size_t required_number_of_buckets); + + static size_t seed_; /* Seed for fast_rand, should be non-zero */ + + static t_heap** heap_; /* Buckets for linked lists*/ + static size_t heap_size_; /* Number of buckets */ + static size_t heap_head_; /* First non-empty bucket */ + static size_t heap_tail_; /* Last non-empty bucket */ +}; + +inline bool is_empty_heap() { + return Bucket::empty(); +} + +inline void init_heap(const DeviceGrid& grid) { + Bucket::init(grid); +} + +inline void empty_heap() { + BucketItems::clear(); + Bucket::clear(); +} + +inline void add_to_heap(t_heap* hptr) { + Bucket::push(hptr); +} + +inline t_heap* get_heap_head() { + return Bucket::pop(); +} + +namespace heap_ { + +inline void push_back(t_heap* const hptr) { + add_to_heap(hptr); +} + +inline bool is_valid() { + return true; +} + +// extract every element and print it +inline void pop_heap() { + while (!is_empty_heap()) + VTR_LOG("%e ", get_heap_head()->cost); + VTR_LOG("\n"); +} + +inline void build_heap() { +} + +inline void verify_extract_top() { + Bucket::verify(); +} + +inline void print_heap() { + Bucket::print(); +} + +inline void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream) { + /* Puts an rr_node on the heap with the same condition as node_to_heap, + * but do not fix heap property yet as that is more efficiently done from + * bottom up with build_heap */ + + auto& route_ctx = g_vpr_ctx.routing(); + if (total_cost >= route_ctx.rr_node_route_inf[inode].path_cost) + return; + + t_heap* hptr = alloc_heap_data(); + hptr->index = inode; + hptr->cost = total_cost; + hptr->u.prev.node = prev_node; + hptr->u.prev.edge = prev_edge; + hptr->backward_path_cost = backward_path_cost; + hptr->R_upstream = R_upstream; + push_back(hptr); +} + +} // namespace heap_ + +#endif /* _BUCKET_ITEMS_H_ */ diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 6204dad984b..45ba72bbb2c 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -44,22 +44,12 @@ struct t_trace_branch { /**************** Static variables local to route_common.c ******************/ -static t_heap** heap; /* Indexed from [1..heap_size] */ -static int heap_size; /* Number of slots in the heap array */ -static int heap_tail; /* Index of first unused slot in the heap array */ - -/* For managing my own list of currently free heap data structures. */ -static t_heap* heap_free_head = nullptr; -/* For keeping track of the sudo malloc memory for the heap*/ -static vtr::t_chunk heap_ch; - /* For managing my own list of currently free trace data structures. */ static t_trace* trace_free_head = nullptr; /* For keeping track of the sudo malloc memory for the trace*/ static vtr::t_chunk trace_ch; static int num_trace_allocated = 0; /* To watch for memory leaks. */ -static int num_heap_allocated = 0; static int num_linked_f_pointer_allocated = 0; /* The numbering relation between the channels and clbs is: * @@ -467,17 +457,6 @@ void pathfinder_update_cost(float pres_fac, float acc_fac) { } } -void init_heap(const DeviceGrid& grid) { - if (heap != nullptr) { - vtr::free(heap + 1); - heap = nullptr; - } - heap_size = (grid.width() - 1) * (grid.height() - 1); - heap = (t_heap**)vtr::malloc(heap_size * sizeof(t_heap*)); - heap--; /* heap stores from [1..heap_size] */ - heap_tail = 1; -} - /* Call this before you route any nets. It frees any old traceback and * * sets the list of rr_nodes touched to empty. */ void init_route_structs(int bb_factor) { @@ -493,7 +472,7 @@ void init_route_structs(int bb_factor) { route_ctx.trace.resize(cluster_ctx.clb_nlist.nets().size()); route_ctx.trace_nodes.resize(cluster_ctx.clb_nlist.nets().size()); - init_heap(device_ctx.grid); + Bucket::init(device_ctx.grid); //Various look-ups route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices); @@ -505,7 +484,7 @@ void init_route_structs(int bb_factor) { /* Check that things that should have been emptied after the last routing * * really were. */ - if (heap_tail != 1) { + if (!is_empty_heap()) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in init_route_structs. Heap is not empty.\n"); } @@ -953,36 +932,12 @@ void free_route_structs() { * final routing result is not freed. */ auto& route_ctx = g_vpr_ctx.mutable_routing(); - if (heap != nullptr) { - //Free the individiaul heap elements (calls destructors) - for (int i = 1; i < num_heap_allocated; i++) { - VTR_LOG("Freeing %p\n", heap[i]); - vtr::chunk_delete(heap[i], &heap_ch); - } - - // coverity[offset_free : Intentional] - free(heap + 1); - - heap = nullptr; /* Defensive coding: crash hard if I use these. */ - } - - if (heap_free_head != nullptr) { - t_heap* curr = heap_free_head; - while (curr) { - t_heap* tmp = curr; - curr = curr->u.next; + BucketItems::free(); + Bucket::free(); - vtr::chunk_delete(tmp, &heap_ch); - } - - heap_free_head = nullptr; - } if (route_ctx.route_bb.size() != 0) { route_ctx.route_bb.clear(); } - - /*free the memory chunks that were used by heap and linked f pointer */ - free_chunk_memory(&heap_ch); } /* Frees the data structures needed to save a routing. */ @@ -1200,227 +1155,18 @@ void add_to_mod_list(int inode, std::vector& modified_rr_node_inf) { } } -namespace heap_ { -size_t parent(size_t i); -size_t left(size_t i); -size_t right(size_t i); -size_t size(); -void expand_heap_if_full(); - -size_t parent(size_t i) { return i >> 1; } -// child indices of a heap -size_t left(size_t i) { return i << 1; } -size_t right(size_t i) { return (i << 1) + 1; } -size_t size() { return static_cast(heap_tail - 1); } // heap[0] is not valid element - -// make a heap rooted at index i by **sifting down** in O(lgn) time -void sift_down(size_t hole) { - t_heap* head{heap[hole]}; - size_t child{left(hole)}; - while ((int)child < heap_tail) { - if ((int)child + 1 < heap_tail && heap[child + 1]->cost < heap[child]->cost) - ++child; - if (heap[child]->cost < head->cost) { - heap[hole] = heap[child]; - hole = child; - child = left(child); - } else - break; - } - heap[hole] = head; -} - -// runs in O(n) time by sifting down; the least work is done on the most elements: 1 swap for bottom layer, 2 swap for 2nd, ... lgn swap for top -// 1*(n/2) + 2*(n/4) + 3*(n/8) + ... + lgn*1 = 2n (sum of i/2^i) -void build_heap() { - // second half of heap are leaves - for (size_t i = heap_tail >> 1; i != 0; --i) - sift_down(i); -} - -// O(lgn) sifting up to maintain heap property after insertion (should sift down when building heap) -void sift_up(size_t leaf, t_heap* const node) { - while ((leaf > 1) && (node->cost < heap[parent(leaf)]->cost)) { - // sift hole up - heap[leaf] = heap[parent(leaf)]; - leaf = parent(leaf); - } - heap[leaf] = node; -} - -void expand_heap_if_full() { - if (heap_tail > heap_size) { /* Heap is full */ - heap_size *= 2; - heap = (t_heap**)vtr::realloc((void*)(heap + 1), - heap_size * sizeof(t_heap*)); - heap--; /* heap goes from [1..heap_size] */ - } -} - -// adds an element to the back of heap and expand if necessary, but does not maintain heap property -void push_back(t_heap* const hptr) { - expand_heap_if_full(); - heap[heap_tail] = hptr; - ++heap_tail; -} - -void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream) { - /* Puts an rr_node on the heap with the same condition as node_to_heap, - * but do not fix heap property yet as that is more efficiently done from - * bottom up with build_heap */ - - auto& route_ctx = g_vpr_ctx.routing(); - if (total_cost >= route_ctx.rr_node_route_inf[inode].path_cost) - return; - - t_heap* hptr = alloc_heap_data(); - hptr->index = inode; - hptr->cost = total_cost; - hptr->u.prev.node = prev_node; - hptr->u.prev.edge = prev_edge; - hptr->backward_path_cost = backward_path_cost; - hptr->R_upstream = R_upstream; - push_back(hptr); -} - -bool is_valid() { - for (size_t i = 1; (int)i <= heap_tail >> 1; ++i) { - if ((int)left(i) < heap_tail && heap[left(i)]->cost < heap[i]->cost) return false; - if ((int)right(i) < heap_tail && heap[right(i)]->cost < heap[i]->cost) return false; - } - return true; -} -// extract every element and print it -void pop_heap() { - while (!is_empty_heap()) - VTR_LOG("%e ", get_heap_head()->cost); - VTR_LOG("\n"); -} -// print every element; not necessarily in order for minheap -void print_heap() { - for (int i = 1; i> 1; ++i) - VTR_LOG("(%e %e %e) ", heap[i]->cost, heap[left(i)]->cost, heap[right(i)]->cost); - VTR_LOG("\n"); -} -// verify correctness of extract top by making a copy, sorting it, and iterating it at the same time as extraction -void verify_extract_top() { - constexpr float float_epsilon = 1e-20; - std::cout << "copying heap\n"; - std::vector heap_copy{heap + 1, heap + heap_tail}; - // sort based on cost with cheapest first - VTR_ASSERT(heap_copy.size() == size()); - std::sort(begin(heap_copy), end(heap_copy), - [](const t_heap* a, const t_heap* b) { - return a->cost < b->cost; - }); - std::cout << "starting to compare top elements\n"; - size_t i = 0; - while (!is_empty_heap()) { - while (heap_copy[i]->index == OPEN) - ++i; // skip the ones that won't be extracted - auto top = get_heap_head(); - if (abs(top->cost - heap_copy[i]->cost) > float_epsilon) - std::cout << "mismatch with sorted " << top << '(' << top->cost << ") " << heap_copy[i] << '(' << heap_copy[i]->cost << ")\n"; - ++i; - } - if (i != heap_copy.size()) - std::cout << "did not finish extracting: " << i << " vs " << heap_copy.size() << std::endl; - else - std::cout << "extract top working as intended\n"; -} -} // namespace heap_ // adds to heap and maintains heap quality -void add_to_heap(t_heap* hptr) { - heap_::expand_heap_if_full(); - // start with undefined hole - ++heap_tail; - heap_::sift_up(heap_tail - 1, hptr); -} - /*WMF: peeking accessor :) */ -bool is_empty_heap() { - return (bool)(heap_tail == 1); -} - -t_heap* -get_heap_head() { - /* Returns a pointer to the smallest element on the heap, or NULL if the * - * heap is empty. Invalid (index == OPEN) entries on the heap are never * - * returned -- they are just skipped over. */ - - t_heap* cheapest; - size_t hole, child; - - do { - if (heap_tail == 1) { /* Empty heap. */ - VTR_LOG_WARN("Empty heap occurred in get_heap_head.\n"); - return (nullptr); - } - - cheapest = heap[1]; - - hole = 1; - child = 2; - --heap_tail; - while ((int)child < heap_tail) { - if (heap[child + 1]->cost < heap[child]->cost) - ++child; // become right child - heap[hole] = heap[child]; - hole = child; - child = heap_::left(child); - } - heap_::sift_up(hole, heap[heap_tail]); - - } while (cheapest->index == OPEN); /* Get another one if invalid entry. */ - - return (cheapest); -} - -void empty_heap() { - for (int i = 1; i < heap_tail; i++) - free_heap_data(heap[i]); - - heap_tail = 1; -} - -t_heap* -alloc_heap_data() { - if (heap_free_head == nullptr) { /* No elements on the free list */ - heap_free_head = vtr::chunk_new(&heap_ch); - } - - //Extract the head - t_heap* temp_ptr = heap_free_head; - heap_free_head = heap_free_head->u.next; - - num_heap_allocated++; - - //Reset - temp_ptr->u.next = nullptr; - temp_ptr->cost = 0.; - temp_ptr->backward_path_cost = 0.; - temp_ptr->R_upstream = 0.; - temp_ptr->index = OPEN; - temp_ptr->u.prev.node = NO_PREVIOUS; - temp_ptr->u.prev.edge = NO_PREVIOUS; - return (temp_ptr); -} - -void free_heap_data(t_heap* hptr) { - hptr->u.next = heap_free_head; - heap_free_head = hptr; - num_heap_allocated--; -} void invalidate_heap_entries(int sink_node, int ipin_node) { /* Marks all the heap entries consisting of sink_node, where it was reached * * via ipin_node, as invalid (OPEN). Used only by the breadth_first router * * and even then only in rare circumstances. */ - for (int i = 1; i < heap_tail; i++) { - if (heap[i]->index == sink_node) { - if (heap[i]->u.prev.node == ipin_node) { - heap[i]->index = OPEN; /* Invalid. */ + for (auto* item : vtr::make_range(BucketItems::begin(), BucketItems::end())) { + if (item->index == sink_node) { + if (item->u.prev.node == ipin_node) { + item->index = OPEN; /* Invalid. */ break; } } @@ -1573,7 +1319,7 @@ void print_route(const char* placement_file, const char* route_file) { if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_MEM)) { fp = vtr::fopen(getEchoFileName(E_ECHO_MEM), "w"); fprintf(fp, "\nNum_heap_allocated: %d Num_trace_allocated: %d\n", - num_heap_allocated, num_trace_allocated); + BucketItems::num_heap_allocated(), num_trace_allocated); fprintf(fp, "Num_linked_f_pointer_allocated: %d\n", num_linked_f_pointer_allocated); fclose(fp); @@ -1583,14 +1329,14 @@ void print_route(const char* placement_file, const char* route_file) { route_ctx.routing_id = vtr::secure_digest_file(route_file); } -//To ensure the router can only swaps pin which are actually logically equivalent some block output pins must be +//To ensure the router can only swap pins which are actually logically equivalent, some block output pins must be //reserved in certain cases. // // In the RR graph, output pin equivalence is modelled by a single SRC node connected to (multiple) OPINs, modelling // that each of the OPINs is logcially equivalent (i.e. it doesn't matter through which the router routes a signal, // so long as it is from the appropriate SRC). // -// This correctly models 'full' equivalence (e.g. if there is a full crossbar between the outputs), but is to +// This correctly models 'full' equivalence (e.g. if there is a full crossbar between the outputs), but is too // optimistic for 'instance' equivalence (which typcially models the pin equivalence possible by swapping sub-block // instances like BLEs). In particular, for the 'instance' equivalence case, some of the 'equivalent' block outputs // may be used by internal signals which are routed entirely *within* the block (i.e. the signals which never leave @@ -1637,7 +1383,7 @@ void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local VTR_ASSERT(type->class_inf[iclass].equivalence == PortEquivalence::INSTANCE); //From the SRC node we walk through it's out going edges to collect the - //OPIN nodes. We then push them onto a heap so the the OPINs with lower + //OPIN nodes. We then push them onto a heap so the OPINs with lower //congestion cost are popped-off/reserved first. (Intuitively, we want //the reserved OPINs to move out of the way of congestion, by preferring //to reserve OPINs with lower congestion costs). diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h index 147ff9ddc23..19d537295be 100644 --- a/vpr/src/route/route_common.h +++ b/vpr/src/route/route_common.h @@ -3,52 +3,7 @@ #include #include "clustered_netlist.h" #include "vtr_vector.h" - -/* Used by the heap as its fundamental data structure. - * Each heap element represents a partial route. - * - * cost: The cost used to sort heap. - * For the timing-driven router this is the backward_path_cost + - * expected cost to the target. - * For the breadth-first router it is the node cost to reach this - * point. - * - * backward_path_cost: Used only by the timing-driven router. The "known" - * cost of the path up to and including this node. - * In this case, the .cost member contains not only - * the known backward cost but also an expected cost - * to the target. - * - * R_upstream: Used only by the timing-driven router. Stores the upstream - * resistance to ground from this node, including the - * resistance of the node itself (device_ctx.rr_nodes[index].R). - * - * index: The RR node index associated with the costs/R_upstream values - * - * u.prev.node: The previous node used to reach the current 'index' node - * u.prev.next: The edge from u.prev.node used to reach the current 'index' node - * - * u.next: pointer to the next s_heap structure in the free - * linked list. Not used when on the heap. - * - */ -struct t_heap { - float cost = 0.; - float backward_path_cost = 0.; - float R_upstream = 0.; - - int index = OPEN; - - struct t_prev { - int node; - int edge; - }; - - union { - t_heap* next; - t_prev prev; - } u; -}; +#include "bucket.h" /******* Subroutines in route_common used only by other router modules ******/ @@ -72,36 +27,14 @@ float get_rr_cong_cost(int inode); void mark_ends(ClusterNetId net_id); void mark_remaining_ends(const std::vector& remaining_sinks); -void add_to_heap(t_heap* hptr); -t_heap* alloc_heap_data(); void node_to_heap(int inode, float cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream); -bool is_empty_heap(); - void free_traceback(ClusterNetId net_id); void drop_traceback_tail(ClusterNetId net_id); void free_traceback(t_trace* tptr); void add_to_mod_list(int inode, std::vector& modified_rr_node_inf); -namespace heap_ { -void build_heap(); -void sift_down(size_t hole); -void sift_up(size_t tail, t_heap* const hptr); -void push_back(t_heap* const hptr); -void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream); -bool is_valid(); -void pop_heap(); -void print_heap(); -void verify_extract_top(); -} // namespace heap_ - -t_heap* get_heap_head(); - -void empty_heap(); - -void free_heap_data(t_heap* hptr); - void invalidate_heap_entries(int sink_node, int ipin_node); void init_route_structs(int bb_factor); @@ -112,7 +45,6 @@ void reset_rr_node_route_structs(); void free_trace_structs(); -void init_heap(const DeviceGrid& grid); void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local_opins); void free_chunk_memory_trace(); From 28c807e58bc130963ab928b8ad7ff0594fc1bdde Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Tue, 10 Dec 2019 15:53:25 +0100 Subject: [PATCH 095/107] Revert bad revision. Signed-off-by: Alessandro Comodi --- libs/libarchfpga/src/read_xml_arch_file.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index cb4022a27b6..32381facab6 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -4907,7 +4907,8 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t if (pb_type->num_pins != (int)pin_direct_mapping.size()) { archfpga_throw(__FILE__, __LINE__, - "Logical and Physical types have a different number of ports.\n"); + "Logical block (%s) and Physical tile (%s) have a different number of ports.\n", + logical_block->name, physical_tile->name); } for (auto pin_map : pin_direct_mapping) { @@ -4921,7 +4922,8 @@ static void check_port_direct_mappings(t_physical_tile_type_ptr physical_tile, t || tile_port->num_pins != block_port->num_pins || tile_port->equivalent != block_port->equivalent) { archfpga_throw(__FILE__, __LINE__, - "Logical and Physical types do not have equivalent port specifications.\n"); + "Logical block (%s) and Physical tile (%s) do not have equivalent port specifications.\n", + logical_block->name, physical_tile->name); } } } From f5de65cb452ab0f99ee4333b5e1ce28099430bcc Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 9 Sep 2019 10:24:25 -0700 Subject: [PATCH 096/107] Add logic to rescale bucketing for wirelength driven routing. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/bucket.cpp | 69 +++++++++++++++++++++++++++++++++++++--- vpr/src/route/bucket.h | 18 +++++++---- 2 files changed, 77 insertions(+), 10 deletions(-) diff --git a/vpr/src/route/bucket.cpp b/vpr/src/route/bucket.cpp index e531ba8699a..da7a4ca99ad 100644 --- a/vpr/src/route/bucket.cpp +++ b/vpr/src/route/bucket.cpp @@ -16,6 +16,11 @@ void Bucket::init(const DeviceGrid& grid) { heap_head_ = std::numeric_limits::max(); heap_tail_ = 0; + + conv_factor_ = kDefaultConvFactor; + + min_cost_ = std::numeric_limits::max(); + max_cost_ = std::numeric_limits::min(); } void Bucket::free() { @@ -46,6 +51,9 @@ t_heap** Bucket::heap_ = nullptr; size_t Bucket::heap_size_ = 0; size_t Bucket::heap_head_ = std::numeric_limits::max(); size_t Bucket::heap_tail_ = 0; +float Bucket::min_cost_ = 0.f; +float Bucket::max_cost_ = 0.f; +float Bucket::conv_factor_ = 0.f; void Bucket::clear() { if (heap_head_ != std::numeric_limits::max()) { @@ -55,19 +63,74 @@ void Bucket::clear() { heap_tail_ = 0; } +void Bucket::check_scaling() { + float min_cost = min_cost_; + float max_cost = max_cost_; + VTR_ASSERT(max_cost != std::numeric_limits::min()); + if (min_cost == std::numeric_limits::max()) { + min_cost = max_cost; + } + auto min_bucket = cost_to_int(min_cost); + auto max_bucket = cost_to_int(max_cost); + + if (min_bucket < 0 || max_bucket < 0 || max_bucket > 1000000) { + // If min and max are close to each other, assume 3 orders of + // magnitude between min and max. + // + // If min and max are at least 3 orders of magnitude apart, scale + // soley based on max cost. + conv_factor_ = 50000.f / max_cost_ / std::max(1.f, 1000.f / (max_cost_ / min_cost_)); + + VTR_ASSERT(cost_to_int(min_cost_) >= 0); + VTR_ASSERT(cost_to_int(max_cost_) >= 0); + VTR_ASSERT(cost_to_int(max_cost_) < 1000000); + + // Reheap after adjusting scaling. + if (heap_head_ != std::numeric_limits::max()) { + std::vector reheap; + for (size_t bucket = heap_head_; bucket <= heap_tail_; ++bucket) { + for (t_heap* item = heap_[bucket]; item != nullptr; item = item->next_bucket) { + reheap.push_back(item); + } + } + + std::fill(heap_ + heap_head_, heap_ + heap_tail_ + 1, nullptr); + heap_head_ = std::numeric_limits::max(); + heap_tail_ = 0; + + for (t_heap* item : reheap) { + push(item); + } + } + } +} + void Bucket::push(t_heap* hptr) { float cost = hptr->cost; if (!std::isfinite(cost)) { return; } - //heap_::verify_extract_top(); + bool check_scale = false; + // Exclude 0 cost from min_cost to provide useful scaling factor. + if (cost < min_cost_ && cost > 0) { + min_cost_ = cost; + check_scale = true; + } + if (cost > max_cost_) { + max_cost_ = cost; + check_scale = true; + } + + if (check_scale) { + check_scaling(); + } // Which bucket should this go into? auto int_cost = cost_to_int(cost); if (int_cost < 0) { - VTR_LOG_WARN("Cost is negative? cost = %g\n", cost); + VTR_LOG_WARN("Cost is negative? cost = %g, bucket = %d\n", cost, int_cost); int_cost = 0; } @@ -90,8 +153,6 @@ void Bucket::push(t_heap* hptr) { if (uint_cost > heap_tail_) { heap_tail_ = uint_cost; } - - //heap_::verify_extract_top(); } t_heap* Bucket::pop() { diff --git a/vpr/src/route/bucket.h b/vpr/src/route/bucket.h index aad509a1ccc..9a6045e56e4 100644 --- a/vpr/src/route/bucket.h +++ b/vpr/src/route/bucket.h @@ -223,11 +223,11 @@ class Bucket { private: // Factor used to convert cost from float to int. Should be scaled to // enable sufficent precision in bucketting. - static constexpr float kConvFactor = 1e12; + static constexpr float kDefaultConvFactor = 1e12; // Convert cost from float to integer bucket id. static int cost_to_int(float cost) { - return (int)(cost * kConvFactor); + return (int)(cost * conv_factor_); } // Simple fast random function used for randomizing item selection on pop. @@ -236,6 +236,8 @@ class Bucket { return seed_; } + static void check_scaling(); + // Expand the number of buckets. // // Only call if insufficient bucets exist. @@ -243,10 +245,14 @@ class Bucket { static size_t seed_; /* Seed for fast_rand, should be non-zero */ - static t_heap** heap_; /* Buckets for linked lists*/ - static size_t heap_size_; /* Number of buckets */ - static size_t heap_head_; /* First non-empty bucket */ - static size_t heap_tail_; /* Last non-empty bucket */ + static t_heap** heap_; /* Buckets for linked lists*/ + static size_t heap_size_; /* Number of buckets */ + static size_t heap_head_; /* First non-empty bucket */ + static size_t heap_tail_; /* Last non-empty bucket */ + static float conv_factor_; /* Cost bucket scaling factor */ + + static float min_cost_; /* Smallest cost seen */ + static float max_cost_; /* Large cost seen */ }; inline bool is_empty_heap() { From 0b380c986dfe05d81665fda9a87b6c5f1b7651b7 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 21 Nov 2019 15:05:39 -0800 Subject: [PATCH 097/107] Remove clock test. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 4f29fadb034..afa3dc97a2e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -52,6 +52,5 @@ regression_tests/vtr_reg_strong/strong_global_nonuniform regression_tests/vtr_reg_strong/strong_sdc regression_tests/vtr_reg_strong/strong_timing_report_detail regression_tests/vtr_reg_strong/strong_route_reconverge -regression_tests/vtr_reg_strong/strong_clock_buf regression_tests/vtr_reg_strong/strong_equivalent_sites regression_tests/vtr_reg_strong/strong_absorb_buffers From 59e9d8080e12953c24de74df790649e61f614162 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Mon, 9 Sep 2019 12:14:33 -0700 Subject: [PATCH 098/107] Add assumptions about cost structure. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/bucket.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/vpr/src/route/bucket.h b/vpr/src/route/bucket.h index 9a6045e56e4..8426fc48d26 100644 --- a/vpr/src/route/bucket.h +++ b/vpr/src/route/bucket.h @@ -182,6 +182,16 @@ alloc_heap_data() { // with items is returned. This randomization exists to prevent the router // from following identical paths when operating with identical costs. // Consider two parallel paths to a node. +// +// Important node: This approximation makes some assumptions about the +// structure of costs. +// +// Assumptions: +// 1. 0 is the minimum cost +// 2. Costs that are different by 0.1 % of the maximum cost are effectively +// equivilant +// 3. The cost function is roughly linear. +// class Bucket { public: Bucket() {} From cc9b8fb084cddb636870033fdcf6a2f6b1dbedda Mon Sep 17 00:00:00 2001 From: Andrew Butt Date: Thu, 20 Jun 2019 12:20:08 -0400 Subject: [PATCH 099/107] Added binary read/write to vpr Signed-off-by: Andrew Butt --- vpr/src/route/rr_graph.cpp | 48 ++++++++ vpr/src/route/rr_graph.h | 6 + vpr/src/route/rr_graph_reader.cpp | 187 ++++++++++++++++++++++++++---- vpr/src/route/rr_graph_writer.cpp | 47 +++++++- vpr/src/util/vpr_utils.cpp | 9 ++ vpr/src/util/vpr_utils.h | 2 + 6 files changed, 272 insertions(+), 27 deletions(-) diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index df1bb8b0967..de22b6069d7 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -2509,6 +2509,54 @@ static vtr::NdMatrix, 4> alloc_and_load_track_to_pin_lookup(vtr return track_to_pin_lookup; } +/* Writes out data (excludes fasm metadata) about node inode to binary in file fp * + * Writes data in the following order: int inode, t_rr_type type, e_direction * + * direction (if CHANX or CHANY), uint16_t capacity, length 5 uint16_t array pos, * + * e_side side (if IPIN or OPIN), float R, float C, uint16_t num_edges.Then loops * + * through every edge writing out int edge_sink node and uint16_t edge_switch. */ +void write_rr_node(FILE* fp, const std::vector& L_rr_node, int inode) { + const auto& rr_node = L_rr_node[inode]; + t_rr_type type = rr_node.type(); + uint16_t num_edges = rr_node.num_edges(); + int edge_sink_node; + uint16_t edge_switch; + uint16_t capacity = (uint16_t)rr_node.capacity(); + float R = rr_node.R(); + float C = rr_node.C(); + uint16_t pos[5]; + + pos[0] = rr_node.xlow(); + pos[1] = rr_node.ylow(); + pos[2] = rr_node.xhigh(); + pos[3] = rr_node.yhigh(); + pos[4] = rr_node.ptc_num(); + + fwrite(&inode, sizeof(inode), 1, fp); + fwrite(&type, sizeof(type), 1, fp); + if (rr_node.type() == CHANX || rr_node.type() == CHANY) { + e_direction direction = rr_node.direction(); + fwrite(&direction, sizeof(direction), 1, fp); + } + fwrite(&capacity, sizeof(capacity), 1, fp); + fwrite(pos, sizeof(*pos), 5, fp); + + if (rr_node.type() == IPIN || rr_node.type() == OPIN) { + e_side side = rr_node.side(); + fwrite(&side, sizeof(side), 1, fp); + } + + fwrite(&R, sizeof(R), 1, fp); + fwrite(&C, sizeof(C), 1, fp); + fwrite(&num_edges, sizeof(num_edges), 1, fp); + + for (int iedge = 0; iedge < rr_node.num_edges(); ++iedge) { + edge_sink_node = rr_node.edge_sink_node(iedge); + edge_switch = rr_node.edge_switch(iedge); + fwrite(&edge_sink_node, sizeof(edge_sink_node), 1, fp); + fwrite(&edge_switch, sizeof(edge_switch), 1, fp); + } +} + std::string describe_rr_node(int inode) { auto& device_ctx = g_vpr_ctx.device(); diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index f55a64f7f9f..e3185de09d6 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -6,6 +6,9 @@ * and so are not currently used in commercial architectures. */ #define INCLUDE_TRACK_BUFFERS false +#define BINARY_MAGIC_NUM 0x42525247 +#define BINARY_FILE_VERSION 1 + #include "device_grid.h" enum e_graph_type { @@ -45,6 +48,9 @@ void free_rr_graph(); //Returns a brief one-line summary of an RR node std::string describe_rr_node(int inode); +void print_rr_node(FILE* fp, const std::vector& L_rr_node, int inode); +void write_rr_node(FILE* fp, const std::vector& L_rr_node, int inode); + void init_fan_in(std::vector& L_rr_node, const int num_rr_nodes); // Sets the spec for the rr_switch based on the arch switch diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index e9380b12d7e..e0c51ee14e6 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -52,12 +52,14 @@ void verify_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data, void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid); +void process_nodes_and_switches_bin(FILE* fp, int* wire_to_rr_ipin_switch, bool is_global_graph, const std::vector& segment_inf, int numSwitches); void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches); void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_rr_node_indices(const DeviceGrid& grid); void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const bool is_global_graph, const int num_seg_types); +void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id); /************************ Subroutine definitions ****************************/ @@ -137,14 +139,6 @@ void load_rr_file(const t_graph_type graph_type, int max_chan_width = (is_global_graph ? 1 : nodes_per_chan.max); VTR_ASSERT(max_chan_width > 0); - /* Alloc rr nodes and count count nodes */ - next_component = get_single_child(rr_graph, "rr_nodes", loc_data); - - int num_rr_nodes = count_children(next_component, "node", loc_data); - - device_ctx.rr_nodes.resize(num_rr_nodes); - process_nodes(next_component, loc_data); - /* Loads edges, switches, and node look up tables*/ next_component = get_single_child(rr_graph, "switches", loc_data); @@ -152,26 +146,53 @@ void load_rr_file(const t_graph_type graph_type, device_ctx.rr_switch_inf.resize(numSwitches); process_switches(next_component, loc_data); + /* Branches to binary format */ + next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, OPTIONAL); + if (next_component) { + auto filename = get_attribute(next_component, "file", loc_data).as_string(""); + VTR_LOG("Using Binary File: %s\n", filename); + FILE* fp = fopen(filename, "rb"); + if (fp == NULL) { + VPR_THROW(VPR_ERROR_OTHER, "Binary File %s Does Not Exist\n", filename); + } + + process_nodes_and_switches_bin(fp, wire_to_rr_ipin_switch, is_global_graph, segment_inf, numSwitches); + + partition_rr_graph_edges(device_ctx); + process_rr_node_indices(grid); + init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size()); + alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, + max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); - next_component = get_single_child(rr_graph, "rr_edges", loc_data); - process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches); + } else { + /* Alloc rr nodes and count count nodes */ + next_component = get_single_child(rr_graph, "rr_nodes", loc_data); + + int num_rr_nodes = count_children(next_component, "node", loc_data); + + device_ctx.rr_nodes.resize(num_rr_nodes); + process_nodes(next_component, loc_data); - //Partition the rr graph edges for efficient access to configurable/non-configurable - //edge subsets. Must be done after RR switches have been allocated - partition_rr_graph_edges(device_ctx); + next_component = get_single_child(rr_graph, "rr_edges", loc_data); + process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches); - process_rr_node_indices(grid); + //Partition the rr graph edges for efficient access to configurable/non-configurable + //edge subsets. Must be done after RR switches have been allocated + partition_rr_graph_edges(device_ctx); - init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size()); + process_rr_node_indices(grid); - //sets the cost index and seg id information - next_component = get_single_child(rr_graph, "rr_nodes", loc_data); - set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size()); + init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size()); - alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, - max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); + //sets the cost index and seg id information + next_component = get_single_child(rr_graph, "rr_nodes", loc_data); + set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size()); - process_seg_id(next_component, loc_data); + alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, + max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); + + process_seg_id(next_component, loc_data); + } device_ctx.chan_width = nodes_per_chan; device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); @@ -183,6 +204,103 @@ void load_rr_file(const t_graph_type graph_type, } } +void process_nodes_and_switches_bin(FILE* fp, + int* wire_to_rr_ipin_switch, + bool is_global_graph, + const std::vector& segment_inf, + int numSwitches) { + auto& device_ctx = g_vpr_ctx.mutable_device(); + uint32_t magic_num; + uint16_t format_version; + uint16_t header_length; + uint64_t num_rr_nodes; + fread_secure(&magic_num, sizeof(magic_num), 1, fp); + fread_secure(&format_version, sizeof(format_version), 1, fp); + fread_secure(&header_length, sizeof(header_length), 1, fp); + char* header = new char[header_length + 1]; + header[header_length] = '\0'; + fread_secure(header, sizeof(char), header_length, fp); + fread_secure(&num_rr_nodes, sizeof(num_rr_nodes), 1, fp); + device_ctx.rr_nodes.resize(num_rr_nodes); + + if (magic_num != BINARY_MAGIC_NUM) { + VTR_LOG_WARN("Not a VPR Binary rr_graph file\n"); + } + + if (format_version != BINARY_FILE_VERSION) { + VTR_LOG_WARN("Binary file format versions do not match\n"); + } + + int inode; + t_rr_type node_type; + uint16_t num_edges; + e_direction direction; + e_side side; + int edge_sink_node; + uint16_t edge_switch; + uint16_t capacity; + float R; + float C; + uint16_t pos[5]; + + for (uint64_t i = 0; i < num_rr_nodes; i++) { + fread_secure(&inode, sizeof(inode), 1, fp); + fread_secure(&node_type, sizeof(node_type), 1, fp); + auto& node = device_ctx.rr_nodes[inode]; + node.set_type(node_type); + if (node.type() == CHANX || node.type() == CHANY) { + fread_secure(&direction, sizeof(direction), 1, fp); + node.set_direction(direction); + } + + fread_secure(&capacity, sizeof(capacity), 1, fp); + if (capacity > 0) + node.set_capacity(capacity); + fread_secure(pos, sizeof(*pos), 5, fp); + node.set_coordinates(pos[0], pos[1], pos[2], pos[3]); + node.set_ptc_num(pos[4]); + if (node.type() == IPIN || node.type() == OPIN) { + fread_secure(&side, sizeof(side), 1, fp); + node.set_side(side); + } + + fread_secure(&R, sizeof(R), 1, fp); + fread_secure(&C, sizeof(C), 1, fp); + node.set_rc_index(find_create_rr_rc_data(R, C)); + + fread_secure(&num_edges, sizeof(num_edges), 1, fp); + + node.set_num_edges(num_edges); + for (int j = 0; j < num_edges; j++) { + fread_secure(&edge_sink_node, sizeof(edge_sink_node), 1, fp); + fread_secure(&edge_switch, sizeof(edge_switch), 1, fp); + node.set_edge_sink_node(j, edge_sink_node); + node.set_edge_switch(j, edge_switch); + } + set_cost_index_bin(inode, node_type, is_global_graph, segment_inf.size(), 0); + } + std::vector count_for_wire_to_ipin_switches; + count_for_wire_to_ipin_switches.resize(numSwitches, 0); + for (uint64_t i = 0; i < num_rr_nodes; i++) { + auto& node = device_ctx.rr_nodes[i]; + if (node.type() == CHANX || node.type() == CHANY) { + num_edges = node.num_edges(); + for (int j = 0; j < num_edges; j++) { + if (device_ctx.rr_nodes[node.edge_sink_node(j)].type() == IPIN) { + count_for_wire_to_ipin_switches[j]++; + } + } + } + } + int max = -1; + for (int j = 0; j < numSwitches; j++) { + if (count_for_wire_to_ipin_switches[j] > max) { + *wire_to_rr_ipin_switch = j; + max = count_for_wire_to_ipin_switches[j]; + } + } +} + /* Reads in the switch information and adds it to device_ctx.rr_switch_inf as specified*/ void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -884,3 +1002,30 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, rr_node = rr_node.next_sibling(rr_node.name()); } } + +/* This function sets the Source pins, sink pins, ipin, and opin + * to their unique cost index identifier. CHANX and CHANY cost indicies are set after the + * seg_id is read in from the rr graph */ +void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id) { + auto& device_ctx = g_vpr_ctx.mutable_device(); + auto& node = device_ctx.rr_nodes[inode]; + //set the cost index in order to load the segment information, rr nodes should be set already + if (node_type == SOURCE) { + node.set_cost_index(SOURCE_COST_INDEX); + } else if (node_type == SINK) { + node.set_cost_index(SINK_COST_INDEX); + } else if (node_type == IPIN) { + node.set_cost_index(IPIN_COST_INDEX); + } else if (node_type == OPIN) { + node.set_cost_index(OPIN_COST_INDEX); + } else if (node_type == CHANX || node_type == CHANY) { + /*CHANX and CHANY cost index is dependent on the segment id*/ + if (is_global_graph) { + node.set_cost_index(0); + } else if (device_ctx.rr_nodes[inode].type() == CHANX) { + node.set_cost_index(CHANX_COST_INDEX_START + seg_id); + } else if (device_ctx.rr_nodes[inode].type() == CHANY) { + node.set_cost_index(CHANX_COST_INDEX_START + num_seg_types + seg_id); + } + } +} diff --git a/vpr/src/route/rr_graph_writer.cpp b/vpr/src/route/rr_graph_writer.cpp index 9b0b960cb1c..cd705cd3f9a 100644 --- a/vpr/src/route/rr_graph_writer.cpp +++ b/vpr/src/route/rr_graph_writer.cpp @@ -5,6 +5,7 @@ * children tags such as timing, location, or some general * details. Each tag has attributes to describe them */ +#include #include #include #include @@ -15,6 +16,7 @@ #include "read_xml_arch_file.h" #include "vtr_version.h" #include "rr_graph_writer.h" +#include "rr_graph.h" /* All values are printed with this precision value. The higher the * value, the more accurate the read in rr graph is. Using numeric_limits @@ -35,7 +37,17 @@ void write_rr_segments(std::fstream& fp, const std::vector& segme /* This function is used to write the rr_graph into xml format into a a file with name: file_name */ void write_rr_graph(const char* file_name, const std::vector& segment_inf) { std::fstream fp; - fp.open(file_name, std::fstream::out | std::fstream::trunc); + FILE* fb = nullptr; + std::stringstream header; + std::string filename_str(file_name); + bool binary_mode = (filename_str.substr(filename_str.length() - 7) == "bin.xml"); + std::string bin_file_name; + if (binary_mode) { + bin_file_name = filename_str.substr(0, filename_str.length() - 4); + VTR_LOG("RR_Graph binary file %s\n", bin_file_name.c_str()); + fb = vtr::fopen(bin_file_name.c_str(), "w"); + } + fp.open(file_name, fstream::out | fstream::trunc); /* Prints out general info for easy error checking*/ if (!fp.is_open() || !fp.good()) { @@ -43,8 +55,9 @@ void write_rr_graph(const char* file_name, const std::vector& seg "couldn't open file \"%s\" for generating RR graph file\n", file_name); } std::cout << "Writing RR graph" << std::endl; - fp << "" << std::endl; + header << "" << std::endl; + fp << header.rdbuf(); /* Write out each individual component*/ write_rr_channel(fp); @@ -52,9 +65,31 @@ void write_rr_graph(const char* file_name, const std::vector& seg write_rr_segments(fp, segment_inf); write_rr_block_types(fp); write_rr_grid(fp); - write_rr_node(fp); - write_rr_edges(fp); - fp << ""; + if (binary_mode) { + fp << " \n"; + auto& device_ctx = g_vpr_ctx.device(); + const std::string header_s = header.str(); + const char* header_c = header_s.c_str(); + uint32_t magic_num = BINARY_MAGIC_NUM; + uint16_t format_version = BINARY_FILE_VERSION; + uint16_t header_length = header_s.length(); + uint64_t num_rr_nodes = (uint64_t)device_ctx.rr_nodes.size(); + VTR_LOG("RR_Graph binary mode\n"); + printf("Header length: %d\n", header_length); + fwrite(&magic_num, sizeof(magic_num), 1, fb); + fwrite(&format_version, sizeof(format_version), 1, fb); + fwrite(&header_length, sizeof(header_length), 1, fb); + fwrite(&header_c, sizeof(char), header_length, fb); + fwrite(&num_rr_nodes, sizeof(num_rr_nodes), 1, fb); + for (size_t inode = 0; inode < num_rr_nodes; inode++) { + write_rr_node(fb, device_ctx.rr_nodes, inode); + } + fclose(fb); + } else { + write_rr_node(fp); + write_rr_edges(fp); + } + fp << "\n"; fp.close(); diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index e19d1720915..fc9377adc29 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -1917,6 +1917,15 @@ static int convert_switch_index(int* switch_index, int* fanin) { return -1; } +void fread_secure(void* var, size_t size, unsigned int count, FILE* fp) { + auto result = fread(var, size, count, fp); + if (result != count) { + VPR_THROW(VPR_ERROR_OTHER, "ERROR reading file\n"); + } + + return; +} + /* * print out number of usage for every switch (type / fanin combination) * (referring to rr_graph.c: alloc_rr_switch_inf()) diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index e43cc91dacd..c4345af84ed 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -41,6 +41,8 @@ void get_pin_range_for_block(const ClusterBlockId blk_id, void sync_grid_to_blocks(); +void fread_secure(void* var, size_t size, unsigned int count, FILE* fp); + //Returns the name of the pin_index'th pin on the specified block type std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_index); From ca6f2b6262705d9e3b357f0410fd99bddfad38ce Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 27 Sep 2019 13:32:24 -0700 Subject: [PATCH 100/107] Reflow binary graph read to keep changes in 1 diff hunks. This helps avoid conflicts with other changes. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/rr_graph_reader.cpp | 124 +++++++++++++++++------------- 1 file changed, 70 insertions(+), 54 deletions(-) diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index e0c51ee14e6..773c83a260c 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -139,16 +139,18 @@ void load_rr_file(const t_graph_type graph_type, int max_chan_width = (is_global_graph ? 1 : nodes_per_chan.max); VTR_ASSERT(max_chan_width > 0); - /* Loads edges, switches, and node look up tables*/ - next_component = get_single_child(rr_graph, "switches", loc_data); - - int numSwitches = count_children(next_component, "switch", loc_data); - device_ctx.rr_switch_inf.resize(numSwitches); - - process_switches(next_component, loc_data); /* Branches to binary format */ next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, OPTIONAL); if (next_component) { + /* Loads edges, switches, and node look up tables*/ + next_component = get_single_child(rr_graph, "switches", loc_data); + + int numSwitches = count_children(next_component, "switch", loc_data); + device_ctx.rr_switch_inf.resize(numSwitches); + + process_switches(next_component, loc_data); + + next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, OPTIONAL); auto filename = get_attribute(next_component, "file", loc_data).as_string(""); VTR_LOG("Using Binary File: %s\n", filename); FILE* fp = fopen(filename, "rb"); @@ -164,35 +166,49 @@ void load_rr_file(const t_graph_type graph_type, alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); - } else { - /* Alloc rr nodes and count count nodes */ - next_component = get_single_child(rr_graph, "rr_nodes", loc_data); + device_ctx.chan_width = nodes_per_chan; + device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); - int num_rr_nodes = count_children(next_component, "node", loc_data); + check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); - device_ctx.rr_nodes.resize(num_rr_nodes); - process_nodes(next_component, loc_data); + return; + } - next_component = get_single_child(rr_graph, "rr_edges", loc_data); - process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches); + /* Alloc rr nodes and count count nodes */ + next_component = get_single_child(rr_graph, "rr_nodes", loc_data); - //Partition the rr graph edges for efficient access to configurable/non-configurable - //edge subsets. Must be done after RR switches have been allocated - partition_rr_graph_edges(device_ctx); + int num_rr_nodes = count_children(next_component, "node", loc_data); - process_rr_node_indices(grid); + device_ctx.rr_nodes.resize(num_rr_nodes); + process_nodes(next_component, loc_data); - init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size()); + /* Loads edges, switches, and node look up tables*/ + next_component = get_single_child(rr_graph, "switches", loc_data); - //sets the cost index and seg id information - next_component = get_single_child(rr_graph, "rr_nodes", loc_data); - set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size()); + int numSwitches = count_children(next_component, "switch", loc_data); + device_ctx.rr_switch_inf.resize(numSwitches); - alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, - max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); + process_switches(next_component, loc_data); - process_seg_id(next_component, loc_data); - } + next_component = get_single_child(rr_graph, "rr_edges", loc_data); + process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches); + + //Partition the rr graph edges for efficient access to configurable/non-configurable + //edge subsets. Must be done after RR switches have been allocated + partition_rr_graph_edges(device_ctx); + + process_rr_node_indices(grid); + + init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size()); + + //sets the cost index and seg id information + next_component = get_single_child(rr_graph, "rr_nodes", loc_data); + set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size()); + + alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, + max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); + + process_seg_id(next_component, loc_data); device_ctx.chan_width = nodes_per_chan; device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); @@ -204,6 +220,33 @@ void load_rr_file(const t_graph_type graph_type, } } +/* This function sets the Source pins, sink pins, ipin, and opin + * to their unique cost index identifier. CHANX and CHANY cost indicies are set after the + * seg_id is read in from the rr graph */ +void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id) { + auto& device_ctx = g_vpr_ctx.mutable_device(); + auto& node = device_ctx.rr_nodes[inode]; + //set the cost index in order to load the segment information, rr nodes should be set already + if (node_type == SOURCE) { + node.set_cost_index(SOURCE_COST_INDEX); + } else if (node_type == SINK) { + node.set_cost_index(SINK_COST_INDEX); + } else if (node_type == IPIN) { + node.set_cost_index(IPIN_COST_INDEX); + } else if (node_type == OPIN) { + node.set_cost_index(OPIN_COST_INDEX); + } else if (node_type == CHANX || node_type == CHANY) { + /*CHANX and CHANY cost index is dependent on the segment id*/ + if (is_global_graph) { + node.set_cost_index(0); + } else if (device_ctx.rr_nodes[inode].type() == CHANX) { + node.set_cost_index(CHANX_COST_INDEX_START + seg_id); + } else if (device_ctx.rr_nodes[inode].type() == CHANY) { + node.set_cost_index(CHANX_COST_INDEX_START + num_seg_types + seg_id); + } + } +} + void process_nodes_and_switches_bin(FILE* fp, int* wire_to_rr_ipin_switch, bool is_global_graph, @@ -1002,30 +1045,3 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, rr_node = rr_node.next_sibling(rr_node.name()); } } - -/* This function sets the Source pins, sink pins, ipin, and opin - * to their unique cost index identifier. CHANX and CHANY cost indicies are set after the - * seg_id is read in from the rr graph */ -void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id) { - auto& device_ctx = g_vpr_ctx.mutable_device(); - auto& node = device_ctx.rr_nodes[inode]; - //set the cost index in order to load the segment information, rr nodes should be set already - if (node_type == SOURCE) { - node.set_cost_index(SOURCE_COST_INDEX); - } else if (node_type == SINK) { - node.set_cost_index(SINK_COST_INDEX); - } else if (node_type == IPIN) { - node.set_cost_index(IPIN_COST_INDEX); - } else if (node_type == OPIN) { - node.set_cost_index(OPIN_COST_INDEX); - } else if (node_type == CHANX || node_type == CHANY) { - /*CHANX and CHANY cost index is dependent on the segment id*/ - if (is_global_graph) { - node.set_cost_index(0); - } else if (device_ctx.rr_nodes[inode].type() == CHANX) { - node.set_cost_index(CHANX_COST_INDEX_START + seg_id); - } else if (device_ctx.rr_nodes[inode].type() == CHANY) { - node.set_cost_index(CHANX_COST_INDEX_START + num_seg_types + seg_id); - } - } -} From 77db33de5913e6db577344de18a1dcba0e657244 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 16 Oct 2019 12:39:17 -0700 Subject: [PATCH 101/107] Use Dijkstra to generate place delay matrix. This avoids width * height A* runs, and is likely much faster and will return better results than the previous place delay matrix algorithm for larger graphs. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/place/timing_place_lookup.cpp | 240 ++++++++++++++++++++++---- 1 file changed, 202 insertions(+), 38 deletions(-) diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 4aa439aab16..98782b7db76 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -90,6 +90,19 @@ static void generic_compute_matrix( bool measure_directconnect, const std::set& allowed_types); +static void generic_compute_matrix_expand( + const RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types); + static vtr::Matrix compute_delta_delays( const RouterDelayProfiler& route_profiler, const t_placer_opts& palcer_opts, @@ -340,6 +353,151 @@ static float route_connection_delay( return (net_delay_value); } +static void add_delay_to_matrix( + vtr::Matrix>* matrix, + int delta_x, + int delta_y, + float delay) { + if ((*matrix)[delta_x][delta_y].size() == 1 && (*matrix)[delta_x][delta_y][0] == EMPTY_DELTA) { + //Overwrite empty delta + (*matrix)[delta_x][delta_y][0] = delay; + } else { + //Collect delta + (*matrix)[delta_x][delta_y].push_back(delay); + } +} + +static void generic_compute_matrix_expand( + const RouterDelayProfiler& route_profiler, + vtr::Matrix>& matrix, + int source_x, + int source_y, + int start_x, + int start_y, + int end_x, + int end_y, + const t_router_opts& router_opts, + bool measure_directconnect, + const std::set& allowed_types) { + auto& device_ctx = g_vpr_ctx.device(); + + t_physical_tile_type_ptr src_type = device_ctx.grid[source_x][source_y].type; + bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); + if (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE || !is_allowed_type) { + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + + if (matrix[delta_x][delta_y].empty()) { + //Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + } + } + } + + return; + } + + vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); + + auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid[source_x][source_y].type); + for (int driver_ptc : best_driver_ptcs) { + VTR_ASSERT(driver_ptc != OPEN); + int source_rr_node = get_rr_node_index(device_ctx.rr_node_indices, source_x, source_y, SOURCE, driver_ptc); + auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts); + + bool path_to_all_sinks = true; + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + + if (found_matrix[delta_x][delta_y]) { + continue; + } + + t_physical_tile_type_ptr sink_type = device_ctx.grid[sink_x][sink_y].type; + if (sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + if (matrix[delta_x][delta_y].empty()) { + //Only set empty target if we don't already have a valid delta delay + matrix[delta_x][delta_y].push_back(EMPTY_DELTA); +#ifdef VERBOSE + VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", + "EMPTY", + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + found_matrix[delta_x][delta_y] = true; + } + } else { + bool found_a_sink = false; + auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid[sink_x][sink_y].type); + for (int sink_ptc : best_sink_ptcs) { + VTR_ASSERT(sink_ptc != OPEN); + + int sink_rr_node = get_rr_node_index(device_ctx.rr_node_indices, sink_x, sink_y, SINK, sink_ptc); + + VTR_ASSERT(sink_rr_node != OPEN); + + if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { + //Skip if we shouldn't measure direct connects and a direct connect exists + continue; + } + + if (std::isnan(delays[sink_rr_node])) { + // This sink was not found + continue; + } + +#ifdef VERBOSE + VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", + delay, + delta_x, delta_y, + source_x, source_y, + sink_x, sink_y); +#endif + found_matrix[delta_x][delta_y] = true; + + add_delay_to_matrix(&matrix, delta_x, delta_y, delays[sink_rr_node]); + + found_a_sink = true; + break; + } + + if (!found_a_sink) { + path_to_all_sinks = false; + } + } + } + } + + if (path_to_all_sinks) { + break; + } + } + + for (int sink_x = start_x; sink_x <= end_x; sink_x++) { + for (int sink_y = start_y; sink_y <= end_y; sink_y++) { + int delta_x = abs(sink_x - source_x); + int delta_y = abs(sink_y - source_y); + if (!found_matrix[delta_x][delta_y]) { + add_delay_to_matrix(&matrix, delta_x, delta_y, IMPOSSIBLE_DELTA); + VTR_LOG_WARN("Unable to route between blocks at (%d,%d) and (%d,%d) to characterize delay (setting to %g)\n", + source_x, source_y, sink_x, sink_y, IMPOSSIBLE_DELTA); + } + } + } +} + static void generic_compute_matrix( const RouterDelayProfiler& route_profiler, vtr::Matrix>& matrix, @@ -426,8 +584,14 @@ static vtr::Matrix compute_delta_delays( size_t low_x = std::min(longest_length, mid_x); size_t low_y = std::min(longest_length, mid_y); - size_t high_x = std::max(grid.width() - longest_length, mid_x); - size_t high_y = std::max(grid.height() - longest_length, mid_y); + size_t high_x = mid_x; + size_t high_y = mid_y; + if (longest_length <= grid.width()) { + high_x = std::max(grid.width() - longest_length, mid_x); + } + if (longest_length <= grid.height()) { + high_y = std::max(grid.height() - longest_length, mid_y); + } std::set allowed_types; if (!placer_opts.allowed_tiles_for_delay_model.empty()) { @@ -488,12 +652,12 @@ static vtr::Matrix compute_delta_delays( #ifdef VERBOSE VTR_LOG("Computing from lower left edge (%d,%d):\n", x, y); #endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix_expand(route_profiler, sampled_delta_delays, + x, y, + x, y, + grid.width() - 1, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Find the lowest x location on the bottom edge with a non-empty block src_type = nullptr; @@ -517,60 +681,60 @@ static vtr::Matrix compute_delta_delays( #ifdef VERBOSE VTR_LOG("Computing from left bottom edge (%d,%d):\n", x, y); #endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix_expand(route_profiler, sampled_delta_delays, + x, y, + x, y, + grid.width() - 1, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions B, C, E, F #ifdef VERBOSE VTR_LOG("Computing from low/low:\n"); #endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - low_x, low_y, - low_x, low_y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix_expand(route_profiler, sampled_delta_delays, + low_x, low_y, + low_x, low_y, + grid.width() - 1, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions D, E, G, H #ifdef VERBOSE VTR_LOG("Computing from high/high:\n"); #endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - high_x, high_y, - 0, 0, - high_x, high_y, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix_expand(route_profiler, sampled_delta_delays, + high_x, high_y, + 0, 0, + high_x, high_y, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions A, B, D, E #ifdef VERBOSE VTR_LOG("Computing from high/low:\n"); #endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - high_x, low_y, - 0, low_y, - high_x, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix_expand(route_profiler, sampled_delta_delays, + high_x, low_y, + 0, low_y, + high_x, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions E, F, H, I #ifdef VERBOSE VTR_LOG("Computing from low/high:\n"); #endif - generic_compute_matrix(route_profiler, sampled_delta_delays, - low_x, high_y, - low_x, 0, - grid.width() - 1, high_y, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix_expand(route_profiler, sampled_delta_delays, + low_x, high_y, + low_x, 0, + grid.width() - 1, high_y, + router_opts, + measure_directconnect, allowed_types); vtr::Matrix delta_delays({grid.width(), grid.height()}); for (size_t dx = 0; dx < sampled_delta_delays.dim_size(0); ++dx) { From df2a906f4f5dad266d9c9e152bedeb79e85df262 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 5 Mar 2019 16:17:00 -0800 Subject: [PATCH 102/107] Revert badge to the SymbiFlow Travis-CI. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> Updated README.md Signed-off-by: Alessandro Comodi --- README.md | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 3a3836a4752..0b751972b52 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,14 @@ + +SymbiFlow WIP changes for Verilog to Routing (VTR) +================================================== + +This branch contains work in progress changes for using Verilog to Routing +(VTR) as part of SymbiFlow. + +--- + # Verilog to Routing (VTR) -[![Build Status](https://travis-ci.com/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest) +[![Build Status](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest) ## Introduction The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. From 7ed19bec22b1e829df4bb60c17c199b4240939c3 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 2 Oct 2019 11:06:33 -0700 Subject: [PATCH 103/107] Add explicit namespaces for std and pugixml. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/route/rr_graph_reader.cpp | 4 ++-- vpr/src/route/rr_graph_writer.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index 773c83a260c..cfb0f7e8a82 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -140,7 +140,7 @@ void load_rr_file(const t_graph_type graph_type, VTR_ASSERT(max_chan_width > 0); /* Branches to binary format */ - next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, OPTIONAL); + next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, pugiutil::OPTIONAL); if (next_component) { /* Loads edges, switches, and node look up tables*/ next_component = get_single_child(rr_graph, "switches", loc_data); @@ -150,7 +150,7 @@ void load_rr_file(const t_graph_type graph_type, process_switches(next_component, loc_data); - next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, OPTIONAL); + next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, pugiutil::OPTIONAL); auto filename = get_attribute(next_component, "file", loc_data).as_string(""); VTR_LOG("Using Binary File: %s\n", filename); FILE* fp = fopen(filename, "rb"); diff --git a/vpr/src/route/rr_graph_writer.cpp b/vpr/src/route/rr_graph_writer.cpp index cd705cd3f9a..128fc5afcfb 100644 --- a/vpr/src/route/rr_graph_writer.cpp +++ b/vpr/src/route/rr_graph_writer.cpp @@ -47,7 +47,7 @@ void write_rr_graph(const char* file_name, const std::vector& seg VTR_LOG("RR_Graph binary file %s\n", bin_file_name.c_str()); fb = vtr::fopen(bin_file_name.c_str(), "w"); } - fp.open(file_name, fstream::out | fstream::trunc); + fp.open(file_name, std::fstream::out | std::fstream::trunc); /* Prints out general info for easy error checking*/ if (!fp.is_open() || !fp.good()) { From 3f4b1b15014f511b80b48d2c3b0f0b87c8b13aec Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Tue, 22 Oct 2019 11:40:11 -0700 Subject: [PATCH 104/107] Always mark locations as found if empty. - Use is_empty_type over direct comparisions. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/place/timing_place_lookup.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 98782b7db76..1745f6f6f51 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -383,7 +383,7 @@ static void generic_compute_matrix_expand( t_physical_tile_type_ptr src_type = device_ctx.grid[source_x][source_y].type; bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); - if (src_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE || !is_allowed_type) { + if (is_empty_type(src_type) || !is_allowed_type) { for (int sink_x = start_x; sink_x <= end_x; sink_x++) { for (int sink_y = start_y; sink_y <= end_y; sink_y++) { int delta_x = abs(sink_x - source_x); @@ -425,7 +425,8 @@ static void generic_compute_matrix_expand( } t_physical_tile_type_ptr sink_type = device_ctx.grid[sink_x][sink_y].type; - if (sink_type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) { + if (is_empty_type(sink_type)) { + found_matrix[delta_x][delta_y] = true; if (matrix[delta_x][delta_y].empty()) { //Only set empty target if we don't already have a valid delta delay matrix[delta_x][delta_y].push_back(EMPTY_DELTA); @@ -436,7 +437,6 @@ static void generic_compute_matrix_expand( source_x, source_y, sink_x, sink_y); #endif - found_matrix[delta_x][delta_y] = true; } } else { bool found_a_sink = false; From 664c83358cdef6ff8b6ae56b9b92f797617de21f Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 13 Dec 2019 15:20:02 -0800 Subject: [PATCH 105/107] Revert master+wip to master (2780988d58da6be454364e4a06cff8da8caf09e8) Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- .github/ISSUE_TEMPLATE/bug_report.md | 3 - .github/ISSUE_TEMPLATE/feature_request.md | 3 - .github/ISSUE_TEMPLATE/vtr-change.md | 25 - ODIN_II/exec_wrapper.sh | 72 +- .../.library/output_on_error.conf | 4 +- ODIN_II/verify_odin.sh | 750 +- README.md | 11 +- libs/EXTERNAL/CMakeLists.txt | 2 +- .../libtatum/libtatum/tatum/TimingGraph.cpp | 5 +- libs/libvtrcapnproto/CMakeLists.txt | 1 - libs/libvtrcapnproto/connection_map.capnp | 25 - libs/libvtrutil/src/vtr_geometry.h | 32 +- libs/libvtrutil/src/vtr_geometry.tpp | 43 - libs/libvtrutil/test/test_geometry.cpp | 206 +- utils/fasm/src/main.cpp | 1 - utils/fasm/test/test_fasm.cpp | 2 - utils/route_diag/src/main.cpp | 2 +- vpr/src/base/SetupGrid.cpp | 71 +- vpr/src/base/SetupVPR.cpp | 4 +- vpr/src/base/ShowSetup.cpp | 3 - vpr/src/base/atom_netlist_utils.cpp | 96 +- vpr/src/base/device_grid.cpp | 2 +- vpr/src/base/device_grid.h | 6 +- vpr/src/base/echo_files.cpp | 2 - vpr/src/base/echo_files.h | 1 - vpr/src/base/place_and_route.cpp | 4 +- vpr/src/base/read_options.cpp | 44 +- vpr/src/base/read_options.h | 3 - vpr/src/base/read_place.cpp | 40 +- vpr/src/base/vpr_api.cpp | 8 +- vpr/src/base/vpr_context.h | 4 - vpr/src/base/vpr_tatum_error.cpp | 28 +- vpr/src/base/vpr_types.h | 9 +- vpr/src/draw/buttons.cpp | 2 +- vpr/src/draw/draw.cpp | 36 +- vpr/src/draw/draw.h | 2 + vpr/src/draw/draw_global.h | 2 - vpr/src/draw/draw_types.cpp | 64 +- vpr/src/draw/draw_types.h | 16 +- vpr/src/draw/intra_logic_block.cpp | 127 +- vpr/src/place/initial_placement.cpp | 158 +- vpr/src/place/move_utils.cpp | 4 +- vpr/src/place/place.cpp | 19 +- vpr/src/place/place_delay_model.cpp | 6 +- vpr/src/place/timing_place_lookup.cpp | 254 +- vpr/src/route/bucket.cpp | 213 - vpr/src/route/bucket.h | 338 - vpr/src/route/check_rr_graph.cpp | 5 +- vpr/src/route/connection_box.cpp | 130 - vpr/src/route/connection_box.h | 80 - .../route/connection_box_lookahead_map.cpp | 1124 - vpr/src/route/connection_box_lookahead_map.h | 84 - vpr/src/route/route_common.cpp | 286 +- vpr/src/route/route_common.h | 70 +- vpr/src/route/route_profiling.cpp | 40 - vpr/src/route/route_profiling.h | 4 - vpr/src/route/route_timing.cpp | 207 +- vpr/src/route/route_timing.h | 2 - vpr/src/route/router_delay_profiling.cpp | 4 +- vpr/src/route/router_lookahead.cpp | 3 - vpr/src/route/router_lookahead_map_utils.cpp | 250 - vpr/src/route/router_lookahead_map_utils.h | 206 - vpr/src/route/rr_graph.cpp | 57 +- vpr/src/route/rr_graph.h | 10 +- vpr/src/route/rr_graph_indexed_data.cpp | 17 - vpr/src/route/rr_graph_reader.cpp | 260 +- vpr/src/route/rr_graph_reader.h | 4 +- vpr/src/route/rr_graph_writer.cpp | 45 +- vpr/src/route/rr_node.h | 2 +- vpr/src/timing/PreClusterDelayCalculator.h | 3 +- vpr/src/timing/atom_delay_calc.inl | 6 +- vpr/src/timing/timing_graph_builder.cpp | 30 +- vpr/src/timing/timing_util.cpp | 4 - vpr/src/util/vpr_utils.cpp | 23 +- vpr/src/util/vpr_utils.h | 10 +- vpr/test/test_vpr.cpp | 2 - .../benchmarks/tests/riscv_core_lut6.blif | 19187 ++++++++++++++++ .../strong_absorb_buffers/config/config.txt | 31 + .../config/golden_results.txt | 3 + .../config/golden_results.txt | 4 +- .../strong_bidir/config/golden_results.txt | 8 +- .../strong_binary/config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 16 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 18 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 2 +- .../strong_depop/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../strong_fc_abs/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 40 +- .../config/golden_results.txt | 12 +- .../config/golden_results.txt | 12 +- .../config/golden_results.txt | 6 +- .../config/golden_results.txt | 2 +- .../strong_mcnc/config/golden_results.txt | 6 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../strong_pack/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../strong_power/config/golden_results.txt | 4 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 4 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../strong_sdc/config/golden_results.txt | 12 +- .../config/golden_results.txt | 12 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 26 +- .../strong_timing/config/golden_results.txt | 2 +- .../config/golden_results.txt | 6 +- .../strong_titan/config/golden_results.txt | 2 +- .../config/golden_results.txt | 2 +- .../config/golden_results.txt | 8 +- .../config/golden_results.txt | 4 +- .../vtr_reg_strong/task_list.txt | 2 + 133 files changed, 20902 insertions(+), 4328 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/vtr-change.md delete mode 100644 libs/libvtrcapnproto/connection_map.capnp delete mode 100644 vpr/src/route/bucket.cpp delete mode 100644 vpr/src/route/bucket.h delete mode 100644 vpr/src/route/connection_box.cpp delete mode 100644 vpr/src/route/connection_box.h delete mode 100644 vpr/src/route/connection_box_lookahead_map.cpp delete mode 100644 vpr/src/route/connection_box_lookahead_map.h delete mode 100644 vpr/src/route/router_lookahead_map_utils.cpp delete mode 100644 vpr/src/route/router_lookahead_map_utils.h create mode 100644 vtr_flow/benchmarks/tests/riscv_core_lut6.blif create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt create mode 100644 vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index 1e5584ab1b6..dc1b48f28cc 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -1,9 +1,6 @@ --- name: Bug report about: Create a report to help us improve -title: '' -labels: '' -assignees: '' --- diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md index 7523b9efbf8..96a3a6f322e 100644 --- a/.github/ISSUE_TEMPLATE/feature_request.md +++ b/.github/ISSUE_TEMPLATE/feature_request.md @@ -1,9 +1,6 @@ --- name: Feature request about: Suggest an idea for this project -title: '' -labels: '' -assignees: '' --- diff --git a/.github/ISSUE_TEMPLATE/vtr-change.md b/.github/ISSUE_TEMPLATE/vtr-change.md deleted file mode 100644 index 74d5ec9e8f6..00000000000 --- a/.github/ISSUE_TEMPLATE/vtr-change.md +++ /dev/null @@ -1,25 +0,0 @@ ---- -name: VTR change -about: Describe purpose and lifecycle of a local change we made to VTR -title: '' -labels: '' -assignees: '' - ---- - -### Why did we need this? (what does this change enable us to do) - - -### What did it change? - - -### Should it be merged upstream - if not, when can we delete it? - -### What is needed to get this merged / deleted? - -* [ ] is the implementation work to make suitable for merging / deletion completed? -* [ ] Is there an associated test? -* [ ] is this currently part of the Conda package? -* [ ] is this properly cleaned up in our local repositories? - -### Tracker / branch / PR & other useful links diff --git a/ODIN_II/exec_wrapper.sh b/ODIN_II/exec_wrapper.sh index 711f9f084d6..20c20564e06 100755 --- a/ODIN_II/exec_wrapper.sh +++ b/ODIN_II/exec_wrapper.sh @@ -23,6 +23,8 @@ PERF_EXEC="perf stat record -a -d -d -d -o" GDB_EXEC="gdb --args" EXEC_PREFIX="" +TOOL_LIST="" + TEST_NAME="N/A" LOG="" LOG_FILE="" @@ -98,6 +100,7 @@ Usage: ./exec_wrapper.sh [options] --time_limit * stops Odin after X seconds --limit_ressource * limit ressource usage using ulimit -m (25% of hrdw memory) and nice value of 19 --verbosity [0, 1, 2] * [0] no output, [1] output on error, [2] output the log to stdout + --no_color * force no color on output " } @@ -213,6 +216,12 @@ then _exit_with_code "-1" fi +if [[ -t 1 ]] && [[ -t 2 ]] && [[ ! -p /dev/stdout ]] && [[ ! -p /dev/stderr ]] +then + COLORIZE_OUTPUT="on" + log_it "Using colorized output\n" +fi + while [[ "$#" > 0 ]] do case $1 in @@ -242,6 +251,10 @@ do RESTRICT_RESSOURCE="on" ;; + --no_color) + COLORIZE_OUTPUT="off" + ;; + --verbosity) case "_$2" in _0) VERBOSE="0";; @@ -267,14 +280,17 @@ do else case $2 in valgrind) + TOOL_LIST="valgrind ${TOOL_LIST}" EXEC_PREFIX="${VALGRIND_EXEC} ${EXEC_PREFIX}" ;; gdb) + TOOL_LIST="gdb ${TOOL_LIST}" USE_TIMEOUT="off" USE_LOGS="off" EXEC_PREFIX="${GDB_EXEC} ${EXEC_PREFIX}" ;; perf) + TOOL_LIST="perf ${TOOL_LIST}" EXEC_PREFIX="${PERF_EXEC} ${EXEC_PREFIX}" shift ;; @@ -302,13 +318,6 @@ then restrict_ressource fi - -if [[ -t 1 ]] && [[ -t 2 ]] && [[ ! -p /dev/stdout ]] && [[ ! -p /dev/stderr ]] -then - COLORIZE_OUTPUT="on" - log_it "Using colorized output\n" -fi - if [ "${USE_LOGS}" == "on" ] then if [ "_${LOG_FILE}" == "_" ] @@ -331,12 +340,14 @@ fi if [ "${USE_TIME}" == "on" ] then + TOOL_LIST="time ${TOOL_LIST}" EXEC_PREFIX="${TIME_EXEC} --output=${LOG_FILE} --append ${EXEC_PREFIX}" log_it "running with /bin/time\n" fi if [ "${USE_TIMEOUT}" == "on" ] then + TOOL_LIST="timeout ${TOOL_LIST}" EXEC_PREFIX="timeout ${TIME_LIMIT} ${EXEC_PREFIX}" log_it "running with timeout ${TIME_LIMIT}\n" fi @@ -352,23 +363,52 @@ then log_it "Must define a path to a valid argument file" dump_log else - _ARGS=$(cat ${ARG_FILE}) - if [ "${USE_LOGS}" == "on" ] + failed_requirements="" + # test all necessary tool + for tool_used in ${TOOL_LIST} + do + which ${tool_used} &> /dev/null + if [ "$?" != "0" ]; + then + failed_requirements="${tool_used} ${failed_requirements}" + fi + done + + if [ "_${failed_requirements}" != "_" ]; then - if [ "${VERBOSE}" == "2" ] + if [ "${USE_LOGS}" == "on" ] then - ${EXEC_PREFIX} ${_ARGS} 2>&1 | tee ${LOG_FILE} + if [ "${VERBOSE}" == "2" ] + then + echo "missing \"${failed_requirements}\"" | tee ${LOG_FILE} + else + echo "missing \"${failed_requirements}\"" &>> ${LOG_FILE} + fi else - ${EXEC_PREFIX} ${_ARGS} &>> ${LOG_FILE} + echo "missing \"${failed_requirements}\"" fi + + EXIT_CODE="-1" + pretty_print_status "Missing package: ${failed_requirements}" + else - ${EXEC_PREFIX} ${_ARGS} + _ARGS=$(cat ${ARG_FILE}) + if [ "${USE_LOGS}" == "on" ] + then + if [ "${VERBOSE}" == "2" ] + then + ${EXEC_PREFIX} ${_ARGS} 2>&1 | tee ${LOG_FILE} + else + ${EXEC_PREFIX} ${_ARGS} &>> ${LOG_FILE} + fi + else + ${EXEC_PREFIX} ${_ARGS} + fi + EXIT_CODE=$? + display "${EXIT_CODE}" fi - EXIT_CODE=$? fi -display "${EXIT_CODE}" - EXIT_STATUS=0 if [ "${EXIT_CODE}" != "0" ] then diff --git a/ODIN_II/regression_test/.library/output_on_error.conf b/ODIN_II/regression_test/.library/output_on_error.conf index 7db9a08a2f6..c13223adb16 100644 --- a/ODIN_II/regression_test/.library/output_on_error.conf +++ b/ODIN_II/regression_test/.library/output_on_error.conf @@ -1,2 +1,2 @@ -script_synthesis_params=--verbosity 1 -script_simulation_params=--verbosity 1 \ No newline at end of file +script_synthesis_params=--verbosity 1 --no_color +script_simulation_params=--verbosity 1 --no_color \ No newline at end of file diff --git a/ODIN_II/verify_odin.sh b/ODIN_II/verify_odin.sh index 1f1ad028cbc..ec61de0cf03 100755 --- a/ODIN_II/verify_odin.sh +++ b/ODIN_II/verify_odin.sh @@ -23,7 +23,17 @@ ODIN_EXEC="${THIS_DIR}/odin_II" BENCHMARK_DIR="${REGRESSION_DIR}/benchmark" -TEST_DIR_LIST=$(ls -d ${BENCHMARK_DIR}/*/ | sed "s/\/$//g" | xargs -n1 -I TEST_FILE /bin/bash -c 'printf "$(basename TEST_FILE) "') + +VTR_REG_DIR="${THIS_DIR}/../vtr_flow/tasks/regression_tests" +VTR_REG_LIST=$(ls ${VTR_REG_DIR} | grep "vtr_reg") + +SUITE_DIR="${BENCHMARK_DIR}/suite" +SUITE_LIST=$(ls ${SUITE_DIR}) + +TASK_DIR="${BENCHMARK_DIR}/task" +TASK_LIST=$(ls ${TASK_DIR}) + +PREVIOUS_RUN_DIR="" NEW_RUN_DIR="${REGRESSION_DIR}/run001/" ############################################## @@ -63,12 +73,14 @@ _prt_cur_arg() { ############## # defaults _TEST="" +_TEST_NAME="" +_SUBTEST_LIST="" _NUMBER_OF_PROCESS="1" _SIM_COUNT="1" _RUN_DIR_OVERRIDE="" +_EXTRA_CONFIG="" -_CONFIG_OVERRIDE="" - +_OVERRIDE_CONFIG="off" _GENERATE_BENCH="off" _GENERATE_OUTPUT="off" _GENERATE_CONFIG="off" @@ -78,22 +90,41 @@ function help() { printf "Called program with $INPUT Usage: - $0 [ OPTIONS / FLAGS ] + $0 [ OPTIONS / FLAGS ] [ SUBTEST_LIST ... ] + SUBTEST_LIST + should be a list of the form < task_name/test_file_name/architecture_file_name > + passing this in will limit a task to a subset of test + current: $(_prt_cur_arg ${_SUBTEST_LIST}) - OPTIONS: - -h|--help $(_prt_cur_arg off) print this - -t|--test < test name > $(_prt_cur_arg ${_TEST}) Test name is one of ( ${TEST_DIR_LIST} heavy_suite light_suite full_suite vtr_basic vtr_strong pre_commit pre_merge) - -j|--nb_of_process < N > $(_prt_cur_arg ${_NUMBER_OF_PROCESS}) Number of process requested to be used - -d|--output_dir < /abs/path > $(_prt_cur_arg ${_RUN_DIR_OVERRIDE}) Change the run directory output - -C|--config $(_prt_cur_arg ${_CONFIG_OVERRIDE}) Add a config override file - - FLAGS: + FLAGS -g|--generate_bench $(_prt_cur_arg ${_GENERATE_BENCH}) Generate input and output vector for test -o|--generate_output $(_prt_cur_arg ${_GENERATE_OUTPUT}) Generate output vector for test given its input vector -b|--build_config $(_prt_cur_arg ${_GENERATE_CONFIG}) Generate a config file for a given directory -c|--clean $(_prt_cur_arg off ) Clean temporary directory -f|--force_simulate $(_prt_cur_arg ${_FORCE_SIM}) Force the simulation to be executed regardless of the config + --override $(_prt_cur_arg ${_OVERRIDE_CONFIG}) if a config file is passed in, override arguments rather than append + + OPTIONS + -h|--help $(_prt_cur_arg off) print this + -j|--nb_of_process < N > $(_prt_cur_arg ${_NUMBER_OF_PROCESS}) Number of process requested to be used + -d|--output_dir < /abs/path > $(_prt_cur_arg ${_RUN_DIR_OVERRIDE}) Change the run directory output + -C|--config $(_prt_cur_arg ${_EXTRA_CONFIG}) Add a config file to append to the config for the tests + -t|--test < test name > $(_prt_cur_arg ${_TEST}) Test name is either a absolute or relative path to + a directory containing a task.conf, task_list.conf + (see CONFIG FILE HELP) or one of the following predefined test + + AVAILABLE_TEST: + + regression_test/benchmark/suite/ +$( echo "${SUITE_LIST}" | awk '{print "\t " $0}') + + regression_test/benchmark/task/ +$( echo "${TASK_LIST}" | awk '{print "\t " $0}') + + vtr_reg_ +$( echo "${VTR_REG_LIST}" | awk '{print "\t " substr($0,9)}') + CONFIG FILE HELP: " @@ -131,11 +162,11 @@ function init_temp() { OUTPUT_DIRECTORY=${_RUN_DIR_OVERRIDE} fi - last_run=$(find ${OUTPUT_DIRECTORY}/run* -maxdepth 0 -type d 2>/dev/null | tail -1 ) + PREVIOUS_RUN_DIR=$(find ${OUTPUT_DIRECTORY}/run* -maxdepth 0 -type d 2>/dev/null | tail -1 ) n="1" - if [ "_${last_run}" != "_" ] + if [ "_${PREVIOUS_RUN_DIR}" != "_" ] then - n=$(echo ${last_run##${OUTPUT_DIRECTORY}/run} | awk '{print $0 + 1}') + n=$(echo ${PREVIOUS_RUN_DIR##${OUTPUT_DIRECTORY}/run} | awk '{print $0 + 1}') fi NEW_RUN_DIR=${OUTPUT_DIRECTORY}/run$(printf "%03d" $n) @@ -150,6 +181,11 @@ function create_temp() { rm -Rf ${REGRESSION_DIR}/latest || /bin/true ln -s ${NEW_RUN_DIR} ${REGRESSION_DIR}/latest + + # put in the passed parameter for keepsake + echo ${_TEST} > ${NEW_RUN_DIR}/cmd.task + echo "=========" + echo "$0 ${INPUT}" >> ${NEW_RUN_DIR}/cmd.task fi } @@ -212,94 +248,108 @@ function mv_failed() { fi } + function parse_args() { + PARSE_SUBTEST="off" while [[ "$#" > 0 ]] do - case $1 in + if [ ${PARSE_SUBTEST} == "on" ]; + then + # parse subtest + _SUBTEST_LIST="$1 ${_SUBTEST_LIST}" + shift + else + # parse [ OPTIONS / FLAGS ] + case $1 in - # Help Desk - -h|--help) - echo "Printing Help information" - help - _exit_with_code "0" + # Help Desk + -h|--help) + echo "Printing Help information" + help + _exit_with_code "0" - - ## directory in benchmark - ;;-t|--test) - # this is handled down stream - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi + + ## directory in benchmark + ;;-t|--test) + # this is handled down stream + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _TEST="$2" + shift + + ;;-d|--output_dir) + + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _RUN_DIR_OVERRIDE=$2 - _TEST="$2" - shift + if [ ! -d "${_RUN_DIR_OVERRIDE}" ] + then + echo "Directory ${_RUN_DIR_OVERRIDE} does not exist" + _exit_with_code "-1" + fi - ;;-d|--output_dir) + shift - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi - - _RUN_DIR_OVERRIDE=$2 + ;;-C|--config) - if [ ! -d "${_RUN_DIR_OVERRIDE}" ] - then - echo "Directory ${_RUN_DIR_OVERRIDE} does not exist" - _exit_with_code "-1" - fi + if [ "_$2" == "_" ] + then + echo "empty argument for $1" + _exit_with_code "-1" + fi + + _EXTRA_CONFIG=$2 + echo "Reading extra config directive from ${_EXTRA_CONFIG}" - shift + shift - ;;-C|--config) + ## number + ;;-j|--nb_of_process) + _NUMBER_OF_PROCESS=$(_flag_is_number $1 $2) + echo "Using [$2] processors for this benchmarking suite" + shift - if [ "_$2" == "_" ] - then - echo "empty argument for $1" - _exit_with_code "-1" - fi - - _CONFIG_OVERRIDE=$2 - echo "Reading override from ${_CONFIG_OVERRIDE}" + # Boolean flags + ;;-g|--generate_bench) + _GENERATE_BENCH="on" + echo "generating output vector for test given predefined input" - shift + ;;-o|--generate_output) + _GENERATE_OUTPUT="on" + echo "generating input and output vector for test" - ## number - ;;-j|--nb_of_process) - _NUMBER_OF_PROCESS=$(_flag_is_number $1 $2) - echo "Using [$2] processors for this benchmarking suite" - shift + ;;-b|--build_config) + _GENERATE_CONFIG="on" + echo "generating a config file for test directory" - # Boolean flags - ;;-g|--generate_bench) - _GENERATE_BENCH="on" - echo "generating output vector for test given predefined input" + ;;-c|--clean) + echo "Cleaning temporary run in directory" + cleanup_temp - ;;-o|--generate_output) - _GENERATE_OUTPUT="on" - echo "generating input and output vector for test" + ;;-f|--force_simulate) + _FORCE_SIM="on" + echo "Forcing Simulation" - ;;-b|--build_config) - _GENERATE_CONFIG="on" - echo "generating a config file for test directory" + ;;--override) + _OVERRIDE_CONFIG="on" + echo "Forcing override of config" - ;;-c|--clean) - echo "Cleaning temporary run in directory" - cleanup_temp - - ;;-f|--force_simulate) - _FORCE_SIM="on" - echo "Forcing Simulation" + ;;*) + PARSE_SUBTEST="on" + esac - ;;*) - echo "Unknown parameter passed: $1" - help - _exit_with_code "-1" - esac - shift + # keep the subtest in case we caught the end of options and flags + [ ${PARSE_SUBTEST} != "on" ] && shift + fi done } @@ -440,11 +490,21 @@ function populate_arg_from_file() { IFS=${OLD_IFS} fi - _regression_params=$(echo "${_local_regression_params} ") - _script_simulation_params=$(echo "${_local_script_simulation_params} ") - _script_synthesis_params=$(echo "${_local_script_synthesis_params} ") - _synthesis_params=$(echo "${_local_synthesis_params} ") - _simulation_params=$(echo "${_local_simulation_params} ") + if [ "${_OVERRIDE_CONFIG}" == "on" ]; + then + _regression_params=$(echo "${_local_regression_params} ") + _script_simulation_params=$(echo "${_local_script_simulation_params} ") + _script_synthesis_params=$(echo "${_local_script_synthesis_params} ") + _synthesis_params=$(echo "${_local_synthesis_params} ") + _simulation_params=$(echo "${_local_simulation_params} ") + else + _regression_params=$(echo "${_local_regression_params} ${_regression_params} ") + _script_simulation_params=$(echo "${_local_script_simulation_params} ${_script_simulation_params} ") + _script_synthesis_params=$(echo "${_local_script_synthesis_params} ${_script_synthesis_params}") + _synthesis_params=$(echo "${_local_synthesis_params} ${_synthesis_params}") + _simulation_params=$(echo "${_local_simulation_params} ${_simulation_params}") + fi + _circuit_list=$(echo "${_circuit_list} ") _arch_list=$(echo "${_arch_list} ") _circuit_dir=$(echo "${THIS_DIR}/${_circuit_dir}") @@ -560,7 +620,6 @@ function run_bench_in_parallel() { function sim() { - ########################################### # find the benchmark benchmark_dir=$1 @@ -577,283 +636,314 @@ function sim() { benchmark_dir=$(readlink -f "${benchmark_dir}") bench_name=$(basename ${benchmark_dir}) - echo "Task is: ${bench_name}" - ########################################## - # setup the parameters + # check if we only run some subtask + run_benchmark="off" + if [ "_${_SUBTEST_LIST}" == "_" ]; + then + run_benchmark="on" + else + for subtest in ${_SUBTEST_LIST}; + do + if [ "_${subtest%%/*}" == "_${bench_name}" ] + then + run_benchmark="on" + break; + fi + done + fi + + if [ "${run_benchmark}" == "on" ]; + then + echo "Task is: ${bench_name}" - init_args_for_test - populate_arg_from_file "${benchmark_dir}/task.conf" + ########################################## + # setup the parameters - ########################################## - # use the overrides from the user - if [ "_${_CONFIG_OVERRIDE}" != "_" ] - then - _CONFIG_OVERRIDE=$(readlink -f ${_CONFIG_OVERRIDE}) - if [ ! -f ${_CONFIG_OVERRIDE} ] + init_args_for_test + populate_arg_from_file "${benchmark_dir}/task.conf" + + ########################################## + # use the overrides from the user + if [ "_${_EXTRA_CONFIG}" != "_" ] then - echo "Passed in an invalid global configuration file ${_CONFIG_OVERRIDE}" - _exit_with_code "-1" - else - populate_arg_from_file "${_CONFIG_OVERRIDE}" + _EXTRA_CONFIG=$(readlink -f ${_EXTRA_CONFIG}) + if [ ! -f ${_EXTRA_CONFIG} ] + then + echo "Passed in an invalid global configuration file ${_EXTRA_CONFIG}" + _exit_with_code "-1" + else + populate_arg_from_file "${_EXTRA_CONFIG}" + fi fi - fi - #################################### - # parse the function commands passed - _threads=${_NUMBER_OF_PROCESS} - _generate_bench="off" - _generate_output="off" - _concat_circuit_list="off" - _synthesis="on" - _simulation="on" + #################################### + # parse the function commands passed + _threads=${_NUMBER_OF_PROCESS} + _generate_bench="off" + _generate_output="off" + _concat_circuit_list="off" + _synthesis="on" + _simulation="on" + + ########################################## + # populate the wrapper command using the configs + for _regression_param in ${_regression_params} + do + case ${_regression_param} in - ########################################## - # populate the wrapper command using the configs - for _regression_param in ${_regression_params} - do - case ${_regression_param} in + --concat_circuit_list) + _concat_circuit_list="on" + ;; - --concat_circuit_list) - _concat_circuit_list="on" - ;; + --generate_bench) + echo "This test will have the input and output regenerated" + _generate_bench="on" + ;; - --generate_bench) - echo "This test will have the input and output regenerated" - _generate_bench="on" - ;; + --generate_output) + echo "This test will have the output regenerated" + _generate_output="on" + ;; - --generate_output) - echo "This test will have the output regenerated" - _generate_output="on" - ;; + --disable_simulation) + echo "This test will not be simulated" + if [ "_${_FORCE_SIM}" == "on" ] + then + echo "WARNING: This test will be forcefully simulated, unexpected results may occur" + _simulation="on" + else + _simulation="off" + fi + ;; + + --disable_parallel_jobs) + echo "This test will not be multithreaded" + _threads="1" + ;; + + --include_default_arch) + _arch_list="no_arch ${_arch_list}" + ;; - --disable_simulation) - echo "This test will not be simulated" - if [ "_${_FORCE_SIM}" == "on" ] - then - echo "WARNING: This test will be forcefully simulated, unexpected results may occur" - _simulation="on" - else - _simulation="off" - fi - ;; - - --disable_parallel_jobs) - echo "This test will not be multithreaded" - _threads="1" + *) + echo "Unknown internal parameter passed: ${_regression_param}" + config_help + _exit_with_code "-1" + ;; + esac + done + + ########################################## + # setup defaults + global_synthesis_failure="${NEW_RUN_DIR}/synthesis_failures" + global_simulation_failure="${NEW_RUN_DIR}/simulation_failures" + + wrapper_synthesis_file_name="wrapper_synthesis_params" + wrapper_simulation_generate_io_file_name="wrapper_simulation_generate_io_file_name" + wrapper_simulation_generate_output_file_name="wrapper_simulation_generate_output_file_name" + wrapper_simulation_predefined_io_file_name="wrapper_simulation_predefined_io_file_name" + + circuit_list_temp="" + if [ ${_concat_circuit_list} == "on" ] + then + circuit_list_temp="$(echo ${_circuit_list} | sed 's/\n/ /g')" + _circuit_list=${bench_name} + fi + + for circuit in $(echo ${_circuit_list}) + do + circuit_dir=$(dirname ${circuit}) + circuit_file=$(basename ${circuit}) + input_verilog_file="" + input_blif_file="" + + case "${circuit_file}" in + *.v) + input_verilog_file="${circuit}" + _synthesis="on" ;; - - --include_default_arch) - _arch_list="no_arch ${_arch_list}" + *.blif) + input_blif_file="${circuit}" + # disable synthesis for blif files + _synthesis="off" ;; - - *) - echo "Unknown internal parameter passed: ${_regression_param}" - config_help - _exit_with_code "-1" + *) + if [ ${_concat_circuit_list} == "on" ] + then + input_verilog_file="${circuit_list_temp}" + _synthesis="on" + else + echo "Invalid circuit passed in: ${circuit}, skipping" + continue + fi ;; - esac - done - - ########################################## - # setup defaults - global_synthesis_failure="${NEW_RUN_DIR}/synthesis_failures" - global_simulation_failure="${NEW_RUN_DIR}/simulation_failures" + esac + circuit_name="${circuit_file%.*}" - wrapper_synthesis_file_name="wrapper_synthesis_params" - wrapper_simulation_generate_io_file_name="wrapper_simulation_generate_io_file_name" - wrapper_simulation_generate_output_file_name="wrapper_simulation_generate_output_file_name" - wrapper_simulation_predefined_io_file_name="wrapper_simulation_predefined_io_file_name" - circuit_list_temp="" - if [ ${_concat_circuit_list} == "on" ] - then - circuit_list_temp="$(echo ${_circuit_list} | sed 's/\n/ /g')" - _circuit_list=${bench_name} - fi + # lookup for input and output vector files to do comparison + input_vector_file="${circuit_dir}/${circuit_name}_input" + output_vector_file="${circuit_dir}/${circuit_name}_output" - for circuit in $(echo ${_circuit_list}) - do - circuit_dir=$(dirname ${circuit}) - circuit_file=$(basename ${circuit}) - input_verilog_file="" - input_blif_file="" - - case "${circuit_file}" in - *.v) - input_verilog_file="${circuit}" - _synthesis="on" - ;; - *.blif) - input_blif_file="${circuit}" - # disable synthesis for blif files - _synthesis="off" - ;; - *) - if [ ${_concat_circuit_list} == "on" ] + for arches in $(echo ${_arch_list}) + do + arch_cmd="" + if [ -e ${arches} ] then - input_verilog_file="${circuit_list_temp}" - _synthesis="on" - else - echo "Invalid circuit passed in: ${circuit}, skipping" - continue + arch_cmd="-a ${arches}" fi - ;; - esac - circuit_name="${circuit_file%.*}" + arch_name=$(basename ${arches%.*}) - # lookup for input and output vector files to do comparison - input_vector_file="${circuit_dir}/${circuit_name}_input" - output_vector_file="${circuit_dir}/${circuit_name}_output" + TEST_FULL_REF="${bench_name}/${circuit_name}/${arch_name}" - for arches in $(echo ${_arch_list}) - do - arch_cmd="" - if [ -e ${arches} ] - then - arch_cmd="-a ${arches}" - fi + run_this_test="on" - arch_name=$(basename ${arches%.*}) - - TEST_FULL_REF="${bench_name}/${circuit_name}/${arch_name}" - DIR="${NEW_RUN_DIR}/${TEST_FULL_REF}" - mkdir -p $DIR - - ############################### - # Synthesis - if [ "${_synthesis}" == "on" ] - then - - # if synthesis was on, we need to specify a blif output name - input_blif_file="${DIR}/${circuit_name}.blif" - - synthesis_params_file=${DIR}/synthesis_params - - wrapper_command="${WRAPPER_EXEC} - ${_script_synthesis_params} - --log_file ${DIR}/synthesis.log - --test_name ${TEST_FULL_REF} - --failure_log ${global_synthesis_failure}.log - ${synthesis_params_file}" - - synthesis_command="${ODIN_EXEC} - ${_synthesis_params} - ${arch_cmd} - -V ${input_verilog_file} - -o ${input_blif_file} - -sim_dir ${DIR}" - - _echo_args "${synthesis_command}" > ${synthesis_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_synthesis_file_name} - fi - ############################### - # Simulation - if [ "${_simulation}" == "on" ] - then - simulation_params_file=${DIR}/simulation_params - - wrapper_command="${WRAPPER_EXEC} - ${_script_simulation_params} - --log_file ${DIR}/simulation.log - --test_name ${TEST_FULL_REF} - --failure_log ${global_simulation_failure}.log - ${simulation_params_file}" - - simulation_command="${ODIN_EXEC} - ${_simulation_params} - ${arch_cmd} - -b ${input_blif_file} - -sim_dir ${DIR}" - - if [ "${_GENERATE_BENCH}" == "on" ] || [ ! -f ${input_vector_file} ] + if [ "_${_SUBTEST_LIST}" != "_" ]; then - _echo_args "${simulation_command}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_io_file_name} + echo ${_SUBTEST_LIST} | grep "${TEST_FULL_REF}" &> /dev/null + [ "$?" != "0" ] && run_this_test="off" + fi - elif [ "${_GENERATE_OUTPUT}" == "on" ] || [ ! -f ${output_vector_file} ] + if [ "${run_this_test}" == "on" ]; then - _echo_args "${simulation_command} -t ${input_vector_file}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_output_file_name} - else - _echo_args "${simulation_command} -t ${input_vector_file} -T ${output_vector_file}" > ${simulation_params_file} - _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_predefined_io_file_name} + DIR="${NEW_RUN_DIR}/${TEST_FULL_REF}" + mkdir -p $DIR + ############################### + # Synthesis + if [ "${_synthesis}" == "on" ] + then + + # if synthesis was on, we need to specify a blif output name + input_blif_file="${DIR}/${circuit_name}.blif" + + synthesis_params_file=${DIR}/synthesis_params + + wrapper_command="${WRAPPER_EXEC} + ${_script_synthesis_params} + --log_file ${DIR}/synthesis.log + --test_name ${TEST_FULL_REF} + --failure_log ${global_synthesis_failure}.log + ${synthesis_params_file}" + + synthesis_command="${ODIN_EXEC} + ${_synthesis_params} + ${arch_cmd} + -V ${input_verilog_file} + -o ${input_blif_file} + -sim_dir ${DIR}" + + _echo_args "${synthesis_command}" > ${synthesis_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_synthesis_file_name} + fi + ############################### + # Simulation + if [ "${_simulation}" == "on" ] + then + simulation_params_file=${DIR}/simulation_params + + wrapper_command="${WRAPPER_EXEC} + ${_script_simulation_params} + --log_file ${DIR}/simulation.log + --test_name ${TEST_FULL_REF} + --failure_log ${global_simulation_failure}.log + ${simulation_params_file}" + + simulation_command="${ODIN_EXEC} + ${_simulation_params} + ${arch_cmd} + -b ${input_blif_file} + -sim_dir ${DIR}" + + if [ "${_GENERATE_BENCH}" == "on" ] || [ ! -f ${input_vector_file} ] + then + _echo_args "${simulation_command}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_io_file_name} + + elif [ "${_GENERATE_OUTPUT}" == "on" ] || [ ! -f ${output_vector_file} ] + then + _echo_args "${simulation_command} -t ${input_vector_file}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_generate_output_file_name} + + else + _echo_args "${simulation_command} -t ${input_vector_file} -T ${output_vector_file}" > ${simulation_params_file} + _echo_args "${wrapper_command}" > ${DIR}/${wrapper_simulation_predefined_io_file_name} + + fi + fi fi + done + done - fi - - done - done - - #synthesize the circuits - if [ "${_synthesis}" == "on" ] - then - run_bench_in_parallel \ - "Synthesis" \ - "${_threads}" \ - "${global_synthesis_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_synthesis_file_name})" - fi + #synthesize the circuits + if [ "${_synthesis}" == "on" ] + then + run_bench_in_parallel \ + "Synthesis" \ + "${_threads}" \ + "${global_synthesis_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_synthesis_file_name})" + fi - if [ "${_simulation}" == "on" ] - then + if [ "${_simulation}" == "on" ] + then - run_bench_in_parallel \ - "Generate_IO_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_io_file_name})" - - run_bench_in_parallel \ - "Generate_Output_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_output_file_name})" - - run_bench_in_parallel \ - "Predefined_IO_Simulation" \ - "${_threads}" \ - "${global_simulation_failure}" \ - "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_predefined_io_file_name})" + run_bench_in_parallel \ + "Generate_IO_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_io_file_name})" + + run_bench_in_parallel \ + "Generate_Output_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_generate_output_file_name})" + + run_bench_in_parallel \ + "Predefined_IO_Simulation" \ + "${_threads}" \ + "${global_simulation_failure}" \ + "$(formated_find ${NEW_RUN_DIR}/${bench_name} ${wrapper_simulation_predefined_io_file_name})" - fi + fi - INPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name input_vectors)" - if [ "${_simulation}" == "on" ] && [ "_${INPUT_VECTOR_LIST}" != "_" ] - then - mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors + INPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name input_vectors)" + if [ "${_simulation}" == "on" ] && [ "_${INPUT_VECTOR_LIST}" != "_" ] + then + mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors - # move the input vectors - for sim_input_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "input_vectors") - do - BM_DIR=$(dirname ${sim_input_vectors}) - BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_input" + # move the input vectors + for sim_input_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "input_vectors") + do + BM_DIR=$(dirname ${sim_input_vectors}) + BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_input" - cp ${sim_input_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} - mv ${sim_input_vectors} ${BM_DIR}/${BM_NAME} - - done - fi + cp ${sim_input_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} + mv ${sim_input_vectors} ${BM_DIR}/${BM_NAME} + + done + fi - OUTPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name output_vectors)" - if [ "${_simulation}" == "on" ] && [ "_${OUTPUT_VECTOR_LIST}" != "_" ] - then - mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors + OUTPUT_VECTOR_LIST="$(find ${NEW_RUN_DIR}/${bench_name}/ -name output_vectors)" + if [ "${_simulation}" == "on" ] && [ "_${OUTPUT_VECTOR_LIST}" != "_" ] + then + mkdir -p ${NEW_RUN_DIR}/${bench_name}/vectors - # move the output vectors - for sim_output_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "output_vectors") - do - BM_DIR=$(dirname ${sim_output_vectors}) - BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_output" + # move the output vectors + for sim_output_vectors in $(find ${NEW_RUN_DIR}/${bench_name}/ -name "output_vectors") + do + BM_DIR=$(dirname ${sim_output_vectors}) + BM_NAME="$(basename $(readlink -f ${BM_DIR}/..))_output" - cp ${sim_output_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} - mv ${sim_output_vectors} ${BM_DIR}/${BM_NAME} + cp ${sim_output_vectors} ${NEW_RUN_DIR}/${bench_name}/vectors/${BM_NAME} + mv ${sim_output_vectors} ${BM_DIR}/${BM_NAME} - done + done + fi fi } @@ -914,7 +1004,7 @@ function run_suite() { input_path=$(ls -d -1 ${THIS_DIR}/${input_path} 2> /dev/null) ;; esac - + input_list=( ${input_list[@]} ${input_path[@]} ) done @@ -931,7 +1021,6 @@ function run_suite() { ;; *) - # bash expand when possible echo "no such Directory for task: ${current_input}" ;; esac @@ -978,8 +1067,9 @@ then fi _TEST=$(readlink -f ${_TEST}) +_TEST_NAME=$(basename ${_TEST}) -echo "Task: ${_TEST}" +echo "Task: ${_TEST_NAME} (${_TEST})" input_list=( "${_TEST}" ) diff --git a/README.md b/README.md index 0b751972b52..3a3836a4752 100644 --- a/README.md +++ b/README.md @@ -1,14 +1,5 @@ - -SymbiFlow WIP changes for Verilog to Routing (VTR) -================================================== - -This branch contains work in progress changes for using Verilog to Routing -(VTR) as part of SymbiFlow. - ---- - # Verilog to Routing (VTR) -[![Build Status](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.com/SymbiFlow/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest) +[![Build Status](https://travis-ci.com/verilog-to-routing/vtr-verilog-to-routing.svg?branch=master)](https://travis-ci.org/verilog-to-routing/vtr-verilog-to-routing) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/?badge=latest) ## Introduction The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development. diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index ebf52b0e3c7..38a14d76e25 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -8,7 +8,7 @@ add_subdirectory(libsdcparse) add_subdirectory(libblifparse) add_subdirectory(libtatum) -#VPR_USE_EZGL is initialized in the root CMakeLists. +#VPR_USE_EZGL is initialized in the root CMakeLists. #compile libezgl only if the user asks for or has its dependencies installed. if(VPR_USE_EZGL STREQUAL "on") add_subdirectory(libezgl) diff --git a/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp b/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp index f897851f52f..ab46e91ab8e 100644 --- a/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp +++ b/libs/EXTERNAL/libtatum/libtatum/tatum/TimingGraph.cpp @@ -731,8 +731,9 @@ bool TimingGraph::validate_structure() const { } else if (src_type == NodeType::CPIN) { if( sink_type != NodeType::SOURCE - && sink_type != NodeType::SINK) { - throw tatum::Error("CPIN nodes should only drive SOURCE or SINK nodes", src_node, out_edge); + && sink_type != NodeType::SINK + && sink_type != NodeType::OPIN) { + throw tatum::Error("CPIN nodes should only drive SOURCE, OPIN or SINK nodes", src_node, out_edge); } if(sink_type == NodeType::SOURCE && out_edge_type != EdgeType::PRIMITIVE_CLOCK_LAUNCH) { diff --git a/libs/libvtrcapnproto/CMakeLists.txt b/libs/libvtrcapnproto/CMakeLists.txt index 33ce15ef397..ccf3b6bd80b 100644 --- a/libs/libvtrcapnproto/CMakeLists.txt +++ b/libs/libvtrcapnproto/CMakeLists.txt @@ -19,7 +19,6 @@ endif() # Each schema used should appear here. capnp_generate_cpp(CAPNP_SRCS CAPNP_HDRS place_delay_model.capnp - connection_map.capnp matrix.capnp ) diff --git a/libs/libvtrcapnproto/connection_map.capnp b/libs/libvtrcapnproto/connection_map.capnp deleted file mode 100644 index 30b9864153b..00000000000 --- a/libs/libvtrcapnproto/connection_map.capnp +++ /dev/null @@ -1,25 +0,0 @@ -@0x876ec83c2fea5a18; - -using Matrix = import "matrix.capnp"; - -struct VprCostEntry { - delay @0 :Float32; - congestion @1 :Float32; - fill @2 :Bool; -} - -struct VprVector2D { - x @0 :Int64; - y @1 :Int64; -} - -struct VprFloatEntry { - value @0 :Float32; -} - -struct VprCostMap { - costMap @0 :Matrix.Matrix((Matrix.Matrix(VprCostEntry))); - offset @1 :Matrix.Matrix(VprVector2D); - segmentMap @2 :List(Int64); - penalty @3 :Matrix.Matrix(VprFloatEntry); -} diff --git a/libs/libvtrutil/src/vtr_geometry.h b/libs/libvtrutil/src/vtr_geometry.h index 0545581b3dd..65c53ecea65 100644 --- a/libs/libvtrutil/src/vtr_geometry.h +++ b/libs/libvtrutil/src/vtr_geometry.h @@ -1,12 +1,10 @@ #ifndef VTR_GEOMETRY_H #define VTR_GEOMETRY_H #include "vtr_range.h" -#include "vtr_assert.h" #include #include #include -#include namespace vtr { @@ -77,16 +75,9 @@ class Point { template class Rect { public: //Constructors - Rect(); Rect(T left_val, T bottom_val, T right_val, T top_val); Rect(Point bottom_left_val, Point top_right_val); - - //Constructs a rectangle that only contains the given point - // Rect(p1).contains(p2) => p1 == p2 - //It is only enabled for integral types, because making this work for floating point types would be difficult and brittle. - //The following line only enables the constructor if std::is_integral::value == true - template::value>::type...> - Rect(Point point); + Rect(); public: //Accessors //Co-ordinates @@ -110,11 +101,6 @@ class Rect { //Returns true if the point is coincident with the rectangle (including the top-right edges) bool coincident(Point point) const; - //Returns true if no points are contained in the rectangle - // rect.empty() => not exists p. rect.contains(p) - // This also implies either the width or height is 0. - bool empty() const; - friend bool operator== <>(const Rect& lhs, const Rect& rhs); friend bool operator!= <>(const Rect& lhs, const Rect& rhs); @@ -125,27 +111,11 @@ class Rect { void set_xmax(T xmax_val); void set_ymax(T ymax_val); - //Equivalent to `*this = bounding_box(*this, other)` - Rect& expand_bounding_box(const Rect& other); - private: Point bottom_left_; Point top_right_; }; -//Return the smallest rectangle containing both given rectangles -//Note that this isn't a union and the resulting rectangle may include points not in either given rectangle -template -Rect bounding_box(const Rect& lhs, const Rect& rhs); - -//Sample on a uniformly spaced grid within a rectangle -// sample(vtr::Rect(l, h), 0, 0, M) == l -// sample(vtr::Rect(l, h), M, M, M) == h -//To avoid the edges, use `sample(r, x+1, y+1, N+1) for x, y, in 0..N-1 -//Only defined for integral types -template::value>::type...> -Point sample(const vtr::Rect& r, T x, T y, T d); - //A 2D line template class Line { diff --git a/libs/libvtrutil/src/vtr_geometry.tpp b/libs/libvtrutil/src/vtr_geometry.tpp index 5fd065b3107..a1a852850c1 100644 --- a/libs/libvtrutil/src/vtr_geometry.tpp +++ b/libs/libvtrutil/src/vtr_geometry.tpp @@ -61,12 +61,6 @@ void Point::swap() { /* * Rect */ -template -Rect::Rect() - : Rect(Point(0, 0), Point(0, 0)) { - //pass -} - template Rect::Rect(T left_val, T bottom_val, T right_val, T top_val) : Rect(Point(left_val, bottom_val), Point(right_val, top_val)) { @@ -80,16 +74,6 @@ Rect::Rect(Point bottom_left_val, Point top_right_val) //pass } -//Only defined for integral types -template -template::value>::type...> -Rect::Rect(Point point) - : bottom_left_(point) - , top_right_(point.x() + 1, - point.y() + 1) { - //pass -} - template T Rect::xmin() const { return bottom_left_.x(); @@ -151,11 +135,6 @@ bool Rect::coincident(Point point) const { && point.y() >= ymin() && point.y() <= ymax(); } -template -bool Rect::empty() const { - return xmax() <= xmin() || ymax() <= ymin(); -} - template bool operator==(const Rect& lhs, const Rect& rhs) { return lhs.bottom_left() == rhs.bottom_left() @@ -167,22 +146,6 @@ bool operator!=(const Rect& lhs, const Rect& rhs) { return !(lhs == rhs); } -template -Rect bounding_box(const Rect& lhs, const Rect& rhs) { - return Rect(std::min(lhs.xmin(), rhs.xmin()), - std::min(lhs.ymin(), rhs.ymin()), - std::max(lhs.xmax(), rhs.xmax()), - std::max(lhs.ymax(), rhs.ymax())); -} - -//Only defined for integral types -template::value>::type...> -Point sample(const vtr::Rect& r, T x, T y, T d) { - VTR_ASSERT(d > 0); - return Point((r.xmin() * (d - x) + r.xmax() * x + d / 2) / d, - (r.ymin() * (d - y) + r.ymax() * y + d / 2) / d); -} - template void Rect::set_xmin(T xmin_val) { bottom_left_.set_x(xmin_val); @@ -203,12 +166,6 @@ void Rect::set_ymax(T ymax_val) { top_right_.set_y(ymax_val); } -template -Rect& Rect::expand_bounding_box(const Rect& other) { - *this = bounding_box(*this, other); - return *this; -} - /* * Line */ diff --git a/libs/libvtrutil/test/test_geometry.cpp b/libs/libvtrutil/test/test_geometry.cpp index 8d3d91f4444..60010d503c6 100644 --- a/libs/libvtrutil/test/test_geometry.cpp +++ b/libs/libvtrutil/test/test_geometry.cpp @@ -20,146 +20,108 @@ TEST_CASE("Point", "[vtr_geometry/Point]") { } TEST_CASE("Rect", "[vtr_geometry/Rect]") { - // int tests - { - vtr::Point pi_1(5, 3); - vtr::Point pi_2(10, 11); - vtr::Point pi_3(7, 9); - - vtr::Rect r1(pi_1.x(), pi_1.y(), pi_2.x(), pi_2.y()); - vtr::Rect r2(pi_1, pi_2); - vtr::Rect r3(pi_1, pi_3); - vtr::Rect r4(pi_3, pi_2); - - SECTION("equality") { - REQUIRE(r1 == r2); - } + vtr::Point pi_1(5, 3); + vtr::Point pi_2(10, 11); - SECTION("location") { - REQUIRE(r1.xmin() == pi_1.x()); - REQUIRE(r1.xmax() == pi_2.x()); - REQUIRE(r1.ymin() == pi_1.y()); - REQUIRE(r1.ymax() == pi_2.y()); - } + vtr::Rect r1(pi_1.x(), pi_1.y(), pi_2.x(), pi_2.y()); + vtr::Rect r2(pi_1, pi_2); - SECTION("point_accessors") { - REQUIRE(r1.bottom_left() == pi_1); - REQUIRE(r1.top_right() == pi_2); - REQUIRE(r2.bottom_left() == pi_1); - REQUIRE(r2.top_right() == pi_2); - } - - SECTION("dimensions") { - REQUIRE(r1.width() == 5); - REQUIRE(r1.height() == 8); - REQUIRE(r2.width() == 5); - REQUIRE(r2.height() == 8); - } - - SECTION("contains_int") { - REQUIRE(r2.contains(pi_1)); - REQUIRE(r2.contains({6, 4})); - REQUIRE_FALSE(r2.contains({100, 4})); - REQUIRE_FALSE(r2.contains(pi_2)); - REQUIRE(vtr::Rect(pi_1).contains(pi_1)); - } - - SECTION("strictly_contains_int") { - REQUIRE_FALSE(r2.strictly_contains(pi_1)); - REQUIRE(r2.strictly_contains({6, 4})); - REQUIRE_FALSE(r2.strictly_contains({100, 4})); - REQUIRE_FALSE(r2.strictly_contains(pi_2)); - } + SECTION("equality") { + REQUIRE(r1 == r2); + } - SECTION("coincident_int") { - REQUIRE(r2.coincident(pi_1)); - REQUIRE(r2.coincident({6, 4})); - REQUIRE_FALSE(r2.coincident({100, 4})); - REQUIRE(r2.coincident(pi_2)); - } + SECTION("location") { + REQUIRE(r1.xmin() == pi_1.x()); + REQUIRE(r1.xmax() == pi_2.x()); + REQUIRE(r1.ymin() == pi_1.y()); + REQUIRE(r1.ymax() == pi_2.y()); + } - SECTION("bounds_int") { - REQUIRE(r1 == bounding_box(r3, r4)); - } + SECTION("point_accessors") { + REQUIRE(r1.bottom_left() == pi_1); + REQUIRE(r1.top_right() == pi_2); + REQUIRE(r2.bottom_left() == pi_1); + REQUIRE(r2.top_right() == pi_2); + } - SECTION("empty_int") { - REQUIRE(vtr::Rect().empty()); - } + SECTION("dimensions") { + REQUIRE(r1.width() == 5); + REQUIRE(r1.height() == 8); + REQUIRE(r2.width() == 5); + REQUIRE(r2.height() == 8); + } - SECTION("sample_int") { - auto r = vtr::Rect(pi_1, pi_2); - REQUIRE(sample(r, 0, 0, 17) == pi_1); - REQUIRE(sample(r, 17, 17, 17) == pi_2); - auto inside = sample(r, 3, 11, 17); - REQUIRE(r.contains(inside)); - } + SECTION("contains_int") { + REQUIRE(r2.contains(pi_1)); + REQUIRE(r2.contains({6, 4})); + REQUIRE_FALSE(r2.contains({100, 4})); + REQUIRE_FALSE(r2.contains(pi_2)); } - // float tests - { - vtr::Point pf_1(5.3, 3.9); - vtr::Point pf_2(10.5, 11.1); - vtr::Point pf_3(7.2, 9.4); + SECTION("strictly_contains_int") { + REQUIRE_FALSE(r2.strictly_contains(pi_1)); + REQUIRE(r2.strictly_contains({6, 4})); + REQUIRE_FALSE(r2.strictly_contains({100, 4})); + REQUIRE_FALSE(r2.strictly_contains(pi_2)); + } - vtr::Rect r3(pf_1.x(), pf_1.y(), pf_2.x(), pf_2.y()); - vtr::Rect r4(pf_1, pf_2); - vtr::Rect r5(pf_1, pf_3); - vtr::Rect r6(pf_3, pf_2); - // vtr::Rect r7(pf_1); // <-- will fail to compile + SECTION("coincident_int") { + REQUIRE(r2.coincident(pi_1)); + REQUIRE(r2.coincident({6, 4})); + REQUIRE_FALSE(r2.coincident({100, 4})); + REQUIRE(r2.coincident(pi_2)); + } - SECTION("equality_float") { - REQUIRE(r3 == r4); - } + vtr::Point pf_1(5.3, 3.9); + vtr::Point pf_2(10.5, 11.1); - SECTION("location_float") { - REQUIRE(r3.xmin() == pf_1.x()); - REQUIRE(r3.xmax() == pf_2.x()); - REQUIRE(r3.ymin() == pf_1.y()); - REQUIRE(r3.ymax() == pf_2.y()); - } + vtr::Rect r3(pf_1.x(), pf_1.y(), pf_2.x(), pf_2.y()); + vtr::Rect r4(pf_1, pf_2); - SECTION("point_accessors_float") { - REQUIRE(r3.bottom_left() == pf_1); - REQUIRE(r3.top_right() == pf_2); - REQUIRE(r4.bottom_left() == pf_1); - REQUIRE(r4.top_right() == pf_2); - } + SECTION("equality_float") { + REQUIRE(r3 == r4); + } - SECTION("dimensions") { - REQUIRE(r3.width() == Approx(5.2)); - REQUIRE(r3.height() == Approx(7.2)); - REQUIRE(r4.width() == Approx(5.2)); - REQUIRE(r4.height() == Approx(7.2)); - } + SECTION("location_float") { + REQUIRE(r3.xmin() == pf_1.x()); + REQUIRE(r3.xmax() == pf_2.x()); + REQUIRE(r3.ymin() == pf_1.y()); + REQUIRE(r3.ymax() == pf_2.y()); + } - SECTION("contains_float") { - REQUIRE(r4.contains(pf_1)); - REQUIRE(r4.contains({6, 4})); - REQUIRE_FALSE(r4.contains({100, 4})); - REQUIRE_FALSE(r4.contains(pf_2)); - } + SECTION("point_accessors_float") { + REQUIRE(r3.bottom_left() == pf_1); + REQUIRE(r3.top_right() == pf_2); + REQUIRE(r4.bottom_left() == pf_1); + REQUIRE(r4.top_right() == pf_2); + } - SECTION("strictly_contains_float") { - REQUIRE_FALSE(r4.strictly_contains(pf_1)); - REQUIRE(r4.strictly_contains({6, 4})); - REQUIRE_FALSE(r4.strictly_contains({100, 4})); - REQUIRE_FALSE(r4.strictly_contains(pf_2)); - } + SECTION("dimensions") { + REQUIRE(r3.width() == Approx(5.2)); + REQUIRE(r3.height() == Approx(7.2)); + REQUIRE(r4.width() == Approx(5.2)); + REQUIRE(r4.height() == Approx(7.2)); + } - SECTION("coincident_float") { - REQUIRE(r4.coincident(pf_1)); - REQUIRE(r4.coincident({6, 4})); - REQUIRE_FALSE(r4.coincident({100, 4})); - REQUIRE(r4.coincident(pf_2)); - } + SECTION("contains_float") { + REQUIRE(r4.contains(pf_1)); + REQUIRE(r4.contains({6, 4})); + REQUIRE_FALSE(r4.contains({100, 4})); + REQUIRE_FALSE(r4.contains(pf_2)); + } - SECTION("bounds_float") { - REQUIRE(r3 == bounding_box(r5, r6)); - } + SECTION("strictly_contains_float") { + REQUIRE_FALSE(r4.strictly_contains(pf_1)); + REQUIRE(r4.strictly_contains({6, 4})); + REQUIRE_FALSE(r4.strictly_contains({100, 4})); + REQUIRE_FALSE(r4.strictly_contains(pf_2)); + } - SECTION("empty_float") { - REQUIRE(vtr::Rect().empty()); - } + SECTION("coincident_float") { + REQUIRE(r4.coincident(pf_1)); + REQUIRE(r4.coincident({6, 4})); + REQUIRE_FALSE(r4.coincident({100, 4})); + REQUIRE(r4.coincident(pf_2)); } } diff --git a/utils/fasm/src/main.cpp b/utils/fasm/src/main.cpp index 58cc2227cc5..dae4edf9994 100644 --- a/utils/fasm/src/main.cpp +++ b/utils/fasm/src/main.cpp @@ -72,7 +72,6 @@ int main(int argc, const char **argv) { vpr_setup.PackerOpts.doPacking = STAGE_LOAD; vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD; vpr_setup.RouterOpts.doRouting = STAGE_LOAD; - vpr_setup.RouterOpts.read_edge_metadata = true; vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP; bool flow_succeeded = false; diff --git a/utils/fasm/test/test_fasm.cpp b/utils/fasm/test/test_fasm.cpp index 706f1eb0e04..543d3a92636 100644 --- a/utils/fasm/test/test_fasm.cpp +++ b/utils/fasm/test/test_fasm.cpp @@ -182,7 +182,6 @@ TEST_CASE("fasm_integration_test", "[fasm]") { }; vpr_init(sizeof(argv)/sizeof(argv[0]), argv, &options, &vpr_setup, &arch); - vpr_setup.RouterOpts.read_edge_metadata = true; bool flow_succeeded = vpr_flow(vpr_setup, arch); REQUIRE(flow_succeeded == true); @@ -220,7 +219,6 @@ TEST_CASE("fasm_integration_test", "[fasm]") { vpr_setup.PackerOpts.doPacking = STAGE_LOAD; vpr_setup.PlacerOpts.doPlacement = STAGE_LOAD; vpr_setup.RouterOpts.doRouting = STAGE_LOAD; - vpr_setup.RouterOpts.read_edge_metadata = true; vpr_setup.AnalysisOpts.doAnalysis = STAGE_SKIP; bool flow_succeeded = vpr_flow(vpr_setup, arch); diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index e972e7131e1..ee1c467d17c 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -83,7 +83,7 @@ static void do_one_route(int source_node, int sink_node, bounding_box.ymax = device_ctx.grid.height() + 1; t_conn_cost_params cost_params; - cost_params.criticality = router_opts.max_criticality; + cost_params.criticality = 1.; cost_params.astar_fac = router_opts.astar_fac; cost_params.bend_cost = router_opts.bend_cost; diff --git a/vpr/src/base/SetupGrid.cpp b/vpr/src/base/SetupGrid.cpp index 982f313cafc..e306dda21a5 100644 --- a/vpr/src/base/SetupGrid.cpp +++ b/vpr/src/base/SetupGrid.cpp @@ -25,9 +25,9 @@ #include "expr_eval.h" static DeviceGrid auto_size_device_grid(const std::vector& grid_layouts, const std::map& minimum_instance_counts, float maximum_device_utilization); -static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); +static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts); static bool grid_satisfies_instance_counts(const DeviceGrid& grid, std::map instance_counts, float maximum_utilization); -static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, std::vector limiting_resources = std::vector()); +static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t width, size_t height, bool warn_out_of_range = true, std::vector limiting_resources = std::vector()); static void CheckGrid(const DeviceGrid& grid); @@ -152,7 +152,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo //specifications size_t width = 3; size_t height = 3; - std::vector limiting_resources; + std::vector limiting_resources; do { //Scale opposite dimension to match aspect ratio height = vtr::nint(width / grid_def.aspect_ratio); @@ -203,7 +203,7 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo }; std::stable_sort(grid_layouts_view.begin(), grid_layouts_view.end(), area_cmp); - std::vector limiting_resources; + std::vector limiting_resources; //Try all the fixed devices in order from smallest to largest for (const auto* grid_def : grid_layouts_view) { @@ -220,37 +220,58 @@ static DeviceGrid auto_size_device_grid(const std::vector& grid_layo return grid; //Unreachable } -static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts) { +static std::vector grid_overused_resources(const DeviceGrid& grid, std::map instance_counts) { + //Estimates what logical block types will be unimplementable due to resource limits in the available grid + // + //Performs a fast counting based estimate, allocating the least flexible block types (those with the fewest + //equivalent tiles) first. auto& device_ctx = g_vpr_ctx.device(); - std::vector overused_resources; + std::vector overused_resources; std::unordered_map min_count_map; // Initialize min_count_map - for (const auto& physical_tile : device_ctx.physical_tile_types) { - min_count_map.insert(std::make_pair(&physical_tile, size_t(0))); + for (const auto& tile_type : device_ctx.physical_tile_types) { + min_count_map.insert(std::make_pair(&tile_type, size_t(0))); } - //Are the resources satisified? - for (auto kv : instance_counts) { - t_physical_tile_type_ptr type = nullptr; + //Initialize available tile counts + std::unordered_map avail_tiles; + for (auto& tile_type : device_ctx.physical_tile_types) { + avail_tiles[&tile_type] = grid.num_instances(&tile_type); + } - size_t inst_cnt = 0; - for (auto& physical_tile : kv.first->equivalent_tiles) { - size_t tmp_inst_cnt = grid.num_instances(physical_tile); + //Sort so we allocate logical blocks with the fewest equivalent sites first (least flexible) + std::vector logical_block_types; + for (auto& block_type : device_ctx.logical_block_types) { + logical_block_types.push_back(&block_type); + } - if (inst_cnt <= tmp_inst_cnt) { - type = physical_tile; - inst_cnt = tmp_inst_cnt; - } - } + auto by_ascending_equiv_tiles = [](t_logical_block_type_ptr lhs, t_logical_block_type_ptr rhs) { + return lhs->equivalent_tiles.size() < rhs->equivalent_tiles.size(); + }; + std::stable_sort(logical_block_types.begin(), logical_block_types.end(), by_ascending_equiv_tiles); + + //Allocate logical blocks to available tiles + for (auto block_type : logical_block_types) { + if (instance_counts.count(block_type)) { + int required_blocks = instance_counts[block_type]; + + for (auto tile_type : block_type->equivalent_tiles) { + if (avail_tiles[tile_type] >= required_blocks) { + avail_tiles[tile_type] -= required_blocks; + required_blocks = 0; + } else { + required_blocks -= avail_tiles[tile_type]; + avail_tiles[tile_type] = 0; + } - VTR_ASSERT(type); - size_t min_count = min_count_map.at(type) + kv.second; - min_count_map.at(type) = min_count; + if (required_blocks == 0) break; + } - if (inst_cnt < min_count) { - overused_resources.push_back(type); + if (required_blocks > 0) { + overused_resources.push_back(block_type); + } } } @@ -276,7 +297,7 @@ static bool grid_satisfies_instance_counts(const DeviceGrid& grid, std::map limiting_resources) { +static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_width, size_t grid_height, bool warn_out_of_range, const std::vector limiting_resources) { if (grid_def.grid_type == GridDefType::FIXED) { if (grid_def.width != int(grid_width) || grid_def.height != int(grid_height)) { VPR_FATAL_ERROR(VPR_ERROR_OTHER, diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp index 0ffa8c306f7..4fd21004eb5 100644 --- a/vpr/src/base/SetupVPR.cpp +++ b/vpr/src/base/SetupVPR.cpp @@ -160,7 +160,6 @@ void SetupVPR(const t_options* Options, } Segments = Arch->Segments; - device_ctx.segment_inf = Arch->Segments; SetupSwitches(*Arch, RoutingArch, Arch->Switches, Arch->num_switches); SetupRoutingArch(*Arch, RoutingArch); @@ -323,7 +322,6 @@ static void SetupRoutingArch(const t_arch& Arch, } static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) { - RouterOpts->do_check_rr_graph = !Options.disable_check_rr_graph; RouterOpts->astar_fac = Options.astar_fac; RouterOpts->bb_factor = Options.bb_factor; RouterOpts->criticality_exp = Options.criticality_exp; @@ -373,11 +371,11 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts) RouterOpts->max_convergence_count = Options.router_max_convergence_count; RouterOpts->reconvergence_cpd_threshold = Options.router_reconvergence_cpd_threshold; RouterOpts->first_iteration_timing_report_file = Options.router_first_iteration_timing_report_file; + RouterOpts->strict_checks = Options.strict_checks; RouterOpts->write_router_lookahead = Options.write_router_lookahead; RouterOpts->read_router_lookahead = Options.read_router_lookahead; - RouterOpts->disable_check_route = Options.disable_check_route; } static void SetupAnnealSched(const t_options& Options, diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index ac2f324eb92..05501cc9c71 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -202,9 +202,6 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) { case DELAY_NORMALIZED_LENGTH: VTR_LOG("DELAY_NORMALIZED_LENGTH\n"); break; - case DELAY_NORMALIZED_LENGTH_BOUNDED: - VTR_LOG("DELAY_NORMALIZED_LENGTH_BOUNDED\n"); - break; case DELAY_NORMALIZED_FREQUENCY: VTR_LOG("DELAY_NORMALIZED_FREQUENCY\n"); break; diff --git a/vpr/src/base/atom_netlist_utils.cpp b/vpr/src/base/atom_netlist_utils.cpp index ba8e6eea93e..ea32a2d071b 100644 --- a/vpr/src/base/atom_netlist_utils.cpp +++ b/vpr/src/base/atom_netlist_utils.cpp @@ -29,7 +29,9 @@ int infer_and_mark_block_sequential_outputs_constant(AtomNetlist& netlist, AtomB //Returns the set of input ports which are combinationally connected to output_port std::vector find_combinationally_connected_input_ports(const AtomNetlist& netlist, AtomPortId output_port); -std::vector identify_buffer_luts(const AtomNetlist& netlist); +//Returns the set of clock ports which are combinationally connected to output_port +std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port); + bool is_buffer_lut(const AtomNetlist& netlist, const AtomBlockId blk); bool is_removable_block(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); bool is_removable_input(const AtomNetlist& netlist, const AtomBlockId blk, std::string* reason = nullptr); @@ -660,6 +662,28 @@ std::vector find_combinationally_connected_input_ports(const AtomNet return upstream_ports; } +std::vector find_combinationally_connected_clock_ports(const AtomNetlist& netlist, AtomPortId output_port) { + std::vector upstream_ports; + + VTR_ASSERT(netlist.port_type(output_port) == PortType::OUTPUT); + + std::string out_port_name = netlist.port_name(output_port); + + AtomBlockId blk = netlist.port_block(output_port); + + //Look through each block input port to find those which are combinationally connected to the output port + for (AtomPortId clock_port : netlist.block_clock_ports(blk)) { + const t_model_ports* clock_model_port = netlist.port_model(clock_port); + for (const std::string& sink_port_name : clock_model_port->combinational_sink_ports) { + if (sink_port_name == out_port_name) { + upstream_ports.push_back(clock_port); + } + } + } + + return upstream_ports; +} + void absorb_buffer_luts(AtomNetlist& netlist, int verbosity) { //First we look through the netlist to find LUTs with identity logic functions //we then remove those luts, replacing the net's they drove with the inputs to the @@ -839,26 +863,16 @@ bool remove_buffer_lut(AtomNetlist& netlist, AtomBlockId blk, int verbosity) { }); std::string new_net_name; - if (!driver_is_pi && !po_in_input_sinks && !po_in_output_sinks) { - //No PIs or POs, we can choose arbitarily in this case - new_net_name = netlist.net_name(output_net); - } else if ((driver_is_pi || po_in_input_sinks) && !po_in_output_sinks) { + if ((driver_is_pi || po_in_input_sinks) && !po_in_output_sinks) { //Must use the input name to perserve primary-input or primary-output name new_net_name = netlist.net_name(input_net); - - } else if ((!driver_is_pi && !po_in_input_sinks) && po_in_output_sinks) { + } else if (!(driver_is_pi || po_in_input_sinks) && po_in_output_sinks) { //Must use the output name to perserve primary-output name new_net_name = netlist.net_name(output_net); - } else { - VTR_ASSERT((driver_is_pi || po_in_input_sinks) && po_in_output_sinks); - //This is a buffered connection from a primary input to primary output, or to - //more than one primary output. - //TODO: consider implications of removing these... - - //Do not remove such buffers - return false; + //Arbitrarily merge the net names + new_net_name = netlist.net_name(input_net) + "__" + netlist.net_name(output_net); } size_t initial_input_net_pins = netlist.net_pins(input_net).size(); @@ -1365,7 +1379,7 @@ std::set find_netlist_physical_clock_nets(const AtomNetlist& netlist) return clock_nets; } -//Finds all logical clock drivers in the netlist +//Finds all logical clock drivers in the netlist (by back-tracing through logic) std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlist) { auto clock_nets = find_netlist_physical_clock_nets(netlist); @@ -1374,28 +1388,62 @@ std::set find_netlist_logical_clock_drivers(const AtomNetlist& netlis //However, some of them may be the same logical clock (e.g. if there are //buffers between them). Here we trace-back through any clock buffers //to find the true source + size_t assumed_buffer_count = 0; std::set prev_clock_nets; while (prev_clock_nets != clock_nets) { //Still tracing back prev_clock_nets = clock_nets; clock_nets.clear(); for (auto clk_net : prev_clock_nets) { - auto driver_block = netlist.net_driver_block(clk_net); + AtomPinId driver_pin = netlist.net_driver(clk_net); + AtomPortId driver_port = netlist.pin_port(driver_pin); + AtomBlockId driver_blk = netlist.port_block(driver_port); - if (is_buffer(netlist, driver_block)) { - //Driver is a buffer lut, use it's input net - auto input_pins = netlist.block_input_pins(driver_block); - VTR_ASSERT(input_pins.size() == 1); - auto input_pin = *input_pins.begin(); + std::vector upstream_ports; - auto input_net = netlist.pin_net(input_pin); - clock_nets.insert(input_net); + if (netlist.block_model(driver_blk)->name == std::string(".names")) { + //For .names we allow tracing back through data connections + //which allows us to traceback through white-box .names buffers + upstream_ports = find_combinationally_connected_input_ports(netlist, driver_port); } else { + //For black boxes, we only trace back through inputs marked as clocks + upstream_ports = find_combinationally_connected_clock_ports(netlist, driver_port); + } + + if (upstream_ports.empty()) { + //This net is a root net of a clock, keep it clock_nets.insert(clk_net); + } else { + //Trace the clock back through any combinational logic + // + // We are assuming that the combinational connections are independent and non-inverting. + // If this is not the case, it is up to the end-user to specify the clocks explicitly + // at the intermediate pins in the netlist. + for (AtomPortId upstream_port : upstream_ports) { + for (AtomPinId upstream_pin : netlist.port_pins(upstream_port)) { + AtomNetId upstream_net = netlist.pin_net(upstream_pin); + + VTR_ASSERT(upstream_net); + + VTR_LOG_WARN("Assuming clocks may propagate through %s (%s) from pin %s to %s (assuming a non-inverting buffer).\n", + netlist.block_name(driver_blk).c_str(), netlist.block_model(driver_blk)->name, + netlist.pin_name(upstream_pin).c_str(), netlist.pin_name(driver_pin).c_str()); + + clock_nets.insert(upstream_net); + ++assumed_buffer_count; + } + } } } } + if (assumed_buffer_count > 0) { + VTR_LOG_WARN( + "Assumed %zu netlist logic connections may be clock buffers. " + "To override this behaviour explicitly create clocks at the appropriate netlist pins.\n", + assumed_buffer_count); + } + //Extract the net drivers std::set clock_drivers; for (auto net : clock_nets) { diff --git a/vpr/src/base/device_grid.cpp b/vpr/src/base/device_grid.cpp index 3be488d26dd..e4e05a7241c 100644 --- a/vpr/src/base/device_grid.cpp +++ b/vpr/src/base/device_grid.cpp @@ -7,7 +7,7 @@ DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid) count_instances(); } -DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res) +DeviceGrid::DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res) : DeviceGrid(grid_name, grid) { limiting_resources_ = limiting_res; } diff --git a/vpr/src/base/device_grid.h b/vpr/src/base/device_grid.h index 6f0584c94db..44bdc8b6659 100644 --- a/vpr/src/base/device_grid.h +++ b/vpr/src/base/device_grid.h @@ -8,7 +8,7 @@ class DeviceGrid { public: DeviceGrid() = default; DeviceGrid(std::string grid_name, vtr::Matrix grid); - DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res); + DeviceGrid(std::string grid_name, vtr::Matrix grid, std::vector limiting_res); const std::string& name() const { return name_; } @@ -25,7 +25,7 @@ class DeviceGrid { //Returns the block types which limits the device size (may be empty if //resource limits were not considered when selecting the device). - std::vector limiting_resources() const { return limiting_resources_; } + std::vector limiting_resources() const { return limiting_resources_; } private: void count_instances(); @@ -39,7 +39,7 @@ class DeviceGrid { std::map instance_counts_; - std::vector limiting_resources_; + std::vector limiting_resources_; }; #endif diff --git a/vpr/src/base/echo_files.cpp b/vpr/src/base/echo_files.cpp index cd4e2566f9b..6f8de45933b 100644 --- a/vpr/src/base/echo_files.cpp +++ b/vpr/src/base/echo_files.cpp @@ -114,8 +114,6 @@ void alloc_and_load_echo_file_info() { setEchoFileName(E_ECHO_CHAN_DETAILS, "chan_details.txt"); setEchoFileName(E_ECHO_SBLOCK_PATTERN, "sblock_pattern.txt"); setEchoFileName(E_ECHO_ENDPOINT_TIMING, "endpoint_timing.echo.json"); - - setEchoFileName(E_ECHO_LOOKAHEAD_MAP, "lookahead_map.echo"); } void free_echo_file_info() { diff --git a/vpr/src/base/echo_files.h b/vpr/src/base/echo_files.h index d273c575d50..70df3a3d962 100644 --- a/vpr/src/base/echo_files.h +++ b/vpr/src/base/echo_files.h @@ -46,7 +46,6 @@ enum e_echo_files { E_ECHO_CHAN_DETAILS, E_ECHO_SBLOCK_PATTERN, E_ECHO_ENDPOINT_TIMING, - E_ECHO_LOOKAHEAD_MAP, //Timing Graphs E_ECHO_PRE_PACKING_TIMING_GRAPH, diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index abd197f320d..0f47ebebb37 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -357,9 +357,7 @@ int binary_search_place_and_route(const t_placer_opts& placer_opts_ref, router_opts.trim_obs_channels, router_opts.clock_modeling, arch->Directs, arch->num_directs, - &warnings, - router_opts.read_edge_metadata, - router_opts.do_check_rr_graph); + &warnings); init_draw_coords(final); restore_routing(best_routing, route_ctx.clb_opins_used_locally, saved_clb_opins_used_locally); diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp index 123c4d854be..5f654445efd 100644 --- a/vpr/src/base/read_options.cpp +++ b/vpr/src/base/read_options.cpp @@ -245,8 +245,6 @@ struct ParseBaseCost { conv_value.set_value(DEMAND_ONLY_NORMALIZED_LENGTH); else if (str == "demand_only") conv_value.set_value(DEMAND_ONLY); - else if (str == "delay_normalized_length_bounded") - conv_value.set_value(DELAY_NORMALIZED_LENGTH_BOUNDED); else { std::stringstream msg; msg << "Invalid conversion from '" << str << "' to e_router_algorithm (expected one of: " << argparse::join(default_choices(), ", ") << ")"; @@ -267,8 +265,6 @@ struct ParseBaseCost { conv_value.set_value("delay_normalized_length_frequency"); else if (val == DEMAND_ONLY_NORMALIZED_LENGTH) conv_value.set_value("demand_only_normalized_length"); - else if (val == DELAY_NORMALIZED_LENGTH_BOUNDED) - conv_value.set_value("delay_normalized_length_bounded"); else { VTR_ASSERT(val == DEMAND_ONLY); conv_value.set_value("demand_only"); @@ -277,7 +273,7 @@ struct ParseBaseCost { } std::vector default_choices() { - return {"demand_only", "demand_only_normalized_length", "delay_normalized", "delay_normalized_length", "delay_normalized_length_bounded", "delay_normalized_frequency", "delay_normalized_length_frequency"}; + return {"demand_only", "demand_only_normalized_length", "delay_normalized", "delay_normalized_length", "delay_normalized_frequency", "delay_normalized_length_frequency"}; } }; @@ -656,8 +652,6 @@ struct ParseRouterLookahead { conv_value.set_value(e_router_lookahead::CLASSIC); else if (str == "map") conv_value.set_value(e_router_lookahead::MAP); - else if (str == "connection_box_map") - conv_value.set_value(e_router_lookahead::CONNECTION_BOX_MAP); else { std::stringstream msg; msg << "Invalid conversion from '" @@ -671,22 +665,17 @@ struct ParseRouterLookahead { ConvertedValue to_str(e_router_lookahead val) { ConvertedValue conv_value; - if (val == e_router_lookahead::CLASSIC) { + if (val == e_router_lookahead::CLASSIC) conv_value.set_value("classic"); - } else if (val == e_router_lookahead::MAP) { + else { + VTR_ASSERT(val == e_router_lookahead::MAP); conv_value.set_value("map"); - } else if (val == e_router_lookahead::CONNECTION_BOX_MAP) { - conv_value.set_value("connection_box_map"); - } else { - std::stringstream msg; - msg << "Unrecognized e_router_lookahead"; - conv_value.set_error(msg.str()); } return conv_value; } std::vector default_choices() { - return {"classic", "map", "connection_box_map"}; + return {"classic", "map"}; } }; @@ -1462,13 +1451,9 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg " to magnitude of typical routing resource delay\n" " * delay_normalized_length: like delay_normalized but\n" " scaled by routing resource length\n" - " * delay_normalized_length_bounded: like delay_normalized but\n" - " scaled by routing resource length. Scaling is normalized\n" - " between 1 to 4, with min lengths getting scaled at 1,\n" - " and max lengths getting scaled at 4.\n" - " * delay_normalized_frequency: like delay_normalized\n" + " * delay_normalized_freqeuncy: like delay_normalized\n" " but scaled inversely by segment type frequency\n" - " * delay_normalized_length_frequency: like delay_normalized\n" + " * delay_normalized_length_freqeuncy: like delay_normalized\n" " but scaled by routing resource length, and inversely\n" " by segment type frequency\n" "(Default: demand_only for breadth-first router,\n" @@ -1528,11 +1513,6 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("1.2") .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.lookahead_search_locations, "--lookahead_search_locations") - .help("DEPRECATED Semi-colon seperated x,y coordinates to use for lookahead search coordinates.") - .default_value("") - .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.max_criticality, "--max_criticality") .help( "Sets the maximum fraction of routing cost derived from delay (vs routability) for any net." @@ -1640,11 +1620,6 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("") .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.disable_check_route, "--disable_check_route") - .help("Disables check_route once routing step has finished or when routing file is loaded") - .default_value("off") - .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.router_debug_net, "--router_debug_net") .help( "Controls when router debugging is enabled.\n" @@ -1667,11 +1642,6 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg .default_value("-2") .show_in(argparse::ShowIn::HELP_ONLY); - route_timing_grp.add_argument(args.disable_check_rr_graph, "--disable_check_rr_graph") - .help("Disables checking rr graph when reading from disk.") - .default_value("off") - .show_in(argparse::ShowIn::HELP_ONLY); - auto& analysis_grp = parser.add_argument_group("analysis options"); analysis_grp.add_argument(args.full_stats, "--full_stats") diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h index 55c2695d828..97d320abbe3 100644 --- a/vpr/src/base/read_options.h +++ b/vpr/src/base/read_options.h @@ -119,7 +119,6 @@ struct t_options { argparse::ArgValue allowed_tiles_for_delay_model; /* Router Options */ - argparse::ArgValue disable_check_rr_graph; argparse::ArgValue max_router_iterations; argparse::ArgValue first_iter_pres_fac; argparse::ArgValue initial_pres_fac; @@ -134,7 +133,6 @@ struct t_options { argparse::ArgValue verify_binary_search; argparse::ArgValue RouterAlgorithm; argparse::ArgValue min_incremental_reroute_fanout; - argparse::ArgValue disable_check_route; /* Timing-driven router options only */ argparse::ArgValue astar_fac; @@ -154,7 +152,6 @@ struct t_options { argparse::ArgValue router_max_convergence_count; argparse::ArgValue router_reconvergence_cpd_threshold; argparse::ArgValue router_first_iteration_timing_report_file; - argparse::ArgValue lookahead_search_locations; /* Analysis options */ argparse::ArgValue full_stats; diff --git a/vpr/src/base/read_place.cpp b/vpr/src/base/read_place.cpp index dc83c90b48e..929192ec34c 100644 --- a/vpr/src/base/read_place.cpp +++ b/vpr/src/base/read_place.cpp @@ -146,7 +146,6 @@ void read_user_pad_loc(const char* pad_loc_file) { int xtmp, ytmp; FILE* fp; char buf[vtr::bufsize], bname[vtr::bufsize], *ptr; - std::unordered_set constrained_blocks; auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); @@ -161,14 +160,17 @@ void read_user_pad_loc(const char* pad_loc_file) { hash_table = alloc_hash_table(); for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - insert_in_hash_table(hash_table, cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id)); - place_ctx.block_locs[blk_id].loc.x = OPEN; /* Mark as not seen yet. */ + auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); + if (is_io_type(pick_best_physical_type(logical_block))) { + insert_in_hash_table(hash_table, cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id)); + place_ctx.block_locs[blk_id].loc.x = OPEN; /* Mark as not seen yet. */ + } } for (size_t i = 0; i < device_ctx.grid.width(); i++) { for (size_t j = 0; j < device_ctx.grid.height(); j++) { auto type = device_ctx.grid[i][j].type; - if (!is_empty_type(type)) { + if (is_io_type(type)) { for (int k = 0; k < type->capacity; k++) { if (place_ctx.grid_blocks[i][j].blocks[k] != INVALID_BLOCK_ID) { place_ctx.grid_blocks[i][j].blocks[k] = EMPTY_BLOCK_ID; /* Flag for err. check */ @@ -234,12 +236,12 @@ void read_user_pad_loc(const char* pad_loc_file) { int j = ytmp; if (place_ctx.block_locs[bnum].loc.x != OPEN) { - VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), + vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), "Block %s is listed twice in pad file.\n", bname); } if (i < 0 || i > int(device_ctx.grid.width() - 1) || j < 0 || j > int(device_ctx.grid.height() - 1)) { - VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, + vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0, "Block #%zu (%s) location, (%d,%d) is out of range.\n", size_t(bnum), bname, i, j); } @@ -248,33 +250,27 @@ void read_user_pad_loc(const char* pad_loc_file) { place_ctx.block_locs[bnum].loc.z = k; place_ctx.block_locs[bnum].is_fixed = true; - auto physical_tile = device_ctx.grid[i][j].type; - auto logical_block = cluster_ctx.clb_nlist.block_type(bnum); - if (!is_tile_compatible(physical_tile, logical_block)) { - VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, - "Attempt to place block %s at illegal location (%d, %d).\n", bname, i, j); + auto type = device_ctx.grid[i][j].type; + if (!is_io_type(type)) { + vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0, + "Attempt to place IO block %s at illegal location (%d, %d).\n", bname, i, j); } - if (k >= physical_tile->capacity || k < 0) { - VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), + if (k >= type->capacity || k < 0) { + vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, vtr::get_file_line_number_of_last_opened_file(), "Block %s subblock number (%d) is out of range.\n", bname, k); } place_ctx.grid_blocks[i][j].blocks[k] = bnum; place_ctx.grid_blocks[i][j].usage++; - constrained_blocks.insert(bnum); - ptr = vtr::fgets(buf, vtr::bufsize, fp); } for (auto blk_id : cluster_ctx.clb_nlist.blocks()) { - auto result = constrained_blocks.find(blk_id); - if (result == constrained_blocks.end()) { - continue; - } - - if (place_ctx.block_locs[blk_id].loc.x == OPEN) { - VPR_THROW(VPR_ERROR_PLACE_F, pad_loc_file, 0, + auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); + auto type = pick_best_physical_type(logical_block); + if (is_io_type(type) && place_ctx.block_locs[blk_id].loc.x == OPEN) { + vpr_throw(VPR_ERROR_PLACE_F, pad_loc_file, 0, "IO block %s location was not specified in the pad file.\n", cluster_ctx.clb_nlist.block_name(blk_id).c_str()); } } diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp index 1688f0ae932..f2900d0d299 100644 --- a/vpr/src/base/vpr_api.cpp +++ b/vpr/src/base/vpr_api.cpp @@ -688,9 +688,7 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch) { std::string graphics_msg; if (route_status.success()) { //Sanity check the routing - if (!router_opts.disable_check_route) { - check_route(router_opts.route_type); - } + check_route(router_opts.route_type); get_serial_num(); //Update status @@ -851,9 +849,7 @@ void vpr_create_rr_graph(t_vpr_setup& vpr_setup, const t_arch& arch, int chan_wi router_opts.trim_obs_channels, router_opts.clock_modeling, arch.Directs, arch.num_directs, - &warnings, - router_opts.read_edge_metadata, - router_opts.do_check_rr_graph); + &warnings); //Initialize drawing, now that we have an RR graph init_draw_coords(chan_width_fac); } diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 06b3731cf2b..b6a1f9859da 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -21,7 +21,6 @@ #include "router_lookahead.h" #include "place_macro.h" #include "compressed_grid.h" -#include "connection_box.h" //A Context is collection of state relating to a particular part of VPR // @@ -162,7 +161,6 @@ struct DeviceContext : public Context { t_rr_node_indices rr_node_indices; //[0..NUM_RR_TYPES-1][0..grid.width()-1][0..grid.width()-1][0..size-1] std::vector rr_switch_inf; /* autogenerated in build_rr_graph based on switch fan-in. [0..(num_rr_switches-1)] */ - std::vector segment_inf; int num_arch_switches; t_arch_switch_inf* arch_switch_inf; /* [0..(num_arch_switches-1)] */ @@ -214,8 +212,6 @@ struct DeviceContext : public Context { // Name of rrgraph file read (if any). // Used to determine when reading rrgraph if file is already loaded. std::string read_rr_graph_filename; - - ConnectionBoxes connection_boxes; }; //State relating to power analysis diff --git a/vpr/src/base/vpr_tatum_error.cpp b/vpr/src/base/vpr_tatum_error.cpp index 61504daa8a5..ea106def804 100644 --- a/vpr/src/base/vpr_tatum_error.cpp +++ b/vpr/src/base/vpr_tatum_error.cpp @@ -45,24 +45,26 @@ std::string format_tatum_error(const tatum::Error& error) { } if (error.edge) { - tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); - tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); + if (timing_ctx.graph) { + tatum::NodeId src_node = timing_ctx.graph->edge_src_node(error.edge); + tatum::NodeId sink_node = timing_ctx.graph->edge_sink_node(error.edge); - AtomPinId src_pin = atom_ctx.lookup.tnode_atom_pin(src_node); - AtomPinId sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_node); + AtomPinId src_pin = atom_ctx.lookup.tnode_atom_pin(src_node); + AtomPinId sink_pin = atom_ctx.lookup.tnode_atom_pin(sink_node); - if (src_pin && sink_pin) { - msg += "Between netlist pins "; + if (src_pin && sink_pin) { + msg += "Between netlist pins "; - msg += "'" + atom_ctx.nlist.pin_name(src_pin) + "' -> '" + atom_ctx.nlist.pin_name(sink_pin) + "'"; + msg += "'" + atom_ctx.nlist.pin_name(src_pin) + "' -> '" + atom_ctx.nlist.pin_name(sink_pin) + "'"; - AtomNetId src_net = atom_ctx.nlist.pin_net(src_pin); - AtomNetId sink_net = atom_ctx.nlist.pin_net(sink_pin); - if (src_net && src_net == sink_net) { - msg += " via net '" + atom_ctx.nlist.net_name(src_net) + "'"; - } + AtomNetId src_net = atom_ctx.nlist.pin_net(src_pin); + AtomNetId sink_net = atom_ctx.nlist.pin_net(sink_pin); + if (src_net && src_net == sink_net) { + msg += " via net '" + atom_ctx.nlist.net_name(src_net) + "'"; + } - msg += ", "; + msg += ", "; + } } msg += "Timing Graph Edge: " + std::to_string(size_t(error.edge)); diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index f5266ef97a4..e6c010f7398 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -104,10 +104,7 @@ constexpr const char* EMPTY_BLOCK_NAME = "EMPTY"; enum class e_router_lookahead { CLASSIC, //VPR's classic lookahead (assumes uniform wire types) MAP, //Lookahead considering different wire types (see Oleg Petelin's MASc Thesis) - NO_OP, //A no-operation lookahead which always returns zero - CONNECTION_BOX_MAP, - // Lookahead considering different wire types and IPIN - // connection box. + NO_OP //A no-operation lookahead which always returns zero }; enum class e_route_bb_update { @@ -879,7 +876,6 @@ enum e_base_cost_type { DELAY_NORMALIZED_LENGTH, DELAY_NORMALIZED_FREQUENCY, DELAY_NORMALIZED_LENGTH_FREQUENCY, - DELAY_NORMALIZED_LENGTH_BOUNDED, DEMAND_ONLY, DEMAND_ONLY_NORMALIZED_LENGTH }; @@ -909,8 +905,6 @@ enum class e_incr_reroute_delay_ripup { constexpr int NO_FIXED_CHANNEL_WIDTH = -1; struct t_router_opts { - bool read_edge_metadata = false; - bool do_check_rr_graph = true; float first_iter_pres_fac; float initial_pres_fac; float pres_fac_mult; @@ -955,7 +949,6 @@ struct t_router_opts { std::string write_router_lookahead; std::string read_router_lookahead; - bool disable_check_route; }; struct t_analysis_opts { diff --git a/vpr/src/draw/buttons.cpp b/vpr/src/draw/buttons.cpp index 21a2781ee31..aac65fff2e3 100644 --- a/vpr/src/draw/buttons.cpp +++ b/vpr/src/draw/buttons.cpp @@ -59,7 +59,7 @@ void button_for_toggle_blk_internal() { t_draw_state* draw_state = get_draw_state_vars(); //spin box for toggle_blk_internal, set the range and increment step - GtkWidget* toggle_blk_internal_widget = gtk_spin_button_new_with_range(0., (double)draw_state->max_sub_blk_lvl, 1.); + GtkWidget* toggle_blk_internal_widget = gtk_spin_button_new_with_range(0., (double)(draw_state->max_sub_blk_lvl - 1), 1.); GtkWidget* toggle_blk_internal_label = gtk_label_new("Toggle Block Internal:"); gtk_widget_set_name(toggle_blk_internal_widget, "toggle_blk_internal"); diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index d29ede76133..505928cf667 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -124,7 +124,6 @@ static t_edge_size find_edge(int prev_inode, int inode); static void draw_color_map_legend(const vtr::ColorMap& cmap, ezgl::renderer* g); -ezgl::color get_block_type_color(t_physical_tile_type_ptr type); ezgl::color lighten_color(ezgl::color color, float amount); static void draw_block_pin_util(); @@ -826,7 +825,8 @@ void alloc_draw_structs(const t_arch* arch) { draw_internal_alloc_blk(); draw_state->net_color.resize(cluster_ctx.clb_nlist.nets().size()); - draw_state->block_color.resize(cluster_ctx.clb_nlist.blocks().size()); + draw_state->block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); + draw_state->use_default_block_color_.resize(cluster_ctx.clb_nlist.blocks().size()); /* Space is allocated for draw_rr_node but not initialized because we do * * not yet know information about the routing resources. */ @@ -934,6 +934,7 @@ static void drawplace(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); t_draw_coords* draw_coords = get_draw_coords_vars(); auto& device_ctx = g_vpr_ctx.device(); + auto& cluster_ctx = g_vpr_ctx.clustering(); auto& place_ctx = g_vpr_ctx.placement(); ClusterBlockId bnum; @@ -961,15 +962,20 @@ static void drawplace(ezgl::renderer* g) { if (bnum == INVALID_BLOCK_ID) continue; //Determine the block color ezgl::color block_color; + t_logical_block_type_ptr logical_block_type = nullptr; if (bnum != EMPTY_BLOCK_ID) { - block_color = draw_state->block_color[bnum]; + block_color = draw_state->block_color(bnum); + logical_block_type = cluster_ctx.clb_nlist.block_type(bnum); } else { block_color = get_block_type_color(device_ctx.grid[i][j].type); block_color = lighten_color(block_color, EMPTY_BLOCK_LIGHTEN_FACTOR); + + auto tile_type = device_ctx.grid[i][j].type; + logical_block_type = pick_best_logical_type(tile_type); } g->set_color(block_color); /* Get coords of current sub_tile */ - ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(i, j, k); + ezgl::rectangle abs_clb_bbox = draw_coords->get_absolute_clb_bbox(i, j, k, logical_block_type); ezgl::point2d center = abs_clb_bbox.center(); g->fill_rectangle(abs_clb_bbox); @@ -980,7 +986,6 @@ static void drawplace(ezgl::renderer* g) { g->draw_rectangle(abs_clb_bbox); /* Draw text if the space has parts of the netlist */ if (bnum != EMPTY_BLOCK_ID && bnum != INVALID_BLOCK_ID) { - auto& cluster_ctx = g_vpr_ctx.clustering(); std::string name = cluster_ctx.clb_nlist.block_name(bnum) + vtr::string_fmt(" (#%zu)", size_t(bnum)); g->draw_text(center, name.c_str(), abs_clb_bbox.width(), abs_clb_bbox.height()); @@ -2666,7 +2671,7 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b iclass = physical_tile->pin_class[physical_pin]; if (physical_tile->class_inf[iclass].type == DRIVER) { /* Fanout */ - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanout. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { @@ -2678,11 +2683,11 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b draw_state->net_color[net_id] = DRIVES_IT_COLOR; for (auto pin_id : cluster_ctx.clb_nlist.net_sinks(net_id)) { fanblk = cluster_ctx.clb_nlist.pin_block(pin_id); - draw_state->block_color[fanblk] = DRIVES_IT_COLOR; + draw_state->set_block_color(fanblk, DRIVES_IT_COLOR); } } } else { /* This net is fanin to the block. */ - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanin. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; fanblk = cluster_ctx.clb_nlist.net_driver_block(net_id); /* DRIVER to net */ @@ -2691,17 +2696,17 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, ClusterBlockId b /* Highlight the fanin */ draw_state->net_color[net_id] = DRIVEN_BY_IT_COLOR; fanblk = cluster_ctx.clb_nlist.net_driver_block(net_id); /* DRIVER to net */ - draw_state->block_color[fanblk] = DRIVEN_BY_IT_COLOR; + draw_state->set_block_color(fanblk, DRIVEN_BY_IT_COLOR); } } } - if (draw_state->block_color[blk_id] == SELECTED_COLOR) { + if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the selected block. */ draw_reset_blk_color(blk_id); } else { /* Highlight the selected block. */ - draw_state->block_color[blk_id] = SELECTED_COLOR; + draw_state->set_block_color(blk_id, SELECTED_COLOR); } } @@ -2730,13 +2735,8 @@ void deselect_all() { } static void draw_reset_blk_color(ClusterBlockId blk_id) { - auto& clb_nlist = g_vpr_ctx.clustering().clb_nlist; - - auto logical_block = clb_nlist.block_type(blk_id); - t_draw_state* draw_state = get_draw_state_vars(); - - draw_state->block_color[blk_id] = get_block_type_color(pick_best_physical_type(logical_block)); + draw_state->reset_block_color(blk_id); } /** @@ -3337,7 +3337,7 @@ static void draw_block_pin_util() { for (auto blk : blks) { ezgl::color color = to_ezgl_color(cmap->color(pin_util[blk])); - draw_state->block_color[blk] = color; + draw_state->set_block_color(blk, color); } draw_state->color_map = std::move(cmap); diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index eb8dd4c2df7..acc9d214572 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -77,6 +77,8 @@ void toggle_block_pin_util(GtkWidget* /*widget*/, gint /*response_id*/, gpointer void toggle_router_rr_costs(GtkWidget* /*widget*/, gint /*response_id*/, gpointer /*data*/); void toggle_placement_macros(GtkWidget* /*widget*/, gint /*response_id*/, gpointer /*data*/); +ezgl::color get_block_type_color(t_physical_tile_type_ptr type); + #endif /* NO_GRAPHICS */ #endif /* DRAW_H */ diff --git a/vpr/src/draw/draw_global.h b/vpr/src/draw/draw_global.h index 68e6df6062d..158546f7ec4 100644 --- a/vpr/src/draw/draw_global.h +++ b/vpr/src/draw/draw_global.h @@ -15,8 +15,6 @@ # include "draw_types.h" -# define MAX_BLOCK_COLOURS 5 - constexpr float DEFAULT_ARROW_SIZE = 0.3; // a very small area, in (screen pixels)^2 diff --git a/vpr/src/draw/draw_types.cpp b/vpr/src/draw/draw_types.cpp index 5d6e4ca7a83..fdb0755b689 100644 --- a/vpr/src/draw/draw_types.cpp +++ b/vpr/src/draw/draw_types.cpp @@ -4,11 +4,34 @@ # include "draw_types.h" # include "globals.h" # include "vpr_utils.h" +# include "draw.h" # include /******************************************* * begin t_draw_state function definitions * *******************************************/ +ezgl::color t_draw_state::block_color(ClusterBlockId blk) const { + if (use_default_block_color_[blk]) { + t_physical_tile_type_ptr tile_type = get_physical_tile_type(blk); + return get_block_type_color(tile_type); + } else { + return block_color_[blk]; + } +} + +void t_draw_state::set_block_color(ClusterBlockId blk, ezgl::color color) { + block_color_[blk] = color; + use_default_block_color_[blk] = false; +} + +void t_draw_state::reset_block_color(ClusterBlockId blk) { + use_default_block_color_[blk] = true; +} +void t_draw_state::reset_block_colors() { + std::fill(use_default_block_color_.begin(), + use_default_block_color_.end(), + true); +} void t_draw_state::reset_nets_congestion_and_rr() { show_nets = DRAW_NO_NETS; @@ -19,6 +42,7 @@ void t_draw_state::reset_nets_congestion_and_rr() { bool t_draw_state::showing_sub_blocks() { return show_blk_internal > 0; } + /************************************************** * begin t_draw_pb_type_info function definitions * **************************************************/ @@ -53,14 +77,33 @@ float t_draw_coords::get_tile_height() { ezgl::rectangle t_draw_coords::get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode) { auto& place_ctx = g_vpr_ctx.placement(); - return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, pb_gnode); + auto& cluster_ctx = g_vpr_ctx.clustering(); + return get_pb_bbox(place_ctx.block_locs[clb_index].loc.x, place_ctx.block_locs[clb_index].loc.y, place_ctx.block_locs[clb_index].loc.z, cluster_ctx.clb_nlist.block_type(clb_index), pb_gnode); +} + +ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type, const t_pb_graph_node& pb_gnode) { + auto& device_ctx = g_vpr_ctx.device(); + t_draw_pb_type_info& blk_type_info = this->blk_info.at(logical_block_type->index); + + ezgl::rectangle result = blk_type_info.get_pb_bbox(pb_gnode); + + // if getting clb bbox, apply location info. + if (pb_gnode.is_root()) { + float sub_blk_offset = this->tile_width * (sub_block_index / (float)device_ctx.grid[grid_x][grid_y].type->capacity); + + result += ezgl::point2d(this->tile_x[grid_x], this->tile_y[grid_y]); + if (sub_block_index != 0) { + result += ezgl::point2d(sub_blk_offset, 0); + } + } + return result; } -ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode) { +ezgl::rectangle t_draw_coords::get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { auto& device_ctx = g_vpr_ctx.device(); - const int clb_type_id = device_ctx.grid[grid_x][grid_y].type->index; - t_draw_pb_type_info& blk_type_info = this->blk_info.at(clb_type_id); + t_draw_pb_type_info& blk_type_info = this->blk_info.at(logical_block_type->index); + auto& pb_gnode = *logical_block_type->pb_graph_head; ezgl::rectangle result = blk_type_info.get_pb_bbox(pb_gnode); // if getting clb bbox, apply location info. @@ -89,13 +132,20 @@ ezgl::rectangle t_draw_coords::get_absolute_pb_bbox(const ClusterBlockId clb_ind return result; } -ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type) { - return get_pb_bbox(clb_index, *type->pb_graph_head); +ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr block_type) { + auto& place_ctx = g_vpr_ctx.placement(); + + t_pl_loc loc = place_ctx.block_locs[clb_index].loc; + return get_pb_bbox(loc.x, loc.y, loc.z, block_type); } ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index) { auto& device_ctx = g_vpr_ctx.device(); - return get_pb_bbox(grid_x, grid_y, sub_block_index, *pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)->pb_graph_head); + return get_pb_bbox(grid_x, grid_y, sub_block_index, pick_best_logical_type(device_ctx.grid[grid_x][grid_y].type)); +} + +ezgl::rectangle t_draw_coords::get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr logical_block_type) { + return get_pb_bbox(grid_x, grid_y, sub_block_index, logical_block_type); } #endif // NO_GRAPHICS diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index f6e507a02ac..1ef320afabc 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -172,7 +172,6 @@ struct t_draw_state { e_route_type draw_route_type = GLOBAL; char default_message[vtr::bufsize]; vtr::vector net_color; - vtr::vector block_color; t_draw_rr_node* draw_rr_node = nullptr; std::shared_ptr setup_timing_info; const t_arch* arch_info = nullptr; @@ -185,6 +184,16 @@ struct t_draw_state { void reset_nets_congestion_and_rr(); bool showing_sub_blocks(); + + ezgl::color block_color(ClusterBlockId blk) const; + void set_block_color(ClusterBlockId blk, ezgl::color color); + void reset_block_color(ClusterBlockId blk); + void reset_block_colors(); + + private: + friend void alloc_draw_structs(const t_arch* arch); + vtr::vector block_color_; + vtr::vector use_default_block_color_; }; /* For each cluster type, this structure stores drawing @@ -228,7 +237,8 @@ struct t_draw_coords { * clb, from this data structure */ ezgl::rectangle get_pb_bbox(ClusterBlockId clb_index, const t_pb_graph_node& pb_gnode); - ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_pb_graph_node& pb_gnode); + ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type, const t_pb_graph_node& pb_gnode); + ezgl::rectangle get_pb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr type); /** * Return a bounding box for the given pb in the given @@ -243,6 +253,8 @@ struct t_draw_coords { ezgl::rectangle get_absolute_clb_bbox(const ClusterBlockId clb_index, const t_logical_block_type_ptr type); ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index); + ezgl::rectangle get_absolute_clb_bbox(int grid_x, int grid_y, int sub_block_index, const t_logical_block_type_ptr block_type); + private: float tile_width; friend void init_draw_coords(float); diff --git a/vpr/src/draw/intra_logic_block.cpp b/vpr/src/draw/intra_logic_block.cpp index a3771f7fed5..2c2166ecd95 100644 --- a/vpr/src/draw/intra_logic_block.cpp +++ b/vpr/src/draw/intra_logic_block.cpp @@ -40,7 +40,6 @@ static void draw_internal_load_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, float parent_width, float parent_height); static int draw_internal_find_max_lvl(const t_pb_type& pb_type); static void draw_internal_calc_coords(int type_descrip_index, t_pb_graph_node* pb_graph_node, int num_pb_types, int type_index, int num_pb, int pb_index, float parent_width, float parent_height, float* blk_width, float* blk_height); -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_logical_block_type_ptr type); std::vector collect_pb_atoms(const t_pb* pb); void collect_pb_atoms_recurr(const t_pb* pb, std::vector& atoms); t_pb* highlight_sub_block_helper(const ClusterBlockId clb_index, t_pb* pb, const ezgl::point2d& local_pt, int max_depth); @@ -68,7 +67,7 @@ void draw_internal_alloc_blk() { draw_coords->blk_info.resize(device_ctx.logical_block_types.size()); for (const auto& type : device_ctx.logical_block_types) { - if (&type == device_ctx.EMPTY_LOGICAL_BLOCK_TYPE) { + if (is_empty_type(&type)) { continue; } @@ -90,17 +89,24 @@ void draw_internal_init_blk() { t_pb_graph_node* pb_graph_head_node; auto& device_ctx = g_vpr_ctx.device(); - for (const auto& type : device_ctx.physical_tile_types) { + for (const auto& type : device_ctx.logical_block_types) { /* Empty block has no sub_blocks */ if (is_empty_type(&type)) { continue; } - auto logical_block = pick_best_logical_type(&type); - pb_graph_head_node = logical_block->pb_graph_head; + pb_graph_head_node = type.pb_graph_head; int type_descriptor_index = type.index; - int num_sub_tiles = type.capacity; + //We use the maximum over all tiles which can implement this logical block type + int num_sub_tiles = 1; + int width = 1; + int height = 1; + for (const auto& tile : type.equivalent_tiles) { + num_sub_tiles = std::max(num_sub_tiles, tile->capacity); + width = std::max(width, tile->width); + height = std::max(height, tile->height); + } // set the clb dimensions ezgl::rectangle& clb_bbox = draw_coords->blk_info.at(type_descriptor_index).subblk_array.at(0); @@ -110,17 +116,17 @@ void draw_internal_init_blk() { // note, that all clbs of the same type are the same size, // and that consequently we have *one* model for each type. bot_left = {0, 0}; - if (size_t(type.width) > device_ctx.grid.width() || size_t(type.height) > device_ctx.grid.height()) { + if (size_t(width) > device_ctx.grid.width() || size_t(height) > device_ctx.grid.height()) { // in this case, the clb certainly wont't fit, but this prevents // an out-of-bounds access, and provides some sort of (probably right) // value top_right = ezgl::point2d( - (draw_coords->tile_x[1] - draw_coords->tile_x[0]) * (type.width - 1), - (draw_coords->tile_y[1] - draw_coords->tile_y[0]) * (type.height - 1)); + (draw_coords->tile_x[1] - draw_coords->tile_x[0]) * (width - 1), + (draw_coords->tile_y[1] - draw_coords->tile_y[0]) * (height - 1)); } else { top_right = ezgl::point2d( - draw_coords->tile_x[type.width - 1], - draw_coords->tile_y[type.height - 1]); + draw_coords->tile_x[width - 1], + draw_coords->tile_y[height - 1]); } top_right += ezgl::point2d( draw_coords->get_tile_width() / num_sub_tiles, @@ -131,9 +137,10 @@ void draw_internal_init_blk() { clb_bbox.width(), clb_bbox.height()); /* Determine the max number of sub_block levels in the FPGA */ - draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*logical_block->pb_type), + draw_state->max_sub_blk_lvl = std::max(draw_internal_find_max_lvl(*type.pb_type), draw_state->max_sub_blk_lvl); } + //draw_state->max_sub_blk_lvl -= 1; } # ifndef NO_GRAPHICS @@ -153,7 +160,7 @@ void draw_internal_draw_subblk(ezgl::renderer* g) { continue; /* Don't draw if tile is empty. This includes corners. */ - if (device_ctx.grid[i][j].type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE) + if (is_empty_type(device_ctx.grid[i][j].type)) continue; int num_sub_tiles = device_ctx.grid[i][j].type->capacity; @@ -331,54 +338,33 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg if (pb_type->depth > draw_state->show_blk_internal) { return; } - /// first draw box /// - if (pb_type->depth == 0) { - if (!is_top_lvl_block_highlighted(clb_index, type)) { - // if this is a top level pb, and only if it isn't selected (ie. a funny colour), - // overwrite it. (but stil draw the text) + /// first draw box /// - g->set_color(ezgl::WHITE); - g->fill_rectangle(abs_bbox); - g->set_color(ezgl::BLACK); - g->set_line_dash(ezgl::line_dash::none); - g->draw_rectangle(abs_bbox); + if (pb->name != nullptr) { + // If block is used, draw it in colour with solid border. + g->set_line_dash(ezgl::line_dash::none); + + // determine default background color + if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { + g->set_color(SELECTED_COLOR); + } else if (sel_sub_info.is_sink_of_selected(pb->pb_graph_node, clb_index)) { + g->set_color(DRIVES_IT_COLOR); + } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { + g->set_color(DRIVEN_BY_IT_COLOR); + } else { + g->set_color(draw_state->block_color(clb_index)); } } else { - if (pb->name != nullptr) { - // If block is used, draw it in colour with solid border. - g->set_line_dash(ezgl::line_dash::none); - - // type_index indicates what type of block. - const int type_index = type->index; - - // determine default background color - if (sel_sub_info.is_selected(pb->pb_graph_node, clb_index)) { - g->set_color(SELECTED_COLOR); - } else if (sel_sub_info.is_sink_of_selected(pb->pb_graph_node, clb_index)) { - g->set_color(DRIVES_IT_COLOR); - } else if (sel_sub_info.is_source_of_selected(pb->pb_graph_node, clb_index)) { - g->set_color(DRIVEN_BY_IT_COLOR); - } else if (pb_type->depth != draw_state->show_blk_internal && pb->child_pbs != nullptr) { - g->set_color(ezgl::WHITE); // draw anything else that will have a child as white - } else if (type_index < 3) { - g->set_color(blk_LIGHTGREY); - } else if (type_index < 3 + MAX_BLOCK_COLOURS) { - g->set_color((block_colors[MAX_BLOCK_COLOURS + type_index - 3])); - } else { - g->set_color((block_colors[2 * MAX_BLOCK_COLOURS - 1])); - } - } else { - // If block is not used, draw as empty block (ie. white - // background with dashed border). + // If block is not used, draw as empty block (ie. white + // background with dashed border). - g->set_line_dash(ezgl::line_dash::asymmetric_5_3); - g->set_color(ezgl::WHITE); - } - g->fill_rectangle(abs_bbox); - g->set_color(ezgl::BLACK); - g->draw_rectangle(abs_bbox); + g->set_line_dash(ezgl::line_dash::asymmetric_5_3); + g->set_color(ezgl::WHITE); } + g->fill_rectangle(abs_bbox); + g->set_color(ezgl::BLACK); + g->draw_rectangle(abs_bbox); /// then draw text /// @@ -393,7 +379,7 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg int tot_len = type_len + name_len; char* blk_tag = (char*)vtr::malloc((tot_len + 8) * sizeof(char)); - sprintf(blk_tag, "%s(%s)", pb_type->name, pb->name); + sprintf(blk_tag, "%s (%s)", pb_type->name, pb->name); g->draw_text( abs_bbox.center(), @@ -444,10 +430,10 @@ static void draw_internal_pb(const ClusterBlockId clb_index, t_pb* pb, const ezg t_pb_type* pb_child_type = child_pb->pb_graph_node->pb_type; - // don't go farther if 0 modes - if (pb_child_type == nullptr || pb_child_type->num_modes == 0) { + if (pb_child_type == nullptr) { continue; } + // now recurse draw_internal_pb(clb_index, child_pb, abs_bbox, type, g); } @@ -662,31 +648,6 @@ void draw_one_logical_connection(const AtomPinId src_pin, const AtomPinId sink_p } # endif /* NO_GRAPHICS */ -/* This function checks whether a top-level clb has been highlighted. It does - * so by checking whether the color in this block is default color. - */ -static bool is_top_lvl_block_highlighted(const ClusterBlockId blk_id, const t_logical_block_type_ptr type) { - t_draw_state* draw_state; - - /* Call accessor function to retrieve global variables. */ - draw_state = get_draw_state_vars(); - - if (type->index < 3) { - if (draw_state->block_color[blk_id] == blk_LIGHTGREY) - return false; - } else if (type->index < 3 + MAX_BLOCK_COLOURS) { - if (draw_state->block_color[blk_id] == block_colors[MAX_BLOCK_COLOURS + type->index - 3]) - // if (draw_state->block_color[blk_id] == to_ezgl_color((color_types)(BISQUE + MAX_BLOCK_COLOURS + type->index - 3))) - return false; - } else { - if (draw_state->block_color[blk_id] == block_colors[2 * MAX_BLOCK_COLOURS - 1]) - // if (draw_state->block_color[blk_id] == to_ezgl_color((color_types)(BISQUE + 2 * MAX_BLOCK_COLOURS - 1))) - return false; - } - - return true; -} - int highlight_sub_block(const ezgl::point2d& point_in_clb, ClusterBlockId clb_index, t_pb* pb) { t_draw_state* draw_state = get_draw_state_vars(); diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index c79d8647578..6631e3f70e8 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -167,7 +167,6 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca ClusterBlockId blk_id; auto& cluster_ctx = g_vpr_ctx.clustering(); - auto& device_ctx = g_vpr_ctx.device(); auto& place_ctx = g_vpr_ctx.placement(); auto& pl_macros = place_ctx.pl_macros; @@ -185,9 +184,7 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca return lhs_num_tiles < rhs_num_tiles; }; - if (device_ctx.has_multiple_equivalent_tiles) { - std::sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); - } + std::stable_sort(sorted_pl_macros.begin(), sorted_pl_macros.end(), criteria); /* Macros are harder to place. Do them first */ for (auto pl_macro : sorted_pl_macros) { @@ -196,57 +193,57 @@ static void initial_placement_pl_macros(int macros_max_num_tries, int* free_loca // Assume that all the blocks in the macro are of the same type blk_id = pl_macro.members[0].blk_index; - auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - auto type = pick_placement_type(logical_block, int(pl_macro.members.size()), free_locations); - - if (type == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n" - "VPR cannot auto-size for your circuit, please resize the FPGA manually.\n", - pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); - } - - itype = type->index; - - // Try to place the macro first, if can be placed - place them, otherwise try again - for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) { - // Choose a random position for the head - ipos = vtr::irand(free_locations[itype] - 1); + auto block_type = cluster_ctx.clb_nlist.block_type(blk_id); - // Try to place the macro - macro_placed = try_place_macro(itype, ipos, pl_macro); + for (auto tile_type : block_type->equivalent_tiles) { //Try each possible tile type + itype = tile_type->index; - } // Finished all tries + // Try to place the macro first, if can be placed - place them, otherwise try again + for (itry = 0; itry < macros_max_num_tries && macro_placed == false; itry++) { + // Choose a random position for the head + ipos = vtr::irand(free_locations[itype] - 1); - if (macro_placed == false) { - // if a macro still could not be placed after macros_max_num_tries times, - // go through the chip exhaustively to find a legal placement for the macro - // place the macro on the first location that is legal - // then set macro_placed = true; - // if there are no legal positions, error out - - // Exhaustive placement of carry macros - for (ipos = 0; ipos < free_locations[itype] && macro_placed == false; ipos++) { // Try to place the macro macro_placed = try_place_macro(itype, ipos, pl_macro); - } // Exhausted all the legal placement position for this macro + } // Finished all tries - // If macro could not be placed after exhaustive placement, error out if (macro_placed == false) { - // Error out - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type %s (#%d).\n" - "Please manually size the FPGA because VPR can't do this yet.\n", - pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), device_ctx.physical_tile_types[itype].name, itype); + // if a macro still could not be placed after macros_max_num_tries times, + // go through the chip exhaustively to find a legal placement for the macro + // place the macro on the first location that is legal + // then set macro_placed = true; + // if there are no legal positions, error out + + // Exhaustive placement of carry macros + for (ipos = 0; ipos < free_locations[itype] && macro_placed == false; ipos++) { + // Try to place the macro + macro_placed = try_place_macro(itype, ipos, pl_macro); + + } // Exhausted all the legal placement position for this macro + + // If macro could not be placed after exhaustive placement, error out + } else { + // This macro has been placed successfully + break; } + } - } else { - // This macro has been placed successfully, proceed to place the next macro - continue; + if (macro_placed == false) { + std::vector tried_types; + for (auto tile_type : block_type->equivalent_tiles) { + tried_types.push_back(tile_type->name); + } + std::string tried_types_str = "{" + vtr::join(tried_types, ", ") + "}"; + + // Error out + VPR_FATAL_ERROR(VPR_ERROR_PLACE, + "Initial placement failed.\n" + "Could not place macro length %zu with head block %s (#%zu); not enough free locations of type(s) %s.\n" + "Please manually size the FPGA because VPR can't do this yet.\n", + pl_macro.members.size(), cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), tried_types_str.c_str()); } + } // Finish placing all the pl_macros successfully } @@ -285,46 +282,49 @@ static void initial_placement_blocks(int* free_locations, enum e_pad_loc_type pa auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id); - /* Randomly select a free location of the appropriate type for blk_id. - * We have a linearized list of all the free locations that can - * accommodate a block of that type in free_locations[itype]. - * Choose one randomly and put blk_id there. Then we don't want to pick - * that location again, so remove it from the free_locations array. - */ + /* Don't do IOs if the user specifies IOs; we'll read those locations later. */ + if (!(is_io_type(pick_best_physical_type(logical_block)) && pad_loc_type == USER)) { + /* Randomly select a free location of the appropriate type for blk_id. + * We have a linearized list of all the free locations that can + * accommodate a block of that type in free_locations[itype]. + * Choose one randomly and put blk_id there. Then we don't want to pick + * that location again, so remove it from the free_locations array. + */ - auto type = pick_placement_type(logical_block, 1, free_locations); + auto type = pick_placement_type(logical_block, 1, free_locations); - if (type == nullptr) { - VPR_FATAL_ERROR(VPR_ERROR_PLACE, - "Initial placement failed.\n" - "Could not place block %s (#%zu); no free locations of type %s (#%d).\n", - cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); - } + if (type == nullptr) { + VPR_FATAL_ERROR(VPR_ERROR_PLACE, + "Initial placement failed.\n" + "Could not place block %s (#%zu); no free locations of type %s (#%d).\n", + cluster_ctx.clb_nlist.block_name(blk_id).c_str(), size_t(blk_id), logical_block->name, logical_block->index); + } - itype = type->index; + itype = type->index; - t_pl_loc to; - initial_placement_location(free_locations, ipos, itype, to); + t_pl_loc to; + initial_placement_location(free_locations, ipos, itype, to); - // Make sure that the position is EMPTY_BLOCK before placing the block down - VTR_ASSERT(place_ctx.grid_blocks[to.x][to.y].blocks[to.z] == EMPTY_BLOCK_ID); + // Make sure that the position is EMPTY_BLOCK before placing the block down + VTR_ASSERT(place_ctx.grid_blocks[to.x][to.y].blocks[to.z] == EMPTY_BLOCK_ID); - place_ctx.grid_blocks[to.x][to.y].blocks[to.z] = blk_id; - place_ctx.grid_blocks[to.x][to.y].usage++; + place_ctx.grid_blocks[to.x][to.y].blocks[to.z] = blk_id; + place_ctx.grid_blocks[to.x][to.y].usage++; - place_ctx.block_locs[blk_id].loc = to; + place_ctx.block_locs[blk_id].loc = to; - //Mark IOs as fixed if specifying a (fixed) random placement - if (is_io_type(pick_best_physical_type(logical_block)) && pad_loc_type == RANDOM) { - place_ctx.block_locs[blk_id].is_fixed = true; - } + //Mark IOs as fixed if specifying a (fixed) random placement + if (is_io_type(pick_best_physical_type(logical_block)) && pad_loc_type == RANDOM) { + place_ctx.block_locs[blk_id].is_fixed = true; + } - /* Ensure randomizer doesn't pick this location again, since it's occupied. Could shift all the - * legal positions in legal_pos to remove the entry (choice) we just used, but faster to - * just move the last entry in legal_pos to the spot we just used and decrement the - * count of free_locations. */ - legal_pos[itype][ipos] = legal_pos[itype][free_locations[itype] - 1]; /* overwrite used block position */ - free_locations[itype]--; + /* Ensure randomizer doesn't pick this location again, since it's occupied. Could shift all the + * legal positions in legal_pos to remove the entry (choice) we just used, but faster to + * just move the last entry in legal_pos to the spot we just used and decrement the + * count of free_locations. */ + legal_pos[itype][ipos] = legal_pos[itype][free_locations[itype] - 1]; /* overwrite used block position */ + free_locations[itype]--; + } } } @@ -394,10 +394,6 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, place_ctx.block_locs[blk_id].loc = t_pl_loc(); } - if (pad_loc_type == USER) { - read_user_pad_loc(pad_loc_file); - } - initial_placement_pl_macros(MAX_NUM_TRIES_TO_PLACE_MACROS_RANDOMLY, free_locations); // All the macros are placed, update the legal_pos[][] array @@ -421,6 +417,10 @@ void initial_placement(enum e_pad_loc_type pad_loc_type, initial_placement_blocks(free_locations, pad_loc_type); + if (pad_loc_type == USER) { + read_user_pad_loc(pad_loc_file); + } + /* Restore legal_pos */ load_legal_placement_locations(); diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index ef00c65cbbe..b2ea57bf1c5 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -217,8 +217,8 @@ e_block_move_result record_macro_macro_swaps(t_pl_blocks_to_be_moved& blocks_aff //At the moment, we only support blk_to being the first element of the 'to' macro. // //For instance, this means that we can swap two carry chains so long as one starts - //below the other (not a big limitation since swapping in the oppostie direction would - //allow these blocks to swap) + //below the other (not a big limitation since swapping in the opposite direction + //allows these blocks to swap) if (place_ctx.pl_macros[imacro_to].members[0].blk_index != blk_to) { int imember_to = 0; auto outcome = record_macro_swaps(blocks_affected, imacro_to, imember_to, -swap_offset); diff --git a/vpr/src/place/place.cpp b/vpr/src/place/place.cpp index 8a2b32fd962..0d82de03fdf 100644 --- a/vpr/src/place/place.cpp +++ b/vpr/src/place/place.cpp @@ -800,6 +800,8 @@ void try_place(const t_placer_opts& placer_opts, size_t total_swap_attempts = num_swap_rejected + num_swap_accepted + num_swap_aborted; VTR_ASSERT(total_swap_attempts > 0); + print_resources_utilization(); + size_t num_swap_print_digits = ceil(log10(total_swap_attempts)); float reject_rate = (float)num_swap_rejected / total_swap_attempts; float accept_rate = (float)num_swap_accepted / total_swap_attempts; @@ -812,8 +814,6 @@ void try_place(const t_placer_opts& placer_opts, report_aborted_moves(); - print_resources_utilization(); - free_placement_structs(placer_opts); if (placer_opts.place_algorithm == PATH_TIMING_DRIVEN_PLACE || placer_opts.enable_timing_computations) { @@ -2572,6 +2572,9 @@ static void print_resources_utilization() { auto& cluster_ctx = g_vpr_ctx.clustering(); auto& device_ctx = g_vpr_ctx.device(); + int max_block_name = 0; + int max_tile_name = 0; + //Record the resource requirement std::map num_type_instances; std::map> num_placed_instances; @@ -2584,15 +2587,17 @@ static void print_resources_utilization() { num_type_instances[logical_block]++; num_placed_instances[logical_block][physical_tile]++; + + max_block_name = std::max(max_block_name, strlen(logical_block->name)); + max_tile_name = std::max(max_tile_name, strlen(physical_tile->name)); } + VTR_LOG("\n"); + VTR_LOG("Placement resource usage:\n"); for (auto logical_block : num_type_instances) { - VTR_LOG("Logical Block: %s\n", logical_block.first->name); - VTR_LOG("\tInstances -> %d\n", logical_block.second); - - VTR_LOG("\tPhysical Tiles used:\n"); for (auto physical_tile : num_placed_instances[logical_block.first]) { - VTR_LOG("\t\t%s: %d\n", physical_tile.first->name, physical_tile.second); + VTR_LOG(" %-*s implemented as %-*s: %d\n", max_block_name, logical_block.first->name, max_tile_name, physical_tile.first->name, physical_tile.second); } } + VTR_LOG("\n"); } diff --git a/vpr/src/place/place_delay_model.cpp b/vpr/src/place/place_delay_model.cpp index 75342d54fed..a7bfc674895 100644 --- a/vpr/src/place/place_delay_model.cpp +++ b/vpr/src/place/place_delay_model.cpp @@ -239,11 +239,7 @@ void DeltaDelayModel::write(const std::string& file) const { void OverrideDelayModel::read(const std::string& file) { MmapFile f(file); - - /* Increase reader limit to 1G words. */ - ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); - opts.traversalLimitInWords = 1024 * 1024 * 1024; - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); + ::capnp::FlatArrayMessageReader reader(f.getData()); vtr::Matrix delays; auto model = reader.getRoot(); diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index c065d56e504..4aa439aab16 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -68,7 +68,6 @@ struct t_profile_info { static t_chan_width setup_chan_width(const t_router_opts& router_opts, t_chan_width_dist chan_width_dist); -#if 0 static float route_connection_delay( const RouterDelayProfiler& route_profiler, int source_x_loc, @@ -90,20 +89,6 @@ static void generic_compute_matrix( const t_router_opts& router_opts, bool measure_directconnect, const std::set& allowed_types); -#endif - -static void generic_compute_matrix_expand( - const RouterDelayProfiler& route_profiler, - vtr::Matrix>& matrix, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types); static vtr::Matrix compute_delta_delays( const RouterDelayProfiler& route_profiler, @@ -296,7 +281,6 @@ static t_chan_width setup_chan_width(const t_router_opts& router_opts, return init_chan(width_fac, chan_width_dist); } -#if 0 static float route_connection_delay( const RouterDelayProfiler& route_profiler, int source_x, @@ -355,154 +339,7 @@ static float route_connection_delay( return (net_delay_value); } -#endif - -static void add_delay_to_matrix( - vtr::Matrix>* matrix, - int delta_x, - int delta_y, - float delay) { - if ((*matrix)[delta_x][delta_y].size() == 1 && (*matrix)[delta_x][delta_y][0] == EMPTY_DELTA) { - //Overwrite empty delta - (*matrix)[delta_x][delta_y][0] = delay; - } else { - //Collect delta - (*matrix)[delta_x][delta_y].push_back(delay); - } -} - -static void generic_compute_matrix_expand( - const RouterDelayProfiler& /*route_profiler*/, - vtr::Matrix>& matrix, - int source_x, - int source_y, - int start_x, - int start_y, - int end_x, - int end_y, - const t_router_opts& router_opts, - bool measure_directconnect, - const std::set& allowed_types) { - auto& device_ctx = g_vpr_ctx.device(); - - t_physical_tile_type_ptr src_type = device_ctx.grid[source_x][source_y].type; - bool is_allowed_type = allowed_types.empty() || allowed_types.find(src_type->name) != allowed_types.end(); - if (is_empty_type(src_type) || !is_allowed_type) { - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - } - } - } - - return; - } - - vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); - - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid[source_x][source_y].type); - for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); - int source_rr_node = get_rr_node_index(device_ctx.rr_node_indices, source_x, source_y, SOURCE, driver_ptc); - auto delays = calculate_all_path_delays_from_rr_node(source_rr_node, router_opts); - - bool path_to_all_sinks = true; - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - - if (found_matrix[delta_x][delta_y]) { - continue; - } - - t_physical_tile_type_ptr sink_type = device_ctx.grid[sink_x][sink_y].type; - if (is_empty_type(sink_type)) { - found_matrix[delta_x][delta_y] = true; - if (matrix[delta_x][delta_y].empty()) { - //Only set empty target if we don't already have a valid delta delay - matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE - VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", - "EMPTY", - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - } - } else { - bool found_a_sink = false; - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid[sink_x][sink_y].type); - for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); - - int sink_rr_node = get_rr_node_index(device_ctx.rr_node_indices, sink_x, sink_y, SINK, sink_ptc); - - VTR_ASSERT(sink_rr_node != OPEN); - - if (!measure_directconnect && directconnect_exists(source_rr_node, sink_rr_node)) { - //Skip if we shouldn't measure direct connects and a direct connect exists - continue; - } - - if (std::isnan(delays[sink_rr_node])) { - // This sink was not found - continue; - } - -#ifdef VERBOSE - VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", - delay, - delta_x, delta_y, - source_x, source_y, - sink_x, sink_y); -#endif - found_matrix[delta_x][delta_y] = true; - - add_delay_to_matrix(&matrix, delta_x, delta_y, delays[sink_rr_node]); - - found_a_sink = true; - break; - } - - if (!found_a_sink) { - path_to_all_sinks = false; - } - } - } - } - - if (path_to_all_sinks) { - break; - } - } - - for (int sink_x = start_x; sink_x <= end_x; sink_x++) { - for (int sink_y = start_y; sink_y <= end_y; sink_y++) { - int delta_x = abs(sink_x - source_x); - int delta_y = abs(sink_y - source_y); - if (!found_matrix[delta_x][delta_y]) { - add_delay_to_matrix(&matrix, delta_x, delta_y, IMPOSSIBLE_DELTA); - VTR_LOG_WARN("Unable to route between blocks at (%d,%d) and (%d,%d) to characterize delay (setting to %g)\n", - source_x, source_y, sink_x, sink_y, IMPOSSIBLE_DELTA); - } - } - } -} -#if 0 static void generic_compute_matrix( const RouterDelayProfiler& route_profiler, vtr::Matrix>& matrix, @@ -537,26 +374,26 @@ static void generic_compute_matrix( if (matrix[delta_x][delta_y].empty()) { //Only set empty target if we don't already have a valid delta delay matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -# ifdef VERBOSE +#ifdef VERBOSE VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", "EMPTY", delta_x, delta_y, source_x, source_y, sink_x, sink_y); -# endif +#endif } } else { //Valid start/end float delay = route_connection_delay(route_profiler, source_x, source_y, sink_x, sink_y, router_opts, measure_directconnect); -# ifdef VERBOSE +#ifdef VERBOSE VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", delay, delta_x, delta_y, source_x, source_y, sink_x, sink_y); -# endif +#endif if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { //Overwrite empty delta matrix[delta_x][delta_y][0] = delay; @@ -568,7 +405,6 @@ static void generic_compute_matrix( } } } -#endif static vtr::Matrix compute_delta_delays( const RouterDelayProfiler& route_profiler, @@ -590,14 +426,8 @@ static vtr::Matrix compute_delta_delays( size_t low_x = std::min(longest_length, mid_x); size_t low_y = std::min(longest_length, mid_y); - size_t high_x = mid_x; - size_t high_y = mid_y; - if (longest_length <= grid.width()) { - high_x = std::max(grid.width() - longest_length, mid_x); - } - if (longest_length <= grid.height()) { - high_y = std::max(grid.height() - longest_length, mid_y); - } + size_t high_x = std::max(grid.width() - longest_length, mid_x); + size_t high_y = std::max(grid.height() - longest_length, mid_y); std::set allowed_types; if (!placer_opts.allowed_tiles_for_delay_model.empty()) { @@ -658,12 +488,12 @@ static vtr::Matrix compute_delta_delays( #ifdef VERBOSE VTR_LOG("Computing from lower left edge (%d,%d):\n", x, y); #endif - generic_compute_matrix_expand(route_profiler, sampled_delta_delays, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix(route_profiler, sampled_delta_delays, + x, y, + x, y, + grid.width() - 1, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Find the lowest x location on the bottom edge with a non-empty block src_type = nullptr; @@ -687,60 +517,60 @@ static vtr::Matrix compute_delta_delays( #ifdef VERBOSE VTR_LOG("Computing from left bottom edge (%d,%d):\n", x, y); #endif - generic_compute_matrix_expand(route_profiler, sampled_delta_delays, - x, y, - x, y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix(route_profiler, sampled_delta_delays, + x, y, + x, y, + grid.width() - 1, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions B, C, E, F #ifdef VERBOSE VTR_LOG("Computing from low/low:\n"); #endif - generic_compute_matrix_expand(route_profiler, sampled_delta_delays, - low_x, low_y, - low_x, low_y, - grid.width() - 1, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix(route_profiler, sampled_delta_delays, + low_x, low_y, + low_x, low_y, + grid.width() - 1, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions D, E, G, H #ifdef VERBOSE VTR_LOG("Computing from high/high:\n"); #endif - generic_compute_matrix_expand(route_profiler, sampled_delta_delays, - high_x, high_y, - 0, 0, - high_x, high_y, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix(route_profiler, sampled_delta_delays, + high_x, high_y, + 0, 0, + high_x, high_y, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions A, B, D, E #ifdef VERBOSE VTR_LOG("Computing from high/low:\n"); #endif - generic_compute_matrix_expand(route_profiler, sampled_delta_delays, - high_x, low_y, - 0, low_y, - high_x, grid.height() - 1, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix(route_profiler, sampled_delta_delays, + high_x, low_y, + 0, low_y, + high_x, grid.height() - 1, + router_opts, + measure_directconnect, allowed_types); //Since the other delta delay values may have suffered from edge effects, //we recalculate deltas within regions E, F, H, I #ifdef VERBOSE VTR_LOG("Computing from low/high:\n"); #endif - generic_compute_matrix_expand(route_profiler, sampled_delta_delays, - low_x, high_y, - low_x, 0, - grid.width() - 1, high_y, - router_opts, - measure_directconnect, allowed_types); + generic_compute_matrix(route_profiler, sampled_delta_delays, + low_x, high_y, + low_x, 0, + grid.width() - 1, high_y, + router_opts, + measure_directconnect, allowed_types); vtr::Matrix delta_delays({grid.width(), grid.height()}); for (size_t dx = 0; dx < sampled_delta_delays.dim_size(0); ++dx) { diff --git a/vpr/src/route/bucket.cpp b/vpr/src/route/bucket.cpp deleted file mode 100644 index da7a4ca99ad..00000000000 --- a/vpr/src/route/bucket.cpp +++ /dev/null @@ -1,213 +0,0 @@ -#include "bucket.h" - -std::vector BucketItems::heap_items_; -size_t BucketItems::alloced_items_ = 0; -int BucketItems::num_heap_allocated_ = 0; -t_heap* BucketItems::heap_free_head_ = nullptr; -vtr::t_chunk BucketItems::heap_ch_; - -void Bucket::init(const DeviceGrid& grid) { - vtr::free(heap_); - heap_ = nullptr; - - heap_size_ = (grid.width() - 1) * (grid.height() - 1); - heap_ = (t_heap**)vtr::malloc(heap_size_ * sizeof(t_heap*)); - memset(heap_, 0, heap_size_ * sizeof(t_heap*)); - - heap_head_ = std::numeric_limits::max(); - heap_tail_ = 0; - - conv_factor_ = kDefaultConvFactor; - - min_cost_ = std::numeric_limits::max(); - max_cost_ = std::numeric_limits::min(); -} - -void Bucket::free() { - vtr::free(heap_); - heap_ = nullptr; -} - -void Bucket::expand(size_t required_number_of_buckets) { - auto old_size = heap_size_; - heap_size_ = required_number_of_buckets * 2; - - heap_ = (t_heap**)vtr::realloc((void*)(heap_), - heap_size_ * sizeof(t_heap*)); - std::fill(heap_ + old_size, heap_ + heap_size_, nullptr); -} - -void Bucket::verify() { - for (size_t bucket = heap_head_; bucket <= heap_tail_; ++bucket) { - for (t_heap* data = heap_[bucket]; data != nullptr; - data = data->next_bucket) { - VTR_ASSERT(data->cost > 0 && ((size_t)cost_to_int(data->cost)) == bucket); - } - } -} - -size_t Bucket::seed_ = 1231; -t_heap** Bucket::heap_ = nullptr; -size_t Bucket::heap_size_ = 0; -size_t Bucket::heap_head_ = std::numeric_limits::max(); -size_t Bucket::heap_tail_ = 0; -float Bucket::min_cost_ = 0.f; -float Bucket::max_cost_ = 0.f; -float Bucket::conv_factor_ = 0.f; - -void Bucket::clear() { - if (heap_head_ != std::numeric_limits::max()) { - std::fill(heap_ + heap_head_, heap_ + heap_tail_ + 1, nullptr); - } - heap_head_ = std::numeric_limits::max(); - heap_tail_ = 0; -} - -void Bucket::check_scaling() { - float min_cost = min_cost_; - float max_cost = max_cost_; - VTR_ASSERT(max_cost != std::numeric_limits::min()); - if (min_cost == std::numeric_limits::max()) { - min_cost = max_cost; - } - auto min_bucket = cost_to_int(min_cost); - auto max_bucket = cost_to_int(max_cost); - - if (min_bucket < 0 || max_bucket < 0 || max_bucket > 1000000) { - // If min and max are close to each other, assume 3 orders of - // magnitude between min and max. - // - // If min and max are at least 3 orders of magnitude apart, scale - // soley based on max cost. - conv_factor_ = 50000.f / max_cost_ / std::max(1.f, 1000.f / (max_cost_ / min_cost_)); - - VTR_ASSERT(cost_to_int(min_cost_) >= 0); - VTR_ASSERT(cost_to_int(max_cost_) >= 0); - VTR_ASSERT(cost_to_int(max_cost_) < 1000000); - - // Reheap after adjusting scaling. - if (heap_head_ != std::numeric_limits::max()) { - std::vector reheap; - for (size_t bucket = heap_head_; bucket <= heap_tail_; ++bucket) { - for (t_heap* item = heap_[bucket]; item != nullptr; item = item->next_bucket) { - reheap.push_back(item); - } - } - - std::fill(heap_ + heap_head_, heap_ + heap_tail_ + 1, nullptr); - heap_head_ = std::numeric_limits::max(); - heap_tail_ = 0; - - for (t_heap* item : reheap) { - push(item); - } - } - } -} - -void Bucket::push(t_heap* hptr) { - float cost = hptr->cost; - if (!std::isfinite(cost)) { - return; - } - - bool check_scale = false; - // Exclude 0 cost from min_cost to provide useful scaling factor. - if (cost < min_cost_ && cost > 0) { - min_cost_ = cost; - check_scale = true; - } - if (cost > max_cost_) { - max_cost_ = cost; - check_scale = true; - } - - if (check_scale) { - check_scaling(); - } - - // Which bucket should this go into? - auto int_cost = cost_to_int(cost); - - if (int_cost < 0) { - VTR_LOG_WARN("Cost is negative? cost = %g, bucket = %d\n", cost, int_cost); - int_cost = 0; - } - - size_t uint_cost = int_cost; - - // Is that bucket allocated? - if (uint_cost >= heap_size_) { - // Not enough buckets! - expand(uint_cost); - } - - // Insert into bucket - auto* prev = heap_[uint_cost]; - hptr->next_bucket = prev; - heap_[uint_cost] = hptr; - - if (uint_cost < heap_head_) { - heap_head_ = uint_cost; - } - if (uint_cost > heap_tail_) { - heap_tail_ = uint_cost; - } -} - -t_heap* Bucket::pop() { - auto heap_head = heap_head_; - auto heap_tail = heap_tail_; - t_heap** heap = heap_; - - // Check empty - if (heap_head == std::numeric_limits::max()) { - return nullptr; - } - - // Find first non-empty bucket - - // Randomly remove element - size_t count = fast_rand() % 4; - - t_heap* prev = nullptr; - t_heap* next = heap[heap_head]; - for (size_t i = 0; i < count && next->next_bucket != nullptr; ++i) { - prev = next; - next = prev->next_bucket; - } - - if (prev == nullptr) { - heap[heap_head] = next->next_bucket; - } else { - prev->next_bucket = next->next_bucket; - } - - // Update first non-empty bucket if bucket is now empty - if (heap[heap_head] == nullptr) { - heap_head += 1; - while (heap_head <= heap_tail && heap[heap_head] == nullptr) { - heap_head += 1; - } - - if (heap_head > heap_tail) { - heap_head = std::numeric_limits::max(); - } - - heap_head_ = heap_head; - } - - return next; -} - -void Bucket::print() { - for (size_t i = heap_head_; i < heap_tail_; ++i) { - if (heap_[heap_head_] != nullptr) { - VTR_LOG("B:%d ", i); - for (auto* item = heap_[i]; item != nullptr; item = item->next_bucket) { - VTR_LOG(" %e", item->cost); - } - } - } - VTR_LOG("\n"); -} diff --git a/vpr/src/route/bucket.h b/vpr/src/route/bucket.h deleted file mode 100644 index 8426fc48d26..00000000000 --- a/vpr/src/route/bucket.h +++ /dev/null @@ -1,338 +0,0 @@ -#ifndef _BUCKET_ITEMS_H_ -#define _BUCKET_ITEMS_H_ - -#include - -#include "netlist_fwd.h" -#include "physical_types.h" -#include "vtr_memory.h" -#include "globals.h" - -/* Used by the heap as its fundamental data structure. - * Each heap element represents a partial route. - * - * cost: The cost used to sort heap. - * For the timing-driven router this is the backward_path_cost + - * expected cost to the target. - * For the breadth-first router it is the node cost to reach this - * point. - * - * backward_path_cost: Used only by the timing-driven router. The "known" - * cost of the path up to and including this node. - * In this case, the .cost member contains not only - * the known backward cost but also an expected cost - * to the target. - * - * R_upstream: Used only by the timing-driven router. Stores the upstream - * resistance to ground from this node, including the - * resistance of the node itself (device_ctx.rr_nodes[index].R). - * - * index: The RR node index associated with the costs/R_upstream values - * - * u.prev.node: The previous node used to reach the current 'index' node - * u.prev.next: The edge from u.prev.node used to reach the current 'index' node - * - * u.next: pointer to the next s_heap structure in the free - * linked list. Not used when on the heap. - * - */ -struct t_heap { - float cost = 0.; - float backward_path_cost = 0.; - float R_upstream = 0.; - - int index = OPEN; - - struct t_prev { - int node; - int edge; - }; - - union { - t_heap* next; - t_prev prev; - } u; - - // Next pointer for Bucket linked list. - t_heap* next_bucket; -}; - -// Allocator for t_heap items. -// -// Supports fast clearing of the items, under the assumption that when clear -// is invoked, all outstanding references can be dropped. This should be true -// between net routing, and avoids the need to rebuild the free list between -// nets. -class BucketItems { - public: - // Returns all allocated items to be available for allocation. - // - // This operation is only safe if all outstanding references are discarded. - // This is true when the router is starting on a new net, as all outstanding - // items should be in the bucket, which is cleared at the start of routing. - static void clear() { - heap_free_head_ = nullptr; - num_heap_allocated_ = 0; - alloced_items_ = 0; - } - - // Iterators over all items ever allocated. This is not the list of alive - // items, but can be used for fast invalidation if needed. - static std::vector::iterator begin() { - return heap_items_.begin(); - } - static std::vector::iterator end() { - return heap_items_.end(); - } - - // Deallocate all items. Outstanding references to items will become - // invalid. - static void free() { - // Free each individual heap item. - for (auto* item : heap_items_) { - vtr::chunk_delete(item, &heap_ch_); - } - heap_items_.clear(); - - /*free the memory chunks that were used by heap and linked f pointer */ - free_chunk_memory(&heap_ch_); - } - - // Allocate an item. This may cause a dynamic allocation if no previously - // allocated items are available. - static t_heap* alloc_item() { - t_heap* temp_ptr; - if (alloced_items_ < heap_items_.size()) { - temp_ptr = heap_items_[alloced_items_++]; - } else { - if (heap_free_head_ == nullptr) { /* No elements on the free list */ - heap_free_head_ = vtr::chunk_new(&heap_ch_); - heap_items_.push_back(heap_free_head_); - alloced_items_ += 1; - } - - temp_ptr = heap_free_head_; - heap_free_head_ = heap_free_head_->u.next; - } - - num_heap_allocated_++; - - return temp_ptr; - } - - // Return a free'd item to be reallocated. - static void free_item(t_heap* hptr) { - hptr->u.next = heap_free_head_; - heap_free_head_ = hptr; - num_heap_allocated_--; - } - - // Number of outstanding allocations. - static int num_heap_allocated() { - return num_heap_allocated_; - } - - private: - /* Vector of all items ever allocated. Used for full item iteration and - * for reuse after a `clear` invocation. */ - static std::vector heap_items_; - - /* Tracks how many items from heap_items_ are in use. */ - static size_t alloced_items_; - - /* Number of outstanding allocated items. */ - static int num_heap_allocated_; - - /* For managing my own list of currently free heap data structures. */ - static t_heap* heap_free_head_; - - /* For keeping track of the sudo malloc memory for the heap*/ - static vtr::t_chunk heap_ch_; -}; - -inline void free_heap_data(t_heap* hptr) { - BucketItems::free_item(hptr); -} - -inline t_heap* -alloc_heap_data() { - //Extract the head - t_heap* temp_ptr = BucketItems::alloc_item(); - - //Reset - temp_ptr->u.next = nullptr; - temp_ptr->next_bucket = nullptr; - temp_ptr->cost = 0.; - temp_ptr->backward_path_cost = 0.; - temp_ptr->R_upstream = 0.; - temp_ptr->index = OPEN; - temp_ptr->u.prev.node = NO_PREVIOUS; - temp_ptr->u.prev.edge = NO_PREVIOUS; - return (temp_ptr); -} - -// Prority queue approximation using cost buckets and randomization. -// -// The Bucket contains linked lists for costs at kConvFactor intervals. Given -// that cost is approximately delay, each bucket contains ~1 picosecond (1e12) -// worth items. -// -// Items are pushed into the linked list that matches their cost [0, 1) -// picosecond. When popping the Bucket, a random item in the cheapest bucket -// with items is returned. This randomization exists to prevent the router -// from following identical paths when operating with identical costs. -// Consider two parallel paths to a node. -// -// Important node: This approximation makes some assumptions about the -// structure of costs. -// -// Assumptions: -// 1. 0 is the minimum cost -// 2. Costs that are different by 0.1 % of the maximum cost are effectively -// equivilant -// 3. The cost function is roughly linear. -// -class Bucket { - public: - Bucket() {} - - // Allocate initial buckets for items. - static void init(const DeviceGrid& grid); - - // Deallocate memory for buckets. This does NOT call - // BucketItems::free_item on contained items. - static void free(); - - // Empties all buckets of items. - // - // This does NOT call BucketItems::free_item on contained items. The - // assumption is that when Bucket::clear is called, BucketItems::clear - // is also called. - static void clear(); - - // Push an item onto a bucket. - static void push(t_heap* hptr); - - // Pop an item from the cheapest non-empty bucket. - // - // Returns nullptr if empty. - static t_heap* pop(); - - // True if all buckets are empty. - static bool empty() { - return heap_head_ == std::numeric_limits::max(); - } - - // Sanity check state of buckets (e.g. all items within each bucket have - // a cost that matches their bucket index. - static void verify(); - - // Print items contained in buckets. - static void print(); - - private: - // Factor used to convert cost from float to int. Should be scaled to - // enable sufficent precision in bucketting. - static constexpr float kDefaultConvFactor = 1e12; - - // Convert cost from float to integer bucket id. - static int cost_to_int(float cost) { - return (int)(cost * conv_factor_); - } - - // Simple fast random function used for randomizing item selection on pop. - static size_t fast_rand() { - seed_ = (0x234ab32a1 * seed_) ^ (0x12acbade); - return seed_; - } - - static void check_scaling(); - - // Expand the number of buckets. - // - // Only call if insufficient bucets exist. - static void expand(size_t required_number_of_buckets); - - static size_t seed_; /* Seed for fast_rand, should be non-zero */ - - static t_heap** heap_; /* Buckets for linked lists*/ - static size_t heap_size_; /* Number of buckets */ - static size_t heap_head_; /* First non-empty bucket */ - static size_t heap_tail_; /* Last non-empty bucket */ - static float conv_factor_; /* Cost bucket scaling factor */ - - static float min_cost_; /* Smallest cost seen */ - static float max_cost_; /* Large cost seen */ -}; - -inline bool is_empty_heap() { - return Bucket::empty(); -} - -inline void init_heap(const DeviceGrid& grid) { - Bucket::init(grid); -} - -inline void empty_heap() { - BucketItems::clear(); - Bucket::clear(); -} - -inline void add_to_heap(t_heap* hptr) { - Bucket::push(hptr); -} - -inline t_heap* get_heap_head() { - return Bucket::pop(); -} - -namespace heap_ { - -inline void push_back(t_heap* const hptr) { - add_to_heap(hptr); -} - -inline bool is_valid() { - return true; -} - -// extract every element and print it -inline void pop_heap() { - while (!is_empty_heap()) - VTR_LOG("%e ", get_heap_head()->cost); - VTR_LOG("\n"); -} - -inline void build_heap() { -} - -inline void verify_extract_top() { - Bucket::verify(); -} - -inline void print_heap() { - Bucket::print(); -} - -inline void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream) { - /* Puts an rr_node on the heap with the same condition as node_to_heap, - * but do not fix heap property yet as that is more efficiently done from - * bottom up with build_heap */ - - auto& route_ctx = g_vpr_ctx.routing(); - if (total_cost >= route_ctx.rr_node_route_inf[inode].path_cost) - return; - - t_heap* hptr = alloc_heap_data(); - hptr->index = inode; - hptr->cost = total_cost; - hptr->u.prev.node = prev_node; - hptr->u.prev.edge = prev_edge; - hptr->backward_path_cost = backward_path_cost; - hptr->R_upstream = R_upstream; - push_back(hptr); -} - -} // namespace heap_ - -#endif /* _BUCKET_ITEMS_H_ */ diff --git a/vpr/src/route/check_rr_graph.cpp b/vpr/src/route/check_rr_graph.cpp index 2c0e7c435a1..66609917624 100644 --- a/vpr/src/route/check_rr_graph.cpp +++ b/vpr/src/route/check_rr_graph.cpp @@ -177,8 +177,9 @@ void check_rr_graph(const t_graph_type graph_type, if (node.type() == IPIN || node.type() == OPIN) { if (has_adjacent_channel(node, device_ctx.grid)) { auto block_type = device_ctx.grid[node.xlow()][node.ylow()].type; - VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s has no fanin.\n", - inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string()); + std::string pin_name = block_type_pin_index_to_name(block_type, node.pin_num()); + VTR_LOG_ERROR("in check_rr_graph: node %d (%s) at (%d,%d) block=%s side=%s pin=%s has no fanin.\n", + inode, node.type_string(), node.xlow(), node.ylow(), block_type->name, node.side_string(), pin_name.c_str()); } } else { VTR_LOG_ERROR("in check_rr_graph: node %d (%s) has no fanin.\n", diff --git a/vpr/src/route/connection_box.cpp b/vpr/src/route/connection_box.cpp deleted file mode 100644 index efd8ab2bc95..00000000000 --- a/vpr/src/route/connection_box.cpp +++ /dev/null @@ -1,130 +0,0 @@ -#include "connection_box.h" -#include "vtr_assert.h" -#include "globals.h" - -ConnectionBoxes::ConnectionBoxes() - : size_(std::make_pair(0, 0)) { -} - -size_t ConnectionBoxes::num_connection_box_types() const { - return boxes_.size(); -} - -std::pair ConnectionBoxes::connection_box_grid_size() const { - return size_; -} - -const ConnectionBox* ConnectionBoxes::get_connection_box(ConnectionBoxId box) const { - if (!bool(box)) { - return nullptr; - } - - size_t index = size_t(box); - if (index >= boxes_.size()) { - return nullptr; - } - - return &boxes_.at(index); -} - -bool ConnectionBoxes::find_connection_box(int inode, - ConnectionBoxId* box_id, - std::pair* box_location, - float* site_pin_delay) const { - VTR_ASSERT(box_id != nullptr); - VTR_ASSERT(box_location != nullptr); - VTR_ASSERT(site_pin_delay != nullptr); - - const auto& conn_box_loc = ipin_map_[inode]; - if (conn_box_loc.box_id == ConnectionBoxId::INVALID()) { - return false; - } - - *box_id = conn_box_loc.box_id; - *box_location = conn_box_loc.box_location; - *site_pin_delay = conn_box_loc.site_pin_delay; - return true; -} - -// Clear IPIN map and set connection box grid size and box ids. -void ConnectionBoxes::reset_boxes(std::pair size, - const std::vector boxes) { - clear(); - - size_ = size; - boxes_ = boxes; -} - -void ConnectionBoxes::resize_nodes(size_t rr_node_size) { - ipin_map_.resize(rr_node_size); - canonical_loc_map_.resize(rr_node_size, - std::make_pair(-1, -1)); -} - -void ConnectionBoxes::clear() { - ipin_map_.clear(); - size_ = std::make_pair(0, 0); - boxes_.clear(); - canonical_loc_map_.clear(); - sink_to_ipin_.clear(); -} - -void ConnectionBoxes::add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location, float site_pin_delay) { - // Ensure that box location is in bounds - VTR_ASSERT(box_location.first < size_.first); - VTR_ASSERT(box_location.second < size_.second); - - // Bounds check box_id - VTR_ASSERT(bool(box_id)); - VTR_ASSERT(size_t(box_id) < boxes_.size()); - - // Make sure sink map will not be invalidated upon insertion. - VTR_ASSERT(sink_to_ipin_.size() == 0); - - ipin_map_[inode] = ConnBoxLoc(box_location, site_pin_delay, box_id); -} - -void ConnectionBoxes::add_canonical_loc(int inode, std::pair loc) { - VTR_ASSERT(loc.first < size_.first); - VTR_ASSERT(loc.second < size_.second); - canonical_loc_map_[inode] = loc; -} - -const std::pair* ConnectionBoxes::find_canonical_loc(int inode) const { - const auto& canon_loc = canonical_loc_map_[inode]; - if (canon_loc.first == size_t(-1)) { - return nullptr; - } - - return &canon_loc; -} - -void ConnectionBoxes::create_sink_back_ref() { - const auto& device_ctx = g_vpr_ctx.device(); - - sink_to_ipin_.resize(device_ctx.rr_nodes.size(), {{0, 0, 0, 0}, 0}); - - for (size_t i = 0; i < device_ctx.rr_nodes.size(); ++i) { - const auto& ipin_node = device_ctx.rr_nodes[i]; - if (ipin_node.type() != IPIN) { - continue; - } - - if (ipin_map_[i].box_id == ConnectionBoxId::INVALID()) { - continue; - } - - for (auto edge : ipin_node.edges()) { - int sink_inode = ipin_node.edge_sink_node(edge); - VTR_ASSERT(device_ctx.rr_nodes[sink_inode].type() == SINK); - VTR_ASSERT(sink_to_ipin_[sink_inode].ipin_count < 4); - auto& sink_to_ipin = sink_to_ipin_[sink_inode]; - sink_to_ipin.ipin_nodes[sink_to_ipin.ipin_count++] = i; - } - } -} - -const SinkToIpin& ConnectionBoxes::find_sink_connection_boxes( - int inode) const { - return sink_to_ipin_[inode]; -} diff --git a/vpr/src/route/connection_box.h b/vpr/src/route/connection_box.h deleted file mode 100644 index 1757c6c726b..00000000000 --- a/vpr/src/route/connection_box.h +++ /dev/null @@ -1,80 +0,0 @@ -#ifndef CONNECTION_BOX_H -#define CONNECTION_BOX_H -// Some routing graphs have connectivity driven by types of connection boxes. -// This class relates IPIN rr nodes with connection box type and locations, used -// for connection box driven map lookahead. - -#include -#include "vtr_strong_id.h" -#include "vtr_flat_map.h" -#include "vtr_range.h" -#include - -struct connection_box_tag {}; -typedef vtr::StrongId ConnectionBoxId; - -struct ConnectionBox { - std::string name; -}; - -struct ConnBoxLoc { - ConnBoxLoc() - : box_location(std::make_pair(-1, -1)) {} - ConnBoxLoc( - const std::pair& a_box_location, - float a_site_pin_delay, - ConnectionBoxId a_box_id) - : box_location(a_box_location) - , site_pin_delay(a_site_pin_delay) - , box_id(a_box_id) {} - - std::pair box_location; - float site_pin_delay; - ConnectionBoxId box_id; -}; - -struct SinkToIpin { - int ipin_nodes[4]; - int ipin_count; -}; - -class ConnectionBoxes { - public: - ConnectionBoxes(); - - size_t num_connection_box_types() const; - std::pair connection_box_grid_size() const; - const ConnectionBox* get_connection_box(ConnectionBoxId box) const; - - bool find_connection_box(int inode, - ConnectionBoxId* box_id, - std::pair* box_location, - float* site_pin_delay) const; - const std::pair* find_canonical_loc(int inode) const; - - // Clear IPIN map and set connection box grid size and box ids. - void clear(); - void reset_boxes(std::pair size, - const std::vector boxes); - void resize_nodes(size_t rr_node_size); - - void add_connection_box(int inode, ConnectionBoxId box_id, std::pair box_location, float site_pin_delay); - void add_canonical_loc(int inode, std::pair loc); - - // Create map from SINK's back to IPIN's - // - // This must be called after all connection boxes have been added. - void create_sink_back_ref(); - const SinkToIpin& find_sink_connection_boxes( - int inode) const; - - private: - std::pair size_; - std::vector boxes_; - std::vector ipin_map_; - std::vector sink_to_ipin_; - std::vector> - canonical_loc_map_; -}; - -#endif diff --git a/vpr/src/route/connection_box_lookahead_map.cpp b/vpr/src/route/connection_box_lookahead_map.cpp deleted file mode 100644 index f0328876019..00000000000 --- a/vpr/src/route/connection_box_lookahead_map.cpp +++ /dev/null @@ -1,1124 +0,0 @@ -#include "connection_box_lookahead_map.h" - -#include -#include - -#include "connection_box.h" -#include "rr_node.h" -#include "router_lookahead_map_utils.h" -#include "globals.h" -#include "vtr_math.h" -#include "vtr_time.h" -#include "vtr_geometry.h" -#include "echo_files.h" -#include "rr_graph.h" - -#include "route_timing.h" - -#ifdef VTR_ENABLE_CAPNPROTO -# include "capnp/serialize.h" -# include "connection_map.capnp.h" -# include "ndmatrix_serdes.h" -# include "mmap_file.h" -# include "serdes_utils.h" -#endif - -#if defined(VPR_USE_TBB) -# include -# include -#endif - -/* we're profiling routing cost over many tracks for each wire type, so we'll - * have many cost entries at each |dx|,|dy| offset. There are many ways to - * "boil down" the many costs at each offset to a single entry for a given - * (wire type, chan_type) combination we can take the smallest cost, the - * average, median, etc. This define selects the method we use. - * - * NOTE: Currently, only SMALLEST is supported. - * - * See e_representative_entry_method */ -#define REPRESENTATIVE_ENTRY_METHOD util::SMALLEST - -#define CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_MAPS - -// Sample based an NxN grid of starting segments, where N = SAMPLE_GRID_SIZE -static constexpr int SAMPLE_GRID_SIZE = 3; - -// Don't continue storing a path after hitting a lower-or-same cost entry. -static constexpr bool BREAK_ON_MISS = false; - -// Distance penalties filling are calculated based on available samples, but can be adjusted with this factor. -static constexpr float PENALTY_FACTOR = 1.f; -static constexpr float PENALTY_MIN = 1e-12f; - -static constexpr int MIN_PATH_COUNT = 1000; - -// quantiles (like percentiles but 0-1) of segment count to use as a selection criteria -// choose locations with higher, but not extreme, counts of each segment type -static constexpr double kSamplingCountLowerQuantile = 0.5; -static constexpr double kSamplingCountUpperQuantile = 0.7; - -// a sample point for a segment type, contains all segments at the VPR location -struct SamplePoint { - // canonical location - vtr::Point location; - - // nodes to expand - std::vector nodes; -}; - -struct SampleRegion { - // all nodes in `points' have this segment type - int segment_type; - - // location on the sample grid - vtr::Point grid_location; - - // locations to try - // The computation will keep expanding each of the points - // until a number of paths (segment -> connection box) are found. - std::vector points; - - // used to sort the regions to improve caching - uint64_t order; -}; - -template -static std::pair run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs); - -static std::vector find_sample_regions(int num_segments); - -// also known as the L1 norm -static int manhattan_distance(const vtr::Point& a, const vtr::Point& b) { - return abs(b.x() - a.x()) + abs(b.y() - a.y()); -} - -template -constexpr const T& clamp(const T& v, const T& lo, const T& hi) { - return std::min(std::max(v, lo), hi); -} - -template -static vtr::Point closest_point_in_rect(const vtr::Rect& r, const vtr::Point& p) { - if (r.empty()) { - return vtr::Point(0, 0); - } else { - return vtr::Point(clamp(p.x(), r.xmin(), r.xmax() - 1), - clamp(p.y(), r.ymin(), r.ymax() - 1)); - } -} - -// resize internal data structures -void CostMap::set_counts(size_t seg_count, size_t box_count) { - cost_map_.clear(); - offset_.clear(); - penalty_.clear(); - cost_map_.resize({seg_count, box_count}); - offset_.resize({seg_count, box_count}); - penalty_.resize({seg_count, box_count}); - seg_count_ = seg_count; - box_count_ = box_count; - - const auto& device_ctx = g_vpr_ctx.device(); - segment_map_.resize(device_ctx.rr_nodes.size()); - for (size_t i = 0; i < segment_map_.size(); ++i) { - auto& from_node = device_ctx.rr_nodes[i]; - - int from_cost_index = from_node.cost_index(); - int from_seg_index = device_ctx.rr_indexed_data[from_cost_index].seg_index; - - segment_map_[i] = from_seg_index; - } -} - -// cached node -> segment map -int CostMap::node_to_segment(int from_node_ind) const { - return segment_map_[from_node_ind]; -} - -static util::Cost_Entry penalize(const util::Cost_Entry& entry, int distance, float penalty) { - penalty = std::max(penalty, PENALTY_MIN); - return util::Cost_Entry(entry.delay + distance * penalty * PENALTY_FACTOR, - entry.congestion, entry.fill); -} - -// get a cost entry for a segment type, connection box type, and offset -util::Cost_Entry CostMap::find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const { - VTR_ASSERT(from_seg_index >= 0 && from_seg_index < (ssize_t)offset_.size()); - const auto& cost_map = cost_map_[from_seg_index][size_t(box_id)]; - if (cost_map.dim_size(0) == 0 || cost_map.dim_size(1) == 0) { - return util::Cost_Entry(); - } - - vtr::Point coord(delta_x - offset_[from_seg_index][size_t(box_id)].first, - delta_y - offset_[from_seg_index][size_t(box_id)].second); - vtr::Rect bounds(0, 0, cost_map.dim_size(0), cost_map.dim_size(1)); - auto closest = closest_point_in_rect(bounds, coord); - auto cost = cost_map_[from_seg_index][size_t(box_id)][closest.x()][closest.y()]; - float penalty = penalty_[from_seg_index][size_t(box_id)]; - auto distance = manhattan_distance(closest, coord); - return penalize(cost, distance, penalty); -} - -// set the cost map for a segment type and connection box type, filling holes -void CostMap::set_cost_map(const RoutingCosts& delay_costs, const RoutingCosts& base_costs) { - // calculate the bounding boxes - vtr::Matrix> bounds({seg_count_, box_count_}); - for (const auto& entry : delay_costs) { - bounds[entry.first.seg_index][size_t(entry.first.box_id)].expand_bounding_box(vtr::Rect(entry.first.delta)); - } - for (const auto& entry : base_costs) { - bounds[entry.first.seg_index][size_t(entry.first.box_id)].expand_bounding_box(vtr::Rect(entry.first.delta)); - } - - // store bounds - for (size_t seg = 0; seg < seg_count_; seg++) { - for (size_t box = 0; box < box_count_; box++) { - const auto& seg_box_bounds = bounds[seg][box]; - if (seg_box_bounds.empty()) { - // Didn't find any sample routes, so routing isn't possible between these segment/connection box types. - offset_[seg][box] = std::make_pair(0, 0); - cost_map_[seg][box] = vtr::NdMatrix( - {size_t(0), size_t(0)}); - continue; - } else { - offset_[seg][box] = std::make_pair(seg_box_bounds.xmin(), seg_box_bounds.ymin()); - cost_map_[seg][box] = vtr::NdMatrix( - {size_t(seg_box_bounds.width()), size_t(seg_box_bounds.height())}); - } - } - } - - // store entries into the matrices - for (const auto& entry : delay_costs) { - int seg = entry.first.seg_index; - int box = size_t(entry.first.box_id); - const auto& seg_box_bounds = bounds[seg][box]; - int x = entry.first.delta.x() - seg_box_bounds.xmin(); - int y = entry.first.delta.y() - seg_box_bounds.ymin(); - cost_map_[seg][box][x][y].delay = entry.second; - } - for (const auto& entry : base_costs) { - int seg = entry.first.seg_index; - int box = size_t(entry.first.box_id); - const auto& seg_box_bounds = bounds[seg][box]; - int x = entry.first.delta.x() - seg_box_bounds.xmin(); - int y = entry.first.delta.y() - seg_box_bounds.ymin(); - cost_map_[seg][box][x][y].congestion = entry.second; - } - - // fill the holes - for (size_t seg = 0; seg < seg_count_; seg++) { - for (size_t box = 0; box < box_count_; box++) { - penalty_[seg][box] = std::numeric_limits::infinity(); - const auto& seg_box_bounds = bounds[seg][box]; - if (seg_box_bounds.empty()) { - continue; - } - auto& matrix = cost_map_[seg][box]; - - // calculate delay penalty - float min_delay = std::numeric_limits::infinity(), max_delay = 0.f; - vtr::Point min_location(0, 0), max_location(0, 0); - for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { - for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - util::Cost_Entry& cost_entry = matrix[ix][iy]; - if (cost_entry.valid()) { - if (cost_entry.delay < min_delay) { - min_delay = cost_entry.delay; - min_location = vtr::Point(ix, iy); - } - if (cost_entry.delay > max_delay) { - max_delay = cost_entry.delay; - max_location = vtr::Point(ix, iy); - } - } - } - } - float delay_penalty = (max_delay - min_delay) / static_cast(std::max(1, manhattan_distance(max_location, min_location))); - penalty_[seg][box] = delay_penalty; - - // find missing cost entries and fill them in by copying a nearby cost entry - std::vector> missing; - bool couldnt_fill = false; - auto shifted_bounds = vtr::Rect(0, 0, seg_box_bounds.width(), seg_box_bounds.height()); - int max_fill = 0; - for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { - for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - util::Cost_Entry& cost_entry = matrix[ix][iy]; - if (!cost_entry.valid()) { - // maximum search radius - util::Cost_Entry filler; - int distance; - std::tie(filler, distance) = get_nearby_cost_entry(matrix, ix, iy, shifted_bounds); - if (filler.valid()) { - missing.push_back(std::make_tuple(ix, iy, penalize(filler, distance, delay_penalty))); - max_fill = std::max(max_fill, distance); - } else { - couldnt_fill = true; - } - } - } - if (couldnt_fill) { - // give up trying to fill an empty matrix - break; - } - } - - if (!couldnt_fill) { - VTR_LOG("At %d -> %d: max_fill = %d, delay_penalty = %e\n", seg, box, max_fill, delay_penalty); - } - - // write back the missing entries - for (auto& xy_entry : missing) { - matrix[std::get<0>(xy_entry)][std::get<1>(xy_entry)] = std::get<2>(xy_entry); - } - - if (couldnt_fill) { - VTR_LOG_WARN("Couldn't fill holes in the cost matrix for %d -> %ld, %d x %d bounding box\n", - seg, box, seg_box_bounds.width(), seg_box_bounds.height()); - for (unsigned y = 0; y < matrix.dim_size(1); y++) { - for (unsigned x = 0; x < matrix.dim_size(0); x++) { - VTR_ASSERT(!matrix[x][y].valid()); - } - } - } - } - } -} - -// prints an ASCII diagram of each cost map for a segment type (debug) -// o => above average -// . => at or below average -// * => invalid (missing) -void CostMap::print(int iseg) const { - const auto& device_ctx = g_vpr_ctx.device(); - for (size_t box_id = 0; - box_id < device_ctx.connection_boxes.num_connection_box_types(); - box_id++) { - auto& matrix = cost_map_[iseg][box_id]; - if (matrix.dim_size(0) == 0 || matrix.dim_size(1) == 0) { - VTR_LOG("cost EMPTY for box_id = %lu\n", box_id); - continue; - } - VTR_LOG("cost for box_id = %lu (%zu, %zu)\n", box_id, matrix.dim_size(0), matrix.dim_size(1)); - double sum = 0.0; - for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { - const auto& entry = matrix[ix][iy]; - if (entry.valid()) { - sum += entry.delay; - } - } - } - double avg = sum / ((double)matrix.dim_size(0) * (double)matrix.dim_size(1)); - for (unsigned iy = 0; iy < matrix.dim_size(1); iy++) { - for (unsigned ix = 0; ix < matrix.dim_size(0); ix++) { - const auto& entry = matrix[ix][iy]; - if (!entry.valid()) { - VTR_LOG("*"); - } else if (entry.delay * 4 > avg * 5) { - VTR_LOG("O"); - } else if (entry.delay > avg) { - VTR_LOG("o"); - } else if (entry.delay * 4 > avg * 3) { - VTR_LOG("."); - } else { - VTR_LOG(" "); - } - } - VTR_LOG("\n"); - } - } -} - -// list segment type and connection box type pairs that have empty cost maps (debug) -std::vector> CostMap::list_empty() const { - std::vector> results; - for (int iseg = 0; iseg < (int)cost_map_.dim_size(0); iseg++) { - for (int box_id = 0; box_id < (int)cost_map_.dim_size(1); box_id++) { - auto& matrix = cost_map_[iseg][box_id]; - if (matrix.dim_size(0) == 0 || matrix.dim_size(1) == 0) results.push_back(std::make_pair(iseg, box_id)); - } - } - return results; -} - -static void assign_min_entry(util::Cost_Entry* dst, const util::Cost_Entry& src) { - if (src.delay < dst->delay) { - dst->delay = src.delay; - } - if (src.congestion < dst->congestion) { - dst->congestion = src.congestion; - } -} - -// find the minimum cost entry from the nearest manhattan distance neighbor -std::pair CostMap::get_nearby_cost_entry(const vtr::NdMatrix& matrix, - int cx, - int cy, - const vtr::Rect& bounds) { - // spiral around (cx, cy) looking for a nearby entry - bool in_bounds = bounds.contains(vtr::Point(cx, cy)); - if (!in_bounds) { - return std::make_pair(util::Cost_Entry(), 0); - } - int n = 0; - util::Cost_Entry fill(matrix[cx][cy]); - fill.fill = true; - - while (in_bounds && !fill.valid()) { - n++; - in_bounds = false; - util::Cost_Entry min_entry; - for (int ox = -n; ox <= n; ox++) { - int x = cx + ox; - int oy = n - abs(ox); - int yp = cy + oy; - int yn = cy - oy; - if (bounds.contains(vtr::Point(x, yp))) { - assign_min_entry(&min_entry, matrix[x][yp]); - in_bounds = true; - } - if (bounds.contains(vtr::Point(x, yn))) { - assign_min_entry(&min_entry, matrix[x][yn]); - in_bounds = true; - } - } - if (!std::isfinite(fill.delay)) { - fill.delay = min_entry.delay; - } - if (!std::isfinite(fill.congestion)) { - fill.congestion = min_entry.congestion; - } - } - return std::make_pair(fill, n); -} - -// derive a cost from the map between two nodes -float ConnectionBoxMapLookahead::get_map_cost(int from_node_ind, - int to_node_ind, - float criticality_fac) const { - if (from_node_ind == to_node_ind) { - return 0.f; - } - - auto& device_ctx = g_vpr_ctx.device(); - - auto to_node_type = device_ctx.rr_nodes[to_node_ind].type(); - - if (to_node_type == SINK) { - const auto& sink_to_ipin = device_ctx.connection_boxes.find_sink_connection_boxes(to_node_ind); - float cost = std::numeric_limits::infinity(); - - // Find cheapest cost from from_node_ind to IPINs for this SINK. - for (int i = 0; i < sink_to_ipin.ipin_count; ++i) { - cost = std::min(cost, - get_map_cost( - from_node_ind, - sink_to_ipin.ipin_nodes[i], criticality_fac)); - if (cost <= 0.f) break; - } - - return cost; - } - - if (device_ctx.rr_nodes[to_node_ind].type() != IPIN) { - VPR_THROW(VPR_ERROR_ROUTE, "Not an IPIN/SINK, is %d", to_node_ind); - } - ConnectionBoxId box_id; - std::pair box_location; - float site_pin_delay; - bool found = device_ctx.connection_boxes.find_connection_box( - to_node_ind, &box_id, &box_location, &site_pin_delay); - if (!found) { - VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", to_node_ind); - } - - const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(from_node_ind); - if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical loc for %d (to %d)", - from_node_ind, to_node_ind); - } - - ssize_t dx = ssize_t(from_canonical_loc->first) - ssize_t(box_location.first); - ssize_t dy = ssize_t(from_canonical_loc->second) - ssize_t(box_location.second); - - int from_seg_index = cost_map_.node_to_segment(from_node_ind); - util::Cost_Entry cost_entry = cost_map_.find_cost(from_seg_index, box_id, dx, dy); - - if (!cost_entry.valid()) { - // there is no route - VTR_LOGV_DEBUG(f_router_debug, - "Not connected %d (%s, %d) -> %d (%s, %d, (%d, %d))\n", - from_node_ind, device_ctx.rr_nodes[from_node_ind].type_string(), from_seg_index, - to_node_ind, device_ctx.rr_nodes[to_node_ind].type_string(), - (int)size_t(box_id), (int)box_location.first, (int)box_location.second); - return std::numeric_limits::infinity(); - } - - float expected_delay = cost_entry.delay; - float expected_congestion = cost_entry.congestion; - - expected_delay += site_pin_delay; - - float expected_cost = criticality_fac * expected_delay + (1.0 - criticality_fac) * expected_congestion; - - VTR_LOGV_DEBUG(f_router_debug, "Requested lookahead from node %d to %d\n", from_node_ind, to_node_ind); - const std::string& segment_name = device_ctx.segment_inf[from_seg_index].name; - const std::string& box_name = device_ctx.connection_boxes.get_connection_box(box_id)->name; - VTR_LOGV_DEBUG(f_router_debug, "Lookahead returned %s (%d) to %s (%zu) with distance (%zd, %zd)\n", - segment_name.c_str(), from_seg_index, - box_name.c_str(), - size_t(box_id), - dx, dy); - VTR_LOGV_DEBUG(f_router_debug, "Lookahead delay: %g\n", expected_delay); - VTR_LOGV_DEBUG(f_router_debug, "Lookahead congestion: %g\n", expected_congestion); - VTR_LOGV_DEBUG(f_router_debug, "Criticality: %g\n", criticality_fac); - VTR_LOGV_DEBUG(f_router_debug, "Lookahead cost: %g\n", expected_cost); - VTR_LOGV_DEBUG(f_router_debug, "Site pin delay: %g\n", site_pin_delay); - - if (!std::isfinite(expected_cost) || expected_cost < 0.f) { - VTR_LOG_ERROR("invalid cost for segment %d to connection box %d at (%d, %d)\n", from_seg_index, (int)size_t(box_id), (int)dx, (int)dy); - VTR_ASSERT(0); - } - - return expected_cost; -} - -// add a best cost routing path from start_node_ind to node_ind to routing costs -template -static bool add_paths(int start_node_ind, - Entry current, - std::unordered_map* paths, - RoutingCosts* routing_costs) { - auto& device_ctx = g_vpr_ctx.device(); - ConnectionBoxId box_id; - std::pair box_location; - float site_pin_delay; - int node_ind = current.rr_node_ind; - bool found = device_ctx.connection_boxes.find_connection_box( - node_ind, &box_id, &box_location, &site_pin_delay); - bool new_sample_found = false; - if (!found) { - VPR_THROW(VPR_ERROR_ROUTE, "No connection box for IPIN %d", node_ind); - } - - // reconstruct the path - std::vector path; - for (int i = (*paths)[node_ind].parent; i != start_node_ind; i = (*paths)[i].parent) { - path.push_back(i); - } - path.push_back(start_node_ind); - - current.adjust_Tsw(-site_pin_delay); - - // add each node along the path subtracting the incremental costs from the current costs - Entry start_to_here(start_node_ind, UNDEFINED, nullptr); - int parent = start_node_ind; - for (auto it = path.rbegin(); it != path.rend(); it++) { - auto& here = device_ctx.rr_nodes[*it]; - int seg_index = device_ctx.rr_indexed_data[here.cost_index()].seg_index; - const std::pair* from_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(*it); - if (from_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", *it); - } - - vtr::Point delta(ssize_t(from_canonical_loc->first) - ssize_t(box_location.first), - ssize_t(from_canonical_loc->second) - ssize_t(box_location.second)); - RoutingCostKey key = { - seg_index, - box_id, - delta}; - - if (*it != start_node_ind) { - auto& parent_node = device_ctx.rr_nodes[parent]; - start_to_here = Entry(*it, parent_node.edge_switch((*paths)[*it].edge), &start_to_here); - parent = *it; - } - - float cost = current.cost() - start_to_here.cost(); - if (cost < 0.f && cost > -10e-15 /* 10 femtosecond */) { - cost = 0.f; - } - - VTR_ASSERT(cost >= 0.f); - - // NOTE: implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - auto result = routing_costs->insert(std::make_pair(key, cost)); - if (!result.second) { - if (cost < result.first->second) { - result.first->second = cost; - new_sample_found = true; - } else if (BREAK_ON_MISS) { - break; - } - } else { - new_sample_found = true; - } - } - return new_sample_found; -} - -/* Runs Dijkstra's algorithm from specified node until all nodes have been - * visited. Each time a pin is visited, the delay/congestion information - * to that pin is stored to an entry in the routing_cost_map. - * - * Returns the maximum (last) minimum cost path stored, and - * the number of paths from start_node_ind stored. */ -template -static std::pair run_dijkstra(int start_node_ind, - RoutingCosts* routing_costs) { - auto& device_ctx = g_vpr_ctx.device(); - int path_count = 0; - const std::pair* start_canonical_loc = device_ctx.connection_boxes.find_canonical_loc(start_node_ind); - if (start_canonical_loc == nullptr) { - VPR_THROW(VPR_ERROR_ROUTE, "No canonical location of node %d", - start_node_ind); - } - - /* a list of boolean flags (one for each rr node) to figure out if a - * certain node has already been expanded */ - std::vector node_expanded(device_ctx.rr_nodes.size(), false); - /* For each node keep a list of the cost with which that node has been - * visited (used to determine whether to push a candidate node onto the - * expansion queue. - * Also store the parent node so we can reconstruct a specific path. */ - std::unordered_map paths; - /* a priority queue for expansion */ - std::priority_queue, std::greater> pq; - - /* first entry has no upstream delay or congestion */ - Entry first_entry(start_node_ind, UNDEFINED, nullptr); - float max_cost = first_entry.cost(); - - pq.push(first_entry); - - /* now do routing */ - while (!pq.empty()) { - auto current = pq.top(); - pq.pop(); - - int node_ind = current.rr_node_ind; - - /* check that we haven't already expanded from this node */ - if (node_expanded[node_ind]) { - continue; - } - - /* if this node is an ipin record its congestion/delay in the routing_cost_map */ - if (device_ctx.rr_nodes[node_ind].type() == IPIN) { - // the last cost should be the highest - max_cost = current.cost(); - - path_count++; - add_paths(start_node_ind, current, &paths, routing_costs); - } else { - util::expand_dijkstra_neighbours(device_ctx.rr_nodes, - current, paths, node_expanded, pq); - node_expanded[node_ind] = true; - } - } - return std::make_pair(max_cost, path_count); -} - -// compute the cost maps for lookahead -void ConnectionBoxMapLookahead::compute(const std::vector& segment_inf) { - vtr::ScopedStartFinishTimer timer("Computing connection box lookahead map"); - - // Initialize rr_node_route_inf if not already - alloc_and_load_rr_node_route_structs(); - - size_t num_segments = segment_inf.size(); - std::vector sample_regions = find_sample_regions(num_segments); - - /* free previous delay map and allocate new one */ - auto& device_ctx = g_vpr_ctx.device(); - cost_map_.set_counts(segment_inf.size(), - device_ctx.connection_boxes.num_connection_box_types()); - - VTR_ASSERT(REPRESENTATIVE_ENTRY_METHOD == util::SMALLEST); - RoutingCosts all_delay_costs; - RoutingCosts all_base_costs; - - /* run Dijkstra's algorithm for each segment type & channel type combination */ -#if defined(VPR_USE_TBB) - tbb::mutex all_costs_mutex; - tbb::parallel_for_each(sample_regions, [&](const SampleRegion& region) { -#else - for (const auto& region : sample_regions) { -#endif - // holds the cost entries for a run - RoutingCosts delay_costs; - RoutingCosts base_costs; - int total_path_count = 0; - - for (auto& point : region.points) { - // statistics - vtr::Timer run_timer; - float max_delay_cost = 0.f; - float max_base_cost = 0.f; - int path_count = 0; - for (auto node_ind : point.nodes) { - { - auto result = run_dijkstra(node_ind, &delay_costs); - max_delay_cost = std::max(max_delay_cost, result.first); - path_count += result.second; - } - { - auto result = run_dijkstra(node_ind, &base_costs); - max_base_cost = std::max(max_base_cost, result.first); - path_count += result.second; - } - } - - if (path_count > 0) { - VTR_LOG("Expanded %d paths of segment type %s(%d) starting at (%d, %d) from %d segments, max_cost %e %e (%g paths/sec)\n", - path_count, segment_inf[region.segment_type].name.c_str(), region.segment_type, - point.location.x(), point.location.y(), - (int)point.nodes.size(), - max_delay_cost, max_base_cost, - path_count / run_timer.elapsed_sec()); - } - - /* - * if (path_count == 0) { - * for (auto node_ind : point.nodes) { - * VTR_LOG("Expanded node %s\n", describe_rr_node(node_ind).c_str()); - * } - * } - */ - - total_path_count += path_count; - if (total_path_count > MIN_PATH_COUNT) { - break; - } - } - -#if defined(VPR_USE_TBB) - all_costs_mutex.lock(); -#endif - - if (total_path_count == 0) { - VTR_LOG_WARN("No paths found for sample region %s(%d, %d)\n", - segment_inf[region.segment_type].name.c_str(), region.grid_location.x(), region.grid_location.y()); - } - - // combine the cost map from this run with the final cost maps for each segment - for (const auto& cost : delay_costs) { - const auto& val = cost.second; - auto result = all_delay_costs.insert(std::make_pair(cost.first, val)); - if (!result.second) { - // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - result.first->second = std::min(result.first->second, val); - } - } - for (const auto& cost : base_costs) { - const auto& val = cost.second; - auto result = all_base_costs.insert(std::make_pair(cost.first, val)); - if (!result.second) { - // implements REPRESENTATIVE_ENTRY_METHOD == SMALLEST - result.first->second = std::min(result.first->second, val); - } - } - -#if defined(VPR_USE_TBB) - all_costs_mutex.unlock(); - }); -#else - } -#endif - - VTR_LOG("Combining results\n"); - /* boil down the cost list in routing_cost_map at each coordinate to a - * representative cost entry and store it in the lookahead cost map */ - cost_map_.set_cost_map(all_delay_costs, all_base_costs); - -// diagnostics -#if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_ENTRIES) - for (auto& cost : all_costs) { - const auto& key = cost.first; - const auto& val = cost.second; - VTR_LOG("%d -> %d (%d, %d): %g, %g\n", - val.from_node, val.to_node, - key.delta.x(), key.delta.y(), - val.cost_entry.delay, val.cost_entry.congestion); - } -#endif - -#if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_COST_MAPS) - for (int iseg = 0; iseg < (ssize_t)num_segments; iseg++) { - VTR_LOG("cost map for %s(%d)\n", - segment_inf[iseg].name.c_str(), iseg); - cost_map_.print(iseg); - } -#endif - -#if defined(CONNECTION_BOX_LOOKAHEAD_MAP_PRINT_EMPTY_MAPS) - for (std::pair p : cost_map_.list_empty()) { - int iseg, box_id; - std::tie(iseg, box_id) = p; - VTR_LOG("cost map for %s(%d), connection box %d EMPTY\n", - segment_inf[iseg].name.c_str(), iseg, box_id); - } -#endif -} - -// get an expected minimum cost for routing from the current node to the target node -float ConnectionBoxMapLookahead::get_expected_cost( - int current_node, - int target_node, - const t_conn_cost_params& params, - float /*R_upstream*/) const { - auto& device_ctx = g_vpr_ctx.device(); - - t_rr_type rr_type = device_ctx.rr_nodes[current_node].type(); - - if (rr_type == CHANX || rr_type == CHANY) { - return get_map_cost( - current_node, target_node, params.criticality); - } else if (rr_type == IPIN) { /* Change if you're allowing route-throughs */ - return (device_ctx.rr_indexed_data[SINK_COST_INDEX].base_cost); - } else { /* Change this if you want to investigate route-throughs */ - return (0.); - } -} - -// the smallest bounding box containing a node -static vtr::Rect bounding_box_for_node(const ConnectionBoxes& connection_boxes, int node_ind) { - const std::pair* loc = connection_boxes.find_canonical_loc(node_ind); - if (loc == nullptr) { - return vtr::Rect(); - } else { - return vtr::Rect(vtr::Point(loc->first, loc->second)); - } -} - -static vtr::Rect sample_window(const vtr::Rect& bounding_box, int sx, int sy, int n) { - return vtr::Rect(sample(bounding_box, sx, sy, n), - sample(bounding_box, sx + 1, sy + 1, n)); -} - -static std::vector choose_points(const vtr::Matrix& counts, - const vtr::Rect& window, - int min_count, - int max_count) { - VTR_ASSERT(min_count <= max_count); - std::vector points; - for (int y = window.ymin(); y < window.ymax(); y++) { - for (int x = window.xmin(); x < window.xmax(); x++) { - if (counts[x][y] >= min_count && counts[x][y] <= max_count) { - points.push_back(SamplePoint{/* .location = */ vtr::Point(x, y), - /* .nodes = */ {}}); - } - } - } - - vtr::Point center = sample(window, 1, 1, 2); - - // sort by distance from center - std::sort(points.begin(), points.end(), - [&](const SamplePoint& a, const SamplePoint& b) { - return manhattan_distance(a.location, center) < manhattan_distance(b.location, center); - }); - - return points; -} - -// histogram is a map from segment count to number of locations having that count -static int quantile(const std::map& histogram, float ratio) { - if (histogram.empty()) { - return 0; - } - int sum = 0; - for (const auto& entry : histogram) { - sum += entry.second; - } - int limit = std::ceil(sum * ratio); - for (const auto& entry : histogram) { - limit -= entry.second; - if (limit <= 0) { - return entry.first; - } - } - return 0; -} - -// select a good number of segments to find -static std::map count_histogram(const vtr::Rect& box, const vtr::Matrix& counts) { - std::map histogram; - for (int y = box.ymin(); y < box.ymax(); y++) { - for (int x = box.xmin(); x < box.xmax(); x++) { - int count = counts[x][y]; - if (count > 0) { - ++histogram[count]; - } - } - } - return histogram; -} - -// Used to calculate each region's `order.' -// A space-filling curve will order the regions so that -// nearby points stay close in order. A Hilbert curve might -// be better, but a Morton (Z)-order curve is easy to compute, -// because it's just interleaving binary bits, so this -// function interleaves with 0's so that the X and Y -// dimensions can then be OR'ed together. -static uint64_t interleave(uint32_t x) { - uint64_t i = x; - i = (i ^ (i << 16)) & 0x0000ffff0000ffff; - i = (i ^ (i << 8)) & 0x00ff00ff00ff00ff; - i = (i ^ (i << 4)) & 0x0f0f0f0f0f0f0f0f; - i = (i ^ (i << 2)) & 0x3333333333333333; - i = (i ^ (i << 1)) & 0x5555555555555555; - return i; -} - -// for each segment type, find the nearest nodes to an equally spaced grid of points -// within the bounding box for that segment type -static std::vector find_sample_regions(int num_segments) { - vtr::ScopedStartFinishTimer timer("finding sample regions"); - std::vector sample_regions; - auto& device_ctx = g_vpr_ctx.device(); - auto& rr_nodes = device_ctx.rr_nodes; - std::vector> segment_counts(num_segments); - - // compute bounding boxes for each segment type - std::vector> bounding_box_for_segment(num_segments, vtr::Rect()); - for (size_t i = 0; i < rr_nodes.size(); i++) { - auto& node = rr_nodes[i]; - if (node.type() != CHANX && node.type() != CHANY) continue; - if (node.capacity() == 0 || node.num_edges() == 0) continue; - int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; - - VTR_ASSERT(seg_index != OPEN); - VTR_ASSERT(seg_index < num_segments); - - bounding_box_for_segment[seg_index].expand_bounding_box(bounding_box_for_node(device_ctx.connection_boxes, i)); - } - - // initialize counts - for (int seg = 0; seg < num_segments; seg++) { - const auto& box = bounding_box_for_segment[seg]; - segment_counts[seg] = vtr::Matrix({size_t(box.width()), size_t(box.height())}, 0); - } - - // count sample points - for (size_t i = 0; i < rr_nodes.size(); i++) { - auto& node = rr_nodes[i]; - if (node.type() != CHANX && node.type() != CHANY) continue; - if (node.capacity() == 0 || node.num_edges() == 0) continue; - const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(i); - if (loc == nullptr) continue; - - int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; - segment_counts[seg_index][loc->first][loc->second] += 1; - - VTR_ASSERT(seg_index != OPEN); - VTR_ASSERT(seg_index < num_segments); - } - - // select sample points - for (int i = 0; i < num_segments; i++) { - const auto& counts = segment_counts[i]; - const auto& bounding_box = bounding_box_for_segment[i]; - if (bounding_box.empty()) continue; - for (int y = 0; y < SAMPLE_GRID_SIZE; y++) { - for (int x = 0; x < SAMPLE_GRID_SIZE; x++) { - vtr::Rect window = sample_window(bounding_box, x, y, SAMPLE_GRID_SIZE); - auto histogram = count_histogram(window, segment_counts[i]); - SampleRegion region = { - /* .segment_type = */ i, - /* .grid_location = */ vtr::Point(x, y), - /* .points = */ choose_points(counts, window, quantile(histogram, kSamplingCountLowerQuantile), quantile(histogram, kSamplingCountUpperQuantile)), - /* .order = */ 0}; - if (!region.points.empty()) { - /* In order to improve caching, the list of sample points are - * sorted to keep points that are nearby on the Euclidean plane also - * nearby in the vector of sample points. - * - * This means subsequent expansions on the same thread are likely - * to cover a similar set of nodes, so they are more likely to be - * cached. This improves performance by about 7%, which isn't a lot, - * but not a bad improvement for a few lines of code. */ - vtr::Point location = region.points[0].location; - - // interleave bits of X and Y for a Z-curve ordering. - region.order = interleave(location.x()) | (interleave(location.y()) << 1); - - sample_regions.push_back(region); - } - } - } - } - - // sort regions - std::sort(sample_regions.begin(), sample_regions.end(), - [](const SampleRegion& a, const SampleRegion& b) { - return a.order < b.order; - }); - - // build an index of sample points on segment type and location - std::map, SamplePoint*> sample_point_index; - for (auto& region : sample_regions) { - for (auto& point : region.points) { - sample_point_index[std::make_tuple(region.segment_type, point.location.x(), point.location.y())] = &point; - } - } - - // collect the node indices for each segment type at the selected sample points - for (size_t i = 0; i < rr_nodes.size(); i++) { - auto& node = rr_nodes[i]; - if (node.type() != CHANX && node.type() != CHANY) continue; - if (node.capacity() == 0 || node.num_edges() == 0) continue; - const std::pair* loc = device_ctx.connection_boxes.find_canonical_loc(i); - if (loc == nullptr) continue; - - int seg_index = device_ctx.rr_indexed_data[node.cost_index()].seg_index; - - VTR_ASSERT(seg_index != OPEN); - VTR_ASSERT(seg_index < num_segments); - - auto point = sample_point_index.find(std::make_tuple(seg_index, loc->first, loc->second)); - if (point != sample_point_index.end()) { - point->second->nodes.push_back(i); - } - } - - return sample_regions; -} - -#ifndef VTR_ENABLE_CAPNPROTO - -void ConnectionBoxMapLookahead::read(const std::string& file) { - VPR_THROW(VPR_ERROR_ROUTE, "ConnectionBoxMapLookahead::read not implemented"); -} -void ConnectionBoxMapLookahead::write(const std::string& file) const { - VPR_THROW(VPR_ERROR_ROUTE, "ConnectionBoxMapLookahead::write not implemented"); -} - -#else - -void ConnectionBoxMapLookahead::read(const std::string& file) { - cost_map_.read(file); -} -void ConnectionBoxMapLookahead::write(const std::string& file) const { - cost_map_.write(file); -} - -static void ToCostEntry(util::Cost_Entry* out, const VprCostEntry::Reader& in) { - out->delay = in.getDelay(); - out->congestion = in.getCongestion(); - out->fill = in.getFill(); -} - -static void FromCostEntry(VprCostEntry::Builder* out, const util::Cost_Entry& in) { - out->setDelay(in.delay); - out->setCongestion(in.congestion); - out->setFill(in.fill); -} - -static void ToVprVector2D(std::pair* out, const VprVector2D::Reader& in) { - *out = std::make_pair(in.getX(), in.getY()); -} - -static void FromVprVector2D(VprVector2D::Builder* out, const std::pair& in) { - out->setX(in.first); - out->setY(in.second); -} - -static void ToMatrixCostEntry(vtr::NdMatrix* out, - const Matrix::Reader& in) { - ToNdMatrix<2, VprCostEntry, util::Cost_Entry>(out, in, ToCostEntry); -} - -static void FromMatrixCostEntry( - Matrix::Builder* out, - const vtr::NdMatrix& in) { - FromNdMatrix<2, VprCostEntry, util::Cost_Entry>( - out, in, FromCostEntry); -} - -static void ToFloat(float* out, const VprFloatEntry::Reader& in) { - // Getting a scalar field is always "get()". - *out = in.getValue(); -} - -static void FromFloat(VprFloatEntry::Builder* out, const float& in) { - // Setting a scalar field is always "set(value)". - out->setValue(in); -} - -void CostMap::read(const std::string& file) { - MmapFile f(file); - - /* Increase reader limit to 1G words. */ - ::capnp::ReaderOptions opts = ::capnp::ReaderOptions(); - opts.traversalLimitInWords = 1024 * 1024 * 1024; - ::capnp::FlatArrayMessageReader reader(f.getData(), opts); - - auto cost_map = reader.getRoot(); - - { - const auto& segment_map = cost_map.getSegmentMap(); - segment_map_.resize(segment_map.size()); - auto dst_iter = segment_map_.begin(); - for (const auto& src : segment_map) { - *dst_iter++ = src; - } - } - - { - const auto& offset = cost_map.getOffset(); - ToNdMatrix<2, VprVector2D, std::pair>( - &offset_, offset, ToVprVector2D); - } - - { - const auto& cost_maps = cost_map.getCostMap(); - ToNdMatrix<2, Matrix, vtr::NdMatrix>( - &cost_map_, cost_maps, ToMatrixCostEntry); - } - - { - const auto& penalty = cost_map.getPenalty(); - ToNdMatrix<2, VprFloatEntry, float>( - &penalty_, penalty, ToFloat); - } -} - -void CostMap::write(const std::string& file) const { - ::capnp::MallocMessageBuilder builder; - - auto cost_map = builder.initRoot(); - - { - auto segment_map = cost_map.initSegmentMap(segment_map_.size()); - for (size_t i = 0; i < segment_map_.size(); ++i) { - segment_map.set(i, segment_map_[i]); - } - } - - { - auto offset = cost_map.initOffset(); - FromNdMatrix<2, VprVector2D, std::pair>( - &offset, offset_, FromVprVector2D); - } - - { - auto cost_maps = cost_map.initCostMap(); - FromNdMatrix<2, Matrix, vtr::NdMatrix>( - &cost_maps, cost_map_, FromMatrixCostEntry); - } - - { - auto penalty = cost_map.initPenalty(); - FromNdMatrix<2, VprFloatEntry, float>( - &penalty, penalty_, FromFloat); - } - - writeMessageToFile(file, &builder); -} -#endif diff --git a/vpr/src/route/connection_box_lookahead_map.h b/vpr/src/route/connection_box_lookahead_map.h deleted file mode 100644 index 70423409f7a..00000000000 --- a/vpr/src/route/connection_box_lookahead_map.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef CONNECTION_BOX_LOOKAHEAD_H_ -#define CONNECTION_BOX_LOOKAHEAD_H_ - -#include -#include "physical_types.h" -#include "router_lookahead.h" -#include "router_lookahead_map_utils.h" -#include "connection_box.h" -#include "vtr_geometry.h" - -// Keys in the RoutingCosts map -struct RoutingCostKey { - // segment type index - int seg_index; - - // type of the destination connection box - ConnectionBoxId box_id; - - // offset of the destination connection box from the starting segment - vtr::Point delta; - - RoutingCostKey() - : seg_index(-1) - , delta(0, 0) {} - RoutingCostKey(int seg_index_arg, ConnectionBoxId box_id_arg, vtr::Point delta_arg) - : seg_index(seg_index_arg) - , box_id(box_id_arg) - , delta(delta_arg) {} - - bool operator==(const RoutingCostKey& other) const { - return seg_index == other.seg_index && box_id == other.box_id && delta == other.delta; - } -}; - -// hash implementation for RoutingCostKey -struct HashRoutingCostKey { - std::size_t operator()(RoutingCostKey const& key) const noexcept { - std::size_t hash = std::hash{}(key.seg_index); - vtr::hash_combine(hash, key.box_id); - vtr::hash_combine(hash, key.delta.x()); - vtr::hash_combine(hash, key.delta.y()); - return hash; - } -}; - -// Map used to store intermediate routing costs -typedef std::unordered_map RoutingCosts; - -// Dense cost maps per source segment and destination connection box types -class CostMap { - public: - void set_counts(size_t seg_count, size_t box_count); - int node_to_segment(int from_node_ind) const; - util::Cost_Entry find_cost(int from_seg_index, ConnectionBoxId box_id, int delta_x, int delta_y) const; - void set_cost_map(const RoutingCosts& delay_costs, const RoutingCosts& base_costs); - std::pair get_nearby_cost_entry(const vtr::NdMatrix& matrix, int cx, int cy, const vtr::Rect& bounds); - void read(const std::string& file); - void write(const std::string& file) const; - void print(int iseg) const; - std::vector> list_empty() const; - - private: - vtr::Matrix> cost_map_; - vtr::Matrix> offset_; - vtr::Matrix penalty_; - std::vector segment_map_; - size_t seg_count_; - size_t box_count_; -}; - -// Implementation of RouterLookahead based on source segment and destination connection box types -class ConnectionBoxMapLookahead : public RouterLookahead { - public: - float get_expected_cost(int node, int target_node, const t_conn_cost_params& params, float R_upstream) const override; - float get_map_cost(int from_node_ind, int to_node_ind, float criticality_fac) const; - void compute(const std::vector& segment_inf) override; - - void read(const std::string& file) override; - void write(const std::string& file) const override; - - CostMap cost_map_; -}; - -#endif diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index c6dd9449a4e..6204dad984b 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -44,12 +44,22 @@ struct t_trace_branch { /**************** Static variables local to route_common.c ******************/ +static t_heap** heap; /* Indexed from [1..heap_size] */ +static int heap_size; /* Number of slots in the heap array */ +static int heap_tail; /* Index of first unused slot in the heap array */ + +/* For managing my own list of currently free heap data structures. */ +static t_heap* heap_free_head = nullptr; +/* For keeping track of the sudo malloc memory for the heap*/ +static vtr::t_chunk heap_ch; + /* For managing my own list of currently free trace data structures. */ static t_trace* trace_free_head = nullptr; /* For keeping track of the sudo malloc memory for the trace*/ static vtr::t_chunk trace_ch; static int num_trace_allocated = 0; /* To watch for memory leaks. */ +static int num_heap_allocated = 0; static int num_linked_f_pointer_allocated = 0; /* The numbering relation between the channels and clbs is: * @@ -228,9 +238,7 @@ void try_graph(int width_fac, const t_router_opts& router_opts, t_det_routing_ar router_opts.trim_obs_channels, router_opts.clock_modeling, directs, num_directs, - &warning_count, - router_opts.read_edge_metadata, - router_opts.do_check_rr_graph); + &warning_count); } bool try_route(int width_fac, @@ -280,9 +288,7 @@ bool try_route(int width_fac, router_opts.trim_obs_channels, router_opts.clock_modeling, directs, num_directs, - &warning_count, - router_opts.read_edge_metadata, - router_opts.do_check_rr_graph); + &warning_count); //Initialize drawing, now that we have an RR graph init_draw_coords(width_fac); @@ -461,6 +467,17 @@ void pathfinder_update_cost(float pres_fac, float acc_fac) { } } +void init_heap(const DeviceGrid& grid) { + if (heap != nullptr) { + vtr::free(heap + 1); + heap = nullptr; + } + heap_size = (grid.width() - 1) * (grid.height() - 1); + heap = (t_heap**)vtr::malloc(heap_size * sizeof(t_heap*)); + heap--; /* heap stores from [1..heap_size] */ + heap_tail = 1; +} + /* Call this before you route any nets. It frees any old traceback and * * sets the list of rr_nodes touched to empty. */ void init_route_structs(int bb_factor) { @@ -476,7 +493,7 @@ void init_route_structs(int bb_factor) { route_ctx.trace.resize(cluster_ctx.clb_nlist.nets().size()); route_ctx.trace_nodes.resize(cluster_ctx.clb_nlist.nets().size()); - Bucket::init(device_ctx.grid); + init_heap(device_ctx.grid); //Various look-ups route_ctx.net_rr_terminals = load_net_rr_terminals(device_ctx.rr_node_indices); @@ -488,7 +505,7 @@ void init_route_structs(int bb_factor) { /* Check that things that should have been emptied after the last routing * * really were. */ - if (!is_empty_heap()) { + if (heap_tail != 1) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in init_route_structs. Heap is not empty.\n"); } @@ -936,12 +953,36 @@ void free_route_structs() { * final routing result is not freed. */ auto& route_ctx = g_vpr_ctx.mutable_routing(); - BucketItems::free(); - Bucket::free(); + if (heap != nullptr) { + //Free the individiaul heap elements (calls destructors) + for (int i = 1; i < num_heap_allocated; i++) { + VTR_LOG("Freeing %p\n", heap[i]); + vtr::chunk_delete(heap[i], &heap_ch); + } + + // coverity[offset_free : Intentional] + free(heap + 1); + + heap = nullptr; /* Defensive coding: crash hard if I use these. */ + } + + if (heap_free_head != nullptr) { + t_heap* curr = heap_free_head; + while (curr) { + t_heap* tmp = curr; + curr = curr->u.next; + vtr::chunk_delete(tmp, &heap_ch); + } + + heap_free_head = nullptr; + } if (route_ctx.route_bb.size() != 0) { route_ctx.route_bb.clear(); } + + /*free the memory chunks that were used by heap and linked f pointer */ + free_chunk_memory(&heap_ch); } /* Frees the data structures needed to save a routing. */ @@ -1159,18 +1200,227 @@ void add_to_mod_list(int inode, std::vector& modified_rr_node_inf) { } } +namespace heap_ { +size_t parent(size_t i); +size_t left(size_t i); +size_t right(size_t i); +size_t size(); +void expand_heap_if_full(); + +size_t parent(size_t i) { return i >> 1; } +// child indices of a heap +size_t left(size_t i) { return i << 1; } +size_t right(size_t i) { return (i << 1) + 1; } +size_t size() { return static_cast(heap_tail - 1); } // heap[0] is not valid element + +// make a heap rooted at index i by **sifting down** in O(lgn) time +void sift_down(size_t hole) { + t_heap* head{heap[hole]}; + size_t child{left(hole)}; + while ((int)child < heap_tail) { + if ((int)child + 1 < heap_tail && heap[child + 1]->cost < heap[child]->cost) + ++child; + if (heap[child]->cost < head->cost) { + heap[hole] = heap[child]; + hole = child; + child = left(child); + } else + break; + } + heap[hole] = head; +} + +// runs in O(n) time by sifting down; the least work is done on the most elements: 1 swap for bottom layer, 2 swap for 2nd, ... lgn swap for top +// 1*(n/2) + 2*(n/4) + 3*(n/8) + ... + lgn*1 = 2n (sum of i/2^i) +void build_heap() { + // second half of heap are leaves + for (size_t i = heap_tail >> 1; i != 0; --i) + sift_down(i); +} + +// O(lgn) sifting up to maintain heap property after insertion (should sift down when building heap) +void sift_up(size_t leaf, t_heap* const node) { + while ((leaf > 1) && (node->cost < heap[parent(leaf)]->cost)) { + // sift hole up + heap[leaf] = heap[parent(leaf)]; + leaf = parent(leaf); + } + heap[leaf] = node; +} + +void expand_heap_if_full() { + if (heap_tail > heap_size) { /* Heap is full */ + heap_size *= 2; + heap = (t_heap**)vtr::realloc((void*)(heap + 1), + heap_size * sizeof(t_heap*)); + heap--; /* heap goes from [1..heap_size] */ + } +} + +// adds an element to the back of heap and expand if necessary, but does not maintain heap property +void push_back(t_heap* const hptr) { + expand_heap_if_full(); + heap[heap_tail] = hptr; + ++heap_tail; +} + +void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream) { + /* Puts an rr_node on the heap with the same condition as node_to_heap, + * but do not fix heap property yet as that is more efficiently done from + * bottom up with build_heap */ + + auto& route_ctx = g_vpr_ctx.routing(); + if (total_cost >= route_ctx.rr_node_route_inf[inode].path_cost) + return; + + t_heap* hptr = alloc_heap_data(); + hptr->index = inode; + hptr->cost = total_cost; + hptr->u.prev.node = prev_node; + hptr->u.prev.edge = prev_edge; + hptr->backward_path_cost = backward_path_cost; + hptr->R_upstream = R_upstream; + push_back(hptr); +} + +bool is_valid() { + for (size_t i = 1; (int)i <= heap_tail >> 1; ++i) { + if ((int)left(i) < heap_tail && heap[left(i)]->cost < heap[i]->cost) return false; + if ((int)right(i) < heap_tail && heap[right(i)]->cost < heap[i]->cost) return false; + } + return true; +} +// extract every element and print it +void pop_heap() { + while (!is_empty_heap()) + VTR_LOG("%e ", get_heap_head()->cost); + VTR_LOG("\n"); +} +// print every element; not necessarily in order for minheap +void print_heap() { + for (int i = 1; i> 1; ++i) + VTR_LOG("(%e %e %e) ", heap[i]->cost, heap[left(i)]->cost, heap[right(i)]->cost); + VTR_LOG("\n"); +} +// verify correctness of extract top by making a copy, sorting it, and iterating it at the same time as extraction +void verify_extract_top() { + constexpr float float_epsilon = 1e-20; + std::cout << "copying heap\n"; + std::vector heap_copy{heap + 1, heap + heap_tail}; + // sort based on cost with cheapest first + VTR_ASSERT(heap_copy.size() == size()); + std::sort(begin(heap_copy), end(heap_copy), + [](const t_heap* a, const t_heap* b) { + return a->cost < b->cost; + }); + std::cout << "starting to compare top elements\n"; + size_t i = 0; + while (!is_empty_heap()) { + while (heap_copy[i]->index == OPEN) + ++i; // skip the ones that won't be extracted + auto top = get_heap_head(); + if (abs(top->cost - heap_copy[i]->cost) > float_epsilon) + std::cout << "mismatch with sorted " << top << '(' << top->cost << ") " << heap_copy[i] << '(' << heap_copy[i]->cost << ")\n"; + ++i; + } + if (i != heap_copy.size()) + std::cout << "did not finish extracting: " << i << " vs " << heap_copy.size() << std::endl; + else + std::cout << "extract top working as intended\n"; +} +} // namespace heap_ // adds to heap and maintains heap quality +void add_to_heap(t_heap* hptr) { + heap_::expand_heap_if_full(); + // start with undefined hole + ++heap_tail; + heap_::sift_up(heap_tail - 1, hptr); +} + /*WMF: peeking accessor :) */ +bool is_empty_heap() { + return (bool)(heap_tail == 1); +} + +t_heap* +get_heap_head() { + /* Returns a pointer to the smallest element on the heap, or NULL if the * + * heap is empty. Invalid (index == OPEN) entries on the heap are never * + * returned -- they are just skipped over. */ + + t_heap* cheapest; + size_t hole, child; + + do { + if (heap_tail == 1) { /* Empty heap. */ + VTR_LOG_WARN("Empty heap occurred in get_heap_head.\n"); + return (nullptr); + } + + cheapest = heap[1]; + + hole = 1; + child = 2; + --heap_tail; + while ((int)child < heap_tail) { + if (heap[child + 1]->cost < heap[child]->cost) + ++child; // become right child + heap[hole] = heap[child]; + hole = child; + child = heap_::left(child); + } + heap_::sift_up(hole, heap[heap_tail]); + + } while (cheapest->index == OPEN); /* Get another one if invalid entry. */ + + return (cheapest); +} + +void empty_heap() { + for (int i = 1; i < heap_tail; i++) + free_heap_data(heap[i]); + + heap_tail = 1; +} + +t_heap* +alloc_heap_data() { + if (heap_free_head == nullptr) { /* No elements on the free list */ + heap_free_head = vtr::chunk_new(&heap_ch); + } + + //Extract the head + t_heap* temp_ptr = heap_free_head; + heap_free_head = heap_free_head->u.next; + + num_heap_allocated++; + + //Reset + temp_ptr->u.next = nullptr; + temp_ptr->cost = 0.; + temp_ptr->backward_path_cost = 0.; + temp_ptr->R_upstream = 0.; + temp_ptr->index = OPEN; + temp_ptr->u.prev.node = NO_PREVIOUS; + temp_ptr->u.prev.edge = NO_PREVIOUS; + return (temp_ptr); +} + +void free_heap_data(t_heap* hptr) { + hptr->u.next = heap_free_head; + heap_free_head = hptr; + num_heap_allocated--; +} void invalidate_heap_entries(int sink_node, int ipin_node) { /* Marks all the heap entries consisting of sink_node, where it was reached * * via ipin_node, as invalid (OPEN). Used only by the breadth_first router * * and even then only in rare circumstances. */ - for (auto* item : vtr::make_range(BucketItems::begin(), BucketItems::end())) { - if (item->index == sink_node) { - if (item->u.prev.node == ipin_node) { - item->index = OPEN; /* Invalid. */ + for (int i = 1; i < heap_tail; i++) { + if (heap[i]->index == sink_node) { + if (heap[i]->u.prev.node == ipin_node) { + heap[i]->index = OPEN; /* Invalid. */ break; } } @@ -1323,7 +1573,7 @@ void print_route(const char* placement_file, const char* route_file) { if (getEchoEnabled() && isEchoFileEnabled(E_ECHO_MEM)) { fp = vtr::fopen(getEchoFileName(E_ECHO_MEM), "w"); fprintf(fp, "\nNum_heap_allocated: %d Num_trace_allocated: %d\n", - BucketItems::num_heap_allocated(), num_trace_allocated); + num_heap_allocated, num_trace_allocated); fprintf(fp, "Num_linked_f_pointer_allocated: %d\n", num_linked_f_pointer_allocated); fclose(fp); @@ -1333,14 +1583,14 @@ void print_route(const char* placement_file, const char* route_file) { route_ctx.routing_id = vtr::secure_digest_file(route_file); } -//To ensure the router can only swap pins which are actually logically equivalent, some block output pins must be +//To ensure the router can only swaps pin which are actually logically equivalent some block output pins must be //reserved in certain cases. // // In the RR graph, output pin equivalence is modelled by a single SRC node connected to (multiple) OPINs, modelling // that each of the OPINs is logcially equivalent (i.e. it doesn't matter through which the router routes a signal, // so long as it is from the appropriate SRC). // -// This correctly models 'full' equivalence (e.g. if there is a full crossbar between the outputs), but is too +// This correctly models 'full' equivalence (e.g. if there is a full crossbar between the outputs), but is to // optimistic for 'instance' equivalence (which typcially models the pin equivalence possible by swapping sub-block // instances like BLEs). In particular, for the 'instance' equivalence case, some of the 'equivalent' block outputs // may be used by internal signals which are routed entirely *within* the block (i.e. the signals which never leave @@ -1387,7 +1637,7 @@ void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local VTR_ASSERT(type->class_inf[iclass].equivalence == PortEquivalence::INSTANCE); //From the SRC node we walk through it's out going edges to collect the - //OPIN nodes. We then push them onto a heap so the OPINs with lower + //OPIN nodes. We then push them onto a heap so the the OPINs with lower //congestion cost are popped-off/reserved first. (Intuitively, we want //the reserved OPINs to move out of the way of congestion, by preferring //to reserve OPINs with lower congestion costs). diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h index 19d537295be..147ff9ddc23 100644 --- a/vpr/src/route/route_common.h +++ b/vpr/src/route/route_common.h @@ -3,7 +3,52 @@ #include #include "clustered_netlist.h" #include "vtr_vector.h" -#include "bucket.h" + +/* Used by the heap as its fundamental data structure. + * Each heap element represents a partial route. + * + * cost: The cost used to sort heap. + * For the timing-driven router this is the backward_path_cost + + * expected cost to the target. + * For the breadth-first router it is the node cost to reach this + * point. + * + * backward_path_cost: Used only by the timing-driven router. The "known" + * cost of the path up to and including this node. + * In this case, the .cost member contains not only + * the known backward cost but also an expected cost + * to the target. + * + * R_upstream: Used only by the timing-driven router. Stores the upstream + * resistance to ground from this node, including the + * resistance of the node itself (device_ctx.rr_nodes[index].R). + * + * index: The RR node index associated with the costs/R_upstream values + * + * u.prev.node: The previous node used to reach the current 'index' node + * u.prev.next: The edge from u.prev.node used to reach the current 'index' node + * + * u.next: pointer to the next s_heap structure in the free + * linked list. Not used when on the heap. + * + */ +struct t_heap { + float cost = 0.; + float backward_path_cost = 0.; + float R_upstream = 0.; + + int index = OPEN; + + struct t_prev { + int node; + int edge; + }; + + union { + t_heap* next; + t_prev prev; + } u; +}; /******* Subroutines in route_common used only by other router modules ******/ @@ -27,14 +72,36 @@ float get_rr_cong_cost(int inode); void mark_ends(ClusterNetId net_id); void mark_remaining_ends(const std::vector& remaining_sinks); +void add_to_heap(t_heap* hptr); +t_heap* alloc_heap_data(); void node_to_heap(int inode, float cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream); +bool is_empty_heap(); + void free_traceback(ClusterNetId net_id); void drop_traceback_tail(ClusterNetId net_id); void free_traceback(t_trace* tptr); void add_to_mod_list(int inode, std::vector& modified_rr_node_inf); +namespace heap_ { +void build_heap(); +void sift_down(size_t hole); +void sift_up(size_t tail, t_heap* const hptr); +void push_back(t_heap* const hptr); +void push_back_node(int inode, float total_cost, int prev_node, int prev_edge, float backward_path_cost, float R_upstream); +bool is_valid(); +void pop_heap(); +void print_heap(); +void verify_extract_top(); +} // namespace heap_ + +t_heap* get_heap_head(); + +void empty_heap(); + +void free_heap_data(t_heap* hptr); + void invalidate_heap_entries(int sink_node, int ipin_node); void init_route_structs(int bb_factor); @@ -45,6 +112,7 @@ void reset_rr_node_route_structs(); void free_trace_structs(); +void init_heap(const DeviceGrid& grid); void reserve_locally_used_opins(float pres_fac, float acc_fac, bool rip_up_local_opins); void free_chunk_memory_trace(); diff --git a/vpr/src/route/route_profiling.cpp b/vpr/src/route/route_profiling.cpp index b393711eba9..c5e5737caca 100644 --- a/vpr/src/route/route_profiling.cpp +++ b/vpr/src/route/route_profiling.cpp @@ -2,7 +2,6 @@ #include "globals.h" #include "vpr_types.h" #include "route_profiling.h" -#include "rr_graph.h" namespace profiling { @@ -30,10 +29,6 @@ void time_on_fanout_analysis() {} void profiling_initialization(unsigned /*max_net_fanout*/) {} -void conn_start() {} -void conn_finish(int /*src_rr*/, int /*sink_rr*/, float /*criticality*/) {} -void net_finish() {} - #else constexpr unsigned int fanout_per_bin = 1; @@ -186,12 +181,6 @@ void congestion_analysis() { # endif } -static clock_t conn_start_time; -static float worst_conn_time = 0.f; -static int worst_src_rr; -static int worst_sink_rr; -static float worst_crit; - void profiling_initialization(unsigned max_fanout) { // add 1 so that indexing on the max fanout would still be valid time_on_fanout.resize((max_fanout / fanout_per_bin) + 1, 0); @@ -206,37 +195,8 @@ void profiling_initialization(unsigned max_fanout) { part_tree_preserved = 0; connections_forced_to_reroute = 0; connections_rerouted_due_to_forcing = 0; - worst_conn_time = 0.f; return; } - -void conn_start() { - conn_start_time = clock(); -} -void conn_finish(int src_rr, int sink_rr, float criticality) { - float route_time = static_cast(clock() - conn_start_time) / CLOCKS_PER_SEC; - if (route_time > worst_conn_time) { - worst_src_rr = src_rr; - worst_sink_rr = sink_rr; - worst_conn_time = route_time; - worst_crit = criticality; - } - - VTR_LOG("%s to %s (crit: %f) took %f\n", - describe_rr_node(src_rr).c_str(), - describe_rr_node(sink_rr).c_str(), - criticality, - route_time); -} -void net_finish() { - if (worst_conn_time > 0.f) { - VTR_LOG("Worst conn was %s to %s (crit: %f) took %f\n", - describe_rr_node(worst_src_rr).c_str(), - describe_rr_node(worst_sink_rr).c_str(), - worst_crit, - worst_conn_time); - } -} #endif } // end namespace profiling diff --git a/vpr/src/route/route_profiling.h b/vpr/src/route/route_profiling.h index 3cc1ec377a2..52a73655214 100644 --- a/vpr/src/route/route_profiling.h +++ b/vpr/src/route/route_profiling.h @@ -30,10 +30,6 @@ void congestion_analysis(); void time_on_criticality_analysis(); void time_on_fanout_analysis(); -void conn_start(); -void conn_finish(int src_rr, int sink_rr, float criticality); -void net_finish(); - void profiling_initialization(unsigned max_net_fanout); } // end namespace profiling diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp index 8987e1aaf3a..cc738162be4 100644 --- a/vpr/src/route/route_timing.cpp +++ b/vpr/src/route/route_timing.cpp @@ -179,14 +179,13 @@ static std::vector timing_driven_find_all_shortest_paths_from_heap(const RouterStats& router_stats); void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* node); - -static inline void timing_driven_expand_cheapest(t_heap* cheapest, - int target_node, - const t_conn_cost_params cost_params, - t_bb bounding_box, - const RouterLookahead& router_lookahead, - std::vector& modified_rr_node_inf, - RouterStats& router_stats); +static void timing_driven_expand_cheapest(t_heap* cheapest, + int target_node, + const t_conn_cost_params cost_params, + t_bb bounding_box, + const RouterLookahead& router_lookahead, + std::vector& modified_rr_node_inf, + RouterStats& router_stats); static t_rt_node* setup_routing_resources(int itry, ClusterNetId net_id, unsigned num_sinks, float pres_fac, int min_incremental_reroute_fanout, CBRR& incremental_rerouting_res, t_rt_node** rt_node_of_sink); @@ -206,54 +205,54 @@ static t_bb add_high_fanout_route_tree_to_heap(t_rt_node* rt_root, static t_bb adjust_highfanout_bounding_box(t_bb highfanout_bb); -static inline void add_route_tree_node_to_heap(t_rt_node* rt_node, - int target_node, - const t_conn_cost_params cost_params, - const RouterLookahead& router_lookahead, - RouterStats& router_stats); +static void add_route_tree_node_to_heap(t_rt_node* rt_node, + int target_node, + const t_conn_cost_params cost_params, + const RouterLookahead& router_lookahead, + RouterStats& router_stats); + +static void timing_driven_expand_neighbours(t_heap* current, + const t_conn_cost_params cost_params, + t_bb bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + RouterStats& router_stats); + +static void timing_driven_expand_neighbour(t_heap* current, + const int from_node, + const t_edge_size from_edge, + const int to_node, + const t_conn_cost_params cost_params, + const t_bb bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + const t_bb target_bb, + RouterStats& router_stats); + +static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, + const RouterLookahead& router_lookahead, + const t_heap* current, + const int from_node, + const int to_node, + const int iconn, + const int target_node, + RouterStats& router_stats); + +static void timing_driven_expand_node(const t_conn_cost_params cost_params, + const RouterLookahead& router_lookahead, + t_heap* current, + const int from_node, + const int to_node, + const int iconn, + const int target_node); -static inline void timing_driven_expand_neighbours(t_heap* current, - const t_conn_cost_params cost_params, - const t_bb& bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - RouterStats& router_stats); - -static inline void timing_driven_expand_neighbour(t_heap* current, - const int from_node, - const t_edge_size from_edge, - const int to_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - const t_bb& target_bb, - RouterStats& router_stats); - -static inline void timing_driven_add_to_heap(const t_conn_cost_params& cost_params, - const RouterLookahead& router_lookahead, - const t_heap* current, - const int from_node, - const int to_node, - const int iconn, - const int target_node, - RouterStats& router_stats); - -static inline void timing_driven_expand_node(const t_conn_cost_params& cost_params, - const RouterLookahead& router_lookahead, - t_heap* current, - const int from_node, - const int to_node, - const int iconn, - const int target_node); - -static inline void evaluate_timing_driven_node_costs(t_heap* from, - const t_conn_cost_params& cost_params, - const RouterLookahead& router_lookahead, - const int from_node, - const int to_node, - const int iconn, - const int target_node); +static void evaluate_timing_driven_node_costs(t_heap* from, + const t_conn_cost_params cost_params, + const RouterLookahead& router_lookahead, + const int from_node, + const int to_node, + const int iconn, + const int target_node); static bool timing_driven_check_net_delays(vtr::vector& net_delay); @@ -1044,8 +1043,6 @@ bool timing_driven_route_net(ClusterNetId net_id, conn_delay_budget.short_path_criticality = budgeting_inf.get_crit_short_path(net_id, target_pin); } - profiling::conn_start(); - // build a branch in the route tree to the target if (!timing_driven_route_sink(net_id, itarget, @@ -1059,15 +1056,10 @@ bool timing_driven_route_net(ClusterNetId net_id, router_stats)) return false; - profiling::conn_finish(route_ctx.net_rr_terminals[net_id][0], - sink_rr, - pin_criticality[target_pin]); - ++router_stats.connections_routed; } // finished all sinks ++router_stats.nets_routed; - profiling::net_finish(); /* For later timing analysis. */ @@ -1602,8 +1594,8 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, int inode = cheapest->index; - float old_total_cost = route_ctx.rr_node_route_inf[inode].path_cost; - float old_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost; + float best_total_cost = route_ctx.rr_node_route_inf[inode].path_cost; + float best_back_cost = route_ctx.rr_node_route_inf[inode].backward_path_cost; float new_total_cost = cheapest->cost; float new_back_cost = cheapest->backward_path_cost; @@ -1616,7 +1608,9 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, * than one with higher cost. Test whether or not I should disallow * * re-expansion based on a higher total cost. */ - if (old_total_cost > new_total_cost && old_back_cost > new_back_cost) { + if (best_total_cost > new_total_cost && best_back_cost > new_back_cost) { + //Explore from this node, since the current/new partial path has the best cost + //found so far VTR_LOGV_DEBUG(f_router_debug, " Better cost to %d\n", inode); VTR_LOGV_DEBUG(f_router_debug, " New total cost: %g\n", new_total_cost); VTR_LOGV_DEBUG(f_router_debug, " New back cost: %g\n", new_back_cost); @@ -1634,9 +1628,11 @@ static void timing_driven_expand_cheapest(t_heap* cheapest, target_node, router_stats); } else { + //Post-heap prune, do not re-explore from the current/new partial path as it + //has worse cost than the best partial path to this node found so far VTR_LOGV_DEBUG(f_router_debug, " Worse cost to %d\n", inode); - VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", old_total_cost); - VTR_LOGV_DEBUG(f_router_debug, " Old back cost: %g\n", old_back_cost); + VTR_LOGV_DEBUG(f_router_debug, " Old total cost: %g\n", best_total_cost); + VTR_LOGV_DEBUG(f_router_debug, " Old back cost: %g\n", best_back_cost); VTR_LOGV_DEBUG(f_router_debug, " New total cost: %g\n", new_total_cost); VTR_LOGV_DEBUG(f_router_debug, " New back cost: %g\n", new_back_cost); } @@ -1965,12 +1961,12 @@ static void add_route_tree_node_to_heap(t_rt_node* rt_node, ++router_stats.heap_pushes; } -static inline void timing_driven_expand_neighbours(t_heap* current, - const t_conn_cost_params cost_params, - const t_bb& bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - RouterStats& router_stats) { +static void timing_driven_expand_neighbours(t_heap* current, + const t_conn_cost_params cost_params, + t_bb bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + RouterStats& router_stats) { /* Puts all the rr_nodes adjacent to current on the heap. */ @@ -2002,16 +1998,16 @@ static inline void timing_driven_expand_neighbours(t_heap* current, //Conditionally adds to_node to the router heap (via path from from_node via from_edge). //RR nodes outside the expanded bounding box specified in bounding_box are not added //to the heap. -static inline void timing_driven_expand_neighbour(t_heap* current, - const int from_node, - const t_edge_size from_edge, - const int to_node, - const t_conn_cost_params& cost_params, - const t_bb& bounding_box, - const RouterLookahead& router_lookahead, - int target_node, - const t_bb& target_bb, - RouterStats& router_stats) { +static void timing_driven_expand_neighbour(t_heap* current, + const int from_node, + const t_edge_size from_edge, + const int to_node, + const t_conn_cost_params cost_params, + const t_bb bounding_box, + const RouterLookahead& router_lookahead, + int target_node, + const t_bb target_bb, + RouterStats& router_stats) { auto& device_ctx = g_vpr_ctx.device(); int to_xlow = device_ctx.rr_nodes[to_node].xlow(); @@ -2067,14 +2063,14 @@ static inline void timing_driven_expand_neighbour(t_heap* current, } //Add to_node to the heap, and also add any nodes which are connected by non-configurable edges -static inline void timing_driven_add_to_heap(const t_conn_cost_params& cost_params, - const RouterLookahead& router_lookahead, - const t_heap* current, - const int from_node, - const int to_node, - const int iconn, - const int target_node, - RouterStats& router_stats) { +static void timing_driven_add_to_heap(const t_conn_cost_params cost_params, + const RouterLookahead& router_lookahead, + const t_heap* current, + const int from_node, + const int to_node, + const int iconn, + const int target_node, + RouterStats& router_stats) { t_heap* next = alloc_heap_data(); next->index = to_node; @@ -2089,28 +2085,29 @@ static inline void timing_driven_add_to_heap(const t_conn_cost_params& cost_para auto& route_ctx = g_vpr_ctx.routing(); - float old_next_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost; - float old_next_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost; + float best_total_cost = route_ctx.rr_node_route_inf[to_node].path_cost; + float best_back_cost = route_ctx.rr_node_route_inf[to_node].backward_path_cost; - float new_next_total_cost = next->cost; - float new_next_back_cost = next->backward_path_cost; + float new_total_cost = next->cost; + float new_back_cost = next->backward_path_cost; - if (old_next_total_cost > new_next_total_cost && old_next_back_cost > new_next_back_cost) { - //Add node to the heap only if the current cost is less than its historic cost, since - //there is no point in for the router to expand more expensive paths. - VTR_LOGV_DEBUG(f_router_debug, " Adding node %8d to heap from init route tree with cost %g (%s)\n", - next->index, new_next_total_cost, describe_rr_node(next->index).c_str()); + VTR_ASSERT_SAFE(next->index == to_node); + + if (new_total_cost < best_total_cost && new_back_cost < best_back_cost) { + //Add node to the heap only if the cost via the current partial path is less than the + //best known cost, since there is no reason for the router to expand more expensive paths. + // + //Pre-heap prune to keep the heap small, by not putting paths which are known to be + //sub-optimal (at this point in time) into the heap. add_to_heap(next); ++router_stats.heap_pushes; - } - - else { + } else { free_heap_data(next); } } //Updates current (path step and costs) to account for the step taken to reach to_node -static void timing_driven_expand_node(const t_conn_cost_params& cost_params, +static void timing_driven_expand_node(const t_conn_cost_params cost_params, const RouterLookahead& router_lookahead, t_heap* current, const int from_node, @@ -2132,7 +2129,7 @@ static void timing_driven_expand_node(const t_conn_cost_params& cost_params, //Calculates the cost of reaching to_node static void evaluate_timing_driven_node_costs(t_heap* to, - const t_conn_cost_params& cost_params, + const t_conn_cost_params cost_params, const RouterLookahead& router_lookahead, const int from_node, const int to_node, diff --git a/vpr/src/route/route_timing.h b/vpr/src/route/route_timing.h index 7f3a646624d..c356b096c3b 100644 --- a/vpr/src/route/route_timing.h +++ b/vpr/src/route/route_timing.h @@ -11,8 +11,6 @@ #include "router_stats.h" #include "router_lookahead.h" -extern bool f_router_debug; - int get_max_pins_per_net(); bool try_timing_driven_route(const t_router_opts& router_opts, diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index 59352d966ef..ab0343e4380 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -197,9 +197,7 @@ void alloc_routing_structs(t_chan_width chan_width, router_opts.trim_obs_channels, router_opts.clock_modeling, directs, num_directs, - &warnings, - router_opts.read_edge_metadata, - router_opts.do_check_rr_graph); + &warnings); alloc_and_load_rr_node_route_structs(); diff --git a/vpr/src/route/router_lookahead.cpp b/vpr/src/route/router_lookahead.cpp index 80f29911aa9..130b862e94c 100644 --- a/vpr/src/route/router_lookahead.cpp +++ b/vpr/src/route/router_lookahead.cpp @@ -1,7 +1,6 @@ #include "router_lookahead.h" #include "router_lookahead_map.h" -#include "connection_box_lookahead_map.h" #include "vpr_error.h" #include "globals.h" #include "route_timing.h" @@ -14,8 +13,6 @@ static std::unique_ptr make_router_lookahead_object(e_router_lo return std::make_unique(); } else if (router_lookahead_type == e_router_lookahead::MAP) { return std::make_unique(); - } else if (router_lookahead_type == e_router_lookahead::CONNECTION_BOX_MAP) { - return std::make_unique(); } else if (router_lookahead_type == e_router_lookahead::NO_OP) { return std::make_unique(); } diff --git a/vpr/src/route/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead_map_utils.cpp deleted file mode 100644 index 081d6276057..00000000000 --- a/vpr/src/route/router_lookahead_map_utils.cpp +++ /dev/null @@ -1,250 +0,0 @@ -#include "router_lookahead_map_utils.h" - -#include "globals.h" -#include "vpr_context.h" -#include "vtr_math.h" -#include "route_common.h" - -namespace util { - -PQ_Entry::PQ_Entry( - int set_rr_node_ind, - int switch_ind, - float parent_delay, - float parent_R_upstream, - float parent_congestion_upstream, - bool starting_node, - float Tsw_adjust) { - this->rr_node_ind = set_rr_node_ind; - - auto& device_ctx = g_vpr_ctx.device(); - this->delay = parent_delay; - this->congestion_upstream = parent_congestion_upstream; - this->R_upstream = parent_R_upstream; - if (!starting_node) { - float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; - Tsw += Tsw_adjust; - VTR_ASSERT(Tsw >= 0.f); - float Rsw = device_ctx.rr_switch_inf[switch_ind].R; - float Cnode = device_ctx.rr_nodes[set_rr_node_ind].C(); - float Rnode = device_ctx.rr_nodes[set_rr_node_ind].R(); - - float T_linear = 0.f; - if (device_ctx.rr_switch_inf[switch_ind].buffered()) { - T_linear = Tsw + Rsw * Cnode + 0.5 * Rnode * Cnode; - } else { /* Pass transistor */ - T_linear = Tsw + 0.5 * Rsw * Cnode; - } - - float base_cost = 0.f; - if (device_ctx.rr_switch_inf[switch_ind].configurable()) { - base_cost = get_rr_cong_cost(set_rr_node_ind); - } - - VTR_ASSERT(T_linear >= 0.); - VTR_ASSERT(base_cost >= 0.); - this->delay += T_linear; - - this->congestion_upstream += base_cost; - } - - /* set the cost of this node */ - this->cost = this->delay; -} - -util::PQ_Entry_Delay::PQ_Entry_Delay( - int set_rr_node_ind, - int switch_ind, - const util::PQ_Entry_Delay* parent) { - this->rr_node_ind = set_rr_node_ind; - - if (parent != nullptr) { - auto& device_ctx = g_vpr_ctx.device(); - float Tsw = device_ctx.rr_switch_inf[switch_ind].Tdel; - float Rsw = device_ctx.rr_switch_inf[switch_ind].R; - float Cnode = device_ctx.rr_nodes[set_rr_node_ind].C(); - float Rnode = device_ctx.rr_nodes[set_rr_node_ind].R(); - - float T_linear = 0.f; - if (device_ctx.rr_switch_inf[switch_ind].buffered()) { - T_linear = Tsw + Rsw * Cnode + 0.5 * Rnode * Cnode; - } else { /* Pass transistor */ - T_linear = Tsw + 0.5 * Rsw * Cnode; - } - - VTR_ASSERT(T_linear >= 0.); - this->delay_cost = parent->delay_cost + T_linear; - } else { - this->delay_cost = 0.f; - } -} - -util::PQ_Entry_Base_Cost::PQ_Entry_Base_Cost( - int set_rr_node_ind, - int switch_ind, - const util::PQ_Entry_Base_Cost* parent) { - this->rr_node_ind = set_rr_node_ind; - - if (parent != nullptr) { - auto& device_ctx = g_vpr_ctx.device(); - if (device_ctx.rr_switch_inf[switch_ind].configurable()) { - this->base_cost = parent->base_cost + get_rr_cong_cost(set_rr_node_ind); - } else { - this->base_cost = parent->base_cost; - } - } else { - this->base_cost = 0.f; - } -} - -/* returns cost entry with the smallest delay */ -util::Cost_Entry util::Expansion_Cost_Entry::get_smallest_entry() const { - util::Cost_Entry smallest_entry; - - for (auto entry : this->cost_vector) { - if (!smallest_entry.valid() || entry.delay < smallest_entry.delay) { - smallest_entry = entry; - } - } - - return smallest_entry; -} - -/* returns a cost entry that represents the average of all the recorded entries */ -util::Cost_Entry util::Expansion_Cost_Entry::get_average_entry() const { - float avg_delay = 0; - float avg_congestion = 0; - - for (auto cost_entry : this->cost_vector) { - avg_delay += cost_entry.delay; - avg_congestion += cost_entry.congestion; - } - - avg_delay /= (float)this->cost_vector.size(); - avg_congestion /= (float)this->cost_vector.size(); - - return util::Cost_Entry(avg_delay, avg_congestion); -} - -/* returns a cost entry that represents the geomean of all the recorded entries */ -util::Cost_Entry util::Expansion_Cost_Entry::get_geomean_entry() const { - float geomean_delay = 0; - float geomean_cong = 0; - for (auto cost_entry : this->cost_vector) { - geomean_delay += log(cost_entry.delay); - geomean_cong += log(cost_entry.congestion); - } - - geomean_delay = exp(geomean_delay / (float)this->cost_vector.size()); - geomean_cong = exp(geomean_cong / (float)this->cost_vector.size()); - - return util::Cost_Entry(geomean_delay, geomean_cong); -} - -/* returns a cost entry that represents the medial of all recorded entries */ -util::Cost_Entry util::Expansion_Cost_Entry::get_median_entry() const { - /* find median by binning the delays of all entries and then chosing the bin - * with the largest number of entries */ - - int num_bins = 10; - - /* find entries with smallest and largest delays */ - util::Cost_Entry min_del_entry; - util::Cost_Entry max_del_entry; - for (auto entry : this->cost_vector) { - if (!min_del_entry.valid() || entry.delay < min_del_entry.delay) { - min_del_entry = entry; - } - if (!max_del_entry.valid() || entry.delay > max_del_entry.delay) { - max_del_entry = entry; - } - } - - /* get the bin size */ - float delay_diff = max_del_entry.delay - min_del_entry.delay; - float bin_size = delay_diff / (float)num_bins; - - /* sort the cost entries into bins */ - std::vector> entry_bins(num_bins, std::vector()); - for (auto entry : this->cost_vector) { - float bin_num = floor((entry.delay - min_del_entry.delay) / bin_size); - - VTR_ASSERT(vtr::nint(bin_num) >= 0 && vtr::nint(bin_num) <= num_bins); - if (vtr::nint(bin_num) == num_bins) { - /* largest entry will otherwise have an out-of-bounds bin number */ - bin_num -= 1; - } - entry_bins[vtr::nint(bin_num)].push_back(entry); - } - - /* find the bin with the largest number of elements */ - int largest_bin = 0; - int largest_size = 0; - for (int ibin = 0; ibin < num_bins; ibin++) { - if (entry_bins[ibin].size() > (unsigned)largest_size) { - largest_bin = ibin; - largest_size = (unsigned)entry_bins[ibin].size(); - } - } - - /* get the representative delay of the largest bin */ - util::Cost_Entry representative_entry = entry_bins[largest_bin][0]; - - return representative_entry; -} - -template -void expand_dijkstra_neighbours(const std::vector& rr_nodes, - const Entry& parent_entry, - std::unordered_map& paths, - std::vector& node_expanded, - std::priority_queue, - std::greater>& pq) { - int parent_ind = parent_entry.rr_node_ind; - - auto& parent_node = rr_nodes[parent_ind]; - - for (int iedge = 0; iedge < parent_node.num_edges(); iedge++) { - int child_node_ind = parent_node.edge_sink_node(iedge); - int switch_ind = parent_node.edge_switch(iedge); - - /* skip this child if it has already been expanded from */ - if (node_expanded[child_node_ind]) { - continue; - } - - Entry child_entry(child_node_ind, switch_ind, &parent_entry); - VTR_ASSERT(child_entry.cost() >= 0); - pq.push(child_entry); - - /* Create (if it doesn't exist) or update (if the new cost is lower) - * to specified node */ - Search_Path path_entry = {child_entry.cost(), parent_ind, iedge}; - auto result = paths.insert(std::make_pair( - child_node_ind, - path_entry)); - if (!result.second) { - if (child_entry.cost() < result.first->second.cost) { - result.first->second = path_entry; - } - } - } -} - -template void expand_dijkstra_neighbours(const std::vector& rr_nodes, - const PQ_Entry_Delay& parent_entry, - std::unordered_map& paths, - std::vector& node_expanded, - std::priority_queue, - std::greater>& pq); -template void expand_dijkstra_neighbours(const std::vector& rr_nodes, - const PQ_Entry_Base_Cost& parent_entry, - std::unordered_map& paths, - std::vector& node_expanded, - std::priority_queue, - std::greater>& pq); - -} // namespace util diff --git a/vpr/src/route/router_lookahead_map_utils.h b/vpr/src/route/router_lookahead_map_utils.h deleted file mode 100644 index 36e6ea510f7..00000000000 --- a/vpr/src/route/router_lookahead_map_utils.h +++ /dev/null @@ -1,206 +0,0 @@ -#ifndef ROUTER_LOOKAHEAD_MAP_UTILS_H_ -#define ROUTER_LOOKAHEAD_MAP_UTILS_H_ -/* - * The router lookahead provides an estimate of the cost from an intermediate node to the target node - * during directed (A*-like) routing. - * - * The VPR 7.0 lookahead (route/route_timing.c ==> get_timing_driven_expected_cost) lower-bounds the remaining delay and - * congestion by assuming that a minimum number of wires, of the same type as the current node being expanded, can be used - * to complete the route. While this method is efficient, it can run into trouble with architectures that use - * multiple interconnected wire types. - * - * The lookahead in this file pre-computes delay/congestion costs up and to the right of a starting tile. This generates - * delay/congestion tables for {CHANX, CHANY} channel types, over all wire types defined in the architecture file. - * See Section 3.2.4 in Oleg Petelin's MASc thesis (2016) for more discussion. - * - */ - -#include -#include -#include -#include -#include -#include "vpr_types.h" -#include "rr_node.h" - -namespace util { - -/* when a list of delay/congestion entries at a coordinate in Cost_Entry is boiled down to a single - * representative entry, this enum is passed-in to specify how that representative entry should be - * calculated */ -enum e_representative_entry_method { - FIRST = 0, //the first cost that was recorded - SMALLEST, //the smallest-delay cost recorded - AVERAGE, - GEOMEAN, - MEDIAN -}; - -/* f_cost_map is an array of these cost entries that specifies delay/congestion estimates - * to travel relative x/y distances */ -class Cost_Entry { - public: - float delay; - float congestion; - bool fill; - - Cost_Entry() { - delay = std::numeric_limits::infinity(); - congestion = std::numeric_limits::infinity(); - fill = false; - } - Cost_Entry(float set_delay, float set_congestion) - : delay(set_delay) - , congestion(set_congestion) - , fill(false) {} - Cost_Entry(float set_delay, float set_congestion, bool set_fill) - : delay(set_delay) - , congestion(set_congestion) - , fill(set_fill) {} - bool valid() const { - return std::isfinite(delay) && std::isfinite(congestion); - } -}; - -/* a class that stores delay/congestion information for a given relative coordinate during the Dijkstra expansion. - * since it stores multiple cost entries, it is later boiled down to a single representative cost entry to be stored - * in the final lookahead cost map */ -class Expansion_Cost_Entry { - private: - std::vector cost_vector; - - Cost_Entry get_smallest_entry() const; - Cost_Entry get_average_entry() const; - Cost_Entry get_geomean_entry() const; - Cost_Entry get_median_entry() const; - - public: - void add_cost_entry(e_representative_entry_method method, - float add_delay, - float add_congestion) { - Cost_Entry cost_entry(add_delay, add_congestion); - if (method == SMALLEST) { - /* taking the smallest-delay entry anyway, so no need to push back multple entries */ - if (this->cost_vector.empty()) { - this->cost_vector.push_back(cost_entry); - } else { - if (add_delay < this->cost_vector[0].delay) { - this->cost_vector[0] = cost_entry; - } - } - } else { - this->cost_vector.push_back(cost_entry); - } - } - void clear_cost_entries() { - this->cost_vector.clear(); - } - - Cost_Entry get_representative_cost_entry(e_representative_entry_method method) const { - Cost_Entry entry; - - if (!cost_vector.empty()) { - switch (method) { - case FIRST: - entry = cost_vector[0]; - break; - case SMALLEST: - entry = this->get_smallest_entry(); - break; - case AVERAGE: - entry = this->get_average_entry(); - break; - case GEOMEAN: - entry = this->get_geomean_entry(); - break; - case MEDIAN: - entry = this->get_median_entry(); - break; - default: - break; - } - } - return entry; - } -}; - -/* a class that represents an entry in the Dijkstra expansion priority queue */ -class PQ_Entry { - public: - int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents - float cost; //the cost of the path to get to this node - - /* store backward delay, R and congestion info */ - float delay; - float R_upstream; - float congestion_upstream; - - PQ_Entry(int set_rr_node_ind, int /*switch_ind*/, float parent_delay, float parent_R_upstream, float parent_congestion_upstream, bool starting_node, float Tsw_adjust); - - bool operator<(const PQ_Entry& obj) const { - /* inserted into max priority queue so want queue entries with a lower cost to be greater */ - return (this->cost > obj.cost); - } -}; - -// A version of PQ_Entry that only calculates and stores the delay. -class PQ_Entry_Delay { - public: - int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents - float delay_cost; //the cost of the path to get to this node - - PQ_Entry_Delay(int set_rr_node_ind, int /*switch_ind*/, const PQ_Entry_Delay* parent); - - float cost() const { - return delay_cost; - } - - void adjust_Tsw(float amount) { - delay_cost += amount; - } - - bool operator>(const PQ_Entry_Delay& obj) const { - return (this->delay_cost > obj.delay_cost); - } -}; - -// A version of PQ_Entry that only calculates and stores the base cost. -class PQ_Entry_Base_Cost { - public: - int rr_node_ind; //index in device_ctx.rr_nodes that this entry represents - float base_cost; - - PQ_Entry_Base_Cost(int set_rr_node_ind, int /*switch_ind*/, const PQ_Entry_Base_Cost* parent); - - float cost() const { - return base_cost; - } - - void adjust_Tsw(float /* amount */) { - // do nothing - } - - bool operator>(const PQ_Entry_Base_Cost& obj) const { - return (this->base_cost > obj.base_cost); - } -}; - -struct Search_Path { - float cost; - int parent; - int edge; -}; - -/* iterates over the children of the specified node and selectively pushes them onto the priority queue */ -template -void expand_dijkstra_neighbours(const std::vector& rr_nodes, - const Entry& parent_entry, - std::unordered_map& paths, - std::vector& node_expanded, - std::priority_queue, - std::greater>& pq); - -} // namespace util - -#endif diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index d6eb3c7d8fd..df1bb8b0967 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -32,7 +32,6 @@ #include "rr_graph_writer.h" #include "rr_graph_reader.h" #include "router_lookahead_map.h" -#include "connection_box_lookahead_map.h" #include "rr_graph_clock.h" #include "rr_types.h" @@ -319,9 +318,7 @@ void create_rr_graph(const t_graph_type graph_type, const enum e_clock_modeling clock_modeling, const t_direct_inf* directs, const int num_directs, - int* Warnings, - bool read_edge_metadata, - bool do_check_rr_graph) { + int* Warnings) { const auto& device_ctx = g_vpr_ctx.device(); if (!det_routing_arch->read_rr_graph_filename.empty()) { @@ -333,9 +330,7 @@ void create_rr_graph(const t_graph_type graph_type, segment_inf, base_cost_type, &det_routing_arch->wire_to_rr_ipin_switch, - det_routing_arch->read_rr_graph_filename.c_str(), - read_edge_metadata, - do_check_rr_graph); + det_routing_arch->read_rr_graph_filename.c_str()); } } else { if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_nodes.empty()) { @@ -2514,54 +2509,6 @@ static vtr::NdMatrix, 4> alloc_and_load_track_to_pin_lookup(vtr return track_to_pin_lookup; } -/* Writes out data (excludes fasm metadata) about node inode to binary in file fp * - * Writes data in the following order: int inode, t_rr_type type, e_direction * - * direction (if CHANX or CHANY), uint16_t capacity, length 5 uint16_t array pos, * - * e_side side (if IPIN or OPIN), float R, float C, uint16_t num_edges.Then loops * - * through every edge writing out int edge_sink node and uint16_t edge_switch. */ -void write_rr_node(FILE* fp, const std::vector& L_rr_node, int inode) { - const auto& rr_node = L_rr_node[inode]; - t_rr_type type = rr_node.type(); - uint16_t num_edges = rr_node.num_edges(); - int edge_sink_node; - uint16_t edge_switch; - uint16_t capacity = (uint16_t)rr_node.capacity(); - float R = rr_node.R(); - float C = rr_node.C(); - uint16_t pos[5]; - - pos[0] = rr_node.xlow(); - pos[1] = rr_node.ylow(); - pos[2] = rr_node.xhigh(); - pos[3] = rr_node.yhigh(); - pos[4] = rr_node.ptc_num(); - - fwrite(&inode, sizeof(inode), 1, fp); - fwrite(&type, sizeof(type), 1, fp); - if (rr_node.type() == CHANX || rr_node.type() == CHANY) { - e_direction direction = rr_node.direction(); - fwrite(&direction, sizeof(direction), 1, fp); - } - fwrite(&capacity, sizeof(capacity), 1, fp); - fwrite(pos, sizeof(*pos), 5, fp); - - if (rr_node.type() == IPIN || rr_node.type() == OPIN) { - e_side side = rr_node.side(); - fwrite(&side, sizeof(side), 1, fp); - } - - fwrite(&R, sizeof(R), 1, fp); - fwrite(&C, sizeof(C), 1, fp); - fwrite(&num_edges, sizeof(num_edges), 1, fp); - - for (int iedge = 0; iedge < rr_node.num_edges(); ++iedge) { - edge_sink_node = rr_node.edge_sink_node(iedge); - edge_switch = rr_node.edge_switch(iedge); - fwrite(&edge_sink_node, sizeof(edge_sink_node), 1, fp); - fwrite(&edge_switch, sizeof(edge_switch), 1, fp); - } -} - std::string describe_rr_node(int inode) { auto& device_ctx = g_vpr_ctx.device(); diff --git a/vpr/src/route/rr_graph.h b/vpr/src/route/rr_graph.h index dd65a5fd963..f55a64f7f9f 100644 --- a/vpr/src/route/rr_graph.h +++ b/vpr/src/route/rr_graph.h @@ -6,9 +6,6 @@ * and so are not currently used in commercial architectures. */ #define INCLUDE_TRACK_BUFFERS false -#define BINARY_MAGIC_NUM 0x42525247 -#define BINARY_FILE_VERSION 1 - #include "device_grid.h" enum e_graph_type { @@ -41,18 +38,13 @@ void create_rr_graph(const t_graph_type graph_type, const enum e_clock_modeling clock_modeling, const t_direct_inf* directs, const int num_directs, - int* Warnings, - bool read_edge_metadata, - bool do_check_rr_graph); + int* Warnings); void free_rr_graph(); //Returns a brief one-line summary of an RR node std::string describe_rr_node(int inode); -void print_rr_node(FILE* fp, const std::vector& L_rr_node, int inode); -void write_rr_node(FILE* fp, const std::vector& L_rr_node, int inode); - void init_fan_in(std::vector& L_rr_node, const int num_rr_nodes); // Sets the spec for the rr_switch based on the arch switch diff --git a/vpr/src/route/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_indexed_data.cpp index 2c449d5b95a..0d8fc853268 100644 --- a/vpr/src/route/rr_graph_indexed_data.cpp +++ b/vpr/src/route/rr_graph_indexed_data.cpp @@ -168,14 +168,6 @@ static void load_rr_indexed_data_base_costs(int nodes_per_chan, size_t total_segments = std::accumulate(rr_segment_counts.begin(), rr_segment_counts.end(), 0u); /* Load base costs for CHANX and CHANY segments */ - float max_length = 0; - float min_length = 1; - if (base_cost_type == DELAY_NORMALIZED_LENGTH_BOUNDED) { - for (index = CHANX_COST_INDEX_START; index < device_ctx.rr_indexed_data.size(); index++) { - float length = (1 / device_ctx.rr_indexed_data[index].inv_length); - max_length = std::max(max_length, length); - } - } //Future Work: Since we can now have wire types which don't connect to IPINs, // perhaps consider lowering cost of wires which connect to IPINs @@ -188,15 +180,6 @@ static void load_rr_indexed_data_base_costs(int nodes_per_chan, } else if (base_cost_type == DELAY_NORMALIZED_LENGTH || base_cost_type == DEMAND_ONLY_NORMALIZED_LENGTH) { device_ctx.rr_indexed_data[index].base_cost = delay_normalization_fac / device_ctx.rr_indexed_data[index].inv_length; - } else if (base_cost_type == DELAY_NORMALIZED_LENGTH_BOUNDED) { - float length = (1 / device_ctx.rr_indexed_data[index].inv_length); - if (max_length != min_length) { - float length_scale = 1.f + 3.f * (length - min_length) / (max_length - min_length); - device_ctx.rr_indexed_data[index].base_cost = delay_normalization_fac * length_scale; - } else { - device_ctx.rr_indexed_data[index].base_cost = delay_normalization_fac; - } - } else if (base_cost_type == DELAY_NORMALIZED_FREQUENCY) { int seg_index = device_ctx.rr_indexed_data[index].seg_index; diff --git a/vpr/src/route/rr_graph_reader.cpp b/vpr/src/route/rr_graph_reader.cpp index 55e3f4c876e..e9380b12d7e 100644 --- a/vpr/src/route/rr_graph_reader.cpp +++ b/vpr/src/route/rr_graph_reader.cpp @@ -47,20 +47,17 @@ #include "rr_graph_reader.h" /*********************** Subroutines local to this module *******************/ -void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_segments(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const std::vector& segment_inf); void verify_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_blocks(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void verify_grid(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const DeviceGrid& grid); -void process_nodes_and_switches_bin(FILE* fp, int* wire_to_rr_ipin_switch, bool is_global_graph, const std::vector& segment_inf, int numSwitches); void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data); -void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata); +void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches); void process_channels(t_chan_width& chan_width, const DeviceGrid& grid, pugi::xml_node parent, const pugiutil::loc_data& loc_data); void process_rr_node_indices(const DeviceGrid& grid); void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data); void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, const bool is_global_graph, const int num_seg_types); -void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id); /************************ Subroutine definitions ****************************/ @@ -72,9 +69,7 @@ void load_rr_file(const t_graph_type graph_type, const std::vector& segment_inf, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, - const char* read_rr_graph_name, - bool read_edge_metadata, - bool do_check_rr_graph) { + const char* read_rr_graph_name) { vtr::ScopedStartFinishTimer timer("Loading routing resource graph"); const char* Prop; @@ -135,13 +130,6 @@ void load_rr_file(const t_graph_type graph_type, t_chan_width nodes_per_chan; process_channels(nodes_per_chan, grid, next_component, loc_data); - next_component = get_first_child(rr_graph, "connection_boxes", loc_data, pugiutil::OPTIONAL); - if (next_component != nullptr) { - process_connection_boxes(next_component, loc_data); - } else { - device_ctx.connection_boxes.clear(); - } - /* Decode the graph_type */ bool is_global_graph = (GRAPH_GLOBAL == graph_type ? true : false); @@ -149,48 +137,12 @@ void load_rr_file(const t_graph_type graph_type, int max_chan_width = (is_global_graph ? 1 : nodes_per_chan.max); VTR_ASSERT(max_chan_width > 0); - /* Branches to binary format */ - next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, pugiutil::OPTIONAL); - if (next_component) { - /* Loads edges, switches, and node look up tables*/ - next_component = get_single_child(rr_graph, "switches", loc_data); - - int numSwitches = count_children(next_component, "switch", loc_data); - device_ctx.rr_switch_inf.resize(numSwitches); - - process_switches(next_component, loc_data); - - next_component = get_single_child(rr_graph, "binary_nodes_and_edges", loc_data, pugiutil::OPTIONAL); - auto filename = get_attribute(next_component, "file", loc_data).as_string(""); - VTR_LOG("Using Binary File: %s\n", filename); - FILE* fp = fopen(filename, "rb"); - if (fp == NULL) { - VPR_THROW(VPR_ERROR_OTHER, "Binary File %s Does Not Exist\n", filename); - } - - process_nodes_and_switches_bin(fp, wire_to_rr_ipin_switch, is_global_graph, segment_inf, numSwitches); - - partition_rr_graph_edges(device_ctx); - process_rr_node_indices(grid); - init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size()); - alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices, - max_chan_width, *wire_to_rr_ipin_switch, base_cost_type); - - device_ctx.chan_width = nodes_per_chan; - device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); - - check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); - - return; - } - /* Alloc rr nodes and count count nodes */ next_component = get_single_child(rr_graph, "rr_nodes", loc_data); int num_rr_nodes = count_children(next_component, "node", loc_data); device_ctx.rr_nodes.resize(num_rr_nodes); - device_ctx.connection_boxes.resize_nodes(num_rr_nodes); process_nodes(next_component, loc_data); /* Loads edges, switches, and node look up tables*/ @@ -202,7 +154,7 @@ void load_rr_file(const t_graph_type graph_type, process_switches(next_component, loc_data); next_component = get_single_child(rr_graph, "rr_edges", loc_data); - process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches, read_edge_metadata); + process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches); //Partition the rr graph edges for efficient access to configurable/non-configurable //edge subsets. Must be done after RR switches have been allocated @@ -221,144 +173,16 @@ void load_rr_file(const t_graph_type graph_type, process_seg_id(next_component, loc_data); - device_ctx.connection_boxes.create_sink_back_ref(); - device_ctx.chan_width = nodes_per_chan; device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name); - if (do_check_rr_graph) { - check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); - } + check_rr_graph(graph_type, grid, device_ctx.physical_tile_types); } catch (pugiutil::XmlError& e) { vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what()); } } -/* This function sets the Source pins, sink pins, ipin, and opin - * to their unique cost index identifier. CHANX and CHANY cost indicies are set after the - * seg_id is read in from the rr graph */ -void set_cost_index_bin(int inode, t_rr_type node_type, const bool is_global_graph, const int num_seg_types, short seg_id) { - auto& device_ctx = g_vpr_ctx.mutable_device(); - auto& node = device_ctx.rr_nodes[inode]; - //set the cost index in order to load the segment information, rr nodes should be set already - if (node_type == SOURCE) { - node.set_cost_index(SOURCE_COST_INDEX); - } else if (node_type == SINK) { - node.set_cost_index(SINK_COST_INDEX); - } else if (node_type == IPIN) { - node.set_cost_index(IPIN_COST_INDEX); - } else if (node_type == OPIN) { - node.set_cost_index(OPIN_COST_INDEX); - } else if (node_type == CHANX || node_type == CHANY) { - /*CHANX and CHANY cost index is dependent on the segment id*/ - if (is_global_graph) { - node.set_cost_index(0); - } else if (device_ctx.rr_nodes[inode].type() == CHANX) { - node.set_cost_index(CHANX_COST_INDEX_START + seg_id); - } else if (device_ctx.rr_nodes[inode].type() == CHANY) { - node.set_cost_index(CHANX_COST_INDEX_START + num_seg_types + seg_id); - } - } -} - -void process_nodes_and_switches_bin(FILE* fp, - int* wire_to_rr_ipin_switch, - bool is_global_graph, - const std::vector& segment_inf, - int numSwitches) { - auto& device_ctx = g_vpr_ctx.mutable_device(); - uint32_t magic_num; - uint16_t format_version; - uint16_t header_length; - uint64_t num_rr_nodes; - fread_secure(&magic_num, sizeof(magic_num), 1, fp); - fread_secure(&format_version, sizeof(format_version), 1, fp); - fread_secure(&header_length, sizeof(header_length), 1, fp); - char* header = new char[header_length + 1]; - header[header_length] = '\0'; - fread_secure(header, sizeof(char), header_length, fp); - fread_secure(&num_rr_nodes, sizeof(num_rr_nodes), 1, fp); - device_ctx.rr_nodes.resize(num_rr_nodes); - - if (magic_num != BINARY_MAGIC_NUM) { - VTR_LOG_WARN("Not a VPR Binary rr_graph file\n"); - } - - if (format_version != BINARY_FILE_VERSION) { - VTR_LOG_WARN("Binary file format versions do not match\n"); - } - - int inode; - t_rr_type node_type; - uint16_t num_edges; - e_direction direction; - e_side side; - int edge_sink_node; - uint16_t edge_switch; - uint16_t capacity; - float R; - float C; - uint16_t pos[5]; - - for (uint64_t i = 0; i < num_rr_nodes; i++) { - fread_secure(&inode, sizeof(inode), 1, fp); - fread_secure(&node_type, sizeof(node_type), 1, fp); - auto& node = device_ctx.rr_nodes[inode]; - node.set_type(node_type); - if (node.type() == CHANX || node.type() == CHANY) { - fread_secure(&direction, sizeof(direction), 1, fp); - node.set_direction(direction); - } - - fread_secure(&capacity, sizeof(capacity), 1, fp); - if (capacity > 0) - node.set_capacity(capacity); - fread_secure(pos, sizeof(*pos), 5, fp); - node.set_coordinates(pos[0], pos[1], pos[2], pos[3]); - node.set_ptc_num(pos[4]); - if (node.type() == IPIN || node.type() == OPIN) { - fread_secure(&side, sizeof(side), 1, fp); - node.set_side(side); - } - - fread_secure(&R, sizeof(R), 1, fp); - fread_secure(&C, sizeof(C), 1, fp); - node.set_rc_index(find_create_rr_rc_data(R, C)); - - fread_secure(&num_edges, sizeof(num_edges), 1, fp); - - node.set_num_edges(num_edges); - for (int j = 0; j < num_edges; j++) { - fread_secure(&edge_sink_node, sizeof(edge_sink_node), 1, fp); - fread_secure(&edge_switch, sizeof(edge_switch), 1, fp); - node.set_edge_sink_node(j, edge_sink_node); - node.set_edge_switch(j, edge_switch); - } - set_cost_index_bin(inode, node_type, is_global_graph, segment_inf.size(), 0); - } - std::vector count_for_wire_to_ipin_switches; - count_for_wire_to_ipin_switches.resize(numSwitches, 0); - for (uint64_t i = 0; i < num_rr_nodes; i++) { - auto& node = device_ctx.rr_nodes[i]; - if (node.type() == CHANX || node.type() == CHANY) { - num_edges = node.num_edges(); - for (int j = 0; j < num_edges; j++) { - if (device_ctx.rr_nodes[node.edge_sink_node(j)].type() == IPIN) { - count_for_wire_to_ipin_switches[j]++; - } - } - } - } - int max = -1; - for (int j = 0; j < numSwitches; j++) { - if (count_for_wire_to_ipin_switches[j] > max) { - *wire_to_rr_ipin_switch = j; - max = count_for_wire_to_ipin_switches[j]; - } - } -} - /* Reads in the switch information and adds it to device_ctx.rr_switch_inf as specified*/ void process_switches(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { auto& device_ctx = g_vpr_ctx.mutable_device(); @@ -480,20 +304,6 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { node.set_type(OPIN); } else if (strcmp(node_type, "IPIN") == 0) { node.set_type(IPIN); - - pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "connection_box", loc_data, pugiutil::OPTIONAL); - if (connection_boxSubnode) { - int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); - int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); - int id = get_attribute(connection_boxSubnode, "id", loc_data).as_int(); - float site_pin_delay = get_attribute(connection_boxSubnode, "site_pin_delay", loc_data).as_float(); - - device_ctx.connection_boxes.add_connection_box(inode, - ConnectionBoxId(id), - std::make_pair(x, y), - site_pin_delay); - } - } else { VPR_FATAL_ERROR(VPR_ERROR_OTHER, "Valid inputs for class types are \"CHANX\", \"CHANY\",\"SOURCE\", \"SINK\",\"OPIN\", and \"IPIN\"."); @@ -513,15 +323,6 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { } } - pugi::xml_node connection_boxSubnode = get_single_child(rr_node, "canonical_loc", loc_data, pugiutil::OPTIONAL); - if (connection_boxSubnode) { - int x = get_attribute(connection_boxSubnode, "x", loc_data).as_int(); - int y = get_attribute(connection_boxSubnode, "y", loc_data).as_int(); - - device_ctx.connection_boxes.add_canonical_loc(inode, - std::make_pair(x, y)); - } - node.set_capacity(get_attribute(rr_node, "capacity", loc_data).as_float()); //-------------- @@ -535,15 +336,15 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { if (node.type() == IPIN || node.type() == OPIN) { e_side side; - const char* side_str = get_attribute(locSubnode, "side", loc_data).as_string(); - if (strcmp(side_str, "LEFT") == 0) { + std::string side_str = get_attribute(locSubnode, "side", loc_data).as_string(); + if (side_str == "LEFT") { side = LEFT; - } else if (strcmp(side_str, "RIGHT") == 0) { + } else if (side_str == "RIGHT") { side = RIGHT; - } else if (strcmp(side_str, "TOP") == 0) { + } else if (side_str == "TOP") { side = TOP; } else { - VTR_ASSERT(strcmp(side_str, "BOTTOM") == 0); + VTR_ASSERT(side_str == "BOTTOM"); side = BOTTOM; } node.set_side(side); @@ -587,7 +388,7 @@ void process_nodes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { /*Loads the edges information from file into vpr. Nodes and switches must be loaded * before calling this function*/ -void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches, bool read_edge_metadata) { +void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, int* wire_to_rr_ipin_switch, const int num_rr_switches) { auto& device_ctx = g_vpr_ctx.mutable_device(); pugi::xml_node edges; @@ -661,18 +462,16 @@ void process_edges(pugi::xml_node parent, const pugiutil::loc_data& loc_data, in device_ctx.rr_nodes[source_node].set_edge_switch(num_edges_for_node[source_node], switch_id); // Read the metadata for the edge - if (read_edge_metadata) { - auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL); - if (metadata) { - auto edges_meta = get_first_child(metadata, "meta", loc_data); - while (edges_meta) { - auto key = get_attribute(edges_meta, "name", loc_data).as_string(); + auto metadata = get_single_child(edges, "metadata", loc_data, pugiutil::OPTIONAL); + if (metadata) { + auto edges_meta = get_first_child(metadata, "meta", loc_data); + while (edges_meta) { + auto key = get_attribute(edges_meta, "name", loc_data).as_string(); - vpr::add_rr_edge_metadata(source_node, sink_node, switch_id, - key, edges_meta.child_value()); + vpr::add_rr_edge_metadata(source_node, sink_node, switch_id, + key, edges_meta.child_value()); - edges_meta = edges_meta.next_sibling(edges_meta.name()); - } + edges_meta = edges_meta.next_sibling(edges_meta.name()); } } num_edges_for_node[source_node]++; @@ -1085,26 +884,3 @@ void set_cost_indices(pugi::xml_node parent, const pugiutil::loc_data& loc_data, rr_node = rr_node.next_sibling(rr_node.name()); } } - -void process_connection_boxes(pugi::xml_node parent, const pugiutil::loc_data& loc_data) { - auto& device_ctx = g_vpr_ctx.mutable_device(); - - int x_dim = get_attribute(parent, "x_dim", loc_data).as_int(0); - int y_dim = get_attribute(parent, "y_dim", loc_data).as_int(0); - int num_boxes = get_attribute(parent, "num_boxes", loc_data).as_int(0); - VTR_ASSERT(num_boxes >= 0); - - pugi::xml_node connection_box = get_first_child(parent, "connection_box", loc_data); - std::vector boxes(num_boxes); - while (connection_box) { - int id = get_attribute(connection_box, "id", loc_data).as_int(-1); - const char* name = get_attribute(connection_box, "name", loc_data).as_string(nullptr); - VTR_ASSERT(id >= 0 && id < num_boxes); - VTR_ASSERT(boxes.at(id).name == ""); - boxes.at(id).name = std::string(name); - - connection_box = connection_box.next_sibling(connection_box.name()); - } - - device_ctx.connection_boxes.reset_boxes(std::make_pair(x_dim, y_dim), boxes); -} diff --git a/vpr/src/route/rr_graph_reader.h b/vpr/src/route/rr_graph_reader.h index 0b7a67392b8..83a5f1100b2 100644 --- a/vpr/src/route/rr_graph_reader.h +++ b/vpr/src/route/rr_graph_reader.h @@ -9,8 +9,6 @@ void load_rr_file(const t_graph_type graph_type, const std::vector& segment_inf, const enum e_base_cost_type base_cost_type, int* wire_to_rr_ipin_switch, - const char* read_rr_graph_name, - bool read_edge_metadata, - bool do_check_rr_graph); + const char* read_rr_graph_name); #endif /* RR_GRAPH_READER_H */ diff --git a/vpr/src/route/rr_graph_writer.cpp b/vpr/src/route/rr_graph_writer.cpp index 128fc5afcfb..9b0b960cb1c 100644 --- a/vpr/src/route/rr_graph_writer.cpp +++ b/vpr/src/route/rr_graph_writer.cpp @@ -5,7 +5,6 @@ * children tags such as timing, location, or some general * details. Each tag has attributes to describe them */ -#include #include #include #include @@ -16,7 +15,6 @@ #include "read_xml_arch_file.h" #include "vtr_version.h" #include "rr_graph_writer.h" -#include "rr_graph.h" /* All values are printed with this precision value. The higher the * value, the more accurate the read in rr graph is. Using numeric_limits @@ -37,16 +35,6 @@ void write_rr_segments(std::fstream& fp, const std::vector& segme /* This function is used to write the rr_graph into xml format into a a file with name: file_name */ void write_rr_graph(const char* file_name, const std::vector& segment_inf) { std::fstream fp; - FILE* fb = nullptr; - std::stringstream header; - std::string filename_str(file_name); - bool binary_mode = (filename_str.substr(filename_str.length() - 7) == "bin.xml"); - std::string bin_file_name; - if (binary_mode) { - bin_file_name = filename_str.substr(0, filename_str.length() - 4); - VTR_LOG("RR_Graph binary file %s\n", bin_file_name.c_str()); - fb = vtr::fopen(bin_file_name.c_str(), "w"); - } fp.open(file_name, std::fstream::out | std::fstream::trunc); /* Prints out general info for easy error checking*/ @@ -55,9 +43,8 @@ void write_rr_graph(const char* file_name, const std::vector& seg "couldn't open file \"%s\" for generating RR graph file\n", file_name); } std::cout << "Writing RR graph" << std::endl; - header << "" << std::endl; - fp << header.rdbuf(); + fp << "" << std::endl; /* Write out each individual component*/ write_rr_channel(fp); @@ -65,31 +52,9 @@ void write_rr_graph(const char* file_name, const std::vector& seg write_rr_segments(fp, segment_inf); write_rr_block_types(fp); write_rr_grid(fp); - if (binary_mode) { - fp << " \n"; - auto& device_ctx = g_vpr_ctx.device(); - const std::string header_s = header.str(); - const char* header_c = header_s.c_str(); - uint32_t magic_num = BINARY_MAGIC_NUM; - uint16_t format_version = BINARY_FILE_VERSION; - uint16_t header_length = header_s.length(); - uint64_t num_rr_nodes = (uint64_t)device_ctx.rr_nodes.size(); - VTR_LOG("RR_Graph binary mode\n"); - printf("Header length: %d\n", header_length); - fwrite(&magic_num, sizeof(magic_num), 1, fb); - fwrite(&format_version, sizeof(format_version), 1, fb); - fwrite(&header_length, sizeof(header_length), 1, fb); - fwrite(&header_c, sizeof(char), header_length, fb); - fwrite(&num_rr_nodes, sizeof(num_rr_nodes), 1, fb); - for (size_t inode = 0; inode < num_rr_nodes; inode++) { - write_rr_node(fb, device_ctx.rr_nodes, inode); - } - fclose(fb); - } else { - write_rr_node(fp); - write_rr_edges(fp); - } - fp << "\n"; + write_rr_node(fp); + write_rr_edges(fp); + fp << ""; fp.close(); diff --git a/vpr/src/route/rr_node.h b/vpr/src/route/rr_node.h index 9ff480b0848..cc9df7a42f8 100644 --- a/vpr/src/route/rr_node.h +++ b/vpr/src/route/rr_node.h @@ -173,7 +173,7 @@ class t_rr_node { t_edge_size edges_capacity_ = 0; uint8_t num_non_configurable_edges_ = 0; - uint16_t cost_index_ = -1; + int8_t cost_index_ = -1; int16_t rc_index_ = -1; int16_t xlow_ = -1; diff --git a/vpr/src/timing/PreClusterDelayCalculator.h b/vpr/src/timing/PreClusterDelayCalculator.h index 24a1b3a5884..54e97e66a1a 100644 --- a/vpr/src/timing/PreClusterDelayCalculator.h +++ b/vpr/src/timing/PreClusterDelayCalculator.h @@ -101,8 +101,9 @@ class PreClusterDelayCalculator : public tatum::DelayCalculator { VTR_ASSERT_MSG((src_node_type == tatum::NodeType::IPIN && sink_node_type == tatum::NodeType::OPIN) || (src_node_type == tatum::NodeType::SOURCE && sink_node_type == tatum::NodeType::SINK) || (src_node_type == tatum::NodeType::SOURCE && sink_node_type == tatum::NodeType::OPIN) + || (src_node_type == tatum::NodeType::CPIN && sink_node_type == tatum::NodeType::OPIN) || (src_node_type == tatum::NodeType::IPIN && sink_node_type == tatum::NodeType::SINK), - "Primitive combinational delay must be between {SOURCE, IPIN} and {SINK, OPIN}"); + "Primitive combinational delay must be between {SOURCE, IPIN} and {SINK, OPIN}, or CPIN/OPIN"); //Primitive internal combinational delay AtomPinId input_pin = netlist_lookup_.tnode_atom_pin(src_node); diff --git a/vpr/src/timing/atom_delay_calc.inl b/vpr/src/timing/atom_delay_calc.inl index 407602c99f9..ec32aa9a361 100644 --- a/vpr/src/timing/atom_delay_calc.inl +++ b/vpr/src/timing/atom_delay_calc.inl @@ -10,8 +10,10 @@ inline AtomDelayCalc::AtomDelayCalc(const AtomNetlist& netlist, const AtomLookup inline float AtomDelayCalc::atom_combinational_delay(const AtomPinId src_pin, const AtomPinId sink_pin, const DelayType delay_type) const { VTR_ASSERT_MSG(netlist_.pin_block(src_pin) == netlist_.pin_block(sink_pin), "Combinational primitive delay must be between pins on the same block"); - VTR_ASSERT_MSG( netlist_.port_type(netlist_.pin_port(src_pin)) == PortType::INPUT - && netlist_.port_type(netlist_.pin_port(sink_pin)) == PortType::OUTPUT, + auto src_pin_type = netlist_.port_type(netlist_.pin_port(src_pin)); + auto sink_pin_type = netlist_.port_type(netlist_.pin_port(sink_pin)); + VTR_ASSERT_MSG((src_pin_type == PortType::INPUT && sink_pin_type == PortType::OUTPUT) + || (src_pin_type == PortType::CLOCK && sink_pin_type == PortType::OUTPUT), "Combinational connections must go from primitive input to output"); //Determine the combinational delay from the pb_graph_pin. diff --git a/vpr/src/timing/timing_graph_builder.cpp b/vpr/src/timing/timing_graph_builder.cpp index 86ff555711a..4d4ac33be99 100644 --- a/vpr/src/timing/timing_graph_builder.cpp +++ b/vpr/src/timing/timing_graph_builder.cpp @@ -267,7 +267,7 @@ void TimingGraphBuilder::add_block_to_timing_graph(const AtomBlockId blk) { } } - //Connect the combinational edges + //Connect the combinational edges from input pins for (AtomPinId src_pin : netlist_.block_input_pins(blk)) { //Combinational edges go between IPINs and OPINs for combinational blocks //and between the internal SOURCEs and SINKS for sequential blocks @@ -327,6 +327,34 @@ void TimingGraphBuilder::add_block_to_timing_graph(const AtomBlockId blk) { } } } + + //Connect the combinational edges from clock pins + // + //These are typically used to represent clock buffers + for (AtomPinId src_clock_pin : netlist_.block_clock_pins(blk)) { + NodeId src_tnode = netlist_lookup_.atom_pin_tnode(src_clock_pin, BlockTnode::EXTERNAL); + + if (!src_tnode) continue; + + //Look-up the combinationally connected sink ports name on the port model + AtomPortId src_port = netlist_.pin_port(src_clock_pin); + const t_model_ports* model_port = netlist_.port_model(src_port); + + for (const std::string& sink_port_name : model_port->combinational_sink_ports) { + AtomPortId sink_port = netlist_.find_port(blk, sink_port_name); + if (!sink_port) continue; //Port may not be connected + + //We now need to create edges between the source pin, and all the pins in the + //output port + for (AtomPinId sink_pin : netlist_.port_pins(sink_port)) { + //Get the tnode of the sink + NodeId sink_tnode = netlist_lookup_.atom_pin_tnode(sink_pin, BlockTnode::EXTERNAL); + + tg_->add_edge(tatum::EdgeType::PRIMITIVE_COMBINATIONAL, src_tnode, sink_tnode); + VTR_LOG("Adding edge from '%s' (%zu) -> '%s' (%zu)\n", netlist_.pin_name(src_clock_pin).c_str(), size_t(src_tnode), netlist_.pin_name(sink_pin).c_str(), size_t(sink_tnode)); + } + } + } } void TimingGraphBuilder::add_net_to_timing_graph(const AtomNetId net) { diff --git a/vpr/src/timing/timing_util.cpp b/vpr/src/timing/timing_util.cpp index 79afcfd67ed..0117ea5fc49 100644 --- a/vpr/src/timing/timing_util.cpp +++ b/vpr/src/timing/timing_util.cpp @@ -571,10 +571,6 @@ float calc_relaxed_criticality(const std::map& domains_max_re max_req += shift; } - if (!std::isfinite(slack)) { - continue; - } - float crit = std::numeric_limits::quiet_NaN(); if (max_req > 0.) { //Standard case diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 13a0da96c0f..e19d1720915 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -1917,15 +1917,6 @@ static int convert_switch_index(int* switch_index, int* fanin) { return -1; } -void fread_secure(void* var, size_t size, unsigned int count, FILE* fp) { - auto result = fread(var, size, count, fp); - if (result != count) { - VPR_THROW(VPR_ERROR_OTHER, "ERROR reading file\n"); - } - - return; -} - /* * print out number of usage for every switch (type / fanin combination) * (referring to rr_graph.c: alloc_rr_switch_inf()) @@ -2123,6 +2114,20 @@ t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physica return physical_tile->equivalent_sites[0]; } +t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk) { + auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& place_ctx = g_vpr_ctx.placement(); + if (place_ctx.block_locs.empty()) { //No placement, pick best match + return pick_best_physical_type(cluster_ctx.clb_nlist.block_type(blk)); + } else { //Have placement, select physical tile implementing blk + auto& device_ctx = g_vpr_ctx.device(); + + t_pl_loc loc = place_ctx.block_locs[blk].loc; + + return device_ctx.grid[loc.x][loc.y].type; + } +} + int get_logical_pin(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int pin) { diff --git a/vpr/src/util/vpr_utils.h b/vpr/src/util/vpr_utils.h index c511bc243df..e43cc91dacd 100644 --- a/vpr/src/util/vpr_utils.h +++ b/vpr/src/util/vpr_utils.h @@ -41,8 +41,6 @@ void get_pin_range_for_block(const ClusterBlockId blk_id, void sync_grid_to_blocks(); -void fread_secure(void* var, size_t size, unsigned int count, FILE* fp); - //Returns the name of the pin_index'th pin on the specified block type std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_index); @@ -156,9 +154,17 @@ void place_sync_external_block_connections(ClusterBlockId iblk); int get_max_num_pins(t_logical_block_type_ptr logical_block); bool is_tile_compatible(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block); + +//Returns the physical tile type which 'best' matches logical_block t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logical_block); + +//Returns the logical block type which 'best' matches the physical tile t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physical_tile); +//Returns the current tile implemnting blk (if placement is valid), or +//the best expected physical tile the block should use (if no valid placement). +t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk); + int get_logical_pin(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int pin); diff --git a/vpr/test/test_vpr.cpp b/vpr/test/test_vpr.cpp index f3ff24b61b1..3aa4029deed 100644 --- a/vpr/test/test_vpr.cpp +++ b/vpr/test/test_vpr.cpp @@ -123,7 +123,6 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { }; vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); - vpr_setup.RouterOpts.read_edge_metadata = true; vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); @@ -165,7 +164,6 @@ TEST_CASE("read_rr_graph_metadata", "[vpr]") { vpr_init(sizeof(argv) / sizeof(argv[0]), argv, &options, &vpr_setup, &arch); - vpr_setup.RouterOpts.read_edge_metadata = true; vpr_create_device(vpr_setup, arch); const auto& device_ctx = g_vpr_ctx.device(); diff --git a/vtr_flow/benchmarks/tests/riscv_core_lut6.blif b/vtr_flow/benchmarks/tests/riscv_core_lut6.blif new file mode 100644 index 00000000000..a313bebc127 --- /dev/null +++ b/vtr_flow/benchmarks/tests/riscv_core_lut6.blif @@ -0,0 +1,19187 @@ +# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os) + +.model riscv_core +.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31] +.outputs bus_address[0] bus_address[1] bus_address[2] bus_address[3] bus_address[4] bus_address[5] bus_address[6] bus_address[7] bus_address[8] bus_address[9] bus_address[10] bus_address[11] bus_address[12] bus_address[13] bus_address[14] bus_address[15] bus_address[16] bus_address[17] bus_address[18] bus_address[19] bus_address[20] bus_address[21] bus_address[22] bus_address[23] bus_address[24] bus_address[25] bus_address[26] bus_address[27] bus_address[28] bus_address[29] bus_address[30] bus_address[31] bus_write_data[0] bus_write_data[1] bus_write_data[2] bus_write_data[3] bus_write_data[4] bus_write_data[5] bus_write_data[6] bus_write_data[7] bus_write_data[8] bus_write_data[9] bus_write_data[10] bus_write_data[11] bus_write_data[12] bus_write_data[13] bus_write_data[14] bus_write_data[15] bus_write_data[16] bus_write_data[17] bus_write_data[18] bus_write_data[19] bus_write_data[20] bus_write_data[21] bus_write_data[22] bus_write_data[23] bus_write_data[24] bus_write_data[25] bus_write_data[26] bus_write_data[27] bus_write_data[28] bus_write_data[29] bus_write_data[30] bus_write_data[31] bus_byte_enable[0] bus_byte_enable[1] bus_byte_enable[2] bus_byte_enable[3] bus_read_enable bus_write_enable pc[0] pc[1] pc[2] pc[3] pc[4] pc[5] pc[6] pc[7] pc[8] pc[9] pc[10] pc[11] pc[12] pc[13] pc[14] pc[15] pc[16] pc[17] pc[18] pc[19] pc[20] pc[21] pc[22] pc[23] pc[24] pc[25] pc[26] pc[27] pc[28] pc[29] pc[30] pc[31] regfile_write_enable rd_address[0] rd_address[1] rd_address[2] rd_address[3] rd_address[4] rs1_address[0] rs1_address[1] rs1_address[2] rs1_address[3] rs1_address[4] rs2_address[0] rs2_address[1] rs2_address[2] rs2_address[3] rs2_address[4] rd_data[0] rd_data[1] rd_data[2] rd_data[3] rd_data[4] rd_data[5] rd_data[6] rd_data[7] rd_data[8] rd_data[9] rd_data[10] rd_data[11] rd_data[12] rd_data[13] rd_data[14] rd_data[15] rd_data[16] rd_data[17] rd_data[18] rd_data[19] rd_data[20] rd_data[21] rd_data[22] rd_data[23] rd_data[24] rd_data[25] rd_data[26] rd_data[27] rd_data[28] rd_data[29] rd_data[30] rd_data[31] +.names $false +.names $true +1 +.names $undef +.names $abc$8517$new_n299_ $abc$8517$new_n303_ inst[2] regfile_write_enable +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n302_ $abc$8517$new_n301_ $abc$8517$new_n300_ $abc$8517$new_n299_ +000 1 +.names inst[1] inst[0] inst[2] inst[4] inst[3] inst[6] $abc$8517$new_n300_ +111100 1 +.names inst[1] inst[0] inst[4] inst[2] inst[3] inst[6] $abc$8517$new_n301_ +111000 1 +.names inst[1] inst[0] inst[2] inst[6] inst[5] inst[4] $abc$8517$new_n302_ +111110 1 +.names inst[1] inst[0] inst[3] inst[6] inst[5] inst[4] $abc$8517$new_n303_ +110000 1 +.names $abc$8517$new_n1349_ $abc$8517$new_n1352_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1344_ bus_address[0] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n307_ $abc$8517$new_n374_ $abc$8517$new_n407_ $abc$8517$new_n404_ $abc$8517$new_n409_ $abc$8517$new_n340_ $abc$8517$new_n306_ +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n308_ $abc$8517$new_n322_ $abc$8517$new_n336_ $abc$8517$new_n307_ +110 1 +.names $abc$8517$new_n319_ $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n308_ +000 1 +.names $abc$8517$new_n315_ $abc$8517$new_n310_ $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ rs2_data[19] $abc$8517$new_n309_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n311_ inst[4] inst[6] $abc$8517$new_n302_ inst[5] inst[2] $abc$8517$new_n310_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100001 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +.names inst[1] inst[0] inst[3] $abc$8517$new_n311_ +110 1 +.names $abc$8517$new_n313_ inst[3] inst[6] inst[5] inst[4] inst[2] $abc$8517$new_n312_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100011 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names inst[1] inst[0] $abc$8517$new_n313_ +11 1 +.names inst[19] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n314_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[19] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n315_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n318_ $abc$8517$new_n310_ $abc$8517$new_n317_ inst[31] $abc$8517$new_n312_ rs2_data[18] $abc$8517$new_n316_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[18] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n317_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[18] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n318_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n321_ $abc$8517$new_n310_ $abc$8517$new_n320_ inst[31] $abc$8517$new_n312_ rs2_data[17] $abc$8517$new_n319_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[17] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n320_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[17] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[17] $abc$8517$new_n321_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n333_ $abc$8517$new_n330_ $abc$8517$new_n327_ $abc$8517$new_n323_ $abc$8517$new_n322_ +0000 1 +.names $abc$8517$new_n326_ $abc$8517$new_n310_ $abc$8517$new_n325_ inst[31] $abc$8517$new_n324_ rs2_data[23] $abc$8517$new_n323_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n311_ inst[5] inst[2] inst[6] inst[4] $abc$8517$new_n302_ $abc$8517$new_n324_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100110 1 +101010 1 +101100 1 +101110 1 +110010 1 +110110 1 +111010 1 +111100 1 +111110 1 +.names inst[23] $abc$8517$new_n300_ $abc$8517$new_n325_ +11 1 +.names rs1_data[23] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n326_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n329_ $abc$8517$new_n310_ $abc$8517$new_n328_ inst[31] $abc$8517$new_n324_ rs2_data[22] $abc$8517$new_n327_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[22] $abc$8517$new_n300_ $abc$8517$new_n328_ +11 1 +.names rs1_data[22] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n329_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n332_ $abc$8517$new_n310_ $abc$8517$new_n331_ inst[31] $abc$8517$new_n324_ rs2_data[21] $abc$8517$new_n330_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[21] $abc$8517$new_n300_ $abc$8517$new_n331_ +11 1 +.names rs1_data[21] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[21] $abc$8517$new_n332_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n335_ $abc$8517$new_n310_ $abc$8517$new_n334_ inst[31] $abc$8517$new_n324_ rs2_data[20] $abc$8517$new_n333_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[20] $abc$8517$new_n300_ $abc$8517$new_n334_ +11 1 +.names rs1_data[20] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n335_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n339_ $abc$8517$new_n337_ $abc$8517$new_n336_ +01 1 +10 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[16] inst[31] inst[16] $abc$8517$new_n337_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n300_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n338_ +000 1 +001 1 +010 1 +.names rs1_data[16] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[16] $abc$8517$new_n339_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n369_ $abc$8517$new_n341_ $abc$8517$new_n367_ $abc$8517$new_n365_ $abc$8517$new_n351_ $abc$8517$new_n340_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11100 1 +.names $abc$8517$new_n345_ $abc$8517$new_n350_ $abc$8517$new_n344_ $abc$8517$new_n342_ $abc$8517$new_n341_ +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8517$new_n310_ rs2_data[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n342_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n344_ $abc$8517$new_n310_ rs2_data[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n343_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names rs1_data[5] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[5] $abc$8517$new_n344_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[4] $abc$8517$new_n346_ inst[11] inst[24] $abc$8517$new_n347_ $abc$8517$new_n345_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +.names inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n346_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n303_ $abc$8517$new_n302_ $abc$8517$new_n348_ $abc$8517$new_n349_ $abc$8517$new_n347_ +0000 1 +0001 1 +0010 1 +.names inst[1] inst[0] inst[2] inst[3] $abc$8517$new_n348_ +1100 1 +.names inst[6] inst[5] $abc$8517$new_n349_ +00 1 +.names rs1_data[4] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[4] $abc$8517$new_n350_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n359_ $abc$8517$new_n363_ $abc$8517$new_n356_ $abc$8517$new_n352_ $abc$8517$new_n351_ +000000 1 +000100 1 +000101 1 +000110 1 +110000 1 +110100 1 +110101 1 +110110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n353_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n352_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names rs1_data[0] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n353_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names inst[7] $abc$8517$new_n311_ inst[5] inst[6] inst[4] $abc$8517$new_n354_ +11100 1 +.names inst[20] $abc$8517$new_n303_ $abc$8517$new_n349_ $abc$8517$new_n348_ $abc$8517$new_n302_ inst[3] $abc$8517$new_n355_ +100010 1 +100110 1 +101010 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n310_ rs2_data[1] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n356_ +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names inst[8] inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n357_ +111000 1 +111001 1 +111010 1 +.names inst[21] $abc$8517$new_n303_ $abc$8517$new_n302_ $abc$8517$new_n349_ $abc$8517$new_n348_ $abc$8517$new_n358_ +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n361_ $abc$8517$new_n310_ $abc$8517$new_n360_ inst[23] $abc$8517$new_n347_ rs2_data[3] $abc$8517$new_n359_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[10] inst[5] $abc$8517$new_n311_ inst[4] inst[6] inst[2] $abc$8517$new_n360_ +111000 1 +111001 1 +111010 1 +.names rs1_data[3] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n361_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[2] $abc$8517$new_n346_ inst[9] inst[22] $abc$8517$new_n347_ $abc$8517$new_n362_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +.names rs1_data[1] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n363_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[2] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n364_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n364_ $abc$8517$new_n362_ $abc$8517$new_n366_ $abc$8517$new_n365_ +100 1 +.names $abc$8517$new_n310_ $abc$8517$new_n361_ $abc$8517$new_n360_ rs2_data[3] $abc$8517$new_n347_ inst[23] $abc$8517$new_n366_ +000000 1 +000010 1 +000011 1 +000100 1 +000110 1 +000111 1 +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +.names $abc$8517$new_n343_ $abc$8517$new_n345_ $abc$8517$new_n350_ $abc$8517$new_n361_ $abc$8517$new_n368_ $abc$8517$new_n367_ +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n360_ rs2_data[3] $abc$8517$new_n347_ inst[23] $abc$8517$new_n368_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n370_ $abc$8517$new_n372_ $abc$8517$new_n373_ $abc$8517$new_n369_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n371_ $abc$8517$new_n310_ rs2_data[7] inst[27] $abc$8517$new_n324_ $abc$8517$new_n370_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names rs1_data[7] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n371_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ rs2_data[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n372_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names rs1_data[6] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n373_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n375_ $abc$8517$new_n381_ $abc$8517$new_n829_ $abc$8517$new_n402_ $abc$8517$new_n395_ $abc$8517$new_n387_ $abc$8517$new_n374_ +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n380_ $abc$8517$new_n376_ $abc$8517$new_n377_ $abc$8517$new_n375_ +000 1 +110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[14] inst[31] inst[14] $abc$8517$new_n376_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n379_ $abc$8517$new_n310_ $abc$8517$new_n378_ inst[31] $abc$8517$new_n312_ rs2_data[15] $abc$8517$new_n377_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[15] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n378_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[15] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n379_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[14] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[14] $abc$8517$new_n380_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n386_ $abc$8517$new_n385_ $abc$8517$new_n382_ $abc$8517$new_n381_ +000 1 +110 1 +.names $abc$8517$new_n384_ $abc$8517$new_n310_ $abc$8517$new_n383_ inst[31] $abc$8517$new_n312_ rs2_data[13] $abc$8517$new_n382_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names inst[13] $abc$8517$new_n300_ inst[3] $abc$8517$new_n302_ $abc$8517$new_n383_ +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names rs1_data[13] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n384_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n312_ rs2_data[12] inst[31] inst[12] $abc$8517$new_n385_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names rs1_data[12] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n386_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n394_ $abc$8517$new_n388_ $abc$8517$new_n392_ $abc$8517$new_n387_ +000 1 +110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n389_ rs2_data[11] $abc$8517$new_n390_ inst[31] $abc$8517$new_n388_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01100 1 +01101 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n313_ inst[3] inst[2] inst[5] inst[6] inst[4] $abc$8517$new_n389_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100101 1 +100110 1 +100111 1 +101001 1 +101010 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names inst[20] inst[3] $abc$8517$new_n302_ $abc$8517$new_n390_ +111 1 +.names inst[7] inst[6] inst[5] $abc$8517$new_n348_ inst[4] $abc$8517$new_n391_ +11110 1 +.names $abc$8517$new_n393_ $abc$8517$new_n310_ inst[30] $abc$8517$new_n324_ rs2_data[10] $abc$8517$new_n392_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names rs1_data[10] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[10] $abc$8517$new_n393_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[11] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[11] $abc$8517$new_n394_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n399_ $abc$8517$new_n398_ $abc$8517$new_n397_ $abc$8517$new_n396_ $abc$8517$new_n395_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ rs2_data[9] inst[29] $abc$8517$new_n324_ $abc$8517$new_n396_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n310_ rs2_data[8] inst[28] $abc$8517$new_n324_ $abc$8517$new_n397_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names rs1_data[9] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[9] $abc$8517$new_n398_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[8] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n399_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n383_ rs2_data[13] $abc$8517$new_n312_ inst[31] $abc$8517$new_n401_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n394_ $abc$8517$new_n403_ $abc$8517$new_n388_ $abc$8517$new_n402_ +010 1 +100 1 +110 1 +111 1 +.names $abc$8517$new_n393_ $abc$8517$new_n310_ rs2_data[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n403_ +10010 1 +10110 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n405_ $abc$8517$new_n387_ $abc$8517$new_n381_ $abc$8517$new_n375_ $abc$8517$new_n404_ +1111 1 +.names $abc$8517$new_n399_ $abc$8517$new_n397_ $abc$8517$new_n406_ $abc$8517$new_n405_ +000 1 +110 1 +.names $abc$8517$new_n398_ $abc$8517$new_n310_ inst[29] $abc$8517$new_n324_ rs2_data[9] $abc$8517$new_n406_ +00000 1 +00001 1 +00010 1 +00011 1 +00110 1 +00111 1 +01000 1 +01010 1 +01100 1 +01110 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n380_ $abc$8517$new_n379_ $abc$8517$new_n376_ $abc$8517$new_n408_ $abc$8517$new_n407_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n378_ rs2_data[15] $abc$8517$new_n312_ inst[31] $abc$8517$new_n408_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n371_ $abc$8517$new_n410_ inst[27] $abc$8517$new_n324_ rs2_data[7] $abc$8517$new_n409_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +011111 1 +100000 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n373_ rs2_data[6] $abc$8517$new_n324_ inst[26] $abc$8517$new_n410_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n326_ $abc$8517$new_n428_ $abc$8517$new_n1347_ $abc$8517$new_n426_ $abc$8517$new_n411_ +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1101 1 +1111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n414_ rs2_data[22] $abc$8517$new_n413_ +010 1 +011 1 +100 1 +110 1 +.names $abc$8517$new_n328_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n414_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n418_ $abc$8517$new_n335_ $abc$8517$new_n332_ $abc$8517$new_n416_ $abc$8517$new_n415_ +0000 1 +0010 1 +0011 1 +0100 1 +0110 1 +0111 1 +1010 1 +1100 1 +1110 1 +1111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n331_ rs2_data[21] $abc$8517$new_n324_ inst[31] $abc$8517$new_n416_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n334_ rs2_data[20] $abc$8517$new_n324_ inst[31] $abc$8517$new_n418_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n316_ $abc$8517$new_n309_ $abc$8517$new_n339_ $abc$8517$new_n321_ $abc$8517$new_n337_ $abc$8517$new_n420_ $abc$8517$new_n419_ +000100 1 +000110 1 +001000 1 +001100 1 +001101 1 +001110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n320_ rs2_data[17] $abc$8517$new_n312_ inst[31] $abc$8517$new_n420_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n314_ rs2_data[19] $abc$8517$new_n312_ inst[31] $abc$8517$new_n422_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n317_ rs2_data[18] $abc$8517$new_n312_ inst[31] $abc$8517$new_n423_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n427_ rs2_data[23] $abc$8517$new_n426_ +010 1 +011 1 +100 1 +110 1 +.names $abc$8517$new_n325_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n427_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n329_ $abc$8517$new_n414_ rs2_data[22] $abc$8517$new_n428_ +0010 1 +0011 1 +1000 1 +1010 1 +.names $abc$8517$new_n310_ $abc$8517$new_n324_ rs2_data[30] inst[31] inst[30] $abc$8517$new_n431_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names rs1_data[30] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[30] $abc$8517$new_n432_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n434_ $abc$8517$new_n310_ inst[31] rs2_data[31] $abc$8517$new_n433_ +0000 1 +0001 1 +0100 1 +0110 1 +1010 1 +1011 1 +1101 1 +1111 1 +.names rs1_data[31] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n434_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n441_ $abc$8517$new_n440_ $abc$8517$new_n438_ $abc$8517$new_n437_ $abc$8517$new_n436_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n324_ rs2_data[29] inst[31] inst[29] $abc$8517$new_n437_ +00000 1 +00001 1 +00100 1 +00101 1 +01000 1 +01010 1 +01100 1 +01110 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n439_ rs2_data[28] $abc$8517$new_n324_ inst[31] $abc$8517$new_n438_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[28] $abc$8517$new_n300_ $abc$8517$new_n439_ +11 1 +.names rs1_data[29] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n440_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[28] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[28] $abc$8517$new_n441_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n443_ $abc$8517$new_n442_ +000 1 +110 1 +.names $abc$8517$new_n441_ $abc$8517$new_n310_ $abc$8517$new_n439_ inst[31] $abc$8517$new_n324_ rs2_data[28] $abc$8517$new_n443_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n450_ $abc$8517$new_n449_ $abc$8517$new_n447_ $abc$8517$new_n445_ $abc$8517$new_n444_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n446_ rs2_data[27] $abc$8517$new_n324_ inst[31] $abc$8517$new_n445_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[27] $abc$8517$new_n300_ $abc$8517$new_n446_ +11 1 +.names $abc$8517$new_n310_ $abc$8517$new_n448_ rs2_data[26] $abc$8517$new_n324_ inst[31] $abc$8517$new_n447_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[26] $abc$8517$new_n300_ $abc$8517$new_n448_ +11 1 +.names rs1_data[27] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n449_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names rs1_data[26] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[26] $abc$8517$new_n450_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 +100010 1 +100110 1 +101010 1 +101100 1 +101110 1 +111100 1 +111110 1 +.names $abc$8517$new_n453_ $abc$8517$new_n452_ $abc$8517$new_n451_ +00 1 +.names $abc$8517$new_n449_ $abc$8517$new_n310_ $abc$8517$new_n446_ inst[31] $abc$8517$new_n324_ rs2_data[27] $abc$8517$new_n452_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n450_ $abc$8517$new_n310_ $abc$8517$new_n448_ inst[31] $abc$8517$new_n324_ rs2_data[26] $abc$8517$new_n453_ +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +000111 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100100 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n460_ $abc$8517$new_n459_ $abc$8517$new_n457_ $abc$8517$new_n455_ $abc$8517$new_n454_ +0100 1 +0110 1 +1000 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n310_ $abc$8517$new_n456_ rs2_data[25] $abc$8517$new_n324_ inst[31] $abc$8517$new_n455_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[25] $abc$8517$new_n300_ $abc$8517$new_n456_ +11 1 +.names $abc$8517$new_n310_ $abc$8517$new_n458_ rs2_data[24] $abc$8517$new_n324_ inst[31] $abc$8517$new_n457_ +00000 1 +00010 1 +00011 1 +00100 1 +00110 1 +00111 1 +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names inst[24] $abc$8517$new_n300_ $abc$8517$new_n458_ +11 1 +.names rs1_data[25] inst[5] inst[3] $abc$8517$new_n302_ $abc$8517$new_n300_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n459_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011110 1 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$abc$8517$new_n355_ $abc$8517$new_n512_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8517$new_n356_ $abc$8517$new_n515_ $abc$8517$new_n514_ $abc$8517$new_n517_ $abc$8517$new_n516_ $abc$8517$new_n513_ +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n350_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n514_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n344_ rs2_data[0] $abc$8517$new_n354_ $abc$8517$new_n355_ $abc$8517$new_n515_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n373_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n516_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n371_ rs2_data[0] $abc$8517$new_n354_ $abc$8517$new_n355_ $abc$8517$new_n517_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8517$new_n356_ $abc$8517$new_n519_ $abc$8517$new_n353_ $abc$8517$new_n364_ $abc$8517$new_n363_ $abc$8517$new_n361_ $abc$8517$new_n518_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n310_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n519_ +0000 1 +0100 1 +1000 1 +1001 1 +1010 1 +1011 1 +.names $abc$8517$new_n362_ $abc$8517$new_n368_ $abc$8517$new_n521_ $abc$8517$new_n526_ $abc$8517$new_n531_ $abc$8517$new_n536_ $abc$8517$new_n520_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 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$abc$8517$new_n315_ rs2_data[0] $abc$8517$new_n354_ $abc$8517$new_n355_ $abc$8517$new_n525_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8517$new_n356_ $abc$8517$new_n528_ $abc$8517$new_n527_ $abc$8517$new_n530_ $abc$8517$new_n529_ $abc$8517$new_n526_ +00000 1 +00100 1 +01000 1 +01100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n335_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n527_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n332_ rs2_data[0] $abc$8517$new_n354_ $abc$8517$new_n355_ $abc$8517$new_n528_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +10100 1 +10101 1 +10110 1 +10111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n329_ rs2_data[0] $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n529_ +00000 1 +00100 1 +10000 1 +10001 1 +10010 1 +10011 1 +.names $abc$8517$new_n310_ $abc$8517$new_n326_ rs2_data[0] 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+000100 1 +000101 1 +000110 1 +001100 1 +001101 1 +001110 1 +010100 1 +010101 1 +010110 1 +011100 1 +011101 1 +011110 1 +101100 1 +101101 1 +101110 1 +110100 1 +110101 1 +110110 1 +.names $abc$8517$new_n437_ $abc$8517$new_n440_ $abc$8517$new_n974_ $abc$8517$new_n442_ $abc$8517$new_n963_ $abc$8517$new_n984_ +00000 1 +00001 1 +00011 1 +01000 1 +01001 1 +01011 1 +01100 1 +01101 1 +01111 1 +11000 1 +11001 1 +11011 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n898_ $abc$8517$new_n943_ $abc$8517$new_n986_ $abc$8517$new_n985_ +00000 1 +00001 1 +00010 1 +00011 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names $abc$8517$new_n356_ $abc$8517$new_n539_ $abc$8517$new_n538_ $abc$8517$new_n535_ $abc$8517$new_n537_ $abc$8517$new_n986_ +00001 1 +00010 1 +00011 1 +00101 1 +00110 1 +00111 1 +01001 1 +01010 1 +01011 1 +01101 1 +01110 1 +01111 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n988_ $abc$8517$new_n789_ $abc$8517$new_n819_ $abc$8517$new_n345_ $abc$8517$new_n795_ $abc$8517$new_n987_ +10000 1 +10001 1 +10011 1 +11000 1 +11001 1 +11011 1 +11100 1 +11101 1 +11111 1 +.names $abc$8517$new_n811_ $abc$8517$new_n432_ $abc$8517$new_n576_ $abc$8517$new_n431_ $abc$8517$new_n547_ $abc$8517$new_n579_ $abc$8517$new_n988_ +000000 1 +000010 1 +000100 1 +000101 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n546_ $abc$8517$new_n433_ $abc$8517$new_n990_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n991_ bus_address[31] +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n982_ $abc$8517$new_n441_ $abc$8517$new_n438_ $abc$8517$new_n440_ $abc$8517$new_n437_ $abc$8517$new_n962_ $abc$8517$new_n990_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +001000 1 +001001 1 +001010 1 +001100 1 +010000 1 +010001 1 +010010 1 +010100 1 +011000 1 +011001 1 +.names $abc$8517$new_n992_ $abc$8517$new_n433_ $abc$8517$new_n431_ $abc$8517$new_n432_ $abc$8517$new_n984_ $abc$8517$new_n548_ $abc$8517$new_n991_ +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +110000 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n996_ $abc$8517$new_n997_ $abc$8517$new_n995_ $abc$8517$new_n993_ $abc$8517$new_n803_ $abc$8517$new_n819_ $abc$8517$new_n992_ +100000 1 +100010 1 +100011 1 +.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n994_ $abc$8517$new_n910_ $abc$8517$new_n957_ $abc$8517$new_n362_ $abc$8517$new_n993_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110011 1 +110100 1 +110101 1 +110111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n519_ $abc$8517$new_n977_ $abc$8517$new_n434_ $abc$8517$new_n432_ $abc$8517$new_n994_ +100100 1 +100101 1 +100110 1 +100111 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n310_ $abc$8517$new_n434_ $abc$8517$new_n576_ rs2_data[31] $abc$8517$new_n494_ $abc$8517$new_n547_ $abc$8517$new_n995_ +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010001 1 +010101 1 +011000 1 +011001 1 +011100 1 +011101 1 +100001 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110101 1 +110111 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n434_ $abc$8517$new_n579_ $abc$8517$new_n310_ $abc$8517$new_n568_ $abc$8517$new_n494_ rs2_data[31] $abc$8517$new_n996_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010010 1 +010011 1 +011000 1 +011010 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n690_ $abc$8517$new_n608_ $abc$8517$new_n549_ $abc$8517$new_n997_ +1111 1 +.names singlecycle_datapath.program_counter.value[0] reset $abc$8517$new_n1013_ $abc$8517$new_n1011_ $abc$8517$new_n999_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] +00000 1 +00001 1 +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n302_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1009_ $abc$8517$new_n999_ +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names $abc$8517$new_n1001_ $abc$8517$new_n983_ bus_address[29] bus_address[28] $abc$8517$new_n981_ $abc$8517$new_n546_ $abc$8517$new_n1000_ +110000 1 +110001 1 +110010 1 +.names $abc$8517$new_n1396_ $abc$8517$new_n1002_ $abc$8517$new_n950_ bus_address[26] bus_address[25] $abc$8517$new_n1001_ +11000 1 +.names $abc$8517$new_n1003_ $abc$8517$new_n1007_ bus_address[21] bus_address[24] bus_address[23] bus_address[22] $abc$8517$new_n1002_ +110000 1 +.names $abc$8517$new_n1004_ bus_address[11] bus_address[14] bus_address[16] bus_address[20] $abc$8517$new_n1003_ +10000 1 +.names $abc$8517$new_n1005_ $abc$8517$new_n1006_ bus_address[9] bus_address[10] $abc$8517$new_n1004_ +1100 1 +.names $abc$8517$new_n1352_ $abc$8517$new_n1349_ bus_address[1] $abc$8517$new_n1344_ $abc$8517$new_n466_ $abc$8517$new_n493_ $abc$8517$new_n1005_ +100000 1 +100001 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +.names bus_address[2] bus_address[8] bus_address[7] bus_address[5] bus_address[4] bus_address[3] $abc$8517$new_n1006_ +000000 1 +.names $abc$8517$new_n1008_ bus_address[12] bus_address[19] $abc$8517$new_n1007_ +100 1 +.names bus_address[6] bus_address[13] bus_address[15] bus_address[18] bus_address[17] $abc$8517$new_n1008_ +00000 1 +.names inst[6] inst[5] $abc$8517$new_n348_ inst[4] $abc$8517$new_n1009_ +1110 1 +.names inst[12] inst[13] inst[14] $abc$8517$new_n1010_ +100 1 +101 1 +111 1 +.names $abc$8517$new_n1012_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1009_ $abc$8517$new_n1011_ +00000 1 +00010 1 +00100 1 +00101 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01110 1 +01111 1 +.names inst[3] $abc$8517$new_n302_ $abc$8517$new_n1012_ +11 1 +.names $abc$8517$new_n355_ $abc$8517$new_n354_ $abc$8517$new_n1013_ +00 1 +.names reset $abc$8517$new_n1015_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n999_ $abc$8517$new_n1017_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[1] $abc$8517$new_n1015_ +11 1 +.names $abc$8517$new_n302_ inst[3] $abc$8517$new_n1016_ +10 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.program_counter.value[0] $abc$8517$new_n358_ $abc$8517$new_n357_ $abc$8517$new_n1013_ $abc$8517$new_n1017_ +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01011 1 +01101 1 +01111 1 +10000 1 +10001 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names reset $abc$8517$new_n1019_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n999_ $abc$8517$new_n1020_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] +000010 1 +000100 1 +000101 1 +000110 1 +000111 1 +001010 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[2] $abc$8517$new_n1019_ +11 1 +.names singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1020_ +001 1 +010 1 +100 1 +111 1 +.names inst[9] $abc$8517$new_n346_ inst[22] $abc$8517$new_n347_ $abc$8517$new_n1021_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names $abc$8517$new_n358_ $abc$8517$new_n357_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n354_ $abc$8517$new_n355_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n1022_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010100 1 +010110 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +.names reset $abc$8517$new_n1024_ $abc$8517$new_n1028_ $abc$8517$new_n999_ $abc$8517$new_n1025_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[3] $abc$8517$new_n1024_ +11 1 +.names singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1025_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1022_ singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1021_ $abc$8517$new_n1026_ +001 1 +100 1 +101 1 +111 1 +.names $abc$8517$new_n360_ $abc$8517$new_n347_ inst[23] $abc$8517$new_n1027_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1028_ +01 1 +10 1 +.names reset $abc$8517$new_n1030_ $abc$8517$new_n1033_ $abc$8517$new_n999_ $abc$8517$new_n1031_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[4] $abc$8517$new_n1030_ +11 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ singlecycle_datapath.program_counter.value[3] $abc$8517$new_n1027_ $abc$8517$new_n1026_ $abc$8517$new_n1031_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[11] $abc$8517$new_n346_ inst[24] $abc$8517$new_n347_ $abc$8517$new_n1032_ +0000 1 +0001 1 +0011 1 +0100 1 +0101 1 +0111 1 +1100 1 +1101 1 +1111 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1033_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1035_ $abc$8517$new_n1042_ $abc$8517$new_n999_ $abc$8517$new_n1036_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[5] $abc$8517$new_n1035_ +11 1 +.names $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1036_ +00 1 +11 1 +.names $abc$8517$new_n1039_ $abc$8517$new_n1038_ $abc$8517$new_n1037_ +00 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n1032_ $abc$8517$new_n1038_ +10 1 +.names $abc$8517$new_n1040_ singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1022_ $abc$8517$new_n1021_ $abc$8517$new_n1027_ $abc$8517$new_n1039_ +100000 1 +101000 1 +101010 1 +101100 1 +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[4] $abc$8517$new_n347_ inst[24] inst[11] $abc$8517$new_n1040_ +0010 1 +0011 1 +0101 1 +0111 1 +1000 1 +1001 1 +1100 1 +1101 1 +1110 1 +.names singlecycle_datapath.program_counter.value[5] inst[25] $abc$8517$new_n324_ $abc$8517$new_n1041_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1042_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1044_ $abc$8517$new_n1048_ $abc$8517$new_n999_ $abc$8517$new_n1045_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[6] $abc$8517$new_n1044_ +11 1 +.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ $abc$8517$new_n1041_ $abc$8517$new_n1037_ $abc$8517$new_n1045_ +0010 1 +0100 1 +0101 1 +0110 1 +0111 1 +1000 1 +1001 1 +1011 1 +.names inst[25] singlecycle_datapath.program_counter.value[5] $abc$8517$new_n324_ $abc$8517$new_n1046_ +110 1 +.names singlecycle_datapath.program_counter.value[6] inst[26] $abc$8517$new_n324_ $abc$8517$new_n1047_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1048_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1050_ $abc$8517$new_n1054_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[7] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1051_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1050_ +100001 1 +100011 1 +100101 1 +100111 1 +101001 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110110 1 +110111 1 +111001 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1051_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1047_ $abc$8517$new_n1046_ singlecycle_datapath.program_counter.value[6] $abc$8517$new_n1041_ $abc$8517$new_n1038_ $abc$8517$new_n1039_ $abc$8517$new_n1052_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1054_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1056_ $abc$8517$new_n1060_ $abc$8517$new_n999_ $abc$8517$new_n1057_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[8] $abc$8517$new_n1056_ +11 1 +.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1057_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ $abc$8517$new_n1052_ $abc$8517$new_n1058_ +000 1 +001 1 +011 1 +101 1 +.names inst[28] $abc$8517$new_n324_ $abc$8517$new_n1059_ +10 1 +.names singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1060_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.program_counter.value[6] singlecycle_datapath.program_counter.value[5] singlecycle_datapath.program_counter.value[4] singlecycle_datapath.program_counter.value[3] singlecycle_datapath.program_counter.value[2] $abc$8517$new_n1061_ +111111 1 +.names reset $abc$8517$new_n1063_ $abc$8517$new_n1067_ $abc$8517$new_n999_ $abc$8517$new_n1064_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[9] $abc$8517$new_n1063_ +11 1 +.names $abc$8517$new_n1066_ $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1058_ $abc$8517$new_n1064_ +00000 1 +00001 1 +00011 1 +00101 1 +01010 1 +01100 1 +01110 1 +01111 1 +10010 1 +10100 1 +10110 1 +10111 1 +11010 1 +11100 1 +11110 1 +11111 1 +.names inst[29] singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ $abc$8517$new_n1065_ +110 1 +.names singlecycle_datapath.program_counter.value[9] $abc$8517$new_n324_ inst[29] $abc$8517$new_n1066_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1067_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1069_ $abc$8517$new_n1073_ $abc$8517$new_n999_ $abc$8517$new_n1070_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[10] $abc$8517$new_n1069_ +11 1 +.names $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1070_ +000 1 +101 1 +110 1 +111 1 +.names $abc$8517$new_n1065_ singlecycle_datapath.program_counter.value[7] $abc$8517$new_n699_ singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1059_ $abc$8517$new_n1052_ $abc$8517$new_n1071_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +001000 1 +001001 1 +001011 1 +001101 1 +010000 1 +010001 1 +010011 1 +010101 1 +011000 1 +011001 1 +.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1072_ +010 1 +100 1 +101 1 +111 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1073_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1075_ $abc$8517$new_n1079_ $abc$8517$new_n999_ $abc$8517$new_n1016_ bus_address[11] $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1076_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1075_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1078_ $abc$8517$new_n1072_ $abc$8517$new_n1066_ $abc$8517$new_n1071_ $abc$8517$new_n1076_ +000100 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100101 1 +100110 1 +100111 1 +110100 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n390_ $abc$8517$new_n391_ $abc$8517$new_n389_ inst[31] $abc$8517$new_n1077_ +0000 1 +0010 1 +0011 1 +.names singlecycle_datapath.program_counter.value[10] inst[30] $abc$8517$new_n324_ $abc$8517$new_n1078_ +110 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1079_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1081_ $abc$8517$new_n1086_ $abc$8517$new_n999_ $abc$8517$new_n1082_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[12] $abc$8517$new_n1081_ +11 1 +.names singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1084_ $abc$8517$new_n1083_ $abc$8517$new_n1082_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[11] $abc$8517$new_n1077_ $abc$8517$new_n1072_ $abc$8517$new_n1071_ $abc$8517$new_n1066_ $abc$8517$new_n1078_ $abc$8517$new_n1083_ +000001 1 +000011 1 +000101 1 +000111 1 +001000 1 +001001 1 +001011 1 +001101 1 +001111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[12] $abc$8517$new_n1084_ +000 1 +010 1 +011 1 +.names inst[31] $abc$8517$new_n312_ $abc$8517$new_n1085_ +10 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1086_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1091_ $abc$8517$new_n1092_ $abc$8517$new_n999_ $abc$8517$new_n1088_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1088_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1084_ singlecycle_datapath.program_counter.value[12] $abc$8517$new_n1083_ $abc$8517$new_n1089_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n383_ $abc$8517$new_n1085_ $abc$8517$new_n1090_ +00 1 +.names $abc$8517$new_n1016_ bus_address[13] $abc$8517$new_n1091_ +11 1 +.names singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1092_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[11] singlecycle_datapath.program_counter.value[10] singlecycle_datapath.program_counter.value[9] singlecycle_datapath.program_counter.value[8] $abc$8517$new_n1061_ $abc$8517$new_n1093_ +111111 1 +.names reset $abc$8517$new_n1095_ $abc$8517$new_n1098_ $abc$8517$new_n999_ $abc$8517$new_n1096_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[14] $abc$8517$new_n1095_ +11 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1090_ $abc$8517$new_n1089_ $abc$8517$new_n1096_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[14] $abc$8517$new_n1097_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1098_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1106_ $abc$8517$new_n1107_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1100_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1100_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ $abc$8517$new_n1101_ +00 1 +.names $abc$8517$new_n1103_ singlecycle_datapath.program_counter.value[12] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1084_ $abc$8517$new_n1090_ $abc$8517$new_n1083_ $abc$8517$new_n1102_ +100001 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +110000 1 +110001 1 +110101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1103_ +00 1 +11 1 +.names singlecycle_datapath.program_counter.value[14] $abc$8517$new_n1097_ $abc$8517$new_n1104_ +10 1 +.names $abc$8517$new_n378_ $abc$8517$new_n1085_ $abc$8517$new_n1105_ +00 1 +.names $abc$8517$new_n1016_ bus_address[15] $abc$8517$new_n1106_ +11 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1107_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1109_ $abc$8517$new_n1112_ $abc$8517$new_n999_ $abc$8517$new_n1110_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[16] $abc$8517$new_n1109_ +11 1 +.names singlecycle_datapath.program_counter.value[16] $abc$8517$new_n1111_ singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1101_ $abc$8517$new_n1110_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n1085_ $abc$8517$new_n338_ inst[16] $abc$8517$new_n1111_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1112_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1114_ $abc$8517$new_n1118_ $abc$8517$new_n999_ bus_address[17] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1115_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1114_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1115_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1104_ $abc$8517$new_n1102_ singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] $abc$8517$new_n1105_ $abc$8517$new_n1111_ $abc$8517$new_n1116_ +000000 1 +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010010 1 +010011 1 +010101 1 +010111 1 +011011 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101011 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111011 1 +.names $abc$8517$new_n320_ $abc$8517$new_n1085_ $abc$8517$new_n1117_ +00 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1118_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1123_ $abc$8517$new_n1124_ $abc$8517$new_n999_ $abc$8517$new_n1120_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1120_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[17] $abc$8517$new_n1117_ $abc$8517$new_n1116_ $abc$8517$new_n1121_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n317_ $abc$8517$new_n1085_ $abc$8517$new_n1122_ +00 1 +.names $abc$8517$new_n1016_ bus_address[18] $abc$8517$new_n1123_ +11 1 +.names singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1124_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[16] singlecycle_datapath.program_counter.value[15] singlecycle_datapath.program_counter.value[14] singlecycle_datapath.program_counter.value[13] $abc$8517$new_n1093_ $abc$8517$new_n1125_ +111111 1 +.names reset $abc$8517$new_n1129_ $abc$8517$new_n1130_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1127_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1121_ $abc$8517$new_n1127_ +00001 1 +00100 1 +00101 1 +00111 1 +01000 1 +01010 1 +01011 1 +01110 1 +10000 1 +10010 1 +10011 1 +10110 1 +11001 1 +11100 1 +11101 1 +11111 1 +.names $abc$8517$new_n314_ $abc$8517$new_n1085_ $abc$8517$new_n1128_ +00 1 +.names $abc$8517$new_n1016_ bus_address[19] $abc$8517$new_n1129_ +11 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1130_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1132_ $abc$8517$new_n1138_ $abc$8517$new_n999_ $abc$8517$new_n1133_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[20] $abc$8517$new_n1132_ +11 1 +.names singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1133_ +0001 1 +0010 1 +0011 1 +0100 1 +1000 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n1135_ $abc$8517$new_n1117_ singlecycle_datapath.program_counter.value[17] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1122_ $abc$8517$new_n1116_ $abc$8517$new_n1134_ +000001 1 +000010 1 +000011 1 +000111 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +010111 1 +011001 1 +011010 1 +011011 1 +011111 1 +.names singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1128_ $abc$8517$new_n1135_ +10 1 +.names $abc$8517$new_n1128_ singlecycle_datapath.program_counter.value[19] $abc$8517$new_n1136_ +10 1 +.names $abc$8517$new_n334_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1137_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1138_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1140_ $abc$8517$new_n1143_ $abc$8517$new_n999_ $abc$8517$new_n1141_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[21] $abc$8517$new_n1140_ +11 1 +.names singlecycle_datapath.program_counter.value[21] $abc$8517$new_n1142_ singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1137_ $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1141_ +000000 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011101 1 +011110 1 +011111 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101101 1 +101110 1 +101111 1 +110000 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +.names $abc$8517$new_n331_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1142_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1143_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1145_ $abc$8517$new_n1146_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] +000000 1 +000001 1 +000010 1 +000011 1 +000110 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +.names reset bus_address[22] $abc$8517$new_n1016_ $abc$8517$new_n1145_ +000 1 +001 1 +010 1 +.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n414_ $abc$8517$new_n1147_ $abc$8517$new_n1146_ +000 1 +011 1 +101 1 +110 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] $abc$8517$new_n1136_ $abc$8517$new_n1134_ $abc$8517$new_n1137_ $abc$8517$new_n1142_ $abc$8517$new_n1147_ +000000 1 +010000 1 +010010 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100100 1 +100110 1 +101000 1 +101010 1 +101100 1 +101110 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +111000 1 +111001 1 +111010 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.program_counter.value[20] singlecycle_datapath.program_counter.value[19] singlecycle_datapath.program_counter.value[18] $abc$8517$new_n1125_ $abc$8517$new_n1148_ +11111 1 +.names reset $abc$8517$new_n1152_ $abc$8517$new_n1153_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1150_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1150_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n414_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1147_ $abc$8517$new_n1151_ +000 1 +100 1 +101 1 +110 1 +.names $abc$8517$new_n1016_ bus_address[23] $abc$8517$new_n1152_ +11 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1153_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ $abc$8517$new_n1154_ +11 1 +.names reset $abc$8517$new_n1158_ $abc$8517$new_n1159_ $abc$8517$new_n999_ $abc$8517$new_n1156_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ singlecycle_datapath.program_counter.value[23] $abc$8517$new_n427_ $abc$8517$new_n1151_ $abc$8517$new_n1156_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n458_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1157_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[24] $abc$8517$new_n1158_ +11 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1159_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[23] $abc$8517$new_n1154_ $abc$8517$new_n1160_ +11 1 +.names reset $abc$8517$new_n1168_ $abc$8517$new_n1169_ $abc$8517$new_n999_ $abc$8517$new_n1162_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1162_ +001 1 +010 1 +100 1 +111 1 +.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ $abc$8517$new_n1163_ +00 1 +.names $abc$8517$new_n1165_ singlecycle_datapath.program_counter.value[22] singlecycle_datapath.program_counter.value[23] $abc$8517$new_n414_ $abc$8517$new_n427_ $abc$8517$new_n1147_ $abc$8517$new_n1164_ +100001 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +110000 1 +110001 1 +110101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1165_ +00 1 +11 1 +.names singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1157_ $abc$8517$new_n1166_ +10 1 +.names $abc$8517$new_n456_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1167_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[25] $abc$8517$new_n1168_ +11 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1169_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n1173_ $abc$8517$new_n1174_ $abc$8517$new_n999_ $abc$8517$new_n1171_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[26] $abc$8517$new_n1172_ singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1163_ $abc$8517$new_n1171_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n448_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1172_ +000 1 +010 1 +011 1 +.names $abc$8517$new_n1016_ bus_address[26] $abc$8517$new_n1173_ +11 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1174_ +0111 1 +1000 1 +1001 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names reset $abc$8517$new_n1176_ $abc$8517$new_n1180_ $abc$8517$new_n999_ $abc$8517$new_n1177_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[27] $abc$8517$new_n1176_ +11 1 +.names singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1177_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1166_ $abc$8517$new_n1164_ singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] $abc$8517$new_n1167_ $abc$8517$new_n1172_ $abc$8517$new_n1178_ +000000 1 +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010010 1 +010011 1 +010101 1 +010111 1 +011011 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101011 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111011 1 +.names $abc$8517$new_n446_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1179_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1180_ +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names reset $abc$8517$new_n1182_ $abc$8517$new_n1185_ $abc$8517$new_n999_ bus_address[28] $abc$8517$new_n1016_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] +000011 1 +000111 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1183_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1182_ +100001 1 +100011 1 +100101 1 +100111 1 +101001 1 +101011 1 +101101 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110110 1 +110111 1 +111001 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ singlecycle_datapath.program_counter.value[27] $abc$8517$new_n1179_ $abc$8517$new_n1178_ $abc$8517$new_n1183_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names $abc$8517$new_n439_ $abc$8517$new_n324_ inst[31] $abc$8517$new_n1184_ +000 1 +010 1 +011 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1185_ +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names reset $abc$8517$new_n1190_ $abc$8517$new_n1191_ $abc$8517$new_n999_ $abc$8517$new_n1011_ $abc$8517$new_n1187_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] +000000 1 +000100 1 +001000 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1187_ +000 1 +011 1 +101 1 +110 1 +.names $abc$8517$new_n1179_ singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[28] $abc$8517$new_n1184_ $abc$8517$new_n1178_ $abc$8517$new_n1188_ +00001 1 +00010 1 +00011 1 +00111 1 +01010 1 +01011 1 +10000 1 +10001 1 +10010 1 +10011 1 +10110 1 +10111 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[29] $abc$8517$new_n1189_ +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n1016_ bus_address[29] $abc$8517$new_n1190_ +11 1 +.names singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1191_ +01 1 +10 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.program_counter.value[27] singlecycle_datapath.program_counter.value[26] singlecycle_datapath.program_counter.value[25] singlecycle_datapath.program_counter.value[24] $abc$8517$new_n1160_ $abc$8517$new_n1192_ +111111 1 +.names reset $abc$8517$new_n1194_ $abc$8517$new_n1197_ $abc$8517$new_n999_ $abc$8517$new_n1195_ $abc$8517$new_n1011_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] +000010 1 +000110 1 +001010 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1016_ bus_address[30] $abc$8517$new_n1194_ +11 1 +.names singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1189_ $abc$8517$new_n1188_ $abc$8517$new_n1195_ +00001 1 +00010 1 +00011 1 +00111 1 +01000 1 +01100 1 +01101 1 +01110 1 +10000 1 +10100 1 +10101 1 +10110 1 +11001 1 +11010 1 +11011 1 +11111 1 +.names inst[31] $abc$8517$new_n324_ $abc$8517$new_n300_ inst[30] $abc$8517$new_n1196_ +0000 1 +0001 1 +0010 1 +0100 1 +0101 1 +0110 1 +1100 1 +1101 1 +1110 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1197_ +011 1 +100 1 +101 1 +110 1 +.names reset $abc$8517$new_n999_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ $abc$8517$new_n1199_ $abc$8517$new_n1202_ $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] +000001 1 +000010 1 +000011 1 +000101 1 +000110 1 +000111 1 +001001 1 +001010 1 +001011 1 +001101 1 +001110 1 +001111 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1200_ $abc$8517$new_n1009_ $abc$8517$new_n1010_ $abc$8517$new_n1000_ bus_address[31] $abc$8517$new_n1012_ $abc$8517$new_n1199_ +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010101 1 +010110 1 +010111 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names $abc$8517$new_n1201_ $abc$8517$new_n1189_ singlecycle_datapath.program_counter.value[29] singlecycle_datapath.program_counter.value[30] $abc$8517$new_n1196_ $abc$8517$new_n1188_ $abc$8517$new_n1200_ +000001 1 +000010 1 +000011 1 +000111 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +010110 1 +010111 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101100 1 +101101 1 +101110 1 +101111 1 +110100 1 +110101 1 +111000 1 +111100 1 +111101 1 +111110 1 +.names singlecycle_datapath.program_counter.value[31] $abc$8517$new_n494_ $abc$8517$new_n1201_ +00 1 +11 1 +.names $abc$8517$new_n1016_ bus_address[31] $abc$8517$new_n1202_ +11 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.program_counter.value[29] $abc$8517$new_n1192_ $abc$8517$new_n1203_ +111 1 +.names $abc$8517$new_n1005_ inst[13] inst[12] bus_byte_enable[0] +100 1 +101 1 +110 1 +.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[1] +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +.names inst[13] inst[12] bus_address[0] bus_address[1] bus_byte_enable[2] +0001 1 +0101 1 +0110 1 +1000 1 +1001 1 +1010 1 +.names inst[12] bus_address[1] inst[13] bus_address[0] bus_byte_enable[3] +0010 1 +0011 1 +0101 1 +0110 1 +0111 1 +1100 1 +1101 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1209_ bus_address[0] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[0] $abc$8517$new_n302_ rd_data[0] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[24] bus_read_data[8] bus_read_data[16] bus_read_data[0] $abc$8517$new_n1209_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n301_ $abc$8517$new_n300_ inst[5] $abc$8517$new_n1210_ +000 1 +001 1 +011 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1212_ bus_address[1] $abc$8517$new_n1210_ singlecycle_datapath.program_counter.value[1] $abc$8517$new_n302_ rd_data[1] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[25] bus_read_data[9] bus_read_data[17] bus_read_data[1] $abc$8517$new_n1212_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1214_ bus_address[2] $abc$8517$new_n1210_ $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[2] rd_data[2] +000010 1 +000110 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +010010 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110010 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +.names bus_address[1] bus_address[0] bus_read_data[26] bus_read_data[10] bus_read_data[18] bus_read_data[2] $abc$8517$new_n1214_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1216_ bus_address[3] $abc$8517$new_n1210_ $abc$8517$new_n1028_ $abc$8517$new_n302_ rd_data[3] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[27] bus_read_data[11] bus_read_data[19] bus_read_data[3] $abc$8517$new_n1216_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1218_ bus_address[4] $abc$8517$new_n1210_ $abc$8517$new_n1033_ $abc$8517$new_n302_ rd_data[4] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[28] bus_read_data[12] bus_read_data[20] bus_read_data[4] $abc$8517$new_n1218_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1220_ bus_address[5] $abc$8517$new_n1210_ $abc$8517$new_n1042_ $abc$8517$new_n302_ rd_data[5] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[29] bus_read_data[13] bus_read_data[21] bus_read_data[5] $abc$8517$new_n1220_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1222_ bus_address[6] $abc$8517$new_n1210_ $abc$8517$new_n1048_ $abc$8517$new_n302_ rd_data[6] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[30] bus_read_data[14] bus_read_data[22] bus_read_data[6] $abc$8517$new_n1222_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1224_ bus_address[7] $abc$8517$new_n1210_ $abc$8517$new_n1054_ $abc$8517$new_n302_ rd_data[7] +000011 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001111 1 +010011 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111111 1 +.names bus_address[1] bus_address[0] bus_read_data[31] bus_read_data[15] bus_read_data[23] bus_read_data[7] $abc$8517$new_n1224_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n1226_ $abc$8517$new_n1210_ bus_address[8] $abc$8517$new_n1060_ $abc$8517$new_n302_ rd_data[8] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1228_ $abc$8517$new_n1227_ $abc$8517$new_n1226_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names inst[13] inst[12] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1227_ +0000 1 +1100 1 +.names bus_address[1] bus_address[0] bus_read_data[16] bus_read_data[24] bus_read_data[8] $abc$8517$new_n1228_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1230_ $abc$8517$new_n1210_ bus_address[9] $abc$8517$new_n1067_ $abc$8517$new_n302_ rd_data[9] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1231_ $abc$8517$new_n1227_ $abc$8517$new_n1230_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[17] bus_read_data[25] bus_read_data[9] $abc$8517$new_n1231_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1233_ $abc$8517$new_n1210_ bus_address[10] $abc$8517$new_n1073_ $abc$8517$new_n302_ rd_data[10] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1234_ $abc$8517$new_n1227_ $abc$8517$new_n1233_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[18] bus_read_data[26] bus_read_data[10] $abc$8517$new_n1234_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1236_ $abc$8517$new_n1210_ bus_address[11] $abc$8517$new_n1079_ $abc$8517$new_n302_ rd_data[11] +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01011 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n299_ inst[12] inst[13] $abc$8517$new_n1237_ $abc$8517$new_n1227_ $abc$8517$new_n1236_ +10001 1 +10011 1 +10100 1 +10101 1 +10111 1 +11000 1 +11001 1 +11011 1 +11101 1 +11111 1 +.names bus_address[1] bus_address[0] bus_read_data[19] bus_read_data[27] bus_read_data[11] $abc$8517$new_n1237_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1239_ $abc$8517$new_n302_ $abc$8517$new_n1086_ rd_data[12] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n1241_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1240_ $abc$8517$new_n1239_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[20] bus_read_data[28] bus_read_data[12] $abc$8517$new_n1240_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1210_ bus_address[12] $abc$8517$new_n300_ $abc$8517$new_n1084_ $abc$8517$new_n1241_ +0000 1 +0001 1 +0010 1 +0011 1 +1000 1 +1001 1 +1011 1 +1100 1 +1101 1 +1111 1 +.names $abc$8517$new_n1243_ bus_address[13] $abc$8517$new_n1210_ rd_data[13] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1245_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1244_ $abc$8517$new_n1243_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[21] bus_read_data[29] bus_read_data[13] $abc$8517$new_n1244_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1092_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1090_ $abc$8517$new_n1245_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1247_ bus_address[14] $abc$8517$new_n1210_ rd_data[14] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1249_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1248_ $abc$8517$new_n1247_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[22] bus_read_data[30] bus_read_data[14] $abc$8517$new_n1248_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1098_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1097_ $abc$8517$new_n1249_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1251_ bus_address[15] $abc$8517$new_n1210_ rd_data[15] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1253_ $abc$8517$new_n1227_ inst[12] inst[13] $abc$8517$new_n299_ $abc$8517$new_n1252_ $abc$8517$new_n1251_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110100 1 +110101 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names bus_address[1] bus_address[0] bus_read_data[23] bus_read_data[31] bus_read_data[15] $abc$8517$new_n1252_ +00000 1 +00010 1 +00100 1 +00110 1 +01000 1 +01001 1 +01010 1 +01011 1 +10000 1 +10001 1 +10100 1 +10101 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1107_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1105_ $abc$8517$new_n1253_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1255_ bus_address[16] $abc$8517$new_n1210_ rd_data[16] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1256_ $abc$8517$new_n302_ $abc$8517$new_n1112_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1111_ $abc$8517$new_n1255_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[24] bus_read_data[16] $abc$8517$new_n1256_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names inst[12] inst[13] inst[14] $abc$8517$new_n1224_ $abc$8517$new_n1252_ $abc$8517$new_n1257_ +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10001 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names inst[13] inst[12] bus_address[1] $abc$8517$new_n1258_ +100 1 +.names $abc$8517$new_n1260_ $abc$8517$new_n302_ $abc$8517$new_n1118_ rd_data[17] +000 1 +001 1 +010 1 +011 1 +111 1 +.names $abc$8517$new_n1261_ bus_address[17] $abc$8517$new_n1210_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1117_ $abc$8517$new_n1260_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[25] bus_read_data[17] $abc$8517$new_n1261_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1263_ bus_address[18] $abc$8517$new_n1210_ rd_data[18] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1264_ $abc$8517$new_n302_ $abc$8517$new_n1124_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1122_ $abc$8517$new_n1263_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[26] bus_read_data[18] $abc$8517$new_n1264_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1266_ bus_address[19] $abc$8517$new_n1210_ rd_data[19] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1267_ $abc$8517$new_n302_ $abc$8517$new_n1130_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1128_ $abc$8517$new_n1266_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[27] bus_read_data[19] $abc$8517$new_n1267_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1269_ bus_address[20] $abc$8517$new_n1210_ rd_data[20] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1270_ $abc$8517$new_n302_ $abc$8517$new_n1138_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1137_ $abc$8517$new_n1269_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[28] bus_read_data[20] $abc$8517$new_n1270_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1272_ bus_address[21] $abc$8517$new_n1210_ rd_data[21] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1273_ $abc$8517$new_n302_ $abc$8517$new_n1143_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1142_ $abc$8517$new_n1272_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[29] bus_read_data[21] $abc$8517$new_n1273_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1276_ $abc$8517$new_n1275_ bus_address[22] $abc$8517$new_n1210_ rd_data[22] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[30] bus_read_data[22] $abc$8517$new_n1275_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[22] $abc$8517$new_n1148_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n414_ $abc$8517$new_n1276_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names $abc$8517$new_n1278_ bus_address[23] $abc$8517$new_n1210_ rd_data[23] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1279_ $abc$8517$new_n302_ $abc$8517$new_n1153_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n427_ $abc$8517$new_n1278_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1257_ bus_read_data[31] bus_read_data[23] $abc$8517$new_n1279_ +100000 1 +100001 1 +100010 1 +100011 1 +101000 1 +101001 1 +101010 1 +101011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1281_ bus_address[24] $abc$8517$new_n1210_ rd_data[24] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1283_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[24] $abc$8517$new_n1281_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1258_ bus_address[0] $abc$8517$new_n1282_ +10 1 +.names $abc$8517$new_n1159_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1157_ $abc$8517$new_n1283_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1285_ bus_address[25] $abc$8517$new_n1210_ rd_data[25] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1286_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[25] $abc$8517$new_n1285_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1169_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1167_ $abc$8517$new_n1286_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1288_ bus_address[26] $abc$8517$new_n1210_ rd_data[26] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1289_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[26] $abc$8517$new_n1288_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1174_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1172_ $abc$8517$new_n1289_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1291_ bus_address[27] $abc$8517$new_n1210_ rd_data[27] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1292_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[27] $abc$8517$new_n1291_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1180_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1179_ $abc$8517$new_n1292_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1294_ bus_address[28] $abc$8517$new_n1210_ rd_data[28] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1295_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[28] $abc$8517$new_n1294_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1185_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1184_ $abc$8517$new_n1295_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1297_ bus_address[29] $abc$8517$new_n1210_ rd_data[29] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1298_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[29] $abc$8517$new_n1297_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1191_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1189_ $abc$8517$new_n1298_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1300_ bus_address[30] $abc$8517$new_n1210_ rd_data[30] +000 1 +001 1 +010 1 +011 1 +110 1 +.names $abc$8517$new_n1301_ $abc$8517$new_n1257_ $abc$8517$new_n299_ $abc$8517$new_n1282_ bus_read_data[30] $abc$8517$new_n1300_ +10000 1 +10001 1 +10010 1 +10011 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n1197_ $abc$8517$new_n302_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n1196_ $abc$8517$new_n1301_ +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01111 1 +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10111 1 +.names $abc$8517$new_n1304_ $abc$8517$new_n1303_ bus_address[31] $abc$8517$new_n1210_ rd_data[31] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1010 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1257_ bus_read_data[31] $abc$8517$new_n1282_ $abc$8517$new_n1303_ +1000 1 +1001 1 +1010 1 +1011 1 +1111 1 +.names $abc$8517$new_n302_ singlecycle_datapath.program_counter.value[31] $abc$8517$new_n1203_ inst[5] $abc$8517$new_n300_ $abc$8517$new_n494_ $abc$8517$new_n1304_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111111 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1009_ $abc$8517$new_n348_ $abc$8517$new_n1307_ $abc$8517$new_n1306_ inst[3] bus_write_enable +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +.names inst[2] $abc$8517$new_n313_ $abc$8517$new_n1306_ +11 1 +.names inst[6] inst[5] inst[4] $abc$8517$new_n1307_ +000 1 +.names $abc$8517$new_n299_ $abc$8517$new_n1306_ $abc$8517$new_n346_ $abc$8517$new_n1310_ bus_read_enable +1010 1 +1011 1 +1100 1 +1110 1 +.names inst[3] $abc$8517$new_n1307_ $abc$8517$new_n1310_ +11 1 +.names rs2_data[0] $abc$8517$new_n1005_ bus_write_data[0] +11 1 +.names rs2_data[1] $abc$8517$new_n1005_ bus_write_data[1] +11 1 +.names rs2_data[2] $abc$8517$new_n1005_ bus_write_data[2] +11 1 +.names rs2_data[3] $abc$8517$new_n1005_ bus_write_data[3] +11 1 +.names rs2_data[4] $abc$8517$new_n1005_ bus_write_data[4] +11 1 +.names rs2_data[5] $abc$8517$new_n1005_ bus_write_data[5] +11 1 +.names rs2_data[6] $abc$8517$new_n1005_ bus_write_data[6] +11 1 +.names rs2_data[7] $abc$8517$new_n1005_ bus_write_data[7] +11 1 +.names bus_address[0] bus_address[1] rs2_data[0] rs2_data[8] bus_write_data[8] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[1] rs2_data[9] bus_write_data[9] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[2] rs2_data[10] bus_write_data[10] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[3] rs2_data[11] bus_write_data[11] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[4] rs2_data[12] bus_write_data[12] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[5] rs2_data[13] bus_write_data[13] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[6] rs2_data[14] bus_write_data[14] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[0] bus_address[1] rs2_data[7] rs2_data[15] bus_write_data[15] +0001 1 +0011 1 +1010 1 +1011 1 +.names bus_address[1] bus_address[0] rs2_data[8] rs2_data[0] rs2_data[16] bus_write_data[16] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[9] rs2_data[1] rs2_data[17] bus_write_data[17] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[10] rs2_data[2] rs2_data[18] bus_write_data[18] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[11] rs2_data[3] rs2_data[19] bus_write_data[19] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[12] rs2_data[4] rs2_data[20] bus_write_data[20] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[13] rs2_data[5] rs2_data[21] bus_write_data[21] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[14] rs2_data[6] rs2_data[22] bus_write_data[22] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[15] rs2_data[7] rs2_data[23] bus_write_data[23] +00001 1 +00011 1 +00101 1 +00111 1 +01100 1 +01101 1 +01110 1 +01111 1 +10010 1 +10011 1 +10110 1 +10111 1 +.names bus_address[1] bus_address[0] rs2_data[0] rs2_data[16] rs2_data[8] rs2_data[24] bus_write_data[24] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[1] rs2_data[17] rs2_data[9] rs2_data[25] bus_write_data[25] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[2] rs2_data[18] rs2_data[10] rs2_data[26] bus_write_data[26] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[3] rs2_data[19] rs2_data[11] rs2_data[27] bus_write_data[27] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[4] rs2_data[20] rs2_data[12] rs2_data[28] bus_write_data[28] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[5] rs2_data[21] rs2_data[13] rs2_data[29] bus_write_data[29] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[6] rs2_data[22] rs2_data[14] rs2_data[30] bus_write_data[30] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names bus_address[1] bus_address[0] rs2_data[7] rs2_data[23] rs2_data[15] rs2_data[31] bus_write_data[31] +000001 1 +000011 1 +000101 1 +000111 1 +001001 1 +001011 1 +001101 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100011 1 +100110 1 +100111 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n462_ $abc$8517$new_n444_ $abc$8517$new_n306_ $abc$8517$new_n411_ $abc$8517$new_n454_ $abc$8517$new_n451_ $abc$8517$new_n1343_ +000011 1 +000111 1 +001011 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n433_ $abc$8517$new_n436_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n442_ $abc$8517$new_n1343_ $abc$8517$new_n1344_ +000000 1 +000001 1 +000010 1 +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +010100 1 +010101 1 +010110 1 +010111 1 +.names $abc$8517$new_n310_ rs2_data[19] $abc$8517$new_n314_ inst[31] $abc$8517$new_n312_ $abc$8517$new_n1345_ +00010 1 +00100 1 +00101 1 +00110 1 +00111 1 +01010 1 +01100 1 +01101 1 +01110 1 +01111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n318_ $abc$8517$new_n315_ $abc$8517$new_n423_ $abc$8517$new_n1345_ $abc$8517$new_n335_ $abc$8517$new_n418_ $abc$8517$new_n1346_ +000000 1 +000001 1 +000011 1 +000100 1 +000101 1 +000111 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +100000 1 +100001 1 +100011 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101111 1 +111000 1 +111001 1 +111011 1 +.names $abc$8517$new_n1346_ $abc$8517$new_n413_ $abc$8517$new_n419_ $abc$8517$new_n330_ $abc$8517$new_n329_ $abc$8517$new_n415_ $abc$8517$new_n1347_ +000000 1 +000100 1 +001000 1 +001100 1 +010000 1 +010010 1 +010100 1 +010110 1 +011000 1 +011010 1 +011100 1 +011110 1 +100000 1 +100001 1 +100100 1 +101000 1 +101100 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110110 1 +111000 1 +111010 1 +111100 1 +111110 1 +.names $abc$8517$new_n433_ $abc$8517$new_n461_ $abc$8517$new_n432_ $abc$8517$new_n431_ $abc$8517$new_n411_ $abc$8517$new_n306_ $abc$8517$new_n1348_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +001111 1 +010010 1 +010100 1 +010101 1 +010110 1 +010111 1 +011110 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n495_ $abc$8517$new_n1348_ $abc$8517$new_n493_ $abc$8517$new_n492_ $abc$8517$new_n1349_ +1000 1 +1001 1 +1010 1 +1011 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n479_ $abc$8517$new_n497_ $abc$8517$new_n519_ $abc$8517$new_n353_ $abc$8517$new_n467_ $abc$8517$new_n489_ $abc$8517$new_n1350_ +000000 1 +000001 1 +000010 1 +000011 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +110010 1 +110110 1 +111010 1 +111110 1 +.names $abc$8517$new_n551_ $abc$8517$new_n520_ $abc$8517$new_n368_ $abc$8517$new_n543_ $abc$8517$new_n542_ $abc$8517$new_n362_ $abc$8517$new_n1351_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +.names $abc$8517$new_n1351_ $abc$8517$new_n545_ $abc$8517$new_n486_ $abc$8517$new_n549_ $abc$8517$new_n502_ $abc$8517$new_n1350_ $abc$8517$new_n1352_ +100000 1 +100010 1 +100110 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n573_ $abc$8517$new_n571_ $abc$8517$new_n574_ $abc$8517$new_n572_ $abc$8517$new_n1353_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n575_ $abc$8517$new_n578_ $abc$8517$new_n345_ $abc$8517$new_n554_ $abc$8517$new_n1353_ $abc$8517$new_n549_ bus_address[1] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110111 1 +111011 1 +111111 1 +.names $abc$8517$new_n359_ $abc$8517$new_n548_ $abc$8517$new_n618_ $abc$8517$new_n546_ $abc$8517$new_n616_ $abc$8517$new_n1358_ $abc$8517$new_n1355_ +000001 1 +000011 1 +000111 1 +001001 1 +001011 1 +001111 1 +010001 1 +010011 1 +010111 1 +100001 1 +100011 1 +100101 1 +101001 1 +101011 1 +101101 1 +111001 1 +111011 1 +111101 1 +.names $abc$8517$new_n486_ $abc$8517$new_n497_ $abc$8517$new_n368_ $abc$8517$new_n361_ $abc$8517$new_n479_ $abc$8517$new_n1357_ +00010 1 +00100 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10000 1 +10001 1 +10011 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.names $abc$8517$new_n1357_ $abc$8517$new_n612_ $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n1358_ +10000 1 +10001 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +.names $abc$8517$new_n659_ $abc$8517$new_n547_ $abc$8517$new_n344_ $abc$8517$new_n342_ $abc$8517$new_n576_ $abc$8517$new_n579_ $abc$8517$new_n1359_ +000000 1 +000100 1 +000101 1 +001000 1 +001001 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010010 1 +011100 1 +011101 1 +011110 1 +011111 1 +.names $abc$8517$new_n1359_ $abc$8517$new_n653_ $abc$8517$new_n647_ $abc$8517$new_n646_ $abc$8517$new_n549_ $abc$8517$new_n657_ bus_address[5] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100010 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n543_ $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n682_ $abc$8517$new_n681_ $abc$8517$new_n680_ $abc$8517$new_n1361_ +000100 1 +000101 1 +000110 1 +000111 1 +001100 1 +001101 1 +001110 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011100 1 +011101 1 +011110 1 +011111 1 +100100 1 +100101 1 +100110 1 +100111 1 +101100 1 +101101 1 +101110 1 +101111 1 +110100 1 +110110 1 +111110 1 +111111 1 +.names $abc$8517$new_n1361_ $abc$8517$new_n665_ $abc$8517$new_n368_ $abc$8517$new_n549_ $abc$8517$new_n1365_ $abc$8517$new_n1367_ $abc$8517$new_n1362_ +100000 1 +100001 1 +100010 1 +100011 1 +100101 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +.names $abc$8517$new_n663_ $abc$8517$new_n548_ $abc$8517$new_n664_ $abc$8517$new_n546_ $abc$8517$new_n662_ $abc$8517$new_n1362_ bus_address[6] +000000 1 +000010 1 +000100 1 +000101 1 +000110 1 +001000 1 +001010 1 +001100 1 +001101 1 +001110 1 +010000 1 +010010 1 +010100 1 +010101 1 +010110 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100010 1 +100100 1 +100110 1 +100111 1 +101000 1 +101010 1 +101100 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111010 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n517_ $abc$8517$new_n516_ $abc$8517$new_n507_ $abc$8517$new_n506_ $abc$8517$new_n1364_ +010000 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +.names $abc$8517$new_n1364_ $abc$8517$new_n356_ $abc$8517$new_n505_ $abc$8517$new_n504_ $abc$8517$new_n510_ $abc$8517$new_n509_ $abc$8517$new_n1365_ +000000 1 +000100 1 +001000 1 +001100 1 +100000 1 +100001 1 +100010 1 +100011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n362_ $abc$8517$new_n356_ $abc$8517$new_n512_ $abc$8517$new_n511_ $abc$8517$new_n525_ $abc$8517$new_n524_ $abc$8517$new_n1366_ +010000 1 +010100 1 +011000 1 +011100 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +.names $abc$8517$new_n1366_ $abc$8517$new_n356_ $abc$8517$new_n523_ $abc$8517$new_n522_ $abc$8517$new_n528_ $abc$8517$new_n527_ $abc$8517$new_n1367_ +000000 1 +000100 1 +001000 1 +001100 1 +100000 1 +100001 1 +100010 1 +100011 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n497_ $abc$8517$new_n486_ $abc$8517$new_n399_ $abc$8517$new_n479_ $abc$8517$new_n397_ $abc$8517$new_n489_ $abc$8517$new_n1368_ +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +001110 1 +001111 1 +010000 1 +010001 1 +010100 1 +010101 1 +010110 1 +010111 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +110001 1 +110011 1 +110101 1 +110111 1 +111001 1 +111011 1 +111101 1 +111111 1 +.names $abc$8517$new_n712_ $abc$8517$new_n1368_ $abc$8517$new_n497_ $abc$8517$new_n701_ $abc$8517$new_n548_ $abc$8517$new_n711_ $abc$8517$new_n1369_ +001000 1 +001001 1 +001010 1 +001100 1 +001101 1 +001110 1 +010000 1 +010001 1 +010010 1 +010100 1 +010101 1 +010110 1 +011100 1 +011101 1 +011110 1 +101000 1 +101001 1 +101011 1 +101100 1 +101101 1 +101111 1 +110000 1 +110001 1 +110011 1 +110100 1 +110101 1 +110111 1 +111000 1 +111001 1 +111011 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n571_ $abc$8517$new_n556_ $abc$8517$new_n572_ $abc$8517$new_n557_ $abc$8517$new_n1371_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n724_ $abc$8517$new_n720_ $abc$8517$new_n717_ $abc$8517$new_n549_ $abc$8517$new_n1371_ $abc$8517$new_n345_ $abc$8517$new_n1372_ +100001 1 +100011 1 +100101 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +.names $abc$8517$new_n1372_ $abc$8517$new_n715_ $abc$8517$new_n406_ $abc$8517$new_n714_ $abc$8517$new_n709_ $abc$8517$new_n546_ bus_address[9] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100011 1 +100101 1 +100111 1 +101001 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n620_ $abc$8517$new_n605_ $abc$8517$new_n621_ $abc$8517$new_n606_ $abc$8517$new_n1374_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n754_ $abc$8517$new_n752_ $abc$8517$new_n755_ $abc$8517$new_n756_ $abc$8517$new_n745_ $abc$8517$new_n548_ $abc$8517$new_n1375_ +100000 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101100 1 +101110 1 +.names $abc$8517$new_n1375_ $abc$8517$new_n746_ $abc$8517$new_n1374_ $abc$8517$new_n549_ $abc$8517$new_n1376_ +1000 1 +1001 1 +1010 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n521_ $abc$8517$new_n531_ $abc$8517$new_n1377_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n768_ $abc$8517$new_n772_ $abc$8517$new_n770_ $abc$8517$new_n769_ $abc$8517$new_n711_ $abc$8517$new_n548_ $abc$8517$new_n1378_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101010 1 +101100 1 +101101 1 +101110 1 +110000 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111110 1 +111111 1 +.names $abc$8517$new_n1378_ $abc$8517$new_n763_ $abc$8517$new_n766_ $abc$8517$new_n549_ $abc$8517$new_n543_ $abc$8517$new_n1377_ $abc$8517$new_n1379_ +100000 1 +100001 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n572_ $abc$8517$new_n557_ $abc$8517$new_n556_ $abc$8517$new_n649_ $abc$8517$new_n1380_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n782_ $abc$8517$new_n781_ $abc$8517$new_n777_ $abc$8517$new_n549_ $abc$8517$new_n543_ $abc$8517$new_n1380_ $abc$8517$new_n1381_ +100000 1 +100001 1 +100100 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101110 1 +.names $abc$8517$new_n1381_ $abc$8517$new_n382_ $abc$8517$new_n783_ $abc$8517$new_n775_ $abc$8517$new_n548_ $abc$8517$new_n1382_ +10000 1 +10010 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11100 1 +11110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n345_ $abc$8517$new_n362_ $abc$8517$new_n837_ $abc$8517$new_n838_ $abc$8517$new_n778_ $abc$8517$new_n1383_ +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110010 1 +110100 1 +110110 1 +111000 1 +111001 1 +111100 1 +111101 1 +.names $abc$8517$new_n1383_ $abc$8517$new_n820_ $abc$8517$new_n345_ $abc$8517$new_n840_ $abc$8517$new_n554_ $abc$8517$new_n581_ $abc$8517$new_n1384_ +000100 1 +000101 1 +000110 1 +000111 1 +001110 1 +001111 1 +010100 1 +010101 1 +010110 1 +010111 1 +011110 1 +011111 1 +100100 1 +100101 1 +100110 1 +100111 1 +101110 1 +101111 1 +110100 1 +110110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n820_ $abc$8517$new_n588_ $abc$8517$new_n345_ $abc$8517$new_n734_ $abc$8517$new_n850_ $abc$8517$new_n1385_ +000100 1 +000101 1 +000110 1 +000111 1 +010110 1 +010111 1 +100100 1 +100101 1 +100110 1 +100111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110101 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +.names $abc$8517$new_n853_ $abc$8517$new_n345_ $abc$8517$new_n845_ $abc$8517$new_n1385_ $abc$8517$new_n600_ $abc$8517$new_n583_ $abc$8517$new_n1386_ +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +110100 1 +110110 1 +.names $abc$8517$new_n546_ $abc$8517$new_n843_ $abc$8517$new_n316_ $abc$8517$new_n1386_ bus_address[18] +0000 1 +0010 1 +0100 1 +0110 1 +1000 1 +1010 1 +1011 1 +1100 1 +1101 1 +1110 1 +.names $abc$8517$new_n368_ $abc$8517$new_n543_ $abc$8517$new_n874_ $abc$8517$new_n819_ $abc$8517$new_n634_ $abc$8517$new_n877_ $abc$8517$new_n1388_ +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010001 1 +010011 1 +010101 1 +010111 1 +011001 1 +011011 1 +011101 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101110 1 +101111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111110 1 +111111 1 +.names $abc$8517$new_n1388_ $abc$8517$new_n878_ $abc$8517$new_n879_ $abc$8517$new_n869_ $abc$8517$new_n333_ $abc$8517$new_n548_ $abc$8517$new_n1389_ +110000 1 +110001 1 +110010 1 +110100 1 +110110 1 +110111 1 +.names $abc$8517$new_n413_ $abc$8517$new_n329_ $abc$8517$new_n497_ $abc$8517$new_n552_ $abc$8517$new_n547_ $abc$8517$new_n478_ $abc$8517$new_n1390_ +000000 1 +000010 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +011000 1 +011001 1 +011100 1 +011101 1 +100000 1 +100001 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n1390_ $abc$8517$new_n901_ $abc$8517$new_n897_ $abc$8517$new_n896_ $abc$8517$new_n894_ $abc$8517$new_n811_ bus_address[22] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n345_ $abc$8517$new_n717_ $abc$8517$new_n933_ $abc$8517$new_n543_ $abc$8517$new_n568_ $abc$8517$new_n434_ $abc$8517$new_n1392_ +000000 1 +000001 1 +000011 1 +001000 1 +001001 1 +001011 1 +001100 1 +001101 1 +001111 1 +010000 1 +010001 1 +010011 1 +011000 1 +011001 1 +011011 1 +011100 1 +011101 1 +011111 1 +110000 1 +110001 1 +110010 1 +110011 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n936_ $abc$8517$new_n1392_ $abc$8517$new_n932_ $abc$8517$new_n929_ $abc$8517$new_n546_ $abc$8517$new_n927_ bus_address[25] +000000 1 +000001 1 +000010 1 +000011 1 +000100 1 +000101 1 +000110 1 +000111 1 +001000 1 +001001 1 +001010 1 +001011 1 +001100 1 +001101 1 +001110 1 +001111 1 +010000 1 +010001 1 +010010 1 +010011 1 +010100 1 +010101 1 +010110 1 +010111 1 +011000 1 +011001 1 +011010 1 +011011 1 +011100 1 +011101 1 +011110 1 +011111 1 +100000 1 +100001 1 +100010 1 +100011 1 +100100 1 +100101 1 +100110 1 +100111 1 +101000 1 +101001 1 +101010 1 +101011 1 +101100 1 +101101 1 +101110 1 +101111 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n820_ $abc$8517$new_n368_ $abc$8517$new_n863_ $abc$8517$new_n362_ $abc$8517$new_n612_ $abc$8517$new_n1394_ +10011 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +.names $abc$8517$new_n345_ $abc$8517$new_n748_ $abc$8517$new_n692_ $abc$8517$new_n1394_ $abc$8517$new_n719_ $abc$8517$new_n747_ $abc$8517$new_n1395_ +000000 1 +000001 1 +000010 1 +000011 1 +001000 1 +001001 1 +001010 1 +001011 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100011 1 +100100 1 +100101 1 +100111 1 +.names $abc$8517$new_n959_ $abc$8517$new_n1395_ $abc$8517$new_n956_ $abc$8517$new_n811_ $abc$8517$new_n548_ $abc$8517$new_n952_ $abc$8517$new_n1396_ +110000 1 +110001 1 +110010 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n623_ $abc$8517$new_n620_ $abc$8517$new_n624_ $abc$8517$new_n621_ $abc$8517$new_n1397_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +111000 1 +111001 1 +111010 1 +111011 1 +111100 1 +111101 1 +111110 1 +111111 1 +.names $abc$8517$new_n1355_ $abc$8517$new_n603_ $abc$8517$new_n1397_ $abc$8517$new_n549_ bus_address[3] +0000 1 +0001 1 +0010 1 +0011 1 +0100 1 +0101 1 +0110 1 +0111 1 +1011 1 +1100 1 +1101 1 +1110 1 +1111 1 +.names $abc$8517$new_n368_ $abc$8517$new_n362_ $abc$8517$new_n503_ $abc$8517$new_n521_ $abc$8517$new_n508_ $abc$8517$new_n526_ $abc$8517$new_n1399_ +000000 1 +000010 1 +000100 1 +000110 1 +001000 1 +001010 1 +001100 1 +001110 1 +010000 1 +010001 1 +010010 1 +010011 1 +011000 1 +011001 1 +011010 1 +011011 1 +100000 1 +100001 1 +100100 1 +100101 1 +101000 1 +101001 1 +101100 1 +101101 1 +110000 1 +110001 1 +110010 1 +110011 1 +110100 1 +110101 1 +110110 1 +110111 1 +.names $abc$8517$new_n1369_ $abc$8517$new_n707_ $abc$8517$new_n703_ $abc$8517$new_n1399_ $abc$8517$new_n549_ bus_address[8] +00000 1 +00001 1 +00010 1 +00011 1 +00100 1 +00101 1 +00110 1 +00111 1 +01000 1 +01001 1 +01010 1 +01011 1 +01100 1 +01101 1 +01110 1 +01111 1 +10011 1 +10100 1 +10101 1 +10110 1 +10111 1 +11000 1 +11001 1 +11010 1 +11011 1 +11100 1 +11101 1 +11110 1 +11111 1 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][0] singlecycle_datapath.program_counter.value[0] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][1] singlecycle_datapath.program_counter.value[1] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][2] singlecycle_datapath.program_counter.value[2] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][3] singlecycle_datapath.program_counter.value[3] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][4] singlecycle_datapath.program_counter.value[4] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][5] singlecycle_datapath.program_counter.value[5] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][6] singlecycle_datapath.program_counter.value[6] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][7] singlecycle_datapath.program_counter.value[7] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] singlecycle_datapath.program_counter.value[8] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] singlecycle_datapath.program_counter.value[9] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] singlecycle_datapath.program_counter.value[10] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][11] singlecycle_datapath.program_counter.value[11] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] singlecycle_datapath.program_counter.value[12] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] singlecycle_datapath.program_counter.value[13] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] singlecycle_datapath.program_counter.value[14] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][15] singlecycle_datapath.program_counter.value[15] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][16] singlecycle_datapath.program_counter.value[16] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][17] singlecycle_datapath.program_counter.value[17] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][18] singlecycle_datapath.program_counter.value[18] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][19] singlecycle_datapath.program_counter.value[19] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][20] singlecycle_datapath.program_counter.value[20] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][21] singlecycle_datapath.program_counter.value[21] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][22] singlecycle_datapath.program_counter.value[22] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][23] singlecycle_datapath.program_counter.value[23] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][24] singlecycle_datapath.program_counter.value[24] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][25] singlecycle_datapath.program_counter.value[25] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][26] singlecycle_datapath.program_counter.value[26] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][27] singlecycle_datapath.program_counter.value[27] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][28] singlecycle_datapath.program_counter.value[28] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][29] singlecycle_datapath.program_counter.value[29] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][30] singlecycle_datapath.program_counter.value[30] re clock 2 +.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] singlecycle_datapath.program_counter.value[31] re clock 2 +.names bus_address[0] address[0] +1 1 +.names bus_address[1] address[1] +1 1 +.names bus_address[2] address[2] +1 1 +.names bus_address[3] address[3] +1 1 +.names bus_address[4] address[4] +1 1 +.names bus_address[5] address[5] +1 1 +.names bus_address[6] address[6] +1 1 +.names bus_address[7] address[7] +1 1 +.names bus_address[8] address[8] +1 1 +.names bus_address[9] address[9] +1 1 +.names bus_address[10] address[10] +1 1 +.names bus_address[11] address[11] +1 1 +.names bus_address[12] address[12] +1 1 +.names bus_address[13] address[13] +1 1 +.names bus_address[14] address[14] +1 1 +.names bus_address[15] address[15] +1 1 +.names bus_address[16] address[16] +1 1 +.names bus_address[17] address[17] +1 1 +.names bus_address[18] address[18] +1 1 +.names bus_address[19] address[19] +1 1 +.names bus_address[20] address[20] +1 1 +.names bus_address[21] address[21] +1 1 +.names bus_address[22] address[22] +1 1 +.names bus_address[23] address[23] +1 1 +.names bus_address[24] address[24] +1 1 +.names bus_address[25] address[25] +1 1 +.names bus_address[26] address[26] +1 1 +.names bus_address[27] address[27] +1 1 +.names bus_address[28] address[28] +1 1 +.names bus_address[29] address[29] +1 1 +.names bus_address[30] address[30] +1 1 +.names bus_address[31] address[31] +1 1 +.names $false alu_function[4] +1 1 +.names bus_address[0] data_memory_interface.address[0] +1 1 +.names bus_address[1] data_memory_interface.address[1] +1 1 +.names bus_address[2] data_memory_interface.address[2] +1 1 +.names bus_address[3] data_memory_interface.address[3] +1 1 +.names bus_address[4] data_memory_interface.address[4] +1 1 +.names bus_address[5] data_memory_interface.address[5] +1 1 +.names bus_address[6] data_memory_interface.address[6] +1 1 +.names bus_address[7] data_memory_interface.address[7] +1 1 +.names bus_address[8] data_memory_interface.address[8] +1 1 +.names bus_address[9] data_memory_interface.address[9] +1 1 +.names bus_address[10] data_memory_interface.address[10] +1 1 +.names bus_address[11] data_memory_interface.address[11] +1 1 +.names bus_address[12] data_memory_interface.address[12] +1 1 +.names bus_address[13] data_memory_interface.address[13] +1 1 +.names bus_address[14] data_memory_interface.address[14] +1 1 +.names bus_address[15] data_memory_interface.address[15] +1 1 +.names bus_address[16] data_memory_interface.address[16] +1 1 +.names bus_address[17] data_memory_interface.address[17] +1 1 +.names bus_address[18] data_memory_interface.address[18] +1 1 +.names bus_address[19] data_memory_interface.address[19] +1 1 +.names bus_address[20] data_memory_interface.address[20] +1 1 +.names bus_address[21] data_memory_interface.address[21] +1 1 +.names bus_address[22] data_memory_interface.address[22] +1 1 +.names bus_address[23] data_memory_interface.address[23] +1 1 +.names bus_address[24] data_memory_interface.address[24] +1 1 +.names bus_address[25] data_memory_interface.address[25] +1 1 +.names bus_address[26] data_memory_interface.address[26] +1 1 +.names bus_address[27] data_memory_interface.address[27] +1 1 +.names bus_address[28] data_memory_interface.address[28] +1 1 +.names bus_address[29] data_memory_interface.address[29] +1 1 +.names bus_address[30] data_memory_interface.address[30] +1 1 +.names bus_address[31] data_memory_interface.address[31] +1 1 +.names bus_address[0] data_memory_interface.bus_address[0] +1 1 +.names bus_address[1] data_memory_interface.bus_address[1] +1 1 +.names bus_address[2] data_memory_interface.bus_address[2] +1 1 +.names bus_address[3] data_memory_interface.bus_address[3] +1 1 +.names bus_address[4] data_memory_interface.bus_address[4] +1 1 +.names bus_address[5] data_memory_interface.bus_address[5] +1 1 +.names bus_address[6] data_memory_interface.bus_address[6] +1 1 +.names bus_address[7] data_memory_interface.bus_address[7] +1 1 +.names bus_address[8] data_memory_interface.bus_address[8] +1 1 +.names bus_address[9] data_memory_interface.bus_address[9] +1 1 +.names bus_address[10] data_memory_interface.bus_address[10] +1 1 +.names bus_address[11] data_memory_interface.bus_address[11] +1 1 +.names bus_address[12] data_memory_interface.bus_address[12] +1 1 +.names bus_address[13] data_memory_interface.bus_address[13] +1 1 +.names bus_address[14] data_memory_interface.bus_address[14] +1 1 +.names bus_address[15] data_memory_interface.bus_address[15] +1 1 +.names bus_address[16] data_memory_interface.bus_address[16] +1 1 +.names bus_address[17] data_memory_interface.bus_address[17] +1 1 +.names bus_address[18] data_memory_interface.bus_address[18] +1 1 +.names bus_address[19] data_memory_interface.bus_address[19] +1 1 +.names bus_address[20] data_memory_interface.bus_address[20] +1 1 +.names bus_address[21] data_memory_interface.bus_address[21] +1 1 +.names bus_address[22] data_memory_interface.bus_address[22] +1 1 +.names bus_address[23] data_memory_interface.bus_address[23] +1 1 +.names bus_address[24] data_memory_interface.bus_address[24] +1 1 +.names bus_address[25] data_memory_interface.bus_address[25] +1 1 +.names bus_address[26] data_memory_interface.bus_address[26] +1 1 +.names bus_address[27] data_memory_interface.bus_address[27] +1 1 +.names bus_address[28] data_memory_interface.bus_address[28] +1 1 +.names bus_address[29] data_memory_interface.bus_address[29] +1 1 +.names bus_address[30] data_memory_interface.bus_address[30] +1 1 +.names bus_address[31] data_memory_interface.bus_address[31] +1 1 +.names bus_byte_enable[0] data_memory_interface.bus_byte_enable[0] +1 1 +.names bus_byte_enable[1] data_memory_interface.bus_byte_enable[1] +1 1 +.names bus_byte_enable[2] data_memory_interface.bus_byte_enable[2] +1 1 +.names bus_byte_enable[3] data_memory_interface.bus_byte_enable[3] +1 1 +.names bus_read_data[0] data_memory_interface.bus_read_data[0] +1 1 +.names bus_read_data[1] data_memory_interface.bus_read_data[1] +1 1 +.names bus_read_data[2] data_memory_interface.bus_read_data[2] +1 1 +.names bus_read_data[3] data_memory_interface.bus_read_data[3] +1 1 +.names bus_read_data[4] data_memory_interface.bus_read_data[4] +1 1 +.names bus_read_data[5] data_memory_interface.bus_read_data[5] +1 1 +.names bus_read_data[6] data_memory_interface.bus_read_data[6] +1 1 +.names bus_read_data[7] data_memory_interface.bus_read_data[7] +1 1 +.names bus_read_data[8] data_memory_interface.bus_read_data[8] +1 1 +.names bus_read_data[9] data_memory_interface.bus_read_data[9] +1 1 +.names bus_read_data[10] data_memory_interface.bus_read_data[10] +1 1 +.names bus_read_data[11] data_memory_interface.bus_read_data[11] +1 1 +.names bus_read_data[12] data_memory_interface.bus_read_data[12] +1 1 +.names bus_read_data[13] data_memory_interface.bus_read_data[13] +1 1 +.names bus_read_data[14] data_memory_interface.bus_read_data[14] +1 1 +.names bus_read_data[15] data_memory_interface.bus_read_data[15] +1 1 +.names bus_read_data[16] data_memory_interface.bus_read_data[16] +1 1 +.names bus_read_data[17] data_memory_interface.bus_read_data[17] +1 1 +.names bus_read_data[18] data_memory_interface.bus_read_data[18] +1 1 +.names bus_read_data[19] data_memory_interface.bus_read_data[19] +1 1 +.names bus_read_data[20] data_memory_interface.bus_read_data[20] +1 1 +.names bus_read_data[21] data_memory_interface.bus_read_data[21] +1 1 +.names bus_read_data[22] data_memory_interface.bus_read_data[22] +1 1 +.names bus_read_data[23] data_memory_interface.bus_read_data[23] +1 1 +.names bus_read_data[24] data_memory_interface.bus_read_data[24] +1 1 +.names bus_read_data[25] data_memory_interface.bus_read_data[25] +1 1 +.names bus_read_data[26] data_memory_interface.bus_read_data[26] +1 1 +.names bus_read_data[27] data_memory_interface.bus_read_data[27] +1 1 +.names bus_read_data[28] data_memory_interface.bus_read_data[28] +1 1 +.names bus_read_data[29] data_memory_interface.bus_read_data[29] +1 1 +.names bus_read_data[30] data_memory_interface.bus_read_data[30] +1 1 +.names bus_read_data[31] data_memory_interface.bus_read_data[31] +1 1 +.names bus_read_enable data_memory_interface.bus_read_enable +1 1 +.names bus_write_data[0] data_memory_interface.bus_write_data[0] +1 1 +.names bus_write_data[1] data_memory_interface.bus_write_data[1] +1 1 +.names bus_write_data[2] data_memory_interface.bus_write_data[2] +1 1 +.names bus_write_data[3] data_memory_interface.bus_write_data[3] +1 1 +.names bus_write_data[4] data_memory_interface.bus_write_data[4] +1 1 +.names bus_write_data[5] data_memory_interface.bus_write_data[5] +1 1 +.names bus_write_data[6] data_memory_interface.bus_write_data[6] +1 1 +.names bus_write_data[7] data_memory_interface.bus_write_data[7] +1 1 +.names bus_write_data[8] data_memory_interface.bus_write_data[8] +1 1 +.names bus_write_data[9] data_memory_interface.bus_write_data[9] +1 1 +.names bus_write_data[10] data_memory_interface.bus_write_data[10] +1 1 +.names bus_write_data[11] data_memory_interface.bus_write_data[11] +1 1 +.names bus_write_data[12] data_memory_interface.bus_write_data[12] +1 1 +.names bus_write_data[13] data_memory_interface.bus_write_data[13] +1 1 +.names bus_write_data[14] data_memory_interface.bus_write_data[14] +1 1 +.names bus_write_data[15] data_memory_interface.bus_write_data[15] +1 1 +.names bus_write_data[16] data_memory_interface.bus_write_data[16] +1 1 +.names bus_write_data[17] data_memory_interface.bus_write_data[17] +1 1 +.names bus_write_data[18] data_memory_interface.bus_write_data[18] +1 1 +.names bus_write_data[19] data_memory_interface.bus_write_data[19] +1 1 +.names bus_write_data[20] data_memory_interface.bus_write_data[20] +1 1 +.names bus_write_data[21] data_memory_interface.bus_write_data[21] +1 1 +.names bus_write_data[22] data_memory_interface.bus_write_data[22] +1 1 +.names bus_write_data[23] data_memory_interface.bus_write_data[23] +1 1 +.names bus_write_data[24] data_memory_interface.bus_write_data[24] +1 1 +.names bus_write_data[25] data_memory_interface.bus_write_data[25] +1 1 +.names bus_write_data[26] data_memory_interface.bus_write_data[26] +1 1 +.names bus_write_data[27] data_memory_interface.bus_write_data[27] +1 1 +.names bus_write_data[28] data_memory_interface.bus_write_data[28] +1 1 +.names bus_write_data[29] data_memory_interface.bus_write_data[29] +1 1 +.names bus_write_data[30] data_memory_interface.bus_write_data[30] +1 1 +.names bus_write_data[31] data_memory_interface.bus_write_data[31] +1 1 +.names bus_write_enable data_memory_interface.bus_write_enable +1 1 +.names clock data_memory_interface.clock +1 1 +.names inst[12] data_memory_interface.data_format[0] +1 1 +.names inst[13] data_memory_interface.data_format[1] +1 1 +.names inst[14] data_memory_interface.data_format[2] +1 1 +.names bus_read_enable data_memory_interface.read_enable +1 1 +.names rs2_data[0] data_memory_interface.write_data[0] +1 1 +.names rs2_data[1] data_memory_interface.write_data[1] +1 1 +.names rs2_data[2] data_memory_interface.write_data[2] +1 1 +.names rs2_data[3] data_memory_interface.write_data[3] +1 1 +.names rs2_data[4] data_memory_interface.write_data[4] +1 1 +.names rs2_data[5] data_memory_interface.write_data[5] +1 1 +.names rs2_data[6] data_memory_interface.write_data[6] +1 1 +.names rs2_data[7] data_memory_interface.write_data[7] +1 1 +.names rs2_data[8] data_memory_interface.write_data[8] +1 1 +.names rs2_data[9] data_memory_interface.write_data[9] +1 1 +.names rs2_data[10] data_memory_interface.write_data[10] +1 1 +.names rs2_data[11] data_memory_interface.write_data[11] +1 1 +.names rs2_data[12] data_memory_interface.write_data[12] +1 1 +.names rs2_data[13] data_memory_interface.write_data[13] +1 1 +.names rs2_data[14] data_memory_interface.write_data[14] +1 1 +.names rs2_data[15] data_memory_interface.write_data[15] +1 1 +.names rs2_data[16] data_memory_interface.write_data[16] +1 1 +.names rs2_data[17] data_memory_interface.write_data[17] +1 1 +.names rs2_data[18] data_memory_interface.write_data[18] +1 1 +.names rs2_data[19] data_memory_interface.write_data[19] +1 1 +.names rs2_data[20] data_memory_interface.write_data[20] +1 1 +.names rs2_data[21] data_memory_interface.write_data[21] +1 1 +.names rs2_data[22] data_memory_interface.write_data[22] +1 1 +.names rs2_data[23] data_memory_interface.write_data[23] +1 1 +.names rs2_data[24] data_memory_interface.write_data[24] +1 1 +.names rs2_data[25] data_memory_interface.write_data[25] +1 1 +.names rs2_data[26] data_memory_interface.write_data[26] +1 1 +.names rs2_data[27] data_memory_interface.write_data[27] +1 1 +.names rs2_data[28] data_memory_interface.write_data[28] +1 1 +.names rs2_data[29] data_memory_interface.write_data[29] +1 1 +.names rs2_data[30] data_memory_interface.write_data[30] +1 1 +.names rs2_data[31] data_memory_interface.write_data[31] +1 1 +.names bus_write_enable data_memory_interface.write_enable +1 1 +.names inst[12] inst_funct3[0] +1 1 +.names inst[13] inst_funct3[1] +1 1 +.names inst[14] inst_funct3[2] +1 1 +.names inst[25] inst_funct7[0] +1 1 +.names inst[26] inst_funct7[1] +1 1 +.names inst[27] inst_funct7[2] +1 1 +.names inst[28] inst_funct7[3] +1 1 +.names inst[29] inst_funct7[4] +1 1 +.names inst[30] inst_funct7[5] +1 1 +.names inst[31] inst_funct7[6] +1 1 +.names inst[0] inst_opcode[0] +1 1 +.names inst[1] inst_opcode[1] +1 1 +.names inst[2] inst_opcode[2] +1 1 +.names inst[3] inst_opcode[3] +1 1 +.names inst[4] inst_opcode[4] +1 1 +.names inst[5] inst_opcode[5] +1 1 +.names inst[6] inst_opcode[6] +1 1 +.names singlecycle_datapath.program_counter.value[0] pc[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] pc[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] pc[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] pc[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] pc[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] pc[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] pc[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] pc[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] pc[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] pc[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] pc[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] pc[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] pc[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] pc[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] pc[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] pc[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] pc[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] pc[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] pc[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] pc[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] pc[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] pc[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] pc[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] pc[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] pc[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] pc[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] pc[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] pc[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] pc[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] pc[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] pc[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] pc[31] +1 1 +.names $true pc_write_enable +1 1 +.names inst[7] rd_address[0] +1 1 +.names $false rd_address[1] +1 1 +.names $false rd_address[2] +1 1 +.names $false rd_address[3] +1 1 +.names $false rd_address[4] +1 1 +.names bus_read_enable read_enable +1 1 +.names inst[15] rs1_address[0] +1 1 +.names $false rs1_address[1] +1 1 +.names $false rs1_address[2] +1 1 +.names $false rs1_address[3] +1 1 +.names $false rs1_address[4] +1 1 +.names inst[20] rs2_address[0] +1 1 +.names $false rs2_address[1] +1 1 +.names $false rs2_address[2] +1 1 +.names $false rs2_address[3] +1 1 +.names $false rs2_address[4] +1 1 +.names alu_function[0] singlecycle_ctlpath.alu_control.alu_function[0] +1 1 +.names alu_function[1] singlecycle_ctlpath.alu_control.alu_function[1] +1 1 +.names alu_function[2] singlecycle_ctlpath.alu_control.alu_function[2] +1 1 +.names alu_function[3] singlecycle_ctlpath.alu_control.alu_function[3] +1 1 +.names $false singlecycle_ctlpath.alu_control.alu_function[4] +1 1 +.names singlecycle_ctlpath.alu_control.branch_funct[2] singlecycle_ctlpath.alu_control.branch_funct[1] +1 1 +.names inst[12] singlecycle_ctlpath.alu_control.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.alu_control.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.alu_control.inst_funct3[2] +1 1 +.names inst[25] singlecycle_ctlpath.alu_control.inst_funct7[0] +1 1 +.names inst[26] singlecycle_ctlpath.alu_control.inst_funct7[1] +1 1 +.names inst[27] singlecycle_ctlpath.alu_control.inst_funct7[2] +1 1 +.names inst[28] singlecycle_ctlpath.alu_control.inst_funct7[3] +1 1 +.names inst[29] singlecycle_ctlpath.alu_control.inst_funct7[4] +1 1 +.names inst[30] singlecycle_ctlpath.alu_control.inst_funct7[5] +1 1 +.names inst[31] singlecycle_ctlpath.alu_control.inst_funct7[6] +1 1 +.names $false singlecycle_ctlpath.alu_control.op_funct[4] +1 1 +.names $false singlecycle_ctlpath.alu_control.op_imm_funct[4] +1 1 +.names alu_function[0] singlecycle_ctlpath.alu_function[0] +1 1 +.names alu_function[1] singlecycle_ctlpath.alu_function[1] +1 1 +.names alu_function[2] singlecycle_ctlpath.alu_function[2] +1 1 +.names alu_function[3] singlecycle_ctlpath.alu_function[3] +1 1 +.names $false singlecycle_ctlpath.alu_function[4] +1 1 +.names inst[12] singlecycle_ctlpath.control_transfer.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.control_transfer.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.control_transfer.inst_funct3[2] +1 1 +.names bus_read_enable singlecycle_ctlpath.data_mem_read_enable +1 1 +.names bus_write_enable singlecycle_ctlpath.data_mem_write_enable +1 1 +.names inst[12] singlecycle_ctlpath.inst_funct3[0] +1 1 +.names inst[13] singlecycle_ctlpath.inst_funct3[1] +1 1 +.names inst[14] singlecycle_ctlpath.inst_funct3[2] +1 1 +.names inst[25] singlecycle_ctlpath.inst_funct7[0] +1 1 +.names inst[26] singlecycle_ctlpath.inst_funct7[1] +1 1 +.names inst[27] singlecycle_ctlpath.inst_funct7[2] +1 1 +.names inst[28] singlecycle_ctlpath.inst_funct7[3] +1 1 +.names inst[29] singlecycle_ctlpath.inst_funct7[4] +1 1 +.names inst[30] singlecycle_ctlpath.inst_funct7[5] +1 1 +.names inst[31] singlecycle_ctlpath.inst_funct7[6] +1 1 +.names inst[0] singlecycle_ctlpath.inst_opcode[0] +1 1 +.names inst[1] singlecycle_ctlpath.inst_opcode[1] +1 1 +.names inst[2] singlecycle_ctlpath.inst_opcode[2] +1 1 +.names inst[3] singlecycle_ctlpath.inst_opcode[3] +1 1 +.names inst[4] singlecycle_ctlpath.inst_opcode[4] +1 1 +.names inst[5] singlecycle_ctlpath.inst_opcode[5] +1 1 +.names inst[6] singlecycle_ctlpath.inst_opcode[6] +1 1 +.names $true singlecycle_ctlpath.pc_write_enable +1 1 +.names $false singlecycle_ctlpath.reg_writeback_select[2] +1 1 +.names regfile_write_enable singlecycle_ctlpath.regfile_write_enable +1 1 +.names bus_read_enable singlecycle_ctlpath.singlecycle_control.data_mem_read_enable +1 1 +.names bus_write_enable singlecycle_ctlpath.singlecycle_control.data_mem_write_enable +1 1 +.names inst[0] singlecycle_ctlpath.singlecycle_control.inst_opcode[0] +1 1 +.names inst[1] singlecycle_ctlpath.singlecycle_control.inst_opcode[1] +1 1 +.names inst[2] singlecycle_ctlpath.singlecycle_control.inst_opcode[2] +1 1 +.names inst[3] singlecycle_ctlpath.singlecycle_control.inst_opcode[3] +1 1 +.names inst[4] singlecycle_ctlpath.singlecycle_control.inst_opcode[4] +1 1 +.names inst[5] singlecycle_ctlpath.singlecycle_control.inst_opcode[5] +1 1 +.names inst[6] singlecycle_ctlpath.singlecycle_control.inst_opcode[6] +1 1 +.names $true singlecycle_ctlpath.singlecycle_control.pc_write_enable +1 1 +.names $false singlecycle_ctlpath.singlecycle_control.reg_writeback_select[2] +1 1 +.names regfile_write_enable singlecycle_ctlpath.singlecycle_control.regfile_write_enable +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[0] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[1] +1 1 +.names $true singlecycle_datapath.adder_pc_plus_4.operand_a[2] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[3] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[4] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[5] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[6] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[7] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[8] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[9] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[10] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[11] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[12] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[13] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[14] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[15] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[16] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[17] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[18] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[19] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[20] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[21] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[22] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[23] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[24] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[25] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[26] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[27] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[28] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[29] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[30] +1 1 +.names $false singlecycle_datapath.adder_pc_plus_4.operand_a[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.operand_b[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.operand_b[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_4.operand_b[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_4.operand_b[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_4.operand_b[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_4.operand_b[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_4.operand_b[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_4.operand_b[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_4.operand_b[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_4.operand_b[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.adder_pc_plus_4.operand_b[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.adder_pc_plus_4.operand_b[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.adder_pc_plus_4.operand_b[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.adder_pc_plus_4.operand_b[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_4.operand_b[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.adder_pc_plus_4.operand_b[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.adder_pc_plus_4.operand_b[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.adder_pc_plus_4.operand_b[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.adder_pc_plus_4.operand_b[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.adder_pc_plus_4.operand_b[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.adder_pc_plus_4.operand_b[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.adder_pc_plus_4.operand_b[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.adder_pc_plus_4.operand_b[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.adder_pc_plus_4.operand_b[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_4.operand_b[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_4.operand_b[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.adder_pc_plus_4.operand_b[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.adder_pc_plus_4.operand_b[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.adder_pc_plus_4.operand_b[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.adder_pc_plus_4.operand_b[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.adder_pc_plus_4.operand_b[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_4.operand_b[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_4.result[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_4.result[1] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.adder_pc_plus_immediate.operand_a[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.adder_pc_plus_immediate.operand_a[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.adder_pc_plus_immediate.operand_a[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.adder_pc_plus_immediate.operand_a[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.adder_pc_plus_immediate.operand_a[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.adder_pc_plus_immediate.operand_a[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.adder_pc_plus_immediate.operand_a[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.adder_pc_plus_immediate.operand_a[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.adder_pc_plus_immediate.operand_a[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.adder_pc_plus_immediate.operand_a[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.adder_pc_plus_immediate.operand_a[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.adder_pc_plus_immediate.operand_a[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.adder_pc_plus_immediate.operand_a[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.adder_pc_plus_immediate.operand_a[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.adder_pc_plus_immediate.operand_a[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.adder_pc_plus_immediate.operand_a[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.adder_pc_plus_immediate.operand_a[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.adder_pc_plus_immediate.operand_a[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.adder_pc_plus_immediate.operand_a[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.adder_pc_plus_immediate.operand_a[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.adder_pc_plus_immediate.operand_a[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.adder_pc_plus_immediate.operand_a[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.adder_pc_plus_immediate.operand_a[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.adder_pc_plus_immediate.operand_a[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.adder_pc_plus_immediate.operand_a[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.adder_pc_plus_immediate.operand_a[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.adder_pc_plus_immediate.operand_a[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.adder_pc_plus_immediate.operand_a[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.adder_pc_plus_immediate.operand_a[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.adder_pc_plus_immediate.operand_a[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.adder_pc_plus_immediate.operand_a[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.adder_pc_plus_immediate.operand_a[31] +1 1 +.names alu_function[0] singlecycle_datapath.alu.alu_function[0] +1 1 +.names alu_function[1] singlecycle_datapath.alu.alu_function[1] +1 1 +.names alu_function[2] singlecycle_datapath.alu.alu_function[2] +1 1 +.names alu_function[3] singlecycle_datapath.alu.alu_function[3] +1 1 +.names $false singlecycle_datapath.alu.alu_function[4] +1 1 +.names bus_address[0] singlecycle_datapath.alu.result[0] +1 1 +.names bus_address[1] singlecycle_datapath.alu.result[1] +1 1 +.names bus_address[2] singlecycle_datapath.alu.result[2] +1 1 +.names bus_address[3] singlecycle_datapath.alu.result[3] +1 1 +.names bus_address[4] singlecycle_datapath.alu.result[4] +1 1 +.names bus_address[5] singlecycle_datapath.alu.result[5] +1 1 +.names bus_address[6] singlecycle_datapath.alu.result[6] +1 1 +.names bus_address[7] singlecycle_datapath.alu.result[7] +1 1 +.names bus_address[8] singlecycle_datapath.alu.result[8] +1 1 +.names bus_address[9] singlecycle_datapath.alu.result[9] +1 1 +.names bus_address[10] singlecycle_datapath.alu.result[10] +1 1 +.names bus_address[11] singlecycle_datapath.alu.result[11] +1 1 +.names bus_address[12] singlecycle_datapath.alu.result[12] +1 1 +.names bus_address[13] singlecycle_datapath.alu.result[13] +1 1 +.names bus_address[14] singlecycle_datapath.alu.result[14] +1 1 +.names bus_address[15] singlecycle_datapath.alu.result[15] +1 1 +.names bus_address[16] singlecycle_datapath.alu.result[16] +1 1 +.names bus_address[17] singlecycle_datapath.alu.result[17] +1 1 +.names bus_address[18] singlecycle_datapath.alu.result[18] +1 1 +.names bus_address[19] singlecycle_datapath.alu.result[19] +1 1 +.names bus_address[20] singlecycle_datapath.alu.result[20] +1 1 +.names bus_address[21] singlecycle_datapath.alu.result[21] +1 1 +.names bus_address[22] singlecycle_datapath.alu.result[22] +1 1 +.names bus_address[23] singlecycle_datapath.alu.result[23] +1 1 +.names bus_address[24] singlecycle_datapath.alu.result[24] +1 1 +.names bus_address[25] singlecycle_datapath.alu.result[25] +1 1 +.names bus_address[26] singlecycle_datapath.alu.result[26] +1 1 +.names bus_address[27] singlecycle_datapath.alu.result[27] +1 1 +.names bus_address[28] singlecycle_datapath.alu.result[28] +1 1 +.names bus_address[29] singlecycle_datapath.alu.result[29] +1 1 +.names bus_address[30] singlecycle_datapath.alu.result[30] +1 1 +.names bus_address[31] singlecycle_datapath.alu.result[31] +1 1 +.names alu_function[0] singlecycle_datapath.alu_function[0] +1 1 +.names alu_function[1] singlecycle_datapath.alu_function[1] +1 1 +.names alu_function[2] singlecycle_datapath.alu_function[2] +1 1 +.names alu_function[3] singlecycle_datapath.alu_function[3] +1 1 +.names $false singlecycle_datapath.alu_function[4] +1 1 +.names bus_address[0] singlecycle_datapath.alu_result[0] +1 1 +.names bus_address[1] singlecycle_datapath.alu_result[1] +1 1 +.names bus_address[2] singlecycle_datapath.alu_result[2] +1 1 +.names bus_address[3] singlecycle_datapath.alu_result[3] +1 1 +.names bus_address[4] singlecycle_datapath.alu_result[4] +1 1 +.names bus_address[5] singlecycle_datapath.alu_result[5] +1 1 +.names bus_address[6] singlecycle_datapath.alu_result[6] +1 1 +.names bus_address[7] singlecycle_datapath.alu_result[7] +1 1 +.names bus_address[8] singlecycle_datapath.alu_result[8] +1 1 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bus_address[8] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][8] +1 1 +.names bus_address[9] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][9] +1 1 +.names bus_address[10] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][10] +1 1 +.names bus_address[11] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][11] +1 1 +.names bus_address[12] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][12] +1 1 +.names bus_address[13] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][13] +1 1 +.names bus_address[14] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][14] +1 1 +.names bus_address[15] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][15] +1 1 +.names bus_address[16] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][16] +1 1 +.names bus_address[17] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][17] +1 1 +.names bus_address[18] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][18] +1 1 +.names bus_address[19] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][19] +1 1 +.names bus_address[20] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][20] +1 1 +.names bus_address[21] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][21] +1 1 +.names bus_address[22] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][22] +1 1 +.names bus_address[23] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][23] +1 1 +.names bus_address[24] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][24] +1 1 +.names bus_address[25] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][25] +1 1 +.names bus_address[26] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][26] +1 1 +.names bus_address[27] singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[2][27] +1 1 +.names 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singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][6] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][7] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][8] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][9] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][10] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][11] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][12] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][13] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][14] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][15] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][16] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][17] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][18] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][19] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][20] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][21] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][22] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][23] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][24] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][25] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][26] +1 1 +.names $false singlecycle_datapath.mux_next_pc_select.multiplexer.input_array[3][27] +1 1 +.names $false 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singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][5] +1 1 +.names rs1_data[6] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][6] +1 1 +.names rs1_data[7] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][7] +1 1 +.names rs1_data[8] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][8] +1 1 +.names rs1_data[9] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][9] +1 1 +.names rs1_data[10] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][10] +1 1 +.names rs1_data[11] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][11] +1 1 +.names rs1_data[12] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][12] +1 1 +.names rs1_data[13] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][13] +1 1 +.names rs1_data[14] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][14] +1 1 +.names rs1_data[15] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][15] +1 1 +.names rs1_data[16] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][16] +1 1 +.names rs1_data[17] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][17] +1 1 +.names rs1_data[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][18] +1 1 +.names rs1_data[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][19] +1 1 +.names rs1_data[20] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][20] +1 1 +.names rs1_data[21] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][21] +1 1 +.names rs1_data[22] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][22] +1 1 +.names rs1_data[23] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][23] +1 1 +.names rs1_data[24] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][24] +1 1 +.names rs1_data[25] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][25] +1 1 +.names rs1_data[26] singlecycle_datapath.mux_operand_a.multiplexer.input_array[0][26] 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singlecycle_datapath.program_counter.value[4] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][19] +1 1 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singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.mux_operand_a.multiplexer.input_array[1][31] +1 1 +.names rs2_data[0] singlecycle_datapath.mux_operand_b.in0[0] +1 1 +.names rs2_data[1] singlecycle_datapath.mux_operand_b.in0[1] +1 1 +.names rs2_data[2] singlecycle_datapath.mux_operand_b.in0[2] +1 1 +.names rs2_data[3] singlecycle_datapath.mux_operand_b.in0[3] +1 1 +.names rs2_data[4] singlecycle_datapath.mux_operand_b.in0[4] +1 1 +.names rs2_data[5] singlecycle_datapath.mux_operand_b.in0[5] +1 1 +.names rs2_data[6] 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rs2_data[16] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][16] +1 1 +.names rs2_data[17] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][17] +1 1 +.names rs2_data[18] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][18] +1 1 +.names rs2_data[19] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][19] +1 1 +.names rs2_data[20] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][20] +1 1 +.names rs2_data[21] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][21] +1 1 +.names rs2_data[22] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][22] +1 1 +.names rs2_data[23] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][23] +1 1 +.names rs2_data[24] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][24] +1 1 +.names rs2_data[25] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][25] +1 1 +.names rs2_data[26] singlecycle_datapath.mux_operand_b.multiplexer.input_array[0][26] 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singlecycle_datapath.pc[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.pc[1] +1 1 +.names singlecycle_datapath.program_counter.value[2] singlecycle_datapath.pc[2] +1 1 +.names singlecycle_datapath.program_counter.value[3] singlecycle_datapath.pc[3] +1 1 +.names singlecycle_datapath.program_counter.value[4] singlecycle_datapath.pc[4] +1 1 +.names singlecycle_datapath.program_counter.value[5] singlecycle_datapath.pc[5] +1 1 +.names singlecycle_datapath.program_counter.value[6] singlecycle_datapath.pc[6] +1 1 +.names singlecycle_datapath.program_counter.value[7] singlecycle_datapath.pc[7] +1 1 +.names singlecycle_datapath.program_counter.value[8] singlecycle_datapath.pc[8] +1 1 +.names singlecycle_datapath.program_counter.value[9] singlecycle_datapath.pc[9] +1 1 +.names singlecycle_datapath.program_counter.value[10] singlecycle_datapath.pc[10] +1 1 +.names singlecycle_datapath.program_counter.value[11] singlecycle_datapath.pc[11] +1 1 +.names singlecycle_datapath.program_counter.value[12] singlecycle_datapath.pc[12] +1 1 +.names singlecycle_datapath.program_counter.value[13] singlecycle_datapath.pc[13] +1 1 +.names singlecycle_datapath.program_counter.value[14] singlecycle_datapath.pc[14] +1 1 +.names singlecycle_datapath.program_counter.value[15] singlecycle_datapath.pc[15] +1 1 +.names singlecycle_datapath.program_counter.value[16] singlecycle_datapath.pc[16] +1 1 +.names singlecycle_datapath.program_counter.value[17] singlecycle_datapath.pc[17] +1 1 +.names singlecycle_datapath.program_counter.value[18] singlecycle_datapath.pc[18] +1 1 +.names singlecycle_datapath.program_counter.value[19] singlecycle_datapath.pc[19] +1 1 +.names singlecycle_datapath.program_counter.value[20] singlecycle_datapath.pc[20] +1 1 +.names singlecycle_datapath.program_counter.value[21] singlecycle_datapath.pc[21] +1 1 +.names singlecycle_datapath.program_counter.value[22] singlecycle_datapath.pc[22] +1 1 +.names singlecycle_datapath.program_counter.value[23] singlecycle_datapath.pc[23] +1 1 +.names singlecycle_datapath.program_counter.value[24] singlecycle_datapath.pc[24] +1 1 +.names singlecycle_datapath.program_counter.value[25] singlecycle_datapath.pc[25] +1 1 +.names singlecycle_datapath.program_counter.value[26] singlecycle_datapath.pc[26] +1 1 +.names singlecycle_datapath.program_counter.value[27] singlecycle_datapath.pc[27] +1 1 +.names singlecycle_datapath.program_counter.value[28] singlecycle_datapath.pc[28] +1 1 +.names singlecycle_datapath.program_counter.value[29] singlecycle_datapath.pc[29] +1 1 +.names singlecycle_datapath.program_counter.value[30] singlecycle_datapath.pc[30] +1 1 +.names singlecycle_datapath.program_counter.value[31] singlecycle_datapath.pc[31] +1 1 +.names singlecycle_datapath.program_counter.value[0] singlecycle_datapath.pc_plus_4[0] +1 1 +.names singlecycle_datapath.program_counter.value[1] singlecycle_datapath.pc_plus_4[1] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[2] singlecycle_datapath.pc_plus_4[2] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[3] singlecycle_datapath.pc_plus_4[3] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[4] singlecycle_datapath.pc_plus_4[4] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[5] singlecycle_datapath.pc_plus_4[5] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[6] singlecycle_datapath.pc_plus_4[6] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[7] singlecycle_datapath.pc_plus_4[7] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[8] singlecycle_datapath.pc_plus_4[8] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[9] singlecycle_datapath.pc_plus_4[9] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[10] singlecycle_datapath.pc_plus_4[10] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[11] singlecycle_datapath.pc_plus_4[11] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[12] singlecycle_datapath.pc_plus_4[12] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[13] singlecycle_datapath.pc_plus_4[13] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[14] singlecycle_datapath.pc_plus_4[14] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[15] singlecycle_datapath.pc_plus_4[15] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[16] singlecycle_datapath.pc_plus_4[16] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[17] singlecycle_datapath.pc_plus_4[17] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[18] singlecycle_datapath.pc_plus_4[18] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[19] singlecycle_datapath.pc_plus_4[19] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[20] singlecycle_datapath.pc_plus_4[20] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[21] singlecycle_datapath.pc_plus_4[21] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[22] singlecycle_datapath.pc_plus_4[22] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[23] singlecycle_datapath.pc_plus_4[23] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[24] singlecycle_datapath.pc_plus_4[24] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[25] singlecycle_datapath.pc_plus_4[25] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[26] singlecycle_datapath.pc_plus_4[26] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[27] singlecycle_datapath.pc_plus_4[27] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[28] singlecycle_datapath.pc_plus_4[28] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[29] singlecycle_datapath.pc_plus_4[29] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[30] singlecycle_datapath.pc_plus_4[30] +1 1 +.names singlecycle_datapath.adder_pc_plus_4.result[31] singlecycle_datapath.pc_plus_4[31] +1 1 +.names $true singlecycle_datapath.pc_write_enable +1 1 +.names clock singlecycle_datapath.program_counter.clock +1 1 +.names reset singlecycle_datapath.program_counter.reset +1 1 +.names $true singlecycle_datapath.program_counter.write_enable +1 1 +.names inst[7] singlecycle_datapath.rd_address[0] +1 1 +.names $false singlecycle_datapath.rd_address[1] +1 1 +.names $false singlecycle_datapath.rd_address[2] +1 1 +.names $false singlecycle_datapath.rd_address[3] +1 1 +.names $false singlecycle_datapath.rd_address[4] +1 1 +.names rd_data[0] singlecycle_datapath.rd_data[0] +1 1 +.names rd_data[1] singlecycle_datapath.rd_data[1] +1 1 +.names rd_data[2] singlecycle_datapath.rd_data[2] +1 1 +.names rd_data[3] singlecycle_datapath.rd_data[3] +1 1 +.names rd_data[4] singlecycle_datapath.rd_data[4] +1 1 +.names rd_data[5] singlecycle_datapath.rd_data[5] +1 1 +.names rd_data[6] singlecycle_datapath.rd_data[6] +1 1 +.names rd_data[7] singlecycle_datapath.rd_data[7] +1 1 +.names rd_data[8] singlecycle_datapath.rd_data[8] +1 1 +.names rd_data[9] singlecycle_datapath.rd_data[9] +1 1 +.names rd_data[10] singlecycle_datapath.rd_data[10] +1 1 +.names rd_data[11] singlecycle_datapath.rd_data[11] +1 1 +.names rd_data[12] singlecycle_datapath.rd_data[12] +1 1 +.names rd_data[13] singlecycle_datapath.rd_data[13] +1 1 +.names rd_data[14] singlecycle_datapath.rd_data[14] +1 1 +.names rd_data[15] singlecycle_datapath.rd_data[15] +1 1 +.names rd_data[16] singlecycle_datapath.rd_data[16] +1 1 +.names rd_data[17] singlecycle_datapath.rd_data[17] +1 1 +.names rd_data[18] singlecycle_datapath.rd_data[18] +1 1 +.names rd_data[19] singlecycle_datapath.rd_data[19] +1 1 +.names rd_data[20] singlecycle_datapath.rd_data[20] +1 1 +.names rd_data[21] singlecycle_datapath.rd_data[21] +1 1 +.names rd_data[22] singlecycle_datapath.rd_data[22] +1 1 +.names rd_data[23] singlecycle_datapath.rd_data[23] +1 1 +.names rd_data[24] singlecycle_datapath.rd_data[24] +1 1 +.names rd_data[25] singlecycle_datapath.rd_data[25] +1 1 +.names rd_data[26] singlecycle_datapath.rd_data[26] +1 1 +.names rd_data[27] singlecycle_datapath.rd_data[27] +1 1 +.names rd_data[28] singlecycle_datapath.rd_data[28] +1 1 +.names rd_data[29] singlecycle_datapath.rd_data[29] +1 1 +.names rd_data[30] singlecycle_datapath.rd_data[30] +1 1 +.names rd_data[31] singlecycle_datapath.rd_data[31] +1 1 +.names $false singlecycle_datapath.reg_writeback_select[2] +1 1 +.names reset singlecycle_datapath.reset +1 1 +.names inst[15] singlecycle_datapath.rs1_address[0] +1 1 +.names $false singlecycle_datapath.rs1_address[1] +1 1 +.names $false singlecycle_datapath.rs1_address[2] +1 1 +.names $false singlecycle_datapath.rs1_address[3] +1 1 +.names $false singlecycle_datapath.rs1_address[4] +1 1 +.names rs1_data[0] singlecycle_datapath.rs1_data[0] +1 1 +.names rs1_data[1] singlecycle_datapath.rs1_data[1] +1 1 +.names rs1_data[2] singlecycle_datapath.rs1_data[2] +1 1 +.names rs1_data[3] singlecycle_datapath.rs1_data[3] +1 1 +.names rs1_data[4] singlecycle_datapath.rs1_data[4] +1 1 +.names rs1_data[5] singlecycle_datapath.rs1_data[5] +1 1 +.names rs1_data[6] singlecycle_datapath.rs1_data[6] +1 1 +.names rs1_data[7] singlecycle_datapath.rs1_data[7] +1 1 +.names rs1_data[8] singlecycle_datapath.rs1_data[8] +1 1 +.names rs1_data[9] singlecycle_datapath.rs1_data[9] +1 1 +.names rs1_data[10] singlecycle_datapath.rs1_data[10] +1 1 +.names rs1_data[11] singlecycle_datapath.rs1_data[11] +1 1 +.names rs1_data[12] singlecycle_datapath.rs1_data[12] +1 1 +.names rs1_data[13] singlecycle_datapath.rs1_data[13] +1 1 +.names rs1_data[14] singlecycle_datapath.rs1_data[14] +1 1 +.names rs1_data[15] singlecycle_datapath.rs1_data[15] +1 1 +.names rs1_data[16] singlecycle_datapath.rs1_data[16] +1 1 +.names rs1_data[17] singlecycle_datapath.rs1_data[17] +1 1 +.names rs1_data[18] singlecycle_datapath.rs1_data[18] +1 1 +.names rs1_data[19] singlecycle_datapath.rs1_data[19] +1 1 +.names rs1_data[20] singlecycle_datapath.rs1_data[20] +1 1 +.names rs1_data[21] singlecycle_datapath.rs1_data[21] +1 1 +.names rs1_data[22] singlecycle_datapath.rs1_data[22] +1 1 +.names rs1_data[23] singlecycle_datapath.rs1_data[23] +1 1 +.names rs1_data[24] singlecycle_datapath.rs1_data[24] +1 1 +.names rs1_data[25] singlecycle_datapath.rs1_data[25] +1 1 +.names rs1_data[26] singlecycle_datapath.rs1_data[26] +1 1 +.names rs1_data[27] singlecycle_datapath.rs1_data[27] +1 1 +.names rs1_data[28] singlecycle_datapath.rs1_data[28] +1 1 +.names rs1_data[29] singlecycle_datapath.rs1_data[29] +1 1 +.names rs1_data[30] singlecycle_datapath.rs1_data[30] +1 1 +.names rs1_data[31] singlecycle_datapath.rs1_data[31] +1 1 +.names inst[20] singlecycle_datapath.rs2_address[0] +1 1 +.names $false singlecycle_datapath.rs2_address[1] +1 1 +.names $false singlecycle_datapath.rs2_address[2] +1 1 +.names $false singlecycle_datapath.rs2_address[3] +1 1 +.names $false singlecycle_datapath.rs2_address[4] +1 1 +.names rs2_data[0] singlecycle_datapath.rs2_data[0] +1 1 +.names rs2_data[1] singlecycle_datapath.rs2_data[1] +1 1 +.names rs2_data[2] singlecycle_datapath.rs2_data[2] +1 1 +.names rs2_data[3] singlecycle_datapath.rs2_data[3] +1 1 +.names rs2_data[4] singlecycle_datapath.rs2_data[4] +1 1 +.names rs2_data[5] singlecycle_datapath.rs2_data[5] +1 1 +.names rs2_data[6] singlecycle_datapath.rs2_data[6] +1 1 +.names rs2_data[7] singlecycle_datapath.rs2_data[7] +1 1 +.names rs2_data[8] singlecycle_datapath.rs2_data[8] +1 1 +.names rs2_data[9] singlecycle_datapath.rs2_data[9] +1 1 +.names rs2_data[10] singlecycle_datapath.rs2_data[10] +1 1 +.names rs2_data[11] singlecycle_datapath.rs2_data[11] +1 1 +.names rs2_data[12] singlecycle_datapath.rs2_data[12] +1 1 +.names rs2_data[13] singlecycle_datapath.rs2_data[13] +1 1 +.names rs2_data[14] singlecycle_datapath.rs2_data[14] +1 1 +.names rs2_data[15] singlecycle_datapath.rs2_data[15] +1 1 +.names rs2_data[16] singlecycle_datapath.rs2_data[16] +1 1 +.names rs2_data[17] singlecycle_datapath.rs2_data[17] +1 1 +.names rs2_data[18] singlecycle_datapath.rs2_data[18] +1 1 +.names rs2_data[19] singlecycle_datapath.rs2_data[19] +1 1 +.names rs2_data[20] singlecycle_datapath.rs2_data[20] +1 1 +.names rs2_data[21] singlecycle_datapath.rs2_data[21] +1 1 +.names rs2_data[22] singlecycle_datapath.rs2_data[22] +1 1 +.names rs2_data[23] singlecycle_datapath.rs2_data[23] +1 1 +.names rs2_data[24] singlecycle_datapath.rs2_data[24] +1 1 +.names rs2_data[25] singlecycle_datapath.rs2_data[25] +1 1 +.names rs2_data[26] singlecycle_datapath.rs2_data[26] +1 1 +.names rs2_data[27] singlecycle_datapath.rs2_data[27] +1 1 +.names rs2_data[28] singlecycle_datapath.rs2_data[28] +1 1 +.names rs2_data[29] singlecycle_datapath.rs2_data[29] +1 1 +.names rs2_data[30] singlecycle_datapath.rs2_data[30] +1 1 +.names rs2_data[31] singlecycle_datapath.rs2_data[31] +1 1 +.names rs2_data[0] write_data[0] +1 1 +.names rs2_data[1] write_data[1] +1 1 +.names rs2_data[2] write_data[2] +1 1 +.names rs2_data[3] write_data[3] +1 1 +.names rs2_data[4] write_data[4] +1 1 +.names rs2_data[5] write_data[5] +1 1 +.names rs2_data[6] write_data[6] +1 1 +.names rs2_data[7] write_data[7] +1 1 +.names rs2_data[8] write_data[8] +1 1 +.names rs2_data[9] write_data[9] +1 1 +.names rs2_data[10] write_data[10] +1 1 +.names rs2_data[11] write_data[11] +1 1 +.names rs2_data[12] write_data[12] +1 1 +.names rs2_data[13] write_data[13] +1 1 +.names rs2_data[14] write_data[14] +1 1 +.names rs2_data[15] write_data[15] +1 1 +.names rs2_data[16] write_data[16] +1 1 +.names rs2_data[17] write_data[17] +1 1 +.names rs2_data[18] write_data[18] +1 1 +.names rs2_data[19] write_data[19] +1 1 +.names rs2_data[20] write_data[20] +1 1 +.names rs2_data[21] write_data[21] +1 1 +.names rs2_data[22] write_data[22] +1 1 +.names rs2_data[23] write_data[23] +1 1 +.names rs2_data[24] write_data[24] +1 1 +.names rs2_data[25] write_data[25] +1 1 +.names rs2_data[26] write_data[26] +1 1 +.names rs2_data[27] write_data[27] +1 1 +.names rs2_data[28] write_data[28] +1 1 +.names rs2_data[29] write_data[29] +1 1 +.names rs2_data[30] write_data[30] +1 1 +.names rs2_data[31] write_data[31] +1 1 +.names bus_write_enable write_enable +1 1 +.end diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt new file mode 100644 index 00000000000..e06768cd4cf --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/config.txt @@ -0,0 +1,31 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/tests + +# Path to directory of architectures to use +archs_dir=arch/timing + +# Add circuits to list to sweep +circuit_list_add=riscv_core_lut6.blif #Contains dangling LUT buffers + +# Add architectures to list to sweep +arch_list_add=k6_frac_N10_40nm.xml + +# Parse info and how to parse +parse_file=vpr_standard.txt + +# How to parse QoR info +qor_parse_file=qor_standard.txt + +# Pass requirements +pass_requirements_file=pass_requirements.txt + +#Script parameters +script_params=-starting_stage vpr -track_memory_usage --pack + +script_params_list_add=--absorb_buffer_luts on +script_params_list_add=--absorb_buffer_luts off diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt new file mode 100644 index 00000000000..54fc8433be0 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -0,0 +1,3 @@ +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 33088 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 32980 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 3c52ef71400..d4ffa0b7bb1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.97 0.02 9300 4 0.13 -1 -1 33000 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25448 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.22 0.04 9516 5 0.14 -1 -1 33248 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.06 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.36 0.05 9344 4 0.16 -1 -1 33048 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25420 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 433 752 1884 183020 26826 1.07788e+06 1.02399e+06 207176. 4228.08 24 2.24005 -174.527 -2.24005 0 0 0.08 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.72 0.05 9596 5 0.12 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 28136 11 30 313 321 2 117 55 7 7 49 clb auto 0.32 380 0.12 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt index 2cb5bad9888..ea2684cd3c4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bidir/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_n4_v7_bidir.xml styr.blif common 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21744 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1261 0.12 5.33383 -68.3994 -5.33383 16 1903 29 2.43e+06 2.01e+06 -1 -1 0.48 1826 16 939 2863 195365 30983 7.17859 -89.6405 -7.17859 0 0 -1 -1 0.06 -k4_n4_v7_longline_bidir.xml styr.blif common 0.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21888 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2324 21 2.43e+06 2.01e+06 -1 -1 0.25 2262 45 1271 3738 304440 42218 8.37849 -101.759 -8.37849 0 0 -1 -1 0.07 -k4_n4_v7_l1_bidir.xml styr.blif common 1.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22404 10 10 253 263 1 169 87 11 11 121 clb auto 0.04 1227 0.12 6.05408 -74.8187 -6.05408 10 1522 37 2.43e+06 2.01e+06 -1 -1 1.07 1214 16 1112 3531 274215 52624 7.44659 -87.7658 -7.44659 0 0 -1 -1 0.05 -k4_n4_v7_bidir_pass_gate.xml styr.blif common 1.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21504 10 10 253 263 1 169 87 11 11 121 clb auto 0.03 1236 0.33 5.30313 -63.535 -5.30313 16 2042 28 2.43e+06 2.01e+06 -1 -1 0.59 1979 19 1142 3366 494089 68283 7.86978 -98.8292 -7.86978 0 0 -1 -1 0.07 +k4_n4_v7_bidir.xml styr.blif common 1.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22008 10 10 253 263 1 169 87 11 11 121 clb auto 0.06 1261 0.20 5.33383 -68.3994 -5.33383 17 1934 35 2.43e+06 2.01e+06 -1 -1 0.75 1937 20 1286 4168 328994 46247 7.85307 -98.3305 -7.85307 0 0 -1 -1 0.11 +k4_n4_v7_longline_bidir.xml styr.blif common 1.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21856 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1211 0.18 6.07334 -70.9644 -6.07334 18 2206 22 2.43e+06 2.01e+06 -1 -1 0.59 2235 28 1635 4962 403273 51999 8.46175 -102.579 -8.46175 0 0 -1 -1 0.12 +k4_n4_v7_l1_bidir.xml styr.blif common 1.97 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22524 10 10 253 263 1 169 87 11 11 121 clb auto 0.07 1227 0.26 6.05408 -74.8187 -6.05408 10 1516 43 2.43e+06 2.01e+06 -1 -1 1.24 1193 18 1215 4020 298127 55249 7.03996 -86.5204 -7.03996 0 0 -1 -1 0.09 +k4_n4_v7_bidir_pass_gate.xml styr.blif common 2.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 67 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21800 10 10 253 263 1 169 87 11 11 121 clb auto 0.05 1236 0.59 5.30313 -63.535 -5.30313 14 2242 44 2.43e+06 2.01e+06 -1 -1 0.93 2224 21 1592 5130 856330 113214 30.5003 -302.812 -30.5003 0 0 -1 -1 0.18 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 802eb7792dc..23c3bbba0e8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 0.97 0.03 9344 4 0.11 -1 -1 33140 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25236 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.09 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.24 0.04 9336 4 0.16 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25204 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.25 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.51 0.04 9340 4 0.17 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25384 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.14 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.21 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.90 0.05 9312 4 0.14 -1 -1 33012 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25696 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 404 0.16 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.55 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 34026948a96..3e8c896e8d9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.55 0.03 9248 4 0.09 -1 -1 33040 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25732 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 395 0.51 2.21922 -172.773 -2.21922 20 659 32 1.07788e+06 1.02399e+06 49980.0 1020.00 0.13 490 19 532 1247 59762 19337 2.76555 -183.23 -2.76555 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 2.48 0.05 9352 4 0.14 -1 -1 33052 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25580 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 395 0.95 2.21922 -172.773 -2.21922 20 670 41 1.07788e+06 1.02399e+06 49980.0 1020.00 0.26 548 21 878 2095 96841 30313 2.52691 -184.979 -2.52691 0 0 65453.8 1335.79 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt index ef4741413f3..de859d8d00d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.84 0.04 9256 4 0.10 -1 -1 33156 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25920 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 392 0.06 2.2162 -164.467 -2.2162 488 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.43079 -179.827 -2.43079 0 0 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.19 0.04 9472 4 0.15 -1 -1 33020 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25812 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 506 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.56012 -181.991 -2.56012 0 0 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index f8b490ba19f..368b2219414 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 0.76 0.00 5876 1 0.01 -1 -1 29900 -1 -1 3 9 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24584 9 8 71 66 1 37 20 5 5 25 clb auto 0.41 85 0.02 2.22275 -22.4732 -2.22275 26 275 17 151211 75605.7 37105.9 1484.24 0.03 181 14 125 161 5553 3001 3.37425 -36.3478 -3.37425 0 0 45067.1 1802.68 0.01 14 16 16 6 0 0 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.29 0.01 6252 1 0.00 -1 -1 30268 -1 -1 8 19 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26792 19 18 299 240 1 150 45 6 6 36 clb auto 1.68 513 0.07 3.94024 -72.8405 -3.94024 66 919 32 403230 201615 140689. 3908.03 0.13 788 16 603 878 36522 13558 4.8522 -103.597 -4.8522 0 0 172795. 4799.85 0.02 62 81 85 13 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.01 5912 1 0.01 -1 -1 29788 -1 -1 3 9 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23852 9 8 71 66 1 37 20 5 5 25 clb auto 0.65 85 0.04 2.22275 -22.4732 -2.22275 26 275 17 151211 75605.7 37105.9 1484.24 0.05 181 14 125 161 5553 3001 3.37425 -36.3478 -3.37425 0 0 45067.1 1802.68 0.01 14 16 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 3.65 0.01 6104 1 0.01 -1 -1 30212 -1 -1 8 19 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 26504 19 18 299 240 1 150 45 6 6 36 clb auto 2.60 513 0.13 3.94024 -72.8405 -3.94024 66 918 26 403230 201615 140689. 3908.03 0.27 783 17 611 899 37480 13874 4.75135 -103.522 -4.75135 0 0 172795. 4799.85 0.03 62 81 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index e6b840828dd..472c1c7a13d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_global_nets num_routed_nets -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.22 0.00 5380 1 0.00 -1 -1 29660 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18580 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 3 3 56 48 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.23 0.00 5380 1 0.01 -1 -1 29768 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18620 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 1 53894 53894 1588.16 176.462 0.00 5 1 3 3 71 58 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 3.10 0.17 48060 2 0.92 -1 -1 51000 -1 -1 155 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 27504 5 156 191 347 1 163 316 15 15 225 clb auto 0.04 22 0.14 1.10064 -11.3943 -1.10064 8 58 10 9.10809e+06 8.35357e+06 130230. 578.801 0.20 45 11 35 41 1194 592 1.16775 -13.0518 -1.16775 0 0 158426. 704.117 0.01 154 9 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 2.96 0.19 48064 2 0.92 -1 -1 50868 -1 -1 155 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 27624 5 156 191 347 1 163 316 15 15 225 clb auto 0.03 25 0.16 1.079 -11.7073 -1.079 12 80 9 9.10809e+06 8.35357e+06 194400. 864.002 0.12 78 5 36 51 4226 1673 1.7756 -16.1044 -1.7756 -3.13612 -0.488149 255657. 1136.26 0.01 153 10 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.26 0.00 5736 1 0.01 -1 -1 29784 -1 -1 1 2 0 0 v8.0.0-rc1-1092-gb22604c1a success 22984 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 3 3 56 48 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.27 0.01 5744 1 0.00 -1 -1 29744 -1 -1 1 2 0 0 v8.0.0-rc1-1092-gb22604c1a success 22716 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 1 53894 53894 1588.16 176.462 0.00 5 1 3 3 71 58 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 8.01 0.07 15940 2 0.07 -1 -1 33480 -1 -1 32 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 57868 311 156 972 1128 1 953 514 28 28 784 memory auto 0.36 7976 1.53 4.26612 -4292.66 -4.26612 40 13615 28 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 3.77 12850 18 2816 3295 4898763 1500574 4.29603 -4929.32 -4.29603 -20.3472 -0.298787 2.55406e+06 3257.73 0.94 15 938 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 7.96 0.10 15892 2 0.11 -1 -1 33504 -1 -1 32 311 15 0 v8.0.0-rc1-1092-gb22604c1a success 58204 311 156 972 1128 1 953 514 28 28 784 memory auto 0.30 8142 1.46 3.96275 -2917.87 -3.96275 40 13931 23 4.25198e+07 9.94461e+06 2.07480e+06 2646.43 3.81 12943 21 3274 3870 4601511 1352718 4.43746 -3526.24 -4.43746 -894.645 -2.58347 2.60581e+06 3323.74 0.90 14 939 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.28 0.00 5408 1 0.00 -1 -1 29736 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18644 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 4 4 87 77 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.28 0.00 5344 1 0.01 -1 -1 29656 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18612 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.524421 -0.946421 -0.524421 2 5 2 53894 53894 1588.16 176.462 0.00 5 2 4 4 114 93 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 4.79 0.27 47992 2 1.47 -1 -1 50904 -1 -1 155 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 27108 5 156 191 347 1 163 316 15 15 225 clb auto 0.06 22 0.27 1.10064 -11.3943 -1.10064 8 58 10 9.10809e+06 8.35357e+06 130230. 578.801 0.28 45 12 37 43 1274 630 1.16775 -13.0518 -1.16775 0 0 158426. 704.117 0.01 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 4.67 0.25 48016 2 1.44 -1 -1 50872 -1 -1 155 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 27236 5 156 191 347 1 163 316 15 15 225 clb auto 0.07 25 0.29 1.079 -11.7073 -1.079 12 81 10 9.10809e+06 8.35357e+06 194400. 864.002 0.21 78 5 36 51 4359 1735 1.7756 -16.1044 -1.7756 -3.13612 -0.488149 255657. 1136.26 0.01 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal 0.34 0.01 5832 1 0.00 -1 -1 29732 -1 -1 1 2 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22900 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.570641 -0.944653 -0.570641 2 3 2 53894 53894 1165.58 129.509 0.00 3 2 4 4 87 77 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route 0.32 0.01 5936 1 0.00 -1 -1 29852 -1 -1 1 2 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22796 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.01 0.524421 -0.946421 -0.524421 2 5 2 53894 53894 1588.16 176.462 0.00 5 2 4 4 114 93 0.7307 -1.06327 -0.7307 -0.155434 -0.155434 1588.16 176.462 0.00 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal 10.02 0.12 15992 2 0.12 -1 -1 33496 -1 -1 32 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 57752 311 156 972 1128 1 953 514 28 28 784 memory auto 0.52 7976 2.61 4.26612 -4292.66 -4.26612 40 13542 15 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 3.95 12829 18 2820 3287 4811709 1472844 4.29603 -4980.64 -4.29603 -21.7586 -0.298787 2.55406e+06 3257.73 0.93 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route 10.30 0.11 15988 2 0.11 -1 -1 33640 -1 -1 32 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 57728 311 156 972 1128 1 953 514 28 28 784 memory auto 0.55 8142 2.69 3.96275 -2917.87 -3.96275 40 13846 26 4.25198e+07 9.94461e+06 2.07480e+06 2646.43 4.15 12969 19 3084 3659 4345349 1258957 4.30407 -3216.46 -4.30407 -770.89 -1.60451 2.60581e+06 3323.74 0.84 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index e3d8437a449..e88a5877964 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 v8.0.0-rc1-1092-gb22604c1a success 22856 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.00 nan 0 0 2 0 1 107788 107788 1342.00 83.8749 0.00 0 1 0 0 0 0 nan 0 0 0 0 1342.00 83.8749 0.00 +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22644 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.01 nan 0 0 2 0 1 107788 107788 1342.00 83.8749 0.02 0 1 0 0 0 0 nan 0 0 0 0 1342.00 83.8749 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index 96218a45873..9fd514ba486 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -fixed_grid.xml raygentop.v common 24.91 0.35 29812 3 1.36 -1 -1 46744 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 111880 214 305 3028 2934 1 1505 639 25 25 625 -1 25x25 2.57 12605 2.19 4.41596 -2612.27 -4.41596 48 28432 36 3.19446e+07 9.20413e+06 1.97188e+06 3155.02 14.81 23059 24 7120 15025 4954028 1103896 4.89193 -3202.77 -4.89193 0 0 2.52596e+06 4041.53 0.66 -column_io.xml raygentop.v common 16.85 0.35 29556 3 1.41 -1 -1 46796 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 113028 214 305 3028 2934 1 1505 639 25 25 625 io auto 2.63 11829 2.17 4.3 -2616.5 -4.3 50 27225 43 2.82259e+07 9.20413e+06 1.88190e+06 3011.03 6.99 21196 20 6960 15110 4318307 929754 4.87311 -3076.36 -4.87311 0 0 2.49714e+06 3995.43 0.55 -multiwidth_blocks.xml raygentop.v common 15.89 0.35 29764 3 1.28 -1 -1 46772 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 113412 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.57 11338 2.14 4.29768 -2529.75 -4.29768 66 23937 41 1.65001e+07 9.20413e+06 1.25644e+06 3480.44 6.48 19907 18 5801 12392 3140521 809560 4.84591 -2938.92 -4.84591 0 0 1.57029e+06 4349.83 0.44 -non_column.xml raygentop.v common 28.72 0.35 30024 3 1.31 -1 -1 46612 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 115204 214 305 3028 2934 1 1505 639 33 33 1089 io auto 2.63 14616 2.58 4.29046 -2635.7 -4.29046 48 30109 32 5.44432e+07 9.20413e+06 3.01743e+06 2770.83 18.05 24186 19 7051 15889 4433148 1071530 4.85023 -3171.88 -4.85023 0 0 3.86350e+06 3547.75 0.60 -non_column_tall_aspect_ratio.xml raygentop.v common 18.45 0.35 30092 3 1.27 -1 -1 46752 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 126732 214 305 3028 2934 1 1505 639 23 46 1058 io auto 2.56 12529 2.48 4.43753 -2639.16 -4.43753 46 26860 43 5.05849e+07 9.20413e+06 2.90934e+06 2749.85 8.06 22146 18 6584 14208 3679631 917195 4.85524 -3103.91 -4.85524 0 0 3.73194e+06 3527.36 0.50 -non_column_wide_aspect_ratio.xml raygentop.v common 17.73 0.35 30204 3 1.35 -1 -1 46760 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 122820 214 305 3028 2934 1 1505 639 43 22 946 io auto 2.63 13897 2.44 4.78236 -2839.4 -4.78236 48 27697 40 4.55909e+07 9.20413e+06 2.64263e+06 2793.48 7.49 23142 16 5802 12647 3201587 806357 5.1351 -3189.92 -5.1351 0 0 3.38205e+06 3575.11 0.45 -custom_sbloc.xml raygentop.v common 13.16 0.34 29628 3 1.37 -1 -1 46616 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 108560 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.59 10900 2.23 4.30764 -2565.02 -4.30764 62 22962 48 1.65001e+07 9.20413e+06 1.15634e+06 3203.15 3.65 18983 18 5723 12136 3238340 813980 5.0112 -2991.61 -5.0112 0 0 1.43990e+06 3988.64 0.45 -multiple_io_types.xml raygentop.v common 54.11 0.35 29904 3 1.39 -1 -1 46736 -1 -1 112 214 0 8 v8.0.0-rc1-915-g337a46c79 success 421956 214 305 3028 2934 1 1505 639 67 67 4489 io_left auto 3.56 39959 9.71 6.08816 -4548.16 -6.08816 44 55781 49 2.48753e+08 9.20413e+06 1.09868e+07 2447.50 31.93 49814 16 7203 15231 8667353 2053508 6.36455 -5098.86 -6.36455 0 0 1.42904e+07 3183.43 1.15 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time +fixed_grid.xml raygentop.v common 25.84 0.31 29664 3 1.52 -1 -1 40360 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 72184 214 305 2964 2870 1 1438 634 25 25 625 -1 25x25 3.17 12875 3.64 4.4701 -2560.95 -4.4701 56 24974 27 3.19446e+07 8.93466e+06 2.27235e+06 3635.76 12.48 22306 18 5829 12928 3763475 891650 4.89048 -2985.86 -4.89048 0 0 2.89946e+06 4639.14 1.30 +column_io.xml raygentop.v common 30.79 0.30 29656 3 1.47 -1 -1 40420 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 75196 214 305 2964 2870 1 1438 634 25 25 625 io auto 3.12 11261 3.33 4.46107 -2506.79 -4.46107 50 26270 36 2.82259e+07 8.93466e+06 1.88190e+06 3011.03 17.84 20904 17 6177 13915 3771135 818422 4.87754 -2920.16 -4.87754 0 0 2.49714e+06 3995.43 1.34 +multiwidth_blocks.xml raygentop.v common 31.76 0.33 29788 3 1.78 -1 -1 40428 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 67884 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.19 10446 3.78 4.42441 -2494.7 -4.42441 68 23181 35 1.65001e+07 8.93466e+06 1.28755e+06 3566.63 18.26 18866 14 5520 12874 4172039 1070780 4.77245 -2886.5 -4.77245 0 0 1.60474e+06 4445.26 1.39 +non_column.xml raygentop.v common 24.18 0.36 30204 3 1.60 -1 -1 40416 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 90400 214 305 2964 2870 1 1438 634 33 33 1089 io auto 3.14 13212 4.09 4.29383 -2619.77 -4.29383 50 28185 27 5.44432e+07 8.93466e+06 3.11799e+06 2863.17 9.53 22797 19 6862 15251 4449583 1089545 5.14569 -3069.09 -5.14569 0 0 4.13529e+06 3797.33 1.50 +non_column_tall_aspect_ratio.xml raygentop.v common 39.22 0.38 30152 3 1.55 -1 -1 40444 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 98128 214 305 2964 2870 1 1438 634 23 46 1058 io auto 3.13 13287 4.13 4.49581 -2567.26 -4.49581 50 25552 23 5.05849e+07 8.93466e+06 3.11839e+06 2947.44 24.98 21898 15 5590 12773 2718112 668692 5.25903 -2987.14 -5.25903 0 0 4.13508e+06 3908.40 1.05 +non_column_wide_aspect_ratio.xml raygentop.v common 41.31 0.38 30232 3 1.56 -1 -1 40360 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 83160 214 305 2964 2870 1 1438 634 43 22 946 io auto 3.16 14109 3.90 4.53087 -2746.94 -4.53087 46 30005 40 4.55909e+07 8.93466e+06 2.54300e+06 2688.17 26.99 24419 24 7023 15864 4574615 1097967 4.99799 -3215.24 -4.99799 0 0 3.26968e+06 3456.32 1.68 +custom_sbloc.xml raygentop.v common 25.36 0.34 29672 3 1.45 -1 -1 40356 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 62944 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.31 10710 3.67 4.29215 -2514.15 -4.29215 62 23655 46 1.65001e+07 8.93466e+06 1.15634e+06 3203.15 12.04 19234 20 6084 13886 3597203 896399 4.84201 -2951.3 -4.84201 0 0 1.43990e+06 3988.64 1.35 +multiple_io_types.xml raygentop.v common 112.14 0.30 29536 3 1.42 -1 -1 40528 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 416268 214 305 2964 2870 1 1438 634 67 67 4489 io_left auto 3.94 37811 16.94 5.77645 -4658.65 -5.77645 50 52755 46 2.48753e+08 8.93466e+06 1.23326e+07 2747.29 82.43 48473 14 6877 15481 6627715 1528770 6.07015 -5121.09 -6.07015 0 0 1.63652e+07 3645.63 1.15 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index ea08b5de124..a02a8e7c371 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 1.52 0.04 8976 3 0.19 -1 -1 36164 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30184 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 648 0.27 1.98044 -205.036 -1.98044 50 1402 13 5.66058e+06 4.05111e+06 423042. 2937.80 0.36 1312 11 576 728 57051 20205 2.49644 -241.033 -2.49644 0 0 561550. 3899.65 0.03 +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 2.10 0.03 9176 3 0.24 -1 -1 36308 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29860 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 648 0.49 1.98044 -205.036 -1.98044 50 1402 13 5.66058e+06 4.05111e+06 423042. 2937.80 0.43 1312 11 576 728 57051 20205 2.49644 -241.033 -2.49644 0 0 561550. 3899.65 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index 86bd5fae5cb..79184563f70 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.18 0.03 8824 4 0.17 -1 -1 33880 -1 -1 75 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 33720 99 130 378 508 1 307 305 15 15 225 memory auto 0.04 867 0.31 1.53958 -153.957 -1.53958 1404 664 1563 256146 64082 1.16234e+06 375248 2.18283e+06 9701.45 11 1.7679 -171.086 -1.7679 -0.0322204 -0.0322204 0.07 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 1.85 0.04 8880 4 0.28 -1 -1 33932 -1 -1 75 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 33336 99 130 378 508 1 307 305 15 15 225 memory auto 0.06 867 0.50 1.53958 -153.957 -1.53958 1404 664 1563 256146 64082 1.16234e+06 375248 2.18283e+06 9701.45 11 1.7679 -171.086 -1.7679 -0.0322204 -0.0322204 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index b9f71e69852..7308c682561 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_global_nets num_routed_nets -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 11.90 0.11 15932 2 0.12 -1 -1 41156 -1 -1 29 311 15 0 v8.0.0-rc1-1400-ge1ff30c2f success 109624 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.62 8049 2.45 4.39014 -3508.77 -4.39014 40 14355 17 4.25198e+07 9.78293e+06 2.15488e+06 2748.57 5.94 13340 14 2575 2984 2890890 864023 4.47512 -4294.11 -4.47512 -229.075 -0.938948 2.69199e+06 3433.66 0.71 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 9.24 0.11 16104 2 0.13 -1 -1 40376 -1 -1 29 311 15 0 v8.0.0-rc1-1400-ge1ff30c2f success 113492 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.63 7956 2.42 4.09743 -3819.07 -4.09743 40 14778 30 4.25198e+07 9.78293e+06 2.18945e+06 2792.66 3.22 13612 18 3210 3663 3242196 933097 4.35038 -5481.7 -4.35038 -262.106 -1.75122 2.74222e+06 3497.72 0.78 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 12.06 0.11 16128 2 0.12 -1 -1 39644 -1 -1 29 311 15 0 v8.0.0-rc1-1400-ge1ff30c2f success 110504 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.63 8049 2.60 4.39014 -3508.77 -4.39014 40 15248 20 4.25198e+07 9.78293e+06 2.15029e+06 2742.71 5.86 14194 13 2606 3050 2855904 921559 4.47512 -4375.09 -4.47512 -146.535 -0.790364 2.68740e+06 3427.80 0.78 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 12.79 0.11 16188 2 0.11 -1 -1 34240 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 65912 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.76 7926 2.69 3.71918 -3791.41 -3.71918 38 14664 22 4.25198e+07 9.78293e+06 2.06134e+06 2629.25 5.78 13215 12 2732 3118 2727378 877873 4.6565 -4338.38 -4.6565 -217.731 -0.937841 2.60756e+06 3325.97 1.23 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.71 0.10 16176 2 0.10 -1 -1 34268 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 65764 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.79 7855 2.67 4.29577 -3815.97 -4.29577 40 14565 31 4.25198e+07 9.78293e+06 2.18945e+06 2792.66 6.37 13336 16 3013 3384 3288699 970769 4.44197 -4744.42 -4.44197 -296.276 -1.26627 2.74222e+06 3497.72 1.46 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.25 0.11 16296 2 0.10 -1 -1 34304 -1 -1 29 311 15 0 v8.0.0-rc1-1194-g64d9b2790 success 66468 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.76 7926 2.70 3.71918 -3791.41 -3.71918 38 15436 16 4.25198e+07 9.78293e+06 2.05675e+06 2623.40 6.15 14101 14 2682 3088 2566936 820999 4.6565 -4410.32 -4.6565 -156.683 -0.791471 2.60298e+06 3320.12 1.27 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index 677e608df28..3e6f00a5572 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 6.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 47932 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.29 10133 1.54 6.77352 -1333.3 -6.77352 24 12220 20 983127 929624 797780. 1508.09 3.07 10949 16 6016 20588 2159891 493894 6.8984 -1445.89 -6.8984 0 0 1.04508e+06 1975.57 0.51 +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 11.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 47732 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.40 10133 2.53 6.77352 -1333.3 -6.77352 24 12541 23 983127 929624 797780. 1508.09 6.43 11441 17 6774 22853 2446188 571128 6.96084 -1500.96 -6.96084 0 0 1.04508e+06 1975.57 0.64 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index 6bf3edd42e8..74a5f0d6399 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 14.66 0.18 29408 4 1.52 -1 -1 39844 -1 -1 167 193 5 0 v8.0.0-rc1-1092-gb22604c1a success 71136 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.32 10711 2.51 4.0362 -2478.27 -4.0362 80 21050 36 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 6.52 19612 16 5228 14998 1697996 377704 4.77524 -2855.18 -4.77524 -7.14113 -0.293253 2.64606e+06 6615.15 0.60 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 30.68 0.28 29452 4 2.32 -1 -1 39812 -1 -1 167 193 5 0 v8.0.0-rc1-1194-g64d9b2790 success 70264 193 205 2926 2852 1 1371 570 20 20 400 memory auto 2.06 10711 4.38 4.0362 -2478.27 -4.0362 76 23027 46 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 18.33 20051 16 5536 15485 1831924 411676 4.70984 -2868.45 -4.70984 -7.09172 -0.292146 2.51807e+06 6295.18 0.56 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 0e654601b04..d6d715660c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.72 0.03 9016 3 0.18 -1 -1 36164 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 29808 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 655 0.42 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.35 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.37 0.04 9064 3 0.28 -1 -1 36168 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29732 99 130 363 493 1 251 295 12 12 144 clb auto 0.15 655 0.51 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.48 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index f801f4edbdd..b6c87f17e76 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml test_eblif.eblif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19196 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 20 9 1 53894 53894 4880.82 542.314 0.00 5 1 3 3 38 28 0.544641 -1.07365 -0.544641 0 0 6579.40 731.044 0.00 -k6_frac_N10_40nm.xml conn_order.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19088 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.709011 -1.25365 -0.709011 20 4 2 53894 53894 4880.82 542.314 0.00 8 1 2 2 36 29 1.17134 -1.71599 -1.17134 0 0 6579.40 731.044 0.00 +k6_frac_N10_40nm.xml test_eblif.eblif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19208 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 20 9 1 53894 53894 4880.82 542.314 0.00 5 1 3 3 38 28 0.544641 -1.07365 -0.544641 0 0 6579.40 731.044 0.00 +k6_frac_N10_40nm.xml conn_order.eblif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18628 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.709011 -1.25365 -0.709011 20 4 2 53894 53894 4880.82 542.314 0.00 8 1 2 2 36 29 1.17134 -1.71599 -1.17134 0 0 6579.40 731.044 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index bd3931e8890..f2e465c68c9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.17 0.06 9248 4 0.12 -1 -1 33044 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25408 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 404 0.10 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.10 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.96 0.04 9312 4 0.14 -1 -1 32968 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25592 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 404 0.19 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.21 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 999794c9784..0518b8e3905 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.33 0.04 9276 4 0.10 -1 -1 33068 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25828 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 414 0.08 2.2252 -166.078 -2.2252 14 572 36 1.07788e+06 1.02399e+06 81563.3 1664.56 0.23 496 17 566 1248 92246 25162 2.83162 -197.755 -2.83162 0 0 98201.7 2004.12 0.04 +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.69 0.04 9412 4 0.13 -1 -1 33048 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25564 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 414 0.13 2.2252 -166.078 -2.2252 18 543 24 1.07788e+06 1.02399e+06 98201.7 2004.12 0.44 452 22 829 1925 144634 31657 2.69784 -193.844 -2.69784 0 0 111547. 2276.47 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt index 8cf331b7341..8e6838e0dae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_pad_file/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_40nm.xml stereovision3.v common 1.04 0.04 8832 4 0.13 -1 -1 33000 -1 -1 19 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 21948 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 449 0.11 2.21945 -168.153 -2.21945 20 707 20 1.34735e+06 1.02399e+06 54591.7 1114.12 0.09 543 15 507 1173 62601 20949 2.36754 -182.136 -2.36754 0 0 71469.7 1458.57 0.04 +k6_N10_40nm.xml stereovision3.v common 1.78 0.04 8840 4 0.15 -1 -1 33152 -1 -1 19 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 21668 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 449 0.18 2.21945 -168.153 -2.21945 20 700 27 1.34735e+06 1.02399e+06 54591.7 1114.12 0.22 592 27 884 2154 107177 33979 2.48822 -190.515 -2.48822 0 0 71469.7 1458.57 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index fea01e181d6..ef5f67f9390 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.13 0.03 9288 4 0.15 -1 -1 32996 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25796 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 478 0.10 2.23761 -174.252 -2.23761 20 719 19 1.07788e+06 1.02399e+06 49980.0 1020.00 0.20 614 18 539 1332 68243 22358 2.67002 -194.193 -2.67002 0 0 65453.8 1335.79 0.04 +k6_N10_mem32K_40nm.xml stereovision3.v common 2.32 0.04 9360 4 0.15 -1 -1 33176 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25668 11 30 262 292 2 104 60 7 7 49 clb auto 0.13 478 0.17 2.23761 -174.252 -2.23761 22 729 34 1.07788e+06 1.02399e+06 54623.3 1114.76 0.57 706 32 955 2278 127150 37450 3.18721 -193.511 -3.18721 0 0 69322.2 1414.74 0.08 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 002da357c43..4635f896009 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -shorted_flyover_wires.xml raygentop.v common 13.95 0.29 29620 3 1.01 -1 -1 40424 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 62756 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.22 11388 2.11 4.27581 -2648.79 -4.27581 64 28724 29 1.65001e+07 9.20413e+06 1.11360e+06 3084.77 5.16 23851 15 6088 13507 4078200 1049123 5.27078 -3186.3 -5.27078 0 0 1.39747e+06 3871.11 0.84 -buffered_flyover_wires.xml raygentop.v common 16.04 0.26 29596 3 0.99 -1 -1 40432 -1 -1 112 214 0 8 v8.0.0-rc1-1092-gb22604c1a success 63300 214 305 3028 2934 1 1505 639 19 19 361 io clb auto 2.08 10724 2.11 4.42883 -2547.95 -4.42883 70 27239 49 1.65001e+07 9.20413e+06 1.25135e+06 3466.35 7.35 21887 21 5718 12377 4320243 1123061 4.86613 -3081.64 -4.86613 0 0 1.57792e+06 4370.98 0.97 +shorted_flyover_wires.xml raygentop.v common 30.04 0.29 29556 3 1.51 -1 -1 40428 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 68244 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.25 11108 3.58 4.79392 -2540.18 -4.79392 66 27597 36 1.65001e+07 8.93466e+06 1.15238e+06 3192.19 16.05 23046 15 6018 13533 4245665 1060813 5.29045 -2968.52 -5.29045 0 0 1.43513e+06 3975.42 1.54 +buffered_flyover_wires.xml raygentop.v common 25.09 0.30 29760 3 1.50 -1 -1 40384 -1 -1 107 214 0 8 v8.0.0-rc1-1194-g64d9b2790 success 63188 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 3.16 10687 3.41 4.50659 -2437.12 -4.50659 70 26328 36 1.65001e+07 8.93466e+06 1.25135e+06 3466.35 11.46 20953 17 5222 11702 4411046 1119985 5.08067 -2980.08 -5.08067 0 0 1.57792e+06 4370.98 1.65 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index 65377a5c306..20d8adc93f1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -hard_fpu_arch_timing.xml mm3.v common 1.82 0.01 6520 1 0.02 -1 -1 30472 -1 -1 0 193 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 33644 193 32 545 422 1 289 227 21 21 441 io auto 0.78 3143 0.29 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.37 +hard_fpu_arch_timing.xml mm3.v common 3.04 0.02 6688 1 0.02 -1 -1 30484 -1 -1 0 193 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 33224 193 32 545 422 1 289 227 21 21 441 io auto 1.30 3143 0.53 2.985 -793.636 -2.985 4237 431 431 2130665 802708 809148 68766.3 979092. 2220.16 15 2.985 -804.546 -2.985 -21.8252 -0.0851 0.69 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 184eb3554ca..a4fbccd25c8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 1.36 0.03 8936 3 0.18 -1 -1 36228 -1 -1 67 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30848 99 130 363 493 1 249 297 13 13 169 clb auto 0.38 558 0.18 36 1328 8 0 0 481804. 2850.91 0.15 +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.47 0.04 8992 3 0.27 -1 -1 36292 -1 -1 67 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 30520 99 130 363 493 1 249 297 13 13 169 clb auto 0.74 558 0.36 36 1328 8 0 0 481804. 2850.91 0.24 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 4c2acbdc699..cfab22fbd74 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.02 0.03 9304 4 0.11 -1 -1 33040 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25512 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.08 2.22026 -169.026 -2.22026 20 642 24 1.07788e+06 1.02399e+06 49980.0 1020.00 0.09 540 19 579 1367 67339 22919 2.42646 -182.639 -2.42646 0 0 65453.8 1335.79 0.03 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.55 0.04 9476 4 0.14 -1 -1 33008 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25868 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.16 2.22026 -169.026 -2.22026 20 618 26 1.07788e+06 1.02399e+06 49980.0 1020.00 0.20 543 22 886 2148 101901 32828 2.43384 -187.753 -2.43384 0 0 65453.8 1335.79 0.06 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index 05380269819..4b348ee8b63 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml const_true.blif common 0.23 -1 -1 0 0.01 -1 -1 29592 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19016 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.20 -1 -1 0 0.00 -1 -1 29600 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19236 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.18 -1 -1 0 0.00 -1 -1 29712 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19160 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.23 -1 -1 0 0.00 -1 -1 29692 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19028 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and.blif common 0.22 -1 -1 1 0.00 -1 -1 29724 -1 -1 1 2 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18952 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.708653 -0.708653 -0.708653 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.22 -1 -1 1 0.01 -1 -1 31460 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19292 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.27 -1 -1 1 0.03 -1 -1 31980 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19124 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and_latch.blif common 0.20 -1 -1 1 0.00 -1 -1 29772 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19388 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml false_path_mux.blif common 0.26 -1 -1 1 0.02 -1 -1 31604 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19204 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.708653 -0.708653 -0.708653 -1 4 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_2x2.blif common 0.25 -1 -1 1 0.02 -1 -1 31504 -1 -1 1 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19328 4 4 8 12 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.83461 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_3x3.blif common 0.25 -1 -1 1 0.02 -1 -1 32044 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19304 6 6 12 18 0 12 13 3 3 9 -1 auto 0.00 24 0.00 0.734653 -4.35592 -0.734653 -1 18 12 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_3x4.blif common 0.33 -1 -1 2 0.03 -1 -1 32640 -1 -1 3 7 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19676 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 1.09565 -6.57093 -1.09565 -1 43 15 215576 161682 99039.1 6189.95 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_4x4.blif common 0.32 -1 -1 4 0.03 -1 -1 32432 -1 -1 2 8 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19880 8 8 29 37 0 21 18 4 4 16 clb auto 0.01 54 0.01 1.79165 -10.3186 -1.79165 -1 59 17 215576 107788 99039.1 6189.95 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_5x5.blif common 0.33 -1 -1 4 0.04 -1 -1 32236 -1 -1 4 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 20056 10 10 47 57 0 39 24 4 4 16 clb auto 0.02 126 0.02 2.32358 -16.2013 -2.32358 -1 141 18 215576 215576 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_5x6.blif common 0.52 -1 -1 5 0.07 -1 -1 32692 -1 -1 5 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 20308 11 11 61 72 0 51 27 5 5 25 clb auto 0.03 176 0.03 2.93136 -19.368 -2.93136 -1 215 15 485046 269470 186194. 7447.77 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_1bit.blif common 0.29 -1 -1 1 0.03 -1 -1 30932 -1 -1 1 3 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19364 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.708653 -1.41731 -0.708653 -1 6 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_2bit.blif common 0.27 -1 -1 1 0.03 -1 -1 32292 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19312 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.12596 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_3bit.blif common 0.31 -1 -1 2 0.03 -1 -1 32112 -1 -1 1 7 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19400 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 1.04365 -3.83961 -1.04365 -1 19 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_4bit.blif common 0.26 -1 -1 2 0.02 -1 -1 32148 -1 -1 1 9 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19348 9 5 15 20 0 14 15 3 3 9 -1 auto 0.01 28 0.00 1.04365 -4.54826 -1.04365 -1 22 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml rca_5bit.blif common 0.29 -1 -1 3 0.02 -1 -1 31900 -1 -1 1 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19392 11 6 19 25 0 17 18 3 3 9 -1 auto 0.01 34 0.00 1.37865 -6.93192 -1.37865 -1 27 4 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_true.blif common 0.41 -1 -1 0 0.01 -1 -1 29724 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19124 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.59 -1 -1 0 0.01 -1 -1 29596 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18640 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.38 -1 -1 0 0.00 -1 -1 29720 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19040 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.34 -1 -1 0 0.00 -1 -1 29592 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18780 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and.blif common 0.23 -1 -1 1 0.00 -1 -1 29692 -1 -1 1 2 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19144 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.708653 -0.708653 -0.708653 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.34 -1 -1 1 0.02 -1 -1 31376 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19124 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.37 -1 -1 1 0.03 -1 -1 31888 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18808 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.708653 -0.708653 -0.708653 -1 7 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml and_latch.blif common 0.24 -1 -1 1 0.00 -1 -1 29708 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18996 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.544641 -0.918653 -0.544641 -1 5 1 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml false_path_mux.blif common 0.31 -1 -1 1 0.02 -1 -1 31544 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19180 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.708653 -0.708653 -0.708653 -1 4 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_2x2.blif common 0.33 -1 -1 1 0.03 -1 -1 31564 -1 -1 1 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18776 4 4 8 12 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.83461 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x3.blif common 0.32 -1 -1 1 0.03 -1 -1 31928 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18756 6 6 12 18 0 12 13 3 3 9 -1 auto 0.01 24 0.00 0.734653 -4.35592 -0.734653 -1 18 12 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_3x4.blif common 0.36 -1 -1 2 0.04 -1 -1 32456 -1 -1 3 7 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19572 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 1.09565 -6.57093 -1.09565 -1 43 15 215576 161682 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 0.38 -1 -1 4 0.05 -1 -1 32444 -1 -1 2 8 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19596 8 8 29 37 0 21 18 4 4 16 clb auto 0.02 54 0.02 1.79165 -10.3186 -1.79165 -1 59 17 215576 107788 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 0.47 -1 -1 4 0.06 -1 -1 32056 -1 -1 4 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19884 10 10 47 57 0 39 24 4 4 16 clb auto 0.03 126 0.03 2.32358 -16.2013 -2.32358 -1 141 18 215576 215576 99039.1 6189.95 0.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 0.61 -1 -1 5 0.08 -1 -1 32484 -1 -1 5 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 20232 11 11 61 72 0 51 27 5 5 25 clb auto 0.04 176 0.04 2.93136 -19.368 -2.93136 -1 215 15 485046 269470 186194. 7447.77 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.32 -1 -1 1 0.03 -1 -1 30776 -1 -1 1 3 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19060 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.708653 -1.41731 -0.708653 -1 6 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.36 -1 -1 1 0.03 -1 -1 32372 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19144 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.708653 -2.12596 -0.708653 -1 11 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.34 -1 -1 2 0.03 -1 -1 32092 -1 -1 1 7 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18996 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 1.04365 -3.83961 -1.04365 -1 19 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.36 -1 -1 2 0.02 -1 -1 32136 -1 -1 1 9 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19176 9 5 15 20 0 14 15 3 3 9 -1 auto 0.01 28 0.00 1.04365 -4.54826 -1.04365 -1 22 11 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.33 -1 -1 3 0.03 -1 -1 31852 -1 -1 1 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18836 11 6 19 25 0 17 18 3 3 9 -1 auto 0.01 34 0.00 1.37865 -6.93192 -1.37865 -1 27 4 53894 53894 38783.3 4309.26 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index ddd64c08c03..74e4825ed33 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml const_true.blif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18828 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19132 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18816 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19212 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19128 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19096 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_true.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18860 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18628 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 nan 0 0 -1 0 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18852 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19120 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.736421 -0.736421 -0.736421 -1 9 13 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19072 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18496 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.736421 -0.736421 -0.736421 -1 7 1 53894 53894 20487.3 2276.37 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index d304b6b230c..7142409fdae 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -x_gaussian_y_uniform.xml stereovision3.v common 1.11 0.04 9284 4 0.12 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25832 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 367 0.08 1.91988 -135.359 -1.91988 12 297 4 1.07788e+06 700622 -1 -1 0.12 294 2 153 228 9385 3448 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_uniform_y_gaussian.xml stereovision3.v common 1.15 0.04 9284 4 0.11 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25808 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 344 0.07 1.91988 -135.359 -1.91988 10 310 15 1.07788e+06 700622 -1 -1 0.16 260 2 148 223 8418 3113 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_gaussian_y_gaussian.xml stereovision3.v common 1.13 0.04 9296 4 0.10 -1 -1 33064 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26008 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 349 0.09 1.91988 -135.359 -1.91988 12 289 6 1.07788e+06 700622 -1 -1 0.15 276 3 174 263 10238 3816 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_delta_y_uniform.xml stereovision3.v common 1.05 0.03 9264 4 0.13 -1 -1 33028 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26112 11 30 262 292 2 110 54 7 7 49 clb auto 0.09 370 0.07 1.91988 -135.359 -1.91988 48 290 2 1.07788e+06 700622 -1 -1 0.11 288 2 152 226 9074 3374 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_delta_y_delta.xml stereovision3.v common 1.09 0.04 9200 4 0.15 -1 -1 33012 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25788 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 365 0.08 1.91988 -135.359 -1.91988 48 290 3 1.07788e+06 700622 -1 -1 0.12 285 2 160 237 10171 3912 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 -x_uniform_y_delta.xml stereovision3.v common 1.07 0.04 9272 4 0.14 -1 -1 33160 -1 -1 13 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 26220 11 30 262 292 2 110 54 7 7 49 clb auto 0.08 365 0.07 1.91988 -135.359 -1.91988 38 281 3 1.07788e+06 700622 -1 -1 0.13 282 2 161 237 9088 3379 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 +x_gaussian_y_uniform.xml stereovision3.v common 1.55 0.07 9364 4 0.15 -1 -1 33000 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25968 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 367 0.12 1.91988 -135.359 -1.91988 12 297 4 1.07788e+06 700622 -1 -1 0.16 294 2 153 228 9385 3448 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_uniform_y_gaussian.xml stereovision3.v common 1.68 0.05 9548 4 0.14 -1 -1 33140 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25988 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 344 0.11 1.91988 -135.359 -1.91988 10 310 15 1.07788e+06 700622 -1 -1 0.27 260 2 148 223 8418 3113 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_gaussian_y_gaussian.xml stereovision3.v common 1.53 0.04 9372 4 0.15 -1 -1 33040 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26148 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 349 0.11 1.91988 -135.359 -1.91988 12 289 6 1.07788e+06 700622 -1 -1 0.25 276 3 174 263 10238 3816 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_delta_y_uniform.xml stereovision3.v common 1.53 0.05 9324 4 0.15 -1 -1 32996 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25704 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 370 0.13 1.91988 -135.359 -1.91988 48 290 2 1.07788e+06 700622 -1 -1 0.19 288 2 152 226 9074 3374 1.91988 -135.359 -1.91988 0 0 -1 -1 0.02 +x_delta_y_delta.xml stereovision3.v common 1.52 0.05 9332 4 0.16 -1 -1 32980 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26332 11 30 262 292 2 110 54 7 7 49 clb auto 0.13 365 0.14 1.91988 -135.359 -1.91988 48 290 3 1.07788e+06 700622 -1 -1 0.21 285 2 160 237 10171 3912 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 +x_uniform_y_delta.xml stereovision3.v common 1.42 0.04 9484 4 0.14 -1 -1 33052 -1 -1 13 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26116 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.12 1.91988 -135.359 -1.91988 38 281 3 1.07788e+06 700622 -1 -1 0.16 282 2 161 237 9088 3379 1.91988 -135.359 -1.91988 0 0 -1 -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 4ea8edf62a9..aa93381d5b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.14 0.03 9272 4 0.10 -1 -1 33200 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25580 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.10 1.93141 -141.327 -1.93141 10 278 24 1.07788e+06 1.02399e+06 -1 -1 0.14 269 19 473 930 51635 19952 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 -nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.03 0.04 9284 4 0.14 -1 -1 33136 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25384 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 397 0.06 1.93141 -141.327 -1.93141 14 277 19 1.07788e+06 1.02399e+06 -1 -1 0.09 268 25 443 969 53893 20310 1.93141 -141.327 -1.93141 0 0 -1 -1 0.03 -nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.12 0.05 9304 4 0.13 -1 -1 33004 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25308 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 426 0.06 1.93141 -141.327 -1.93141 14 302 17 1.07788e+06 1.02399e+06 -1 -1 0.08 301 17 408 911 50388 19833 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.65 0.06 9332 4 0.15 -1 -1 32980 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25460 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.11 1.93141 -141.327 -1.93141 10 280 19 1.07788e+06 1.02399e+06 -1 -1 0.17 270 21 623 1237 68382 26000 1.93141 -141.327 -1.93141 0 0 -1 -1 0.05 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.66 0.04 9332 4 0.15 -1 -1 33028 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25276 11 30 262 292 2 104 60 7 7 49 clb auto 0.11 397 0.12 1.93141 -141.327 -1.93141 14 275 26 1.07788e+06 1.02399e+06 -1 -1 0.18 268 31 572 1220 67739 25259 1.93141 -141.327 -1.93141 0 0 -1 -1 0.07 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.47 0.05 9320 4 0.14 -1 -1 33084 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25376 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 426 0.10 1.93141 -141.327 -1.93141 14 307 16 1.07788e+06 1.02399e+06 -1 -1 0.14 304 17 558 1204 67109 26114 1.93141 -141.327 -1.93141 0 0 -1 -1 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index 03592ae360c..9ad3391d09b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml stereovision3.v common 1.12 0.02 8736 4 0.13 -1 -1 33008 -1 -1 13 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22172 11 30 262 292 2 110 54 6 6 36 clb auto 0.11 381 0.05 2.26562 -157.07 -2.26562 34 760 33 862304 700622 62337.4 1731.59 0.19 540 11 343 559 21904 8621 2.5114 -178.2 -2.5114 0 0 76364.4 2121.23 0.02 +k6_frac_N10_40nm.xml stereovision3.v common 1.81 0.04 8876 4 0.14 -1 -1 33064 -1 -1 13 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22068 11 30 262 292 2 110 54 6 6 36 clb auto 0.12 381 0.06 2.26562 -157.07 -2.26562 34 764 40 862304 700622 62337.4 1731.59 0.29 540 11 343 559 21904 8621 2.5114 -178.2 -2.5114 0 0 76364.4 2121.23 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 2a0b67754bb..040866a427e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k4_N4_90nm.xml diffeq.blif common 5.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 47684 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.24 10133 1.50 6.77352 -1333.3 -6.77352 24 12220 20 983127 929624 797780. 1508.09 2.95 10949 16 6016 20588 2159891 493894 6.8984 -1445.89 -6.8984 0 0 1.04508e+06 1975.57 0.51 -k4_N4_90nm.xml ex5p.blif common 13.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 41056 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.23 11365 1.08 6.2011 -272.5 -6.2011 34 15486 43 804782 771343 910617. 2064.89 10.60 13214 20 7563 24669 4289697 1119035 6.2011 -285.89 -6.2011 0 0 1.15594e+06 2621.17 0.77 -k4_N4_90nm.xml s298.blif common 8.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 56600 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.27 12944 1.73 11.3412 -87.4002 -11.3412 26 16841 26 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 5.04 15969 19 7557 34543 4267407 813984 11.3825 -88.9401 -11.3825 0 0 1.43821e+06 2127.53 0.88 +k4_N4_90nm.xml diffeq.blif common 11.61 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 47468 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.38 10133 2.53 6.77352 -1333.3 -6.77352 24 12541 23 983127 929624 797780. 1508.09 6.49 11441 17 6774 22853 2446188 571128 6.96084 -1500.96 -6.96084 0 0 1.04508e+06 1975.57 0.89 +k4_N4_90nm.xml ex5p.blif common 23.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 44112 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.27 11365 1.81 6.2011 -272.5 -6.2011 36 14690 30 804782 771343 957936. 2172.19 18.82 13031 20 7558 24835 4031744 1002168 6.5642 -288.81 -6.5642 0 0 1.20592e+06 2734.52 1.36 +k4_N4_90nm.xml s298.blif common 17.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 55720 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.41 12944 2.92 11.3412 -87.4002 -11.3412 26 18082 37 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 11.23 16266 19 8684 41436 5277893 987865 11.5285 -89.8977 -11.5285 0 0 1.43821e+06 2127.53 1.70 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index a2b03c74342..9032f461e98 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.20 0.04 9588 5 0.11 -1 -1 33396 -1 -1 15 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 29120 11 30 313 321 2 114 56 7 7 49 clb auto 0.31 384 0.06 4.29791 0 0 587 167 333 10080 3225 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.564 -1.707 0.06 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.44 0.04 9500 5 0.14 -1 -1 33300 -1 -1 15 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 29076 11 30 313 321 2 114 56 7 7 49 clb auto 0.35 384 0.11 4.29791 0 0 587 167 333 10080 3225 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.564 -1.707 0.09 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt index 52dbd9c3a7c..5c2edaa907f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_multiclock/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params crit_path_delay_mcw clk_to_clk_cpd clk_to_clk2_cpd clk_to_input_cpd clk_to_output_cpd clk2_to_clk2_cpd clk2_to_clk_cpd clk2_to_input_cpd clk2_to_output_cpd input_to_input_cpd input_to_clk_cpd input_to_clk2_cpd input_to_output_cpd output_to_output_cpd output_to_clk_cpd output_to_clk2_cpd output_to_input_cpd clk_to_clk_setup_slack clk_to_clk2_setup_slack clk_to_input_setup_slack clk_to_output_setup_slack clk2_to_clk2_setup_slack clk2_to_clk_setup_slack clk2_to_input_setup_slack clk2_to_output_setup_slack input_to_input_setup_slack input_to_clk_setup_slack input_to_clk2_setup_slack input_to_output_setup_slack output_to_output_setup_slack output_to_clk_setup_slack output_to_clk2_setup_slack output_to_input_setup_slack clk_to_clk_hold_slack clk_to_clk2_hold_slack clk_to_input_hold_slack clk_to_output_hold_slack clk2_to_clk2_hold_slack clk2_to_clk_hold_slack clk2_to_input_hold_slack clk2_to_output_hold_slack input_to_input_hold_slack input_to_clk_hold_slack input_to_clk2_hold_slack input_to_output_hold_slack output_to_output_hold_slack output_to_clk_hold_slack output_to_clk2_hold_slack output_to_input_hold_slack -k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.46003 0.595 0.782256 -1 -1 0.57 0.757256 -1 1.46003 -1 1.07141 -1 2.17449 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.66026 -1 -1 0.268 3.18526 -1 1.30866 -1 3.30941 -1 -1.19188 -1 -1 -1 -1 +k6_frac_N10_mem32K_40nm.xml multiclock.blif common 1.31564 0.595 0.841581 -1 -1 0.57 0.814813 -1 1.31564 -1 1.07141 -1 1.7816 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.243 1.71958 -1 -1 0.268 3.24281 -1 1.16427 -1 3.30941 -1 -1.46477 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index 87cdc7fbc8b..6440841a9dc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.19 0.03 8956 3 0.20 -1 -1 36196 -1 -1 64 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30468 99 130 363 493 1 251 294 12 12 144 clb auto 0.10 631 0.18 40 1719 15 5.66058e+06 3.99722e+06 360333. 2502.31 0.16 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.97 0.04 9212 3 0.27 -1 -1 36240 -1 -1 64 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29748 99 130 363 493 1 251 294 12 12 144 clb auto 0.17 631 0.39 40 1719 15 5.66058e+06 3.99722e+06 360333. 2502.31 0.31 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index db2e8480e78..3f4919acaf4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.78 0.04 9304 4 0.10 -1 -1 33076 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 24028 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common 0.93 0.07 9336 4 0.14 -1 -1 33044 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24268 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 539a74acf5d..707f2c9ba36 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.82 0.05 9344 4 0.13 -1 -1 33012 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25056 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 404 0.09 2.22026 -169.026 -2.22026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.06 0.04 9472 4 0.15 -1 -1 33032 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24400 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 404 0.14 2.22026 -169.026 -2.22026 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index cc2ed9cb61b..df9b581009d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 19.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 765552 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.36 333 0.78 6.34392 -68.6483 -6.34392 18 769 24 0 0 66239.6 946.281 0.29 683 17 322 1139 141511 78590 7.01253 -76.014 -7.01253 0 0 84868.6 1212.41 0.04 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 19.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 765500 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.36 338 0.78 6.37916 -68.7252 -6.37916 18 722 18 0 0 66239.6 946.281 0.54 641 16 284 987 122407 67992 6.83552 -76.2255 -6.83552 0 0 84868.6 1212.41 0.04 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 31.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 765288 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.59 333 1.42 6.34392 -68.6483 -6.34392 16 953 45 0 0 60092.3 858.461 1.73 730 17 380 1479 176321 92346 7.14809 -77.4881 -7.14809 0 0 74567.7 1065.25 0.07 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 31.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 765580 10 10 168 178 1 62 30 10 7 70 io LAB auto 0.52 338 1.43 6.37916 -68.7252 -6.37916 16 890 49 0 0 60092.3 858.461 1.60 722 17 358 1194 144422 78787 6.91544 -77 -6.91544 0 0 74567.7 1065.25 0.07 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index 657f785364b..ce1694b5e1e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.74 0.03 8988 3 0.24 -1 -1 36284 -1 52468 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 30424 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 654 0.27 2.16091 -202.472 -2.16091 50 1447 13 5.66058e+06 4.05111e+06 406292. 2821.48 0.24 1301 8 594 746 62382 23285 2.63418 -229.877 -2.63418 0 0 539112. 3743.83 0.02 0.008733 0.2181 0.07312 0.7088 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 7.91 0.02 8588 15 0.29 -1 -1 34384 -1 55128 36 162 0 5 v8.0.0-rc1-1092-gb22604c1a success 44428 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.24 5302 0.78 19.6083 -1810.12 -19.6083 48 13097 37 1.21132e+07 3.92018e+06 756778. 2956.16 4.28 10038 17 3116 6081 1638625 418610 22.4888 -2094.22 -22.4888 0 0 968034. 3781.38 0.37 0.007854 0.3502 0.01663 0.6332 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.91 0.04 9028 3 0.28 -1 -1 36172 -1 52332 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29764 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 654 0.51 2.16091 -202.472 -2.16091 50 1447 13 5.66058e+06 4.05111e+06 406292. 2821.48 0.50 1301 8 594 746 62382 23285 2.63418 -229.877 -2.63418 0 0 539112. 3743.83 0.10 0.008811 0.2233 0.07246 0.7042 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 12.66 0.04 8648 15 0.39 -1 -1 34380 -1 55136 36 162 0 5 v8.0.0-rc1-1194-g64d9b2790 success 44228 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.38 5302 1.33 19.6083 -1810.12 -19.6083 48 13061 34 1.21132e+07 3.92018e+06 756778. 2956.16 6.74 10038 17 3116 6081 1638625 418610 22.4888 -2094.22 -22.4888 0 0 968034. 3781.38 0.56 0.007854 0.3502 0.01663 0.6332 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index b6530c4a927..bf1fcf5440e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.07 0.04 9284 4 0.15 -1 -1 33024 -1 -1 19 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 25936 11 30 262 292 2 104 60 7 7 49 clb auto 0.05 392 0.06 2.2162 -164.467 -2.2162 418 556 1363 148905 22193 1.07788e+06 1.02399e+06 207176. 4228.08 40 2.33587 -171.112 -2.33587 0 0 0.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.18 0.03 9592 5 0.14 -1 -1 33252 -1 -1 14 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 27756 11 30 313 321 2 117 55 7 7 49 clb auto 0.21 380 0.07 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.02 +k6_N10_mem32K_40nm.xml stereovision3.v common 1.40 0.05 9472 4 0.15 -1 -1 33020 -1 -1 19 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 25496 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 392 0.11 2.2162 -164.467 -2.2162 433 752 1884 183020 26826 1.07788e+06 1.02399e+06 207176. 4228.08 24 2.24005 -174.527 -2.24005 0 0 0.07 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.75 0.05 9532 5 0.13 -1 -1 33276 -1 -1 14 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 28064 11 30 313 321 2 117 55 7 7 49 clb auto 0.36 380 0.14 2.27833 -152.764 -2.27833 543 267 467 22853 7495 1.07788e+06 754516 219490. 4479.39 8 2.3886 -169.927 -2.3886 0 0 0.04 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index ed32602935a..ae53077a65f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 16.76 0.18 29384 4 1.49 -1 -1 39764 -1 -1 167 193 5 0 v8.0.0-rc1-1092-gb22604c1a success 70844 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.27 10711 2.14 4.0362 -2478.27 -4.0362 80 21050 37 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 9.38 19612 17 5228 14998 1697996 377704 4.77524 -2855.18 -4.77524 -7.14113 -0.293253 2.64606e+06 6615.15 0.46 +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 19.82 0.29 29640 4 1.60 -1 -1 39856 -1 -1 167 193 5 0 v8.0.0-rc1-1194-g64d9b2790 success 71364 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.30 10711 2.36 4.0362 -2478.27 -4.0362 76 23027 51 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 11.51 20051 17 5536 15485 1831924 411676 4.70984 -2868.45 -4.70984 -7.09172 -0.292146 2.51807e+06 6295.18 0.55 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 80e16928c1b..fd9f173e71d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1092-gb22604c1a success 37728 8 63 748 811 0 474 151 13 13 169 clb auto 0.25 4714 0.43 3.70871 -159.069 -3.70871 6562 3107 11690 976222 174155 6.63067e+06 4.31152e+06 558096. 3302.35 24 4.15429 -179.259 -4.15429 0 0 0.24 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.52 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1092-gb22604c1a success 37616 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4726 0.61 3.89144 -158.648 -3.89144 6642 3324 12982 1030781 185339 6.63067e+06 4.31152e+06 558096. 3302.35 22 4.59291 -186.559 -4.59291 0 0 0.29 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 2.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1194-g64d9b2790 success 37700 8 63 748 811 0 474 151 13 13 169 clb auto 0.44 4714 0.79 3.70871 -159.069 -3.70871 6703 4263 15313 1252438 219655 6.63067e+06 4.31152e+06 558096. 3302.35 24 4.15304 -182.999 -4.15304 0 0 0.48 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 2.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 v8.0.0-rc1-1194-g64d9b2790 success 37376 8 63 748 811 0 474 151 13 13 169 clb auto 0.43 4726 0.96 3.89144 -158.648 -3.89144 6985 4100 15083 1207360 214092 6.63067e+06 4.31152e+06 558096. 3302.35 26 4.16831 -189.499 -4.16831 0 0 0.49 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index 2e34bd63c2b..bac71dd39b7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -slicem.xml carry_chain.blif common 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 19472 1 1 69 49 1 47 8 5 5 25 BLK_IG-SLICEM auto 0.15 102 0.01 0.764286 -10.588 -0.764286 25 401 35 133321 88880.4 -1 -1 0.34 409 22 194 196 56704 26791 3.01746 -35.9539 -3.01746 0 0 -1 -1 0.02 +slicem.xml carry_chain.blif common 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 19176 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.15 65 0.02 0.55434 -5.54475 -0.55434 25 164 11 59253.6 59253.6 -1 -1 0.13 197 19 159 159 29188 17227 1.32558 -14.0361 -1.32558 0 0 -1 -1 0.01 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index d3cbcf7a149..efe434968ca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -arch.xml ndff.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 18404 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.198362 -1.99999 -0.198362 4 26 13 59253.6 44440.2 -1 -1 0.01 26 2 12 15 621 269 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 +arch.xml ndff.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 18452 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.198362 -1.99999 -0.198362 4 26 13 59253.6 44440.2 -1 -1 0.02 26 2 12 15 621 269 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index 25040fd3f74..7fe2eb3ff2f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 0.96 0.03 9444 5 0.12 -1 -1 33316 -1 -1 15 11 0 0 v8.0.0-rc1-1092-gb22604c1a success 27692 11 30 313 321 2 114 56 7 7 49 clb auto 0.22 384 0.06 4.29791 0 0 537 167 331 10396 3294 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.809 -1.707 0.01 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.38 0.04 9548 5 0.13 -1 -1 33284 -1 -1 15 11 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27844 11 30 313 321 2 114 56 7 7 49 clb auto 0.34 384 0.13 4.29791 0 0 537 167 331 10396 3294 1.07788e+06 808410 219490. 4479.39 5 4.55967 0 0 -164.809 -1.707 0.02 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index b365cb947f3..64869255b58 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23308 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.738757 -2.61951 -0.738757 8 22 7 323364 161682 9037.03 361.481 0.02 17 7 20 20 554 322 0.756339 -2.63886 -0.756339 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23504 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 27 0.01 0.571 0 0 8 36 4 323364 161682 9037.03 361.481 0.02 45 3 12 12 990 624 0.571 0 0 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23260 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.02 0.570641 -1.88754 -0.570641 6 13 10 323364 161682 7009.75 280.390 0.01 19 1 8 8 231 149 0.592131 -2.24748 -0.592131 0 0 9037.03 361.481 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23468 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 1.57064 -4.87629 -1.57064 8 35 26 323364 161682 9037.03 361.481 0.02 26 7 24 24 700 407 1.58926 -5.4843 -1.58926 0 0 10596.6 423.864 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23420 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 1.37401 -2.68253 -1.37401 6 26 13 323364 161682 7009.75 280.390 0.01 30 2 13 13 598 378 1.3955 -2.70755 -1.3955 0 0 9037.03 361.481 0.00 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 23408 5 3 12 15 2 10 11 5 5 25 clb auto 0.00 18 0.01 0.0706414 0 0 6 19 1 323364 161682 7009.75 280.390 0.01 21 1 8 8 286 184 0.0715255 0 0 0 0 9037.03 361.481 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23348 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.738757 -2.61951 -0.738757 8 23 8 107788 107788 4794.78 299.674 0.01 32 4 14 14 735 589 0.739641 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23268 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 19 0.01 0.571 0 0 8 30 6 107788 107788 4794.78 299.674 0.01 23 4 13 13 349 215 0.571 0 0 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23240 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.569757 -1.88754 -0.569757 8 26 4 107788 107788 4794.78 299.674 0.01 18 8 24 24 632 426 0.681776 -2.31791 -0.681776 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23096 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 1.56976 -4.87541 -1.56976 8 25 11 107788 107788 4794.78 299.674 0.01 17 4 11 11 300 189 1.57153 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23392 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 1.37313 -2.68253 -1.37313 6 24 4 107788 107788 3417.33 213.583 0.01 18 2 10 10 290 190 1.39454 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22904 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.0697572 0 0 8 22 3 107788 107788 4794.78 299.674 0.01 32 5 15 15 764 607 0.0724097 0 0 0 0 5401.54 337.596 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index e31b123c31a..10bc179e6ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 0.83 0.01 5868 1 0.00 -1 -1 29844 -1 -1 3 9 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24252 9 8 74 69 1 33 20 5 5 25 clb auto 0.45 71 0.02 2.25879 -23.7509 -2.25879 26 164 14 151211 75605.7 37105.9 1484.24 0.03 141 10 97 117 3917 2091 2.55561 -33.5675 -2.55561 0 0 45067.1 1802.68 0.00 13 16 19 7 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 3.18 0.00 5932 1 0.01 -1 -1 29864 -1 -1 2 11 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24476 11 10 107 96 1 44 23 4 4 16 clb auto 2.81 96 0.02 2.96669 -32.6902 -2.96669 34 188 14 50403.8 50403.8 21558.4 1347.40 0.05 137 14 148 202 5606 3428 3.73364 -44.2193 -3.73364 0 0 26343.3 1646.46 0.01 14 25 29 8 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 2.43 0.00 6032 1 0.01 -1 -1 30192 -1 -1 2 13 0 -1 v8.0.0-rc1-1092-gb22604c1a success 24616 13 12 148 128 1 59 27 4 4 16 clb auto 1.97 132 0.02 3.01831 -41.2936 -3.01831 36 280 46 50403.8 50403.8 22423.4 1401.47 0.06 189 14 189 223 6865 4126 3.49231 -57.8176 -3.49231 0 0 28178.5 1761.16 0.01 19 36 42 9 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 1.91 0.00 6148 1 0.01 -1 -1 29872 -1 -1 5 15 0 -1 v8.0.0-rc1-1092-gb22604c1a success 25536 15 14 195 164 1 87 34 5 5 25 clb auto 1.24 270 0.05 3.1163 -51.6217 -3.1163 44 573 24 151211 126010 54748.7 2189.95 0.17 404 16 322 527 18672 8548 3.82203 -71.71 -3.82203 0 0 71025.7 2841.03 0.02 33 49 57 11 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 2.22 0.00 6204 1 0.01 -1 -1 30020 -1 -1 7 17 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26060 17 16 250 205 1 114 40 6 6 36 clb auto 1.64 361 0.06 3.26818 -53.849 -3.26818 52 707 33 403230 176413 110337. 3064.92 0.12 578 17 549 859 33650 13481 4.24968 -85.1999 -4.24968 0 0 143382. 3982.83 0.02 52 64 75 13 0 0 -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 2.82 0.00 6152 1 0.01 -1 -1 30212 -1 -1 7 19 0 -1 v8.0.0-rc1-1092-gb22604c1a success 26408 19 18 307 248 1 141 44 6 6 36 clb auto 1.97 436 0.10 4.13322 -71.9714 -4.13322 60 926 18 403230 176413 127342. 3537.27 0.23 689 20 677 1075 39870 15591 5.49585 -110.351 -5.49585 0 0 157803. 4383.41 0.02 58 81 93 14 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.18 0.01 5956 1 0.01 -1 -1 29680 -1 -1 3 9 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23860 9 8 74 69 1 33 20 5 5 25 clb auto 0.62 71 0.04 2.25879 -23.7509 -2.25879 26 164 14 151211 75605.7 37105.9 1484.24 0.05 141 11 100 122 4102 2193 2.55561 -33.5675 -2.55561 0 0 45067.1 1802.68 0.01 13 16 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.68 0.01 6032 1 0.01 -1 -1 29860 -1 -1 2 11 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 23724 11 10 107 96 1 44 23 4 4 16 clb auto 4.08 96 0.04 2.96669 -32.6902 -2.96669 34 188 14 50403.8 50403.8 21558.4 1347.40 0.08 156 18 168 232 6556 3975 3.32273 -45.5748 -3.32273 0 0 26343.3 1646.46 0.01 14 25 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.64 0.01 6012 1 0.01 -1 -1 30336 -1 -1 2 13 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 24260 13 12 148 128 1 59 27 4 4 16 clb auto 2.98 132 0.05 3.01831 -41.2936 -3.01831 38 239 23 50403.8 50403.8 23356.0 1459.75 0.14 182 14 192 219 6796 4029 3.25531 -54.787 -3.25531 0 0 29887.0 1867.94 0.02 19 36 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.86 0.01 6184 1 0.01 -1 -1 29916 -1 -1 5 15 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 24724 15 14 195 164 1 87 34 5 5 25 clb auto 2.08 270 0.08 3.1163 -51.6217 -3.1163 44 537 26 151211 126010 54748.7 2189.95 0.18 404 16 322 527 18672 8548 3.82203 -71.71 -3.82203 0 0 71025.7 2841.03 0.02 33 49 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 3.48 0.01 6120 1 0.01 -1 -1 29956 -1 -1 7 17 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 25948 17 16 250 205 1 114 40 6 6 36 clb auto 2.56 361 0.11 3.26818 -53.849 -3.26818 52 742 23 403230 176413 110337. 3064.92 0.22 590 21 594 946 37002 14662 4.43 -86.7352 -4.43 0 0 143382. 3982.83 0.03 52 64 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.26 0.01 6412 1 0.02 -1 -1 30328 -1 -1 7 19 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 26428 19 18 307 248 1 141 44 6 6 36 clb auto 3.17 436 0.14 4.13322 -71.9714 -4.13322 60 1014 29 403230 176413 127342. 3537.27 0.32 692 21 740 1202 45108 17377 5.26938 -108.577 -5.26938 0 0 157803. 4383.41 0.04 58 81 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index a6acf55e9fb..08fe0f39203 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.07 0.04 8800 3 0.30 -1 -1 42064 -1 -1 14 99 1 0 v8.0.0-rc1-1400-ge1ff30c2f success 64320 99 74 307 381 1 199 188 8 8 64 io memory auto 0.07 648 0.38 1.95184 -194.143 -1.95184 42 1177 26 2.23746e+06 1.30252e+06 130676. 2041.82 0.52 1062 13 720 1013 147980 53129 2.28165 -213.94 -2.28165 0 0 165046. 2578.84 0.06 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 2.26 0.05 9016 3 0.29 -1 -1 36168 -1 -1 14 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 26796 99 74 307 381 1 199 188 8 8 64 io memory auto 0.08 647 0.30 1.9311 -196.847 -1.9311 34 1358 46 2.23746e+06 1.30252e+06 111309. 1739.21 0.67 1092 28 827 1194 140107 49979 2.25027 -229.924 -2.25027 0 0 136889. 2138.88 0.11 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 7d751a2b093..2e1804264a7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -EArch.xml styr.blif common_--target_ext_pin_util_1 0.57 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26940 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 375 0.05 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.11 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.78 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 27172 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.09 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.15 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33272 10 10 168 178 1 162 110 14 14 196 clb auto 0.39 1408 0.18 2.63178 -32.0244 -2.63178 22 2983 14 9.20055e+06 4.85046e+06 325918. 1662.85 0.22 2866 17 635 2380 148243 38092 3.68891 -45.9088 -3.68891 0 0 407540. 2079.28 0.04 -EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.79 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 27648 10 10 168 178 1 73 33 7 7 49 clb auto 0.14 357 0.06 2.19476 -24.8471 -2.19476 28 1161 45 1.07788e+06 700622 79600.7 1624.51 0.29 876 17 434 1600 76377 28777 3.12807 -34.6232 -3.12807 0 0 95067.4 1940.15 0.03 -EArch.xml styr.blif common_--target_ext_pin_util_0.0 1.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33424 10 10 168 178 1 163 121 14 14 196 clb auto 0.58 1381 0.20 2.72722 -32.4843 -2.72722 20 2827 12 9.20055e+06 5.44329e+06 295730. 1508.82 0.09 2752 15 536 2083 128119 32657 3.60179 -43.9525 -3.60179 0 0 387483. 1976.95 0.05 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26880 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.05 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.10 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26748 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.10 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.11 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.02 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 1.38 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 33392 10 10 168 178 1 162 110 14 14 196 clb auto 0.50 1408 0.21 2.63178 -32.0244 -2.63178 22 2983 14 9.20055e+06 4.85046e+06 325918. 1662.85 0.24 2866 17 635 2380 148243 38092 3.68891 -45.9088 -3.68891 0 0 407540. 2079.28 0.05 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1092-gb22604c1a success 26848 10 10 168 178 1 74 31 6 6 36 clb auto 0.12 375 0.06 2.26002 -25.3634 -2.26002 30 783 22 646728 592834 55714.4 1547.62 0.13 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.02 -EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23284 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.07 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23536 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23704 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1092-gb22604c1a exited with return code 1 23408 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1 0.93 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26888 10 10 168 178 1 74 31 6 6 36 clb auto 0.22 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.20 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.95 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27080 10 10 168 178 1 74 31 6 6 36 clb auto 0.21 375 0.11 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.21 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33320 10 10 168 178 1 162 110 14 14 196 clb auto 0.67 1408 0.38 2.63178 -32.0244 -2.63178 22 3011 17 9.20055e+06 4.85046e+06 325918. 1662.85 0.39 2821 14 736 2642 165648 42230 3.68891 -45.7774 -3.68891 0 0 407540. 2079.28 0.07 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 1.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27564 10 10 168 178 1 73 33 7 7 49 clb auto 0.20 357 0.09 2.19476 -24.8471 -2.19476 26 1076 29 1.07788e+06 700622 75813.7 1547.22 0.56 893 24 615 2230 111320 40005 2.71043 -34.388 -2.71043 0 0 91376.6 1864.83 0.07 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33408 10 10 168 178 1 163 121 14 14 196 clb auto 0.81 1381 0.41 2.72722 -32.4843 -2.72722 20 2801 19 9.20055e+06 5.44329e+06 295730. 1508.82 0.18 2742 15 598 2202 137075 34724 3.60179 -43.907 -3.60179 0 0 387483. 1976.95 0.06 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.91 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27236 10 10 168 178 1 74 31 6 6 36 clb auto 0.19 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.22 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 27208 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.22 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 33072 10 10 168 178 1 162 110 14 14 196 clb auto 0.69 1408 0.39 2.63178 -32.0244 -2.63178 22 3011 17 9.20055e+06 4.85046e+06 325918. 1662.85 0.42 2821 14 736 2642 165648 42230 3.68891 -45.7774 -3.68891 0 0 407540. 2079.28 0.08 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 v8.0.0-rc1-1194-g64d9b2790 success 26956 10 10 168 178 1 74 31 6 6 36 clb auto 0.20 375 0.10 2.26002 -25.3634 -2.26002 30 832 31 646728 592834 55714.4 1547.62 0.20 728 16 442 1448 60987 25004 2.63902 -32.0258 -2.63902 0 0 68154.2 1893.17 0.04 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23764 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23680 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23584 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 v8.0.0-rc1-1194-g64d9b2790 exited with return code 1 23892 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index ca2c1ef5b3e..9a3389c2249 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 1.34 0.03 8980 3 0.20 -1 -1 36172 -1 -1 65 99 1 0 v8.0.0-rc1-1092-gb22604c1a success 29976 99 130 363 493 1 251 295 12 12 144 clb auto 0.08 655 0.27 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.27 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.03 +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.25 0.04 9196 3 0.25 -1 -1 36188 -1 -1 65 99 1 0 v8.0.0-rc1-1194-g64d9b2790 success 29304 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 655 0.50 1.83922 -200.183 -1.83922 46 1425 16 5.66058e+06 4.05111e+06 378970. 2631.74 0.46 1340 11 648 842 78620 27838 2.30893 -233.17 -2.30893 0 0 486261. 3376.82 0.05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 6280904abf3..79087b62319 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24860 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24700 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 5 0 0 v8.0.0-rc1-1092-gb22604c1a success 24996 5 3 12 15 2 10 11 5 5 25 clb auto 0.01 18 0.01 0.706884 -3.63242 -0.706884 20 22 2 323364 161682 21003.5 840.140 0.01 37 3 11 11 554 274 0.87598 -4.58293 -0.87598 0 0 27621.7 1104.87 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24868 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24876 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 v8.0.0-rc1-1194-g64d9b2790 success 24552 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.545 -3.13143 -0.545 20 23 1 107788 107788 10441.3 652.579 0.01 25 2 8 8 234 152 0.869227 -3.98629 -0.869227 0 0 13752.8 859.551 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index 8aa53db08b8..7d46687cffd 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 67.05 42 753 0 0 0 0 v8.0.0-rc1-1092-gb22604c1a success 1011288 13 29 26295 20086 1 12415 795 39 29 1131 LAB auto 9.57 80370 40.19 4.8494 -14201.6 -4.8494 83423 24866 32259 28860263 3251424 0 0 2.17765e+07 19254.2 13 4.97188 -15343.1 -4.97188 0 0 3.30 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 80.16 42 753 0 0 0 0 v8.0.0-rc1-1194-g64d9b2790 success 1011024 13 29 26295 20086 1 12415 795 39 29 1131 LAB auto 15.84 80370 38.02 4.8494 -14201.6 -4.8494 83215 26269 34662 30836512 3446780 0 0 2.17765e+07 19254.2 13 4.97188 -15454.7 -4.97188 0 0 3.51 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 2532b379d5b..835e38df2df 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 8.59 0.01 8828 6 0.09 -1 -1 34012 -1 -1 15 66 0 -1 v8.0.0-rc1-1092-gb22604c1a success 53224 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.14 4812 0.76 14.7278 -819.907 -14.7278 62 11943 18 6.4517e+06 1.13409e+06 1.72337e+06 5319.03 5.17 10760 17 3483 7402 3135131 764282 16.6282 -1030.56 -16.6282 0 0 2.10074e+06 6483.76 0.52 135 200 146 33 66 33 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 15.76 0.02 8916 6 0.12 -1 -1 34112 -1 -1 15 66 0 -1 v8.0.0-rc1-1194-g64d9b2790 success 46780 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.61 4812 1.39 14.7278 -819.907 -14.7278 60 12276 35 6.4517e+06 1.13409e+06 1.66893e+06 5151.03 9.76 10886 40 3329 7348 3578053 1134156 16.8599 -1041.74 -16.8599 0 0 2.06264e+06 6366.18 1.40 135 200 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index 9afc4c5ccd7..580d216346d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a success 23148 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.01 1.10382 -14.1235 -1.10382 62 98 144 4949 2328 323364 161682 20103.2 804.128 15 1.18331 -15.7108 -1.18331 0 0 0.00 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a success 22972 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.01 1.10382 -14.1235 -1.10382 62 98 144 4949 2328 323364 161682 20103.2 804.128 15 1.18331 -15.7108 -1.18331 0 0 0.01 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a exited with return code 2 23616 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 52 0.01 1.14517 -14.2319 -1.14517 -1 734 954 51286 35882 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.02 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1092-gb22604c1a exited with return code 2 23468 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 52 0.01 1.14517 -14.2319 -1.14517 138 734 954 51286 35882 323364 161682 9037.03 361.481 -1 1.57884 -20.2194 -1.57884 0 0 0.02 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 success 22676 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.04 1.10382 -14.1235 -1.10382 69 167 230 8395 3681 323364 161682 20103.2 804.128 21 1.18331 -15.9141 -1.18331 0 0 0.02 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 success 23216 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.02 1.10382 -14.1235 -1.10382 69 167 230 8395 3681 323364 161682 20103.2 804.128 21 1.18331 -15.9141 -1.18331 0 0 0.01 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 exited with return code 2 23648 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 52 0.02 1.14517 -14.2319 -1.14517 -1 761 989 53376 36845 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.04 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 v8.0.0-rc1-1194-g64d9b2790 exited with return code 2 23284 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 52 0.02 1.14517 -14.2319 -1.14517 139 761 989 53376 36845 323364 161682 9037.03 361.481 -1 1.66401 -20.8061 -1.66401 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 5af3c158894..60b71a0b84b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N4_90nm.xml stereovision3.v common 4.92 0.03 8728 6 0.15 -1 -1 33160 -1 -1 66 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 23608 11 30 336 366 2 186 107 11 11 121 clb auto 0.04 1075 0.11 3.34892 -239.501 -3.34892 995 849 2411 331915 45511 180575 147135 597941. 4941.66 13 3.34892 -248.18 -3.34892 -0.21991 -0.0734 0.05 -k6_frac_N10_40nm.xml stereovision3.v common 2.21 0.02 8852 4 0.14 -1 -1 33044 -1 -1 13 11 -1 -1 v8.0.0-rc1-1092-gb22604c1a success 22544 11 30 262 292 2 110 54 6 6 36 clb auto 0.08 366 0.07 2.26563 -155.916 -2.26563 467 182 317 10207 3363 862304 700622 161034. 4473.17 6 2.47845 -169.802 -2.47845 0 0 0.01 +k4_N4_90nm.xml stereovision3.v common 7.18 0.04 8836 6 0.17 -1 -1 33036 -1 -1 66 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 23748 11 30 336 366 2 186 107 11 11 121 clb auto 0.06 1075 0.19 3.34892 -239.501 -3.34892 1023 868 2391 322050 43514 180575 147135 597941. 4941.66 13 3.34892 -247.922 -3.34892 -0.21991 -0.0734 0.09 +k6_frac_N10_40nm.xml stereovision3.v common 3.08 0.03 8864 4 0.16 -1 -1 33036 -1 -1 13 11 -1 -1 v8.0.0-rc1-1194-g64d9b2790 success 22576 11 30 262 292 2 110 54 6 6 36 clb auto 0.13 366 0.14 2.26563 -155.916 -2.26563 467 183 320 10273 3381 862304 700622 161034. 4473.17 6 2.47845 -169.802 -2.47845 0 0 0.03 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt index 5f206f5e1fd..4f29fadb034 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt @@ -52,4 +52,6 @@ regression_tests/vtr_reg_strong/strong_global_nonuniform regression_tests/vtr_reg_strong/strong_sdc regression_tests/vtr_reg_strong/strong_timing_report_detail regression_tests/vtr_reg_strong/strong_route_reconverge +regression_tests/vtr_reg_strong/strong_clock_buf regression_tests/vtr_reg_strong/strong_equivalent_sites +regression_tests/vtr_reg_strong/strong_absorb_buffers From 4dce4900a875f21b3062822cb984385768550089 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Thu, 21 Nov 2019 11:33:26 -0800 Subject: [PATCH 106/107] Fix some compile warnings for now. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- vpr/src/place/timing_place_lookup.cpp | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/vpr/src/place/timing_place_lookup.cpp b/vpr/src/place/timing_place_lookup.cpp index 1745f6f6f51..c065d56e504 100644 --- a/vpr/src/place/timing_place_lookup.cpp +++ b/vpr/src/place/timing_place_lookup.cpp @@ -68,6 +68,7 @@ struct t_profile_info { static t_chan_width setup_chan_width(const t_router_opts& router_opts, t_chan_width_dist chan_width_dist); +#if 0 static float route_connection_delay( const RouterDelayProfiler& route_profiler, int source_x_loc, @@ -89,6 +90,7 @@ static void generic_compute_matrix( const t_router_opts& router_opts, bool measure_directconnect, const std::set& allowed_types); +#endif static void generic_compute_matrix_expand( const RouterDelayProfiler& route_profiler, @@ -294,6 +296,7 @@ static t_chan_width setup_chan_width(const t_router_opts& router_opts, return init_chan(width_fac, chan_width_dist); } +#if 0 static float route_connection_delay( const RouterDelayProfiler& route_profiler, int source_x, @@ -352,6 +355,7 @@ static float route_connection_delay( return (net_delay_value); } +#endif static void add_delay_to_matrix( vtr::Matrix>* matrix, @@ -368,7 +372,7 @@ static void add_delay_to_matrix( } static void generic_compute_matrix_expand( - const RouterDelayProfiler& route_profiler, + const RouterDelayProfiler& /*route_profiler*/, vtr::Matrix>& matrix, int source_x, int source_y, @@ -498,6 +502,7 @@ static void generic_compute_matrix_expand( } } +#if 0 static void generic_compute_matrix( const RouterDelayProfiler& route_profiler, vtr::Matrix>& matrix, @@ -532,26 +537,26 @@ static void generic_compute_matrix( if (matrix[delta_x][delta_y].empty()) { //Only set empty target if we don't already have a valid delta delay matrix[delta_x][delta_y].push_back(EMPTY_DELTA); -#ifdef VERBOSE +# ifdef VERBOSE VTR_LOG("Computed delay: %12s delta: %d,%d (src: %d,%d sink: %d,%d)\n", "EMPTY", delta_x, delta_y, source_x, source_y, sink_x, sink_y); -#endif +# endif } } else { //Valid start/end float delay = route_connection_delay(route_profiler, source_x, source_y, sink_x, sink_y, router_opts, measure_directconnect); -#ifdef VERBOSE +# ifdef VERBOSE VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n", delay, delta_x, delta_y, source_x, source_y, sink_x, sink_y); -#endif +# endif if (matrix[delta_x][delta_y].size() == 1 && matrix[delta_x][delta_y][0] == EMPTY_DELTA) { //Overwrite empty delta matrix[delta_x][delta_y][0] = delay; @@ -563,6 +568,7 @@ static void generic_compute_matrix( } } } +#endif static vtr::Matrix compute_delta_delays( const RouterDelayProfiler& route_profiler, From be9a50df39c47e50f03b1ec691dd49cb5aa230b5 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 13 Dec 2019 15:20:41 -0800 Subject: [PATCH 107/107] Octopus merge This is an Octopus Merge commit of the following branches: wip/add-issue-template wip/add_explicit_ports wip/avoid-criticality-issue wip/avoid_unordered_set wip/disable-check-route-option wip/faster_rr_graph_read wip/inline_main_loop wip/length_bounded wip/lookahead_sampling2 wip/place-constraints wip/refactor_heap2 wip/revert_clock_propigation wip/rr-graph-binary-read-write wip/symbiflow-badger wip/use_expansion_for_place_delay Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>